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Features • High performance, low power Atmel® AVR® 8-bit microcontroller • Advanced RISC architecture – 131 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 20 MIPS throughput at 20MHz – On-chip 2-cycle multiplier • High endurance non-volatile memory segments – 4/8/16 Kbytes of in-system self-programmable flash program memory – 256/512/512 bytes EEPROM – 512/1K/1Kbytes internal SRAM – Write/erase cyles: 10,000 flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C() – Optional boot code section with independent lock bits In-system programming by on-chip boot program True read-while-write operation – Programming lock for software security • QTouch® library support – Capacitive touch buttons, sliders and wheels – QTouch and QMatrix acquisition – Up to 64 sense channels • Peripheral features – Two 8-bit timer/counters with separate prescaler and compare mode – One 16-bit timer/counter with separate prescaler, compare mode, and capture mode – Real time counter with separate oscillator – Six PWM channels – 8-channel 10-bit ADC in TQFP and QFN/MLF package – 6-channel 10-bit ADC in PDIP Package – Programmable serial USART – Master/slave SPI serial interface – Byte-oriented 2-wire serial interface (Philips I2 C compatible) – Programmable watchdog timer with separate on-chip oscillator – On-chip analog comparator – Interrupt and wake-up on pin change • Special microcontroller features – DebugWIRE on-chip debug system – Power-on reset and programmable brown-out detection – Internal calibrated oscillator – External and internal interrupt sources – Five sleep modes: Idle, ADC noise reduction, power-save, power-down, and standby • I/O and packages – 23 programmable I/O lines – 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF • Operating voltage: – 1.8V - 5.5V for Atmel ATmega48V/88V/168V – 2.7V - 5.5V for Atmel ATmega48/88/168 • Temperature range: – -40°C to 85°C • Speed grade: – ATmega48V/88V/168V: 0 - 4MHz @ 1.8V - 5.5V, 0 - 10MHz @ 2.7V - 5.5V – ATmega48/88/168: 0 - 10MHz @ 2.7V - 5.5V, 0 - 20MHz @ 4.5V - 5.5V • Low power consumption – Active mode: 250µA at 1MHz, 1.8V 15µA at 32kHz, 1.8V (including oscillator) – Power-down mode: 0.1µA at 1.8V Note: 1. See “Data retention” on page 8 for details. 8-bit Atmel Microcontroller with 4/8/16K Bytes In-System Programmable Flash ATmega48/V ATmega88/V ATmega168/V Rev. 2545T–AVR–05/11 2 2545T–AVR–05/11 ATmega48/88/168 1. Pin configurations Figure 1-1. Pinout Atmel ATmega48/88/168. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) TQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (PCINT14/RESET) PC6 (PCINT16/RXD) PD0 (PCINT17/TXD) PD1 (PCINT18/INT0) PD2 (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 VCC GND (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND AREF AVCC PB5 (SCK/PCINT5) PB4 (MISO/PCINT4) PB3 (MOSI/OC2A/PCINT3) PB2 (SS/OC1B/PCINT2) PB1 (OC1A/PCINT1) PDIP 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 MLF Top View (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 GND VCC GND VCC (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) ADC7 GND AREF ADC6 AVCC PB5 (SCK/PCINT5) (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) NOTE: Bottom pad should be soldered to ground. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 28 MLF Top View (PCINT19/OC2B/INT1) PD3 (PCINT20/XCK/T0) PD4 VCC GND (PCINT6/XTAL1/TOSC1) PB6 (PCINT7/XTAL2/TOSC2) PB7 (PCINT21/OC0B/T1) PD5 (PCINT22/OC0A/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/OC2A/MOSI) PB3 (PCINT4/MISO) PB4 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND AREF AVCC PB5 (SCK/PCINT5) NOTE: Bottom pad should be soldered to ground. 3 2545T–AVR–05/11 ATmega48/88/168 1.1 Pin descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in “Alternate functions of port B” on page 78 and “System clock and clock options” on page 27. 1.1.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 29-3 on page 307. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated in “Alternate functions of port C” on page 81. 1.1.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up 4 2545T–AVR–05/11 ATmega48/88/168 resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in “Alternate functions of port D” on page 84. 1.1.7 AVCC AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC. 1.1.8 AREF AREF is the analog reference pin for the A/D Converter. 1.1.9 ADC7:6 (TQFP and QFN/MLF package only) In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 5 2545T–AVR–05/11 ATmega48/88/168 2. Overview The Atmel ATmega48/88/168 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48/88/168 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block diagram Figure 2-1. Block diagram. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting PORT D (8) PORT B (8) PORT C (7) USART 0 8bit T/C 2 8bit T/C 0 16bit T/C 1 A/D conv. Internal bandgap Analog comp. SPI TWI Flash SRAM EEPROM Watchdog oscillator Watchdog timer Oscillator circuits / clock generation Power supervision POR / BOD & RESET GND VCC PROGRAM LOGIC debugWIRE 2 GND AREF AVCC DATABUS PD[0..7] PB[0..7] PC[0..6] ADC[6..7] 6 RESET XTAL[1..2] CPU 6 2545T–AVR–05/11 ATmega48/88/168 architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATmega48/88/168 provides the following features: 4K/8K/16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512 bytes EEPROM, 512/1K/1K bytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. Atmel offers the QTouch Library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambigiuous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using the Atmel high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega48/88/168 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48/88/168 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison between Atmel ATmega48, Atmel ATmega88, and Atmel ATmega168 The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the three devices. Table 2-1. Memory size summary. Device Flash EEPROM RAM Interrupt vector size ATmega48 4Kbytes 256Bytes 512Bytes 1 instruction word/vector ATmega88 8Kbytes 512Bytes 1Kbytes 1 instruction word/vector ATmega168 16Kbytes 512Bytes 1Kbytes 2 instruction words/vector 7 2545T–AVR–05/11 ATmega48/88/168 ATmega88 and ATmega168 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. 8 2545T–AVR–05/11 ATmega48/88/168 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Data retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 6. Capacitive touch sensing The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. 9 2545T–AVR–05/11 ATmega48/88/168 7. AVR CPU core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.2 Architectural overview Figure 7-1. Block diagram of the AVR architecture. In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. Flash program memory Instruction register Instruction decoder Program counter Control lines 32 x 8 general purpose registrers ALU Status and control I/O lines EEPROM Data bus 8-bit Data SRAM Direct addressing Indirect addressing Interrupt unit SPI unit Watchdog timer Analog comparator I/O module 2 I/O module 1 I/O module n 10 2545T–AVR–05/11 ATmega48/88/168 The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-register, Y-register, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega48/88/168 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See “Instruction set summary” on page 347 for a detailed description. 11 2545T–AVR–05/11 ATmega48/88/168 7.4 Status register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global interrupt enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit copy storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half carry flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s complement overflow flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 12 2545T–AVR–05/11 ATmega48/88/168 • Bit 0 – C: Carry flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.5 General purpose register file The register file is optimized for the AVR enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the register file: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU general purpose working registers. Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E purpose R15 0x0F working R16 0x10 registers R17 0x11 … R26 0x1A X-register low byte R27 0x1B X-register high byte R28 0x1C Y-register low byte R29 0x1D Y-register high byte R30 0x1E Z-register low byte R31 0x1F Z-register high byte 13 2545T–AVR–05/11 ATmega48/88/168 7.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers. In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.6 Stack pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100, preferably RAMEND. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 15 XH XL 0 X-register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 07 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 70 7 0 R31 (0x1F) R30 (0x1E) 14 2545T–AVR–05/11 ATmega48/88/168 7.6.1 SPH and SPL – Stack pointer high and stack pointer low register 7.7 Instruction execution timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-4. The parallel instruction fetches and instruction executions. Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-5. Single cycle ALU operation. Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch T1 T2 T3 T4 CPU Total execution time Register operands fetch ALU operation execute Result write back T1 T2 T3 T4 clkCPU 15 2545T–AVR–05/11 ATmega48/88/168 7.8 Reset and interrupt handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory programming” on page 285 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 56. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 56 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 16 2545T–AVR–05/11 ATmega48/88/168 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. 7.8.1 Interrupt response time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Assembly code example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C code example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< xxx ... ... ... ... 22 0x015 ADC ADC conversion complete 23 0x016 EE READY EEPROM ready 24 0x017 ANALOG COMP Analog comparator 25 0x018 TWI 2-wire serial interface 26 0x019 SPM READY Store program memory ready Table 12-1. Reset and interrupt vectors in ATmega48. (Continued) Vector no. Program address Source Interrupt definition 58 2545T–AVR–05/11 ATmega48/88/168 12.3 Interrupt vectors in Atmel ATmega88 Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the boot loader address at reset, see “Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269. 2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the boot flash section. Table 12-3 on page 59 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. Table 12-2. Reset and interrupt vectors in ATmega88. Vector no. Program address(2) Source Interrupt definition 1 0x000(1) RESET External pin, power-on reset, brown-out reset and watchdog system reset 2 0x001 INT0 External interrupt request 0 3 0x002 INT1 External interrupt request 1 4 0x003 PCINT0 Pin change interrupt request 0 5 0x004 PCINT1 Pin change interrupt request 1 6 0x005 PCINT2 Pin change interrupt request 2 7 0x006 WDT Watchdog time-out interrupt 8 0x007 TIMER2 COMPA Timer/Counter2 compare match A 9 0x008 TIMER2 COMPB Timer/Counter2 compare match B 10 0x009 TIMER2 OVF Timer/Counter2 overflow 11 0x00A TIMER1 CAPT Timer/Counter1 capture event 12 0x00B TIMER1 COMPA Timer/Counter1 compare match A 13 0x00C TIMER1 COMPB Timer/Coutner1 compare match B 14 0x00D TIMER1 OVF Timer/Counter1 overflow 15 0x00E TIMER0 COMPA Timer/Counter0 compare match A 16 0x00F TIMER0 COMPB Timer/Counter0 compare match B 17 0x010 TIMER0 OVF Timer/Counter0 overflow 18 0x011 SPI, STC SPI serial transfer complete 19 0x012 USART, RX USART Rx complete 20 0x013 USART, UDRE USART, data register empty 21 0x014 USART, TX USART, Tx complete 22 0x015 ADC ADC conversion complete 23 0x016 EE READY EEPROM ready 24 0x017 ANALOG COMP Analog comparator 25 0x018 TWI 2-wire serial interface 26 0x019 SPM READY Store program memory ready 59 2545T–AVR–05/11 ATmega48/88/168 Note: 1. The boot reset address is shown in Table 27-6 on page 281. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the reset and interrupt vector addresses in ATmega88 is: Address Labels Code Comments 0x000 rjmp RESET ; Reset Handler 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler 0x003 rjmp PCINT0 ; PCINT0 Handler 0x004 rjmp PCINT1 ; PCINT1 Handler 0x005 rjmp PCINT2 ; PCINT2 Handler 0x006 rjmp WDT ; Watchdog Timer Handler 0x007 rjmp TIM2_COMPA ; Timer2 Compare A Handler 0X008 rjmp TIM2_COMPB ; Timer2 Compare B Handler 0x009 rjmp TIM2_OVF ; Timer2 Overflow Handler 0x00A rjmp TIM1_CAPT ; Timer1 Capture Handler 0x00B rjmp TIM1_COMPA ; Timer1 Compare A Handler 0x00C rjmp TIM1_COMPB ; Timer1 Compare B Handler 0x00D rjmp TIM1_OVF ; Timer1 Overflow Handler 0x00E rjmp TIM0_COMPA ; Timer0 Compare A Handler 0x00F rjmp TIM0_COMPB ; Timer0 Compare B Handler 0x010 rjmp TIM0_OVF ; Timer0 Overflow Handler 0x011 rjmp SPI_STC ; SPI Transfer Complete Handler 0x012 rjmp USART_RXC ; USART, RX Complete Handler 0x013 rjmp USART_UDRE ; USART, UDR Empty Handler 0x014 rjmp USART_TXC ; USART, TX Complete Handler 0x015 rjmp ADC ; ADC Conversion Complete Handler 0x016 rjmp EE_RDY ; EEPROM Ready Handler 0x017 rjmp ANA_COMP ; Analog Comparator Handler 0x018 rjmp TWI ; 2-wire Serial Interface Handler 0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler ; 0x01ARESET: ldi r16, high(RAMEND); Main program start 0x01B out SPH,r16 ; Set Stack Pointer to top of RAM 0x01C ldi r16, low(RAMEND) 0x01D out SPL,r16 0x01E sei ; Enable interrupts 0x01F xxx Table 12-3. Reset and interrupt vectors placement in Atmel ATmega88(1). BOOTRST IVSEL Reset address Interrupt vectors start address 1 0 0x000 0x001 1 1 0x000 Boot reset address + 0x001 0 0 Boot reset address 0x001 0 1 Boot reset address Boot reset address + 0x001 60 2545T–AVR–05/11 ATmega48/88/168 When the BOOTRST fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in Atmel ATmega88 is: Address Labels Code Comments 0x000 RESET: ldi r16,high(RAMEND); Main program start 0x001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x002 ldi r16,low(RAMEND) 0x003 out SPL,r16 0x004 sei ; Enable interrupts 0x005 xxx ; .org 0xC01 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the reset and interrupt vector addresses in ATmega88 is: Address Labels Code Comments .org 0x001 0x001 rjmp EXT_INT0 ; IRQ0 Handler 0x002 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x019 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0xC00 0xC00 RESET: ldi r16,high(RAMEND); Main program start 0xC01 out SPH,r16 ; Set Stack Pointer to top of RAM 0xC02 ldi r16,low(RAMEND) 0xC03 out SPL,r16 0xC04 sei ; Enable interrupts 0xC05 xxx When the BOOTRST fuse is programmed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in ATmega88 is: Address Labels Code Comments ; .org 0xC00 0xC00 rjmp RESET ; Reset handler 0xC01 rjmp EXT_INT0 ; IRQ0 Handler 0xC02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0xC19 rjmp SPM_RDY ; Store Program Memory Ready Handler ; 0xC1A RESET: ldi r16,high(RAMEND); Main program start 0xC1B out SPH,r16 ; Set Stack Pointer to top of RAM 61 2545T–AVR–05/11 ATmega48/88/168 0xC1C ldi r16,low(RAMEND) 0xC1D out SPL,r16 0xC1E sei ; Enable interrupts 0xC1F xxx 12.4 Interrupt vectors in Atmel ATmega168 Notes: 1. When the BOOTRST fuse is programmed, the device will jump to the boot loader address at reset, see “Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269. 2. When the IVSEL bit in MCUCR is set, interrupt vectors will be moved to the start of the boot flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the boot flash section. Table 12-4. Reset and interrupt vectors in ATmega168. Vector no. Program address(2) Source Interrupt definition 1 0x0000(1) RESET External pin, power-on reset, brown-out reset and watchdog system reset 2 0x0002 INT0 External interrupt request 0 3 0x0004 INT1 External interrupt request 1 4 0x0006 PCINT0 Pin change interrupt request 0 5 0x0008 PCINT1 Pin change interrupt request 1 6 0x000A PCINT2 Pin change interrupt request 2 7 0x000C WDT Watchdog time-out interrupt 8 0x000E TIMER2 COMPA Timer/Counter2 compare match A 9 0x0010 TIMER2 COMPB Timer/Counter2 compare match B 10 0x0012 TIMER2 OVF Timer/Counter2 overflow 11 0x0014 TIMER1 CAPT Timer/Counter1 capture event 12 0x0016 TIMER1 COMPA Timer/Counter1 compare match A 13 0x0018 TIMER1 COMPB Timer/Coutner1 compare match B 14 0x001A TIMER1 OVF Timer/Counter1 overflow 15 0x001C TIMER0 COMPA Timer/Counter0 compare match A 16 0x001E TIMER0 COMPB Timer/Counter0 compare match B 17 0x0020 TIMER0 OVF Timer/Counter0 overflow 18 0x0022 SPI, STC SPI serial transfer complete 19 0x0024 USART, RX USART Rx complete 20 0x0026 USART, UDRE USART, data register empty 21 0x0028 USART, TX USART, Tx complete 22 0x002A ADC ADC conversion complete 23 0x002C EE READY EEPROM ready 24 0x002E ANALOG COMP Analog comparator 25 0x0030 TWI 2-wire serial interface 26 0x0032 SPM READY Store program memory ready 62 2545T–AVR–05/11 ATmega48/88/168 Table 12-5 shows reset and interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. This is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. Note: 1. The boot reset address is shown in Table 27-6 on page 281. For the BOOTRST fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the reset and interrupt vector addresses in ATmega168 is: Address Labels Code Comments 0x0000 jmp RESET ; Reset Handler 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler 0x0006 jmp PCINT0 ; PCINT0 Handler 0x0008 jmp PCINT1 ; PCINT1 Handler 0x000A jmp PCINT2 ; PCINT2 Handler 0x000C jmp WDT ; Watchdog Timer Handler 0x000E jmp TIM2_COMPA ; Timer2 Compare A Handler 0x0010 jmp TIM2_COMPB ; Timer2 Compare B Handler 0x0012 jmp TIM2_OVF ; Timer2 Overflow Handler 0x0014 jmp TIM1_CAPT ; Timer1 Capture Handler 0x0016 jmp TIM1_COMPA ; Timer1 Compare A Handler 0x0018 jmp TIM1_COMPB ; Timer1 Compare B Handler 0x001A jmp TIM1_OVF ; Timer1 Overflow Handler 0x001C jmp TIM0_COMPA ; Timer0 Compare A Handler 0x001E jmp TIM0_COMPB ; Timer0 Compare B Handler 0x0020 jmp TIM0_OVF ; Timer0 Overflow Handler 0x0022 jmp SPI_STC ; SPI Transfer Complete Handler 0x0024 jmp USART_RXC ; USART, RX Complete Handler 0x0026 jmp USART_UDRE ; USART, UDR Empty Handler 0x0028 jmp USART_TXC ; USART, TX Complete Handler 0x002A jmp ADC ; ADC Conversion Complete Handler 0x002C jmp EE_RDY ; EEPROM Ready Handler 0x002E jmp ANA_COMP ; Analog Comparator Handler 0x0030 jmp TWI ; 2-wire Serial Interface Handler 0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x0033RESET: ldi r16, high(RAMEND); Main program start Table 12-5. Reset and interrupt vectors placement in Atmel ATmega168(1). BOOTRST IVSEL Reset address Interrupt vectors start address 1 0 0x000 0x001 1 1 0x000 Boot reset address + 0x0002 0 0 Boot reset address 0x001 0 1 Boot reset address Boot reset address + 0x0002 63 2545T–AVR–05/11 ATmega48/88/168 0x0034 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0035 ldi r16, low(RAMEND) 0x0036 out SPL,r16 0x0037 sei ; Enable interrupts 0x0038 xxx ... ... ... ... When the BOOTRST fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in Atmel ATmega168 is: Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0002 ldi r16,low(RAMEND) 0x0003 out SPL,r16 0x0004 sei ; Enable interrupts 0x0005 xxx ; .org 0xC02 0x1C02 jmp EXT_INT0 ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the reset and interrupt vector addresses in ATmega168 is: Address Labels Code Comments .org 0x0002 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x0032 jmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0x1C00 0x1C00 RESET: ldi r16,high(RAMEND); Main program start 0x1C01 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1C02 ldi r16,low(RAMEND) 0x1C03 out SPL,r16 0x1C04 sei ; Enable interrupts 0x1C05 xxx When the BOOTRST fuse is programmed, the boot section size set to 2Kbytes and the IVSEL bit in the MCUCR register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in ATmega168 is: 64 2545T–AVR–05/11 ATmega48/88/168 Address Labels Code Comments ; .org 0x1C00 0x1C00 jmp RESET ; Reset handler 0x1C02 jmp EXT_INT0 ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x1C33 RESET: ldi r16,high(RAMEND); Main program start 0x1C34 out SPH,r16 ; Set Stack Pointer to top of RAM 0x1C35 ldi r16,low(RAMEND) 0x1C36 out SPL,r16 0x1C37 sei ; Enable interrupts 0x1C38 xxx 12.4.1 Moving interrupts between application and boot space, Atmel ATmega88 and Atmel ATmega168 The MCU control register controls the placement of the interrupt vector table. 12.5 Register description 12.5.1 MCUCR – MCU control register • Bit 1 – IVSEL: Interrupt vector select When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. Refer to the section “Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: a. Write the interrupt vector change enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the status register is unaffected by the automatic disabling. Note: If interrupt vectors are placed in the boot loader section and boot lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the Application section and boot lock bit BLB12 is programmed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot loader support – Read-whilewrite self-programming, Atmel ATmega88 and Atmel ATmega168” on page 269 for details on Boot Lock bits. This bit is not available in Atmel ATmega48. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – PUD – – IVSEL IVCE MCUCR Read/write R R R R/W R R R/W R/W Initial value 0 0 0 0 0 0 0 0 65 2545T–AVR–05/11 ATmega48/88/168 • Bit 0 – IVCE: Interrupt vector change enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See code example below. This bit is not available in Atmel ATmega48. Assembly code example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 17.0.3 External clock source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 17-1 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 17-1. T1/T0 pin sampling. The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Tn_sync (to clock select logic) Synchronization Edge detector D Q D Q LE Tn D Q clkI/O 138 2545T–AVR–05/11 ATmega48/88/168 Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 17-2. Prescaler for timer/counter0 and timer/counter1(1). Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 17-1 on page 137. PSRSYNC Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization 139 2545T–AVR–05/11 ATmega48/88/168 17.1 Register description 17.1.1 GTCCR – General timer/counter control register • Bit 7 – TSM: Timer/counter synchronization mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSRSYNC: Prescaler reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR Read/write R/W R R R R R R/W R/W Initial value 0 0 0 0 0 0 0 0 140 2545T–AVR–05/11 ATmega48/88/168 18. 8-bit Timer/Counter2 with PWM and asynchronous operation 18.1 Features • Single channel counter • Clear timer on compare match (auto reload) • Glitch-free, phase correct pulse width modulator (PWM) • Frequency generator • 10-bit clock prescaler • Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B) • Allows clocking from external 32kHz watch crystal independent of the I/O clock 18.2 Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 18-1. For the actual placement of I/O pins, refer to “Pinout Atmel ATmega48/88/168.” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register description” on page 153. The PRTIM2 bit in “Minimizing power consumption” on page 41 must be written to zero to enable Timer/Counter2 module. Figure 18-1. 8-bit timer/counter block diagram. Clock select Timer/counter DATA BUS OCRnA OCRnB = = TCNTn Waveform generation Waveform generation OCnA OCnB = Fixed TOP value Control logic = 0 TOP BOTTOM Count Clear Direction TOVn (Int.req.) OCnA (Int.req.) OCnB (Int.req.) TCCRnA TCCRnB Tn Edge detector (From prescaler) clkTn 141 2545T–AVR–05/11 ATmega48/88/168 18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See “Output compare unit” on page 142. for details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request. 18.2.2 Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions in Table 18-1 are also used extensively throughout the section. 18.3 Timer/counter clock sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR – Asynchronous status register” on page 159. For details on clock sources and prescaler, see “Timer/counter prescaler” on page 152. 18.4 Counter unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 on page 142 shows a block diagram of the counter and its surrounding environment. Table 18-1. Definitions. BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation. 142 2545T–AVR–05/11 ATmega48/88/168 Figure 18-2. Counter unit block diagram. Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter Control Register B (TCCR2B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform generation, see “Modes of operation” on page 145. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. 18.5 Output compare unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of operation” on page 145). Figure 18-3 on page 143 shows a block diagram of the Output Compare unit. DATA BUS TCNTn Control logic count TOVn (Int.req.) bottom top direction clear TOSC1 T/C oscillator TOSC2 Prescaler clkI/O clk Tn 143 2545T–AVR–05/11 ATmega48/88/168 Figure 18-3. Output compare unit, block diagram. The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x directly. 18.5.1 Force output compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 18.5.2 Compare match blocking by TCNT2 write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 18.5.3 Using the output compare unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. OCFnx (int.req.) = (8-bit comparator) OCRnx OCnx DATA BUS TCNTn WGMn1:0 Waveform generator top FOCn COMnX1:0 bottom 144 2545T–AVR–05/11 ATmega48/88/168 The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 18.6 Compare match output unit The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x1:0 bits control the OC2x pin output source. Figure 18-4 shows a simplified schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. Figure 18-4. Compare match output unit, schematic. The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See “Register description” on page 153. PORT DDR D Q D Q OCnx OCnx pin D Q Waveform generator COMnx1 COMnx0 0 1 DATA BUS FOCnx clkI/O 145 2545T–AVR–05/11 ATmega48/88/168 18.6.1 Compare output mode and waveform generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 18-5 on page 154. For fast PWM mode, refer to Table 18-6 on page 155, and for phase correct PWM refer to Table 18-7 on page 155. A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 18.7 Modes of operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare match output unit” on page 144.). For detailed timing information refer to “Timer/counter timing diagrams” on page 149. 18.7.1 Normal mode The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 18.7.2 Clear timer on compare match (CTC) mode In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 18-5 on page 146. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. 146 2545T–AVR–05/11 ATmega48/88/168 Figure 18-5. CTC mode, timing diagram. An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 18.7.3 Fast PWM mode The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In noninverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. TCNTn OCnx (toggle) OCnx interrupt flag set Period 1 2 3 4 (COMnx1:0 = 1) f OCnx f clk_I/O 2 ⋅ ⋅ N ( ) 1 + OCRnx = ------------------------------------------------- 147 2545T–AVR–05/11 ATmega48/88/168 In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 18-6. Fast PWM mode, timing diagram. The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. (See Table 18-3 on page 154). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform TCNTn OCRnx update and TOVn interrupt flag set Period 1 2 3 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) OCRnx interrupt flag set 4 5 6 7 f OCnxPWM f clk_I/O N ⋅ 256 = ------------------ 148 2545T–AVR–05/11 ATmega48/88/168 generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.4 Phase correct PWM mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7. In noninverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 18-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 18-7. Phase correct PWM mode, timing diagram. The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM TOVn interrupt flag set OCnx interrupt flag set 1 2 3 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) OCRnx update 149 2545T–AVR–05/11 ATmega48/88/168 output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 18-4 on page 154). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 18-7 on page 148 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCR2A changes its value from MAX, like in Figure 18-7 on page 148. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up 18.8 Timer/counter timing diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 18-8. Timer/counter timing diagram, no prescaling. Figure 18-9 on page 150 shows the same timing data, but with the prescaler enabled. f OCnxPCPWM f clk_I/O N ⋅ 510 = ------------------ clkTn (clkI/O/1) TOVn clkI/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 150 2545T–AVR–05/11 ATmega48/88/168 Figure 18-9. Timer/counter timing diagram, with prescaler (fclk_I/O/8). Figure 18-10 shows the setting of OCF2A in all modes except CTC mode. Figure 18-10. Timer/counter timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8). Figure 18-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 18-11. Timer/counter timing diagram, clear timer on compare match mode, with prescaler (fclk_I/O/8). TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) OCFnx OCRnx TCNTn OCRnx value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8) OCFnx OCRnx TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) 151 2545T–AVR–05/11 ATmega48/88/168 18.9 Asynchronous operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. b. Select clock source by setting AS2 as appropriate. c. Write new values to TCNT2, OCR2x, and TCCR2x. d. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. e. Clear the Timer/Counter2 Interrupt Flags. f. Enable interrupts, if needed. • The CPU main clock frequency must be more than four times the Oscillator frequency • When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned registers have their individual temporary register, which means that, for example, writing to TCNT2 does not disturb an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented • When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: If reentering sleep mode within the TOSC1 cycle, the interrupt will immidiately occur and the device wake up again. The result is multiple interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: a. Write a value to TCCR2x, TCNT2, or OCR2x. b. Wait until the corresponding Update Busy Flag in ASSR returns to zero. c. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wakeup from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin 152 2545T–AVR–05/11 ATmega48/88/168 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Powersave mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: a. Write any value to either of the registers OCR2x or TCCR2x. b. Wait for the corresponding Update Busy Flag to be cleared. c. Read TCNT2. During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 18.10 Timer/counter prescaler Figure 18-12. Prescaler for Timer/Counter2. 10-BIT T/C PRESCALER TIMER/COUNTER2 CLOCK SOURCE clkI/O clkT2S TOSC1 AS2 CS20 CS21 CS22 clkT2S/8 clkT2S/64 clkT2S/128 clkT2S/1024 clkT2S/256 clkT2S/32 PSRASY 0 Clear clkT2 153 2545T–AVR–05/11 ATmega48/88/168 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 18.11 Register description 18.11.1 TCCR2A – Timer/counter control register A • Bits 7:6 – COM2A1:0: Compare match output A mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 18-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 18-3 on page 154 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Bit 7 6 5 4 3 2 1 0 (0xB0) COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A Read/write R/W R/W R/W R/W R R R/W R/W Initial value 0 0 0 0 0 0 0 0 Table 18-2. Compare output mode, non-PWM mode. COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected 0 1 Toggle OC2A on compare match 1 0 Clear OC2A on compare match 1 1 Set OC2A on compare match 154 2545T–AVR–05/11 ATmega48/88/168 Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 146 for more details. Table 18-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on page 148 for more details. • Bits 5:4 – COM2B1:0: Compare match output B mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 18-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 18-3. Compare output mode, fast PWM mode(1). COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected 0 1 WGM22 = 0: Normal port operation, OC0A disconnected WGM22 = 1: Toggle OC2A on compare match 1 0 Clear OC2A on compare match, set OC2A at BOTTOM, (non-inverting mode) 1 1 Set OC2A on compare match, clear OC2A at BOTTOM, (inverting mode) Table 18-4. Compare output mode, phase correct PWM Mode(1). COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected 0 1 WGM22 = 0: Normal port operation, OC2A disconnected WGM22 = 1: Toggle OC2A on compare match 1 0 Clear OC2A on compare match when up-counting Set OC2A on compare match when down-counting 1 1 Set OC2A on compare match when up-counting Clear OC2A on compare match when down-counting Table 18-5. Compare output mode, non-PWM mode. COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected 0 1 Toggle OC2B on compare match 1 0 Clear OC2B on compare match 1 1 Set OC2B on compare match 155 2545T–AVR–05/11 ATmega48/88/168 Table 18-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode. Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on page 148 for more details. Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on page 148 for more details. • Bits 3, 2 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM21:0: Waveform generation mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 18-8 on page 156. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 145). Table 18-6. Compare output mode, fast PWM mode(1). COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected 0 1 Reserved 1 0 Clear OC2B on compare match, set OC2B at BOTTOM, (non-inverting mode) 1 1 Set OC2B on compare match, clear OC2B at BOTTOM, (invertiing mode) Table 18-7. Compare output mode, phase correct PWM mode(1). COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected 0 1 Reserved 1 0 Clear OC2B on compare match when up-counting Set OC2B on compare match when down-counting 1 1 Set OC2B on compare match when up-counting Clear OC2B on compare match when down-counting 156 2545T–AVR–05/11 ATmega48/88/168 Notes: 1. MAX= 0xFF 2. BOTTOM= 0x00 18.11.2 TCCR2B – Timer/counter control register B • Bit 7 – FOC2A: Force output compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. • Bit 6 – FOC2B: Force output compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the forced compare. Table 18-8. Waveform generation mode bit description. Mode WGM2 WGM1 WGM0 Timer/counter mode of operation TOP Update of OCRx at TOV flag set on(1)(2) 0 0 0 0 Normal 0xFF Immediate MAX 10 0 1 PWM, phase correct 0xFF TOP BOTTOM 2 0 1 0 CTC OCRA Immediate MAX 3 0 1 1 Fast PWM 0xFF BOTTOM MAX 4 1 0 0 Reserved – – – 51 0 1 PWM, phase correct OCRA TOP BOTTOM 6 1 1 0 Reserved – – – 7 1 1 1 Fast PWM OCRA BOTTOM TOP Bit 7 6 5 4 3 2 1 0 (0xB1) FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B Read/write W W R R R R R/W R/W Initial value 0 0 0 0 0 0 0 0 157 2545T–AVR–05/11 ATmega48/88/168 A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved bits These bits are reserved bits in the Atmel ATmega48/88/168 and will always read as zero. • Bit 3 – WGM22: Waveform generation mode See the description in the “TCCR2A – Timer/counter control register A” on page 153. • Bit 2:0 – CS22:0: Clock select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 18-9. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 18.11.3 TCNT2 – Timer/counter register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 18.11.4 OCR2A – Output compare register A Table 18-9. Clock select bit description. CS22 CS21 CS20 Description 0 0 0 No clock source (timer/counter stopped) 0 0 1 clkT2S/(no prescaling) 0 1 0 clkT2S/8 (from prescaler) 0 1 1 clkT2S/32 (from prescaler) 1 0 0 clkT2S/64 (from prescaler) 1 0 1 clkT2S/128 (from prescaler) 1 1 0 clkT2S/256 (from prescaler) 1 1 1 clkT2S/1024 (from prescaler) Bit 7 6 5 4 3 2 1 0 (0xB2) TCNT2[7:0] TCNT2 Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0xB3) OCR2A[7:0] OCR2A Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 158 2545T–AVR–05/11 ATmega48/88/168 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 18.11.5 OCR2B – Output compare register B The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin. 18.11.6 TIMSK2 – Timer/Counter2 interrupt mask register • Bit 2 – OCIE2B: Timer/Counter2 output compare match B interrupt enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. • Bit 1 – OCIE2A: Timer/Counter2 output compare match A interrupt enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. • Bit 0 – TOIE2: Timer/Counter2 overflow interrupt enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 18.11.7 TIFR2 – Timer/Counter2 interrupt flag register • Bit 2 – OCF2B: Output compare flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed. Bit 7 6 5 4 3 2 1 0 (0xB4) OCR2B[7:0] OCR2B Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x70) – – – – – OCIE2B OCIE2A TOIE2 TIMSK2 Read/write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – OCF2B OCF2A TOV2 TIFR2 Read/write R R R R R R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 159 2545T–AVR–05/11 ATmega48/88/168 • Bit 1 – OCF2A: Output compare flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 overflow flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 18.11.8 ASSR – Asynchronous status register • Bit 7 – RES: Reserved bit This bit is reserved and will always read as zero. • Bit 6 – EXCLK: Enable external clock input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. • Bit 5 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. • Bit 4 – TCN2UB: Timer/Counter2 update busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 3 – OCR2AUB: Output compare Register2 update busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. • Bit 2 – OCR2BUB: Output compare Register2 update busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. Bit 7 6 5 4 3 2 1 0 (0xB6) – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR Read/write R R/W R/W R R R R R Initial value 0 0 0 0 0 0 0 0 160 2545T–AVR–05/11 ATmega48/88/168 • Bit 1 – TCR2AUB: Timer/counter control Register2 update busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. • Bit 0 – TCR2BUB: Timer/counter control Register2 update busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 18.11.9 GTCCR – General timer/counter control register • Bit 1 – PSRASY: Prescaler reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/counter synchronization mode” on page 139 for a description of the Timer/Counter Synchronization mode. Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC GTCCR Read/write R/W R R R R R R/W R/W Initial value 0 0 0 0 0 0 0 0 161 2545T–AVR–05/11 ATmega48/88/168 19. SPI – Serial peripheral interface 19.1 Features • Full-duplex, three-wire synchronous data transfer • Master or slave operation • LSB first or MSB first data transfer • Seven programmable bit rates • End of transmission interrupt flag • Write collision flag protection • Wake-up from idle mode • Double speed (CK/2) master SPI mode 19.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the Atmel ATmega48/88/168 and peripheral devices or between several AVR devices. The USART can also be used in Master SPI mode, see “USART in SPI mode” on page 199. The PRSPI bit in “Minimizing power consumption” on page 41 must be written to zero to enable SPI module. 162 2545T–AVR–05/11 ATmega48/88/168 Figure 19-1. SPI block diagram(1). Note: 1. Refer to Figure 1-1 on page 2, and Table 14-3 on page 78 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 163. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 163 2545T–AVR–05/11 ATmega48/88/168 Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 19-2. SPI master-slave interconnection. The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low periods: Longer than 2 CPU clock cycles. High periods: Longer than 2 CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1. For more details on automatic port overrides, refer to “Alternate port functions” on page 76. Note: See “Alternate functions of port B” on page 78 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example if MOSI is placed on pin PB3, replace DD_MOSI with DDB3 and DDR_SPI with DDRB. Table 19-1. SPI pin overrides(Note:). Pin Direction, master SPI Direction, slave SPI MOSI User defined Input MISO Input User defined SCK User defined Input SS User defined Input SHIFT ENABLE 164 2545T–AVR–05/11 ATmega48/88/168 Note: 1. See ”About code examples” on page 8. Assembly code example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSR0B = (1<> 1) & 0x01; return ((resh << 8) | resl); } 184 2545T–AVR–05/11 ATmega48/88/168 20.7.3 Receive complete flag and interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 20.7.4 Receiver error flags The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see “Parity bit calculation” on page 176 and “Parity checker” on page 184. 20.7.5 Parity checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. 185 2545T–AVR–05/11 ATmega48/88/168 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 20.7.6 Disabling the receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 20.7.7 Flushing the receive buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. See ”About code examples” on page 8. 20.8 Asynchronous data reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 20.8.1 Asynchronous clock recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 20-5 on page 186 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity). Assembly code example(1) USART_Flush: sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush C code example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRnA & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz VCC GND XTAL1 SCK MISO MOSI RESET +1.8V - 5.5V AVCC +1.8V - 5.5V(2) 299 2545T–AVR–05/11 ATmega48/88/168 28.8.1 Serial programming pin mapping 28.8.2 Serial programming algorithm When writing serial data to the Atmel ATmega48/88/168, data is clocked on the rising edge of SCK. When reading data from the ATmega48/88/168, data is clocked on the falling edge of SCK. See Figure 28-9 on page 302 for timing details. To program and verify the ATmega48/88/168 in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 28-17 on page 300): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page (see Table 28-16 on page 300). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte (see Table 28-16 on page 300). In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table Table 28-15. Pin mapping serial programming. Symbol Pins I/O Description MOSI PB3 I Serial Data in MISO PB4 O Serial Data out SCK PB5 I Serial Clock 300 2545T–AVR–05/11 ATmega48/88/168 28-16 on page 300). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. 28.8.3 Serial programming instruction set Table 28-17 and Figure 28-8 on page 302 describes the instruction set. Table 28-16. Typical wait delay before writing the next flash or EEPROM location. Symbol Minimum wait delay tWD_FLASH 4.5ms tWD_EEPROM 3.6ms tWD_ERASE 9.0ms Table 28-17. Serial programming instruction set (hexadecimal values). Instruction/operation Instruction format Byte 1 Byte 2 Byte 3 Byte 4 Programming enable $AC $53 $00 $00 Chip erase (program memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load instructions Load extended address byte(1) $4D $00 Extended adr $00 Load program memory page, high byte $48 $00 adr LSB high data byte in Load program memory page, low byte $40 $00 adr LSB low data byte in Load EEPROM memory page (page access) $C1 $00 0000 000aa data byte in Read instructions Read program memory, high byte $28 adr MSB adr LSB high data byte out Read program memory, low byte $20 adr MSB adr LSB low data byte out Read EEPROM memory $A0 0000 00aa aaaa aaaa data byte out Read lock bits $58 $00 $00 data byte out Read signature byte $30 $00 0000 000aa data byte out Read fuse bits $50 $00 $00 data byte out Read fuse high bits $58 $08 $00 data byte out Read extended fuse bits $50 $08 $00 data byte out Read calibration byte $38 $00 $00 data byte out 301 2545T–AVR–05/11 ATmega48/88/168 Notes: 1. Not all instructions are applicable for all parts. 2. a = address. 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused fuses and lock bits should be unprogrammed (‘1’). 5. Refer to the correspondig section for fuse and lock bits, calibration and signature bytes and page size. 6. Instructions accessing program memory use a word address. This word may be random within the page range. 7. See htt://www.atmel.com/avr for application notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 28-8. Write instructions(6) Write program memory page $4C adr MSB adr LSB $00 Write EEPROM memory $C0 0000 00aa aaaa aaaa data byte in Write EEPROM memory page (page access) $C2 0000 00aa aaaa aa00 $00 Write lock bits $AC $E0 $00 data byte in Write fuse bits $AC $A0 $00 data byte in Write fuse high bits $AC $A8 $00 data byte in Write extended fuse bits $AC $A4 $00 data byte in Table 28-17. Serial programming instruction set (hexadecimal values). (Continued) Instruction/operation Instruction format Byte 1 Byte 2 Byte 3 Byte 4 302 2545T–AVR–05/11 ATmega48/88/168 Figure 28-8. Serial programming instruction example. 28.8.4 SPI serial programming characteristics Figure 28-9. Serial programming waveforms. For characteristics of the SPI module see “SPI timing characteristics” on page 309. Byte 1 Byte 2 Byte 3 Byte 4 Adr MSB Adr LSB Bit 15 B 0 Serial programming instruction Program memory/ EEPROM memory Page 0 Page 1 Page 2 Page N-1 Page buffer Write program memory page/ Write EEPROM memory page Load program memory page (high/low byte)/ Load EEPROM memory page (page access) Byte 1 Byte 2 Byte 3 Byte 4 Bit 15 B 0 Adr MSB Adr LSB Page offset Page number Adr MSB Adr LSB MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT 303 2545T–AVR–05/11 ATmega48/88/168 29. Electrical characteristics 29.1 Absolute maximum ratings* 29.2 DC characteristics Operating temperature................................... -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage temperature...................................... -65°C to +150°C Voltage on any pin except RESET with respect to ground .................................-0.5V to VCC+0.5V Voltage on RESET with respect to ground ......-0.5V to +13.0V Maximum operating voltage.............................................. 6.0V DC current per I/O pin.................................................. 40.0mA DC current VCC and GND pins .................................. 200.0mA TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted). Symbol Parameter Condition Minimum Typical Maximum Units VIL Input low voltage, except XTAL1 and RESET pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 -0.5 0.2VCC(1) 0.3VCC(1) V VIH Input high voltage, except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC + 0.5 VCC + 0.5 VIL1 Input low voltage, XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) VIH1 Input high voltage, XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(2) 0.7VCC(2) VCC + 0.5 VCC + 0.5 VIL2 Input low voltage, RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC(1) VIH2 Input high voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 VIL3 Input low voltage, RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 -0.5 0.2VCC(1) 0.3VCC(1) VIH3 Input high voltage, RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC + 0.5 VCC + 0.5 VOL Output low voltage(3), RESET pin as I/O I OL = 20mA, VCC = 5V IOL = 6mA, VCC = 3V 0.7 0.5 VOH Output high voltage(4), RESET pin as I/O I OH = -20mA, VCC = 5V I OH = -10mA, VCC = 3V 4.2 2.3 IIL Input leakage current I/O pin VCC = 5.5V, pin low (absolute value) 1 µA I IH Input leakage current I/O pin VCC = 5.5V, pin high (absolute value) 1 RRST Reset pull-up resistor 30 60 kΩ RPU I/O pin pull-up resistor 20 50 304 2545T–AVR–05/11 ATmega48/88/168 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: ATmega48/88/168: 1] The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100mA. 2] The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA. 3] The sum of all IOL, for ports D0 - D4, RESET should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: ATmega48/88/168: 1] The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 150mA. 2] The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 150mA. If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Values with “Minimizing power consumption” on page 41 enabled (0xFF). ICC Power supply current(5) Active 1MHz, VCC = 2V (Atmel ATmega48/88/168V) 0.55 mA Active 4MHz, VCC = 3V (Atmel ATmega48/88/168L) 3.5 Active 8MHz, VCC = 5V (Atmel ATmega48/88/168) 12 Idle 1MHz, VCC = 2V (ATmega48/88/168V) 0.25 0.5 Idle 4MHz, VCC = 3V (ATmega48/88/168L) 1.5 Idle 8MHz, VCC = 5V (ATmega48/88/168) 5.5 Power-down mode WDT enabled, VCC = 3V 8 15 µA WDT disabled, VCC = 3V 1 2 VACIO Analog comparator input offset voltage VCC = 5V Vin = VCC/2 10 40 mV IACLK Analog comparator input leakage current VCC = 5V Vin = VCC/2 -50 50 nA t ACID Analog comparator propagation delay VCC = 2.7V VCC = 4.0V 750 500 ns TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted). (Continued) Symbol Parameter Condition Minimum Typical Maximum Units 305 2545T–AVR–05/11 ATmega48/88/168 29.3 Speed grades Maximum frequency is dependent on VCC. As shown in Figure 29-1 and Figure 29-2, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 29-1. Maximum frequency vs. VCC, Atmel ATmega48V/88V/168V. Figure 29-2. Maximum frequency vs. VCC, ATmega48/88/168. 10MHz 4MHz 1.8V 2.7V 5.5V Safe operating area 20MHz 10MHz 2.7V 4.5V 5.5V Safe operating area 306 2545T–AVR–05/11 ATmega48/88/168 29.4 Clock characteristics 29.4.1 Calibrated internal RC oscillator accuracy Notes: 1. Voltage range for Atmel ATmega48V/88V/168V. 2. Voltage range for Atmel ATmega48/88/168. 29.4.2 External clock drive waveforms Figure 29-3. External clock drive waveforms. 29.4.3 External clock drive Table 29-1. Calibration accuracy of internal RC oscillator. Frequency VCC Temperature Calibration accuracy Factory calibration 8.0MHz 3V 25°C ±10% User calibration 7.3MHz - 8.1MHz 1.8V - 5.5V(1) 2.7V - 5.5V(2) -40°C - 85°C ±1% VIL1 VIH1 Table 29-2. External clock drive. Symbol Parameter VCC = 1.8V - 5.5V VCC = 2.7V - 5.5V VCC = 4.5V - 5.5V Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator frequency 0 4 0 10 0 20 MHz tCLCL Clock period 250 100 50 tCHCX High time 100 40 20 ns tCLCX Low time 100 40 20 tCLCH Rise time 2.0 1.6 0.5 μs tCHCL Fall time 2.0 1.6 0.5 ΔtCLCL Change in period from one clock cycle to the next 2 2 2% 307 2545T–AVR–05/11 ATmega48/88/168 29.5 System and reset characteristics Note: 1. The power-on reset will not work unless the supply voltage has been below VPOT (falling). Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a brown-out reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 and BODLEVEL = 101 for Atmel ATmega48V/88V/168V, and BODLEVEL = 101 and BODLEVEL = 100 for Atmel ATmega48/88/168. Table 29-3. Reset, brown-out and internal voltage characteristics. Symbol Parameter Condition Min. Typ. Max. Units VPOT Power-on reset threshold voltage (rising) 0.7 1.0 1.4 V Power-on reset threshold voltage (falling)(1) 0.05 0.9 1.3 VPONSR Power-on slope rate 0.01 4.5 V/ms VRST RESET pin threshold voltage 0.2VCC 0.9VCC V tRST Minimum pulse width on RESET pin 2.5 µs VHYST Brown-out detector hysteresis 50 mV tBOD Min pulse width on brown-out reset 2 µs VBG Bandgap reference voltage VCC = 2.7 TA = 25°C 1.0 1.1 1.2 V t BG Bandgap reference start-up time VCC = 2.7 TA = 25°C 40 70 µs I BG Bandgap reference current consumption VCC = 2.7 TA = 25°C 10 µA Table 29-4. BODLEVEL fuse coding(1). BODLEVEL 2:0 Fuses Min. VBOT Typ. VBOT Max. VBOT Units 111 BOD disabled 110 1.7 1.8 2.0 101 2.5 2.7 2.9 V 100 4.1 4.3 4.5 011 Reserved 010 001 000 308 2545T–AVR–05/11 ATmega48/88/168 29.6 2-wire serial interface characteristics Table 29-5 describes the requirements for devices connected to the 2-wire Serial Bus. The Atmel ATmega48/88/168 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-4 on page 309. Notes: 1. In ATmega48/88/168, this parameter is characterized and not 100% tested. 2. Required only for fSCL > 100kHz. Table 29-5. 2-wire serial bus requirements. Symbol Parameter Condition Min. Max. Units VIL Input low-voltage -0.5 0.3VCC V VIH Input high-voltage 0.7VCC VCC + 0.5 Vhys(1) Hysteresis of schmitt trigger inputs 0.05VCC(2) – VOL(1) Output low-voltage 3mA sink current 0 0.4 tr (1) Rise time for both SDA and SCL 20 + 0.1Cb (3)(2) 300 tof ns (1) Output fall time from VIHmin to VILmax 10pF < Cb < 400pF(3) 20 + 0.1Cb (3)(2) 250 tSP(1) Spikes suppressed by input filter 0 50(2) Ii Input current each I/O pin 0.1VCC < Vi < 0.9VCC -10 10 µA Ci (1) Capacitance for each I/O pin – 10 pF fSCL SCL clock frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz Rp Value of pull-up resistor fSCL ≤ 100kHz fSCL > 100kHz tHD;STA Hold time (repeated) START condition fSCL ≤ 100kHz 4.0 – µs fSCL > 100kHz 0.6 – tLOW Low period of the SCL clock fSCL ≤ 100kHz 4.7 – fSCL > 100kHz 1.3 – tHIGH High period of the SCL clock fSCL ≤ 100kHz 4.0 – fSCL > 100kHz 0.6 – tSU;STA Setup time for a repeated START condition fSCL ≤ 100kHz 4.7 – fSCL > 100kHz 0.6 – tHD;DAT Data hold time fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 tSU;DAT Data setup time fSCL ≤ 100kHz 250 – ns fSCL > 100kHz 100 – tSU;STO Setup time for STOP condition fSCL ≤ 100kHz 4.0 – µs fSCL > 100kHz 0.6 – tBUF Bus free time between a STOP and START condition fSCL ≤ 100kHz 4.7 – fSCL > 100kHz 1.3 – VCC – 0.4V 3mA --------------------------- 1000ns Cb ---------------- Ω VCC – 0.4V 3mA --------------------------- 300ns Cb ------------- 309 2545T–AVR–05/11 ATmega48/88/168 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency. 5. This requirement applies to all Atmel ATmega48/88/168 2-wire Serial Interface operation. Other devices connected to the 2- wire Serial Bus need only obey the general fSCL requirement. Figure 29-4. 2-wire serial bus timing. 29.7 SPI timing characteristics See Figure 29-5 on page 310 and Figure 29-6 on page 310 for details. Note: 1. In SPI programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK > 12MHz t SU;STA t LOW t HIGH t LOW t of t HD;STA t HD;DAT t SU;DAT t SU;STO t BUF SCL SDA t r Table 29-6. SPI timing parameters. Description Mode Minimum Typical Maximum 1 SCK period Master See Table 19-5 on page 169 ns 2 SCK high/low Master 50% duty cycle 3 Rise/fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/fall time Slave 1600 13 Setup Slave 10 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 310 2545T–AVR–05/11 ATmega48/88/168 Figure 29-5. SPI interface timing requirements (master mode). Figure 29-6. SPI interface timing requirements (slave mode). MOSI (Data output) SCK (CPOL = 1) MISO (Data input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 6 1 2 2 4 5 3 7 8 MISO (Data output) SCK (CPOL = 1) MOSI (Data input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 10 11 11 13 14 12 15 17 9 X 16 311 2545T–AVR–05/11 ATmega48/88/168 29.8 ADC characteristics Note: 1. AVCC absolute min./max.: 1.8V/5.5V Table 29-7. ADC characteristics. Symbol Parameter Condition Minimum Typical Maximum Units Resolution 10 Bits Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1MHz 4.5 VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise reduction mode 2 VREF = 4V, VCC = 4V, ADC clock = 1MHz Noise reduction mode 4.5 Integral non-linearity (INL) VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.5 Differential non-linearity (DNL) VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.25 Gain error VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 Offset error VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 Conversion time Free running conversion 13 260 µs Clock frequency 50 1000 kHz AVCC(1) Analog supply voltage VCC - 0.3 VCC + 0.3 VREF Reference voltage 1.0 AVCC V VIN Input voltage GND VREF Input bandwidth 38.5 kHz VINT Internal voltage reference 1.0 1.1 1.2 V RREF Reference input resistance 32 kΩ RAIN Analog input resistance 100 MΩ 312 2545T–AVR–05/11 ATmega48/88/168 29.9 Parallel programming characteristics Figure 29-7. Parallel programming timing, including some general timing requirements. Figure 29-8. Parallel programming timing, loading sequence with timing requirements(1). Note: 1. The timing requirements shown in Figure 29-7 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Data & contol (DATA, XA0/1, BS1, BS2) XTAL1 t XHXL t WLWH t DVXH t XLDX t PLWL t WLRH WR RDY/BSY PAGEL t PHPL t PLBX t BVPH t XLWL t WLBX tBVWL WLRL XTAL1 PAGEL t XLXH PLXH t t XLPH DATA ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte) BS1 XA0 XA1 LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD DATA LOAD ADDRESS (LOW BYTE) 313 2545T–AVR–05/11 ATmega48/88/168 Figure 29-9. Parallel programming timing, reading sequence (within the same page) with timing requirements(1). Note: 1. The timing requirements shown in Figure 29-7 on page 312 (that is, tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 29-8. Parallel programming characteristics, VCC = 5V ±10%. Symbol Parameter Min. Typ. Max. Units VPP Programming enable voltage 11.5 12.5 V IPP Programming enable current 250 µA tDVXH Data and control valid before XTAL1 high 67 ns tXLXH XTAL1 low to XTAL1 high 200 tXHXL XTAL1 pulse width high 150 tXLDX Data and control hold after XTAL1 low 67 tXLWL XTAL1 low to WR low 0 tXLPH XTAL1 low to PAGEL high 0 tPLXH PAGEL low to XTAL1 high 150 tBVPH BS1 valid before PAGEL high 67 tPHPL PAGEL pulse width high 150 tPLBX BS1 hold after PAGEL low 67 tWLBX BS2/1 hold after WR low 67 tPLWL PAGEL low to WR low 67 tBVWL BS1 valid to WR low 67 tWLWH WR pulse width low 150 tWLRL WR low to RDY/BSY low 0 1 µs tWLRH WR low to RDY/BSY high(1) 3.7 4.5 ms tWLRH_CE WR low to RDY/BSY high for chip erase(2) 7.5 9 XTAL1 OE DATA ADDR0 (low byte) DATA (low byte) DATA (high byte) ADDR1 (low byte) BS1 XA0 XA1 LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t BVDV t OLDV t XLOL t OHDZ 314 2545T–AVR–05/11 ATmega48/88/168 Notes: 1. tWLRH is valid for the write flash, write EEPROM, write fuse bits and write lock bits commands. 2. tWLRH_CE is valid for the chip erase command. t XLOL XTAL1 low to OE low 0 ns t BVDV BS1 valid to DATA valid 0 250 tOLDV OE low to DATA valid 250 t OHDZ OE high to DATA tri-stated 250 Table 29-8. Parallel programming characteristics, VCC = 5V ±10%. (Continued) Symbol Parameter Min. Typ. Max. Units 315 2545T–AVR–05/11 ATmega48/88/168 30. Typical characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. Table 30-1 on page 321 and Table 30-2 on page 321 show the additional current consumption compared to ICC Active and ICC Idle for every I/O module controlled by the Power Reduction Register. See “Power reduction register” on page 41 for details. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 30.1 Active supply current Figure 30-1. Active supply current vs. frequency (0.1MHz - 1.0MHz). 5.5V 5.0V 4.5V 4.0V 3.3V 2.7V 1.8V 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 316 2545T–AVR–05/11 ATmega48/88/168 Figure 30-2. Active supply current vs. frequency (1MHz - 24MHz). Figure 30-3. Active supply current vs. VCC (internal RC oscillator, 128kHz). 0 2 4 6 8 10 12 14 16 18 0 4 8 12 16 20 24 Frequency (MHz) ICC (mA) 2.7V 1.8V 3.3V 4.0V 4.5V 5.0V 5.5V , 85°C 25°C -40°C 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 317 2545T–AVR–05/11 ATmega48/88/168 Figure 30-4. Active supply current vs. VCC (internal RC oscillator, 1MHz). Figure 30-5. Active supply current vs. VCC (internal RC oscillator, 8MHz). , 85°C 25°C -40°C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) , 85°C 25°C -40°C 0 1 2 3 4 5 6 7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 318 2545T–AVR–05/11 ATmega48/88/168 Figure 30-6. Active supply current vs. VCC (32kHz external oscillator). 30.2 Idle supply current Figure 30-7. Idle supply current vs. frequency (0.1MHz - 1.0MHz). 25°C 0 10 20 30 40 50 60 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 5.5V 5.0V 4.5V 4.0V 3.3V 2.7V 1.8V 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 319 2545T–AVR–05/11 ATmega48/88/168 Figure 30-8. Idle supply current vs. frequency (1MHz - 24MHz). Figure 30-9. Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 4 8 12 16 20 24 Frequency (MHz) ICC (mA) 2.7V 1.8V 3.3V 4.0V 4.5V 5.0V 5.5V 85°C 25°C -40°C 0 0.005 0.01 0.015 0.02 0.025 0.03 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 320 2545T–AVR–05/11 ATmega48/88/168 Figure 30-10. Idle supply current vs. VCC (internal RC oscillator, 1MHz). Figure 30-11. Idle supply current vs. VCC (internal RC oscillator, 8MHz). , 85°C 25°C -40°C 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) , 85°C 25°C -40°C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 321 2545T–AVR–05/11 ATmega48/88/168 Figure 30-12. Idle supply current vs. VCC (32kHz external oscillator). 30.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See “Power reduction register” on page 41 for details. 25°C 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) Table 30-1. Additional current consumption for the different I/O modules (absolute values). PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART0 8.0µA 51µA 220µA PRTWI 12µA 75µA 315µA PRTIM2 11µA 72µA 300µA PRTIM1 5.0µA 32µA 130µA PRTIM0 4.0µA 24µA 100µA PRSPI 15µA 95µA 400µA PRADC 12µA 75µA 315µA Table 30-2. Additional current consumption (percentage) in active and idle mode. PRR bit Additional current consumption compared to active with external clock (see Figure 30-1 on page 315 and Figure 30-2 on page 316) Additional current consumption compared to Idle with external clock (see Figure 30-7 on page 318 and Figure 30-8 on page 319) PRUSART0 3.3% 18% PRTWI 4.8% 26% PRTIM2 4.7% 25% 322 2545T–AVR–05/11 ATmega48/88/168 It is possible to calculate the typical current consumption based on the numbers from Table 30-2 on page 321 for other VCC and frequency settings than listed in Table 30-1 on page 321. 30.3.0.1 Example 1 Calculate the expected current consumption in idle mode with USART0, TIMER1, and TWI enabled at VCC = 3.0V and F = 1MHz. From Table 30-2 on page 321, third column, we see that we need to add 18% for the USART0, 26% for the TWI, and 11% for the TIMER1 module. Reading from Figure 30-7 on page 318, we find that the idle current consumption is ~0.075mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and TWI enabled, gives: 30.3.0.2 Example 2 Same conditions as in example 1, but in active mode instead. From Table 30-2 on page 321, second column we see that we need to add 3.3% for the USART0, 4.8% for the TWI, and 2.0% for the TIMER1 module. Reading from Figure 30-1 on page 315, we find that the active current consumption is ~0.42mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and TWI enabled, gives: 30.3.0.3 Example 3 All I/O modules should be enabled. Calculate the expected current consumption in active mode at VCC = 3.6V and F = 10MHz. We find the active current consumption without the I/O modules to be ~ 4.0mA (from Figure 30-2 on page 316). Then, by using the numbers from Table 30-2 on page 321 - second column, we find the total current consumption: PRTIM1 2.0% 11% PRTIM0 1.6% 8.5% PRSPI 6.1% 33% PRADC 4.9% 26% Table 30-2. Additional current consumption (percentage) in active and idle mode. (Continued) PRR bit Additional current consumption compared to active with external clock (see Figure 30-1 on page 315 and Figure 30-2 on page 316) Additional current consumption compared to Idle with external clock (see Figure 30-7 on page 318 and Figure 30-8 on page 319) ICCtotal ≈ ≈ 0.075mA • ( ) 1 0.18 0.26 0.11 +++ 0.116mA ICCtotal ≈ ≈ 0.42mA • ( ) 1 0.033 0.048 0.02 +++ 0.46mA ICCtotal ≈ ≈ 4.0mA • ( ) 1 0.033 0.048 0.047 0.02 0.016 0.061 0.049 + + + ++ + + 5.1mA 323 2545T–AVR–05/11 ATmega48/88/168 30.4 Power-down supply current Figure 30-13. Power-down supply current vs. VCC (watchdog timer disabled). Figure 30-14. Power-down supply current vs. VCC (watchdog timer enabled). 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C 0 2 4 6 8 10 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 324 2545T–AVR–05/11 ATmega48/88/168 30.5 Power-save supply current Figure 30-15. Power-save supply current vs. VCC (watchdog timer disabled). 30.6 Standby supply current Figure 30-16. Standby supply current vs. VCC (low power crystal oscillator). 25°C 0 2 4 6 8 10 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 6MHz Xtal 6MHz Res. 4MHz Xtal 4MHz Res. 455kHz Res. 32kHz Xtal 2MHz Xtal 2MHz Res. 1MHz Res. 0 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 325 2545T–AVR–05/11 ATmega48/88/168 Figure 30-17. Standby supply current vs. VCC (full swing crystal oscillator). 30.7 Pin pull-up Figure 30-18. I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 6MHz Xtal (ckopt) 4MHz Xtal (ckopt) 2MHz Xtal (ckopt) 16MHz Xtal 12MHz Xtal 0 50 100 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C 0 20 40 60 80 100 120 140 160 0123456 VOP (V) IOP (µA) 326 2545T–AVR–05/11 ATmega48/88/168 Figure 30-19. I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). Figure 30-20. Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 85°C 25°C -40°C 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 VOP (V) IOP (µA) 0 20 40 60 80 100 120 0123456 VRESET (V) IRESET (µA) -40°C 25°C 85°C 327 2545T–AVR–05/11 ATmega48/88/168 Figure 30-21. Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 30.8 Pin driver strength Figure 30-22. I/O pin source current vs. output voltage (VCC = 5V). -40°C 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 VRESET (V) IRESET (µA) 25°C 85°C 85°C 25°C -40°C 0 10 20 30 40 50 60 70 80 90 0123456 VOH (V) IOH (mA) 328 2545T–AVR–05/11 ATmega48/88/168 Figure 30-23. I/O pin source current vs. output voltage (VCC = 2.7V). Figure 30-24. I/O pin source current vs. output voltage (VCC = 1.8V). 85°C 25°C -40°C 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA) 85°C 25°C -40°C 0 1 2 3 4 5 6 7 8 9 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) IOH (mA) 329 2545T–AVR–05/11 ATmega48/88/168 Figure 30-25. I/O pin sink current vs. output voltage (VCC = 5V). Figure 30-26. I/O pin sink current vs. output voltage (VCC = 2.7V). 85°C 25°C 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 VOL (V) IOL (mA) 85°C 25°C -40°C 0 5 10 15 20 25 30 35 40 0 0.5 1 1.5 2 2.5 VOL (V) IOL (mA) 330 2545T–AVR–05/11 ATmega48/88/168 Figure 30-27. I/O pin sink current vs. output voltage (VCC = 1.8V). 30.9 Pin thresholds and hysteresis Figure 30-28. I/O pin input threshold voltage vs. VCC (VIH, I/O pin read as '1'). 85°C 25°C -40°C 0 2 4 6 8 10 12 14 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 331 2545T–AVR–05/11 ATmega48/88/168 Figure 30-29. I/O pin input threshold voltage vs. VCC (VIL, I/O pin read as '0'). Figure 30-30. I/O pin input hystreresis vs. Vcc. 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input hysteresis (V) 332 2545T–AVR–05/11 ATmega48/88/168 Figure 30-31. Reset input threshold voltage vs. VCC (VIH, reset pin read as '1'). Figure 30-32. Reset input threshold voltage vs. VCC (VIL, reset pin read as '0'). 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 333 2545T–AVR–05/11 ATmega48/88/168 Figure 30-33. Reset input pin hysteresis vs. VCC. 30.10 BOD thresholds and analog comparator offset Figure 30-34. BOD thresholds vs. temperature (BODLEVEL is 4.3V). VIL 0 100 200 300 400 500 600 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input hysteresis (mV) 4.2 4.25 4.3 4.35 4.4 4.45 4.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Threshold (V) Rising Vcc Falling Vcc 334 2545T–AVR–05/11 ATmega48/88/168 Figure 30-35. BOD thresholds vs. temperature (BODLEVEL is 2.7V). Figure 30-36. BOD thresholds vs. temperature (BODLEVEL is 1.8V). 2.6 2.65 2.7 2.75 2.8 2.85 2.9 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Threshold (V) Rising Vcc Falling Vcc 1.76 1.78 1.8 1.82 1.84 1.86 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Threshold (V) Rising Vcc Falling Vcc 335 2545T–AVR–05/11 ATmega48/88/168 Figure 30-37. Bandgap voltage vs. VCC. Figure 30-38. Analog comparator offset voltage vs. common mode voltage (VCC = 5V). -40°C 85°C 1.08 1.085 1.09 1.095 1.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Bandgap voltage (V) -40°C 85°C 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Analog comparator offset voltage (V) 336 2545T–AVR–05/11 ATmega48/88/168 Figure 30-39. Analog comparator offset voltage vs. common mode voltage (VCC = 2.7V). 30.11 Internal oscillator speed Figure 30-40. Watchdog oscillator frequency vs. VCC. -40°C 85°C 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 Common Mode Voltage (V) Analog comparator offset voltage (mV) 85°C 25°C -40°C 95 100 105 110 115 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (kHz) 337 2545T–AVR–05/11 ATmega48/88/168 Figure 30-41. Calibrated 8MHz RC oscillator frequency vs. temperature. Figure 30-42. Calibrated 8MHz RC oscillator frequency vs. VCC. 5.0V 2.7V 1.8V 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) FRC (MHz) 85°C 25°C -40°C 7.4 7.6 7.8 8 8.2 8.4 8.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 338 2545T–AVR–05/11 ATmega48/88/168 Figure 30-43. Calibrated 8MHz RC oscillator frequency vs. osccal value. 30.12 Current consumption of peripheral units Figure 30-44. Brownout detector current vs. VCC. 85°C 25°C -40°C 3.5 5.5 7.5 9.5 11.5 13.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz) 85°C 25°C -40°C 18 20 22 24 26 28 30 32 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 339 2545T–AVR–05/11 ATmega48/88/168 Figure 30-45. ADC current vs. VCC (AREF = AVCC). Figure 30-46. AREF external reference current vs. VCC. 85°C 25°C -40°C 150 200 250 300 350 400 450 500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C 0 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 340 2545T–AVR–05/11 ATmega48/88/168 Figure 30-47. Analog comparator current vs. VCC. Figure 30-48. Programming current vs. VCC. 85°C 25°C -40°C 0 20 40 60 80 100 120 140 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C 0 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 0 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 341 2545T–AVR–05/11 ATmega48/88/168 30.13 Current consumption in reset and reset pulse width Figure 30-49. Reset supply current vs. VCC (0.1MHz - 1.0MHz, excluding current through the reset pull-up). Figure 30-50. Reset supply current vs. VCC (1MHz - 24MHz, excluding current through the reset pull-up). 5.5V 5.0V 4.5V 4.0V 3.3V 2.7V 1.8V 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) , 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 4 8 12 16 20 24 Frequency (MHz) ICC (mA) 2.7V 1.8V 3.3V 4.0V 4.5V 5.0V 5.5V 342 2545T–AVR–05/11 ATmega48/88/168 Figure 30-51. Reset pulse width vs. VCC. 85°C 25°C -40°C 0 500 1000 1500 2000 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pulsewidth (ns) 343 2545T–AVR–05/11 ATmega48/88/168 31. Register summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved – – – – – – – – (0xFE) Reserved – – – – – – – – (0xFD) Reserved – – – – – – – – (0xFC) Reserved – – – – – – – – (0xFB) Reserved – – – – – – – – (0xFA) Reserved – – – – – – – – (0xF9) Reserved – – – – – – – – (0xF8) Reserved – – – – – – – – (0xF7) Reserved – – – – – – – – (0xF6) Reserved – – – – – – – – (0xF5) Reserved – – – – – – – – (0xF4) Reserved – – – – – – – – (0xF3) Reserved – – – – – – – – (0xF2) Reserved – – – – – – – – (0xF1) Reserved – – – – – – – – (0xF0) Reserved – – – – – – – – (0xEF) Reserved – – – – – – – – (0xEE) Reserved – – – – – – – – (0xED) Reserved – – – – – – – – (0xEC) Reserved – – – – – – – – (0xEB) Reserved – – – – – – – – (0xEA) Reserved – – – – – – – – (0xE9) Reserved – – – – – – – – (0xE8) Reserved – – – – – – – – (0xE7) Reserved – – – – – – – – (0xE6) Reserved – – – – – – – – (0xE5) Reserved – – – – – – – – (0xE4) Reserved – – – – – – – – (0xE3) Reserved – – – – – – – – (0xE2) Reserved – – – – – – – – (0xE1) Reserved – – – – – – – – (0xE0) Reserved – – – – – – – – (0xDF) Reserved – – – – – – – – (0xDE) Reserved – – – – – – – – (0xDD) Reserved – – – – – – – – (0xDC) Reserved – – – – – – – – (0xDB) Reserved – – – – – – – – (0xDA) Reserved – – – – – – – – (0xD9) Reserved – – – – – – – – (0xD8) Reserved – – – – – – – – (0xD7) Reserved – – – – – – – – (0xD6) Reserved – – – – – – – – (0xD5) Reserved – – – – – – – – (0xD4) Reserved – – – – – – – – (0xD3) Reserved – – – – – – – – (0xD2) Reserved – – – – – – – – (0xD1) Reserved – – – – – – – – (0xD0) Reserved – – – – – – – – (0xCF) Reserved – – – – – – – – (0xCE) Reserved – – – – – – – – (0xCD) Reserved – – – – – – – – (0xCC) Reserved – – – – – – – – (0xCB) Reserved – – – – – – – – (0xCA) Reserved – – – – – – – – (0xC9) Reserved – – – – – – – – (0xC8) Reserved – – – – – – – – (0xC7) Reserved – – – – – – – – (0xC6) UDR0 USART I/O data register 190 (0xC5) UBRR0H USART baud rate register high 194 (0xC4) UBRR0L USART baud rate register low 194 (0xC3) Reserved – – – – – – – – (0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 UCPOL0 192/207 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 191 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190 344 2545T–AVR–05/11 ATmega48/88/168 (0xBF) Reserved – – – – – – – – (0xBE) Reserved – – – – – – – – (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 – 239 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 236 (0xBB) TWDR 2-wire serial interface data register 238 (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 239 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 238 (0xB8) TWBR 2-wire serial interface bit rate register 236 (0xB7) Reserved – – – – – – – (0xB6) ASSR – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 159 (0xB5) Reserved – – – – – – – – (0xB4) OCR2B Timer/Counter2 output compare register B 158 (0xB3) OCR2A Timer/Counter2 output compare register A 157 (0xB2) TCNT2 Timer/Counter2 (8-bit) 157 (0xB1) TCCR2B FOC2A FOC2B – – WGM22 CS22 CS21 CS20 156 (0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 153 (0xAF) Reserved – – – – – – – – (0xAE) Reserved – – – – – – – – (0xAD) Reserved – – – – – – – – (0xAC) Reserved – – – – – – – – (0xAB) Reserved – – – – – – – – (0xAA) Reserved – – – – – – – – (0xA9) Reserved – – – – – – – – (0xA8) Reserved – – – – – – – – (0xA7) Reserved – – – – – – – – (0xA6) Reserved – – – – – – – – (0xA5) Reserved – – – – – – – – (0xA4) Reserved – – – – – – – – (0xA3) Reserved – – – – – – – – (0xA2) Reserved – – – – – – – – (0xA1) Reserved – – – – – – – – (0xA0) Reserved – – – – – – – – (0x9F) Reserved – – – – – – – – (0x9E) Reserved – – – – – – – – (0x9D) Reserved – – – – – – – – (0x9C) Reserved – – – – – – – – (0x9B) Reserved – – – – – – – – (0x9A) Reserved – – – – – – – – (0x99) Reserved – – – – – – – – (0x98) Reserved – – – – – – – – (0x97) Reserved – – – – – – – – (0x96) Reserved – – – – – – – – (0x95) Reserved – – – – – – – – (0x94) Reserved – – – – – – – – (0x93) Reserved – – – – – – – – (0x92) Reserved – – – – – – – – (0x91) Reserved – – – – – – – – (0x90) Reserved – – – – – – – – (0x8F) Reserved – – – – – – – – (0x8E) Reserved – – – – – – – – (0x8D) Reserved – – – – – – – – (0x8C) Reserved – – – – – – – – (0x8B) OCR1BH Timer/Counter1 - output compare register B high byte 134 (0x8A) OCR1BL Timer/Counter1 - output compare register B low byte 134 (0x89) OCR1AH Timer/Counter1 - output compare register A high byte 134 (0x88) OCR1AL Timer/Counter1 - output compare register A low byte 134 (0x87) ICR1H Timer/Counter1 - input capture register high byte 135 (0x86) ICR1L Timer/Counter1 - input capture register low byte 135 (0x85) TCNT1H Timer/Counter1 - counter register high byte 134 (0x84) TCNT1L Timer/Counter1 - counter register low byte 134 (0x83) Reserved – – – – – – – – (0x82) TCCR1C FOC1A FOC1B – – – – – – 133 (0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 132 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 130 (0x7F) DIDR1 – – – – – – AIN1D AIN0D 243 (0x7E) DIDR0 – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 259 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 345 2545T–AVR–05/11 ATmega48/88/168 (0x7D) Reserved – – – – – – – – (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 255 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 258 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 256 (0x79) ADCH ADC data register high byte 258 (0x78) ADCL ADC data register low byte 258 (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved – – – – – – – – (0x74) Reserved – – – – – – – – (0x73) Reserved – – – – – – – – (0x72) Reserved – – – – – – – – (0x71) Reserved – – – – – – – – (0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 158 (0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 135 (0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 106 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 70 (0x6C) PCMSK1 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 70 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 70 (0x6A) Reserved – – – – – – – – (0x69) EICRA – – – – ISC11 ISC10 ISC01 ISC00 67 (0x68) PCICR – – – – – PCIE2 PCIE1 PCIE0 (0x67) Reserved – – – – – – – – (0x66) OSCCAL Oscillator calibration register 37 (0x65) Reserved – – – – – – – – (0x64) PRR PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC 41 (0x63) Reserved – – – – – – – – (0x62) Reserved – – – – – – – – (0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 37 (0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 53 0x3F (0x5F) SREG I T H S V N Z C 11 0x3E (0x5E) SPH – – – – – (SP10) 5. SP9 SP8 13 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13 0x3C (0x5C) Reserved – – – – – – – – 0x3B (0x5B) Reserved – – – – – – – – 0x3A (0x5A) Reserved – – – – – – – – 0x39 (0x59) Reserved – – – – – – – – 0x38 (0x58) Reserved – – – – – – – – 0x37 (0x57) SPMCSR SPMIE (RWWSB)5. – (RWWSRE)5. BLBSET PGWRT PGERS SELFPRGEN 283 0x36 (0x56) Reserved – – – – – – – – 0x35 (0x55) MCUCR – – – PUD – – IVSEL IVCE 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE 39 0x32 (0x52) Reserved – – – – – – – – 0x31 (0x51) Reserved – – – – – – – – 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 242 0x2F (0x4F) Reserved – – – – – – – – 0x2E (0x4E) SPDR SPI data register 170 0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 169 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 168 0x2B (0x4B) GPIOR2 General purpose I/O register 2 26 0x2A (0x4A) GPIOR1 General purpose I/O register 1 26 0x29 (0x49) Reserved – – – – – – – – 0x28 (0x48) OCR0B Timer/Counter0 output compare register B 0x27 (0x47) OCR0A Timer/Counter0 output compare register A 0x26 (0x46) TCNT0 Timer/Counter0 (8-bit) 0x25 (0x45) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 0x23 (0x43) GTCCR TSM – – – – – PSRASY PSRSYNC 139/160 0x22 (0x42) EEARH (EEPROM address register high byte) 5. 22 0x21 (0x41) EEARL EEPROM address register low byte 22 0x20 (0x40) EEDR EEPROM data register 22 0x1F (0x3F) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 22 0x1E (0x3E) GPIOR0 General purpose I/O register 0 26 0x1D (0x3D) EIMSK – – – – – – INT1 INT0 68 0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 68 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 346 2545T–AVR–05/11 ATmega48/88/168 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel ATmega48/88/168 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. Only valid for ATmega88/168 0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 158 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 136 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 0x14 (0x34) Reserved – – – – – – – – 0x13 (0x33) Reserved – – – – – – – – 0x12 (0x32) Reserved – – – – – – – – 0x11 (0x31) Reserved – – – – – – – – 0x10 (0x30) Reserved – – – – – – – – 0x0F (0x2F) Reserved – – – – – – – – 0x0E (0x2E) Reserved – – – – – – – – 0x0D (0x2D) Reserved – – – – – – – – 0x0C (0x2C) Reserved – – – – – – – – 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88 0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 87 0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 87 0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 87 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 87 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 87 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87 0x02 (0x22) Reserved – – – – – – – – 0x01 (0x21) Reserved – – – – – – – – 0x0 (0x20) Reserved – – – – – – – – Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 347 2545T–AVR–05/11 ATmega48/88/168 32. Instruction set summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two registers Rd ← Rd + Rr Z, C, N, V, H 1 ADC Rd, Rr Add with carry two registers Rd ← Rd + Rr + C Z, C, N, V, H 1 ADIW Rdl,K Add immediate to word Rdh:Rdl ← Rdh:Rdl + K Z, C, N, V, S 2 SUB Rd, Rr Subtract two registers Rd ← Rd - Rr Z, C, N, V, H 1 SUBI Rd, K Subtract constant from register Rd ← Rd - K Z, C, N, V, H 1 SBC Rd, Rr Subtract with carry two registers Rd ← Rd - Rr - C Z, C, N, V, H 1 SBCI Rd, K Subtract with carry constant from reg. Rd ← Rd - K - C Z, C, N, V, H 1 SBIW Rdl,K Subtract immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z, C, N, V, S 2 AND Rd, Rr Logical AND registers Rd ← Rd • Rr Z, N, V 1 ANDI Rd, K Logical AND register and constant Rd ← Rd • K Z, N, V 1 OR Rd, Rr Logical OR registers Rd ← Rd v Rr Z, N, V 1 ORI Rd, K Logical OR register and constant Rd ← Rd v K Z, N, V 1 EOR Rd, Rr Exclusive OR registers Rd ← Rd ⊕ Rr Z, N, V 1 COM Rd One’s complement Rd ← 0xFF − Rd Z, C, N, V 1 NEG Rd Two’s complement Rd ← 0x00 − Rd Z, C, N, V, H 1 SBR Rd,K Set bit(s) in register Rd ← Rd v K Z, N, V 1 CBR Rd,K Clear bit(s) in register Rd ← Rd • (0xFF - K) Z, N, V 1 INC Rd Increment Rd ← Rd + 1 Z, N, V 1 DEC Rd Decrement Rd ← Rd − 1 Z, N, V 1 TST Rd Test for zero or minus Rd ← Rd • Rd Z, N, V 1 CLR Rd Clear register Rd ← Rd ⊕ Rd Z, N, V 1 SER Rd Set register Rd ← 0xFF None 1 MUL Rd, Rr Multiply unsigned R1:R0 ← Rd x Rr Z, C 2 MULS Rd, Rr Multiply signed R1:R0 ← Rd x Rr Z, C 2 MULSU Rd, Rr Multiply signed with unsigned R1:R0 ← Rd x Rr Z, C 2 FMUL Rd, Rr Fractional multiply unsigned R1:R0 ← (Rd x Rr) << 1 Z, C 2 FMULS Rd, Rr Fractional multiply signed R1:R0 ← (Rd x Rr) << 1 Z, C 2 FMULSU Rd, Rr Fractional multiply signed with unsigned R1:R0 ← (Rd x Rr) << 1 Z, C 2 BRANCH INSTRUCTIONS RJMP k Relative jump PC ← PC + k + 1 None 2 IJMP Indirect jump to (Z) PC ← Z None 2 JMP(1) k Direct jump PC ← k None 3 RCALL k Relative subroutine call PC ← PC + k + 1 None 3 ICALL Indirect call to (Z) PC ← Z None 3 CALL(1) k Direct subroutine call PC ← k None 4 RET Subroutine return PC ← STACK None 4 RETI Interrupt return PC ← STACK I 4 CPSE Rd,Rr Compare, skip if equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N, V, C, H 1 CPC Rd,Rr Compare with carry Rd − Rr − C Z, N, V, C, H 1 CPI Rd,K Compare register with immediate Rd − K Z, N, V, C, H 1 SBRC Rr, b Skip if bit in register cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if bit in register is set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if bit in I/O register cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if bit in I/O register is set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if status flag set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if status flag cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if not equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if carry set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if carry cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if same or higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if greater or equal, signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if less than zero, signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if half carry flag set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if half carry flag cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T flag set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T flag cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if overflow flag is set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if overflow flag is cleared if (V = 0) then PC ← PC + k + 1 None 1/2 348 2545T–AVR–05/11 ATmega48/88/168 BRIE k Branch if interrupt enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if interrupt disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set bit in I/O register I/O(P,b) ← 1 None 2 CBI P,b Clear bit in I/O register I/O(P,b) ← 0 None 2 LSL Rd Logical shift left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z, C, N, V 1 LSR Rd Logical shift right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z, C, N, V 1 ROL Rd Rotate left through carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z, C, N, V 1 ROR Rd Rotate right through carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z, C, N, V 1 ASR Rd Arithmetic shift right Rd(n) ← Rd(n+1), n=0..6 Z, C, N, V 1 SWAP Rd Swap nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag set SREG(s) ← 1 SREG(s) 1 BCLR s Flag clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit store from register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to register Rd(b) ← T None 1 SEC Set carry C ← 1 C1 CLC Clear carry C ← 0 C 1 SEN Set negative flag N ← 1 N1 CLN Clear negative flag N ← 0 N 1 SEZ Set zero flag Z ← 1 Z1 CLZ Clear zero flag Z ← 0 Z 1 SEI Global interrupt enable I ← 1 I1 CLI Global interrupt disable I ← 0 I 1 SES Set signed test flag S ← 1 S1 CLS Clear signed test flag S ← 0 S 1 SEV Set Twos complement overflow V ← 1 V1 CLV Clear Twos complement overflow V ← 0 V 1 SET Set T in SREG T ← 1 T1 CLT Clear T in SREG T ← 0 T 1 SEH Set half carry flag in SREG H ← 1 H1 CLH Clear half carry flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move between registers Rd ← Rr None 1 MOVW Rd, Rr Copy register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load immediate Rd ← K None 1 LD Rd, X Load indirect Rd ← (X) None 2 LD Rd, X+ Load indirect and post-inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load indirect and pre-dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load indirect Rd ← (Y) None 2 LD Rd, Y+ Load indirect and post-inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load indirect and pre-dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load indirect with displacement Rd ← (Y + q) None 2 LD Rd, Z Load indirect Rd ← (Z) None 2 LD Rd, Z+ Load indirect and post-inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load indirect and pre-dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load indirect with displacement Rd ← (Z + q) None 2 LDS Rd, k Load direct from SRAM Rd ← (k) None 2 ST X, Rr Store indirect (X) ← Rr None 2 ST X+, Rr Store indirect and post-inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store indirect and pre-dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store indirect (Y) ← Rr None 2 ST Y+, Rr Store indirect and post-inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store indirect and pre-dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store indirect with displacement (Y + q) ← Rr None 2 ST Z, Rr Store indirect (Z) ← Rr None 2 ST Z+, Rr Store indirect and post-inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store indirect and pre-dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store indirect with displacement (Z + q) ← Rr None 2 STS k, Rr Store direct to SRAM (k) ← Rr None 2 LPM Load program memory R0 ← (Z) None 3 LPM Rd, Z Load program memory Rd ← (Z) None 3 LPM Rd, Z+ Load program memory and post-inc Rd ← (Z), Z ← Z+1 None 3 SPM Store program memory (Z) ← R1:R0 None - IN Rd, P In port Rd ← P None 1 OUT P, Rr Out port P ← Rr None 1 PUSH Rr Push register on stack STACK ← Rr None 2 Mnemonics Operands Description Operation Flags #Clocks 349 2545T–AVR–05/11 ATmega48/88/168 Note: 1. These instructions are only available in Atmel ATmega168. POP Rd Pop register from stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No operation None 1 SLEEP Sleep (See specific descr. for sleep function) None 1 WDR Watchdog reset (See specific descr. for WDR/timer) None 1 BREAK Break For on-chip debug only None N/A Mnemonics Operands Description Operation Flags #Clocks 350 2545T–AVR–05/11 ATmega48/88/168 33. Ordering information 33.1 Atmel ATmega48 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. See Figure 29-1 on page 305 and Figure 29-2 on page 305. 4. NiPdAu lead finish. 5. Tape & Reel. Speed (MHz) Power supply Ordering code(2) Package(1) Operational range 10(3) 1.8V - 5.5V ATmega48V-10AUR(5) ATmega48V-10MUR(5) ATmega48V-10AU ATmega48V-10MMU ATmega48V-10MMUR(5) ATmega48V-10MMH(4) ATmega48V-10MMHR(4)(5) ATmega48V-10MU ATmega48V-10PU 32A 32M1-A 32A 28M1 28M1 28M1 28M1 32M1-A 28P3 Industrial (-40°C to 85°C) 20(3) 2.7V - 5.5V ATmega48-20AUR(5) ATmega48-20MUR(5) ATmega48-20AU ATmega48-20MMU ATmega48-20MMUR(5) ATmega48-20MMH(4) ATmega48-20MMHR(4)(5) ATmega48-20MU ATmega48-20PU 32A 32M1-A 32A 28M1 28M1 28M1 28M1 32M1-A 28P3 Industrial (-40°C to 85°C) Package type 32A 32-lead, thin (1.0mm) plastic quad flat package (TQFP) 28M1 28-pad, 4 × 4 × 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (QFN/MLF) 32M1-A 32-pad, 5 × 5 × 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (QFN/MLF) 28P3 28-lead, 0.300” wide, plastic dual inline package (PDIP) 351 2545T–AVR–05/11 ATmega48/88/168 33.2 Atmel ATmega88 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. See Figure 29-1 on page 305 and Figure 29-2 on page 305. 4. Tape & reel Speed (MHz) Power supply Ordering code(2) Package(1) Operational range 10(3) 1.8V - 5.5V ATmega88V-10AUR(4) ATmega88V-10MUR(4) ATmega88V-10AU ATmega88V-10MU ATmega88V-10PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) 20(3) 2.7V - 5.5V ATmega88-20AUR(4) ATmega88-20MUR(4) ATmega88-20AU ATmega88-20MU ATmega88-20PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) Package type 32A 32-lead, thin (1.0mm) plastic quad flat package (TQFP) 32M1-A 32-pad, 5 × 5 × 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (QFN/MLF) 28P3 28-lead, 0.300” wide, plastic dual inline package (PDIP) 352 2545T–AVR–05/11 ATmega48/88/168 33.3 Atmel ATmega168 Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. See Figure 29-1 on page 305 and Figure 29-2 on page 305. 4. Tape & reel Speed (MHz)(3) Power supply Ordering code(2) Package(1) Operational range 10 1.8V - 5.5V ATmega168V-10AUR(4) ATmega168V-10MUR(4) ATmega168V-10AU ATmega168V-10MU ATmega168V-10PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) 20 2.7V - 5.5V ATmega168-20AUR(4) ATmega168-20MUR(4) ATmega168-20AU ATmega168-20MU ATmega168-20PU 32A 32M1-A 32A 32M1-A 28P3 Industrial (-40°C to 85°C) Package type 32A 32-lead, thin (1.0mm) plastic quad flat package (TQFP) 32M1-A 32-pad, 5 × 5 × 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (QFN/MLF) 28P3 28-lead, 0.300” wide, plastic dual inline package (PDIP) 353 2545T–AVR–05/11 ATmega48/88/168 34. Packaging information 34.1 32A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 32A, 32-lead, 7 x 7mm Body Size, 1.0mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 32A C 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 354 2545T–AVR–05/11 ATmega48/88/168 34.2 28M1 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com ZBV B 28M1 28M1, 28-pad, 4 x 4 x 1.0mm Body, Lead Pitch 0.45mm, 2.4 x 2.4mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) 10/24/08 SIDE VIEW Pin 1 ID BOTTOM VIEW TOP VIEW Note: The terminal #1 ID is a Laser-marked Feature. D E e K A1 C A D2 E2 y L 1 2 3 b 1 2 3 0.45 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C 0.20 REF D 3.95 4.00 4.05 D2 2.35 2.40 2.45 E 3.95 4.00 4.05 E2 2.35 2.40 2.45 e 0.45 L 0.35 0.40 0.45 y 0.00 – 0.08 K 0.20 – – R 0.20 0.4 Ref (4x) 355 2545T–AVR–05/11 ATmega48/88/168 34.3 32M1-A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm, 32M1-A E 5/25/06 3.10mm Exposed Pad, Micro Lead Frame Package (MLF) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D1 D E1 E b e A3 A2 A1 A D2 E2 0.08 C L 1 2 3 P P 0 1 2 3 A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 0.20 REF b 0.18 0.23 0.30 D D1 D2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4.80 4.70 4.75 4.80 4.90 5.00 5.10 E E1 E2 2.95 3.10 3.25 e 0.50 BSC L 0.30 0.40 0.50 P – – 0.60 – – 12o Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. TOP VIEW SIDE VIEW BOTTOM VIEW 0 Pin 1 ID Pin #1 Notch (0.20 R) K 0.20 – – K K 356 2545T–AVR–05/11 ATmega48/88/168 34.4 28P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual Inline Package (PDIP) 28P3 B 09/28/01 PIN 1 E1 A1 B REF E B1 C L SEATING PLANE A 0º ~ 15º D e eB B2 (4 PLACES) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.5724 A1 0.508 – – D 34.544 – 34.798 Note 1 E 7.620 – 8.255 E1 7.112 – 7.493 Note 1 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.160 e 2.540 TYP Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). 357 2545T–AVR–05/11 ATmega48/88/168 35. Errata 35.1 Errata Atmel ATmega48 The revision letter in this section refers to the revision of the ATmega48 device. 35.1.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 35.1.2 Rev. C • Reading EEPROM when system clock frequency is below 900kHz may not work • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Reading EEPROM when system clock frequency is below 900kHz may not work Reading Data from the EEPROM at system clock frequency below 900kHz may result in wrong data read. Problem fix/workaround Avoid using the EEPROM at clock frequency below 900kHz. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 35.1.3 Rev. B • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 358 2545T–AVR–05/11 ATmega48/88/168 35.1.4 Rev A • Part may hang in reset • Wrong values read after erase only operation • Watchdog timer interrupt disabled • Start-up time with crystal oscillator is higher than expected • High power consumption in power-down with external clock • Asynchronous oscillator does not stop in power-down • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Part may hang in reset Some parts may get stuck in a reset state when a reset signal is applied when the internal reset state-machine is in a specific state. The internal reset state-machine is in this state for approximately 10ns immediately before the part wakes up after a reset, and in a 10ns window when altering the system clock prescaler. The problem is most often seen during InSystem Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: - Two succeeding resets are applied where the second reset occurs in the 10ns window before the device is out of the reset-state caused by the first reset. - A reset is applied in a 10ns window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device. Problem fix/workaround The first case can be avoided during run-mode by ensuring that only one reset source is active. If an external reset push button is used, the reset start-up time should be selected such that the reset line is fully debounced during the start-up time. The second case can be avoided by not using the system clock prescaler. The third case occurs during In-System programming only. It is most frequently seen when using the internal RC at maximum frequency. If the device gets stuck in the reset-state, turn power off, then on again to get the device out of this state. 2. Wrong values read after erase only operation At supply voltages below 2.7V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem fix/workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 359 2545T–AVR–05/11 ATmega48/88/168 3. Watchdog timer interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout following an interrupt, the device works correctly. Problem fix/workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. 4. Start-up time with crystal oscillator is higher than expected The clock counting part of the start-up time is about two times higher than expected for all start-up periods when running on an external Crystal. This applies only when waking up by reset. Wake-up from power down is not affected. For most settings, the clock counting parts is a small fraction of the overall start-up time, and thus, the problem can be ignored. The exception is when using a very low frequency crystal like for instance a 32kHz clock crystal. Problem fix/workaround No known workaround. 5. High power consumption in power-down with external clock The power consumption in power down with an active external clock is about 10 times higher than when using internal RC or external oscillators. Problem fix/workaround Stop the external clock when the device is in power down. 6. Asynchronous oscillator does not stop in power-down The Asynchronous oscillator does not stop when entering power down mode. This leads to higher power consumption than expected. Problem fix/workaround Manually disable the asynchronous timer before entering power down. 7. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 360 2545T–AVR–05/11 ATmega48/88/168 35.2 Errata Atmel ATmega88 The revision letter in this section refers to the revision of the ATmega88 device. 35.2.1 Rev. D • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 35.2.2 Rev. B/C Not sampled. 35.2.3 Rev. A • Writing to EEPROM does not work at low operating voltages • Part may hang in reset • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Writing to EEPROM does not work at low operating voltages Writing to the EEPROM does not work at low voltages. Problem fix/workaround Do not write the EEPROM at voltages below 4.5 Volts. This will be corrected in rev. B. 2. Part may hang in reset Some parts may get stuck in a reset state when a reset signal is applied when the internal reset state-machine is in a specific state. The internal reset state-machine is in this state for approximately 10ns immediately before the part wakes up after a reset, and in a 10ns window when altering the system clock prescaler. The problem is most often seen during InSystem Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: - Two succeeding resets are applied where the second reset occurs in the 10ns window before the device is out of the reset-state caused by the first reset. - A reset is applied in a 10ns window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device. 361 2545T–AVR–05/11 ATmega48/88/168 Problem fix/workaround The first case can be avoided during run-mode by ensuring that only one reset source is active. If an external reset push button is used, the reset start-up time should be selected such that the reset line is fully debounced during the start-up time. The second case can be avoided by not using the system clock prescaler. The third case occurs during In-System programming only. It is most frequently seen when using the internal RC at maximum frequency. If the device gets stuck in the reset-state, turn power off, then on again to get the device out of this state. 3. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 35.3 Errata Atmel ATmega168 The revision letter in this section refers to the revision of the ATmega168 device. 35.3.1 Rev C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 35.3.2 Rev B • Part may hang in reset • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Part may hang in reset Some parts may get stuck in a reset state when a reset signal is applied when the internal reset state-machine is in a specific state. The internal reset state-machine is in this state for approximately 10ns immediately before the part wakes up after a reset, and in a 10ns window when altering the system clock prescaler. The problem is most often seen during InSystem Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: - Two succeeding resets are applied where the second reset occurs in the 10ns window before the device is out of the reset-state caused by the first reset. 362 2545T–AVR–05/11 ATmega48/88/168 - A reset is applied in a 10ns window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device. Problem fix/workaround The first case can be avoided during run-mode by ensuring that only one reset source is active. If an external reset push button is used, the reset start-up time should be selected such that the reset line is fully debounced during the start-up time. The second case can be avoided by not using the system clock prescaler. The third case occurs during In-System programming only. It is most frequently seen when using the internal RC at maximum frequency. If the device gets stuck in the reset-state, turn power off, then on again to get the device out of this state. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 35.3.3 Rev A • Wrong values read after erase only operation • Part may hang in reset • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Wrong values read after erase only operation At supply voltages below 2.7V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem fix/workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. Part may hang in reset Some parts may get stuck in a reset state when a reset signal is applied when the internal reset state-machine is in a specific state. The internal reset state-machine is in this state for approximately 10ns immediately before the part wakes up after a reset, and in a 10ns window when altering the system clock prescaler. The problem is most often seen during InSystem Programming of the device. There are theoretical possibilities of this happening also in run-mode. The following three cases can trigger the device to get stuck in a reset-state: 363 2545T–AVR–05/11 ATmega48/88/168 - Two succeeding resets are applied where the second reset occurs in the 10ns window before the device is out of the reset-state caused by the first reset. - A reset is applied in a 10ns window while the system clock prescaler value is updated by software. - Leaving SPI-programming mode generates an internal reset signal that can trigger this case. The two first cases can occur during normal operating mode, while the last case occurs only during programming of the device. Problem fix/workaround The first case can be avoided during run-mode by ensuring that only one reset source is active. If an external reset push button is used, the reset start-up time should be selected such that the reset line is fully debounced during the start-up time. The second case can be avoided by not using the system clock prescaler. The third case occurs during In-System programming only. It is most frequently seen when using the internal RC at maximum frequency. If the device gets stuck in the reset-state, turn power off, then on again to get the device out of this state. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem fix/workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 364 2545T–AVR–05/11 ATmega48/88/168 36. Datasheet revision history Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 Rev. 2545T-04/11 36.2 Rev. 2545S-07/10 36.3 Rev. 2545R-07/09 36.4 Rev. 2545Q-06/09 36.5 Rev. 2545P-02/09 1. Ordering information has been updated by removing AI and MI and added AUR and MUR (tape & reel). 2. Added and corrected cross references and short-cuts. 3. Document updated according to new Atmel standard. 4. QTouch Library Support Features 1. Note 6 and Note 7 in Table 29-5, “2-wire serial bus requirements.,” on page 308 have been removed. 2. Document updated according to Atmel standard. 1. Updated “Errata” on page 357. 2. Updated the last page with the Atmel new addresses. 1. Removed the heading “About”. The subsections of this sectionis now separate sections, “Resources”, “Data Retention” and “About Code Examples” 2. Updated “Ordering information” on page 350. 1. Removed Power-off slope rate from Table 29-3 on page 307. 365 2545T–AVR–05/11 ATmega48/88/168 36.6 Rev. 2545O-02/09 36.7 Rev. 2545N-01/09 36.8 Rev. 2545M-09/07 36.9 Rev. 2545L-08/07 36.10 Rev. 2545K-04/07 36.11 Rev. 2545J-12/06 1. Changed minimum Power-on Reset Threshold Voltage (falling) to 0.05V in Table 29- 3 on page 307. 2. Removed section “Power-on slope rate” from “System and reset characteristics” on page 307. 1. Updated “Features” on page 1 and added the note “Not recommended for new designs”. 2. Merged the sections Resources, Data Retention and About Code Examples under one common section, “Resources” on page 8. 3. Updated Figure 9-4 on page 35. 4. Updated “System clock prescaler” on page 36. 5. Updated “Alternate functions of port B” on page 78. 6. Added section “” on page 307. 7. Updated “Pin thresholds and hysteresis” on page 330. 1. Added “Data retention” on page 8. 2. Updated “ADC characteristics” on page 311. 3. “Preliminary“ removed through the datasheet. 1. Updated “Features” on page 1. 2. Updated code example in “MCUCR – MCU control register” on page 64. 3. Updated “System and reset characteristics” on page 307. 4. Updated Note in Table 9-3 on page 30, Table 9-5 on page 31, Table 9-8 on page 34, Table 9-10 on page 34. 1. Updated “Interrupts” on page 56. 2. Updated“Errata Atmel ATmega48” on page 357 . 3. Changed description in “Analog-to-digital converter” on page 244. 1. Updated “Features” on page 1. 366 2545T–AVR–05/11 ATmega48/88/168 36.12 Rev. 2545I-11/06 36.13 Rev. 2545H-10/06 36.14 Rev. 2545G-06/06 2. Updated Table 1-1 on page 2. 3. Updated “Ordering information” on page 350. 4. Updated “Packaging information” on page 353. 1. Updated “Features” on page 1. 2. Updated Features in “2-wire serial interface” on page 209. 3. Fixed typos in Table 29-3 on page 307. 1. Updated typos. 2. Updated “Features” on page 1. 3. Updated “Calibrated internal RC oscillator” on page 33. 4. Updated “System control and reset” on page 45. 5. Updated “Brown-out detection” on page 47. 6. Updated “Fast PWM mode” on page 121. 7. Updated bit description in “TCCR1C – Timer/Counter1 control register C” on page 133. 8. Updated code example in “SPI – Serial peripheral interface” on page 161. 9. Updated Table 15-3 on page 101, Table 15-6 on page 102, Table 15-8 on page 103, Table 16-2 on page 130, Table 16-3 on page 131, Table 16-4 on page 132, Table 18- 3 on page 154, Table 18-6 on page 155, Table 18-8 on page 156, and Table 28-5 on page 287. 10. Added Note to Table 26-1 on page 265, Table 27-5 on page 279, and Table 28-17 on page 300. 11. Updated “Setting the boot loader lock bits by SPM” on page 277. 12. Updated “Signature bytes” on page 288 13. Updated “Electrical characteristics” on page 303. 14. Updated “Errata” on page 357. 1. Added Addresses in Registers. 2. Updated “Calibrated internal RC oscillator” on page 33. 3. Updated Table 9-12 on page 35, Table 10-1 on page 39, Table 11-1 on page 54, Table 14-3 on page 78. 4. Updated “ADC noise reduction mode” on page 40. 5. Updated note for Table 10-2 on page 43. 6. Updatad “Bit 2 - PRSPI: Power reduction serial peripheral interface” on page 44. 7. Updated “TCCR0B – Timer/counter control register B” on page 104. 8. Updated “Fast PWM mode” on page 121. 9. Updated “Asynchronous operation of Timer/Counter2” on page 151. 10. Updated “SPI – Serial peripheral interface” on page 161. 367 2545T–AVR–05/11 ATmega48/88/168 36.15 Rev. 2545F-05/05 36.16 Rev. 2545E-02/05 36.17 Rev. 2545D-07/04 11. Updated “UCSRnA – USART MSPIM control and status register n A” on page 206. 12. Updated note in “Bit rate generator unit” on page 216. 13. Updated “Bit 6 – ACBG: Analog comparator bandgap select” on page 242. 14. Updated Features in “Analog-to-digital converter” on page 244. 15. Updated “Prescaling and conversion timing” on page 247. 16. Updated “Limitations of debugWIRE” on page 261. 17 Added Table 29-1 on page 306. 18. Updated Figure 16-7 on page 122, Figure 30-45 on page 339. 19. Updated rev. A in “Errata Atmel ATmega48” on page 357. 20. Added rev. C and D in “Errata Atmel ATmega48” on page 357. 1. Added Section 3. “Resources” on page 8 2. Update Section 9.6 “Calibrated internal RC oscillator” on page 33. 3. Updated Section 28.8.3 “Serial programming instruction set” on page 300. 4. Table notes in Section 29.2 “DC characteristics” on page 303 updated. 5. Updated Section 35. “Errata” on page 357. 1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. 2. Updated “EECR – The EEPROM control register” on page 22. 3. Updated “Calibrated internal RC oscillator” on page 33. 4. Updated “External clock” on page 35. 5. Updated Table 29-3 on page 307, Table 29-6 on page 309, Table 29-2 on page 306 and Table 28-16 on page 300 6. Added “Pin change interrupt timing” on page 66 7. Updated “8-bit timer/counter block diagram.” on page 90. 8. Updated “SPMCSR – Store program memory control and status register” on page 267. 9. Updated “Enter programming mode” on page 291. 10. Updated “DC characteristics” on page 303. 11. Updated “Ordering information” on page 350. 12. Updated “Errata Atmel ATmega88” on page 360 and “Errata Atmel ATmega168” on page 361. 1. Updated instructions used with WDTCSR in relevant code examples. 2. Updated Table 9-5 on page 31, Table 29-4 on page 307, Table 27-9 on page 282, and Table 27-11 on page 283. 3. Updated “System clock prescaler” on page 36. 368 2545T–AVR–05/11 ATmega48/88/168 36.18 Rev. 2545C-04/04 36.19 Rev. 2545B-01/04 4. Moved “TIMSK2 – Timer/Counter2 interrupt mask register” on page 158 and “TIFR2 – Timer/Counter2 interrupt flag register” on page 158 to “Register description” on page 153. 5. Updated cross-reference in “Electrical interconnection” on page 210. 6. Updated equation in “Bit rate generator unit” on page 216. 7. Added “Page size” on page 289. 8. Updated “Serial programming algorithm” on page 299. 9. Updated Ordering Information for “Atmel ATmega168” on page 352. 10. Updated “Errata Atmel ATmega88” on page 360 and “Errata Atmel ATmega168” on page 361. 11. Updated equation in “Bit rate generator unit” on page 216. 1. Speed Grades changed: 12MHz to 10MHz and 24MHz to 20MHz 2. Updated “Speed grades” on page 305. 3. Updated “Ordering information” on page 350. 4. Updated “Errata Atmel ATmega88” on page 360. 1. Added PDIP to “I/O and Packages”, updated “Speed Grade” and Power Consumption Estimates in 36.“Features” on page 1. 2. Updated “Stack pointer” on page 13 with RAMEND as recommended Stack Pointer value. 3. Added section “Power reduction register” on page 41 and a note regarding the use of the PRR bits to 2-wire, Timer/Counters, USART, Analog Comparator and ADC sections. 4. Updated “Watchdog timer” on page 49. 5. Updated Figure 16-2 on page 130 and Table 16-3 on page 131. 6. Extra Compare Match Interrupt OCF2B added to features in section “8-bit Timer/Counter2 with PWM and asynchronous operation” on page 140 7. Updated Table 10-1 on page 39, Table 24-5 on page 259, Table 28-4 to Table 28-7 on page 286 to 288 and Table 24-1 on page 249. Added note 2 to Table 28-1 on page 285. Fixed typo in Table 13-1 on page 67. 8. Updated whole “Typical characteristics” on page 315. 9. Added item 2 to 5 in “Errata Atmel ATmega48” on page 357. 10. Renamed the following bits: - SPMEN to SELFPRGEN - PSR2 to PSRASY - PSR10 to PSRSYNC - Watchdog Reset to Watchdog System Reset 11. Updated C code examples containing old IAR syntax. 12. Updated BLBSET description in “SPMCSR – Store program memory control and status register” on page 283. i 2545T–AVR–05/11 ATmega48/88/168 Table of contents Features ..................................................................................................... 1 1 Pin configurations ................................................................................... 2 1.1Pin descriptions .........................................................................................................3 2 Overview ................................................................................................... 5 2.1Block diagram ............................................................................................................5 2.2Comparison between Atmel ATmega48, Atmel ATmega88, and Atmel ATmega168 . 6 3 Resources ................................................................................................. 8 4 Data retention ........................................................................................... 8 5 About code examples .............................................................................. 8 6 Capacitive touch sensing ........................................................................ 8 7 AVR CPU core .......................................................................................... 9 7.1Overview ...................................................................................................................9 7.2Architectural overview ...............................................................................................9 7.3ALU – Arithmetic Logic Unit ....................................................................................10 7.4Status register .........................................................................................................11 7.5General purpose register file ...................................................................................12 7.6Stack pointer ...........................................................................................................13 7.7Instruction execution timing .....................................................................................14 7.8Reset and interrupt handling ...................................................................................15 8 AVR memories ....................................................................................... 17 8.1Overview .................................................................................................................17 8.2In-system reprogrammable flash program memory .................................................17 8.3SRAM data memory ................................................................................................19 8.4EEPROM data memory ...........................................................................................20 8.5I/O memory ..............................................................................................................21 8.6Register description .................................................................................................22 9 System clock and clock options .......................................................... 27 9.1Clock systems and their distribution ........................................................................27 9.2Clock sources ..........................................................................................................28 9.3Low power crystal oscillator ....................................................................................29 9.4Full swing crystal oscillator ......................................................................................31 ii 2545T–AVR–05/11 ATmega48/88/168 9.5Low frequency crystal oscillator ..............................................................................33 9.6Calibrated internal RC oscillator ..............................................................................33 9.7128kHz internal oscillator ........................................................................................34 9.8External clock ..........................................................................................................35 9.9Clock output buffer ..................................................................................................35 9.10Timer/counter oscillator .........................................................................................36 9.11System clock prescaler .........................................................................................36 9.12Register description ...............................................................................................37 10 Power management and sleep modes ................................................. 39 10.1Sleep modes .........................................................................................................39 10.2Idle mode ...............................................................................................................39 10.3ADC noise reduction mode ...................................................................................40 10.4Power-down mode ................................................................................................40 10.5Power-save mode .................................................................................................40 10.6Standby mode .......................................................................................................41 10.7Power reduction register .......................................................................................41 10.8Minimizing power consumption .............................................................................41 10.9Register description ...............................................................................................43 11 System control and reset ...................................................................... 45 11.1Resetting the AVR .................................................................................................45 11.2Reset sources .......................................................................................................45 11.3Power-on reset ......................................................................................................46 11.4External reset ........................................................................................................47 11.5Brown-out detection ..............................................................................................47 11.6Watchdog system reset .........................................................................................48 11.7Internal voltage reference ......................................................................................48 11.8Watchdog timer .....................................................................................................49 11.9Register description ...............................................................................................53 12 Interrupts ................................................................................................ 56 12.1Overview ...............................................................................................................56 12.2Interrupt vectors in ATmega48 ..............................................................................56 12.3Interrupt vectors in Atmel ATmega88 ....................................................................58 12.4Interrupt vectors in Atmel ATmega168 ..................................................................61 12.5Register description ...............................................................................................64 13 External interrupts ................................................................................. 66 iii 2545T–AVR–05/11 ATmega48/88/168 13.1Pin change interrupt timing ....................................................................................66 13.2Register description ...............................................................................................67 14 I/O-ports .................................................................................................. 71 14.1Overview ...............................................................................................................71 14.2Ports as general digital I/O ....................................................................................72 14.3Alternate port functions .........................................................................................76 14.4Register description ...............................................................................................87 15 8-bit Timer/Counter0 with PWM ............................................................ 89 15.1Features ................................................................................................................89 15.2Overview ...............................................................................................................89 15.3Timer/counter clock sources .................................................................................91 15.4Counter unit ...........................................................................................................91 15.5Output compare unit ..............................................................................................92 15.6Compare match output unit ...................................................................................93 15.7Modes of operation ................................................................................................94 15.8Timer/counter timing diagrams ..............................................................................99 15.9Register description .............................................................................................101 16 16-bit Timer/Counter1 with PWM ........................................................ 108 16.1Features ..............................................................................................................108 16.2Overview .............................................................................................................108 16.3Accessing 16-bit registers ...................................................................................110 16.4Timer/counter clock sources ...............................................................................113 16.5Counter unit .........................................................................................................114 16.6Input capture unit .................................................................................................115 16.7Output compare units ..........................................................................................116 16.8Compare match output unit .................................................................................118 16.9Modes of operation ..............................................................................................119 16.10Timer/counter timing diagrams ..........................................................................127 16.11Register description ...........................................................................................130 17 Timer/Counter0 and Timer/Counter1 prescalers .............................. 137 17.1Register description .............................................................................................139 18 8-bit Timer/Counter2 with PWM and asynchronous operation ........ 140 18.1Features ..............................................................................................................140 18.2Overview .............................................................................................................140 iv 2545T–AVR–05/11 ATmega48/88/168 18.3Timer/counter clock sources ...............................................................................141 18.4Counter unit .........................................................................................................141 18.5Output compare unit ............................................................................................142 18.6Compare match output unit .................................................................................144 18.7Modes of operation ..............................................................................................145 18.8Timer/counter timing diagrams ............................................................................149 18.9Asynchronous operation of Timer/Counter2 ........................................................151 18.10Timer/counter prescaler ....................................................................................152 18.11Register description ...........................................................................................153 19 SPI – Serial peripheral interface ......................................................... 161 19.1Features ..............................................................................................................161 19.2Overview .............................................................................................................161 19.3SS pin functionality ..............................................................................................166 19.4Data modes .........................................................................................................166 19.5Register description .............................................................................................168 20 USART0 ................................................................................................. 171 20.1Features ..............................................................................................................171 20.2Overview .............................................................................................................171 20.3Clock generation .................................................................................................172 20.4Frame formats .....................................................................................................175 20.5USART initialization .............................................................................................176 20.6Data transmission – The USART transmitter ......................................................179 20.7Data reception – The USART receiver ................................................................181 20.8Asynchronous data reception ..............................................................................185 20.9Multi-processor communication mode .................................................................188 20.10Register description ...........................................................................................190 20.11Examples of baud rate setting ...........................................................................194 21 USART in SPI mode ............................................................................. 199 21.1Features ..............................................................................................................199 21.2Overview .............................................................................................................199 21.3Clock generation .................................................................................................199 21.4SPI data modes and timing .................................................................................200 21.5Frame formats .....................................................................................................201 21.6Data transfer ........................................................................................................203 21.7AVR USART MSPIM vs. AVR SPI ......................................................................205 v 2545T–AVR–05/11 ATmega48/88/168 21.8Register description .............................................................................................206 22 2-wire serial interface .......................................................................... 209 22.1Features ..............................................................................................................209 22.22-wire serial interface bus definition ....................................................................209 22.3Data transfer and frame format ...........................................................................210 22.4Multi-master bus systems, arbitration and synchronization .................................213 22.5Overview of the TWI module ...............................................................................216 22.6Using the TWI ......................................................................................................218 22.7Transmission modes ...........................................................................................222 22.8Multi-master systems and arbitration ...................................................................235 22.9Register description .............................................................................................236 23 Analog comparator .............................................................................. 241 23.1Overview .............................................................................................................241 23.2Analog comparator multiplexed input ..................................................................241 23.3Register description .............................................................................................242 24 Analog-to-digital converter ................................................................. 244 24.1Features ..............................................................................................................244 24.2Overview .............................................................................................................244 24.3Starting a conversion ...........................................................................................246 24.4Prescaling and conversion timing ........................................................................247 24.5Changing channel or reference selection ............................................................249 24.6ADC noise canceler .............................................................................................250 24.7ADC conversion result .........................................................................................255 24.8Register description .............................................................................................255 25 debugWIRE on-chip debug system .................................................... 260 25.1Features ..............................................................................................................260 25.2Overview .............................................................................................................260 25.3Physical interface ................................................................................................260 25.4Software break points ..........................................................................................261 25.5Limitations of debugWIRE ...................................................................................261 25.6Register description .............................................................................................261 26 Self-programming the flash, Atmel ATmega48 ................................. 262 26.1Overview .............................................................................................................262 26.2Addressing the flash during self-programming ....................................................263 vi 2545T–AVR–05/11 ATmega48/88/168 26.3Register description .............................................................................................267 27 Boot loader support – Read-while-write self-programming, Atmel ATmega88 and Atmel ATmega168 269 27.1Features ..............................................................................................................269 27.2Overview .............................................................................................................269 27.3Application and boot loader flash sections ..........................................................269 27.4Read-while-write and no read-while-write flash sections .....................................270 27.5Boot loader lock bits ............................................................................................272 27.6Entering the boot loader program ........................................................................273 27.7Addressing the flash during self-programming ....................................................274 27.8Self-programming the flash .................................................................................275 27.9Register description .............................................................................................283 28 Memory programming ......................................................................... 285 28.1Program and data memory lock bits ....................................................................285 28.2Fuse bits ..............................................................................................................286 28.3Signature bytes ...................................................................................................288 28.4Calibration byte ...................................................................................................288 28.5Page size .............................................................................................................289 28.6Parallel programming parameters, pin mapping, and commands .......................289 28.7Parallel programming ..........................................................................................291 28.8Serial downloading ..............................................................................................298 29 Electrical characteristics ..................................................................... 303 29.1Absolute maximum ratings* .................................................................................303 29.2DC characteristics ...............................................................................................303 29.3Speed grades ......................................................................................................305 29.4Clock characteristics ...........................................................................................306 29.5System and reset characteristics ........................................................................307 29.62-wire serial interface characteristics ..................................................................308 29.7SPI timing characteristics ....................................................................................309 29.8ADC characteristics .............................................................................................311 29.9Parallel programming characteristics ..................................................................312 30 Typical characteristics ........................................................................ 315 30.1Active supply current ...........................................................................................315 30.2Idle supply current ...............................................................................................318 30.3Supply current of I/O modules .............................................................................321 vii 2545T–AVR–05/11 ATmega48/88/168 30.4Power-down supply current .................................................................................323 30.5Power-save supply current ..................................................................................324 30.6Standby supply current ........................................................................................324 30.7Pin pull-up ...........................................................................................................325 30.8Pin driver strength ...............................................................................................327 30.9Pin thresholds and hysteresis .............................................................................330 30.10BOD thresholds and analog comparator offset .................................................333 30.11Internal oscillator speed ....................................................................................336 30.12Current consumption of peripheral units ...........................................................338 30.13Current consumption in reset and reset pulse width .........................................341 31 Register summary ................................................................................ 343 32 Instruction set summary ..................................................................... 347 33 Ordering information ........................................................................... 350 33.1Atmel ATmega48 .................................................................................................350 33.2Atmel ATmega88 .................................................................................................351 33.3Atmel ATmega168 ...............................................................................................352 34 Packaging information ........................................................................ 353 34.132A ......................................................................................................................353 34.228M1 ...................................................................................................................354 34.332M1-A ................................................................................................................355 34.428P3 ....................................................................................................................356 35 Errata ..................................................................................................... 357 35.1Errata Atmel ATmega48 ......................................................................................357 35.2Errata Atmel ATmega88 ......................................................................................360 35.3Errata Atmel ATmega168 ....................................................................................361 36 Datasheet revision history .................................................................. 364 36.1Rev. 2545T-04/11 ................................................................................................364 36.2Rev. 2545S-07/10 ...............................................................................................364 36.3Rev. 2545R-07/09 ...............................................................................................364 36.4Rev. 2545Q-06/09 ...............................................................................................364 36.5Rev. 2545P-02/09 ...............................................................................................364 36.6Rev. 2545O-02/09 ...............................................................................................365 36.7Rev. 2545N-01/09 ...............................................................................................365 36.8Rev. 2545M-09/07 ...............................................................................................365 viii 2545T–AVR–05/11 ATmega48/88/168 36.9Rev. 2545L-08/07 ................................................................................................365 36.10Rev. 2545K-04/07 .............................................................................................365 36.11Rev. 2545J-12/06 ..............................................................................................365 36.12Rev. 2545I-11/06 ...............................................................................................366 36.13Rev. 2545H-10/06 .............................................................................................366 36.14Rev. 2545G-06/06 .............................................................................................366 36.15Rev. 2545F-05/05 ..............................................................................................367 36.16Rev. 2545E-02/05 .............................................................................................367 36.17Rev. 2545D-07/04 .............................................................................................367 36.18Rev. 2545C-04/04 .............................................................................................368 36.19Rev. 2545B-01/04 .............................................................................................368 Table of contents ....................................................................................... i 2545T–AVR–05/11 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81)(3) 3523-3551 Fax: (+81)(3) 3523-7581 © 2011 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 1. General description The 74HC125; 74HCT125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Complies with JEDEC standard no. 7A  Input levels:  The 74HC125: CMOS levels  The 74HCT125: TTL levels  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information 74HC125; 74HCT125 Quad buffer/line driver; 3-state Rev. 5 — 19 January 2015 Product data sheet Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC125N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HCT125N 74HC125D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HCT125D 74HC125DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HCT125DB 74HC125PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT125PW 74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 — 19 January 2015 2 of 17 NXP Semiconductors 74HC125; 74HCT125 Quad buffer/line driver; 3-state 4. Functional diagram 5. Pinning information 5.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) PQD  $ <   2(  $ <   2(  $ <   2(  $ <   2( PQD  (1             PQD Q2( Q$ Q< Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 +& +&7 2( 9&& $ 2( < $ 2( < $ 2( < $ *1' <               DDD 74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 — 19 January 2015 3 of 17 NXP Semiconductors 74HC125; 74HCT125 Quad buffer/line driver; 3-state 5.2 Pin description 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. Table 2. Pin description Symbol Pin Description 1OE, 2OE, 3OE, 4OE 1, 4, 10, 13 output enable input (active LOW) 1A, 2A, 3A, 4A 2, 5, 9, 12 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage Table 3. Function table[1] Control Input Output nOE nA nY LLL H H HXZ Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 35 mA ICC supply current - +70 mA IGND ground current - 70 mA Tstg storage temperature 65 +150 C Ptot total power dissipation [2] DIP14 package - 750 mW SO14 and (T)SSOP14 packages - 500 mW 74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 — 19 January 2015 4 of 17 NXP Semiconductors 74HC125; 74HCT125 Quad buffer/line driver; 3-state 8. Recommended operating conditions 9. Static characteristics Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC125 74HCT125 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 -VCC V VO output voltage 0 - VCC 0 -VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC125 VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - 0.5 - 5.0 - 10.0 A 74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 — 19 January 2015 5 of 17 NXP Semiconductors 74HC125; 74HCT125 Quad buffer/line driver; 3-state ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - pF 74HCT125 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 6 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current per input pin; VI = VCC  2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 100 360 - 450 - 490 A CI input capacitance - 3.5 - pF Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 — 19 January 2015 6 of 17 NXP Semiconductors 74HC125; 74HCT125 Quad buffer/line driver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC125 tpd propagation delay nA to nY; see Figure 5 [1] VCC = 2.0 V - 30 100 - 125 - 150 ns VCC = 4.5 V - 11 20 - 25 - 30 ns VCC = 5 V; CL = 15 pF - 9 - - - - - ns VCC = 6.0 V - 9 17 - 21 - 26 ns ten enable time nOE to nY; see Figure 6 [2] VCC = 2.0 V - 41 125 - 155 - 190 ns VCC = 4.5 V - 15 25 - 31 - 38 ns VCC = 6.0 V - 12 21 - 26 - 32 ns tdis disable time nOE to nY; see Figure 6 [3] VCC = 2.0 V - 41 125 - 155 - 190 ns VCC = 4.5 V - 15 25 - 31 - 38 ns VCC = 6.0 V - 12 21 - 26 - 32 ns tt transition time nY; see Figure 5 [4] VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [5] - 22 - - - - - pF 74HC_HCT125 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 — 19 January 2015 7 of 17 NXP Semiconductors 74HC125; 74HCT125 Quad buffer/line driver; 3-state [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 11. Waveforms 74HCT125 tpd propagation delay nA to nY; see Figure 5 [1] VCC = 4.5 V - 15 25 - 31 - 38 ns VCC = 5 V; CL = 15 pF - 12 - - - - - ns ten enable time nOE to nY; see Figure 6 [2] VCC = 4.5 V - 15 28 - 35 - 42 ns tdis disable time nOE to nY; see Figure 6 [3] VCC = 4.5 V - 15 25 - 31 - 38 ns tt transition time nY; see Figure 5 [4] - 5 12 - 15 - 18 ns CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC  1.5 V [5] - 24 - - - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (nA) to output (nY)   Q$LQSXW Q VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 35 mA ICC supply current - +70 mA IGND ground current - 70 mA Tstg storage temperature 65 +150 C Ptot total power dissipation DIP20 package [1] - 750 mW SO20, SSOP20, TSSOP20 and DHVQFN20 packages [2] - 500 mW 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 6 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 8. Recommended operating conditions 9. Static characteristics Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC573 74HCT573 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 -VCC V VO output voltage 0 - VCC 0 -VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC573 VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - 0.5 - 5.0 - 10.0 A 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 7 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - pF 74HCT573 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 6 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO =0A - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO =0A per input pin; Dn inputs - 35 126 - 158 - 172 A per input pin; LE input - 65 234 - 293 - 319 A per input pin; OE input - 125 450 - 563 - 613 A CI input capacitance - 3.5 - - - - - pF Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 8 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC573 tpd propagation delay Dn to Qn; see Figure 7 [1] VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns tpd propagation delay LE to Qn; see Figure 8 [1] VCC = 2.0 V - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns ten enable time OE to Qn; see Figure 9 [2] VCC = 2.0 V - 44 140 - 175 - 210 ns VCC = 4.5 V - 16 28 - 35 - 42 ns VCC = 6.0 V - 13 24 - 30 - 36 ns tdis disable time OE to Qn; see Figure 9 [3] VCC = 2.0 V - 55 150 - 190 - 225 ns VCC = 4.5 V - 20 30 - 38 - 45 ns VCC = 6.0 V - 16 26 - 33 - 38 ns tt transition time Qn; see Figure 7 [4] VCC = 2.0 V - 14 60 - 75 - 90 ns VCC = 4.5 V - 5 12 - 15 - 18 ns VCC = 6.0 V - 4 10 - 13 - 15 ns tW pulse width LE HIGH; see Figure 8 VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns tsu set-up time Dn to LE; see Figure 10 VCC = 2.0 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6.0 V 9 3 - 11 - 13 - ns th hold time Dn to LE; see Figure 10 VCC = 2.0 V 5 3 - 5 - 5 - ns VCC = 4.5 V 5 1 - 5 - 5 - ns VCC = 6.0 V 5 1 - 5 - 5 - ns CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC [5] - 26 - - - - - pF 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 9 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state [1] tpd is the same as tPLH and tPHL. [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 74HCT573 tpd propagation delay Dn to Qn; see Figure 7 [1] VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 17 - - - - - ns tpd propagation delay LE to Qn; see Figure 8 [1] VCC = 4.5 V - 18 35 - 44 - 53 ns VCC = 5 V; CL = 15 pF - 15 - - - - - ns ten enable time OE to Qn; see Figure 9 [2] VCC = 4.5 V - 17 30 - 38 - 45 ns tdis disable time OE to Qn; see Figure 9 [3] VCC = 4.5 V - 18 30 - 38 - 45 ns tt transition time Qn; see Figure 7 [4] VCC = 4.5 V - 5 12 - 15 - 18 ns tW pulse width LE HIGH; see Figure 8 VCC = 4.5 V 16 5 - 20 - 24 - ns tsu set-up time Dn to LE; see Figure 10 VCC = 4.5 V 13 7 - 16 - 20 - ns th hold time Dn to LE; see Figure 10 VCC = 4.5 V 9 4 - 11 - 15 - ns CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; VI = GND to VCC  1.5 V [5] - 26 - - - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 10 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 11. Waveforms Measurement points are given in Table 8. Fig 7. Propagation delay data input (Dn) to output (Qn) and output transition time DDH 'QLQSXW 4QRXWSXW 90 W3/+ W3+/ W7/+ W7+/ 90   Measurement points are given in Table 8. Fig 8. Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output transition time 90 90 W3+/ W3/+ W: /(LQSXW 4QRXWSXW DDH W7+/ W7/+   74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 11 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Enable and disable times DDH W3/= W3+= RXWSXWV GLVDEOHG RXWSXWV HQDEOHG   RXWSXWV HQDEOHG RXWSXW /2:WR2)) 2))WR/2: RXWSXW +,*+WR2)) 2))WR+,*+ 2(LQSXW 9, 92/ 92+ 9&& 90 *1' *1' W3=/ W3=+ 90 90 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 10. Set-up and hold times for data input (Dn) to latch input (LE) DDH /(LQSXW 90 'QLQSXW 90 WK WVX WK WVX Table 8. Measurement points Type Input Output VM VM 74HC573 0.5VCC 0.5VCC 74HCT573 1.3 V 1.3 V 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 12 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 11. Test circuit for measuring switching times 90 90 W: W:   9 9, 9, QHJDWLYH SXOVH SRVLWLYH SXOVH 9 90 90   WI WU WU WI DDG '87 9&& 9&& 9, 92 57 5/ 6 &/ RSHQ * Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC573 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT573 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 13 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 12. Package outline Fig 12. Package outline SOT146-1 (DIP20) 81,7 $ PD[   E F ' ( H / 0+ 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP LQFKHV ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 627   $ PLQ $ PD[ E = PD[ H 0( Z                                               06 6& 0+ F H  0( $ / VHDWLQJSODQH $ Z 0 E H ' $ =     E ( SLQLQGH[   PP VFDOH 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG    ',3SODVWLFGXDOLQOLQHSDFNDJHOHDGV PLO 627 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 14 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Fig 13. Package outline SOT163-1 (SO20) 81,7 $ PD[ $ $ $ ES F '  (   H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP LQFKHV                       R R   ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG   627   Z 0 ES GHWDLO; = H   ' \  ( 06 SLQLQGH[                                PP VFDOH ; ș $ $ $ +( /S 4 ( F / Y 0 $ $  $ 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627   74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 15 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Fig 14. Package outline SOT339-1 (SSOP20) 81,7 $ $ $ ES F '  (  H +( / /S 4  Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP                      R     R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG   627 02   ; Z 0 ș $ $ $ ES ' +( /S 4 GHWDLO; ( = H F / Y 0 $ $  $     \  SLQLQGH[   PP VFDOH 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 $ PD[  74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 16 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Fig 15. Package outline SOT360-1 (TSSOP20) 81,7 $ $ $ ES F '  (   H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP                      R     R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG   627 02   Z 0 ES ' = H      SLQLQGH[ ș $ $ $ /S 4 GHWDLO; / $  +( ( F Y 0 $ ; $ \   PP VFDOH 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 $ PD[  74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 17 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Fig 16. Package outline SOT764-1 (DHVQFN20) 2XWOLQH 5HIHUHQFHV YHUVLRQ (XURSHDQ SURMHFWLRQ ,VVXHGDWH ,(& -('(& -(,7$ 627  02  VRWBSR   8QLW PP PD[ QRP PLQ         $  'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG $ E  F '  'K (  (K  H H /  Y Z  \ \                    GHWDLO; % $ H H H & \ & \ ; Y & % $ Z & VFDOH $ $ F / (K 'K E         ' ( WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD    PP '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 18 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 13. Abbreviations 14. Revision history Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT573 v.6 20150126 Product data sheet - 74HC_HCT573 v.5 Modifications: • Table 7: Power dissipation capacitance condition for 74HCT573 is corrected. 74HC_HCT573 v.5 20120815 Product data sheet - 74HC_HCT573 v.4 Modifications: • Alternative descriptive title corrected (errata). 74HC_HCT573 v.4 20120806 Product data sheet - 74HC_HCT573 v.3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT573 v.3 20060117 Product data sheet - 74HC_HCT573_CNV v.2 74HC_HCT573_CNV v.2 19901201 Product specification - - 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 19 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state 15. Legal information 15.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 74HC_HCT573 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 26 January 2015 20 of 21 NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors 74HC573; 74HCT573 Octal D-type transparent latch; 3-state © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 January 2015 Document identifier: 74HC_HCT573 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16 Contact information. . . . . . . . . . . . . . . . . . . . . 20 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1. General description The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output pulse width control by three methods: 1. The basic pulse is programmed by selection of an external resistor (REXT) and capacitor (CEXT). 2. Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering. 3. An internal connection from nRD to the input gates makes it possible to trigger the circuit by a HIGH-going signal at input nRD as shown in Table 3. Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower input rise and fall times. The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered via the reset input. 2. Features and benefits  DC triggered from active HIGH or active LOW inputs  Retriggerable for very long pulses up to 100 % duty factor  Direct reset terminates output pulse  Schmitt-trigger action on all inputs except for the reset input  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Specified from 40 C to +85 C and from 40 C to +125 C 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Rev. 9 — 19 January 2015 Product data sheet 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 2 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 3. Ordering information 4. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC123N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT123N 74HC123D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT123D 74HC123DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT123DB 74HC123PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT123PW 74HC123BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm SOT763-1 Fig 1. Functional diagram 4 4 5' 5' 6  5(;7&(;7  &(;7  4 4   DDD 5' $  $  %    % 7 4 5' 6 5(;7&(;7  &(;7  4  4 4  7 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 3 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Fig 2. Logic symbol Fig 3. IEC logic symbol 4 4 5' 5' 6 5(;7&(;7   5(;7&(;7  &(;7  &(;7  4  4 4  4   PQD 5' $  $  %    % 7 PQD &;    5&; 5     &;    5&; 5     Fig 4. Logic diagram PQD Q5(;7&(;7 9&& 9&& 9&& 5 Q5' Q$ Q% 5 &/ &/ &/ &/ &/ Q4 5 Q4 5 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 4 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 5. Pinning information 5.1 Pinning 5.2 Pin description (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to VCC. Fig 5. Pin configuration for DIP16, SO16, SSOP16 and TSSOP16 Fig 6. Pin configuration for DHVQFN16 +& +&7 $ 9&& % 5(;7&(;7 5' &(;7 4 4 4 4 &(;7 5' 5(;7&(;7 % *1' $ DDD                 DDI +& 5(;7&(;7 % &(;7 5' 4 4 4 4 5' &(;7 % 5(;7&(;7 *1'$ $ 9&& 7UDQVSDUHQWWRSYLHZ                 WHUPLQDO LQGH[DUHD 9&&  Table 2. Pin description Symbol Pin Description 1A 1 negative-edge triggered input 1 1B 2 positive-edge triggered input 1 1RD 3 direct reset LOW and positive-edge triggered input 1 1Q 4 active LOW output 1 2Q 5 active HIGH output 2 2CEXT 6 external capacitor connection 2 2REXT/CEXT 7 external resistor and capacitor connection 2 GND 8 ground (0 V) 2A 9 negative-edge triggered input 2 2B 10 positive-edge triggered input 2 2RD 11 direct reset LOW and positive-edge triggered input 2 2Q 12 active LOW output 2 1Q 13 active HIGH output 1 1CEXT 14 external capacitor connection 1 1REXT/CEXT 15 external resistor and capacitor connection 1 VCC 16 supply voltage 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 5 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH transition;  = HIGH-to-LOW transition; = one HIGH level output pulse; = one LOW level output pulse. [2] If the monostable was triggered before this condition was established, the pulse will continue as programmed. 7. Limiting values [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. [3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C. Table 3. Function table[1] Input Output nRD nA nB nQ nQ LXXLH XHXL[2] H[2] XXLL[2] H[2] H L  H  H  L H Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current except for pins nREXT/CEXT; VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC supply current - 50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C Ptot total power dissipation DIP16 package [1] - 750 mW SO16 package [2] - 500 mW SSOP16 package [3] - 500 mW TSSOP16 package [3] - 500 mW DHVQFN16 package [4] - 500 mW 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 6 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 8. Recommended operating conditions 9. Static characteristics Table 5. Recommended operating conditions Symbol Parameter Conditions 74HC123 74HCT123 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 -VCC V VO output voltage 0 - VCC 0 -VCC V t/V input transition rise and fall rate nRD input VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V Tamb ambient temperature 40 +25 +125 40 +25 +125 C Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC123 VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 7 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset CI input capacitance - 3.5 - - - - - pF 74HCT123 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current per input pin; IO = 0 A; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pins nA, nB - 35 125 - 160 - 170 A pin nRD - 50 180 - 225 - 245 A CI input capacitance - 3.5 - - - - - pF Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 8 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC123 tpd propagation delay nRD, nA, nB to nQ or nQ; CEXT = 0 pF; REXT =5k; see Figure 9 [1] VCC = 2.0 V - 83 255 - 320 - 385 ns VCC = 4.5 V - 30 51 - 64 - 77 ns VCC = 5 V; CL = 15 pF - 26 - - - - - ns VCC = 6.0 V - 24 43 - 54 - 65 ns nRD (reset) to nQ or nQ; CEXT = 0 pF; REXT =5k; see Figure 9 VCC = 2.0 V - 66 215 - 270 - 325 ns VCC = 4.5 V - 24 43 - 54 - 65 ns VCC = 5 V; CL = 15 pF - 20 - - - - - ns VCC = 6.0 V - 19 37 - 46 - 55 ns tt transition time see Figure 9 [1] VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns tW pulse width nA LOW; see Figure 10 VCC = 2.0 V 100 8 - 125 - 150 - ns VCC = 4.5 V 20 3 - 25 - 30 - ns VCC = 6.0 V 17 2 - 21 - 26 - ns nB HIGH; see Figure 10 VCC = 2.0 V 100 17 - 125 - 150 - ns VCC = 4.5 V 20 6 - 25 - 30 - ns VCC = 6.0 V 17 5 - 21 - 26 - ns nRD LOW; see Figure 11 VCC = 2.0 V 100 14 - 125 - 150 - ns VCC = 4.5 V 20 5 - 25 - 30 - ns VCC = 6.0 V 17 4 - 21 - 26 - ns nQ HIGH and nQ LOW; VCC = 5.0 V; see Figure 10 and 11 [2] CEXT = 100 nF; REXT = 10 k - 450 - - - - - s CEXT = 0 pF; REXT =5k - 75 - - - - - ns 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 9 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset trtrig retrigger time nA, nB; CEXT = 0 pF; REXT = 5 k; VCC = 5.0 V; see Figure 10 [3][4] - 110 - - - - - ns REXT external timing resistor see Figure 7 VCC = 2.0 V 10 - 1000 - - - - k VCC = 5.0 V 2 - 1000 - - - - k CEXT external timing capacitor VCC = 5.0 V; see Figure 7 [4] - - - - - - - pF CPD power dissipation capacitance per monostable; VI = GND to VCC [5] - 54 - - - - - pF 74HCT123 tPHL HIGH to LOW propagation delay nRD, nA, nB to nQ or nQ; CEXT = 0 pF; REXT = 5 k; see Figure 9 VCC = 4.5 V - 30 51 - 64 - 77 ns VCC = 5 V; CL = 15 pF - 26 - - - - - ns nRD (reset) to nQ or nQ; CEXT = 0 pF; REXT =5k; see Figure 9 VCC = 4.5 V - 27 46 - 58 - 69 ns VCC = 5 V; CL = 15 pF - 23 - - - - - ns tPLH LOW to HIGH propagation delay nRD, nA, nB to nQ or nQ; CEXT = 0 pF; REXT =5k; see Figure 9 VCC = 4.5 V - 28 51 - 64 - 77 ns VCC = 5 V; CL = 15 pF - 26 - - - - - ns nRD (reset) to nQ or nQ; CEXT = 0 pF; REXT = 5 k; see Figure 9 VCC = 4.5 V - 23 46 - 58 - 69 ns VCC = 5 V; CL = 15 pF - 23 - - - - - ns tt transition time VCC = 4.5 V; see Figure 9 [1] - 7 15 - 19 - 22 ns Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 10 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset [1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH [2] For other REXT and CEXT combinations see Figure 7. If CEXT > 10 nF, the next formula is valid. tW = K  REXT  CEXT, where: tW = typical output pulse width in ns; REXT = external resistor in k; CEXT = external capacitor in pF; K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V. The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF. [3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF, the next formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid: trtrig = 30 + 0.19  REXT  CEXT0.9 + 13  REXT1.05, where: trtrig = retrigger time in ns; CEXT = external capacitor in pF; REXT = external resistor in k. The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF. [4] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi + (CL  VCC2  fo) + 0.75  CEXT  VCC2  fo + D  16  VCC where: fi = input frequency in MHz; fo = output frequency in MHz; D = duty factor in %; CL = output load capacitance in pF; VCC = supply voltage in V; CEXT = timing capacitance in pF; (CL  VCC2  fo) sum of outputs. tW pulse width VCC = 4.5 V nA LOW; see Figure 10 20 3 - 25 - 30 - ns nB HIGH; see Figure 10 20 5 - 25 - 30 - ns nRD LOW; see Figure 11 20 7 - 25 - 30 - ns nQ HIGH and nQ LOW; VCC = 5.0 V; see Figure 10 and 11 [2] CEXT = 100 nF; REXT = 10 k - 450 - - - - - s CEXT = 0 pF; REXT =5k - 75 - - - - - ns trtrig retrigger time nA, nB; CEXT = 0 pF; REXT = 5 k; VCC = 5.0 V; see Figure 10 [3][4] - 110 - - - - - ns REXT external timing resistor VCC = 5.0 V; see Figure 7 2 - 1000 - - - - k CEXT external timing capacitor VCC = 5.0 V; see Figure 7 [4] - - - - - - - pF CPD power dissipation capacitance per monostable; VI = GND to VCC  1.5 V [5] - 56 - - - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 11 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset VCC = 5.0 V; Tamb = 25 C. (1) REXT = 100 k (2) REXT = 50 k (3) REXT = 10 k (4) REXT = 2 k CEXT = 10 nF; REXT = 10 k to 100 k. Tamb = 25 C. Fig 7. Typical output pulse width as a function of the external capacitor value Fig 8. 74HC123 typical ‘K’ factor as function of VCC DDD      W: QV  &(;7 S)          9&& 9      DDD     . IDFWRU  74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 12 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 11. Waveforms Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Propagation delays from inputs (nA, nB, nRD) to outputs (nQ, nQ) and output transition times DDD Q%LQSXW W: W: W3/+ 90 92+ 90 90 W: W3/+ W7+/ W: W3+/ W3+/ 90 W: W3/+ Q$LQSXW Q5'LQSXW Q4RXWSXW Q4RXWSXW 90 W7/+ 9< 9; 9< 9; W3+/ W3+/ W3/+ UHVHW UHVHW 92/ 92+ 92/ 9, 9, 9, *1' *1' *1' 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 13 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset nRD = HIGH Fig 10. Output pulse control using retrigger pulse PQD W: W: W: W: W: Q%LQSXW Q$LQSXW Q4RXWSXW WUWULJ nA = LOW Fig 11. Output pulse control using reset input nRD PQD W: W: W: Q%LQSXW Q5'LQSXW Q4RXWSXW 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 14 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Test data is given in Table 8. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 12. Test circuit for measuring switching times 90 90 W: W:   9 9, 9, QHJDWLYH SXOVH SRVLWLYH SXOVH 9 90 90   WI WU WU WI DDG '87 9&& 9&& 9, 92 57 5/ 6 &/ RSHQ * Table 8. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC123 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT123 3 V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 15 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 12. Application information 12.1 Timing component connections The basic output pulse width is essentially determined by the values of the external timing components REXT and CEXT. 12.2 Power-up considerations When the monostable is powered-up it may produce an output pulse, with a pulse width defined by the values of REXT and CEXT. This output pulse can be eliminated using the circuit shown in Figure 14. (1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND). Fig 13. Timing component connections DDD &(;7 5(;7 Q$ Q% 9&& Q&(;7 Q5' Q5(;7&(;7 Q4 Q4 *1'                  Fig 14. Power-up output pulse elimination circuit DDD 5(6(7 9&& Q5' &(;7 5(;7 Q$ Q% 9&& *1' Q5(;7&(;7 Q&(;7 Q4 Q4                 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 16 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 12.3 Power-down considerations A large capacitor CEXT may cause problems when powering-down the monostable due to the energy stored in this capacitor. When a system containing this device is powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain damage, due to the capacitor discharging through the input protection diodes. To avoid this possibility, use a damping diode (DEXT) preferably a germanium or Schottky type diode able to withstand large current surges and connect as shown in Figure 15. Fig 15. Power-down protection circuit DDD '(;7 Q5' &(;7 5(;7 Q$ Q% 9&& Q&(;7 Q5(;7&(;7 Q4 Q4              *1'    74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 17 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 13. Package outline Fig 16. Package outline SOT38-4 (DIP16) 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ 627   0+ F H  0( $ / VHDWLQJSODQH $ Z 0 E E H ' $ =     ( SLQLQGH[ E   PP VFDOH 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 81,7 $ PD[   E    E F ' ( H 0 = / + PP ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV $ PLQ $ PD[ E PD[ H 0( Z                         LQFKHV                            ',3SODVWLFGXDOLQOLQHSDFNDJHOHDGV PLO 627 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 18 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Fig 17. Package outline SOT109-1 (SO16) ; Z 0 ș $ $ $ ES ' +( /S 4 GHWDLO; ( = H F / Y 0 $ $  $     \ SLQLQGH[ 81,7 $ PD[ $ $ $ ES F '  (   H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP LQFKHV                        R R   ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG   627   ( 06                                PP VFDOH 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 19 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Fig 18. Package outline SOT338-1 (SSOP16) 81,7 $ $ $ ES F '  (  H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP                          R    R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 627    Z 0 ES ' +( ( = H F Y 0 $ ; $ \     ș $ $ $ /S 4 GHWDLO; / $  02 SLQLQGH[   PP VFDOH 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 $ PD[  74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 20 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Fig 19. Package outline SOT403-1 (TSSOP16) 81,7 $ $ $ ES F '  (   H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP                      R     R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG   627 02   Z 0 ES ' = H      ș $ $ $ /S 4 GHWDLO; / $  +( ( F Y 0 $ ; $ \   PP VFDOH 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 $ PD[  SLQLQGH[ 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 21 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Fig 20. Package outline SOT763-1 (DHVQFN16) WHUPLQDO LQGH[DUHD   81,7 $ E (K H \  F 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP   'K   \     H        ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 627 02     /  Y  Z   PP VFDOH 627 '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP $  PD[ $ $ F GHWDLO; \ \ H  & / (K 'K H H E         ; ' ( & % $ WHUPLQDO LQGH[DUHD & $ & Y 0 % Z 0 (  1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG '    74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 22 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 14. Abbreviations 15. Revision history Table 9. Abbreviations Acronym Abbreviation CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT123 v.9 20150119 Product data sheet - 74HC_HCT123 v.8 Modifications: • Table 7: Power dissipation capacitance condition for 74HCT123 is corrected. 74HC_HCT123 v.8 20111216 Product data sheet - 74HC_HCT123 v.7 Modifications: • Legal pages updated. 74HC_HCT123 v.7 20110825 Product data sheet - 74HC_HCT123 v.6 74HC_HCT123 v.6 20110314 Product data sheet - 74HC_HCT123 v.5 74HC_HCT123 v.5 20090713 Product data sheet - 74HC_HCT123 v.4 74HC_HCT123 v.4 20060616 Product data sheet - 74HC_HCT123 v.3 74HC_HCT123 v.3 20040511 Product specification - 74HC_HCT123_CNV v.2 74HC_HCT123_CNV v.2 19980708 Product specification - - 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 23 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset 16. Legal information 16.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 74HC_HCT123 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 9 — 19 January 2015 24 of 25 NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors 74HC123; 74HCT123 Dual retriggerable monostable multivibrator with reset © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 January 2015 Document identifier: 74HC_HCT123 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Application information. . . . . . . . . . . . . . . . . . 15 12.1 Timing component connections . . . . . . . . . . . 15 12.2 Power-up considerations . . . . . . . . . . . . . . . . 15 12.3 Power-down considerations . . . . . . . . . . . . . . 16 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 17 Contact information. . . . . . . . . . . . . . . . . . . . . 24 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1. General description The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and 3-state outputs. The registers have separate clocks. Data is shifted on the positive-going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive-going transition of the storage register clock input (STCP). If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features and benefits  8-bit serial input  8-bit serial or parallel output  Storage register with 3-state outputs  Shift register with direct clear  100 MHz (typical) shift out frequency  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications  Serial-to-parallel data conversion  Remote control holding register 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 7 — 26 January 2015 Product data sheet 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 2 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 4. Ordering information 5. Functional diagram Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC595N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT595N 74HC595D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HCT595D 74HC595DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HCT595DB 74HC595PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74HCT595PW 74HC595BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5  3.5  0.85 mm SOT763-1 74HCT595BQ Fig 1. Functional diagram PQD 67$7(2873876 %,76725$*(5(*,67(5 67$*(6+,)75(*,67(5 4 4 4 4 4 4 4 4 46           '6 6+&3 67&3 2(     05 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 3 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 2. Logic symbol Fig 3. IEC logic symbol 05 2(              PQD 4 4 4 4 4 4 4 4 46 '6 6+&3 67&3 PQD          ' ' &    &   (1 5 65*  Fig 4. Logic diagram 67$*( 67$*(672 67$*( )) ' &3 4 5 /$7&+ ' &3 4 )) ' &3 4 5 /$7&+ ' &3 4 PQD ' 4 4 4 4 4 4 4 4 46 4 '6 67&3 6+&3 2( 05 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 4 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 6. Pinning information 6.1 Pinning Fig 5. Pin configuration DIP16, SO16 Fig 6. Pin configuration SSOP16, TSSOP16 +& +&7 4 9&& 4 4 4 '6 4 2( 4 67&3 4 6+&3 4 05 *1' 46 DDR                 +& +&7 4 9&& 4 4 4 '6 4 2( 4 67&3 4 6+&3 4 05 *1' 46 DDR                 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 7. Pin configuration for DHVQFN16 DDR +& +&7 4 05 4 6+&3 4 67&3 4 2( 4 '6 4 4 *1' 46 4 9&& 7UDQVSDUHQWWRSYLHZ                 WHUPLQDO LQGH[DUHD *1'  74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 5 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 6.2 Pin description 7. Functional description [1] H = HIGH voltage state; L = LOW voltage state;  = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. Table 2. Pin description Symbol Pin Description Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input Q0 15 parallel data output 0 VCC 16 supply voltage Table 3. Function table[1] Control Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L X L NC a LOW-level on MR only affects the shift registers X  L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state  X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X  L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages   L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 6 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 8. Limiting values [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. [3] For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. [4] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C. Fig 8. Timing diagram 6+&3 '6 67&3 05 2( 4 4 4 4 46 =VWDWH =VWDWH =VWDWH =VWDWH PQD Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) pin Q7S - 25 mA pins Qn - 35 mA ICC supply current - 70 mA IGND ground current 70 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation DIP16 package [1] - 750 mW SO16 package [2] - 500 mW SSOP16 package [3] - 500 mW TSSOP16 package [3] - 500 mW DHVQFN16 package [4] - 500 mW 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 7 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 9. Recommended operating conditions 10. Static characteristics Table 5. Recommended operating conditions Symbol Parameter Conditions 74HC595 74HCT595 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 -VCC V VO output voltage 0 - VCC 0 -VCC V t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V Tamb ambient temperature 40 +25 +125 40 +25 +125 C Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max 74HC595 VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - V VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V VOH HIGH-level output voltage VI = VIH or VIL all outputs IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V Q7S output IO = 4 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V Qn bus driver outputs IO = 6 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V IO = 7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 8 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state VOL LOW-level output voltage VI = VIH or VIL all outputs IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 V Q7S output IO = 4 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V Qn bus driver outputs IO = 6 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 7.8 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND - - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 - 160 A CI input capacitance - 3.5 - - - pF 74HCT595 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V all outputs IO = 20 A 4.4 4.5 - 4.4 - V Q7S output IO = 4 mA 3.84 4.32 - 3.7 - V Qn bus driver outputs IO = 6 mA 3.7 4.32 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V all outputs IO = 20 A - 0 0.1 - 0.1 V Q7S output IO = 4.0 mA - 0.15 0.33 - 0.4 V Qn bus driver outputs IO = 6.0 mA - 0.16 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 A Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 9 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 11. Dynamic characteristics IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND - - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 80 - 160 A ICC additional supply current per input pin; IO = 0 A; VI = VCC  2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V pins MR, SHCP, STCP, OE - 150 675 - 735 A pin DS - 25 113 - 123 A CI input capacitance - 3.5 - - - pF Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max 74HC595 tpd propagation delay SHCP to Q7S; see Figure 9 [2] VCC = 2 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns VCC = 6 V - 15 27 - 34 - 41 ns STCP to Qn; see Figure 10 [2] VCC = 2 V - 55 175 - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns VCC = 6 V - 16 30 - 37 - 45 ns MR to Q7S; see Figure 12 [3] VCC = 2 V - 47 175 - 220 - 265 ns VCC = 4.5 V - 17 35 - 44 - 53 ns VCC = 6 V - 14 30 - 37 - 45 ns ten enable time OE to Qn; see Figure 13 [4] VCC = 2 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 30 - 38 - 45 ns VCC = 6 V - 14 26 - 33 - 38 ns tdis disable time OE to Qn; see Figure 13 [5] VCC = 2 V - 41 150 - 190 - 225 ns VCC = 4.5 V - 15 30 - 38 - 45 ns VCC = 6 V - 12 27 - 33 - 38 ns 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 10 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state tW pulse width SHCP HIGH or LOW; see Figure 9 VCC = 2 V 75 17 - 95 - 110 - ns VCC = 4.5 V 15 6 - 19 - 22 - ns VCC = 6 V 13 5 - 16 - 19 - ns STCP HIGH or LOW; see Figure 10 VCC = 2 V 75 11 - 95 - 110 - ns VCC = 4.5 V 15 4 - 19 - 22 - ns VCC = 6 V 13 3 - 16 - 19 - ns MR LOW; see Figure 12 VCC = 2 V 75 17 - 95 - 110 - ns VCC = 4.5 V 15 6 - 19 - 22 - ns VCC = 6 V 13 5 - 16 - 19 - ns tsu set-up time DS to SHCP; see Figure 10 VCC = 2 V 50 11 - 65 - 75 - ns VCC = 4.5 V 10 4 - 13 - 15 - ns VCC = 6 V 9 3 - 11 - 13 - ns SHCP to STCP; see Figure 11 VCC = 2 V 75 22 - 95 - 110 - ns VCC = 4.5 V 15 8 - 19 - 22 - ns VCC = 6 V 13 7 - 16 - 19 - ns th hold time DS to SHCP; see Figure 11 VCC = 2 V 3 6 - 3 - 3 - ns VCC = 4.5 V 3 2 - 3 - 3 - ns VCC = 6 V 3 2 - 3 - 3 - ns trec recovery time MR to SHCP; see Figure 12 VCC = 2 V 50 19 - 65 - 75 - ns VCC = 4.5 V 10 7 - 13 - 15 - ns VCC = 6 V 9 6 - 11 - 13 - ns fmax maximum frequency SHCP or STCP; see Figure 9 and 10 VCC = 2 V 9 30 - 4.8 - 4 - MHz VCC = 4.5 V 30 91 - 24 - 20 - MHz VCC = 6 V 35 108 - 28 - 24 - MHz CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [6][7] - 115 - - - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 11 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state [1] Typical values are measured at nominal supply voltage. [2] tpd is the same as tPHL and tPLH. [3] tpd is the same as tPHL only. [4] ten is the same as tPZL and tPZH. [5] tdis is the same as tPLZ and tPHZ. [6] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL  VCC2  fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. [7] All 9 outputs switching. 74HCT595; VCC = 4.5 V to 5.5 V tpd propagation delay SHCP to Q7S; see Figure 9 [2] - 25 42 - 53 - 63 ns STCP to Qn; see Figure 10 [2] - 24 40 - 50 - 60 ns MR to Q7S; see Figure 12 [3] - 23 40 - 50 - 60 ns ten enable time OE to Qn; see Figure 13 [4] - 21 35 - 44 - 53 ns tdis disable time OE to Qn; see Figure 13 [5] - 18 30 - 38 - 45 ns tW pulse width SHCP HIGH or LOW; see Figure 9 16 6 - 20 - 24 - ns STCP HIGH or LOW; see Figure 10 16 5 - 20 - 24 - ns MR LOW; see Figure 12 20 8 - 25 - 30 - ns tsu set-up time DS to SHCP; see Figure 10 16 5 - 20 - 24 - ns SHCP to STCP; see Figure 11 16 8 - 20 - 24 - ns th hold time DS to SHCP; see Figure 11 3 2 - 3 - 3 - ns trec recovery time MR to SHCP; see Figure 12 10 7 - 13 - 15 - ns fmax maximum frequency SHCP and STCP; see Figure 9 and 10 30 52 - 24 - 20 - MHz CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC  1.5 V [6] [7] - 130 - - - - - pF Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max Min Max 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 12 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 12. Waveforms Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Shift clock pulse, maximum frequency and input to output propagation delays PQD 6+&3LQSXW 46RXWSXW W3/+ W3+/ W: IPD[ 90 92+ 9, *1' 92/ 90 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Storage clock to output propagation delays PQD 67&3LQSXW 4QRXWSXW W3/+ W3+/ W: WVX IPD[ 90 92+ 9, *1' 92/ 90 6+&3LQSXW 9, *1' 90 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 13 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Data set-up and hold times PQD *1' *1' WK WVX WK WVX 90 90 90 9, 92+ 92/ 9, 46RXWSXW 6+&3LQSXW '6LQSXW Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 12. Master reset to output propagation delays PQD 05 LQSXW 6+&3LQSXW 46RXWSXW W3+/ W: WUHF 90 92+ 92/ 9, *1' 9, *1' 90 90 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 14 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 13. Enable and disable times PVD W 3/= W 3+= RXWSXWV GLVDEOHG RXWSXWV HQDEOHG   RXWSXWV HQDEOHG 2(LQSXW 90 W 3=/ W 3=+ 90 90 4QRXWSXW /2:WR2)) 2))WR/2: 4QRXWSXW +,*+WR2)) 2))WR+,*+ W U W I   Table 8. Measurement points Type Input Output VM VM 74HC595 0.5VCC 0.5VCC 74HCT595 1.3 V 1.3 V 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 15 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Test data is given in Table 9. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. S1 = test selection switch. Fig 14. Test circuit for measuring switching times 90 90 W: W:   9 9, 9, QHJDWLYH SXOVH SRVLWLYH SXOVH 9 90 90   WI WU WU WI DDG '87 9&& 9&& 9, 92 57 5/ 6 &/ RSHQ * Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC595 VCC 6 ns 50 pF 1 k open GND VCC 74HCT595 3 V 6 ns 50 pF 1 k open GND VCC 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 16 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 13. Package outline Fig 15. Package outline SOT38-4 (DIP16) 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ 627   0+ F H  0( $ / VHDWLQJSODQH $ Z 0 E E H ' $ =     ( SLQLQGH[ E   PP VFDOH 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 81,7 $ PD[   E    E F ' ( H 0 = / + PP ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV $ PLQ $ PD[ E PD[ H 0( Z                         LQFKHV                            ',3SODVWLFGXDOLQOLQHSDFNDJHOHDGV PLO 627 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 17 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 16. Package outline SOT109-1 (SO16) ; Z 0 ș $ $ $ ES ' +( /S 4 GHWDLO; ( = H F / Y 0 $ $  $     \ SLQLQGH[ 81,7 $ PD[ $ $ $ ES F '  (   H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP LQFKHV                        R R   ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG   627   ( 06                                PP VFDOH 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 18 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 17. Package outline SOT338-1 (SSOP16) 81,7 $ $ $ ES F '  (  H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP                          R    R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 627    Z 0 ES ' +( ( = H F Y 0 $ ; $ \     ș $ $ $ /S 4 GHWDLO; / $  02 SLQLQGH[   PP VFDOH 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 $ PD[  74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 19 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 18. Package outline SOT403-1 (TSSOP16) 81,7 $ $ $ ES F '  (   H +( / /S 4 Y Z \ = ș 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP                      R     R ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG   627 02   Z 0 ES ' = H      ș $ $ $ /S 4 GHWDLO; / $  +( ( F Y 0 $ ; $ \   PP VFDOH 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 $ PD[  SLQLQGH[ 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 20 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Fig 19. Package outline SOT763-1 (DHVQFN16) WHUPLQDO LQGH[DUHD   81,7 $ E (K H \  F 287/,1( 5()(5(1&(6 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ PP   'K   \     H        ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 627 02     /  Y  Z   PP VFDOH 627 '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP $  PD[ $ $ F GHWDLO; \ \ H  & / (K 'K H H E         ; ' ( & % $ WHUPLQDO LQGH[DUHD & $ & Y 0 % Z 0 (  1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG '    74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 21 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 14. Abbreviations 15. Revision history Table 10. Abbreviations Acronym Abbreviation CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT595 v.7 20150126 Product data sheet - 74HC_HCT595 v.6 Modifications: • Table 7: Power dissipation capacitance condition for 74HCT595 is corrected. 74HC_HCT595 v.6 20111212 Product data sheet - 74HC_HCT595 v.5 Modifications: • Legal pages updated. 74HC_HCT595 v.5 20110628 Product data sheet - 74HC_HCT595 v.4 74HC_HCT595 v.4 20030604 Product specification - 74HC_HCT595_CNV v.3 74HC_HCT595_CNV v.3 19980604 Product specification - - 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 22 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 16. Legal information 16.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 7 — 26 January 2015 23 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 January 2015 Document identifier: 74HC_HCT595 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Recommended operating conditions. . . . . . . . 7 10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 21 15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 21 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 17 Contact information. . . . . . . . . . . . . . . . . . . . . 23 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 La chaîne de signal analogique, selon National Semiconductor Haute vitesse et basse puissance 19 Il y a quelques années, on annonçait le déclin de l’électronique analogique, mais en fait ce secteur va de mieux en mieux. Dans nombre de domaines, les composants analogiques ont été remplacés par des numériques, mais ils ont trouvé d’autres niches de marché. Par exemple, on estime à dix le nombre de composants analogiques requis pour le fonctionnement de chaque DSP dans un circuit. L’organisation mondiale des statistiques du commerce des semi-conducteurs estime le marché analogique à 36.77 milliards de dollars US en 2007 et il semblerait que sa croissance atteigne 12,6% l’année prochaine (le deuxième plus important secteur de croissance de l’industrie, après le logique). Ce développement a été alimenté par une croissance considérable de l’utilisation des appareils électroniques portables grand public et de l’infrastructure de communications venant en support de ceux-ci. Les deux fonctions principales qui restent et demeureront analogiques dans l’avenir prévisible sont la gestion de puissance et la chaîne de signal. Le rôle de la gestion de puissance est évident, notamment dans les appareils portables alimentés sur batteries, la durée de vie de celles-ci étant primordiale au succès d’un produit portable. La chaîne de signal constitue la seconde fonction analogique d’un circuit et, bien qu’elle ait un rôle moins évident qu’auparavant, elle est tout aussi importante. Focus sur les composants analogiques de National Semiconductor National Semiconductor est l’un des premiers fabricants de composants analogiques. L’entreprise a cédé son activité microprocesseur Geode à AMD en 2003 afin de cibler exclusivement ses solutions analogiques. L’entreprise focalise tous ses efforts de R&D dans ce domaine technologique. National offre des solutions de transfert de données série et de conversion, de conditionnement de signal analogique haute performance pour répondre aux besoins des applications finales techniquement exigeantes, telles que les stations de base sans fil, la réseautique, l’instrumentation, l’équipement militaire, aérospatial et médical. L’entreprise tente de simplifier le processus de conception de la chaîne de signal avec une offre étendue de solutions. Cet article traite de certaines solutions de National et explique les spécifications les plus importantes requises par les ingénieurs concepteurs. Les trois domaines du concept MIDAS, sur lesquels l’article se concentre, sont les amplificateurs, les convertisseurs de données et les produits d’interface. Besoins pour la conception La sélection des composants de la chaîne de signal implique la prise en compte du flux d’un signal, de sa source (souvent un capteur ou une source de signal) vers l’univers numérique des contrôleurs, processeurs et FPGA où le traitement du signal a lieu. Le processus de conception nécessite des valeurs d’impédance appariées, une minimisation des sources de bruit et la garantie d’un gain suffisant au niveau de l’entrée pour commander un CAN. Dès que la chaîne de base est élaborée, le travail de développement subsidiaire implique de s’assurer que chaque composant de la chaîne est correctement entraîné et protégé. La sélection du CAN le « mieux adapté » pour une application donnée repose sur plusieurs facteurs. La résolution est l’une des priorités car la précision du système en dépend, généralement. La précision elle-même dépend beaucoup de l’exécution du CAN et peut varier selon qu’il s’agit d’applications à très haut débit avec des fréquences d’échantillonnage supérieures à 200Msps (ex., ADC08D1000WG-QV), d’applications à haut débit allant de 1Msps à 200Msps (ex., ADC14V155) ou d’applications à usage général et débit plus faible, inférieur à 1Msps. En général, le choix entre le CAN ou l’amplificateur est habituellement le facteur restrictif dans les chaînes de signal à haute fréquence, si bien que la sélection des deux exige une grande attention. L’un des besoins les plus exigeants pour ce qui concerne le traitement de signal analogique est la fonction de conversion d’une terminaison simple vers une différentielle : éclatement du signal en deux signaux identiques qui peuvent être comparés pour filtrer le bruit, la distorsion ou tout autre effet non désiré au niveau signal. Celle-ci est souvent réalisée avec des transformateurs, mais si la gamme de fréquence du signal inclut du courant continu, le transformateur ne fonctionnera pas et il sera nécessaire d’utiliser un amplificateur terminaison simple / différentielle (ex., LMH6551). L’amplificateur ne fournit pas seulement une amplification, mais offre également déphasage niveau (permettant de soustraire le composant CC du signal), fonctions de correspondance d’impédance et gain. Bande passante, gain, bruit et distorsion constituent les principales spécifications dont il faut tenir compte pour un amplificateur. Le gain d’un amplificateur qui est légèrement inférieur au signal maximum de la pleine échelle d’un CAN est idéal pour éviter que le signal amplifié ne surcharge l’entrée du CAN et écrêter le signal en raison d’un décalage ou de légères imprécisions des valeurs de gain. Pour éviter également l’atténuation du signal avant qu’il arrive au CAN, il est souhaitable d’utiliser une bande passante d’amplificateur de 3dB supérieure à la bande passante du signal d’entrée. Enfin, dans tout système intégrant une chaîne de signal, le rapport signal/bruit est sans conteste une métrique clé. Du fait que le bruit d’horloge contribue au bruit d’ensemble du système, et que les horloges sont des composants essentiels de tout système, la régulation du bruit d’horloge est un élément capital de la conception système. National fabrique des conditionneurs d’horloge de précision avec VCO intégré (ex., LMK03000). Ce dispositif permet au concepteur de créer une architecture d’horloge complète (sous-système) qui réalise la meilleure performance possible et, à un niveau fonctionnel, non seulement génère une horloge de précision, mais également reconditionne et distribue une horloge générée en externe. Invitez vos clients à consulter cet article en ligne sur www.electronicsdesignworld.com 11 Puissance utile pour une performance de pointe Aujourd’hui, cette déclaration est devenue une nécessité. Dans la conception électronique moderne, la puissance représente un produit fini et la plus grande partie de la puissance qui fait fonctionner l’électronique finit en chaleur perdue car inutilisée. De plus en plus de pays ajoutent des fonctionnalités technologiquement avancées, la courbe de la consommation énergétique va cependant continuer à monter. Conscient de cette tendance à la hausse, National Semiconductor a développé des produits PowerWise pour offrir un niveau de performance avec une consommation énergétique réduite. Le rapport performance/puissance Une mesure métrique simple pour une voiture est la consommation moyenne de 0 à 100 km/h. Du fait de l’augmentation du prix des carburants, cette mesure métrique prend de l’importance. Ce concept s’applique également au rapport performance/puissance et pour un ingénieur cela peut signifier une ou deux choses : consommation plus faible ou performance supérieure. L’avantage évident d’une consommation moindre est l’économie plus importante réalisée ou la durée de vie prolongée des batteries, en plus d’une usure thermique réduite des composants électroniques. Plus la température ambiante est faible, plus la durée de vie du produit est prolongée, impliquant une baisse des coûts de remplacement. Améliorer le rapport performance/ puissance peut aussi offrir des avantages lorsqu’il est nécessaire d’installer un nouveau design avec des ressources sortantes. Par exemple, un boîtier Set Top (STB) pour connexion par câble peut nécessiter un espace physique égal ou plus petit que le modèle précédent, une puissance de même niveau ou supérieur, mais requiert un niveau de performance supérieur. Même si les ressources n’ont pas changées, pour réaliser avec succès son projet, le concepteur doit utiliser des composants plus performants et consommant la même énergie ou moins. Technologie de processus, architecture et systèmes La technologie de processus est importante, non seulement pour un niveau de qualité constant, mais également pour une meilleure performance avec une consommation moindre. Des traitements à bande passante élevée et faible déperdition sont essentiels pour fournir une performance globale optimale dans les semiconducteurs, mais ils ne représentent que 50% des critères requis. Les techniques et propriétés intellectuelles à la base de la conception des dispositifs sont aussi importantes que les traitements employés. Autre aspect important de la mesure du rapport performance/puissance qui n’est pas toujours apparent au niveau des composants individuels : la façon dont ces composants interagissent entre eux et qui permettra de réduire la consommation d’énergie. Outils pour augmenter l’efficacité Certains composants ont besoin d’outils pour contribuer à améliorer le rapport performance/puissance. Cela s’applique essentiellement, mais non exclusivement, aux régulateurs de commutation de puissance. L’outil de conception WEBENCH de National Semiconductor permet aux ingénieurs de ‘composer en interne’ un niveau de performance pour circuits d’alimentation en contrepartie d’autres paramètres, c.-à-d. la taille des composants. La famille PowerWise de régulateurs commutateurs simples (LM5576) en est un bon exemple. Cette famille est prise en charge par l’outil WEBENCH avec un contrôle du réglage du rendement requis pour le système, comme indiqué en Figure 1. En 1908, William A. Smith déclarait, « L’ingénierie est la science de la maîtrise, de la conservation de l’énergie fournie et stockée sous forme naturelle pour les besoins de l’homme. C’est le rôle de l’ingénierie d’utiliser cette énergie de manière optimale afin qu’il y ait le moins de pertes possible. » Figure 1. Contrôle d’optimisation WEBENCH Premier Farnell Global Technology Centre Conception de systèmes médicaux avec des microprocesseurs Abrégé Les dispositifs électroniques médicaux représentent toute une gamme de matériel comprenant aussi bien des machines de diagnostic par imagerie qui occupent toute une pièce, que des petits dispositifs portables que les patients peuvent emporter partout. Pour atteindre leurs objectifs de prestations optimales et de coûts réduits, les prestataires de soins de santé réclament aux fabricants des améliorations dans le domaine de la visualisation et de la transmission des données médicales image et vidéo. En réponse à cette demande, nous assistons à l'émergence de plusieurs tendances techniques susceptibles d'influencer l'architecture des matériels futurs : 􀁺 Le développement de matériel disponible dans le commerce et de matériel portable ; 􀁺 L'interface parallèle propriétaire sera remplacée par une interface HSIO standardisée ; 􀁺 Ajout de dispositifs de communication par Internet filaires et sans-fil. Alors que le public se préoccupe de plus en plus des questions de santé, la demande en produits médicaux électroniques sur le marché augmente, plus particulièrement dans le secteur des produits haut de gamme, comme les scanners CT, les IRM, les appareils de diagnostic à ultrasons ultra performants, etc. La taille du marché mondial de l'électronique médicale a connu une croissance importante. Espicom (une société d'étude de marché) prévoit que le volume des ventes sur le marché mondial de l'instrumentation médicale dépassera les 200 milliards de dollars, la part des produits médicaux électroniques étant de 45 %, c'est-à-dire 90 milliards de dollars. Quant à la perspective sur le marché médical chinois, il est évident que l'influence favorable provient des changements de politique gouvernementale, des progrès en matière de libéralisation du milieu hospitalier et d'une croissance accélérée du marché. La tendance au développement de matériel de petites dimensions plus portable sera accompagnée d'exigences plus strictes en matière de consommation d'énergie et de traitement des signaux. Les ingénieurs vont donc devoir relever des défis encore plus importants. Le marché chinois de l'électronique médicale poursuivait son expansion en 2006. Le volume total des ventes sur ce marché a dépassé les 20 milliards de RMB pour atteindre 21,08 milliards de RMB, une croissance de 15,6 % par rapport à l'année précédente, ce qui, de toute évidence, dépasse celle du même marché à l'échelle mondiale. Le marché chinois de l'électronique médicale maintiendra une croissance régulière avec un taux de croissance annuel moyen de 18,2 % dans les années à venir et on peut s'attendre à ce qu'en 2011, le volume de ce marché approche les 50 milliards de RMB. NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre Taux de croissance annuel moyen 11 % Figure 1 Marché international des semi-conducteurs médicaux Taux de croissance annuel moyen 12 % Taux de croissance annuel moyen ultrasons 15 % Source : Databeans, 2007 Figure 2 Marché international des semi-conducteurs d'imagerie médicale NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ bone density scanner scanner de densité osseuse MRI scanner scanner IRM Premier Farnell Global Technology Centre X-ray Rayon-X PET scanner scanner PET CT Scanner scanner CT electrocardiogram électrocardiogramme other imaging autre type d'imagerie ultrasound ultrasons Les secteurs de l'industrie tels que les semi-conducteurs, les composants, les matériaux électroniques médicaux et le matériel de fabrication ont vu leur production accélérée par la croissance du marché de l'électronique médicale. Dans les cinq prochaines années, le volume du marché des semi-conducteurs électroniques médicaux dépassera les 3,5 milliards de dollars avec un taux de croissance annuel moyen de 11 %. Pour répondre aux exigences strictes concernant la stabilité et les performances du matériel électronique médical, la sécurité du matériel et la sécurité personnelle des utilisateurs, ainsi qu'aux exigences spécifiques de certification des systèmes médicaux, les éléments électroniques médicaux et les programmes de conception, ainsi que les matériaux et les technologies de fabrication, etc., doivent satisfaire des exigences plus strictes. Architecture des systèmes médicaux À l'exclusion des analyseurs des gaz du sang, des tensiomètres numériques, des moniteurs de rythme cardiaque/pouls numériques, des glucomètres ou même des thermomètres numériques, la plupart des dispositifs médicaux se composent de cinq blocs de niveau système communs à chaque : 􀁺 Élément de biocapteur 􀁺 Module AFE 􀁺 Contrôle et traitement des données 􀁺 Interface utilisateur 􀁺 Gestion de batterie/d'alimentation électrique En apparence, la topologie de mise en oeuvre effective diffère largement d'un bloc à l'autre selon les exigences de détection, de traitement et d'affichage des informations qui dépendent du type d'appareil de mesure et de l'ensemble des caractéristiques. NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre Figure 3 Schéma fonctionnel d'un système médical uProcessor microprocesseur biosensor biocapteur precision amp ampli. précision buffer/ op. amp. buffer/ampli op. monitor moniteur speaker haut-parleur ADC CAN LCD Ctrl Commande LCD data bus bus de données Bluetooth ..... Transmission de données sans fil Bluetooth Zigbee WiFi/WiMax LED/KEY driver Driver de LED/Clavier USB controller wired data transmission Contrôleur USB - Transmission de données filaire Flash/ROM Mémoire flash/ROM Keypad clavier Power charger/management chargeur/gestion d'alimentation sensor capteur user interface interface utilisateur power alimentation back end arrière data ctrl contrôle des données LED display affichage LED NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre Matériel à ultrasons utilisant des DSP et MCU Les systèmes à ultrasons tant médicaux qu'industriels utilisent des techniques d'imagerie focales pour obtenir des images performantes ; cette technique dépasse largement ce qui peut être obtenu par une approche à une voie. En utilisant un réseau de récepteurs, on peut créer une image haute définition en décalant, en mettant à l'échelle puis en résumant intelligemment l'énergie d'écho. Le concept de décalage et les signaux reçus d'un réseau de transducteurs de mise à l'échelle lui permettent de se concentrer sur un point unique dans la région balayée. En se concentrant sur différents points en une seule séquence, on peut finalement assembler une image. Figure 4 Schéma fonctionnel d'un système à ultrasons scan conversion post processing post-traitement de conversion de scan spectral doppler processing traitement de doppler spectral color/power doppler processing traitement de doppler couleur/Power doppler B mode processing traitement mode B switches commutateurs feedback retour time gain control contrôle de gain de temps audio amp. ampli audio monitor moniteur speaker haut-parleur beamformer unit Tx & Tx Transmission/réception - filtre de formation de voies numériques ADC CAN transducer matrix matrice de transducteur data bus bus de données Power management gestion de puissance NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre Core power alimentation de coeur I/O power alimentation des E/S system power alimentation du système Flash/ROM Mémoire flash/ROM data storage stockage de données Keypad clavier Power management gestion d'alimentation sensor capteur user interface interface utilisateur power alimentation back end arrière data ctrl contrôle des données LED display affichage LED On utilise généralement un filtre passe-bas comme filtre anti-alias entre la tension Vac et le CAN, pour limiter la bande passante du bruit. On pourra trouver ici les topologies en phase linéaire basées sur le filtre deux à cinq pôles d'un système spécifique. Quant à la sélection d'un ampli op., les considérations primaires doivent inclure les fréquences d'entrée minimales et maximales, les déviations de signal, les distorsions harmoniques et les exigences de gain. Typiquement, les convertisseurs analogique/numérique (CAN) sont de 10 et 12 bits. Le rapport signal/bruit et la consommation électrique sont les facteurs les plus importants, suivis de l'intégration de voie. Source : www.ti.com/ADS527x EVM User’s Guide Figure 5 Mise en oeuvre des convertisseurs analogiques/numériques (CAN) [see note = voir note] L'ajout d'une interface LVDS entre le CAN et le filtre de formation de voies représente une autre tendance dans les CAN, le nombre de lignes d'interface pouvant être réduit de 6144 à 1024 pour un système à 512 voies en sérialisant les données sortant du CAN. Cette réduction permet d'utiliser des cartes de circuit imprimé plus petites et plus économiques qui forment une partie essentielle des systèmes d'imagerie portables. Les fonctions du DSP pouvant être utilisées dans un système d'imagerie comprennent le traitement Doppler, l'imagerie 2D, 3D et même 4D ainsi que tout un éventail d'algorithmes post-traitement destinés à améliorer la fonctionnalité et les performances. Les exigences les plus importantes d'un système d'imagerie sont des performances élevées et une large bande passante. Les systèmes à ultrasons offrent de nombreux niveaux de performance et de fonctionnalité différents. NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre Certaines solutions peuvent contenir des composants réclamant une gamme dynamique élevée, ou des composants dont les fonctions consistent à réaliser un traitement en virgule flottante en beaucoup moins de cycles. On peut citer la réduction spectrale ou la racine carrée comme exemples de ce type de fonctions. Les DSP conviennent parfaitement dans les applications qui favorisent un traitement en virgule flottante. Lorsqu'une application à ultrasons réclame un système d'exécution, un microcontrôleur de type processeur ARM, peut fournir la solution, car il est capable de gérer les exigences d'un système d'exécution. L'assemblage des signaux est assuré par un filtre de formation des voies numérique. Il s'agit d'un ASIC normal conçu sur mesure, mais sa fonction est mise en oeuvre par un procédé de logique programmable différent. Le signal numérisé est mis à l'échelle et décalé dans le filtre de formation des voies de manière à générer l'effet de concentration dans la chaîne réceptrice. Après le réglage correct, les signaux de toutes les voies réceptrices sont alors rassemblés et transférés au système d'imagerie. Le système d'imagerie peut être développé en tant qu'ASIC séparé, être un processeur programmable tel qu'un DSP, ou être entièrement un ordinateur de bureau. Les éléments de transmission doivent pouvoir être capables de contrôler des déviations de signal entre 100 V et 200 V. La plupart du temps cette opération est assurée par des FET haute tension. Deux types de commandes de FET peuvent être utilisés : marche/arrêt (pousser/tirer) ou linéaire classe-AB. La plus populaire est la méthode pousser/tirer qui ne demande qu'une interface très simple et très économique pour connecter les FET. La méthode classe-AB peut beaucoup améliorer la distorsion harmonique mais réclame des pilotes plus complexes et consomme plus d'énergie. Les fabricants de systèmes et d'équipement ont choisi de nombreux types de produits différents de plusieurs fournisseurs pour leurs applications d'imagerie à ultrasons, y compris les amplis op., les CAN simples, doubles et octaux (tous avec récupération de surcharge d'entrée rapide et d'excellentes performances dynamiques), les processeurs de signaux numériques, une circuit intégré frontal ultrason basse puissance à 8 voies, par exemple VCA8617 et ADS5270, conçu spécifiquement pour le marché des appareils à ultrasons. NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre Conception d'un scanner PET avec FPGA /PLD Selon le type d'isotope utilisé, on peut observer différentes fonctions métaboliques. Un scanner PET étant capable de suivre le trajet d'un cancer dans le corps et d'illustrer avec précision l'étendue de la maladie, c'est un outil particulièrement efficace dans le diagnostic des cancers, par exemple. Un autre secteur d'application en développement constant des scanners PET est le diagnostic des troubles neurologiques courants tels que la maladie d'Alzheimer, la maladie de Hodgkins et les accidents cérébrovasculaires. Figure 6 Schéma fonctionnel d'un scanner PET radiation radiation PMT array réseau PMT motors moteurs Precision amps amplis de précision HV supply control commande d'alimentation HT Rx gain control commande réception gain motor driver Driver moteur motion control contrôle de mouvement monitor moniteur timing and control relation temps et commande image processor processeur d'image ADC CAN data bus bus de données Power management gestion d'alimentation Core power alimentation coeur I/O power alimentation E/S system power alimentation système Flash/ROM Mémoire flash/ROM NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre data storage stockage de données Keypad clavier À cause du grand nombre de détecteurs qu'ils contiennent et de leurs caractéristiques avancées, les scanners PET ont besoin d'une solution de traitement frontal économique, souple, puissante et rapide. L'avantage d'utiliser des FPGA/PLD dans les scanners PET plutôt qu'un circuit intégré spécifique à l'application (ASIC) parait évident aux ingénieurs système. La reconfigurabilité en circuit (ICR) des dispositifs FPGA /PLD leur permet d'être configurés pour l'installation, reconfigurés pour le processus de détection effectif, et reconfigurés encore une fois pour réaliser des autodiagnostics, le cas échéant. Par exemple, pendant la configuration, l'ordinateur PC/104 programme les algorithmes d'étalonnage dans les dispositifs Altera, permettant ainsi à toutes les voies de traitement en bloc de réaliser l'étalonnage en même temps, réduisant ainsi la durée de configuration des détecteurs. La reconfigurabilité du dispositif FPGA/PLD lui permet de traiter facilement toutes ces fonctions. Il suffit de reconfigurer dans le système à chaque étape du processus. De même, la durée de traitement du signal reste minimale car le dispositif Altera peut accéder simultanément à tous les autres dispositifs du sous-système. Les dispositifs FPGA/PLD pouvant être facilement reconfigurés dans le système, ils représentent le meilleur choix pour la plupart des scanner PET haute résolution. Ils peuvent mettre en oeuvre la configuration, le processus de détection et un autodiagnostic dans les mêmes dispositifs FPGA/PLD, et permettent ainsi de raccourcir les temps de développement, d'économiser de l'espace au niveau des cartes et de réduire la consommation et les coûts d'énergie. Ils offrent également l'avantage supplémentaire d'un support garanti en cas de modifications futures éventuelles des exigences ou de la configuration du système. Tensiomètre avec microcontrôleurs Un microcontrôleur est conçu pour les applications haute précision en temps réel portables qui ont besoin d'un circuit intégré avec une grande mémoire. Il est utilisé en général dans les tensiomètres, les moniteurs du rythme cardiaque, les analyseurs de sang, les thermomètres numériques, les oxymètres de pouls, etc. Le système mesure la pression artérielle par l'une de trois méthodes, c'est-à-dire Korotkoff, oscillométrie ou pouls. À l'aide d'un brassard, d'une pompe et d'un transducteur, il mesure la pression artérielle et le rythme cardiaque en trois étapes : gonflement, mesure, et dégonflement. Il comporte un écran LCD, des boutons de sélection, un rappel de mémoire, une gestion d'alimentation et une interface USB. NOUVEAU Le site Produits électroniques de Premier Farnell maintenant consultable en Chinois - Essayez dès AUJOURD'HUI !! http://www.farnell.com/ Premier Farnell Global Technology Centre LCD display afficheur LCD LED display afficheur LED air pressure control commande de pression d'air Precision amp ampli de précision Pressure transducer transducteur de pression audio amp ampli audio MCU processor processeur MCU LCD ctrl commande LCD speaker haut-parleur I/O port LED driver port E/S Driver de LED I/O port keypad port E/S clavier I/O port air pressure control port E/S Commande de pression d'air ADC can data bus bus de données Power charger/management Chargeur/gestion d'alimentation USB controller wired data transmission Contrôleur USB - transmission de données filaire Flash/ROM Mémoire flash/ROM Présentation du modèle : Processeur MCU : commande du système, traitement des données. Mémoire flash : données et consignes d'enregistrement. Interface utilisateur : manipulation par l'utilisateur et affichage des résultats. Capteur : conversion de la pression en signal électronique Modèle AFE : amplification et numérisation du signal analogique Alimentation : électrique. NOUVEAU Le site Produits électroniques de P