cree® Xlamp® XP-e2 leds - PDF - Farnell Element 14 - Revenir à l'accueil

Branding Farnell element14 (France)

 

Farnell Element 14 :

Miniature

Everything You Need To Know About Arduino

Miniature

Tutorial 01 for Arduino: Getting Acquainted with Arduino

Miniature

The Cube® 3D Printer

Miniature

What's easier- DIY Dentistry or our new our website features?

 

Miniature

Ben Heck's Getting Started with the BeagleBone Black Trailer

Miniature

Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

Miniature

Get Started with Pi Episode 3 - Online with Raspberry Pi

Miniature

Discover Simulink Promo -- Exclusive element14 Webinar

Miniature

Ben Heck's TV Proximity Sensor Trailer

Miniature

Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

Miniature

Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

Miniature

Ben Heck Anti-Pickpocket Wallet Trailer

Miniature

Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

Miniature

Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

Miniature

Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

Miniature

Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

Miniature

3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

Miniature

3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

Miniature

Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

Miniature

Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

Miniature

Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

Miniature

Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

Miniature

Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

Miniature

Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

Miniature

Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

Miniature

3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

Miniature

Innovative LPS Resistor Features Very High Power Dissipation

Miniature

Charge Injection Evaluation Board for DG508B Multiplexer Demo

Miniature

Ben Heck The Great Glue Gun Trailer Part 2

Miniature

Introducing element14 TV

Miniature

Ben Heck Time to Meet Your Maker Trailer

Miniature

Détecteur de composants

Miniature

Recherche intégrée

Miniature

Ben Builds an Accessibility Guitar Trailer Part 1

Miniature

Ben Builds an Accessibility Guitar - Part 2 Trailer

Miniature

PiFace Control and Display Introduction

Miniature

Flashmob Farnell

Miniature

Express Yourself in 3D with Cube 3D Printers from Newark element14

Miniature

Farnell YouTube Channel Move

Miniature

Farnell: Design with the best

Miniature

French Farnell Quest

Miniature

Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

Miniature

Cy-Net3 Network Module

Miniature

MC AT - Professional and Precision Series Thin Film Chip Resistors

Miniature

Solderless LED Connector

Miniature

PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

Miniature

3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

Miniature

Voltage Level Translation

Puce électronique / Microchip :

Miniature

Microchip - 8-bit Wireless Development Kit

Miniature

Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

Miniature

Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

Miniature

Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

Miniature

Microchip - 8-bit Wireless Development Kit

Miniature

Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

Miniature

Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

Miniature

Texas Instruments - Automotive LED Headlights

Miniature

Texas Instruments - Digital Power Solutions

Miniature

Texas Instruments - Industrial Sensor Solutions

Miniature

Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

Miniature

Texas Instruments - Industrial Automation System Components

Miniature

Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

Miniature

Texas Instruments - TMS320C66x KeyStone Multicore Architecture

Miniature

Texas Instruments - Industrial Interfaces

Miniature

Texas Instruments - Concerto™ MCUs - Connectivity without compromise

Miniature

Texas Instruments - Stellaris Robot Chronos

Miniature

Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

Miniature

Ask Ben Heck - Connect Raspberry Pi to Car Computer

Miniature

Ben's Portable Raspberry Pi Computer Trailer

Miniature

Ben's Raspberry Pi Portable Computer Trailer 2

Miniature

Ben Heck's Pocket Computer Trailer

Miniature

Ask Ben Heck - Atari Computer

Miniature

Ask Ben Heck - Using Computer Monitors for External Displays

Miniature

Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

Miniature

Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

Miniature

Raspberry Pi Served - Joey Hudy

Miniature

Happy Birthday Raspberry Pi

Miniature

Raspberry Pi board B product overview

Logiciels :

Miniature

Ask Ben Heck - Best Opensource or Free CAD Software

Miniature

Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

Miniature

Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

Miniature

Introduction to Cadsoft EAGLE PCB Design Software in Chinese

Miniature

Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

Miniature

Ben Heck The Great Glue Gun Trailer Part 1

Miniature

the knode tutorial - element14

Miniature

Ben's Autodesk 123D Tutorial Trailer

Miniature

Ben's CadSoft EAGLE Tutorial Trailer

Miniature

Ben Heck's Soldering Tutorial Trailer

Miniature

Ben Heck's AVR Dev Board tutorial

Miniature

Ben Heck's Pinball Tutorial Trailer

Miniature

Ben Heck's Interface Tutorial Trailer

Miniature

First Stage with Python and PiFace Digital

Miniature

Cypress - Getting Started with PSoC® 3 - Part 2

Miniature

Energy Harvesting Challenge

Miniature

New Features of CadSoft EAGLE v6

Documents PDF :

[TXT]

 Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04  2.1M  

[TXT]

 Farnell-USB1T11A-PDF..> 19-Mar-2014 18:03  2.1M  

[TXT]

 Farnell-OSLON-SSL-Ce..> 19-Mar-2014 18:03  2.1M  

[TXT]

 Farnell-Atmel-ATmega..> 19-Mar-2014 18:03  2.2M  

[TXT]

 Farnell-PBSS5160T-60..> 19-Mar-2014 18:03  2.1M  

[TXT]

 Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02  2.5M  

[TXT]

 Farnell-Ed.081002-DA..> 19-Mar-2014 18:02  2.5M  

[TXT]

 Farnell-Instructions..> 19-Mar-2014 18:01  2.5M  

[TXT]

 Farnell-Serie-PicoSc..> 19-Mar-2014 18:01  2.5M  

[TXT]

 Farnell-ECO-Series-T..> 19-Mar-2014 18:00  2.5M  

[TXT]

 Farnell-F42202-PDF.htm  19-Mar-2014 18:00  2.5M  

[TXT]

 Farnell-propose-plus..> 11-Mar-2014 08:19  2.8M  

[TXT]

 Farnell-Haute-vitess..> 11-Mar-2014 08:17  2.4M  

[TXT]

 Farnell-Controle-de-..> 11-Mar-2014 08:16  2.8M  

[TXT]

 Farnell-NXP-TEA1703T..> 11-Mar-2014 08:15  2.8M  

[TXT]

 Farnell-XPS-MC16-XPS..> 11-Mar-2014 08:15  2.8M  

[TXT]

 Farnell-MC21605-PDF.htm 11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-WetTantalum-..> 11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-ES2333-PDF.htm  11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-SB175-Connec..> 11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13  2.8M  

[TXT]

 Farnell-YAGEO-DATA-S..> 11-Mar-2014 08:13  2.8M  

[TXT]

 Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55  2.1M  

[TXT]

 Farnell-NXP-PCA9555 ..> 11-Mar-2014 07:54  2.2M  

[TXT]

 Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54  2.2M  

[TXT]

 Farnell-Microship-PI..> 11-Mar-2014 07:53  2.2M  

[TXT]

 Farnell-EPCOS-Sample..> 11-Mar-2014 07:53  2.2M  

[TXT]

 Farnell-NXP-BT136-60..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-NTE_SEMICOND..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-L-efficacite..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-LUXEON-Guide..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-Realiser-un-..> 11-Mar-2014 07:51  2.3M  

[TXT]

 Farnell-SOT-23-Multi..> 11-Mar-2014 07:51  2.3M  

[TXT]

 Farnell-ZigBee-ou-le..> 11-Mar-2014 07:50  2.4M  

[TXT]

 Farnell-Les-derniers..> 11-Mar-2014 07:50  2.3M  

[TXT]

 Farnell-Conception-d..> 11-Mar-2014 07:49  2.4M  

[TXT]

 Farnell-Puissance-ut..> 11-Mar-2014 07:49  2.4M  

[TXT]

 Farnell-MOLEX-43160-..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-MOLEX-87439-..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-MOLEX-43020-..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-NXP-PBSS9110..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-TEKTRONIX-DP..> 10-Mar-2014 17:20  2.0M  

[TXT]

 Farnell-uC-OS-III-Br..> 10-Mar-2014 17:20  2.0M  

[TXT]

 Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20  2.1M  

[TXT]

 Farnell-NXP-PSMN7R0-..> 10-Mar-2014 17:19  2.1M  

[TXT]

 Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19  1.9M  

[TXT]

 Farnell-manual-bus-p..> 10-Mar-2014 16:29  1.9M  

[TXT]

 Farnell-Molex-Crimp-..> 10-Mar-2014 16:27  1.7M  

[TXT]

 Farnell-The-essentia..> 10-Mar-2014 16:27  1.7M  

[TXT]

 Farnell-OMRON-Master..> 10-Mar-2014 16:26  1.8M  

[TXT]

 Farnell-Proskit-SS-3..> 10-Mar-2014 16:26  1.8M  

[TXT]

 Farnell-BYV79E-serie..> 10-Mar-2014 16:19  1.6M  

[TXT]

 Farnell-NXP-74VHC126..> 10-Mar-2014 16:17  1.6M  

[TXT]

 Farnell-NXP-PSMN1R7-..> 10-Mar-2014 16:17  1.6M  

[TXT]

 Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17  1.6M  

[TXT]

 Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17  1.7M  

[TXT]

 Farnell-NXP-PMBFJ620..> 10-Mar-2014 16:16  1.7M  

[TXT]

 Farnell-Pico-Spox-Wi..> 10-Mar-2014 16:16  1.7M  

[TXT]

 Farnell-Tektronix-AC..> 10-Mar-2014 15:52  1.5M

 

Product family data sheet Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. CLD-DS56 Rev 4 Cree® XLamp® XP-E2 LEDs Product Description The XLamp XP-E2 LED builds on the unprecedented performance of the original XP-E by increasing lumen output up to 20% while providing a single die LED point source for precise optical control. The XP‑E2 LED shares the same footprint as the original XP‑E, providing a seamless upgrade path to more lumens and/or greater efficiency while shortening the design cycle for existing XP customers. XLamp XP-E2 LEDs are the ideal choice for lighting applications where high light output and maximum efficacy are required, such as LED retrofit lamps, outdoor, portable, indoor directional, emergency vehicle or architectural. FEATURES • Available in white, outdoor white, 80-CRI, 85-CRI, 90-CRI white, royal blue, blue, green, amber, red-orange & red • ANSI-compatible chromaticity bins • White binned at 85 °C • Maximum drive current: 1 A • Low thermal resistance: as low as 5 °C/W • Wide viewing angle: 110°-135° • Unlimited floor life at ≤ 30 °C/85% RH • Reflow solderable - JEDEC J-STD-020C compatible • Electrically neutral thermal path • UL-recognized component (E349212) www.cree.com/Xlamp Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 Table of Contents Characteristics........................... 2 Flux Characteristics - White......... 3 Flux Characteristics - Color.......... 4 Relative Spectral Power Distribution............................... 6 Relative Flux vs. Junction Temperature.............................. 7 Electrical Characteristics.............. 8 Relative Flux vs. Current............. 9 Relative Chromaticity vs. Current and Temperature.......................10 Typical Spatial Distribution..........11 Thermal Design.........................12 Reflow Soldering Characteristics..13 Notes.......................................14 Mechanical Dimensions..............15 Tape and Reel...........................16 Packaging.................................17 Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 2 xlamp xp-e2 leds Characteristics Characteristics Unit Minimum Typical Maximum Thermal resistance, junction to solder point - white, royal blue, blue °C/W 9 Thermal resistance, junction to solder point - green °C/W 15 Thermal resistance, junction to solder point - amber °C/W 7 Thermal resistance, junction to solder point - red-orange, red °C/W 5 Viewing angle (FWHM) - white degrees 110 Viewing angle (FWHM) - royal blue, blue, green degrees 135 Viewing angle (FWHM) - amber, red-orange, red degrees 130 Temperature coefficient of voltage - white mV/°C -2.3 Temperature coefficient of voltage - royal blue, blue mV/°C -3.3 Temperature coefficient of voltage - green mV/°C -3.8 Temperature coefficient of voltage - amber, red-orange, red mV/°C -1.8 ESD withstand voltage (HBM per Mil-Std-883D)- white, royal blue, blue, green V 8000 ESD classification (HBM per Mil-Std-883D) - amber, red-orange, red Class 2 DC forward current mA 1000 Reverse voltage V 5 Forward voltage (@ 350 mA, 85 °C) - white V 2.9 3.25 Forward voltage (@ 700 mA, 85 °C) - white 3.05 Forward voltage (@ 1000 mA, 85 °C) - white 3.15 Forward voltage (@ 350 mA, 25 °C) - royal blue, blue V 3.1 3.5 Forward voltage (@ 350 mA, 25 °C) - green V 3.2 3.6 Forward voltage (@ 350 mA, 25 °C) - amber, red-orange, red V 2.2 2.6 Forward voltage (@ 1000 mA, 25 °C) - royal blue, blue V 3.4 Forward voltage (@ 1000 mA, 25 °C) - green V 3.7 Forward voltage (@ 1000 mA, 25 °C) - amber, red-orange, red V 2.65 LED junction temperature °C 150 Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 3 xlamp xp-e2 leds Flux Characteristics (TJ = 85 °C) - White The following table provides several base order codes for XLamp XP-E2 LEDs. It is important to note that the base order codes listed here are a subset of the total available order codes for the product family. For more order codes, as well as a complete description of the order-code nomenclature, please consult the XLamp XP Family Binning and Labeling document. Color CCT Range Base Order Codes Min. Luminous Flux (lm) @ 350 mA Calculated Minimum Luminous Flux (lm)** @ 85 °C Order Code Min. Max. Group Flux (lm) @ 85 °C Flux (lm) @ 25 °C* 700 mA 1.0 A Cool White 5000 K 10,000 K Q4 100 116 171 218 XPEBWT-L1-0000-00C51 Q5 107 124 183 233 XPEBWT-L1-0000-00D51 R2 114 132 195 249 XPEBWT-L1-0000-00E51 R3 122 142 209 266 XPEBWT-L1-0000-00F51 Outdoor White 4000 K 5300 K Q4 100 116 171 218 XPEBWT-01-0000-00CC2 Q5 107 124 183 233 XPEBWT-01-0000-00DC2 R2 114 132 195 249 XPEBWT-01-0000-00EC2 R3 122 142 209 266 XPEBWT-01-0000-00FC2 Neutral White 3700 K 5300 K Q4 100 116 171 218 XPEBWT-L1-0000-00CE4 Q5 107 124 183 233 XPEBWT-L1-0000-00DE4 R2 114 132 195 249 XPEBWT-L1-0000-00EE4 80-CRI White 2200 K 4300 K Q2 87.4 101 150 191 XPEBWT-H1-0000-00AE7 Q3 93.9 109 161 205 XPEBWT-H1-0000-00BE7 Warm White 2200 K 3700 K Q2 87.4 101 150 191 XPEBWT-L1-0000-00AE7 Q3 93.9 109 161 205 XPEBWT-L1-0000-00BE7 Q4 100 116 171 218 XPEBWT-L1-0000-00CE7 85-CRI White 2600 K 3200 K P2 67.2 78.0 115 147 XPEBWT-P1-0000-007E7 P3 73.9 85.7 127 161 XPEBWT-P1-0000-008E7 P4 80.6 93.5 138 176 XPEBWT-P1-0000-009E7 Q2 87.4 101 150 191 XPEBWT-P1-0000-00AE7 90-CRI White 2600 K 3200 K P2 67.2 78.0 115 147 XPEBWT-U1-0000-007E7 P3 73.9 85.7 127 161 XPEBWT-U1-0000-008E7 P4 80.6 93.5 138 176 XPEBWT-U1-0000-009E7 Notes: • Cree maintains a tolerance of ± 7% on flux and power measurements, ±0.005 on chromaticity (CCx, CCy) measurements and ±2 on CRI measurements. • Typical CRI for Cool White (5000 K – 10,000 K CCT) is 70. • Typical CRI for Neutral White (3700 K – 5300 K CCT) is 75. • Typical CRI for Outdoor White (4000 K - 5300 K CCT) is 70. • Typical CRI for Warm White (2200 K – 3700 K CCT) is 80. • Minimum CRI for 80-CRI White is 80. • Minimum CRI for 85-CRI White is 85. • Minimum CRI for 90-CRI White is 90. * Flux values @ 25 °C are calculated and for reference only. ** Calculated flux values at 700 mA and 1 A are for reference only. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 4 xlamp xp-e2 leds Flux Characteristics (TJ = 25 °C) - Color The following table provides several base order codes for XLamp XP-E2 color LEDs. It is important to note that the base order codes listed here are a subset of the total available order codes for the product family. For more order codes, as well as a complete description of the order-code nomenclature, please consult the XLamp XP Family Binning and Labeling document. Color Minimum Radiant Flux @ 350 mA Dominant Wavelength Range Order Codes, Group Flux (mW) Min. Max. Group DWL (nm) Group DWL (nm) Royal Blue 30 450 D3 450 D5 465 XPEBRY-L1-0000-00J01 31 475 D3 450 D5 465 XPEBRY-L1-0000-00K01 32 500 D3 450 D5 465 XPEBRY-L1-0000-00L01 33 525 D3 450 D5 465 XPEBRY-L1-0000-00M01 34 550 D3 450 D5 465 XPEBRY-L1-0000-00N01 35 575 D3 450 D5 465 XPEBRY-L1-0000-00P01 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Blue B3 465 B6 485 K2 30.6 XPEBBL-L1-0000-00Y01 K3 35.2 XPEBBL-L1-0000-00Z01 M2 39.8 XPEBBL-L1-0000-00201 M3 45.7 XPEBBL-L1-0000-00301 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Green G2 520 G4 535 Q2 87.4 XPEBGR-L1-0000-00A01 Q3 93.9 XPEBGR-L1-0000-00B01 Q4 100 XPEBGR-L1-0000-00C01 Q5 107 XPEBGR-L1-0000-00D01 R2 114 XPEBGR-L1-0000-00E01 R3 122 XPEBGR-L1-0000-00F01 Note: Cree maintains a tolerance of ± 7% on flux and power measurements and ± 1 nm on dominant wavelength measurements. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 5 xlamp xp-e2 leds Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Amber A2 585 A3 595 N4 62.0 XPEBAM-L1-0000-00601 P2 67.2 XPEBAM-L1-0000-00701 P3 73.9 XPEBAM-L1-0000-00801 P4 80.6 XPEBAM-L1-0000-00901 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Red- Orange O3 610 O4 620 P2 67.2 XPEBRO-L1-0000-00701 P3 73.9 XPEBRO-L1-0000-00801 P4 80.6 XPEBRO-L1-0000-00901 Q2 87.4 XPEBRO-L1-0000-00A01 Q3 93.9 XPEBRO-L1-0000-00B01 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Red R2 620 R3 630 N3 56.8 XPEBRD-L1-0000-00501 N4 62.0 XPEBRD-L1-0000-00601 P2 67.2 XPEBRD-L1-0000-00701 P3 73.9 XPEBRD-L1-0000-00801 Note: Cree maintains a tolerance of ± 7% on flux and power measurements and ± 1 nm on dominant wavelength measurements. Flux Characteristics (TJ = 25 °C) - Color (Continued) Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 6 xlamp xp-e2 leds Relative Spectral Power Distribution Relative Spectral Power 0 10 20 30 40 50 60 70 80 90 100 380 430 480 530 580 630 680 730 780 Relative Radiant Power (%) Wavelength (nm) Cool White Warm White Relative Spectral Power 0 20 40 60 80 100 380 430 480 530 580 630 680 730 780 Relative Radiant Power (%) Wavelength (nm) Royal Blue Blue Green Amber Red-Orange Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 7 xlamp xp-e2 leds Relative Flux vs. Junction Temperature (IF = 350 mA) Relative Flux Output vs. Junction Temperature 0 20 40 60 80 100 120 25 50 75 100 125 150 Relative Luminous Flux (%) Junction Temperature (ºC) White Relative Flux Output vs. Junction Temperature 0 10 20 30 40 50 60 70 80 90 100 25 50 75 100 125 150 Relative Radiant Flux (%) Junction Temperature (ºC) Royal Blue Relative Flux Output vs. Junction Temperature 0 10 20 30 40 50 60 70 80 90 100 25 50 75 100 125 150 Relative Luminous Flux (%) Junction Temperature (ºC) Blue Green Amber Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 8 xlamp xp-e2 leds Electrical Characteristics (TJ = 85 °C) Electrical Characteristics (TJ = 25 °C) Electrical Characteristics (Tj = 25ºC) 0 100 200 300 400 500 600 700 800 900 1000 2.7 2.8 2.9 3.0 3.1 3.2 Forward Current (mA) Forward Voltage (V) White Electrical Characteristics (Tj = 85ºC) 0 100 200 300 400 500 600 700 800 900 1000 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 Forward Current (mA) Forward Voltage (V) Royal Blue, Blue Green Amber, Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 9 xlamp xp-e2 leds Relative Flux vs. Current (TJ = 85 °C) Relative Flux vs. Current (TJ = 25 °C) Relative Intensity vs. Current (Tj = 85ºC) 0 50 100 150 200 250 0 100 200 300 400 500 600 700 800 900 1000 Relative Luminous Flux (%) Forward Current (mA) White Relative Intensity vs. Current (Tj = 85ºC) 0 50 100 150 200 250 0 100 200 300 400 500 600 700 800 900 1000 Relative Radiant Flux (%) Forward Current (mA) Royal Blue Relative Intensity vs. Current (Tj = 85ºC) 0 50 100 150 200 250 300 0 100 200 300 400 500 600 700 800 900 1000 Relative Luminous Flux (%) Forward Current (mA) Blue Green Amber Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 10 xlamp xp-e2 leds Relative Chromaticity vs. Current and Temperature - Warm White* * Warm White XLamp XP-E2 LEDs have a typical CRI of 80. Relative Chromaticity Vs. Current, WW -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0 100 200 300 400 500 600 700 800 900 1000 Current (mA) ΔCCx ΔCCy T J = 85 °C Relative Chromaticity Vs. Temperature WW -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0 20 40 60 80 100 120 140 160 Tsp (°C) ΔCCx ΔCCy I F = 350 mA Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 11 xlamp xp-e2 leds Typical Spatial Distribution Typical Spatial Radiation Pattern 0 20 40 60 80 100 -90 -70 -50 -30 -10 10 30 50 70 90 Relative Luminous Intensity (%) Angle (°) White Typical Spatial Radiation Pattern 0 20 40 60 80 100 -90 -70 -50 -30 -10 10 30 50 70 90 Relative Luminous Intensity (%) Angle (º) Royal Blue, Blue, Green Amber, Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 12 xlamp xp-e2 leds Thermal Design The maximum forward current is determined by the thermal resistance between the LED junction and ambient. It is crucial for the end product to be designed in a manner that minimizes the thermal resistance from the solder point to ambient in order to optimize lamp life and optical characteristics. White R oyal Blue, Blue Green A mber, Red-Orange, Red 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Thermal Design - royal blue - same as blue 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Thermal Design - amber, red-orange, red 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Thermal Design - green 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 20°C/W Rj-a = 25°C/W Rj-a = 30°C/W Rj-a = 35°C/W Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 13 xlamp xp-e2 leds Reflow Soldering Characteristics In testing, Cree has found XLamp XP-E2 LEDs to be compatible with JEDEC J-STD-020C, using the parameters listed below. As a general guideline, Cree recommends that users follow the recommended soldering profile provided by the manufacturer of solder paste used. Note that this general guideline may not apply to all PCB designs and configurations of reflow soldering equipment. Profile Feature Lead-Based Solder Lead-Free Solder Average Ramp-Up Rate (Tsmax to Tp) 3 °C/second max. 3 °C/second max. Preheat: Temperature Min (Tsmin) 100 °C 150 °C Preheat: Temperature Max (Tsmax) 150 °C 200 °C Preheat: Time (tsmin to tsmax) 60-120 seconds 60-180 seconds Time Maintained Above: Temperature (TL) 183 °C 217 °C Time Maintained Above: Time (tL) 60-150 seconds 60-150 seconds Peak/Classification Temperature (Tp) 215 °C 260 °C Time Within 5 °C of Actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-Down Rate 6 °C/second max. 6 °C/second max. Time 25 °C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package, measured on the package body surface. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 14 xlamp xp-e2 leds Notes Lumen Maintenance Projections Cree now uses standardized IES LM-80-08 and TM-21-11 methods for collecting long-term data and extrapolating LED lumen maintenance. For information on the specific LM-80 data sets available for this LED, refer to the public LM-80 results document at www.cree.com/xlamp_app_notes/LM80_results. Please read the XLamp Long-Term Lumen Maintenance application note at www.cree.com/xlamp_app_notes/lumen_ maintenance for more details on Cree’s lumen maintenance testing and forecasting. Please read the XLamp Thermal Management application note at www.cree.com/xlamp_app_notes/thermal_management for details on how thermal design, ambient temperature, and drive current affect the LED junction temperature. Moisture Sensitivity In testing, Cree has found XLamp XP-E2 LEDs to have unlimited floor life in conditions ≤ 30 ºC/85% relative humidity (RH). Moisture testing included a 168-hour soak at 85 ºC/85% RH followed by 3 reflow cycles, with visual and electrical inspections at each stage. Cree recommends keeping XLamp LEDs in their sealed moisture-barrier packaging until immediately prior to use. Cree also recommends returning any unused LEDS to the resealable moisture-barrier bag and closing the bag immediately after use. UL Recognized Component Level 4 enclosure consideration. The LED package or a portion thereof has been investigated as a fire and electrical enclosure per ANSI/UL 8750. Vision Advisory Claim WARNING: Do not look at exposed lamp in operation. Eye injury can result. See LED Eye Safety at www.cree.com/ xlamp_app_notes/led_eye_safety. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 15 xlamp xp-e2 leds Mechanical Dimensions All measurements are ±.13 mm unless otherwise indicated. Anode Anode THIRD ANGLE PROJECTION A B C D 6 5 4 3 6 5 4 3 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE X° ± .5 .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS .XX ± .25 .XXX ± .125 X° ± .5 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 2.36 RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION 6 5 4 3 2 PERSON WITHOUT THE WRITTEN CONSENT COPIED, REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL. THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 3.30 .50 2.30 3.30 1.30 2.36 OUTLINE D. CRONIN 07/19/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DRAWING DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION 6 5 4 3 2 PERSON WITHOUT THE WRITTEN CONSENT REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT ARE THE PROPRIETARY AND THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: .50 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 3.30 .50 2.30 3.30 1.30 2.36 OUTLINE D. CRONIN 07/19/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION 5 4 3 2 WITHOUT THE WRITTEN CONSENT REPRODUCED OR DISCLOSED TO ANY OF CREE, INC. THIS PLOT PROPRIETARY AND PLOT AND THE INFORMATION X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: .50 1.30 3.30 3.30 1.15 .65 1.65 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 3.30 .50 2.30 3.30 1.30 2.36 2610-OUTLINE DRAWING D. CRONIN 07/19/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE OF REV. SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 3 2 1 A B C Phone (919) 313-5300 Fax (919) 313-5558 4600 Silicon Drive Durham, N.C 27703 X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 1.20 .60 3.20 1.60 3.20 .40 .65 1.30 22.000 1 /1 2610-00029 A OUTLINE DRAWING XPE G2 D. CRONIN 07/19/12 RECOMMENDED STENCIL PATTERN AREA IS OPENING) Top View Side View Bottom View Recommended PCB Solder Pad Recommended Stencil Pattern Hatched Area is Opening Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 16 xlamp xp-e2 leds Tape and Reel All Cree carrier tapes conform to EIA-481D, Automated Component Handling Systems Standard. All dimensions in mm. Loaded Pockets (1,000 Lamps) Leader 400mm (min) of empty pockets with at least 100mm sealed by tape (50 empty pockets min.) Trailer 160mm (min) of empty pockets sealed with tape (20 pockets min.) END START Cathode Side Anode Side (denoted by + and circle) 2.5±.1 1.5±.1 8.0±.1 4.0±.1 1.75±.10 12.0 .0 +.3 DETAIL B SCALE 2 : 1 13mm 7" Cover Tape Pocket Tape User Feed Direction User Feed Direction 13 61 12.40 0 +2.00 MEASURED AT HUB 12.40 MEASURED AT INSIDE EDGE 16.40 TITLE DATE DATE DATE CHECK MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION .X ± 0.3 .XX ± .13 X° ± 1° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS & BEFORE FINISH. TOLERANCE UNLESS SPECIFIED: A B C D 6 5 4 3 2 1 A B C D Phone (919) 361-4770 4600 Silicon Drive Durham, N.C 27703 NOTICE CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT OF CREE, INC. Reel, 7" x 12mm Wide LIUDEZHI 2012/5/25 +/-0.5 190 ½öÓÃÓÚÆÀ¹À¡£ °æȨËùÓÐ (c) by Foxit Software Company, 2004 ÓÉ Foxit PDF Editor ±à¼- OD 7.5'' 13 61 12.40 0 +2.00 MEASURED AT HUB 12.40 16.40 B C D 6 5 4 3 2 1 B C D NOTICE CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT OF CREE, INC. +/-0.5 190 ½öÓÃÓÚÆÀ¹À¡£ °æȨËùÓÐ (c) by Foxit Software Company, 2004 ÓÉ Foxit PDF Editor ±à¼- OD 7.5'' Y Y X X REF 0.59 F(III) D1 P1 1.5 MIN. Bo Ao R0.2 TYPICAL REF 4.375 Ko (IV) Other material available. (III) (II) (I) hole to centerline of pocket. Measured from centerline of sprocket holes is ± 0.20. Cumulative tolerance of 10 sprocket to centerline of pocket. Measured from centerline of sprocket hole SECTION Y-Y SECTION X-X ±0.05 Do 1.75 E1 REF R 2.24 Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 Y Y X X REF 0.59 W F(III) D1 P1 1.5 MIN. Bo Ao R0.2 TYPICAL REF 4.375 Ko (IV) Other material available. (III) (II) (I) hole to centerline of pocket. Measured from centerline of sprocket holes is ± 0.20. Cumulative tolerance of 10 sprocket to centerline of pocket. Measured from centerline of sprocket hole SECTION Y-Y SECTION X-X 2.0 ±0.05 (I) P2 1.55 ±0.05 Do 4.0 ±0.1 (II) Po 1.75 ±0.1 E1 T 0.30 ±0.05 REF R 2.24 Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 Y Y D1 1.5 MIN. Bo R0.2 TYPICAL REF 4.375 Ko SECTION Y-Y 0.05 REF Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 CATHODE SIDE ANODE SIDE Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 17 xlamp xp-e2 leds Packaging Patent Label (on bottom of box) Label with Cree Bin Code, Qty, Reel ID Label with Cree Bin Code, Qty, Reel ID Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Bin Code, Qty, Reel ID Unpackaged Reel Packaged Reel Boxed Reel CREE Bin Code & Barcode Label Vacuum-Sealed Moisture Barrier Bag Label with Customer P/N, Qty, Lot #, PO # Label with Cree Bin Code, Qty, Lot # Label with Cree Bin Code, Qty, Lot # Vacuum-Sealed Moisture Barrier Bag Patent Label Label with Customer Order Code, Qty, Reel ID, PO # Ideal for power supply 1a/1c/2a/2c/5A/10A power relays JW RELAYS VDE RoHS compliant FEATURES • Miniature package with universal terminal footprint • High dielectric withstanding for transient protection: 10,000 V surge in μs between coil and contact • Sealed construction • Class B coil insulation types available • TV rated (TV-5) types available (only for 1 Form A type) • VDE, TÜV, SEMKO, SEV, FIMKO, TV-5 also approved • Sockets are available. TYPICAL APPLICATIONS 1. Home appliances TV sets, VCR, Microwave ovens 2. Office machines Photocopiers, Vending machines 3. Industrial equipment NC machines, Robots, Temperature controllers Contact arrangement 1: 1a: 2: 2a: 1 Form C 1 Form A 2 Form C 2 Form A Contact capacity Nil: F: Standard (5 A) High capacity (10 A)* JW N Protective construction S: H: Sealed type Flux-resistant type Coil insulation class Nil: B: Class E insulation Class B insulation Pick-up voltage N: 70% of nominal voltage Nominal coil voltage DC5V, DC6V, DC9V, DC12V, DC24V, DC48V Contact material F: AgSnO2 type (1a) Nil: AgNi type (1c, 2a, 2c) *Only for 1 Form A and 1 Form C type Certified by UL, CSA, VDE, SEMKO, FIMKO and SEV Note: When ordering TV rated (TV-5) types, add suffix-TV (available only for 1 Form A type). Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T TYPES * For sockets, see page 140. RATING 1. Coil data Nominal coil voltage Pick-up voltage (at 20°C 68°F) Drop-out voltage (at 20°C 68°F) Nominal operating current [±10%] (at 20°C 68°F) Coil resistance [±10%] (at 20°C 68°F) Nominal operating power Max. applied voltage (at 20°C 68°F) 5V DC 70%V or less of nominal voltage (Initial) 10%V or more of nominal voltage (Initial) 106mA 47Ω 530mW 130%V of nominal voltage (at 60°C 140°F) 120%V of nominal voltage (at 85°C 185°F)*4 6V DC 88mA 68Ω 9V DC 58mA 155Ω 12V DC 44mA 270Ω 24V DC 22mA 1,100Ω 48V DC 11mA 4,400Ω 1) 1 Form A Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. 2) 1 Form A High capacity (10 A) type Standard packing: Carton 100 pcs. Case 500 pcs. Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1aSN-DC5V-F JW1aHN-DC5V-F 6V DC JW1aSN-DC6V-F JW1aHN-DC6V-F 9V DC JW1aSN-DC9V-F JW1aHN-DC9V-F 12V DC JW1aSN-DC12V-F JW1aHN-DC12V-F 24V DC JW1aSN-DC24V-F JW1aHN-DC24V-F 48V DC JW1aSN-DC48V-F JW1aHN-DC48V-F Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1aFSN-DC5V-F JW1aFHN-DC5V-F 6V DC JW1aFSN-DC6V-F JW1aFHN-DC6V-F 9V DC JW1aFSN-DC9V-F JW1aFHN-DC9V-F 12V DC JW1aFSN-DC12V-F JW1aFHN-DC12V-F 24V DC JW1aFSN-DC24V-F JW1aFHN-DC24V-F 48V DC JW1aFSN-DC48V-F JW1aFHN-DC48V-F 3) 1 Form C Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. 4) 1 Form C High capacity (10 A) type Standard packing: Carton 100 pcs. Case 500 pcs. Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1SN-DC5V JW1HN-DC5V 6V DC JW1SN-DC6V JW1HN-DC6V 9V DC JW1SN-DC9V JW1HN-DC9V 12V DC JW1SN-DC12V JW1HN-DC12V 24V DC JW1SN-DC24V JW1HN-DC24V 48V DC JW1SN-DC48V JW1HN-DC48V Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1FSN-DC5V JW1FHN-DC5V 6V DC JW1FSN-DC6V JW1FHN-DC6V 9V DC JW1FSN-DC9V JW1FHN-DC9V 12V DC JW1FSN-DC12V JW1FHN-DC12V 24V DC JW1FSN-DC24V JW1FHN-DC24V 48V DC JW1FSN-DC48V JW1FHN-DC48V 5) 2 Form A Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. 6) 2 Form C Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. Note: Class B coil insulation type is available. Ex) JW1aSN-B-DC12V-F Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW2aSN-DC5V JW2aHN-DC5V 6V DC JW2aSN-DC6V JW2aHN-DC6V 9V DC JW2aSN-DC9V JW2aHN-DC9V 12V DC JW2aSN-DC12V JW2aHN-DC12V 24V DC JW2aSN-DC24V JW2aHN-DC24V 48V DC JW2aSN-DC48V JW2aHN-DC48V Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW2SN-DC5V JW2HN-DC5V 6V DC JW2SN-DC6V JW2HN-DC6V 9V DC JW2SN-DC9V JW2HN-DC9V 12V DC JW2SN-DC12V JW2HN-DC12V 24V DC JW2SN-DC24V JW2HN-DC24V 48V DC JW2SN-DC48V JW2HN-DC48V Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T 2. Specifications * Specifications will vary with foreign standards certification ratings. Notes: *1. This value can change due to the switching frequency, environmental conditions, and desired reliability level, therefore it is recommended to check this with the actual load. *2. Wave is standard shock voltage of ±1.2×50μs according to JEC-212-1981 *3. The upper limit of the ambient temperature is the maximum temperature that can satisfy the coil temperature rise value. Refer to Usage, transport and storage conditions in NOTES. *4. The pick-up and drop out voltages rise approximately 0.4% for every 1°C 33.8°F given a standard ambient temperature of 20°C 68°F. Therefore, when using relays where the ambient temperature is high, please take into consideration the rise in pick-up and drop out voltages and keep the coil applied voltage within the maximum applied voltage. REFERENCE DATA Characteristics Item Specifications Standard type High capacity type Contact Contact material 1 Form A: AgSnO2 type 1 Form C, 2 Form A and 2 Form C: AgNi type Arrangement 1 Form A, 1 Form C, 2 Form A and 2 Form C 1 Form A and 1 Form C Contact resistance (Initial) Max. 100 mΩ (By voltage drop 6 V DC 1A) Rating Nominal switching capacity (resistive load) 5A 250V AC, 5A 30V DC 10A 250V AC, 10A 30V DC Max. switching power (resistive load) 1,250VA, 150W 2,500VA, 300W Max. switching voltage 250V AC, 30V DC Max. switching current 5A 10A Min. switching capacity (reference value)*1 100mA, 5V DC Electrical characteristics Insulation resistance (Initial) Min. 1,000MΩ (at 500V DC) Measurement at same location as “Breakdown voltage” section. Breakdown voltage (Initial) Between open contacts 1,000 Vrms for 1 min. (Detection current: 10 mA) Between contact and coil 5,000 Vrms for 1 min. (Detection current: 10 mA) Between contact sets 3,000 Vrms for 1 min. (2 Form A, 2 Form C) (Detection current: 10 mA) Temperature rise (coil) 1 Form A: Max. 45°C 113°F, 1 Form C, 2 Form A and 2 Form C: Max. 55°C 131°F (resistive method, with nominal coil voltage and at nominal switching capacity, at 20°C 68°F) 1 Form A: Max. 45°C 113°F, 1 Form C: Max. 55°C 131°F (resistive method, with nominal coil voltage and at nominal switching capacity, at 20°C 68°F) Surge breakdown voltage*2 (Between contact and coil) (Initial) 10,000 V Operate time (at nominal voltage) (at 20°C 68°F) Max. 15 ms (excluding contact bounce time.) Release time (at nominal voltage) (at 20°C 68°F) Max. 5 ms (excluding contact bounce time) (Without diode) Mechanical characteristics Shock resistance Functional 98 m/s2 (Half-wave pulse of sine wave: 11 ms; detection time: 10μs.) Destructive 980 m/s2 (Half-wave pulse of sine wave: 6 ms.) Vibration resistance Functional 10 to 55 Hz at double amplitude of 1.6 mm (Detection time: 10μs.) Destructive 10 to 55 Hz at double amplitude of 2.0 mm Expected life Mechanical (at 180 times/min.) Min. 5×106 Electrical (at 6 times/min.) Min. 105 (at resistive load) Conditions Conditions for operation, transport and storage*3 Ambient temperature*4: –40°C to +60°C –40°F to 140°F (Class E), (Class B: –40°C to +85°C –40°F to 185°F) Humidity: 5 to 85% R.H. (Not freezing and condensing at low temperature) Max. operating speed (at nominal switching capacity) Flux-resistant type: 20 times/min., Sealed type: 6 times/min. Unit weight Approx. 13 g .46 oz JW 1 Form A Standard (5A) type 1. Maximum operating power 2. Operate/release time Sample: JW1aSN-DC12V-F, 10 pcs. Ambient temperature: 20°C 68°F 3. Life curve 1 Form A Standard (5 A) type 10 100 10 100 1,000 1 Contact voltage, V AC resistive load DC resistive load Contact current, A 80 90 100 110 120 5 0 10 Min. Max. Min. x - x - Max. Coil applied voltage, %V Operate/release time, ms Operate time Release time 100 10 5 10 15 Contact current, A Life, ×104 250 V AC resistive load 30 V DC resistive load Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T JW 1 Form A High Capacity (10 A) type 1. Maximum operating power 2. Operate/release time Sample: JW1aFSN-DC12V, 10 pcs. Ambient temperature: 20°C 68°F 3. Life curve 10 100 10 100 1,000 1 Contact voltage, V AC resistive load DC resistive load Contact current, A 80 90 100 110 120 5 0 10 Min. Max. Min. x - x - Max. Coil applied voltage, %V Operate/release time, ms Operate time Release time 100 10 1 0 2 4 6 8 10 12 Contact current, A Life, ×104 250 V AC resistive load 30 V DC resistive load 4-(1). Coil temperature rise (Contact carrying current: 5A) Sample JW1aFSN-DC12V-F, 6 pcs. Point measured: Inside the coil 4-(2). Coil temperature rise (Contact carrying current: 10 A) Sample: JW1aFSN-DC12V-F, 6 pcs. Point measured: Inside the coil 100 120 140 160 10 20 30 40 50 60 70 0 Coil applied voltage, %V Temperature rise, °C 85°C 60°C 25°C 100 120 140 160 10 20 30 40 50 60 70 0 Coil applied voltage, %V Temperature rise, °C 85°C 60°C 25°C JW 1 Form C Standard (5 A) type 1-(3). Maximum operating power 2. Operate/release time Sample: JW1SN-DC12V-F, 6 pcs. Ambient temperature: 20°C 68°F JW 1 Form C High Capacity (10 A) type 1. Maximum operating power 10 10 100 1,000 1 0 Contact voltage, V AC resistive load (cosϕ = 1.0) Contact current, A Max. Min. 13 12 11 10 9 6 4 100 8 7 3 2 1 5 80 90 110 120 130 Max. Min. x - x - Coil applied voltage, %V Operate/release time, ms 10 10 100 1,000 1 0 Contact voltage, V AC resistive load (cosϕ = 1.0) Contact current, A JW 2 Form A Standard (5 A) type 1. Maximum operating power 2. Operate/release time Sample: JW2aSN-DC24V-F, 6 pcs. Ambient temperature: 20°C 68°F 10 10 100 1,000 1 0 Contact voltage, V AC resistive load (cosϕ = 1.0) Contact current, A 14 13 12 10 8 6 4 2 80 90 100 110 120 Min. x - x - Coil applied voltage, %V Operate/release time, ms Operate time Release time Max. Max. Min. Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T DIMENSIONS (mm inch) JW 2 Form C Standard (5 A) type 1. Maximum operating power 2. Operate/release time Sample: JW2SN-DC12V-F, 6 pcs. Ambient temperature: 20°C 68°F 10 10 100 1,000 1 0 Contact voltage, V Contact current, A AC resistive load (cosϕ = 1.0) 9 8 7 6 5 4 3 2 1 0 80 90 100 110 120 130 Max. Coil applied voltage, %V Operate/release time, ms Operate time Release time Min. Min. Max. x - x - The CAD data of the products with a CAD Data mark can be downloaded from: http://industrial.panasonic.com/ac/e/ JW 1 Form A External dimensions 0.3 0.3 0.5 0.4 12.8 7.6 1.1 2.4 3.5 0.9 28.6 20 20 3.6 .012 .012 .020 .016 .504 .299 .043 .094 .138 .035 1.126 .787 .787 .142 Wiring diagram (Bottom view) Note: Terminal numbers are not indicated on the relay. PC board pattern (Bottom view) Tolerance: ±0.1 ±.004 COM N.O. Coil 4 6 1 8 Relay outline 12.8 .504 7.6 .299 20.0 .787 2.4 .094 4-1.5 dia. 4-.059 dia. 3.5 .138 CAD Data Dimension: Less than 1mm .039inch: Min. 1mm .039inch less than 3mm .118 inch: Min. 3mm .118 inch: General tolerance ±0.1 ±.004 ±0.2 ±.008 ±0.3 ±.012 JW 1 Form C External dimensions 20 .787 0.4 .016 3.6 .142 0.5 .020 0.3 0.5 .012 .020 0.3 .012 1.1 .043 2.4 .094 3.5 .138 3.5 .138 16.5 .650 28.6 1.128 0.8 .031 7.6 .299 12.8 .504 Wiring diagram (Bottom view) Note: Terminal numbers are not indicated on the relay. PC board pattern (Bottom view) Tolerance: ±0.1 ±.004 COM N.C. N.O. Coil 4 2 6 1 8 Relay outline 5-1.5 dia. 5-.059 dia. 16.5 .650 3.5 .138 3.5 .138 2.4 .094 7.6 .299 CAD Data Dimension: Less than 1mm .039inch: Min. 1mm .039inch less than 3mm .118 inch: Min. 3mm .118 inch: General tolerance ±0.1 ±.004 ±0.2 ±.008 ±0.3 ±.012 Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T SAFETY STANDARDS Item UL/C-UL (Recognized) CSA (Certified) VDE (Certified) TV rating (UL/CSA) TÜV (Certified) SEMKO (Certified) FIMKO SEV File No. Contact rating File No. Contact rating File No. Contact rating File No. Rating File No. Rating File No. Contact rating File No. Contact rating File No. Contact rating Standard type 1 Form A E43028 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC LR26550 etc. 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 40013854 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) Standard type 5A 30V DC (0ms) UL E43028 CSA LR26550 etc. 1a➝TV-5 B 11 05 13461 305 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) 5A 30V DC (0ms) 817817 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 24965 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 11. 0262 5A 250V AC (cosφ =1.0) Standard type 1 Form C E43028 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC LR26550 etc. 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 40013854 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) Standard type 5A 30V DC (0ms) — — B 11 05 13461 305 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) 5A 30V DC (0ms) 817817 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 24965 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 11. 0262 5A 250V AC (cosφ =1.0) Standard type 2 Form A E43028 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 LR26550 etc. 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 40013854 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) Standard type 5A 30V DC (0ms) — — B 11 05 13461 305 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) 5A 30V DC (0ms) Tantalum-Polymer Solid Capacitors New Capacitors Panasonic New Product Introduction Stable Capacitance at High Frequency and Temperature, with Low ESR/ESL Panasonic, a worldwide leader in Capacitor Products, introduces POSCAP Tantalum-Polymer Solid Capacitors to their Capacitor product line. The POSCAP product line spans several series of Solid Electrolyte Chip Capacitors which include the TPE, TQC, TPF, TPSF, TPB, TPC, TPG, and TPU Series. These capacitors utilize a sintered tantalum anode and a proprietary high conductivity polymer for a cathode. Panasonic’s innovative construction and processing yields the lowest ESR level in polymer tantalum technology, and exhibits excellent performance in high frequency applications. Offering a high volumetric efficiency for capacitance, POSCAP Capacitors is available in various, compact package sizes for a small PCB footprint. Additionally, POSCAP parts demonstrate a high reliability and high heat resistance, making them the ideal Chip Capacitor for digital, high-frequency devices and more. • Low Profile Package Size: 0.9mm Height (TPU) • Very Low ESR (Down to 5mΩ) • Large Capacitance (Up to 1500μF) • High Temp Reflow Solder Capable (up to 260°C) • RoHS Compliant • High Volumetric Efficiency for Capacitance • Safe Alternative to Generic Tantalum Capacitors • Variety of Low Profile Packages Opens up PCB Space • Wide Application Coverage • Consumer Electronics • Industrial Electronics • Telecommunications • Appliances • PC/Server • Set Top Box • Audio/Video Equipment • FPGA Power Delivery • Router/Switch/Base Station • Test and Measurement Website: www.panasonic.com/industrial industrial@us.panasonic.com 1-800-344-2112 Copyright © 2013 Panasonic Corporation of North America. All Rights Reserved. Specifications are subject to change without notice. POSCAP NPI, FY13-038-XXX Features Benefits Industries Applications Part Number Information Additional Information For detailed specification information on the POSCAP Line of Tantalum Solid Capacitors, visit our website at: www.panasonic.com/industrial/electronic-components/capacitive-products/ RoHS COMPLIANT Series Information TPE, TQC, TPF, TPSF, TPB, TPC, TPG, TPU Series 2 R 5 Rated Voltage Series Rated Capacitance Cap. Tol. T P E 3 3 0 M Special Code A Z B Series Voltage Capacitance ESR TPE 2-10 VDC 47-1500 μF 7-35 mΩ TQC 16-35 VDC 3.9-150 μF 40-400 mΩ TPF 2-10 VDC 150-1000 μF 5-15 mΩ TPSF 2 VDC 270 μF 6-9 mΩ TPB 4-10 VDC 33-470 μF 35-70 mΩ TPC 6.3-12.5 VDC 10-330 μF 40-80 mΩ TPG 2.5-12.5 VDC 33-220 μF 30-70 mΩ TPU 2.5-10 VDC 4.7-150 μF 100-300 mΩ Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-63 – 0d±0.05 010􀀝 Sleeve L􀀽 14 min. 3 min. (􀀽08􀁌15, 016􀁌15, 018􀁌15 : L±1.5) Pressure relief 06.3􀀝 But exclude 7 mm height 􀀽􀀀L􀀝16 : L±1.0 L􀀟20 : L±2.0 + – 04 to 08 0D±0.5 F±0.5 0D±0.5 ■ Features ● Endurance : 105 °C 1000 h to 5000 h ● Low impedance ● RoHS directive compliant Radial Lead Type Series: FC Type: A ■ Specifi cations Category Temp. Range –55 °C to +105 °C Rated W.V. Range 6.3 V.DC to 100 V.DC Nominal Cap. Range 2.2 μF to 15000 μF Capacitance Tolerance ±20 % (120 Hz/+20 °C) DC Leakage Cur rent I < 0.01 CV or 3 (μA) After 2 minutes (Whichever is greater) tan d W.V. (V) 6.3 10 16 25 35 50 63 100 (120 Hz/+20 °C) tan d 0.22 0.19 0.16 0.14 0.12 0.10 0.08 0.07 For capacitance value > 1000 μF, add 0.02 per every 1000 μF. Endurance After following life test with DC voltage and +105 °C±2 °C ripple current value applied (The sum of DC and ripple peak voltage shall not exceed the rated working voltage) when the capacitors are restored to 20 °C, the capacitors shall meet the limits specifi ed bellow. Duration : 04 to 06.3: 1000 hours, 08: 2000 hours , 010: 3000 hours , 012.5 to 018: 5000 hours Capacitance change ±20 % of initial measured value tan d < 200 % of initial specifi ed value DC leakage current < initial specifi ed value Shelf Life After storage for 1000 hours at +105 °C±2 °C with no voltage applied and then being stabilized at +20 °C, capacitors shall meet the limits specifi ed in Endurance. (With voltage treatment) W.V.(V.DC) Cap (μF) Frequency (Hz) 60 120 1 k 10 k 100 k 6.3 to 100 2.2 to 330 0.55 0.65 0.85 0.90 1.00 390 to 1000 0.70 0.75 0.90 0.95 1.00 1200 to 2200 0.75 0.80 0.90 0.95 1.00 2700 to 15000 0.80 0.85 0.95 1.00 1.00 ■ Frequency correction factor for ripple current L>11 L=7 Body Dia. 0D 4 5 6.3 8 10 12.5 16 18 4 5 6.3 Body Length L 15 to 25 30 to 40 Lead Dia. 0d 0.45 0.5 0.5 0.6 0.6 0.6 0.8 0.8 0.8 0.45 0.45 0.45 Lead space F 1.5 2.0 2.5 3.5 5.0 5.0 5.0 7.5 7.5 1.5 2.0 2.5 ■ Di men sions in mm (not to scale) (Unit : mm) 02 Dec. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-64 – ■ Case size/ Impedance/ Ripple Current W.V(V.DC) 6.3 V to 35 V 50 V 63 V 100 V Case size (0D×L) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) /(100 kHz) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) /(100 kHz) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) /(100 kHz) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) 20 °C –10 °C 20 °C –10 °C 20 °C –10 °C 20 °C –10 °C /(100 kHz) 4 × 7 2.00 5.00 65 5 × 7 0.950 2.40 120 6.3 × 7 0.450 1.20 200 4 × 11 1.30 2.60 120 2.50 5.00 90 3.50 7.00 80 5 × 11 0.800 1.60 175 ✽ ✽ ✽ 2.00 4.00 145 4.10 8.20 80 5 × 15 0.500 1.00 235 0.900 1.80 215 1.30 2.60 200 2.80 5.60 90 6.3 × 11.2 0.350 0.700 290 0.600 1.20 260 1.00 2.00 240 1.80 3.60 114 6.3 × 15 0.250 0.500 400 0.400 0.800 360 0.700 1.40 330 1.10 2.20 155 8 × 11.5 0.117 0.234 555 0.234 0.468 485 0.342 0.684 405 0.680 1.36 260 8 × 15 0.085 0.170 730 0.155 0.310 635 0.230 0.460 535 0.450 0.900 340 8 × 20 0.065 0.130 995 0.120 0.240 860 0.178 0.356 690 0.330 0.660 455 10 × 12.5 0.090 0.180 755 0.162 0.324 615 0.256 0.512 535 0.530 1.06 306 10 × 16 0.068 0.136 1050 0.119 0.238 850 0.194 0.388 600 0.360 0.720 400 10 × 20 0.052 0.104 1220 0.090 0.180 1030 0.147 0.294 885 0.240 0.480 463 10 × 25 0.045 0.090 1440 0.082 0.164 1200 0.130 0.260 1050 0.210 0.420 599 10 × 30 0.035 0.070 1815 0.060 0.120 1610 0.090 0.180 1300 0.150 0.300 698 12.5 × 15 0.065 0.130 1205 0.110 0.220 1150 0.150 0.300 1020 0.230 0.460 511 12.5 × 20 0.038 0.076 1655 0.063 0.126 1480 0.085 0.170 1285 0.180 0.360 671 12.5 × 25 0.030 0.060 1945 0.050 0.100 1832 0.070 0.140 1720 0.110 0.220 807 12.5 × 30 0.025 0.050 2310 0.040 0.080 2215 0.055 0.110 2090 0.098 0.196 937 12.5 × 35 0.022 0.044 2510 0.034 0.068 2285 0.047 0.094 2265 0.087 0.174 1040 12.5 × 40 0.018 0.036 2655 0.030 0.060 2590 0.042 0.084 2560 0.072 0.144 1130 16 × 15 0.043 0.086 1690 0.080 0.160 1610 0.090 0.180 1410 0.140 0.280 793 16 × 20 0.029 0.058 2205 0.048 0.096 1835 0.059 0.118 1765 0.110 0.220 995 16 × 25 0.022 0.044 2555 0.034 0.068 2235 0.050 0.100 2160 0.089 0.178 1170 16 × 31.5 0.018 0.036 3010 0.028 0.056 2700 0.043 0.086 2670 0.062 0.124 1520 16 × 35.5 0.016 0.032 3150 0.025 0.050 2790 0.036 0.072 2770 0.053 0.106 1730 16 × 40 0.015 0.030 3360 0.023 0.046 2845 0.030 0.060 2825 0.047 0.094 1920 18 × 15 0.038 0.076 2000 0.068 0.136 1900 0.086 0.172 1690 0.120 0.240 917 18 × 20 0.028 0.056 2490 0.042 0.084 2420 0.055 0.110 2290 0.080 0.160 1230 18 × 25 0.020 0.040 2740 0.029 0.058 2610 0.043 0.086 2585 0.070 0.140 1420 18 × 31.5 0.016 0.032 3635 0.025 0.050 3000 0.032 0.064 2950 0.062 0.124 1600 18 × 35.5 0.015 0.030 3680 0.023 0.046 3100 0.030 0.060 3095 0.041 0.082 1770 18 × 40 0.014 0.028 3735 – – – 0.025 0.050 3205 0.036 0.072 2300 ✽ Case size (0D×L) Capacitance (μF) Imped ance (Ω)/(100 kHz) Ripple Current 20 °C –10 °C (mA r.m.s)(100 kHz) 5 × 11 1.0 2.40 4.80 20 2.2 1.80 3.60 45 3.3 1.30 2.60 65 4.7 1.30 2.60 95 10 1.30 2.60 125 12 1.30 2.60 135 15 1.30 2.60 145 18 1.30 2.60 155 22 1.30 2.60 155 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-65 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 6.3 27 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC0J270( ) 200 2000 56 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC0J560( ) 200 2000 68 4 11 120 1.300 1000 0.45 1.5 5.0 2.5 EEUFC0J680( ) 200 2000 100 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC0J101( ) 200 2000 120 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC0J121( ) 200 2000 150 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC0J151( ) 200 2000 220 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC0J221( ) 200 2000 270 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC0J271( ) 200 2000 330 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC0J331S( ) 200 2000 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC0J331( ) 200 2000 390 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC0J391( ) 200 1000 470 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC0J471( ) 200 1000 560 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC0J561( ) 200 1000 820 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC0J821L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC0J821( ) 200 500 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC0J102( ) 200 500 1200 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC0J122L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC0J122( ) 200 500 1500 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC0J152( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC0J152S( ) 200 500 1800 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC0J182( ) 200 500 2200 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC0J222( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC0J222S( ) 100 250 2700 10 30 1815 0.035 3000 0.60 5.0 EEUFC0J272L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC0J272( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC0J272S( ) 100 250 3300 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC0J332( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC0J332S( ) 100 250 3900 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC0J392( ) 200 500 4700 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC0J472 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC0J472S( ) 100 250 5600 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC0J562L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC0J562( ) 100 250 6800 12.5 40 2655 0.018 5000 0.80 5.0 EEUFC0J682L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC0J682( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC0J682S( ) 100 250 8200 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC0J822 100 10000 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC0J103 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC0J103S( ) 100 250 12000 16 40 3360 0.015 5000 0.80 7.5 EEUFC0J123L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC0J123 50 15000 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC0J153 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-66 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 10 22 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1A220( ) 200 2000 39 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1A390( ) 200 2000 47 4 11 120 1.300 1000 0.45 1.5 5.0 2.5 EEUFC1A470( ) 200 2000 82 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1A820( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1A820( ) 200 2000 100 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1A101S( ) 200 2000 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1A101( ) 200 2000 150 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1A151( ) 200 2000 180 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1A181( ) 200 2000 220 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1A221S( ) 200 2000 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1A221( ) 200 2000 330 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1A331( ) 200 1000 390 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1A391( ) 200 1000 470 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1A471( ) 200 1000 560 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1A561( ) 200 500 680 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1A681L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1A681( ) 200 500 820 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1A821( ) 200 500 1000 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1A102L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1A102( ) 200 500 1200 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1A122( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1A122S( ) 200 500 1500 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1A152( ) 200 500 1800 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1A182( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1A182S( ) 100 250 2200 10 30 1815 0.035 3000 0.60 5.0 EEUFC1A222L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1A222( ) 200 500 2700 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1A272( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1A272S( ) 100 250 3300 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1A332 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1A332S( ) 100 250 3900 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1A392L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1A392( ) 100 250 4700 12.5 40 2655 0.018 5000 0.80 5.0 EEUFC1A472L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1A472( ) 100 250 5600 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1A562( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1A562S( ) 100 250 6800 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1A682 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1A682S( ) 100 250 8200 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1A822L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1A822 50 10000 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1A103 50 12000 18 40 3735 0.014 5000 0.80 7.5 EEUFC1A123 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-67 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 16 15 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1C150( ) 200 2000 27 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1C270( ) 200 2000 39 4 11 120 1.30 1000 0.45 1.5 5.0 2.5 EEUFC1C390( ) 200 2000 47 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1C470( ) 200 2000 56 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1C560( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1C560( ) 200 2000 68 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1C680( ) 200 2000 82 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1C820( ) 200 2000 100 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1C101( ) 200 2000 120 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1C121( ) 200 2000 180 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1C181( ) 200 2000 220 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1C221( ) 200 1000 270 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1C271( ) 200 1000 330 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1C331( ) 200 1000 390 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1C391( ) 200 500 470 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1C471L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1C471( ) 200 500 560 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1C561( ) 200 500 680 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1C681L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1C681( ) 200 500 820 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1C821( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1C821S( ) 200 500 1000 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1C102S( ) 200 500 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1C102( ) 200 500 1200 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1C122( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1C122S( ) 100 250 1500 10 30 1815 0.035 3000 0.60 5.0 EEUFC1C152L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1C152( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1C152S( ) 100 250 1800 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1C182( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1C182S( ) 100 250 2200 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1C222( ) 200 500 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1C222S( ) 100 250 2700 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1C272L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1C272( ) 100 250 3300 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1C332 100 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1C332S( ) 100 250 3900 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1C392( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1C392S( ) 100 250 4700 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1C472 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1C472S( ) 100 250 5600 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1C562L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1C562 50 6800 16 40 3360 0.015 5000 0.80 7.5 EEUFC1C682 100 8200 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1C822 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-68 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 25 10 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1E100( ) 200 2000 22 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1E220( ) 200 2000 27 4 11 120 1.30 1000 0.45 1.5 5.0 2.5 EEUFC1E270( ) 200 2000 39 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1E390( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1E390( ) 200 2000 47 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1E470( ) 200 2000 56 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1E560( ) 200 2000 82 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1E820( ) 200 2000 100 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1E101S( ) 200 2000 120 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1E121( ) 200 2000 180 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1E181( ) 200 1000 220 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1E221( ) 200 1000 270 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1E271( ) 200 500 330 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1E331L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1E331( ) 200 500 390 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1E391( ) 200 500 470 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1E471L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1E471( ) 200 500 560 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1E561( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1E561S( ) 200 500 680 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1E681( ) 200 500 820 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1E821( ) 200 500 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1E821S( ) 200 500 1000 10 30 1815 0.035 3000 0.60 5.0 EEUFC1E102L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1E102( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1E102S( ) 100 250 1200 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1E122( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1E122S( ) 100 250 1500 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1E152( ) 200 500 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1E152S( ) 100 250 1800 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1E182L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1E182( ) 100 250 2200 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1E222 100 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1E222S( ) 100 250 2700 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1E272( ) 100 250 3300 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1E332 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1E332S( ) 100 250 3900 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1E392L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1E392 50 4700 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1E472 50 5600 18 40 3735 0.014 5000 0.80 7.5 EEUFC1E562 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-69 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 35 6.8 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1V6R8( ) 200 2000 12 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1V120( ) 200 2000 18 4 11 120 1.300 1000 0.45 1.5 5.0 2.5 EEUFC1V180( ) 200 2000 22 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1V220( ) 200 2000 27 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1V270( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1V270( ) 200 2000 33 5 11 175 0.080 1000 0.50 2.0 5.0 2.5 EEUFC1V330( ) 200 2000 39 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1V390( ) 200 2000 47 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1V470( ) 200 2000 56 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1V560( ) 200 2000 68 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1V680( ) 200 2000 82 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1V820( ) 200 2000 100 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1V101( ) 200 1000 120 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1V121( ) 200 1000 150 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1V151( ) 200 1000 180 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1V181( ) 200 500 220 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1V221L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1V221( ) 200 500 270 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1V271( ) 200 500 330 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1V331L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1V331( ) 200 500 390 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1V391( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1V391S( ) 200 500 470 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1V471( ) 200 500 560 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1V561( ) 200 500 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1V561S( ) 200 500 680 10 30 1815 0.035 3000 0.60 5.0 EEUFC1V681L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1V681( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1V681S( ) 100 250 820 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1V821L( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1V821( ) 100 250 1000 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1V102( ) 200 500 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1V102S( ) 100 250 1200 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1V122L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1V122( ) 100 250 1500 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1V152L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1V152( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1V152S( ) 100 250 1800 12.5 40 2655 0.018 5000 0.80 5.0 EEUFC1V182L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1V182( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1V182S( ) 100 250 2200 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1V222 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1V222S( ) 100 250 2700 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1V272L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1V272 50 3300 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1V332 50 3900 18 40 3735 0.014 5000 0.80 7.5 EEUFC1V392 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-70 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 50 1.0 5 11 20 2.400 1000 0.50 2.0 5.0 2.5 EEUFC1H1R0( )✽✽✽ 200 2000 2.2 5 11 45 1.800 1000 0.50 2.0 5.0 2.5 EEUFC1H2R2( ) 200 2000 3.3 5 11 65 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H3R3( ) 200 2000 4.7 5 11 95 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H4R7( ) 200 2000 10 4 11 90 2.500 1000 0.45 1.5 5.0 2.5 EEUFC1H100( ) 200 2000 5 11 125 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H100L( ) 200 2000 12 5 11 135 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H120( ) 200 2000 15 5 11 145 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H150( ) 200 2000 18 5 11 155 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H180( ) 200 2000 22 5 11 155 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H220( ) 200 2000 27 5 15 215 0.900 1000 0.50 2.0 5.0 2.5 EEUFC1H270( ) 200 2000 33 6.3 11.2 260 0.600 1000 0.50 2.5 5.0 2.5 EEUFC1H330( ) 200 2000 39 6.3 11.2 260 0.600 1000 0.50 2.5 5.0 2.5 EEUFC1H390( ) 200 2000 47 6.3 11.2 260 0.600 1000 0.50 2.5 5.0 2.5 EEUFC1H470( ) 200 2000 56 6.3 15 360 0.400 1000 0.50 2.5 5.0 2.5 EEUFC1H560( ) 200 2000 68 8 11.5 485 0.234 2000 0.60 3.5 5.0 EEUFC1H680( ) 200 1000 82 8 11.5 485 0.234 2000 0.60 3.5 5.0 EEUFC1H820( ) 200 1000 100 10 12.5 615 0.162 3000 0.60 5.0 5.0 EEUFC1H101( ) 200 500 120 8 15 635 0.155 2000 0.60 3.5 5.0 EEUFC1H121L( ) 200 1000 10 12.5 615 0.162 3000 0.60 5.0 5.0 EEUFC1H121( ) 200 500 150 10 16 850 0.119 3000 0.60 5.0 5.0 EEUFC1H151( ) 200 500 180 8 20 860 0.120 2000 0.60 3.5 5.0 EEUFC1H181L( ) 200 1000 10 16 850 0.119 3000 0.60 5.0 5.0 EEUFC1H181( ) 200 500 220 10 20 1030 0.090 3000 0.60 5.0 5.0 EEUFC1H221( ) 200 500 12.5 15 1150 0.110 5000 0.60 5.0 5.0 EEUFC1H221S( ) 200 500 270 10 25 1200 0.082 3000 0.60 5.0 5.0 EEUFC1H271( ) 200 500 330 10 30 1610 0.060 3000 0.60 5.0 EEUFC1H331L 100 12.5 20 1480 0.063 5000 0.60 5.0 5.0 EEUFC1H331( ) 200 500 390 12.5 20 1480 0.063 5000 0.60 5.0 5.0 EEUFC1H391( ) 200 500 16 15 1610 0.080 5000 0.80 7.5 7.5 EEUFC1H391S( ) 100 250 470 10 30 1610 0.060 3000 0.60 5.0 EEUFC1H471L 100 12.5 25 1832 0.050 5000 0.60 5.0 5.0 EEUFC1H471( ) 200 500 560 12.5 25 1832 0.050 5000 0.60 5.0 5.0 EEUFC1H561( ) 200 500 18 15 1900 0.068 5000 0.80 7.5 7.5 EEUFC1H561S( ) 100 250 680 12.5 30 2215 0.040 5000 0.80 5.0 EEUFC1H681L 100 16 20 1835 0.048 5000 0.80 7.5 7.5 EEUFC1H681( ) 100 250 820 12.5 35 2285 0.034 5000 0.80 5.0 EEUFC1H821L 100 18 20 2420 0.042 5000 0.80 7.5 7.5 EEUFC1H821( ) 100 250 1000 12.5 40 2590 0.030 5000 0.80 5.0 EEUFC1H102L 100 16 25 2235 0.034 5000 0.80 7.5 7.5 EEUFC1H102( ) 100 250 1200 16 31.5 2700 0.028 5000 0.80 7.5 EEUFC1H122 100 18 25 2610 0.029 5000 0.80 7.5 7.5 EEUFC1H122S( ) 100 250 1500 16 35.5 2790 0.025 5000 0.80 7.5 EEUFC1H152L 100 1800 16 40 2845 0.023 5000 0.80 7.5 EEUFC1H182L 100 18 31.5 3000 0.025 5000 0.80 7.5 EEUFC1H182 50 2200 18 35.5 3100 0.023 5000 0.80 7.5 EEUFC1H222 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. ✽✽✽ Please kindly accept last shipment : 31/Mar/2015 Endurance : 105 °C 04 to 06.3=1000 h, 08=2000 h, 010=3000 h, 012.5 to 018=5000 h 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-71 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 63 6.8 4 11 80 3.500 1000 0.45 1.5 5.0 2.5 EEUFC1J6R8( ) 200 2000 12 5 11 145 2.000 1000 0.50 2.0 5.0 2.5 EEUFC1J120( ) 200 2000 18 5 15 200 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1J180( ) 200 2000 22 6.3 11.2 240 1.000 1000 0.50 2.5 5.0 2.5 EEUFC1J220( ) 200 2000 33 6.3 11.2 240 1.000 1000 0.50 2.5 5.0 2.5 EEUFC1J330( ) 200 2000 39 6.3 15 330 0.700 1000 0.50 2.5 5.0 2.5 EEUFC1J390( ) 200 2000 47 8 11.5 405 0.342 2000 0.60 3.5 5.0 EEUFC1J470( ) 200 1000 56 8 11.5 405 0.342 2000 0.60 3.5 5.0 EEUFC1J560( ) 200 1000 68 8 11.5 405 0.342 2000 0.60 3.5 5.0 EEUFC1J680( ) 200 1000 82 10 12.5 535 0.256 3000 0.60 5.0 5.0 EEUFC1J820( ) 200 500 100 8 15 535 0.230 2000 0.60 3.5 5.0 EEUFC1J101L( ) 200 1000 10 12.5 535 0.256 3000 0.60 5.0 5.0 EEUFC1J101( ) 200 500 120 10 16 600 0.194 3000 0.60 5.0 5.0 EEUFC1J121( ) 200 500 150 8 20 690 0.178 2000 0.60 3.5 5.0 EEUFC1J151( ) 200 1000 180 10 20 885 0.147 3000 0.60 5.0 5.0 EEUFC1J181( ) 200 500 12.5 15 1020 0.150 5000 0.60 5.0 5.0 EEUFC1J181S( ) 200 500 220 10 20 885 0.147 3000 0.60 5.0 5.0 EEUFC1J221X( ) 200 500 10 25 1050 0.130 3000 0.60 5.0 5.0 EEUFC1J221( ) 200 500 12.5 20 1285 0.085 5000 0.60 5.0 5.0 EEUFC1J221S( ) 200 500 270 16 15 1410 0.090 5000 0.80 7.5 7.5 EEUFC1J271( ) 100 250 330 10 30 1300 0.090 3000 0.60 5.0 EEUFC1J331L 100 12.5 20 1285 0.085 5000 0.60 5.0 5.0 EEUFC1J331( ) 200 500 390 12.5 25 1720 0.070 5000 0.60 5.0 5.0 EEUFC1J391( ) 200 500 18 15 1690 0.086 5000 0.80 7.5 7.5 EEUFC1J391S( ) 100 250 470 12.5 30 2090 0.055 5000 0.80 5.0 EEUFC1J471L 100 16 20 1765 0.059 5000 0.80 7.5 7.5 EEUFC1J471( ) 100 250 560 16 25 2160 0.050 5000 0.80 7.5 7.5 EEUFC1J561( ) 100 250 680 12.5 35 2265 0.047 5000 0.80 5.0 EEUFC1J681L 100 16 25 2160 0.050 5000 0.80 7.5 7.5 EEUFC1J681( ) 100 250 18 20 2290 0.055 5000 0.80 7.5 7.5 EEUFC1J681S( ) 100 250 820 12.5 40 2560 0.042 5000 0.80 5.0 EEUFC1J821L 100 16 31.5 2670 0.043 5000 0.80 7.5 EEUFC1J821 100 18 25 2585 0.043 5000 0.80 7.5 7.5 EEUFC1J821S( ) 100 250 1000 16 31.5 2670 0.043 5000 0.80 7.5 EEUFC1J102U 100 16 35.5 2770 0.036 5000 0.80 7.5 EEUFC1J102 100 1200 16 40 2825 0.030 5000 0.80 7.5 EEUFC1J122L 100 18 31.5 2950 0.032 5000 0.80 7.5 EEUFC1J122 50 1500 18 35.5 3095 0.030 5000 0.80 7.5 EEUFC1J152 50 1800 18 40 3205 0.025 5000 0.80 7.5 EEUFC1J182 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C 04 to 06.3=1000 h, 08=2000 h, 010=3000 h, 012.5 to 018=5000 h 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-72 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 100 5.6 5 11 80 4.10 1000 0.5 2.0 5.0 2.5 EEUFC2A5R6( ) 200 2000 8.2 5 15 90 2.80 1000 0.5 2.0 5.0 2.5 EEUFC2A8R2( ) 200 2000 12 6.3 11.2 114 1.80 1000 0.5 2.5 5.0 2.5 EEUFC2A120( ) 200 2000 18 6.3 15 155 1.10 1000 0.5 2.5 5.0 2.5 EEUFC2A180( ) 200 2000 22 8 11.5 260 0.680 2000 0.6 3.5 5.0 EEUFC2A220( ) 200 1000 33 8 15 340 0.450 2000 0.6 3.5 5.0 EEUFC2A330L( ) 200 1000 10 12.5 306 0.530 3000 0.6 5.0 5.0 EEUFC2A330( ) 200 500 39 8 20 455 0.330 2000 0.6 5.0 5.0 EEUFC2A390L( ) 200 1000 10 16 400 0.360 3000 0.6 5.0 5.0 EEUFC2A390( ) 200 500 56 10 20 463 0.240 3000 0.6 5.0 5.0 EEUFC2A560( ) 200 500 68 10 25 599 0.210 3000 0.6 5.0 5.0 EEUFC2A680L( ) 200 500 12.5 15 511 0.230 5000 0.6 5.0 5.0 EEUFC2A680( ) 200 500 100 10 30 698 0.150 3000 0.6 5.0 EEUFC2A101L 100 12.5 20 671 0.180 5000 0.6 5.0 5.0 EEUFC2A101( ) 200 500 120 16 15 793 0.140 5000 0.8 7.5 7.5 EEUFC2A121S( ) 100 250 150 12.5 25 807 0.110 5000 0.6 5.0 5.0 EEUFC2A151( ) 200 500 18 15 917 0.120 5000 0.8 7.5 7.5 EEUFC2A151S( ) 100 250 180 12.5 30 937 0.098 5000 0.8 5.0 EEUFC2A181L 100 16 20 995 0.110 5000 0.8 7.5 7.5 EEUFC2A181( ) 100 250 220 12.5 35 1040 0.087 5000 0.8 5.0 EEUFC2A221L 100 16 25 1170 0.089 5000 0.8 7.5 7.5 EEUFC2A221( ) 100 250 270 12.5 40 1130 0.072 5000 0.8 5.0 EEUFC2A271L 100 18 20 1230 0.080 5000 0.8 7.5 7.5 EEUFC2A271S( ) 100 250 330 16 31.5 1520 0.062 5000 0.8 7.5 EEUFC2A331 100 18 25 1420 0.070 5000 0.8 7.5 7.5 EEUFC2A331S( ) 100 250 390 16 35.5 1730 0.053 5000 0.8 7.5 EEUFC2A391L 100 18 31.5 1600 0.062 5000 0.8 7.5 EEUFC2A391 50 470 16 40 1920 0.047 5000 0.8 7.5 EEUFC2A471 100 560 18 35.5 1770 0.041 5000 0.8 7.5 EEUFC2A561 50 680 18 40 2300 0.036 5000 0.8 7.5 EEUFC2A681 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C 04 to 06.3=1000 h, 08=2000 h, 010=3000 h, 012.5 to 018=5000 h 01 Oct. 2013 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. 􀊵 􀀧􀀤􀀘􀀔 􀊵 Plastic Film Capacitors Metallized Polypropylene Film Capacitors Type: EZPE Series ■Features •High safety, Self-healing and Self-protecting function built-in •Long product life, High reliability •Low loss, Low ESR •Flame retardant (Case and sealing resin) •RoHS directive compliant ■Recommended Applications For DC filtering, DC link circuit •Solar inverters •Wind power generation •Industrial power supplies •Inverter circuit in appliances (Air Conditioners etc.) ■Construction •Dielectric : Polypropylene film •Electrodes : Metallized dielectric with segmented pattern •Plastic case : UL94 V-0 •Sealing : UL94 V-0 •Terminals : Tinned wires,2-pin and 4-pin versions ■Explanation of Part Numbers 1 2 3 4 5 6 7 8 9 10 11 12 E Z P E Product code Dielectric & construction Rated voltage Capacitance T Pin type Suffix A Suffix 50 500 VDC 80 800 VDC 1B 1100 VDC 1D 1300 VDC L 2-pin type M 4-pin type ■Specifications Category temperature range (TC) (*1) Rated voltage(VR) (*2) Rated capacitance (CR) Capacitance tolerance Withstanding DC voltage Insulation resistance (CR) –40 °C to +85 °C 500 VDC, 800 VDC, 1100 VDC, 1300 VDC (Derating of rated voltage by more than 70 °C (*3)) 500 VDC 800 VDC 1100 VDC 1300 VDC 10 μF to 110 μF 10 μF to 60 μF 10 μF to 40 μF 10 μF to 25 μF ±10 % Between terminals:Rated voltage. (VDC)✕150 % 10 s Terminal to case:2110 VAC 10 s CR>=10000 Ω · F (20 °C, 500 VDC, 60 s) *1:The temperature of capacitor surface (case) *2:Use for DC voltage only *3:Refer to the page of “ DC voltage derating ” Metallized Film Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. 􀊵 􀀧􀀤􀀘􀀕 􀊵 Plastic Film Capacitors ■Dimensions in mm (not to scale) 􀀮􀁂􀁓􀁌􀁊􀁏􀁈􀀁 􀀱􀀒􀊶􀀒􀀁 􀀭􀊶􀀑􀀏􀀖􀀁 􀀱􀀓􀊶􀀒􀀁 􀐟􀊶􀀑􀀏􀀓􀀁 􀀕􀀏􀀑􀊶􀀓􀀏􀀑􀀁 􀀸􀊶􀀑􀀏􀀖􀀁 􀀩􀊶􀀑􀀏􀀖􀀁 􀀮􀁂􀁓􀁌􀁊􀁏􀁈􀀁 􀀱􀀒􀊶􀀒􀀁 􀀕􀀏􀀑􀊶􀀓􀀏􀀑􀀁 􀀩􀊶􀀑􀀏􀀖􀀁 􀐟􀊶􀀑􀀏􀀓􀀁 􀀭􀊶􀀑􀀏􀀖􀀁 􀀸􀊶􀀑􀀏􀀖􀀁 􀀥􀀤􀀁 􀀉􀁂􀀊􀀁 􀀷􀀁 􀐖􀀧􀀁 􀀉􀁂􀀊􀉹􀀳􀁂􀁕􀁆􀁅􀀁􀁗􀁐􀁍􀁕􀁂􀁈􀁆 􀀉􀁃􀀊􀉹􀀤􀁂􀁑􀁂􀁄􀁊􀁕􀁂􀁏􀁄􀁆 􀀉􀁄􀀊􀀁 􀀉􀁄􀀊􀉹􀀭􀁐􀁕􀀁􀀯􀁐􀀏􀀁 􀀉􀁃􀀊􀀁 􀀱􀁂􀁏􀁂􀁔􀁐􀁏􀁊􀁄􀀁 􀀮􀁂􀁓􀁌􀁊􀁏􀁈􀀉􀁆􀁙􀀏􀀊􀀁 ■Rating, Dimensions & Quantity / Ammo Box ●Type EZPE Rated voltage : 500 VDC at 70 􀋆 ( 450VDC at 85 􀋆 ) EZPE50106LTA 10 20 42 41.5 37.5 - 1.2 21 210 5.0 22.0 0.28 45 EZPE50156LTA 15 20 42 41.5 37.5 - 1.2 21 315 7.5 14.8 0.28 45 EZPE50206LTA 20 20 42 41.5 37.5 - 1.2 21 420 9.5 11.0 0.28 44 EZPE50256LTA 25 20 42 41.5 37.5 - 1.2 21 525 11.0 8.8 0.28 43 EZPE50306MTA 30 20 42 41.5 37.5 10.2 1.2 21 630 12.5 7.0 0.28 43 EZPE50356MTA 35 30 51 41.5 37.5 10.2 1.2 21 735 13.5 6.2 0.28 83 EZPE50406MTA 40 30 51 41.5 37.5 10.2 1.2 21 840 14.5 5.4 0.28 82 EZPE50456MTA 45 30 51 41.5 37.5 10.2 1.2 21 945 15.2 4.9 0.28 81 EZPE50506MTA 50 30 51 41.5 37.5 20.3 1.2 21 1050 16.0 4.4 0.28 80 EZPE50556MTA 55 30 51 41.5 37.5 20.3 1.2 21 1155 16.3 4.1 0.28 79 EZPE50606MTA 60 30 51 41.5 37.5 20.3 1.2 21 1260 16.5 3.9 0.28 77 EZPE50656MTA 65 30 51 57.5 52.5 10.2 1.2 14 910 15.0 6.8 0.44 111 EZPE50706MTA 70 30 51 57.5 52.5 10.2 1.2 14 980 15.5 6.5 0.44 109 EZPE50756MTA 75 30 51 57.5 52.5 20.3 1.2 14 1050 16.0 6.0 0.44 108 EZPE50806MTA 80 30 51 57.5 52.5 20.3 1.2 14 1120 16.5 5.7 0.44 106 EZPE50856MTA 85 35 56 57.5 52.5 20.3 1.2 14 1190 16.7 5.4 0.44 142 EZPE50906MTA 90 35 56 57.5 52.5 20.3 1.2 14 1260 17.0 5.1 0.44 141 EZPE50956MTA 95 35 56 57.5 52.5 20.3 1.2 14 1330 17.5 4.9 0.44 140 EZPE50107MTA 100 35 56 57.5 52.5 20.3 1.2 14 1400 18.0 4.7 0.44 139 EZPE50117MTA 110 35 56 57.5 52.5 20.3 1.2 14 1540 18.5 4.4 0.44 138 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 600 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) *1:When rising temperature of capacitor surface by continuous peak current (included pulse current), use within limit specified for temperature of capacitor surface and self heating temperature rise. *2:Maximum RMS current @ 70 􀋆, 10 kHz Use within limit for self heating temperature rise at capacitor surface. *3:Typical values @ 20􀋆, 10 kHz ESR : less than 2.5 􀊷 ESRtyp *4:Maximum dissipation factor @20􀋆, 1 kHz *5:Minimum order quantity consists of 4 packing units. Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. 􀊵 􀀧􀀤􀀘􀀖 􀊵 Plastic Film Capacitors ■Rating, Dimensions & Quantity / Ammo Box ●Type EZPE Rated voltage : 800 VDC at 70 􀋆 ( 700VDC at 85 􀋆 ) EZPE80106LTA 10 20 42 41.5 37.5 - 1.2 22 220 7.0 15.8 0.22 44 EZPE80156MTA 15 20 42 41.5 37.5 10.2 1.2 22 330 9.0 10.5 0.22 43 EZPE80206MTA 20 30 51 41.5 37.5 10.2 1.2 22 440 11.0 7.7 0.22 82 EZPE80256MTA 25 30 51 41.5 37.5 10.2 1.2 22 550 13.0 6.4 0.22 80 EZPE80306MTA 30 30 51 41.5 37.5 20.3 1.2 22 660 15.0 5.3 0.22 78 EZPE80356MTA 35 30 51 57.5 52.5 10.2 1.2 15 525 12.0 9.7 0.33 110 EZPE80406MTA 40 30 51 57.5 52.5 20.3 1.2 15 600 13.0 8.3 0.33 107 EZPE80456MTA 45 30 51 57.5 52.5 20.3 1.2 15 675 14.0 7.0 0.33 104 EZPE80506MTA 50 35 56 57.5 52.5 20.3 1.2 15 750 15.0 6.3 0.33 140 EZPE80556MTA 55 35 56 57.5 52.5 20.3 1.2 15 825 16.0 5.9 0.33 138 EZPE80606MTA 60 35 56 57.5 52.5 20.3 1.2 15 900 17.0 5.6 0.33 136 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 600 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) ●Type EZPE Rated voltage : 1100 VDC at 70 􀋆 ( 920VDC at 85 􀋆 ) EZPE1B106MTA 10 20 42 41.5 37.5 10.2 1.2 54 540 7.0 12.3 0.20 43 EZPE1B156MTA 15 30 51 41.5 37.5 10.2 1.2 54 810 8.5 8.2 0.20 80 EZPE1B206MTA 20 30 51 41.5 37.5 20.3 1.2 54 1080 10.0 6.3 0.20 76 EZPE1B256MTA 25 30 51 57.5 52.5 10.2 1.2 35 875 8.0 10.7 0.28 107 EZPE1B306MTA 30 30 51 57.5 52.5 20.3 1.2 35 1050 9.0 8.5 0.28 103 EZPE1B356MTA 35 35 56 57.5 52.5 20.3 1.2 35 1225 10.0 7.2 0.28 137 EZPE1B406MTA 40 35 56 57.5 52.5 20.3 1.2 35 1400 11.0 6.5 0.28 134 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 600 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) ●Type EZPE Rated voltage : 1300 VDC at 70 􀋆 ( 1100VDC at 85 􀋆 ) EZPE1D106MTA 10 30 51 41.5 37.5 10.2 1.2 73 730 12.0 10.0 0.17 80 EZPE1D156MTA 15 30 51 57.5 52.5 10.2 1.2 50 750 10.0 14.5 0.22 109 EZPE1D206MTA 20 30 51 57.5 52.5 20.3 1.2 50 1000 14.0 11.1 0.22 103 EZPE1D256MTA 25 35 56 57.5 52.5 20.3 1.2 50 1250 17.0 8.5 0.22 136 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) *1:When rising temperature of capacitor surface by continuous peak current (included pulse current), use within limit specified for temperature of capacitor surface and self heating temperature rise. *2:Maximum RMS current @ 70 􀋆, 10 kHz Use within limit for self heating temperature rise at capacitor surface. *3:Typical values @ 20􀋆, 10 kHz ESR : less than 2.5 􀊷 ESRtyp *4:Maximum dissipation factor @20􀋆, 1 kHz *5:Minimum order quantity consists of 4 packing units. Metallized Film Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Permissible Conditions ●Permissible Voltage ・These capacitors are designed only for DC voltage, so should not be used for AC line. ・Use the peak voltage (Vo-p) within the rated voltage. ・Use the peak to peak voltage (Vp-p) within 0.2 x VR . ●DC Voltage, Peak current and RMS current derating Derating of voltage (Vo-p), RMS current (Arms), and peak current (Ao-p) according to the following diagram when the temperature of the capacitor surface exceeds 70 ℃. ●Permissible self heating temperature rise ●Total cycles applied peak current 60 65 70 75 80 85 90 95 100 Voltage ① Voltage ② Permissible voltage (Vo-p) Temperature of capacitor surface TC (℃) DC Voltage derating Percentage to the permissible current (%) Current derating Temperature of capacitor surface TC (℃) Total cycles applied peak current (Ao-p) (including pulse current) are within following diagram. Permissible self heating temperature rise is within following diagram when the temperature of the capacitor surface exceeds 70 ℃. Please consult Panasonic if your condition exceeds the above spec. Vp-p = 0.2 × VR VR ≧ Vo-p Vo 0% 20% 40% 60% 80% 100% 120% 60 65 70 75 80 85 90 95 100 Part Number Voltage ① Voltage ② EZPE50 □□□□ TA DC500V DC450V EZPE80 □□□□ TA DC800V DC700V EZPE1B □□□□ TA DC1100V DC920V EZPE1D □□□□ TA DC1300V DC1100V Total cycles Percentage to the permissible peak current (%) Permissible self temp. rise(℃) Temperature of capacitor surface TC (℃) 0% 20% 40% 60% 80% 100% 120% 60 65 70 75 80 85 90 95 100 0% 20% 40% 60% 80% 100% 10 100 1000 10000 100000 Part Number 100% at70℃ 36% at85℃ EZPE50 □□□□ TA 12 ℃ 4.3 ℃ EZPE80 □□□□ TA 10 ℃ 3.6 ℃ EZPE1B □□□□ TA 5 ℃ 1.8 ℃ EZPE1D □□□□ TA 9 ℃ 3.2 ℃ Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 500 VDC at 70 ℃ ( 450VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 60uF 20uF 110uF 100uF Dissipation factor (typical curve) tanδ (%) Temperature (℃) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) Permissible voltage (Vo-p) Lifetime expectancy (h) Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 20uF 60uF 110uF 200 250 300 350 400 450 500 550 1000 10000 100000 1000000 Tc=85℃ Tc=105℃ (I=0Arms) Tc=70℃ Unpredictable life time area Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 800 VDC at 70 ℃ ( 700VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 30uF 10uF 60uF 45uF Dissipation factor (typical curve) tanδ (%) Temperature (℃) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 30uF 10uF 45uF 60uF Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) 300 400 500 600 700 800 900 1000 10000 100000 1000000 Tc=85℃ Tc=105℃ (I=0Arms) Tc=70℃ Unpredictable life time area Permissible voltage (Vo-p) Lifetime expectancy (h) Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 1100 VDC at 70 ℃ ( 920VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy at 1kHz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 20uF 10uF 40uF Dissipation factor (typical curve) tanδ (%) Temperature (℃) -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 20uF 10uF 40uF Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) 400 500 600 700 800 900 1000 1100 1200 1000 10000 100000 1000000 Unpredictable life time area Tc=85℃ Tc=105℃ ( I = 0Arms) Tc=70℃ Permissible voltage (Vo-p) Lifetime expectancy (h) Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 1300 VDC at 70 ℃ ( 1100VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz Dissipation factor (typical curve) tanδ (%) Temperature (℃) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) Permissible voltage (Vo-p) Lifetime expectancy (h) 500 600 700 800 900 1000 1100 1200 1300 1400 1000 10000 100000 1000000 Unpredictable life time area Tc=85℃ Tc=105℃ (I=0Arms) Tc=70℃ 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 25uF 15uF 10uF 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 10uF 15uF 25uF Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage Panasonic Corporation Automation Controls Business Division industrial.panasonic.com/ac/e/ AYF33 ACCTB47E 201303-T ORDERING INFORMATION For FPC Y3B/Y3BW Series FPC connectors (0.3mm pitch) Back lock Y3BW is added. FEATURES 1. Slim and low profile design (Pitch: 0.3 mm) Back lock type and the slim body with a 3.15 mm depth (with the lever). 2. Mechanical design freedom is achieved with double top and bottom contacts Top and bottom double contacts eliminate the need of using different connectors (with either top or bottom contacts) depending on the FPC wiring conditions. 3. Easy-to-handle back lock structure 4. Man-hours of assembly time can be reduced by delivering the connectors with their levers opened. 5. Wiring patterns can be placed underneath the connector. 6. Ni barrier with high resistance to solder creepage 7. Y3BW features advanced functionality, including a structure to temporarily hold the FPC and a higher holding force. The FPC holding contacts located on both ends of the connector facilitate positioning of FPC and further enhance the FPC holding force. (1) The inserted FPC can be temporarily held until the lever is closed. (2) When the lever is closed, the holding contacts lock the FPC by its notches, enhancing the FPC holding force. APPLICATIONS Mobile devices, such as cellular phones, smartphones, digital still cameras and digital video cameras. Y3B Y3BW RoHS compliant Unit: mm 0.9 3.15 Structure to lock notches on both ends of the FPC with holding contacts Applicable FPC shapes New 33: FPC Connector 0.3 mm pitch (Back lock) AYF 3 3 5 Number of pins (2 digits) Contact direction 3: Top and bottom double contacts (Y3B) 6: Top and bottom double contacts, lock holding type (Y3BW) Surface treatment (Contact portion / Terminal portion) 5: Au plating/Au plating (Ni barrier) Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ GN (AGN) ASCTB13E 201209-T ORDERING INFORMATION High Sensitivity, with 100mW nominal operating power, in a compact and space saving case GN RELAYS (AGN) RoHS compliant FEATURES 1. Compact slim body saves space Thanks to the small surface area of 5.7 mm × 10.6 mm .224 inch × .417 inch and low height of 9.0 mm .354 inch, the packaging density can be increased to allow for much smaller designs. 2. High sensitivity single side stable type (Nominal operating power: 100mW) is available 3. Outstanding surge resistance. Surge breakdown voltage between contacts and coil: 2,500 V 2×10 μs (Telcordia) Surge breakdown voltage between open contacts: 1,500 V 10×160 μs (FCC part 68) 4. The use of twin crossbar contacts ensures high contact reliability. AgPd contact is used because of its good sulfide resistance. Adopting lowgas molding material. Coil assembly molding technology which avoids generating volatile gas from coil. 5. Increased packaging density Due to highly efficient magnetic circuit design, leakage flux is reduced and changes in electrical characteristics from components being mounted close-together are minimized. This all means a packaging density higher than ever before. 6. Nominal operating power: 140 mW 7. Outstanding vibration and shock resistance. Functional shock resistance: 750 m/s2 Destructive shock resistance: 1,000 m/s2 Functional vibration resistance: 10 to 55 Hz (at double amplitude of 3.3 mm .130 inch) Destructive vibration resistance: 10 to 55 Hz (at double amplitude of 5 mm .197 inch) 8. Sealed construction allows automatic washing. TYPICAL APPLICATIONS 1. Telephonic equipment 2. Telecommunications equipment 3. Security equipment 4. Test and Measurement equipment 5. Electronic Consumer and Audio Visual equipment Nominal coil voltage (DC) 1H: 1.5V 03: 3V 4H: 4.5V 06: 6V 09: 9V 12: 12V 24: 24V Contact arrangement 2: 2 Form C Type of operation 0: Standard type (B.B.M.) AGN 2 0 Operating function 0: Single side stable 1: 1 coil latching 6: High sensitivity single side stable type Terminal shape Nil: A: S: Standard PC board terminal Surface-mount terminal A type Surface-mount terminal S type Packing style Nil: X: Z: Tube packing Tape and reel packing (picked from 1/2/3/4 pin side) Tape and reel packing (picked from 5/6/7/8 pin side) Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-99 – 05 to 08 0D±0.5 0d±0.05 F±0.5 Sleeve L􀀽 14 min. 3 min. 􀀽􀀀L􀀝16 : L±1.0 L􀀟20 : L±2.0 Pressure relief 06.3􀀝 + – 010􀀝 0D±0.5 ■ Features ● Endurance : 105 °C 1000 h to 2000 h ● RoHS directive compliant Radial Lead Type Series: NHG Type: A ■ Specifi cations Category Temp. Range –55 °C to +105 °C –25 °C to +105 °C Rated W.V. Range 6.3 V.DC to 100 V.DC 160 V.DC to 450 V.DC Nominal Cap. Range 2.2 μF to 22000 μF 1 μF to 330 μF Capacitance Tolerance ±20 % (120 Hz/+20 °C) DC Leakage Cur rent I < 0.01 CV or 3 (μA) After 2 minutes (Which is greater) I < 0.06 CV +10 (μA) After 2 minutes tan d Please see the attached standard products list Endurance After following life test with DC voltage and +105 °C±2 °C ripple current value applied (The sum of DC and ripple peak voltage shall not exceed the rated working voltage), When the capacitors are restored to 20 °C, the capacitors shall meet the limits specifi ed below. Duration : 6.3 V.DC to 100 V.DC : (05 to 08)=1000 hours, (010 to 018)=2000 hours 160 V.DC to 450 V.DC : 2000 hours Capacitance change ±20 % of initial measured value tan d < 200 % of initial specifi ed value DC leakage current < initial specifi ed value Shelf Life After storage for 1000 hours at +105 °C±2 °C with no voltage applied and then being stabilized at +20 °C, capacitors shall meet the limits specifi ed in Endurance. (With voltage treatment) ■ Di men sions in mm (not to scale) W.V.(V.DC) Cap. (μF) Frequency (Hz) 60 120 1 k 10 k 100 k 6.3 to 100 2.2 to 33 0.75 1.00 1.55 1.80 2.00 47 to 470 0.80 1.00 1.35 1.50 1.50 1000 to 22000 0.85 1.00 1.10 1.15 1.15 160 to 450 1 to 330 0.80 1.00 1.35 1.50 1.50 ■ Frequency correction factor for ripple current Body Dia. 0D 5 6.3 8 10 12.5 16 18 Lead Dia. 0d 0.5 0.5 0.6 0.6 0.6 0.8 0.8 Lead space F 2.0 2.5 3.5 5.0 5.0 7.5 7.5 (Unit : mm) 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-100 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 6.3 220 5 11 140 0.28 1000 0.5 2.0 5.0 2.5 ECA0JHG221( ) 200 2000 470 6.3 11.2 230 0.28 1000 0.5 2.5 5.0 2.5 ECA0JHG471( ) 200 2000 1000 8 11.5 380 0.28 1000 0.6 3.5 5.0 ECA0JHG102( ) 200 1000 2200 10 16 710 0.30 2000 0.6 5.0 5.0 ECA0JHG222( ) 200 500 3300 10 20 840 0.32 2000 0.6 5.0 5.0 ECA0JHG332( ) 200 500 4700 12.5 20 1090 0.34 2000 0.6 5.0 5.0 ECA0JHG472( ) 200 500 6800 12.5 25 1350 0.38 2000 0.6 5.0 5.0 ECA0JHG682( ) 200 500 10000 16 25 1650 0.46 2000 0.8 7.5 7.5 ECA0JHG103( ) 100 250 15000 16 31.5 2010 0.56 2000 0.8 7.5 ECA0JHG153 100 22000 18 35.5 2350 0.70 2000 0.8 7.5 ECA0JHG223 50 10 330 6.3 11.2 200 0.24 1000 0.5 2.5 5.0 2.5 ECA1AHG331( ) 200 2000 470 8 11.5 250 0.24 1000 0.6 3.5 5.0 ECA1AHG471( ) 200 1000 1000 10 12.5 460 0.24 2000 0.6 5.0 5.0 ECA1AHG102( ) 200 500 2200 10 20 760 0.26 2000 0.6 5.0 5.0 ECA1AHG222( ) 200 500 3300 12.5 20 1000 0.28 2000 0.6 5.0 5.0 ECA1AHG332( ) 200 500 4700 12.5 25 1260 0.30 2000 0.6 5.0 5.0 ECA1AHG472( ) 200 500 6800 16 25 1570 0.34 2000 0.8 7.5 7.5 ECA1AHG682( ) 100 250 10000 16 31.5 1890 0.42 2000 0.8 7.5 ECA1AHG103 100 15000 18 35.5 2180 0.52 2000 0.8 7.5 ECA1AHG153 50 16 100 5 11 110 0.20 1000 0.5 2.0 5.0 2.5 ECA1CHG101( ) 200 2000 220 6.3 11.2 180 0.20 1000 0.5 2.5 5.0 2.5 ECA1CHG221( ) 200 2000 330 8 11.5 260 0.20 1000 0.6 3.5 5.0 ECA1CHG331( ) 200 1000 470 8 11.5 310 0.20 1000 0.6 3.5 5.0 ECA1CHG471( ) 200 1000 1000 10 16 560 0.20 2000 0.6 5.0 5.0 ECA1CHG102( ) 200 500 2200 12.5 20 920 0.22 2000 0.6 5.0 5.0 ECA1CHG222( ) 200 500 3300 12.5 25 1170 0.24 2000 0.6 5.0 5.0 ECA1CHG332( ) 200 500 4700 16 25 1480 0.26 2000 0.8 7.5 7.5 ECA1CHG472( ) 100 250 6800 16 31.5 1780 0.30 2000 0.8 7.5 ECA1CHG682 100 10000 18 35.5 2060 0.38 2000 0.8 7.5 ECA1CHG103 50 25 47 5 11 91 0.16 1000 0.5 2.0 5.0 2.5 ECA1EHG470( ) 200 2000 100 6.3 11.2 130 0.16 1000 0.5 2.5 5.0 2.5 ECA1EHG101( ) 200 2000 220 8 11.5 230 0.16 1000 0.6 3.5 5.0 ECA1EHG221( ) 200 1000 330 8 11.5 310 0.16 1000 0.6 3.5 5.0 ECA1EHG331( ) 200 1000 470 10 12.5 380 0.16 2000 0.6 5.0 5.0 ECA1EHG471( ) 200 500 1000 10 20 680 0.16 2000 0.6 5.0 5.0 ECA1EHG102( ) 200 500 2200 12.5 25 1090 0.18 2000 0.6 5.0 5.0 ECA1EHG222( ) 200 500 3300 16 25 1400 0.20 2000 0.8 7.5 7.5 ECA1EHG332( ) 100 250 4700 16 31.5 1750 0.22 2000 0.8 7.5 ECA1EHG472 100 6800 18 35.5 2040 0.26 2000 0.8 7.5 ECA1EHG682 50 35 47 5 11 90 0.14 1000 0.5 2.0 5.0 2.5 ECA1VHG470( ) 200 2000 100 6.3 11.2 150 0.14 1000 0.5 2.5 5.0 2.5 ECA1VHG101( ) 200 2000 220 8 11.5 270 0.14 1000 0.6 3.5 5.0 ECA1VHG221( ) 200 1000 330 10 12.5 350 0.14 2000 0.6 5.0 5.0 ECA1VHG331( ) 200 500 470 10 16 460 0.14 2000 0.6 5.0 5.0 ECA1VHG471( ) 200 500 1000 12.5 20 810 0.14 2000 0.6 5.0 5.0 ECA1VHG102( ) 200 500 2200 16 25 1260 0.16 2000 0.8 7.5 7.5 ECA1VHG222( ) 100 250 3300 16 31.5 1610 0.18 2000 0.8 7.5 ECA1VHG332 100 4700 18 35.5 1910 0.20 2000 0.8 7.5 ECA1VHG472 50 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-101 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 50 0.1 5 11 1.1 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG0R1( )✽✽✽ 200 2000 0.22 5 11 2.3 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHGR22( )✽✽✽ 200 2000 0.33 5 11 3.5 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHGR33( )✽✽✽ 200 2000 0.47 5 11 5 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHGR47( )✽✽✽ 200 2000 1 5 11 10 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG010( )✽✽✽ 200 2000 2.2 5 11 18 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG2R2( ) 200 2000 3.3 5 11 22 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG3R3( ) 200 2000 4.7 5 11 26 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG4R7( ) 200 2000 10 5 11 39 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG100( ) 200 2000 22 5 11 65 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG220( ) 200 2000 33 5 11 90 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG330( ) 200 2000 47 6.3 11.2 110 0.12 1000 0.5 2.5 5.0 2.5 ECA1HHG470( ) 200 2000 100 8 11.5 180 0.12 1000 0.6 3.5 5.0 ECA1HHG101( ) 200 1000 220 10 12.5 300 0.12 2000 0.6 5.0 5.0 ECA1HHG221( ) 200 500 330 10 16 410 0.12 2000 0.6 5.0 5.0 ECA1HHG331( ) 200 500 470 10 20 530 0.12 2000 0.6 5.0 5.0 ECA1HHG471( ) 200 500 1000 12.5 25 950 0.12 2000 0.6 5.0 5.0 ECA1HHG102( ) 200 500 2200 16 31.5 1470 0.14 2000 0.8 7.5 ECA1HHG222 100 3300 18 35.5 1770 0.16 2000 0.8 7.5 ECA1HHG332 50 63 10 5 11 46 0.10 1000 0.5 2.0 5.0 2.5 ECA1JHG100( ) 200 2000 22 5 11 71 0.10 1000 0.5 2.0 5.0 2.5 ECA1JHG220( ) 200 2000 33 6.3 11.2 100 0.10 1000 0.5 2.5 5.0 2.5 ECA1JHG330( ) 200 2000 47 6.3 11.2 120 0.10 1000 0.5 2.5 5.0 2.5 ECA1JHG470( ) 200 2000 100 10 12.5 215 0.10 2000 0.6 5.0 5.0 ECA1JHG101( ) 200 500 220 10 16 335 0.10 2000 0.6 5.0 5.0 ECA1JHG221( ) 200 500 330 10 20 510 0.10 2000 0.6 5.0 5.0 ECA1JHG331( ) 200 500 470 12.5 20 640 0.10 2000 0.6 5.0 5.0 ECA1JHG471( ) 200 500 1000 16 25 930 0.10 2000 0.8 7.5 7.5 ECA1JHG102( ) 100 250 2200 18 35.5 1610 0.12 2000 0.8 7.5 ECA1JHG222 50 100 0.47 5 11 9 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHGR47( )✽✽✽ 200 2000 1 5 11 14 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG010( )✽✽✽ 200 2000 2.2 5 11 21 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG2R2( ) 200 2000 3.3 5 11 31 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG3R3( ) 200 2000 4.7 5 11 38 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG4R7( ) 200 2000 10 6.3 11.2 54 0.08 1000 0.5 2.5 5.0 2.5 ECA2AHG100( ) 200 2000 22 6.3 11.2 93 0.08 1000 0.5 2.5 5.0 2.5 ECA2AHG220( ) 200 2000 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. ✽✽✽ Please kindly accept last shipment : 31/Mar/2015 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-102 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 100 33 8 11.5 130 0.08 1000 0.6 3.5 5.0 ECA2AHG330( ) 200 1000 47 10 12.5 165 0.08 2000 0.6 5.0 5.0 ECA2AHG470( ) 200 500 100 10 20 265 0.08 2000 0.6 5.0 5.0 ECA2AHG101( ) 200 500 220 12.5 25 440 0.08 2000 0.6 5.0 5.0 ECA2AHG221( ) 200 500 330 16 25 540 0.08 2000 0.8 7.5 7.5 ECA2AHG331( ) 100 250 470 16 25 715 0.08 2000 0.8 7.5 7.5 ECA2AHG471( ) 100 250 1000 18 35.5 985 0.08 2000 0.8 7.5 ECA2AHG102 50 160 1 6.3 11.2 17 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG010( ) 200 2000 2.2 6.3 11.2 25 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG2R2( ) 200 2000 3.3 6.3 11.2 36 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG3R3( ) 200 2000 4.7 6.3 11.2 43 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG4R7( ) 200 2000 10 10 12.5 70 0.15 2000 0.6 5.0 5.0 ECA2CHG100( ) 200 500 22 10 20 130 0.15 2000 0.6 5.0 5.0 ECA2CHG220( ) 200 500 33 10 20 180 0.15 2000 0.6 5.0 5.0 ECA2CHG330( ) 200 500 47 12.5 20 220 0.15 2000 0.6 5.0 5.0 ECA2CHG470( ) 200 500 100 16 25 335 0.15 2000 0.8 7.5 7.5 ECA2CHG101( ) 100 250 220 16 31.5 540 0.15 2000 0.8 7.5 ECA2CHG221 100 330 18 31.5 705 0.15 2000 0.8 7.5 ECA2CHG331 50 200 1 6.3 11.2 17 0.15 2000 0.5 2.5 5.0 2.5 ECA2DHG010( ) 200 2000 2.2 6.3 11.2 25 0.15 2000 0.5 2.5 5.0 2.5 ECA2DHG2R2( ) 200 2000 3.3 6.3 11.2 36 0.15 2000 0.5 2.5 5.0 2.5 ECA2DHG3R3( ) 200 2000 4.7 8 11.5 50 0.15 2000 0.6 3.5 5.0 ECA2DHG4R7( ) 200 1000 10 10 16 80 0.15 2000 0.6 5.0 5.0 ECA2DHG100( ) 200 500 22 10 20 140 0.15 2000 0.6 5.0 5.0 ECA2DHG220( ) 200 500 33 12.5 20 190 0.15 2000 0.6 5.0 5.0 ECA2DHG330( ) 200 500 47 12.5 20 220 0.15 2000 0.6 5.0 5.0 ECA2DHG470( ) 200 500 100 16 25 335 0.15 2000 0.8 7.5 7.5 2.5 ECA2DHG101( ) 100 250 220 18 31.5 575 0.15 2000 0.8 7.5 ECA2DHG221 50 250 1 6.3 11.2 17 0.15 2000 0.5 2.5 5.0 2.5 ECA2EHG010( ) 200 2000 2.2 6.3 11.2 29 0.15 2000 0.5 2.5 5.0 2.5 ECA2EHG2R2( ) 200 2000 3.3 8 11.5 42 0.15 2000 0.6 3.5 5.0 ECA2EHG3R3 200 1000 4.7 8 11.5 50 0.15 2000 0.6 3.5 5.0 ECA2EHG4R7( ) 200 1000 10 10 16 88 0.15 2000 0.6 5.0 5.0 ECA2EHG100( ) 200 500 22 12.5 20 155 0.15 2000 0.6 5.0 5.0 ECA2EHG220( ) 200 500 33 12.5 20 190 0.15 2000 0.6 5.0 5.0 ECA2EHG330( ) 200 500 47 12.5 25 230 0.15 2000 0.6 5.0 5.0 ECA2EHG470( ) 200 500 100 16 31.5 365 0.15 2000 0.8 7.5 ECA2EHG101 100 350 1 6.3 11.2 18 0.20 2000 0.5 2.5 5.0 2.5 ECA2VHG010( ) 200 2000 2.2 8 11.5 31 0.20 2000 0.6 3.5 5.0 ECA2VHG2R2( ) 200 1000 3.3 10 12.5 38 0.20 2000 0.6 5.0 5.0 ECA2VHG3R3( ) 200 500 4.7 10 16 50 0.20 2000 0.6 5.0 5.0 ECA2VHG4R7( ) 200 500 10 10 20 82 0.20 2000 0.6 5.0 5.0 ECA2VHG100( ) 200 500 22 12.5 20 130 0.20 2000 0.6 5.0 5.0 ECA2VHG220( ) 200 500 33 16 25 195 0.20 2000 0.8 7.5 7.5 ECA2VHG330( ) 100 250 47 16 25 230 0.20 2000 0.8 7.5 7.5 ECA2VHG470( ) 100 250 100 18 31.5 375 0.20 2000 0.8 7.5 ECA2VHG101 50 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-103 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 400 1 6.3 11.2 18 0.24 2000 0.5 2.5 5.0 2.5 ECA2GHG010( ) 200 2000 2.2 8 11.5 30 0.24 2000 0.6 3.5 5.0 ECA2GHG2R2( ) 200 1000 3.3 10 12.5 40 0.24 2000 0.6 5.0 5.0 ECA2GHG3R3( ) 200 500 4.7 10 16 50 0.24 2000 0.6 5.0 5.0 ECA2GHG4R7( ) 200 500 10 10 20 80 0.24 2000 0.6 5.0 5.0 ECA2GHG100( ) 200 500 22 12.5 25 145 0.24 2000 0.6 5.0 5.0 ECA2GHG220( ) 200 500 33 16 25 195 0.24 2000 0.8 7.5 7.5 ECA2GHG330( ) 100 250 47 16 31.5 250 0.24 2000 0.8 7.5 ECA2GHG470 100 450 1 8 11.5 18 0.24 2000 0.6 3.5 5.0 ECA2WHG010( ) 200 1000 2.2 10 12.5 29 0.24 2000 0.6 5.0 5.0 ECA2WHG2R2( ) 200 500 3.3 10 16 41 0.24 2000 0.6 5.0 5.0 ECA2WHG3R3( ) 200 500 4.7 10 20 49 0.24 2000 0.6 5.0 5.0 ECA2WHG4R7( ) 200 500 10 12.5 20 75 0.24 2000 0.6 5.0 5.0 ECA2WHG100( ) 200 500 22 16 25 115 0.24 2000 0.8 7.5 7.5 ECA2WHG220( ) 100 250 33 16 31.5 155 0.24 2000 0.8 7.5 ECA2WHG330 100 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. 01 Oct. 2013  Highest ripple current capability for demanding inverter applications  2 and 3 pin versions available  3000 hour life at 105ºC Part Number System Voltage Capacitance Code Code 2 3 4.0mm 4.0mm H P J Q K R L S TS-ED Standard Ratings (part numbers shown with 6.3mm length terminal and top vinyl plate) Cap. Panasonic Cap. Panasonic (μF) 120Hz 10kHz~ 120Hz 20kHz Part Number (μF) 120Hz 10kHz~ 120Hz 20kHz Part Number 270 22 x 25 1.42 2.03 0.553 0.249 EETED2D271BA 390 22 x 40 1.72 2.45 0.383 0.172 EETED2E391BA 330 22 x 30 1.56 2.23 0.452 0.203 EETED2D331BA 25 x 30 1.71 2.44 0.383 0.172 EETED2E391CA 390 22 x 30 1.71 2.44 0.383 0.172 EETED2D391BA 30 x 25 1.71 2.44 0.383 0.172 EETED2E391DA 25 x 25 1.71 2.44 0.383 0.172 EETED2D391CA 470 22 x 45 1.85 2.64 0.317 0.143 EETED2E471BA 470 22 x 35 1.85 2.64 0.317 0.143 EETED2D471BA 25 x 35 1.85 2.64 0.317 0.143 EETED2E471CA 25 x 30 1.85 2.64 0.317 0.143 EETED2D471CA 30 x 30 1.85 2.64 0.317 0.143 EETED2E471DA 560 22 x 40 2.14 3.05 0.266 0.120 EETED2D561BA 560 25 x 40 2.14 3.05 0.266 0.120 EETED2E561CA 25 x 30 2.14 3.05 0.266 0.120 EETED2D561CA 30 x 30 2.14 3.05 0.266 0.120 EETED2E561DA 30 x 25 2.14 3.05 0.266 0.120 EETED2D561DA 35 x 25 2.14 3.05 0.266 0.133 EETED2E561EA 680 22 x 45 2.42 3.45 0.219 0.099 EETED2D681BA 680 25 x 45 2.42 3.45 0.219 0.099 EETED2E681CA 25 x 35 2.42 3.45 0.219 0.099 EETED2D681CA 30 x 35 2.42 3.45 0.219 0.099 EETED2E681DA 30 x 30 2.42 3.45 0.219 0.099 EETED2D681DA 35 x 30 2.42 3.45 0.219 0.110 EETED2E681EA 820 22 x 50 2.63 3.76 0.182 0.082 EETED2D821BA 820 30 x 40 2.63 3.76 0.182 0.082 EETED2E821DA 25 x 40 2.63 3.76 0.182 0.082 EETED2D821CA 35 x 35 2.63 3.76 0.182 0.091 EETED2E821EA 30 x 30 2.63 3.76 0.182 0.082 EETED2D821DA 1000 30 x 50 2.84 4.06 0.149 0.067 EETED2E102DA 35 x 25 2.63 3.76 0.182 0.091 EETED2D821EA 35 x 40 2.84 4.06 0.149 0.067 EETED2E102EA 1000 25 x 45 2.84 4.06 0.149 0.067 EETED2D102CA 1200 35 x 45 3.13 4.47 0.124 0.062 EETED2E122EA 30 x 35 2.84 4.06 0.149 0.067 EETED2D102DA 1500 35 x 50 3.56 5.08 0.099 0.050 EETED2E152EA 35 x 30 2.84 4.06 0.149 0.067 EETED2D102EA 1200 30 x 40 3.13 4.47 0.124 0.062 EETED2D122DA 82 22 x 25 0.80 1.14 1.617 0.728 EETED2G820BA 35 x 35 3.13 4.47 0.124 0.062 EETED2D122EA 100 22 x 30 0.91 1.30 1.326 0.597 EETED2G101BA 1500 30 x 50 3.56 5.08 0.099 0.050 EETED2D152DA 25 x 25 0.91 1.30 1.326 0.597 EETED2G101CA 35 x 40 3.56 5.08 0.099 0.050 EETED2D152EA 120 22 x 35 1.02 1.46 1.105 0.497 EETED2G121BA 1800 35 x 45 3.84 5.48 0.083 0.041 EETED2D182EA 25 x 30 1.02 1.46 1.105 0.497 EETED2G121CA 2200 35 x 50 4.12 5.89 0.068 0.033 EETED2D222EA 150 22 x 40 1.07 1.53 0.884 0.398 EETED2G151BA 25 x 30 1.07 1.53 0.884 0.398 EETED2G151CA 220 22 x 30 1.28 1.83 0.678 0.305 EETED2E221BA 30 x 25 1.07 1.53 0.884 0.398 EETED2G151DA 270 22 x 30 1.42 2.03 0.553 0.249 EETED2E271BA 180 22 x 45 1.12 1.60 0.737 0.332 EETED2G181BA 25 x 25 1.42 2.03 0.553 0.249 EETED2E271CA 25 x 35 1.12 1.60 0.737 0.332 EETED2G181CA 330 22 x 35 1.64 2.34 0.452 0.203 EETED2E331BA 30 x 30 1.12 1.60 0.737 0.332 EETED2G181DA 25 x 30 1.56 2.23 0.452 0.203 EETED2E331CA 220 22 x 50 1.42 2.03 0.603 0.271 EETED2G221BA 56 ~ 560μF Common Code Endurance: 3000 hours at +105°C with maximum specified ripple current (see page 6) Capacitance Tolerance: Dissipation Factor (120Hz, 20°C): 15% maximum (120Hz, +20°C) 220~2200 μF *Use of temperature ripple current multipliers may limit life to the hours specified for the maximum operating temperature. Rated Working Voltage: Leakage Current: Ripple Current Multipliers: 2 3√CV (μA) max. after 5 minutes; C = Capacitance in μF, V = WV PVC without top plate Operating Temperature: -40 ~ +105°C -25 ~ +105°C Max 105°C R.C. (Arms) 20°C ESR (Ω, max.) D x L Max 105°C R.C. (Arms) 20°C ESR (Ω, max.) Size (mm) 250 VDC Working, 300 VDC Surge (continued) (no suffix) 250 VDC Working, 300 VDC Surge D E B 400 VDC Working, 450 VDC Surge D x L (Please see page 10 for details) Diameter J PET sleeve without plate Size (mm) TS-ED Series 105°C, 3000 hours 200 VDC Working, 250 VDC Surge Nominal Capacitance: Series Insulation Options 6.3mm 200 ~ 250 VDC 400 ~ 450 VDC Code ± 20% 35mm 30mm 25mm 22mm C Diameter / Terminal Code A PVC with top plate # of pins: pin length: E E T E D Ripple Current Frequency Factors Frequency(Hz): Multiplier: 50 0.71 60 0.78 100~120 1.0 1.2 1k 1.25 10k~ 1.4 Ripple Current Ambient Temperature Factors* ≤45°C 2.35 Ambient Temperature: 85°C 70°C 60°C Multiplier: 1.0 2.0 2.2 500 105°C 1.7 Design and specifi cations are subject to change without notice. Ask factory for technical specifi cations before purchase and/or use. Whenever a doubt about safety arises from this product, please contact us immediately for technical consultation. Large Can Aluminum Electrolytic Capacitors TS-ED Standard Ratings (continued) Cap. Panasonic (μF) 120Hz 10kHz~ 120Hz 20kHz Part Number 220 25 x 40 1.42 2.03 0.603 0.271 EETED2G221CA 30 x 30 1.42 2.03 0.603 0.271 EETED2G221DA 35 x 25 1.42 2.03 0.603 0.271 EETED2G221EA 270 25 x 45 1.56 2.23 0.491 0.221 EETED2G271CA 30 x 35 1.56 2.23 0.491 0.221 EETED2G271DA 35 x 30 1.56 2.23 0.491 0.221 EETED2G271EA 330 30 x 40 1.71 2.44 0.402 0.181 EETED2G331DA 35 x 30 1.71 2.44 0.402 0.181 EETED2G331EA 390 30 x 45 1.85 2.64 0.340 0.153 EETED2G391DA 35 x 35 1.85 2.64 0.340 0.153 EETED2G391EA 470 35 x 40 2.01 2.87 0.282 0.127 EETED2G471EA 560 35 x 45 2.35 3.36 0.237 0.107 EETED2G561EA 68 22 x 25 1.08 0.95 1.950 0.878 EETED2S680BA 82 22 x 30 1.14 1.08 1.617 0.728 EETED2S820BA 25 x 25 1.14 1.08 1.617 0.728 EETED2S820CA 100 22 x 30 1.30 1.14 1.326 0.597 EETED2S101BA 25 x 25 1.30 1.14 1.326 0.597 EETED2S101CA 120 22 x 35 1.46 1.30 1.105 0.497 EETED2S121BA 25 x 30 1.46 1.30 1.105 0.497 EETED2S121CA 150 22 x 40 1.53 1.46 0.884 0.398 EETED2S151BA 25 x 35 1.53 1.46 0.884 0.398 EETED2S151CA 30 x 25 1.53 1.46 0.884 0.398 EETED2S151DA 180 22 x 45 1.60 1.53 0.737 0.332 EETED2S181BA 25 x 40 1.60 1.53 0.737 0.332 EETED2S181CA 30 x 30 1.60 1.53 0.737 0.332 EETED2S181DA 35 x 25 1.60 1.53 0.737 0.332 EETED2S181EA 220 25 x 45 2.03 1.60 0.603 0.271 EETED2S221CA 30 x 35 2.03 1.60 0.603 0.271 EETED2S221DA 35 x 30 2.03 1.60 0.603 0.271 EETED2S221EA 270 25 x 50 2.40 2.03 0.491 0.221 EETED2S271CA 30 x 40 2.40 2.03 0.491 0.221 EETED2S271DA 35 x 30 2.40 2.03 0.491 0.221 EETED2S271EA 330 30 x 45 2.54 2.45 0.402 0.181 EETED2S331DA 35 x 35 2.54 2.45 0.402 0.181 EETED2S331EA 390 30 x 50 2.73 2.64 0.340 0.153 EETED2S391DA 35 x 40 2.73 2.64 0.340 0.153 EETED2S391EA 470 35 x 45 3.18 2.82 0.282 0.127 EETED2S471EA 56 22 x 25 0.67 0.95 2.368 1.066 EETED2W560BA 68 22 x 30 0.76 1.08 1.950 0.878 EETED2W680BA 25 x 25 0.76 1.08 1.950 0.878 EETED2W680CA 82 22 x 30 0.80 1.14 1.617 0.728 EETED2W820BA 25 x 25 0.80 1.14 1.617 0.728 EETED2W820CA 100 22 x 35 0.91 1.30 1.326 0.597 EETED2W101BA 25 x 30 0.91 1.30 1.326 0.597 EETED2W101CA 120 22 x 40 1.02 1.46 1.105 0.497 EETED2W121BA 25 x 35 1.02 1.46 1.105 0.497 EETED2W121CA 30 x 25 1.02 1.46 1.105 0.497 EETED2W121DA 150 22 x 45 1.07 1.53 0.884 0.398 EETED2W151BA 25 x 40 1.07 1.53 0.884 0.398 EETED2W151CA 30 x 30 1.07 1.53 0.884 0.398 EETED2W151DA 35 x 25 1.07 1.53 0.884 0.398 EETED2W151EA 180 22 x 50 1.12 1.60 0.737 0.332 EETED2W181BA 25 x 40 1.12 1.60 0.737 0.332 EETED2W181CA 30 x 30 1.12 1.60 0.737 0.332 EETED2W181DA 35 x 25 1.12 1.60 0.737 0.332 EETED2W181EA 220 25 x 45 1.42 2.03 0.603 0.271 EETED2W221CA 30 x 35 1.42 2.03 0.603 0.271 EETED2W221DA 35 x 30 1.42 2.03 0.603 0.271 EETED2W221EA 270 30 x 40 1.72 2.45 0.491 0.221 EETED2W271DA 35 x 35 1.72 2.45 0.491 0.221 EETED2W271EA 330 30 x 50 1.85 2.64 0.402 0.181 EETED2W331DA 35 x 40 1.85 2.64 0.402 0.181 EETED2W331EA 390 35 x 40 1.97 2.82 0.340 0.153 EETED2W391EA 470 35 x 50 2.47 3.53 0.282 0.127 EETED2W471EA D x L Size (mm) Max 105°C R.C. (Arms) 20°C ESR (Ω, max.) 400 VDC Working, 450 VDC Surge (continued) 420 VDC Working, 470 VDC Surge 450 VDC Working, 500 VDC Surge Design and specifi cations are subject to change without notice. Ask factory for technical specifi cations before purchase and/or use. Whenever a doubt about safety arises from this product, please contact us immediately for technical consultation. Large Can Aluminum Electrolytic Capacitors 1. Product profile 1.1 General description PNP Resistor-Equipped Transistor (RET) family in Surface-Mounted Device (SMD) plastic packages. 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k Rev. 5 — 9 December 2011 Product data sheet Table 1. Product overview Type number Package NPN complement Package NXP JEITA JEDEC configuration PDTA143XE SOT416 SC-75 - PDTC143XE ultra small PDTA143XM SOT883 SC-101 - PDTC143XM leadless ultra small PDTA143XT SOT23 - TO-236AB PDTC143XT small PDTA143XU SOT323 SC-70 - PDTC143XU very small  100 mA output current capability  Reduces component count  Built-in bias resistors  Reduces pick and place costs  Simplifies circuit design  AEC-Q101 qualified  Digital applications in automotive and industrial segments  Cost-saving alternative for BC847/857 series in digital applications  Control of IC inputs  Switching loads Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - 50 V IO output current - - 100 mA R1 bias resistor 1 (input) 3.3 4.7 6.1 k R2/R1 bias resistor ratio 1.7 2.1 2.6 PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 2 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 2. Pinning information 3. Ordering information 4. Marking [1] * = placeholder for manufacturing site code Table 3. Pinning Pin Description Simplified outline Graphic symbol SOT23; SOT323; SOT416 1 input (base) 2 GND (emitter) 3 output (collector) SOT883 1 input (base) 2 GND (emitter) 3 output (collector) 006aaa144 1 2 3 sym003 3 2 1 R1 R2 3 1 2 Transparent top view sym003 3 2 1 R1 R2 Table 4. Ordering information Type number Package Name Description Version PDTA143XE SC-75 plastic surface-mounted package; 3 leads SOT416 PDTA143XM SC-101 leadless ultra small plastic package; 3 solder lands; body 1.0  0.6  0.5 mm SOT883 PDTA143XT - plastic surface-mounted package; 3 leads SOT23 PDTA143XU SC-70 plastic surface-mounted package; 3 leads SOT323 Table 5. Marking codes Type number Marking code[1] PDTA143XE 35 PDTA143XM DN PDTA143XT *31 PDTA143XU *46 PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 3 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. [3] Device mounted on an FR4 PCB with 70 m copper strip line, standard footprint. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - 50 V VCEO collector-emitter voltage open base - 50 V VEBO emitter-base voltage open collector - 7 V VI input voltage positive - +7 V negative - 20 V IO output current - 100 mA ICM peak collector current single pulse; tp  1 ms - 100 mA Ptot total power dissipation Tamb  25 C PDTA143XE (SOT416) [1][2]- 150 mW PDTA143XM (SOT883) [2][3]- 250 mW PDTA143XT (SOT23) [1]- 250 mW PDTA143XU (SOT323) [1]- 200 mW Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 4 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. [3] Device mounted on an FR4 PCB with 70 m copper strip line, standard footprint. (1) SOT23; FR4 PCB, standard footprint SOT883; FR4 PCB with 70 m copper strip line, standard footprint (2) SOT323; FR4 PCB, standard footprint (3) SOT416; FR4 PCB, standard footprint Fig 1. Power derating curves Tamb (°C) -75 -25 25 75 125 175 006aac778 100 200 300 Ptot (mW) 0 (1) (2) (3) Table 7. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air PDTA143XE (SOT416) [1][2]- - 830 K/W PDTA143XM (SOT883) [2][3]- - 500 K/W PDTA143XT (SOT23) [1]- - 500 K/W PDTA143XU (SOT323) [1]- - 625 K/W PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 5 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k FR4 PCB, standard footprint Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration for PDTA143XE (SOT416); typical values FR4 PCB, 70 m copper strip line Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration for PDTA143XM (SOT883); typical values 006aac781 10-5 10-4 10-2 10-1 10 102 tp (s) 10-3 1 103 102 10 103 Zth(j-a) (K/W) 1 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 006aac782 10-5 10-4 10-2 10-1 10 102 tp (s) 10-3 1 103 102 10 103 Zth(j-a) (K/W) 1 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 6 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k FR4 PCB, standard footprint Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration for PDTA143XT (SOT23); typical values FR4 PCB, standard footprint Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration for PDTA143XU (SOT323); typical values 006aac779 10-5 10-4 10-2 10-1 10 102 tp (s) 10-3 1 103 102 10 103 Zth(j-a) (K/W) 1 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 006aac780 10-5 10-4 10-2 10-1 10 102 tp (s) 10-3 1 103 102 10 103 Zth(j-a) (K/W) 1 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 7 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 7. Characteristics [1] Characteristics of built-in transistor Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = 50 V; IE = 0 A - - 100 nA ICEO collector-emitter cut-off current VCE = 30 V; IB = 0 A - - 1 A VCE = 30 V; IB = 0 A; Tj = 150 C - - 5 A IEBO emitter-base cut-off current VEB = 5 V; IC = 0 A - - 600 A hFE DC current gain VCE = 5 V; IC = 10 mA 50 - - VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - - 100 mV VI(off) off-state input voltage VCE = 5 V; IC = 100 A - 0.9 0.3 V VI(on) on-state input voltage VCE = 0.3 V; IC = 20 mA 2.5 1.5 - V R1 bias resistor 1 (input) 3.3 4.7 6.1 k R2/R1 bias resistor ratio 1.7 2.1 2.6 Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - - 3 pF fT transition frequency VCE = 5 V; IC = 10 mA; f = 100 MHz [1]- 180 - MHz PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 8 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k VCE = 5 V (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = 40 C IC/IB = 20 (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = 40 C Fig 6. DC current gain as a function of collector current; typical values Fig 7. Collector-emitter saturation voltage as a function of collector current; typical values VCE = 0.3 V (1) Tamb = 40 C (2) Tamb = 25 C (3) Tamb = 100 C VCE = 5 V (1) Tamb = 40 C (2) Tamb = 25 C (3) Tamb = 100 C Fig 8. On-state input voltage as a function of collector current; typical values Fig 9. Off-state input voltage as a function of collector current; typical values IC (mA) -10-1 -1 -10 -102 006aac846 102 10 103 hFE 1 (1) (2) (3) IC (mA) -1 -10 -102 006aac847 -10-1 -1 VCEsat (V) -10-2 (1) (2) (3) 006aac848 IC (mA) -10-1 -1 -10 -102 -1 -10 VI(on) (V) -10-1 (1) (2) (3) IC (mA) -10-1 -1 -10 006aac849 -1 -10 VI(off) (V) -10-1 (1) (2) (3) PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 9 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. f = 1 MHz; Tamb = 25 C VCE = 5 V; Tamb = 25 C Fig 10. Collector capacitance as a function of collector-base voltage; typical values Fig 11. Transition frequency as a function of collector current; typical values of built-in transistor VCB (V) 0 -10 -20 -30 -40 -50 006aac850 4 2 6 8 Cc (pF) 0 006aac763 IC (mA) -10-1 -1 -10 -102 102 103 fT (MHz) 10 PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 10 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. Fig 12. Package outline PDTA143XE (SOT416/SC-75) Fig 13. Package outline PDTA143XM (SOT883/SC-101) Fig 14. Package outline PDTA143XT (SOT23) Fig 15. Package outline PDTA143XU (SOT323/SC-70) Dimensions in mm 04-11-04 0.95 0.60 1.8 1.4 1.75 1.45 0.9 0.7 0.25 0.10 1 0.30 0.15 1 2 3 0.45 0.15 Dimensions in mm 03-04-03 0.62 0.55 0.55 0.47 0.50 0.46 0.65 0.20 0.12 3 2 1 0.30 0.22 0.30 0.22 1.02 0.95 0.35 Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Dimensions in mm 04-11-04 0.45 0.15 1.1 0.8 2.2 1.8 2.2 2.0 1.35 1.15 1.3 0.4 0.3 0.25 0.10 1 2 3 Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 5000 10000 PDTA143XE SOT416 4 mm pitch, 8 mm tape and reel -115 - -135 PDTA143XM SOT883 2 mm pitch, 8 mm tape and reel - - -315 PDTA143XT SOT23 4 mm pitch, 8 mm tape and reel -215 - -235 PDTA143XU SOT323 4 mm pitch, 8 mm tape and reel -115 - -135 PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 11 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 11. Soldering Reflow soldering is the only recommended soldering method. Fig 16. Reflow soldering footprint PDTA143XE (SOT416/SC-75) Reflow soldering is the only recommended soldering method. Fig 17. Reflow soldering footprint PDTA143XM (SOT883/SC-101) solder lands solder resist occupied area solder paste sot416_fr 0.85 1.7 2.2 2 0.5 (3×) 0.6 (3×) 1 1.3 Dimensions in mm solder lands solder resist occupied area solder paste sot883_fr 1.3 0.3 0.6 0.7 0.4 0.9 0.3 (2×) 0.4 (2×) 0.25 (2×) 0.7 R0.05 (12×) Dimensions in mm PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 12 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k Fig 18. Reflow soldering footprint PDTA143XT (SOT23) Fig 19. Wave soldering footprint PDTA143XT (SOT23) solder lands solder resist occupied area solder paste sot023_fr 0.5 (3×) 0.6 (3×) 0.6 (3×) 0.7 (3×) 3 1 3.3 2.9 1.7 1.9 2 Dimensions in mm solder lands solder resist occupied area preferred transport direction during soldering sot023_fw 2.8 4.5 1.4 4.6 1.4 (2×) 1.2 (2×) 2.2 2.6 Dimensions in mm PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 13 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k Fig 20. Reflow soldering footprint PDTA143XU (SOT323/SC-70) Fig 21. Wave soldering footprint PDTA143XU (SOT323/SC-70) solder lands solder resist occupied area solder paste sot323_fr 2.65 2.35 0.6 (3×) 0.5 (3×) 0.55 (3×) 1.325 1.85 1.3 3 2 1 Dimensions in mm sot323_fw 3.65 2.1 1.425 (3×) 4.6 09 (2×) 2.575 1.8 solder lands solder resist occupied area preferred transport direction during soldering Dimensions in mm PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 14 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PDTA143X_SER v.5 20111209 Product data sheet - PDTA143X_SERIES v.4 Modifications: • Type numbers PDTA143XK and PDTA143XS removed. • Section 1 “Product profile”: updated • Section 4 “Marking”: updated • Figure 1 to 5, 10 and 11: added • Section 6 “Thermal characteristics”: updated • Figure 6 to 9: updated • Table 8 “Characteristics”: ICEO updated, fT added • Section 8 “Test information”: added • Section 11 “Soldering”: added • Section 13 “Legal information”: updated PDTA143X_SERIES v.4 20070416 Product data sheet - PDTA143X_SERIES v.3 PDTA143X_SERIES v.3 20040804 Product specification - PDTA143X_SERIES v.2 PDTA143X_SERIES v.2 20030410 Product specification - - PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 15 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PDTA143X_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 9 December 2011 16 of 17 NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors PDTA143X series PNP resistor-equipped transistors; R1 = 4.7 k, R2 = 10 k © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2011 Document identifier: PDTA143X_SER Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 9 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 10 Packing information . . . . . . . . . . . . . . . . . . . . 10 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 Contact information. . . . . . . . . . . . . . . . . . . . . 16 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Circuit Imprimé Français - Tools ECO Series TECHNO LABORATORY DRILLS TECHNO 003 MR TECHNO 003 R Model TECHNO 003 MR TECHNO 003 R TECHNO 003 MRE Adjustable rotation speed 11000 à 37000 rpm 11000 à 37000 rpm 11000 à 37000 rpm Capacity Ø 0.2 à 3.2 mm Ø 0.2 à 3.2 mm 0,2 à 3,2 mm Swan neck 120 mm 170 mm 120 mm Work table 250 x 150 mm 380 x 295 mm 250 x 150 mm Spindle travel 6 mm 6 mm 6 mm Low voltage lighting Yes Yes No Dust removal connection Yes Yes No External dimensions 250 x 150 x 260 mm 380 x 295 x 260 mm 250 x 150 x 260 mm Weight 4 kg 5 kg 3,8 kg Spindle output 115 W 115 W 115 W Electrical connection 220 /240 V - 50/60 Hz 220/240 - 50/60 Hz 220/240 V - 50/60 Hz Code DP 593 EP 503 DP 595 TECHNO 001 TECHNO 002 http://www.cif.fr/uk/ukp40.shtml (1 of 2) [04/08/03 11:08:09] Circuit Imprimé Français - Tools Model TECHNO 001 TECHNO 002 Adjustable rotation speed 8000 à 20000 rpm 20000 rpm Capacity Ø 0.2 à 3.2 mm Ø 0.2 à 3.2 mm Swan neck 175 mm 150 mm Work table 285 x 245 mm 300 x 245 mm Spindle travel 25 mm 15 mm Automatic clamping chuck Ø 0.2 à 3.2 mm Ø 0.2 à 3.2 mm Low voltage lighting Yes Yes Dust removal connection Yes Yes External dimensions 395 x 245 x 230 mm 395 x 245 x 250 mm Weight 8,5 kg 5 kg Spindle output 130 W 24 V/30 W Electrical connection 220/240 V - 50/60 Hz 220/240 V - 50/60 Hz Code EP 501 EP 502 © Circuit Imprimé Français - Technical conception : France Cybermedia - http://www.cif.fr/uk/ukp40.shtml (2 of 2) [04/08/03 11:08:09] DEUTSCH – ENGLISH - FRANCAIS D Bedienungsanleitung ANSMANN Starlight-Serie Starlight 200 (UK) und Starlight 400 (UK) (Starlight 300 – nicht mehr lieferbar) Seite 1 HINWEIS Dieses Gerät muss vor dem Erstgebrauch unbedingt 24 Stunden geladen werden. Der Akku- Handscheinwerfer ist für Dauerladung ausgelegt, d.h. der Steckertrafo verbleibt in der Steckdose und der Arbeitsscheinwerfer im Wandhalter (9). BEFESTIGIGUNG DER WANDHALTERUNG (9) Bohren Sie 2 Löcher im waagrechten Abstand von 87 mm in die Wand. Achten Sie darauf, dass die Wandhalterung in der Nähe einer Steckdose montiert wird, wobei das Netzversorgungskabel in der Mauer nicht beschädigt werden darf. Fixieren Sie die Wandhalterung nun mittels zweier Schrauben in der Wand. AUFLADUNG DES AKKU-ARBEITSSCHEINWERFERS Laden Sie den Akku-Arbeitscheinwerfer vor dem ersten Gebrauch mindestens 24 Stunden auf. Die Aufladung erfolgt in der Wandhalterung (9). Das Ladenetzteil kann dauernd in der Steckdose verbleiben. Der Arbeitsscheinwerfer wird also, sofern Sie Ihn nicht benutzen, in der Wandhalterung dauernd aufgeladen (Dauerladung). Die Aufladung wird durch das Leuchten der Ladekontroll-Leuchte (7) angezeigt. LEUCHTDAUER Die Leuchtdauer des Arbeitsscheinwerfers entnehmen Sie bitte der Tabelle (H – Seite 3). ANWENDUNG Bei Bedarf nehmen Sie bitte den Arbeitsscheinwerfer aus der Wandhalterung (9). Der Handgriff ist um 180 Grad schwenkbar und kann in vier Raststufen hochgeklappt werden. Während des Hoch- oder Zurückklappens muss der Klappmechanismus durch Drücken der Entriegelungstaste entriegelt werden. Mit dem Schiebeschalter (1) schalten Sie den Scheinwerfer ein. Starlight 300 und 400 haben zwei Schaltstufen. 1. Stufe Krypton-Lampe; 2. Stufe Halogen-Lampe. D Bedienungsanleitung ANSMANN Starlight-Serie Starlight 200 (UK) und Starlight 400 (UK) (Starlight 300 – nicht mehr lieferbar) Seite 2 FOKUSSIERUNG Den Brennpunkt des Lichtstrahls können Sie durch Drehen der Fokussierung (4) einstellen. Durch Drehen bis zum rechten Anschlag wird bei Starlight 400 die Blinkelektronik eingeschaltet. Es blinkt die Glühlampe, welche mit dem Schiebeschalter (1) geschaltet ist. AUSWECHSELN DER GLÜHBIRNE Drücken Sie den Gummiring des Reflektors an den beiden Druckpunkten (10) zusammen. Der Reflektor lässt sich nun aus dem Scheinwerfergehäuse herausnehmen und die Glühlampen können gewechselt werden. ZUBEHÖR Starlight 300 und Starlight 400 sind mit Trageriemen (T) ausgestattet. Dieser wird an den beiden Ösen seitlich am Gehäuse befestigt. Starlight 400 ist mit 2 Filterscheiben (F) (rot u. grün) ausgestattet (im Gehäuse des Akkupacks ist Platz für zwei Filterscheiben vorgesehen). NETZAUSFALL-ELEKTRONIK Starlight 400 ist mit einer Netzausfall-Elektronik (N) ausgestattet. Der Handscheinwerfer wird im eingeschalteten Zustand in die Ladestation eingesteckt. Bei Stromausfall schaltet sich der Handscheinwerfer automatisch ein und dient somit als Notbeleuchtung. Nach Ende der Netzunterbrechung schaltet sich der Scheinwerfer wieder automatisch aus und der Akkupack wird wieder geladen. AUSWECHSELN DES AKKUS Nach gleichzeitigem Drücken der beiden Entriegelungspunkte (6) lässt sich der Akkupack herausziehen. D Bedienungsanleitung ANSMANN Starlight-Serie Starlight 200 (UK) und Starlight 400 (UK) (Starlight 300 – nicht mehr lieferbar) Seite 3 UMWELTHINWEIS Akkus gehören nicht in den Hausmüll. Geben Sie verbrauchte Akkus bei Ihrem Händler bzw. der Batteriesammelstelle ab. HINWEIS Das Gerät bitte nicht Nässe und extremen Temperaturen aussetzen. Wartungs- und Reinigungsarbeiten nur bei gezogenem Netzteil durchführen. Den Handscheinwerfer nur mit einem feuchten Tuch reinigen. TABELLE H Technische Daten Typ Nummer Leuchtmittel* Zubehör** Akkupack Leuchtweite Leuchtdauer Starlight 200 UK 5502046 4 W H 4,8V 800m 120 min Starlight 400 UK 5502056 10W H/4W KR T/N/F/B 6V 1200m 60(200)min Starlight 200 5102062 4 W H 4,8V 800m 120 min Starlight 400 5102082 10W H/4W KR T/N/F/B 6V 1200m 60(200)min Zubehör Leuchtmittel ** T = Tragegurt * H = Halogen ** N = Netzausfall-Elektronik * KR = Krypton ** F = Filterscheibe rot und grün ** B = Blink-Elektronik Weitere aktuelle Informationen ANSMANN ENERGY GMBH Industriestraße 10, 97959 Assamstadt Tel.: 06294-4204-0 Fax: 06294-4204-43 info@ansmann.de www.ansmann.de GB Operating Instructions ANSMANN Starlight Series Starlight 200 (UK) and Starlight 400 (UK) (Starlight 300 – no longer available) Page 1 CAUTION ! This appliance has to be charged for 24 hours before using it for the first time. The lamp can be charged continuously, i.e. the charging adaptor can remain permanently in the mains socket and the appliance in the wall bracket (9). MOUNTING OF THE WALL BRACKET (9) Drill two holes 110 mm apart vertically where you wish to fix the wall holder. We recommend that you fit the wall holder to the wall near a mains socket checking that the holes to be drilled are well away from the mains supply cable to the electrical socket. Fit the wall plugs into the holes, position the wall holder against the wall, insert screws and screw up tightly. CHARGING THE LAMP Before using the appliance for the first time charge it for at least 24 hours in the wall bracket (9). The charging unit can remain in the mains socket. This means that the lamp is constantly charged in the wall bracket. The LED (7) indicates that the appliance is being charged. When fully charged the lamp provide its full power. OPERATING TIME For appropriate operating time of your STARLIGHT model please refer to the table H (page 3). USING THE LAMP Before using the lamp take it out of the wall bracket (9). All Starlight lamps have a handle that can be moved by 180 degrees and be folded back in four different positions. The angle can be adjusted by moving the handle forward or backwards whilst pressing the release key (5). With the slide switch (1) you can switch on the lamp. The Starlight 300 and 400 have two switch positions. First step: Krypton; second step: Halogen GB Operating Instructions ANSMANN Starlight Series Starlight 200 (UK) and Starlight 400 (UK) (Starlight 300 – no longer available) Page 2 FOCUS You can adjust the focus by turning the zoom grip (4). Turning the zoom grip fully clockwise will cause the bulb selected by (1) to flash on and off. REPLACING THE BULB Press the rubber ring of the reflector at the two tabs (10). The reflector/lens can now be taken out of the lamp case and the bulbs can be replaced. ACCESSORIES Starlight 300 and 400 are supplied with a shoulder strap. It can be fastened to the two fixings on the upper sides of the case. Starlight 400 is supplied with two coloured filter slides (red and green). The power pack case provides storage for the two slides. MAINS-FAILURE DETECTION Starlight 400 has a mains-failure detection option. This means that the lamp will automatically switch on if it detects that there is a mains failure, to provide a safety light. When the lamp is placed into the wall bracket for charging with the light on, the bulb extinguishes. If it detects a mains failure, the bulb will light until the mains power is restored and the power pack is being charged again. REMOVAL OF THE RECHARGEABLE BATTERY PACK (8) Depress the two release positions (6) at the same time to remove the power pack. Operating Instructions ANSMANN Starlight Series Starlight 200 (UK) and Starlight 400 (UK) (Starlight 300 – no longer available) Page 3 ENVIRONMENTAL REFERENCE Rechargeable batteries must not be disposed of in domestic waste. Return used batteries to your dealer or to an authorised battery collecting point. TIP Keep the appliance in a dry place. Do not carry out any cleaning or maintenance work if the charger is plugged in. Only use a moist cloth to clean the lamp or the wall bracket. TABLE H Technical Data Type Number Bulb* Accessories**Battery Pack Beam Operating Time Starlight 200 UK 5502046 4 W H 4.8V 800m 120 min Starlight 400 UK 5502056 10W H/4W KR T/N/F/B 6V 1200m 60(200)min Starlight 200 5102062 4 W H 4.8V 800m 120 min Starlight 400 5102082 10W H/4W KR T/N/F/B 6V 1200m 60(200)min Accessories BULB ** T= Belt * H= Halogen ** N= Mains-failure electronics *KR= Krypton ** F= Colour-filter red and green ** B= Electronic Indicator For further information please contact ANSMANN ENERGY GMBH Industriestraße 10; D-97959 Assamstadt Fon.: +49 (0) 6294-4204-0 Fax: +49 (0) 6294- 4204-43 info@ansmann.de www.ansmann.de Instructions d’utilisation ANSMANN de la série Starlight F Starlight 200 et Starlight 400 (Starlight 300 – plus disponible) Page 1 REMARQUE Le projecteur doit absolument être chargé 24 heures avant la première utilisation. Le projecteur manuel à accu est conçu pour une charge longue, c’est à dire que la fiche du transformateur reste dans la prise de courant, et le projecteur dans le support mural (9). FIXATION DU SUPPORT MURAL Percer 2 trous écartés de 87 mm à l’horizontale. Vérifier que le support soit à côté d’une prise de courant, en faisant attention à ne pas endommager le câble d’alimentation électrique dans le mur. Fixer le support mural à l’aide de deux vis. CHARGE DU PROJECTEUR Charger le projecteur au moins 24 heures avant la première utilisation. La charge s’effectue dans le support mural (9). Le chargeur peut rester branché longtemps. Le projecteur peut également rester sur son support s’il n’est pas utilisé. La période de charge est signalée par LED (7) DURÉE D’ÉCLAIRAGE Pour la durée d’éclairage, voir le tableau (H – page 3). Instructions d’utilisation ANSMANN de la série Starlight F Starlight 200 et Starlight 400 (Starlight 300 – plus disponible) Page 2 UTILISATION Prendre le projecteur sur le support mural (9). La poignée peut pivoter de 180° et peut être repliée avec 4 crans intermédiaires. Pour abaisser ou remonter la poignée, appuyer sur le bouton de déverrouillage (5). Allumer le projecteur avec l’interrupteur (1). Les projecteurs Starlight 300 & 400 ont deux positions : 1. Position: lampe Krypton ; 2. Position: lampe Halogène. FOCUS Modifier l’intensité du rayon lumineux en tournant le focus (4). En tournant à fond vers la droite pour le Starlight 400, l’ampoule sélectionnée clignote (1). REMPLACEMENT DE L’AMPOULE Appuyer sur le joint caoutchouc du réflecteur aux deux points de serrage (10). Le réflecteur se détache du projecteur et l’ampoule peut être remplacée. ACCESSOIRES Les Starlight 300 & Starlight 400 sont livrés avec une bandoulière (T) fixée de chaque côté de la lampe. Le Starlight 400 est livré avec 2 filtres (F) (rouge & vert). Un espace est prévu pour les deux filtres dans le boîtier de l’accu. COUPURE DU RÉSEAU Le Starlight 400 gère les coupures d’électricité du réseau (N). Lorsque le projecteur est remis sur son support en position allumé, il s’allume s’il y a une coupure de courant, et sert ainsi d’éclairage de sécurité. Le projecteur s’éteint automatiquement au retour du courant et l’accu se recharge. Instructions d’utilisation ANSMANN de la série Starlight F Starlight 200 et Starlight 400 (Starlight 300 – plus disponible) Page 3 REMPLACEMENT DE L’ACCU Appuyer sur les deux points de déverrouillage en même temps (6) pour que l’accu se détache. PROTECTION DE L’ENVIRONNEMENT Les accus ne doivent pas être jetés dans les poubelles domestiques. Renvoyer les au distributeur ou à un centre de collecte autorisé. PRÉCAUTIONS Ne pas laisser le projecteur à l’humidité et ne pas exposer à des températures extrèmes. Les travaux de nettoyage et de maintenance doivent être effectués uniquement par les distributeurs autorisés. Le projecteur doit être nettoyé uniquement avec un chiffon humide. TABLEAU H Données Techniques Type L'article Ampoule * Accessoires** Battery Pack Largeur d'éclat Durée d'éclat Starlight 200 UK*** 5502046 4 W H 4,8V 800m 120 min Starlight 400 UK*** 5502056 10W H/4W KR T/N/F/B 6V 1200m 60(200)min Starlight 200 5102062 4 W H 4,8V 800m 120 min Starlight 400 5102082 10W H/4W KR T/N/F/B 6V 1200m 60(200)min *** Série pour GB Accessories** Ampoule* ** T = Courroie de civière * H = Halogène ** N = Panne de courant électronique * KR = Krypton ** F = Glace de filtre rouge et vert ** B = Se enflammer électronique Pour de plus amples renseignements, contactez ANSMANN ENERGY GMBH Industriestrasse 10, D-97959 Assamstadt Tél.: +49 (0) 6294-4204-0 Fax: +49 (0) 6294-4204-43 info@ansmann.de www.ansmann.de OSCILLOSCOPES USB HAUTE précisio n www.picotech.com Série PicoScope® 4000 Fourni avec un kit de développement logiciel (SDK) complet, y compris des exemples de programmes • Logiciel compatible avec Windows XP, Windows Vista et Windows 7• Assistance technique gratuite Mémoire tampon 32 MS Résolution 12 bits Taux d'échantillonnage 80-250 MS/s Bande passante 20-100 MHz Jusqu'à 4 voies Mode 2 voies IEPE Alimentation USB YE AR Vitesse, précision et capture détaillée IEPE 32 MS TAMPON 12-bit MODÈLE PicoScope 4424 PicoScope 4224 PicoScope 4224 IEPE Entrées Mode sonde passive Mode d'interface IEPE Nombre de voies 4 entrées BNC 2 entrées BNC 2 entrées BNC 2 entrées BNC Bande passante analogique 20 MHz (10 MHz sur une plage de ± 50 mV) CC à 20 MHz 1,6 Hz à 20 MHz (10 MHz sur une plage de ± 50 mV) Plages de tensions De ± 50 mV à ± 100 V De ± 50 mV à ± 20 V Sensibilité 10 mV/div à 20 V/div 10 mV/div à 4 V/div Résolution verticale 12 bits (jusqu’à 16 bits avec l’amélioration de la résolution) 12 bits (jusqu’à 16 bits avec l’amélioration de la résolution) Couplage d'entrée CA ou CC, sous contrôle logiciel CA ou CC, sous contrôle logiciel Impédance d'entrée 1 MΩ || 22 pF 1 MΩ || 22 pF 1 MΩ || 1 nF Protection contre les surtensions ± 200 V ± 100 V Échan till onna ge Bases de temps 100 ns/div à 200 s/div 100 ns/div à 200 s/div Taux d'échantillonnage maximum (temps réel) 1/2 voies : 80 MS/s 3/4 voies : 20 MS/s 80 MS/s 80 MS/s Taille de la mémoire tampon 32 M échantillons partagés entre les voies actives 32 M échantillons partagés entre les voies actives Décl enc hement Sources Toute voie d'entrée Type de déclencheurs voie A, voie B Front avec hystérésis, largeur d'impulsion, impulsion transitoire, perte de niveau, fenêtre Types de déclencheurs EXT Front montant, front descendant Performanc e Précision de la base de temps 50 ppm Précision CC 1 % de déviation maximale Résolution de déclenchement 1 LSB (voie A, voie B) Temps de réarmement du déclenchement 2,5 μs (base de temps la plus rapide) Env ironn ement Plage de températures Fonctionnement : 0 °C à 45 °C Pour la précision mentionnée : 20 °C à 30 °C Entreposage : –20 °C à 60 °C Plage d'humidité Fonctionnement : HR de 5 à 80 %, sans condensation Entreposage : HR de 5 à 95 %, sans condensation Connexion PC USB 2.0. Compatible avec USB 1.1 Système d'exploitation du PC Windows XP, Windows Vista ou Windows 7 Alimentation 5 V à 500 mA max. provenant du port USB Dimensions 200 mm x 140 mm x 38 mm (connecteurs inclus) Poids < 500 g Conformité Normes européennes CEM et LVD RoHS et DEEE , règles FCC Partie 15 Classe A MODÈLE PicoScope 4226 PicoScope 4227 Entrées Nombre de voies 2 entrées BNC Bande passante analogique 50 MHz 100 MHz Plages de tensions De ± 50 mV à ± 20 V Sensibilité 10 mV/div à 4 V/div Résolution verticale 12 bits Couplage d'entrée CA ou CC, sélection logicielle Impédance d'entrée 1 MΩ || 16 pF Protection contre les surtensions ± 100 V Échan till onna ge Bases de temps 100 ns/div à 200 s/div 50 ns/div à 200 s/div Taux d'échantillonnage maximum (temps réel) 1 voie en cours d'utilisation 125 MS/s 1 voie en cours d'utilisation 250 MS/s 2 voies en cours d'utilisation 125 MS/s 2 voies en cours d'utilisation 125 MS/s Fréquence d'échantillonnage maximale (ET S) 10 G S/s Taille de la mémoire tampon 32 MS partagées entre les voies actives Décl enc hement Sources Voie A, voie B, Ext Type de déclencheurs voie A, voie B Front, fenêtre, impulsion, intervalle, perte, transitoire, retardé Types de déclencheurs EXT Front montant/descendant En trée de décl enc hement EXT Connecteur BNC Bande passante 100 MHz Impédance 1 MΩ || 20 pF Plage de tension ± 20 V Plage de seuil De ± 150 mV à ± 20 V Couplage CC Protection contre les surtensions ± 100 V Géné rateur de fonc tions /géné rateur de formes d'ond es arbitraires Connecteur BNC Plage de fréquences du générateur de fonction CC à 100 kHz Formes d'onde du générateur de fonctions Sinusoïdale, carrée, triangulaire, rampante, (sin x)/x gaussienne, demi-sinusoïdale, bruit blanc, niveau CC Taille de la mémoire tampon 8 192 échantillons Fréquence de mise à jour DAC 20 MS/s Résolution du convertisseur numérique-analogique 12 bits Bande passante 100 kHz Précision CC 1 % Plage de sortie De ± 250 mV à ± 2 V Plage de décalage de sortie ± 1 V Max. sortie combinée ± 2.5 V Résistance de sortie 600 Ω Protection contre les surtensions ± 10 V Performanc e Précision de la base de temps 50 ppm Précision CC 1 % de déviation maximale Résolution de déclenchement 1 LSB (voie A, voie B) Temps de réarmement du déclenchement 1 μs (base de temps la plus rapide, déclenchement rapide) Env ironn ement Plage de températures Fonctionnement : 0 °C à 45 °C Pour la précision mentionnée : 20 °C à 30 °C Entreposage : –20 °C à 60 °C Plage d'humidité Fonctionnement : HR de 5 à 80 %, sans condensation Entreposage : HR de 5 à 95 %, sans condensation Connexion PC USB 2.0. Compatible avec USB 1.1 Système d'exploitation du PC Windows XP, Windows Vista ou Windows 7 Alimentation 5 V à 500 mA max. provenant du port USB Dimensions 200 mm x 140 mm x 38 mm (connecteurs inclus) Poids < 500 g Conformité Normes européennes CEM et LVD RoHS et DEEE , règles FCC Partie 15 Classe A Caractéristiques supplémentaires • Tests de limite de masque avec alarmes • Décodage de données série (CAN, I2C etc....) • Filtre passe-bas pour chaque voie • Voies mathématiques • Formes d'ondes de référence • Tampon de formes d'ondes avec 10 000 segments max. et navigateur visuel • Modes de persistance Couleur numérique et Intensité analogique • Mode XY Entrée déclenchement Entrée B Entrée A Générateur de fonctions et de formes d'ondes arbitraires Pico Technology, James House, Colmworth Business Park, St. Neots, Cambridgeshire, PE19 8YP, Royaume-Uni T : +44 (0) 1480 396 395 F : +44 (0) 1480 396 296 E : sales@picotech.com *Prix en vigueur au moment de la publication. Avant de passer commande, veuillez contacter Pico Technology pour connaître les tout derniers tarifs. Sauf erreur ou omission. Copyright © 2011 Pico Technology Ltd. Tous droits réservés. MM002.fr-5 CODE DE COMMANDE DESCRIPTION DE L'ARTICLE Livre sterling USD* EUR* PP493 PicoScope 4424 799 1319 967 PP492 PicoScope 4224 499 824 604 PP695 PicoScope 4224 IEPE 599 989 725 PP671 Kit PicoScope 4226 699 1154 846 PP672 Kit PicoScope 4227 899 1484 1088 Informations concernant la commande www.picotech.com Instruments tout-en-un Les oscilloscopes PC PicoScope série 4000 sont extrêmement polyvalents, et chaque modèle est équipé d'un oscilloscope et d'un analyseur de spectre. PicoScope 4224 IEPE La version IE PE à 2 voies est compatible avec les accéléromètres et microphones IE PE standard, ce qui la rend idéale pour tout type d'applications de mesure, y compris l'analyse du bruit et des vibrations. Confort et rapidité Les oscilloscopes PicoScope série 4000 sont alimentés par l'interface USB 2.0 ; nul besoin de source d'alimentation externe. Le port USB offre également un transfert de données haute vitesse vers votre PC, permettant d'obtenir un affichage haute résolution et réactif. Grâce à des plages d'échantillonnage allant de 80 à 250 MS/s, les oscilloscopes de la série 4000 sont les plus rapides de leur catégorie (avec alimentation par USB et résolution 12 bits). Grande mémoire La mémoire tampon de 32 Méchantillons est "toujours active". Comme le PicoScope série 4000 optimise simultanément la taille de la mémoire tampon et la fréquence de mise à jour de la forme d'onde, il n'y a pas de compromis à faire. Il est désormais possible de capturer chaque forme d'onde en détail sans avoir à s'en soucier. Logiciel avancé Les oscilloscopes sont fournis avec la dernière version de PicoScope pour Windows. PicoScope est simple d'utilisation et permet d'exporter des données sous divers formats graphiques, texte et binaires. Sont également inclus les pilotes Windows et des programmes d'exemple. Générateur de formes d'ondes arbitraires Les PicoScope 4226 et 4227 sont fournis avec un générateur de fonctions/formes d'ondes arbitraires. Grâce à une plage de fréquences de 100 kHz, une résolution de 12 bits et un tampon de 8 192 échantillons, ces deux oscilloscopes complètent notre gamme de la série 4000. Oscilloscope Analyseur de spectre Zoom sur la vue d'oscilloscope Générateur de formes d'ondes arbitraires Datasheets en Français FARNELL Ed.081002 DATASHEETS EN FRANCAIS BB2PROD Kit produits pour machine à graver modèle, GRAV’CI2 • 1 perchlorure de fer pour machine à mousse, jerrycan 5 litres • 1 kit de neutralisation perchlorure de fer • 1 détachant perchlorure de fer, pot 100 g • 2 cuvettes en plastique, 220 x 330 x 50 mm • 1 pince plastique pour films et circuits imprimés • 1 sachet de 100 gants jetables en polyéthylène • 1 stylo CIF pour gravure directe, noir BB4PROD Kit produits pour machine à graver modèles BB48 • 1 perchlorure de fer surractivé, jerrycan 5 litres • 1 kit de neutralisation perchlorure de fer • 1 détachant perchlorure de fer, pot de 100 g • 2 cuvettes en plastique, 220 x 330 x 50 mm • 1 pince plastique pour films et circuits imprimés • 1 sachet de 100 gants jetables en polyéthylène • 1 CIF pen for direct etching, black • 1 stylo CIF pour gravure directe, noir U800005 Kit produits pour châssis d’insolation CIP1840 & MI 10-16 • 10 films auto-positifs Posireflex 210 x 297 mm • 1 révélateur-fixateur, dose pour 1 litre • 20 epoxy présensibilisé positif 16/10e, 35 μ, 1F, 200 x 300 mm • révélateur pour plaque, dose pour 1 litre • 2 cuvettes en plastique 230 x 330 x 50 mm • 1 stylo CIF pour gravure directe, noir U800006 Kit produits pour châssis d’insolation modèles DFE 2340 & DFT 3040 • 10 films auto-positifs Posireflex 210 x 297 mm • 1 révélateur-fixateur, dose pour 1 litre • 20 epoxy présensibilisé positif 16/10e, 35 μ, 2F, 200 x 300 mm • 1 stylo CIF pour gravure directe, noir • révélateur pour plaque, dose pour 1 litre • 2 cuvettes en plastique 230 x 330 x 50 mm • 1 cutter avec 1 lame Datasheets en Français FARNELL Ed.081002 V700043 / CIF852 Température air chaud : 100 to 480°C Capteur de température : automatique Elément chauffant : oui Affichage digital de la température : oui Affichage du débit d’air : oui Masse nette du fer : 0.12 kg Débit pompe : 1 à 23 L/mn Puissance totale : 500 W Dimensions (L x l x H) : 188 x 244 x 127 mm Raccordement électrique: 230 V – 50/60Hz EP116 Contre-plaque de perçage Configuration basique Process Référence Qty Contre-plaque de perçage, par 10 perçage EP116 1 © 2007 Microchip Technology Inc. DS41211D PIC12F683 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41211D-page ii © 2007 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. DS41211D-page 1 PIC12F683 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology High-Performance RISC CPU: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes Special Microcontroller Features: • Precision Internal Oscillator: - Factory calibrated to ±1%, typical - Software selectable frequency range of 8 MHz to 125 kHz - Software tunable - Two-Speed Start-up mode - Crystal fail detect for critical applications - Clock mode switching during operation for power savings • Power-Saving Sleep mode • Wide operating voltage range (2.0V-5.5V) • Industrial and Extended temperature range • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) with software control option • Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable • Multiplexed Master Clear with pull-up/input pin • Programmable code protection • High Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM Retention: > 40 years Low-Power Features: • Standby Current: - 50 nA @ 2.0V, typical • Operating Current: - 11μA @ 32 kHz, 2.0V, typical - 220μA @ 4 MHz, 2.0V, typical • Watchdog Timer Current: - 1μA @ 2.0V, typical Peripheral Features: • 6 I/O pins with individual direction control: - High current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups - Ultra Low-Power Wake-up on GP0 • Analog Comparator module with: - One analog comparator - Programmable on-chip voltage reference (CVREF) module (% of VDD) - Comparator inputs and output externally accessible • A/D Converter: - 10-bit resolution and 4 channels • Timer0: 8-bit timer/counter with 8-bit programmable prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Timer1 Gate (count enable) - Option to use OSC1 and OSC2 in LP mode as Timer1 oscillator if INTOSC mode selected • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Capture, Compare, PWM module: - 16-bit Capture, max resolution 12.5 ns - Compare, max resolution 200 ns - 10-bit PWM, max frequency 20 kHz • In-Circuit Serial Programming™ (ICSP™) via two pins Device Program Memory Data Memory I/O 10-bit A/D (ch) Comparators Timers Flash (words) SRAM (bytes) EEPROM (bytes) 8/16-bit PIC12F683 2048 128 256 6 4 1 2/1 PIC12F683 DS41211D-page 2 © 2007 Microchip Technology Inc. 8-Pin Diagram (PDIP, SOIC) 8-Pin Diagram (DFN) 8-Pin Diagram (DFN-S) TABLE 1: 8-PIN SUMMARY I/O Pin Analog Comparators Timer CCP Interrupts Pull-ups Basic GP0 7 AN0 CIN+ — — IOC Y ICSPDAT/ULPWU GP1 6 AN1/VREF CIN- — — IOC Y ICSPCLK GP2 5 AN2 COUT T0CKI CCP1 INT/IOC Y — GP3(1) 4 — — — — IOC Y(2) MCLR/VPP GP4 3 AN3 — T1G — IOC Y OSC2/CLKOUT GP5 2 — — T1CKI — IOC Y OSC1/CLKIN — 1 — — — — — — VDD — 8 — — — — — — VSS Note 1: Input only. 2: Only when pin is configured for external MCLR. VDD GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/VPP VSS GP0/AN0/CIN+/ICSPDAT/ULPWU GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1 PIC12F683 1 2 3 4 8 7 6 5 1 2 3 4 5 6 7 8 PIC12F683 VSS GP0/AN0/CIN+/ICSPDAT/ULPWU GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1 VDD GP5/TICKI/OSC1/CLKIN GP4/AN3/TIG/OSC2/CLKOUT GP3/MCLR/VPP 1 2 3 4 5 6 7 8 PIC12F683 VSS GP0/AN0/CIN+/ICSPDAT/ULPWU GP1/AN1/CIN-/VREF/ICSPCLK GP2/AN2/T0CKI/INT/COUT/CCP1 VDD GP5/TICKI/OSC1/CLKIN GP4/AN3/TIG/OSC2/CLKOUT GP3/MCLR/VPP © 2007 Microchip Technology Inc. DS41211D-page 3 PIC12F683 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization................................................................................................................................................................... 7 3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 19 4.0 GPIO Port................................................................................................................................................................................... 31 5.0 Timer0 Module ........................................................................................................................................................................... 41 6.0 Timer1 Module with Gate Control............................................................................................................................................... 44 7.0 Timer2 Module ........................................................................................................................................................................... 49 8.0 Comparator Module.................................................................................................................................................................... 51 9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 61 10.0 Data EEPROM Memory ............................................................................................................................................................. 71 11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 75 12.0 Special Features of the CPU...................................................................................................................................................... 83 13.0 Instruction Set Summary .......................................................................................................................................................... 101 14.0 Development Support............................................................................................................................................................... 111 15.0 Electrical Specifications............................................................................................................................................................ 115 16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 137 17.0 Packaging Information.............................................................................................................................................................. 159 Appendix A: Data Sheet Revision History.......................................................................................................................................... 165 Appendix B: Migrating From Other PIC® Devices ............................................................................................................................. 165 The Microchip Web Site ..................................................................................................................................................................... 171 Customer Change Notification Service .............................................................................................................................................. 171 Customer Support.............................................................................................................................................................................. 171 Reader Response .............................................................................................................................................................................. 172 Product Identification System ............................................................................................................................................................ 173 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. PIC12F683 DS41211D-page 4 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 5 PIC12F683 1.0 DEVICE OVERVIEW The PIC12F683 is covered by this data sheet. It is available in 8-pin PDIP, SOIC and DFN-S packages. Figure 1-1 shows a block diagram of the PIC12F683 device. Table 1-1 shows the pinout description. FIGURE 1-1: PIC12F683 BLOCK DIAGRAM Flash Program Memory 13 Data Bus 8 Program 14 Bus Instruction Reg Program Counter RAM File Registers Direct Addr 7 RAM Addr 9 Addr MUX Indirect Addr FSR Reg STATUS Reg MUX ALU W Reg Instruction Decode & Control Timing OSC1/CLKIN Generation OSC2/CLKOUT 8 8 8 3 8-Level Stack 128 bytes 2k x 14 (13-bit) Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer MCLR VSS Brown-out Reset 1 Analog Comparator Timer0 Timer1 Data EEPROM 256 bytes EEDATA EEADDR GP0 GP1 GP2 GP3 GP4 GP5 AN0 AN1 AN2 AN3 CIN- CIN+ COUT T0CKI INT T1CKI Configuration Internal Oscillator VREF T1G VDD 8 Timer2 CCP Block CCP1 CVREF Analog-to-Digital Converter PIC12F683 DS41211D-page 6 © 2007 Microchip Technology Inc. TABLE 1-1: PIC12F683 PINOUT DESCRIPTION Name Function Input Type Output Type Description VDD VDD Power — Positive supply GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change T1CKI ST — Timer1 clock OSC1 XTAL — Crystal/Resonator CLKIN ST — External clock input/RC oscillator connection GP4/AN3/T1G/OSC2/CLKOUT GP4 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN3 AN — A/D Channel 3 input T1G ST — Timer1 gate OSC2 — XTAL Crystal/Resonator CLKOUT — CMOS FOSC/4 output GP3/MCLR/VPP GP3 TTL — GPIO input with interrupt-on-change MCLR ST — Master Clear with internal pull-up VPP HV — Programming voltage GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 ST CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN2 AN — A/D Channel 2 input T0CKI ST — Timer0 clock input INT ST — External Interrupt COUT — CMOS Comparator 1 output CCP1 ST CMOS Capture input/Compare output/PWM output GP1/AN1/CIN-/VREF/ICSPCLK GP1 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN1 AN — A/D Channel 1 input CIN- AN — Comparator 1 input VREF AN — External Voltage Reference for A/D ICSPCLK ST — Serial Programming Clock GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 TTL CMOS GPIO I/O with prog. pull-up and interrupt-on-change AN0 AN — A/D Channel 0 input CIN+ AN — Comparator 1 input ICSPDAT ST CMOS Serial Programming Data I/O ULPWU AN — Ultra Low-Power Wake-up input VSS VSS Power — Ground reference Legend: AN = Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal © 2007 Microchip Technology Inc. DS41211D-page 7 PIC12F683 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F683 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. Only the first 2k x 14 (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 2K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC12F683 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General Purpose Registers, implemented as static RAM. Register locations F0h-FFh in Bank 1 point to addresses 70h-7Fh in Bank 0. All other RAM is unimplemented and returns ‘0’ when read. RP0 of the STATUS register is the bank select bit. RP0 0 → Bank 0 is selected PC<12:0> 1 → Bank 1 is selected 13 0000h 0004h 0005h 07FFh 0800h 1FFFh Stack Level 1 Stack Level 8 Reset Vector Interrupt Vector On-chip Program Memory CALL, RETURN RETFIE, RETLW Stack Level 2 Wraps to 0000h-07FFh Note: The IRP and RP1 bits of the STATUS register are reserved and should always be maintained as ‘0’s. PIC12F683 DS41211D-page 8 © 2007 Microchip Technology Inc. 2.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 x 8 in the PIC12F683. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 2-1). These registers are static RAM. The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F683 Indirect addr.(1) TMR0 PCL STATUS FSR GPIO PCLATH INTCON PIR1 TMR1L TMR1H T1CON 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 7Fh BANK 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. CMCON0 VRCON General Purpose Registers 96 Bytes EEDAT EEADR EECON2(1) File Address File Address WPU IOC Indirect addr.(1) OPTION_REG PCL STATUS FSR TRISIO PCLATH INTCON PIE1 PCON 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h FFh BANK 1 ADRESH ADCON0 EECON1 ADRESL ANSEL BFh General Purpose Registers 32 Bytes Accesses 70h-7Fh F0h TMR2 T2CON CCPR1L CCPR1H CCP1CON WDTCON CMCON1 OSCCON OSCTUNE PR2 C0h EFh © 2007 Microchip Technology Inc. DS41211D-page 9 PIC12F683 TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90 01h TMR0 Timer0 Module Register xxxx xxxx 41, 90 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90 03h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 11, 90 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx 31, 90 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90 0Ch PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 15, 90 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 44, 90 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 90 11h TMR2 Timer2 Module Register 0000 0000 49, 90 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 76, 90 14h CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 76, 90 15h CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 75, 90 16h — Unimplemented — — 17h — Unimplemented — — 18h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 97, 90 19h CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 56, 90 1Ah CMCON1 — — — — — — T1GSS CMSYNC ---- --10 57, 90 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 61,90 1Fh ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 65,90 Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. PIC12F683 DS41211D-page 10 © 2007 Microchip Technology Inc. TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90 81h OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 12, 90 82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 17, 90 83h STATUS IRP(1) RP1(1) RP0 TO PD Z DC C 0001 1xxx 11, 90 84h FSR Indirect Data Memory Address Pointer xxxx xxxx 17, 90 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 90 86h — Unimplemented — — 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 17, 90 8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 13, 90 8Ch PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 14, 90 8Dh — Unimplemented — — 8Eh PCON — — ULPWUE SBOREN — — POR BOR --01 --qq 16, 90 8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 x000 20, 90 90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 24, 90 91h — Unimplemented — — 92h PR2 Timer2 Module Period Register 1111 1111 49, 90 93h — Unimplemented — — 94h — Unimplemented — — 95h WPU(3) — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 34, 90 96h IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 34, 90 97h — Unimplemented — — 98h — Unimplemented — — 99h VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 58, 90 9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 71, 90 9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 71, 90 9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 72, 91 9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 72, 91 9Eh ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx 66, 91 9Fh ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 33, 91 Legend: – = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. 2: OSTS bit of the OSCCON register reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator. 3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register. © 2007 Microchip Technology Inc. DS41211D-page 11 PIC12F683 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • Arithmetic status of the ALU • Reset status • Bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. 2: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. REGISTER 2-1: STATUS: STATUS REGISTER Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IRP: This bit is reserved and should be maintained as ‘0’ bit 6 RP1: This bit is reserved and should be maintained as ‘0’ bit 5 RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h – FFh) 0 = Bank 0 (00h – 7Fh) bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. PIC12F683 DS41211D-page 12 © 2007 Microchip Technology Inc. 2.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External GP2/INT interrupt • TMR0 • Weak pull-ups on GPIO Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’ See Section 5.1.3 “Software Programmable Prescaler”. REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.6 “Watchdog Timer (WDT)” for more information. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 BIT VALUE TIMER0 RATE WDT RATE © 2007 Microchip Technology Inc. DS41211D-page 13 PIC12F683 2.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, GPIO change and external GP2/INT pin interrupts. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GIE PEIE T0IE INTE GPIE T0IF INTF GPIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: GP2/INT External Interrupt Enable bit 1 = Enables the GP2/INT external interrupt 0 = Disables the GP2/INT external interrupt bit 3 GPIE: GPIO Change Interrupt Enable bit(1) 1 = Enables the GPIO change interrupt 0 = Disables the GPIO change interrupt bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = Timer0 register has overflowed (must be cleared in software) 0 = Timer0 register did not overflow bit 1 INTF: GP2/INT External Interrupt Flag bit 1 = The GP2/INT external interrupt occurred (must be cleared in software) 0 = The GP2/INT external interrupt did not occur bit 0 GPIF: GPIO Change Interrupt Flag bit 1 = When at least one of the GPIO <5:0> pins changed state (must be cleared in software) 0 = None of the GPIO <5:0> pins have changed state Note 1: IOC register must also be enabled. 2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit. PIC12F683 DS41211D-page 14 © 2007 Microchip Technology Inc. 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt 0 = Disables the EE write complete interrupt bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator 1 interrupt 0 = Disables the Comparator 1 interrupt bit 2 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the oscillator fail interrupt 0 = Disables the oscillator fail interrupt bit 1 TMR2IE: Timer2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt © 2007 Microchip Technology Inc. DS41211D-page 15 PIC12F683 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation has not completed or has not been started bit 6 ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started bit 5 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 4 Unimplemented: Read as ‘0’ bit 3 CMIF: Comparator Interrupt Flag bit 1 = Comparator 1 output has changed (must be cleared in software) 0 = Comparator 1 output has not changed bit 2 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed PIC12F683 DS41211D-page 16 © 2007 Microchip Technology Inc. 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR. The PCON register bits are shown in Register 2-6. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 R/W-0 R/W-1 U-0 U-0 R/W-0 R/W-x — — ULPWUE SBOREN — — POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 ULPWUE: Ultra Low-Power Wake-Up Enable bit 1 = Ultra Low-Power Wake-up enabled 0 = Ultra Low-Power Wake-up disabled bit 4 SBOREN: Software BOR Enable bit(1) 1 = BOR enabled 0 = BOR disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR. © 2007 Microchip Technology Inc. DS41211D-page 17 PIC12F683 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH). FIGURE 2-3: LOADING OF PC IN DIFFERENT SITUATIONS 2.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). 2.3.2 STACK The PIC12F683 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 2.4 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-4. A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1. EXAMPLE 2-1: INDIRECT ADDRESSING PC 12 8 7 0 5 PCLATH<4:0> PCLATH Instruction with ALU Result GOTO, CALL OPCODE<10:0> 8 PC 12 11 10 0 PCLATH<4:3> 11 PCH PCL 8 7 2 PCLATH PCH PCL PCL as Destination Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. MOVLW 0x20 ;initialize pointer MOVWF FSR ;to RAM NEXT CLRF INDF ;clear INDF register INCF FSR ;inc pointer BTFSS FSR,4 ;all done? GOTO NEXT ;no clear next CONTINUE ;yes continue PIC12F683 DS41211D-page 18 © 2007 Microchip Technology Inc. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. Data Memory Direct Addressing Indirect Addressing Bank Select Location Select RP1(1) RP0 6 From Opcode 0 IRP(1) 7 File Select Register 0 Bank Select Location Select 00 01 10 11 180h 1FFh 00h 7Fh Bank 0 Bank 1 Bank 2 Bank 3 Not Used © 2007 Microchip Technology Inc. DS41211D-page 19 PIC12F683 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 3.1 Overview The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. Clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. The Oscillator module can be configured in one of eight clock modes. 1. EC – External clock with I/O on OSC2/CLKOUT. 2. LP – 32 kHz Low-Power Crystal mode. 3. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode. 4. HS – High Gain Crystal or Ceramic Resonator mode. 5. RC – External Resistor-Capacitor (RC) with FOSC/4 output on OSC2/CLKOUT. 6. RCIO – External Resistor-Capacitor (RC) with I/O on OSC2/CLKOUT. 7. INTOSC – Internal oscillator with FOSC/4 output on OSC2 and I/O on OSC1/CLKIN. 8. INTOSCIO – Internal oscillator with I/O on OSC1/CLKIN and OSC2/CLKOUT. Clock Source modes are configured by the FOSC<2:0> bits in the Configuration Word register (CONFIG). The internal clock can be generated from two internal oscillators. The HFINTOSC is a calibrated high-frequency oscillator. The LFINTOSC is an uncalibrated low-frequency oscillator. FIGURE 3-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM (CPU and Peripherals) OSC1 OSC2 Sleep External Oscillator LP, XT, HS, RC, RCIO, EC System Clock Postscaler MUX MUX 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz 250 kHz IRCF<2:0> 111 110 101 100 011 010 001 000 31 kHz Power-up Timer (PWRT) FOSC<2:0> (Configuration Word Register) SCS<0> (OSCCON Register) Internal Oscillator (OSCCON Register) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) HFINTOSC 8 MHz LFINTOSC 31 kHz INTOSC PIC12F683 DS41211D-page 20 © 2007 Microchip Technology Inc. 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) REGISTER 3-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0 — IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits 111 = 8MHz 110 = 4 MHz (default) 101 = 2MHz 100 = 1MHz 011 = 500kHz 010 = 250kHz 001 = 125kHz 000 = 31 kHz (LFINTOSC) bit 3 OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word register 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz) 1 = HFINTOSC is stable 0 = HFINTOSC is not stable bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz) 1 = LFINTOSC is stable 0 = LFINTOSC is not stable bit 0 SCS: System Clock Select bit 1 = Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> of the Configuration Word register Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. © 2007 Microchip Technology Inc. DS41211D-page 21 PIC12F683 3.3 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the Oscillator module. The Oscillator module has two internal oscillators: the 8 MHz High-Frequency Internal Oscillator (HFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bit of the OSCCON register. See Section 3.6 “Clock Switching” for additional information. 3.4 External Clock Modes 3.4.1 OSCILLATOR START-UP TIMER (OST) If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the Oscillator module. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 3-1. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 3.7 “Two-Speed Clock Start-up Mode”). TABLE 3-1: OSCILLATOR DELAY EXAMPLES 3.4.2 EC MODE The External Clock (EC) mode allows an externally generated logic level as the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input and the OSC2 is available for general purpose I/O. Figure 3-2 shows the pin connections for EC mode. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 3-2: EXTERNAL CLOCK (EC) MODE OPERATION Switch From Switch To Frequency Oscillator Delay Sleep/POR LFINTOSC HFINTOSC 31 kHz 125 kHz to 8 MHz Oscillator Warm-Up Delay (TWARM) Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST) LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 μs (approx.) OSC1/CLKIN I/O OSC2/CLKOUT(1) Clock from Ext. System PIC® MCU Note 1: Alternate pin functions are listed in the Device Overview. PIC12F683 DS41211D-page 22 © 2007 Microchip Technology Inc. 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 3-3 and Figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. FIGURE 3-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 3-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ). C1 C2 Quartz RS(1) OSC1/CLKIN RF(2) Sleep To Internal Logic PIC® MCU Crystal OSC2/CLKOUT Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 MΩ to 10 MΩ). 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. C1 C2 Ceramic RS(1) OSC1/CLKIN RF(2) Sleep To Internal Logic PIC® MCU RP(3) Resonator OSC2/CLKOUT © 2007 Microchip Technology Inc. DS41211D-page 23 PIC12F683 3.4.4 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4. This signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. Figure 3-5 shows the external RC mode connections. FIGURE 3-5: EXTERNAL RC MODES In RCIO mode, the RC circuit is connected to OSC1. OSC2 becomes an additional general purpose I/O pin. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used. 3.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 3-2). 2. The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register. The system clock can be selected between external or internal clock sources via the System Clock Selection (SCS) bit of the OSCCON register. See Section 3.6 “Clock Switching” for more information. 3.5.1 INTOSC AND INTOSCIO MODES The INTOSC and INTOSCIO modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection or the FOSC<2:0> bits in the Configuration Word register (CONFIG). See Section 12.0 “Special Features of the CPU” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT outputs the selected internal oscillator frequency divided by 4. The CLKOUT signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT are available for general purpose I/O. 3.5.2 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 8 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 3-2). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). One of seven frequencies can be selected via software using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The HFINTOSC is enabled by selecting any frequency between 8 MHz and 125 kHz by setting the IRCF<2:0> bits of the OSCCON register ≠ 000. Then, set the System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not. OSC2/CLKOUT(1) CEXT REXT PIC® MCU OSC1/CLKIN FOSC/4 or Internal Clock VDD VSS Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V 3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V CEXT > 20 pF, 2-5V Note 1: Alternate pin functions are listed in the Device Overview. 2: Output depends upon RC or RCIO clock mode. I/O(2) PIC12F683 DS41211D-page 24 © 2007 Microchip Technology Inc. 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits 01111 = Maximum frequency 01110 = • • • 00001 = 00000 = Oscillator module is running at the calibrated frequency. 11111 = • • • 10000 = Minimum frequency © 2007 Microchip Technology Inc. DS41211D-page 25 PIC12F683 3.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<2:0> bits of the OSCCON register = 000) as the system clock source (SCS bit of the OSCCON register = 1), or when any of the following are enabled: • Two-Speed Start-up IESO bit of the Configuration Word register = 1 and IRCF<2:0> bits of the OSCCON register = 000 • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The LF Internal Oscillator (LTS) bit of the OSCCON register indicates whether the LFINTOSC is stable or not. 3.5.4 FREQUENCY SELECT BITS (IRCF) The output of the 8 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). The Internal Oscillator Frequency Select bits IRCF<2:0> of the OSCCON register select the frequency output of the internal oscillators. One of eight frequencies can be selected via software: • 8 MHz • 4 MHz (Default after Reset) • 2 MHz • 1 MHz • 500 kHz • 250 kHz • 125 kHz • 31 kHz (LFINTOSC) 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6). If this is the case, there is a delay after the IRCF<2:0> bits of the OSCCON register are modified before the frequency selection takes place. The LTS and HTS bits of the OSCCON register will reflect the current active status of the LFINTOSC and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. IRCF<2:0> bits of the OSCCON register are modified. 2. If the new clock is shut down, a clock start-up delay is started. 3. Clock switch circuitry waits for a falling edge of the current clock. 4. CLKOUT is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. CLKOUT is now connected with the new clock. LTS and HTS bits of the OSCCON register are updated as required. 6. Clock switch is complete. See Figure 3-1 for more details. If the internal oscillator speed selected is between 8 MHz and 125 kHz, there is no start-up delay before the new frequency is selected. This is because the old and new frequencies are derived from the HFINTOSC via the postscaler and multiplexer. Start-up delay specifications are located in the Electrical Specifications Chapter of this data sheet, under AC Specifications (Oscillator Module). Note: Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. PIC12F683 DS41211D-page 26 © 2007 Microchip Technology Inc. FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC IRCF <2:0> System Clock HFINTOSC LFINTOSC IRCF <2:0> System Clock HF LF(1) ≠ 0 = 0 ≠ 0 = 0 Start-up Time 2-cycle Sync Running 2-cycle Sync Running HFINTOSC LFINTOSC (FSCM and WDT disabled) Note 1: When going from LF to HF. HFINTOSC LFINTOSC (Either FSCM or WDT enabled) LFINTOSC HFINTOSC IRCF <2:0> System Clock = 0 ≠ 0 Start-up Time 2-cycle Sync Running LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled © 2007 Microchip Technology Inc. DS41211D-page 27 PIC12F683 3.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals. • When the SCS bit of the OSCCON register = 0, the system clock source is determined by configuration of the FOSC<2:0> bits in the Configuration Word register (CONFIG). • When the SCS bit of the OSCCON register = 1, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<2:0> bits of the OSCCON register. After a Reset, the SCS bit of the OSCCON register is always cleared. 3.6.2 OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT The Oscillator Start-up Time-out Status (OSTS) bit of the OSCCON register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. 3.7 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC as the clock source and go back to Sleep without waiting for the primary oscillator to become stable. When the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted. Two-Speed Start-up mode minimizes the delay in code execution by operating from the internal oscillator as the OST is counting. When the OST count reaches 1024 and the OSTS bit of the OSCCON register is set, program execution switches to the external oscillator. 3.7.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word register) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). • SCS (of the OSCCON register) = 0. • FOSC<2:0> bits in the Configuration Word register (CONFIG) configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the external clock oscillator is configured to be anything other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. 3.7.2 TWO-SPEED START-UP SEQUENCE 1. Wake-up from Power-on Reset or Sleep. 2. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register. 3. OST enabled to count 1024 clock cycles. 4. OST timed out, wait for falling edge of the internal oscillator. 5. OSTS is set. 6. System clock held low until the next falling edge of new clock (LP, XT or HS mode). 7. System clock is switched to external clock source. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bit of the OSCCON register. The user can monitor the OSTS bit of the OSCCON register to determine the current system clock source. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. PIC12F683 DS41211D-page 28 © 2007 Microchip Technology Inc. 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP 0 1 1022 1023 PC + 1 TOST HFINTOSC OSC1 OSC2 Program Counter System Clock PC - N PC © 2007 Microchip Technology Inc. DS41211D-page 29 PIC12F683 3.8 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO). FIGURE 3-8: FSCM BLOCK DIAGRAM 3.8.1 FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 3-8. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the primary clock goes low. 3.8.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR1 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 3.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register. When the SCS bit is toggled, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared. 3.8.4 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. External LFINTOSC ÷ 64 S R Q 31 kHz (~32 μs) 488 Hz (~2 ms) Clock Monitor Latch Clock Failure Detected Oscillator Clock Q Sample Clock Note: Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock switchover has successfully completed. PIC12F683 DS41211D-page 30 © 2007 Microchip Technology Inc. FIGURE 3-9: FSCM TIMING DIAGRAM TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets(1) CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000 OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. OSCFIF System Clock Output Sample Clock Failure Detected Oscillator Failure Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. (Q) Test Test Test Clock Monitor Output © 2007 Microchip Technology Inc. DS41211D-page 31 PIC12F683 4.0 GPIO PORT There are as many as six general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.1 GPIO and the TRISIO Registers GPIO is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISIO. Setting a TRISIO bit (= 1) will make the corresponding GPIO pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISIO bit (= 0) will make the corresponding GPIO pin an output (i.e., put the contents of the output latch on the selected pin). An exception is GP3, which is input only and its TRISIO bit will always read as ‘1’. Example 4-1 shows how to initialize GPIO. Reading the GPIO register reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. GP3 reads ‘0’ when MCLRE = 1. The TRISIO register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISIO register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. EXAMPLE 4-1: INITIALIZING GPIO Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. BANKSEL GPIO ; CLRF GPIO ;Init GPIO MOVLW 07h ;Set GP<2:0> to MOVWF CMCON0 ;digital I/O BANKSEL ANSEL ; CLRF ANSEL ;digital I/O MOVLW 0Ch ;Set GP<3:2> as inputs MOVWF TRISIO ;and set GP<5:4,1:0> ;as outputs REGISTER 4-1: GPIO: GENERAL PURPOSE I/O REGISTER U-0 U-0 R/W-x R/W-0 R-x R/W-0 R/W-0 R/W-0 — — GP5 GP4 GP3 GP2 GP1 GP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GP<5:0>: GPIO I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL PIC12F683 DS41211D-page 32 © 2007 Microchip Technology Inc. 4.2 Additional Pin Functions Every GPIO pin on the PIC12F683 has an interrupt-on-change option and a weak pull-up option. GP0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSEL bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSEL bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. 4.2.2 WEAK PULL-UPS Each of the GPIO pins, except GP3, has an individually configurable internal weak pull-up. Control bits WPUx enable or disable each pull-up. Refer to Register 4-4. Each weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset by the GPPU bit of the OPTION register). A weak pull-up is automatically enabled for GP3 when configured as MCLR and disabled when GP3 is an I/O. There is no software control of the MCLR pull-up. 4.2.3 INTERRUPT-ON-CHANGE Each of the GPIO pins is individually configurable as an interrupt-on-change pin. Control bits IOCx enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of GPIO. The ‘mismatch’ outputs of the last read are OR’d together to set the GPIO Change Interrupt Flag bit (GPIF) in the INTCON register (Register 2-3). This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the interrupt by: a) Any read or write of GPIO. This will end the mismatch condition, then, b) Clear the flag bit GPIF. A mismatch condition will continue to set flag bit GPIF. Reading GPIO will end the mismatch condition and allow flag bit GPIF to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After these resets, the GPIF flag will continue to be set if a mismatch is present. REGISTER 4-2: TRISIO GPIO TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1 — — TRISIO5(2,3) TRISIO4(2) TRISIO3(1) TRISIO2 TRISIO1 TRISIO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5:4 TRISIO<5:4>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output bit 3 TRISIO<3>: GPIO Tri-State Control bit Input only bit 2:0 TRISIO<2:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated) 0 = GPIO pin configured as an output Note 1: TRISIO<3> always reads ‘1’. 2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP OSC modes. 3: TRISIO<5> always reads ‘1’ in RC and RCIO and EC modes. Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. © 2007 Microchip Technology Inc. DS41211D-page 33 PIC12F683 REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 bit 3-0 ANS<3:0>: Analog Select bits Analog select between analog or digital function on pins AN<3:0>, respectively. 1 = Analog input. Pin is assigned as analog input(1). 0 = Digital I/O. Pin is assigned to port or special function. Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change, if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. PIC12F683 DS41211D-page 34 © 2007 Microchip Technology Inc. REGISTER 4-4: WPU: WEAK PULL-UP REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPU5 WPU4 — WPU2 WPU1 WPU0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPU<2:0>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: Global GPPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0). 3: The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word. 4: WPU<5:4> always reads ‘1’ in XT, HS and LP OSC modes. REGISTER 4-5: IOC: INTERRUPT-ON-CHANGE GPIO REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOC<5:0>: Interrupt-on-change GPIO Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOC<5:4> always reads ‘0’ in XT, HS and LP OSC modes. © 2007 Microchip Technology Inc. DS41211D-page 35 PIC12F683 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on GP0 allows a slow falling voltage to generate an interrupt- on-change on GP0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on GP0. To use this feature, the GP0 pin is configured to output ‘1’ to charge the capacitor, interrupt-on-change for GP0 is enabled and GP0 is configured as an input. The ULPWUE bit is set to begin the discharge and a SLEEP instruction is performed. When the voltage on GP0 drops below VIL, an interrupt will be generated which will cause the device to wake-up. Depending on the state of the GIE bit of the INTCON register, the device will either jump to the interrupt vector (0004h) or execute the next instruction when the interrupt event occurs. See Section 4.2.3 “Interrupt-on-Change” and Section 12.4.3 “GPIO Interrupt” for more information. This feature provides a low-power technique for periodically waking up the device from Sleep. The time-out is dependent on the discharge time of the RC circuit on GP0. See Example 4-2 for initializing the Ultra Low-Power Wake-up module. The series resistor provides overcurrent protection for the GP0 pin and can allow for software calibration of the time-out (see Figure 4-1). A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. EXAMPLE 4-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION Note: For more information, refer to the Application Note AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879). BANKSEL CMCON0 ; MOVLW H’7’ ;Turn off MOVWF CMCON0 ;comparators BANKSEL ANSEL ; BCF ANSEL,0 ;RA0 to digital I/O BCF TRISA,0 ;Output high to BANKSEL PORTA ; BSF PORTA,0 ;charge capacitor CALL CapDelay ; BANKSEL PCON ; BSF PCON,ULPWUE ;Enable ULP Wake-up BSF IOCA,0 ;Select RA0 IOC BSF TRISA,0 ;RA0 to input MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON ; and clear flag SLEEP ;Wait for IOC NOP ; PIC12F683 DS41211D-page 36 © 2007 Microchip Technology Inc. 4.2.5 PIN DESCRIPTIONS AND DIAGRAMS Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the ADC, refer to the appropriate section in this data sheet. 4.2.5.1 GP0/AN0/CIN+/ICSPDAT/ULPWU Figure 4-1 shows the diagram for this pin. The GP0 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • an analog input to the comparator • In-Circuit Serial Programming™ data • an analog input to the Ultra Low-Power Wake-up FIGURE 4-1: BLOCK DIAGRAM OF GP0 I/O pin VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak RD GPIO RD WR WR RD WR IOC RD IOC Interrupt-on- To Comparator Analog Input Mode(1) GPPU Analog Input Mode(1) Change Q3 WR RD 0 1 IULP WPU Data Bus WPU GPIO TRISIO TRISIO GPIO Note 1: Comparator mode and ANSEL determines Analog Input mode. VT ULPWUE -+ VSS To A/D Converter © 2007 Microchip Technology Inc. DS41211D-page 37 PIC12F683 4.2.5.2 GP1/AN1/CIN-/VREF/ICSPCLK Figure 4-2 shows the diagram for this pin. The GP1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a analog input to the comparator • a voltage reference input for the ADC • In-Circuit Serial Programming clock FIGURE 4-2: BLOCK DIAGRAM OF GP1 4.2.5.3 GP2/AN2/T0CKI/INT/COUT/CCP1 Figure 4-3 shows the diagram for this pin. The GP2 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • the clock input for Timer0 • an external edge triggered interrupt • a digital output from the Comparator • a digital input/output for the CCP (refer to Section 11.0 “Capture/Compare/PWM (CCP) Module”). FIGURE 4-3: BLOCK DIAGRAM OF GP2 I/O pin VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak Data WR WPU RD WPU RD GPIO RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC Interrupt-on- To Comparator Analog Input Mode(1) GPPU Analog Input Mode(1) change Bus Note 1: Comparator mode and ANSEL determines Analog Input mode. Q3 To A/D Converter I/O pin VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak Analog Input Mode Data WR WPU RD WPU RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC To A/D Converter 0 COUT 1 COUT Enable To INT To Timer0 Analog Input Mode GPPU RD GPIO Analog Input Mode Interrupt-onchange Bus Q3 Note 1: Comparator mode and ANSEL determines Analog Input mode. PIC12F683 DS41211D-page 38 © 2007 Microchip Technology Inc. 4.2.5.4 GP3/MCLR/VPP Figure 4-4 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up FIGURE 4-4: BLOCK DIAGRAM OF GP3 4.2.5.5 GP4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The GP4 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • a Timer1 gate input • a crystal/resonator connection • a clock output FIGURE 4-5: BLOCK DIAGRAM OF GP4 Input VSS D CK Q Q D EN Q Data RD GPIO RD WR IOC RD Reset MCLRE RD VSS D EN Q MCLRE VDD MCLRE Weak Interrupt-onchange pin GPIO IOC Bus TRISIO Q3 I/O pin VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak Analog Input Mode Data WR WPU RD WPU RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC FOSC/4 To A/D Converter Oscillator Circuit OSC1 CLKOUT 0 1 CLKOUT Enable Enable Analog Input Mode GPPU RD GPIO To T1G INTOSC/ RC/EC(2) CLK(1) Modes CLKOUT Enable Note 1: CLK modes are XT, HS, LP, optional LP oscillator and CLKOUT Enable. 2: With CLKOUT option. Interrupt-onchange Bus Q3 © 2007 Microchip Technology Inc. DS41211D-page 39 PIC12F683 4.2.5.6 GP5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin. The GP5 pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 clock input • a crystal/resonator connection • a clock input FIGURE 4-6: BLOCK DIAGRAM OF GP5 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO I/O pin VDD VSS D CK Q Q D CK Q Q D CK Q Q D CK Q Q VDD D EN Q D EN Q Weak Data WR WPU RD WPU RD GPIO WR GPIO WR TRISIO RD TRISIO WR IOC RD IOC To Timer1 or CLKGEN INTOSC Mode RD GPIO INTOSC Mode GPPU OSC2 (1) Note 1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. TMR1LPEN(1) Interrupt-onchange Oscillator Circuit Bus Q3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --x0 x000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 WPU — — WPU5 WPU4 — WPU2 WPU1 WPU0 --11 -111 --11 -111 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO. PIC12F683 DS41211D-page 40 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 41 PIC12F683 5.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • 8-bit timer/counter register (TMR0) • 8-bit prescaler (shared with Watchdog Timer) • Programmable internal or external clock source • Programmable external clock edge selection • Interrupt on overflow Figure 5-1 is a block diagram of the Timer0 module. 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 5.1.1 8-BIT TIMER MODE When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to ‘0’. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. 5.1.2 8-BIT COUNTER MODE When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. T0CKI T0SE pin TMR0 Watchdog Timer WDT Time-out PS<2:0> WDTE Data Bus Set Flag bit T0IF on Overflow T0CS Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. 0 1 0 1 0 1 8 8 8-bit Prescaler 0 1 FOSC/4 PSA PSA PSA 16-bit Prescaler 16 WDTPS<3:0> 31 kHz INTOSC SWDTEN Sync 2 Tcy PIC12F683 DS41211D-page 42 © 2007 Microchip Technology Inc. 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. 5.1.3.1 Switching Prescaler Between Timer0 and WDT Modules As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 5-1, must be executed. EXAMPLE 5-1: CHANGING PRESCALER (TIMER0 → WDT) When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 5-2). EXAMPLE 5-2: CHANGING PRESCALER (WDT → TIMER0) 5.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. 5.1.5 USING TIMER0 WITH AN EXTERNAL CLOCK When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 15.0 “Electrical Specifications”. BANKSEL TMR0 ; CLRWDT ;Clear WDT CLRF TMR0 ;Clear TMR0 and ;prescaler BANKSEL OPTION_REG ; BSF OPTION_REG,PSA ;Select WDT CLRWDT ; ; MOVLW b’11111000’ ;Mask prescaler ANDWF OPTION_REG,W ;bits IORLW b’00000101’ ;Set WDT prescaler MOVWF OPTION_REG ;to 1:32 Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. CLRWDT ;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b’11110000’ ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b’00000011’ ;Set prescale to 1:16 MOVWF OPTION_REG ; © 2007 Microchip Technology Inc. DS41211D-page 43 PIC12F683 TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GPPU: GPIO Pull-up Enable bit 1 = GPIO pull-ups are disabled 0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.6 “Watchdog Timer (WDT)” for more information. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 BIT VALUE TIMER0 RATE WDT RATE PIC12F683 DS41211D-page 44 © 2007 Microchip Technology Inc. 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • Interrupt on overflow • Wake-up on overflow (external clock, Asynchronous mode only) • Special Event Trigger (with CCP) • Comparator output synchronization to Timer1 clock Figure 6-1 is a block diagram of the Timer1 module. 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter. 6.2 Clock Source Selection The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally. FIGURE 6-1: TIMER1 BLOCK DIAGRAM Clock Source TMR1CS FOSC/4 0 T1CKI pin 1 TMR1H TMR1L Oscillator T1SYNC T1CKPS<1:0> Prescaler 1, 2, 4, 8 Synchronize(3) det 1 0 0 1 Synchronized clock input 2 Set flag bit TMR1IF on Overflow TMR1(2) TMR1GE TMR1ON T1OSCEN 1 COUT 0 T1GSS T1GINV To Comparator Module Timer1 Clock TMR1CS OSC2/T1G OSC1/T1CKI Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. (1) EN INTOSC Without CLKOUT FOSC/4 Internal Clock © 2007 Microchip Technology Inc. DS41211D-page 45 PIC12F683 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. If an external clock oscillator is needed (and the microcontroller is using the INTOSC without CLKOUT), Timer1 can use the LP oscillator as a clock source. 6.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 6.4 Timer1 Oscillator A low-power 32.768 kHz crystal oscillator is built-in between pins OSC1 (input) and OSC2 (amplifier output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISIO<5:4> bits are set when the Timer1 oscillator is enabled. GP5 and GP4 bits read as ‘0’ and TRISIO5 and TRISIO4 bits read as ‘1’. 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 6.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). 6.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TTMR1L register pair. 6.6 Timer1 Gate Timer1 gate source is software configurable to be the T1G pin or the output of the Comparator. This allows the device to directly time external events using T1G or analog events using Comparator 2. See the CMCON1 register (Register 8-2) for selecting the Timer1 gate source. This feature can simplify the software for a Delta-Sigma A/D converter and many other applications. For more information on Delta-Sigma A/D converters, see the Microchip web site (www.microchip.com). Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator 2 output. This configures Timer1 to measure either the active-high or active-low time between events. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce a single spurious increment. Note: TMR1GE bit of the T1CON register must be set to use either T1G or COUT as the Timer1 gate source. See Register 8-2 for more information on selecting the Timer1 gate source. PIC12F683 DS41211D-page 46 © 2007 Microchip Technology Inc. 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • PEIE bit of the INTCON register • GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. 6.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • TMR1ON bit of the T1CON register must be set • TMR1IE bit of the PIE1 register must be set • PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h). 6.9 CCP Special Event Trigger If a CCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section on CCP. 6.10 Comparator Synchronization The same clock used to increment Timer1 can also be used to synchronize the comparator output. This feature is enabled in the Comparator module. When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see Section 8.0 “Comparator Module”. FIGURE 6-2: TIMER1 INCREMENTING EDGE Note: The TMR1H:TTMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments. 2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2007 Microchip Technology Inc. DS41211D-page 47 PIC12F683 6.11 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module. REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T1GINV(1) TMR1GE(2) T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 T1GINV: Timer1 Gate Invert bit(1) 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 6 TMR1GE: Timer1 Gate Enable bit(2) If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 is on if Timer1 gate is not active 0 = Timer1 is on bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value bit 3 T1OSCEN: LP Oscillator Enable Control bit If INTOSC without CLKOUT oscillator is active: 1 = LP oscillator is enabled for Timer1 clock 0 = LP oscillator is off Else: This bit is ignored. LP oscillator is disabled. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register, as a Timer1 gate source. PIC12F683 DS41211D-page 48 © 2007 Microchip Technology Inc. TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CONFIG(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: See Configuration Word register (Register 12-1) for operation of all register bits. © 2007 Microchip Technology Inc. DS41211D-page 49 PIC12F683 7.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • 8-bit timer register (TMR2) • 8-bit period register (PR2) • Interrupt on TMR2 match with PR2 • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) See Figure 7-1 for a block diagram of Timer2. 7.1 Timer2 Operation The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: • TMR2 is reset to 00h on the next increment cycle. • The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR1 register. The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: • A write to TMR2 occurs. • A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). FIGURE 7-1: TIMER2 BLOCK DIAGRAM Note: TMR2 is not cleared when T2CON is written. Comparator TMR2 Sets Flag TMR2 Output Reset Postscaler Prescaler PR2 2 FOSC/4 1:1 to 1:16 1:1, 1:4, 1:16 EQ 4 bit TMR2IF TOUTPS<3:0> T2CKPS<1:0> PIC12F683 DS41211D-page 50 © 2007 Microchip Technology Inc. TABLE 7-1: SUMMARY OF ASSOCIATED TIMER2 REGISTERS REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module. © 2007 Microchip Technology Inc. DS41211D-page 51 PIC12F683 8.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution. The analog comparator module includes the following features: • Multiple comparator configurations • Comparator output is available internally/externally • Programmable output polarity • Interrupt-on-change • Wake-up from Sleep • Timer1 gate (count enable) • Output synchronization to Timer1 clock input • Programmable voltage reference 8.1 Comparator Overview The comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. FIGURE 8-1: SINGLE COMPARATOR FIGURE 8-2: COMPARATOR OUTPUT BLOCK DIAGRAM – VIN+ + VINOutput Output VIN+ VINNote: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. CMSYNC D Q EN To COUT pin RD CMCON0 Set CMIF bit MULTIPLEX Port Pins Q3*RD CMCON0 Reset To Data Bus CINV Timer1 clock source(1) 0 1 To Timer1 Gate Note 1: Comparator output is latched on falling edge of Timer1 clock source. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. D Q D Q EN CL Q1 PIC12F683 DS41211D-page 52 © 2007 Microchip Technology Inc. 8.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. FIGURE 8-3: ANALOG INPUT MODEL Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. VA Rs < 10K CPIN 5 pF VDD VT ≈ 0.6V VT ≈ 0.6V RIC ILEAKAGE ±500 nA Vss AIN Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance RS = Source Impedance VA = Analog Voltage VT = Threshold Voltage To ADC Input © 2007 Microchip Technology Inc. DS41211D-page 53 PIC12F683 8.3 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 8-4. • Analog function (A): digital input buffer is disabled • Digital function (D): comparator digital output, overrides port function • Normal port function (I/O): independent of comparator The port pins denoted as “A” will read as a ‘0’ regardless of the state of the I/O pin or the I/O control TRIS bit. Pins used as analog inputs should also have the corresponding TRIS bit set to ‘1’ to disable the digital output driver. Pins denoted as “D” should have the corresponding TRIS bit set to ‘0’ to enable the digital output driver. FIGURE 8-4: COMPARATOR I/O OPERATING MODES Note: Comparator interrupts should be disabled during a Comparator mode change to prevent unintended interrupts. Comparator Reset (POR Default Value – low power) Comparator w/o Output and with Internal Reference CM<2:0> = 000 CM<2:0> = 100 Comparator with Output Multiplexed Input with Internal Reference and Output CM<2:0> = 001 CM<2:0> = 101 Comparator without Output Multiplexed Input with Internal Reference CM<2:0> = 010 CM<2:0> = 110 Comparator with Output and Internal Reference Comparator Off (Lowest power) CM<2:0> = 011 CM<2:0> = 111 Legend: A = Analog Input, ports always reads ‘0’ CIS = Comparator Input Switch (CMCON0<3>) I/O = Normal port I/O D = Comparator Digital Output Note 1: Reads as ‘0’, unless CINV = 1. CINCIN+ Off(1) A A COUT (pin) I/O CINCIN+ COUT A I/O COUT (pin) I/O From CVREF Module CINCIN+ COUT A A COUT (pin) D CINCIN+ COUT A A COUT (pin) D From CVREF Module CIS = 0 CIS = 1 CINCIN+ COUT A A COUT (pin) I/O CINCIN+ COUT A A COUT (pin) I/O From CVREF Module CIS = 0 CIS = 1 CINCIN+ COUT A I/O COUT (pin) D From CVREF Module CINCIN+ Off(1) I/O I/O COUT (pin) I/O PIC12F683 DS41211D-page 54 © 2007 Microchip Technology Inc. 8.4 Comparator Control The CMCON0 register (Register 8-1) provides access to the following comparator features: • Mode selection • Output state • Output polarity • Input switch 8.4.1 COMPARATOR OUTPUT STATE The Comparator state can always be read internally via the COUT bit of the CMCON0 register. The comparator state may also be directed to the COUT pin in the following modes: • CM<2:0> = 001 • CM<2:0> = 011 • CM<2:0> = 101 When one of the above modes is selected, the associated TRIS bit of the COUT pin must be cleared. 8.4.2 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CINV bit of the CMCON0 register. Clearing CINV results in a non-inverted output. A complete table showing the output state versus input conditions and the polarity bit is shown in Table 8-1. TABLE 8-1: OUTPUT STATE VS. INPUT CONDITIONS 8.4.3 COMPARATOR INPUT SWITCH The inverting input of the comparator may be switched between two analog pins in the following modes: • CM<2:0> = 101 • CM<2:0> = 110 In the above modes, both pins remain in analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch. 8.5 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 15.0 “Electrical Specifications” for more details. Input Conditions CINV COUT VIN- > VIN+ 0 0 VIN- < VIN+ 0 1 VIN- > VIN+ 1 1 VIN- < VIN+ 1 0 Note: COUT refers to both the register bit and output pin. © 2007 Microchip Technology Inc. DS41211D-page 55 PIC12F683 8.6 Comparator Interrupt Operation The comparator interrupt flag is set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusive-or gate (see Figure 8.2). One latch is updated with the comparator output level when the CMCON0 register is read. This latch retains the value until the next read of the CMCON0 register or the occurrence of a Reset. The other latch of the mismatch circuit is updated on every Q1 system clock. A mismatch condition will occur when a comparator output change is clocked through the second latch on the Q1 clock cycle. The mismatch condition will persist, holding the CMIF bit of the PIR1 register true, until either the CMCON0 register is read or the comparator output returns to the previous state. Software will need to maintain information about the status of the comparator output to determine the actual change that has occurred. The CMIF bit of the PIR1 register, is the comparator interrupt flag. This bit must be reset in software by clearing it to ‘0’. Since it is also possible to write a ‘1’ to this register, a simulated interrupt may be initiated. The CMIE bit of the PIE1 register and the PEIE and GIE bits of the INTCON register must all be set to enable comparator interrupts. If any of these bits are cleared, the interrupt is not enabled, although the CMIF bit of the PIR1 register will still be set if an interrupt condition occurs. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of CMCON0. This will end the mismatch condition. b) Clear the CMIF interrupt flag. A persistent mismatch condition will preclude clearing the CMIF interrupt flag. Reading CMCON0 will end the mismatch condition and allow the CMIF bit to be cleared. FIGURE 8-5: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ FIGURE 8-6: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ Note: A write operation to the CMCON0 register will also clear the mismatch condition because all writes include a read operation at the beginning of the write cycle. Note: If a change in the CMCON0 register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF interrupt flag may not get set. Note 1: If a change in the CMCON0 register (COUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF of the PIR1 register interrupt flag may not get set. 2: When either comparator is first enabled, bias circuitry in the Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. Q1 Q3 CIN+ COUT Set CMIF (level) CMIF TRT reset by software Q1 Q3 CIN+ COUT Set CMIF (level) CMIF TRT cleared by CMCON0 read reset by software PIC12F683 DS41211D-page 56 © 2007 Microchip Technology Inc. 8.7 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by selecting mode CM<2:0> = 000 or CM<2:0> = 111 of the CMCON0 register. A change to the comparator output can wake-up the device from Sleep. To enable the comparator to wake the device from Sleep, the CMIE bit of the PIE1 register and the PEIE bit of the INTCON register must be set. The instruction following the Sleep instruction always executes following a wake from Sleep. If the GIE bit of the INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.8 Effects of a Reset A device Reset forces the CMCON0 and CMCON1 registers to their Reset states. This forces the Comparator module to be in the Comparator Reset mode (CM<2:0> = 000). Thus, all comparator inputs are analog inputs with the comparator disabled to consume the smallest current possible. REGISTER 8-1: CMCON0: COMPARATOR CONFIGURATION REGISTER U-0 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — COUT — CINV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 COUT: Comparator Output bit When CINV = 0: 1 = VIN+ > VIN- 0 = VIN+ < VINWhen CINV = 1: 1 = VIN+ < VIN- 0 = VIN+ > VINbit 5 Unimplemented: Read as ‘0’ bit 4 CINV: Comparator Output Inversion bit 1 = Output inverted 0 = Output not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110 or 101: 1 = CIN+ connects to VIN- 0 = CIN- connects to VINWhen CM<2:0> = 0xx or 100 or 111: CIS has no effect. bit 2-0 CM<2:0>: Comparator Mode bits (See Figure 8-5) 000 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off 001 = CIN pins are configured as analog, COUT pin configured as Comparator output 010 = CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally 011 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as Comparator output, CVREF is non-inverting input 100 = CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output available internally, CVREF is non-inverting input 101 = CIN pins are configured as analog and multiplexed, COUT pin is configured as Comparator output, CVREF is non-inverting input 110 = CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O, Comparator output available internally, CVREF is non-inverting input 111 = CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off. © 2007 Microchip Technology Inc. DS41211D-page 57 PIC12F683 8.9 Comparator Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details. It is recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the comparator is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. 8.10 Synchronizing Comparator Output to Timer1 The comparator output can be synchronized with Timer1 by setting the CMSYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 8- 2) and the Timer1 Block Diagram (Figure 6-1) for more information. REGISTER 8-2: CMCON1: COMPARATOR CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 — — — — — — T1GSS CMSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer 1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Timer 1 Gate Source is comparator output bit 0 CMSYNC: Comparator Output Synchronization bit(2) 1 = Output is synchronized with falling edge of Timer1 clock 0 = Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-2. PIC12F683 DS41211D-page 58 © 2007 Microchip Technology Inc. 8.11 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: • Independent from Comparator operation • Two 16-level voltage ranges • Output clamped to VSS • Ratiometric with VDD The VRCON register (Register 8-3) controls the Voltage Reference module shown in Figure 8-7. 8.11.1 INDEPENDENT OPERATION The comparator voltage reference is independent of the comparator configuration. Setting the VREN bit of the VRCON register will enable the voltage reference. 8.11.2 OUTPUT VOLTAGE SELECTION The CVREF voltage reference has 2 ranges with 16 voltage levels in each range. Range selection is controlled by the VRR bit of the VRCON register. The 16 levels are set with the VR<3:0> bits of the VRCON register. The CVREF output voltage is determined by the following equations: EQUATION 8-1: CVREF OUTPUT VOLTAGE The full range of VSS to VDD cannot be realized due to the construction of the module. See Figure 8-1. 8.11.3 OUTPUT CLAMPED TO VSS The CVREF output voltage can be set to Vss with no power consumption by configuring VRCON as follows: • VREN=0 • VRR=1 • VR<3:0>=0000 This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current. 8.11.4 OUTPUT RATIOMETRIC TO VDD The comparator voltage reference is VDD derived and therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the Comparator Voltage Reference can be found in Section 15.0 “Electrical Specifications”. VRR = 1 (low range): VRR = 0 (high range): CVREF = (VDD/4) + CVREF = (VR<3:0>/24) × VDD (VR<3:0> × VDD/32) REGISTER 8-3: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS. bit 6 Unimplemented: Read as ‘0’ bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 Unimplemented: Read as ‘0’ bit 3-0 VR<3:0>: CVREF Value Selection 0 ≤ VR<3:0> ≤ 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD © 2007 Microchip Technology Inc. DS41211D-page 59 PIC12F683 FIGURE 8-7: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 -0-0 0000 CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 -0-0 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for comparator. 8R VRR VR<3:0>(1) 16-1 Analog 8R R R R R CVREF to 16 Stages Comparator Input VREN VDD MUX VR<3:0> = 0000 VREN VRR 0 1 2 14 15 Note 1: Care should be taken to ensure VREF remains within the comparator Common mode input range. See Section 15.0 “Electrical Specifications” for more detail. PIC12F683 DS41211D-page 60 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 61 PIC12F683 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESL and ADRESH). The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 9-1 shows the block diagram of the ADC. FIGURE 9-1: ADC BLOCK DIAGRAM 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • GPIO configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 GPIO CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. See the corresponding GPIO section for more information. 9.1.2 CHANNEL SELECTION The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 9.2 “ADC Operation” for more information. GP0/AN0 A/D GP1/AN1/VREF GP2/AN2 VDD VREF ADON GO/DONE VCFG = 1 VCFG = 0 CHS ADRESH ADRESL 10 10 ADFM GP4/AN3 0 = Left Justify 1 = Right Justify Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. PIC12F683 DS41211D-page 62 © 2007 Microchip Technology Inc. 9.1.3 ADC VOLTAGE REFERENCE The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source. The negative voltage reference is always connected to the ground reference. 9.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ANSEL register. There are seven possible clock options: • FOSC/2 • FOSC/4 • FOSC/8 • FOSC/16 • FOSC/32 • FOSC/64 • FRC (dedicated internal oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods as shown in Figure 9-2. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 15.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 250 ns(2) 500 ns(2) 2.0 μs FOSC/4 100 200 ns(2) 500 ns(2) 1.0 μs(2) 4.0 μs FOSC/8 001 400 ns(2) 1.0 μs(2) 2.0 μs 8.0 μs(3) FOSC/16 101 800 ns(2) 2.0 μs 4.0 μs 16.0 μs(3) FOSC/32 010 1.6 μs 4.0 μs 8.0 μs(3) 32.0 μs(3) FOSC/64 110 3.2 μs 8.0 μs(3) 16.0 μs(3) 64.0 μs(3) FRC x11 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) 2-6 μs(1,4) Legend: Shaded cells are outside of recommended range. Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 Set GO/DONE bit Holding Capacitor is Disconnected from Analog Input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 TAD10 TAD11 b1 b0 TCY to TAD Conversion Starts ADRESH and ADRESL registers are loaded, GO bit is cleared, ADIF bit is set, Holding capacitor is connected to analog input © 2007 Microchip Technology Inc. DS41211D-page 63 PIC12F683 9.1.5 INTERRUPTS The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the interrupt service routine. Please see Section 12.4 “Interrupts” for more information. 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-3 shows the two output formats. FIGURE 9-3: 10-BIT A/D CONVERSION RESULT FORMAT 9.2 ADC Operation 9.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. 9.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 9.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRESH:ADRESL register pair will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. ADRESH ADRESL (ADFM = 0) MSB LSB bit 7 bit 0 bit 7 bit 0 10-bit A/D Result Unimplemented: Read as ‘0’ (ADFM = 1) MSB LSB bit 7 bit 0 bit 7 bit 0 Unimplemented: Read as ‘0’ 10-bit A/D Result Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “A/D Conversion Procedure”. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. PIC12F683 DS41211D-page 64 © 2007 Microchip Technology Inc. 9.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 9.2.5 SPECIAL EVENT TRIGGER The CCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. See Section 11.0 “Capture/Compare/PWM (CCP) Module” for more information. 9.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure GPIO Port: • Disable pin output driver (See TRIS register) • Configure pin as analog 2. Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Select result format • Turn on ADC module 3. Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) 4. Wait the required acquisition time(2). 5. Start conversion by setting the GO/DONE bit. 6. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) 7. Read ADC Result 8. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 9-1: A/D CONVERSION 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 9.3 “A/D Acquisition Requirements”. ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and GP0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL TRISIO ; BSF TRISIO,0 ;Set GP0 to input BANKSEL ANSEL ; MOVLW B’01110001’ ;ADC Frc clock, IORWF ANSEL ; and GP0 as analog BANKSEL ADCON0 ; MOVLW B’10000001’ ;Right justify, MOVWF ADCON0 ;Vdd Vref, AN0, On CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;Store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space © 2007 Microchip Technology Inc. DS41211D-page 65 PIC12F683 REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CHS<1:0>: Analog Channel Select bits 00 = AN0 01 = AN1 10 = AN2 11 = AN3 bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current PIC12F683 DS41211D-page 66 © 2007 Microchip Technology Inc. REGISTER 9-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES1 ADRES0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. REGISTER 9-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result REGISTER 9-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result © 2007 Microchip Technology Inc. DS41211D-page 67 PIC12F683 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4. The maximum recommended impedance for analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. EQUATION 9-1: ACQUISITION TIME EXAMPLE TACQ Amplifier Settling Time Hold Capacitor Charging = + Time + Temperature Coefficient = TAMP + TC + TCOFF = 2μs + TC + [(Temperature - 25°C)(0.05μs/°C)] TC = –CHOLD(RIC + RSS + RS) ln(1/2047) = –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.0004885) = 1.37μs TACQ = 2μS + 1.37μS + [(50°C- 25°C)(0.05μS/°C)] = 4.67μS VAPPLIED 1 e –Tc RC --------- – ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ VAPPLIED 1 1 2047 ⎝ – -----------⎠ = ⎛ ⎞ VAPPLIED 1 1 2047 ⎝ – -----------⎠ ⎛ ⎞ = VCHOLD VAPPLIED 1 e –TC RC --------- – ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ = VCHOLD ;[1] VCHOLD charged to within 1/2 lsb ;[2] VCHOLD charge response to VAPPLIED ;combining [1] and [2] The value for TC can be approximated with the following equations: Solving for TC: Therefore: Assumptions: Temperature = 50°C and external impedance of 10kΩ 5.0V VDD Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. PIC12F683 DS41211D-page 68 © 2007 Microchip Technology Inc. FIGURE 9-4: ANALOG INPUT MODEL FIGURE 9-5: ADC TRANSFER FUNCTION VA CPIN Rs ANx 5 pF VDD VT = 0.6V VT = 0.6V I LEAKAGE RIC ≤ 1k Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF- 6V Sampling Switch 5V 4V 3V 2V 5 6 7 8 91011 (kΩ) VDD ± 500 nA Legend: CPIN VT I LEAKAGE RIC SS CHOLD = Input Capacitance = Threshold Voltage = Leakage current at the pin due to = Interconnect Resistance = Sampling Switch = Sample/Hold Capacitance various junctions RSS 3FFh 3FEh ADC Output Code 3FDh 3FCh 004h 003h 002h 001h 000h Full-Scale 3FBh 1 LSB ideal VSS/VREF- Zero-Scale Transition VDD/VREF+ Transition 1 LSB ideal Full-Scale Range Analog Input Voltage © 2007 Microchip Technology Inc. DS41211D-page 69 PIC12F683 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 ADFM VCFG — — CHS1 CHS0 GO/DONE ADON 00-- 0000 0000 0000 ANSEL — ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1 ANS0 -000 1111 -000 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. PIC12F683 DS41211D-page 70 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 71 PIC12F683 10.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are four SFRs used to read and write this memory: • EECON1 • EECON2 (not a physically implemented register) • EEDAT • EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of data EEPROM with an address range from 0h to FFh. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to AC Specifications in Section 15.0 “Electrical Specifications” for exact limits. When the data memory is code-protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access the data EEPROM data and will read zeroes. REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEDATn: Byte Value to Write To or Read From Data EEPROM bits REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-0 EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits PIC12F683 DS41211D-page 72 © 2007 Microchip Technology Inc. 10.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are nonimplemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit, clear it and rewrite the location. The data and address will be cleared. Therefore, the EEDAT and EEADR registers will need to be re-initialized. Interrupt flag, EEIF bit of the PIR1 register, is set when write is complete. This bit must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the data EEPROM write sequence. Note: The EECON1, EEDAT and EEADR registers should not be modified during a data EEPROM write (WR bit = 1). REGISTER 10-3: EECON1: EEPROM CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 — — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during normal operation or BOR Reset) 0 = The write operation completed bit 2 WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the data EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be set, not cleared, in software.) 0 = Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set, not cleared, in software.) 0 = Does not initiate an EEPROM read © 2007 Microchip Technology Inc. DS41211D-page 73 PIC12F683 10.2 Reading the EEPROM Data Memory To read a data memory location, the user must write the address to the EEADR register and then set control bit RD of the EECON1 register, as shown in Example 10-1. The data is available, at the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation). EXAMPLE 10-1: DATA EEPROM READ 10.3 Writing to the EEPROM Data Memory To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDAT register. Then the user must follow a specific sequence to initiate the write for each byte, as shown in Example 10-2. EXAMPLE 10-2: DATA EEPROM WRITE The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment. A cycle count is executed during the required sequence. Any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the EEPROM. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. The EEIF bit of the PIR1 register must be cleared by software. 10.4 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 10-3) to the desired value to be written. EXAMPLE 10-3: WRITE VERIFY 10.4.1 USING THE DATA EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM (specification D124) without exceeding the total number of write cycles to a single byte (specifications D120 and D120A). If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. BANKSEL EEADR ; MOVLW CONFIG_ADDR ; MOVWF EEADR ;Address to read BSF EECON1,RD ;EE Read MOVF EEDAT,W ;Move data to W BANKSEL EECON1 ; BSF EECON1,WREN ;Enable write BCF INTCON,GIE ;Disable INTs BTFSC INTCON,GIE ;See AN576 GOTO $-2 ; MOVLW 55h ;Unlock write MOVWF EECON2 ; MOVLW AAh ; MOVWF EECON2 ; BSF EECON1,WR ;Start the write BSF INTCON,GIE ;Enable INTS Required Sequence BANKSELEEDAT ; MOVF EEDAT,W ;EEDAT not changed ;from previous write BSF EECON1,RD ;YES, Read the ;value written XORWF EEDAT,W BTFSS STATUS,Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue PIC12F683 DS41211D-page 74 © 2007 Microchip Technology Inc. 10.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: • Brown-out • Power Glitch • Software Malfunction 10.6 Data EEPROM Operation During Code-Protect Data memory can be code-protected by programming the CPD bit in the Configuration Word register (Register 12-1) to ‘0’. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from programming zeroes over the existing code (which will execute as NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to ‘0’ will also help prevent data memory code protection from becoming breached. TABLE 10-1: SUMMARY OF ASSOCIATED DATA EEPROM REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000 EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000 EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000 EECON2(1) EEPROM Control Register 2 ---- ---- ---- ---- Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the Data EEPROM module. Note 1: EECON2 is not a physical register. © 2007 Microchip Technology Inc. DS41211D-page 75 PIC12F683 11.0 CAPTURE/COMPARE/PWM (CCP) MODULE The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event.The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. The timer resources used by the module are shown in Table 11-1 Additional information on CCP modules is available in the Application Note AN594, “Using the CCP Modules” (DS00594). TABLE 11-1: CCP MODE – TIMER RESOURCES REQUIRED CCP Mode Timer Resource Capture Timer1 Compare Timer1 PWM Timer2 REGISTER 11-1: CCP1CON: CCP1 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: CCP Mode Select bits 0000 = Capture/Compare/PWM off (resets CCP module) 0001 = Unused (reserved) 0010 = Unused (reserved) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP1 pin is unaffected.) 110x = PWM mode active-high 111x = PWM mode active-low PIC12F683 DS41211D-page 76 © 2007 Microchip Technology Inc. 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (see Figure 11-1). 11.1.1 CCP1 PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. FIGURE 11-1: CAPTURE MODE OPERATION BLOCK DIAGRAM 11.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. 11.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode. 11.1.4 CCP PRESCALER There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (see Example 11-1). EXAMPLE 11-1: CHANGING BETWEEN CAPTURE PRESCALERS Note: If the CCP1 pin is configured as an output, a write to the GPIO port can cause a capture condition. CCPR1H CCPR1L TMR1H TMR1L Set Flag bit CCP1IF (PIR1 register) Capture Enable CCP1CON<3:0> Prescaler ÷ 1, 4, 16 and Edge Detect pin CCP1 System Clock (FOSC) BANKSEL CCP1CON ;Set Bank bits to point ;to CCP1CON CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value © 2007 Microchip Technology Inc. DS41211D-page 77 PIC12F683 11.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: • Toggle the CCP1 output. • Set the CCP1 output. • Clear the CCP1 output. • Generate a Special Event Trigger. • Generate a Software Interrupt. The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt. FIGURE 11-2: COMPARE MODE OPERATION BLOCK DIAGRAM 11.2.1 CCP1 PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. 11.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. 11.2.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register). 11.2.4 SPECIAL EVENT TRIGGER When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the GPIO I/O data latch. CCPR1H CCPR1L TMR1H TMR1L Comparator Q S R Output Logic Special Event Trigger Set CCP1IF Interrupt Flag (PIR1) Match TRIS CCP1CON<3:0> Mode Select Output Enable Pin Special Event Trigger will: • Clear TMR1H and TMR1L registers. • NOT set interrupt flag bit TMR1IF of the PIR1 register. • Set the GO/DONE bit to start the ADC conversion. CCP1 4 Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. PIC12F683 DS41211D-page 78 © 2007 Microchip Technology Inc. 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver. Figure 11-1 shows a simplified block diagram of PWM operation. Figure 11-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 11.3.7 “Setup for PWM Operation”. FIGURE 11-3: SIMPLIFIED PWM BLOCK DIAGRAM The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 11-4: CCP PWM OUTPUT Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin. CCPR1L CCPR1H(2) (Slave) Comparator TMR2 PR2 (1) R Q S Duty Cycle Registers CCP1CON<5:4> Clear Timer2, toggle CCP1 pin and latch duty cycle Note 1: The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. 2: In PWM mode, CCPR1H is a read-only register. TRIS CCP1 Pin Comparator Period Pulse Width TMR2 = 0 TMR2 = CCPR1L:CCP1CON<5:4> TMR2 = PR2 © 2007 Microchip Technology Inc. DS41211D-page 79 PIC12F683 11.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. EQUATION 11-1: PWM PERIOD When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPR1L into CCPR1H. 11.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the CCP1<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 11-2 is used to calculate the PWM pulse width. Equation 11-3 is used to calculate the PWM duty cycle ratio. EQUATION 11-2: PULSE WIDTH EQUATION 11-3: DUTY CYCLE RATIO The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2- bit latch, then the CCP1 pin is cleared (see Figure 11-1). 11.3.3 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 11-4. EQUATION 11-4: PWM RESOLUTION TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) Note: The Timer2 postscaler (see Section 7.0 “Timer2 Module”) is not used in the determination of the PWM frequency. PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. Pulse Width = (CCPR1L:CCP1CON<5:4>) • TOSC • (TMR2 Prescale Value) Duty Cycle Ratio (CCPR1L:CCP1CON<5:4>) 4(PR2 + 1) = ----------------------------------------------------------------------- Resolution log[4(PR2 + 1)] log(2) = ------------------------------------------ bits PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 6.6 PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09 Maximum Resolution (bits) 8 8 8 6 5 5 PIC12F683 DS41211D-page 80 © 2007 Microchip Technology Inc. 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 11.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 3.0 “Oscillator Module (With Fail-Safe Clock Monitor)” for additional details. 11.3.6 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 11.3.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Disable the PWM pin (CCP1) output drivers by setting the associated TRIS bit. 2. Set the PWM period by loading the PR2 register. 3. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. 4. Set the PWM duty cycle by loading the CCPR1L register and DC1B bits of the CCP1CON register. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. • Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output after a new PWM cycle has started: • Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). • Enable the CCP1 pin output driver by clearing the associated TRIS bit. © 2007 Microchip Technology Inc. DS41211D-page 81 PIC12F683 TABLE 11-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 TABLE 11-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx xxxx xxxx CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx xxxx xxxx TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture and Compare. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) xxxx xxxx xxxx xxxx CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) xxxx xxxx xxxx xxxx INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 000x PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 -000 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 -000 0000 PR2 Timer2 Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 TMR2 Timer2 Module Register 0000 0000 0000 0000 TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111 Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. PIC12F683 DS41211D-page 82 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 83 PIC12F683 12.0 SPECIAL FEATURES OF THE CPU The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Oscillator Selection • Sleep • Code Protection • ID Locations • In-Circuit Serial Programming™ The PIC12F683 has two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in Reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs, which can use the Power-up Timer to provide at least a 64 ms Reset. With these three functions on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through: • External Reset • Watchdog Timer Wake-up • An interrupt Several oscillator options are also made available to allow the part to fit the application. The INTOSC option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options (see Register 12-1). 12.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information. PIC12F683 DS41211D-page 84 © 2007 Microchip Technology Inc. REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — — FCMEN IESO BOREN1 BOREN0 bit 15 bit 8 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘1’ bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 10 IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled 0 = Internal External Switchover mode is disabled bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 7 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 6 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 5 MCLRE: GP3/MCLR pin function select bit(4) 1 = GP3/MCLR pin function is MCLR 0 = GP3/MCLR pin function is digital input, MCLR internally tied to VDD bit 4 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled and can be enabled by SWDTEN bit of the WDTCON register bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 110 = RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN 011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off. 3: The entire program memory will be erased when the code protection is turned off. 4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. © 2007 Microchip Technology Inc. DS41211D-page 85 PIC12F683 12.2 Calibration Bits Brown-out Reset (BOR), Power-on Reset (POR) and 8 MHz internal oscillator (HFINTOSC) are factory calibrated. These calibration values are stored in fuses located in the Calibration Word (2009h). The Calibration Word is not erased when using the specified bulk erase sequence in the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41244) and thus, does not require reprogramming. 12.3 Reset The PIC12F683 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • Power-on Reset • MCLR Reset • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (BOR) WDT wake-up does not cause register resets in the same manner as a WDT Reset since wake-up is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-2. Software can use these bits to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 12-1. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Section 15.0 “Electrical Specifications” for pulse-width specifications. FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Note 1: Refer to the Configuration Word register (Register 12-1). S R Q External Reset MCLR/VPP pin VDD OSC1/ WDT Module VDD Rise Detect OST/PWRT LFINTOSC WDT Time-out Power-on Reset OST 10-bit Ripple Counter PWRT Chip_Reset 11-bit Ripple Counter Reset Enable OST Enable PWRT SLEEP Brown-out(1) Reset SBOREN BOREN CLKI pin PIC12F683 DS41211D-page 86 © 2007 Microchip Technology Inc. 12.3.1 POWER-ON RESET The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOD (see Section 12.3.4 “Brown-Out Reset (BOR)”). When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to the Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC12F683 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Voltages applied to the MCLR pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-2, is suggested. An internal MCLR option is enabled by clearing the MCLRE bit in the Configuration Word register. When MCLRE = 0, the Reset signal to the chip is generated internally. When the MCLRE = 1, the GP3/MCLR pin becomes an external Reset input. In this mode, the GP3/MCLR pin has a weak pull-up to VDD. FIGURE 12-2: RECOMMENDED MCLR CIRCUIT 12.3.3 POWER-UP TIMER (PWRT) The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates from the 31 kHz LFINTOSC oscillator. For more information, see Section 3.5 “Internal Clock Modes”. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A Configuration bit, PWRTE, can disable (if set) or enable (if cleared or programmed) the Power-up Timer. The Power-up Timer should be enabled when Brown-out Reset is enabled, although it is not required. The Power-up Timer delay will vary from chip-to-chip due to: • VDD variation • Temperature variation • Process variation See DC parameters for details (Section 15.0 “Electrical Specifications”). Note: The POR circuit does not produce an internal Reset when VDD declines. To re-enable the POR, VDD must reach Vss for a minimum of 100 μs. Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to VSS. VDD PIC® MCLR R1 1 kΩ (or greater) C1 0.1 μF (optional, not critical) R2 100 Ω SW1 (needed with capacitor) (optional) MCU © 2007 Microchip Technology Inc. DS41211D-page 87 PIC12F683 12.3.4 BROWN-OUT RESET (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR, allowing it to be controlled in software. By selecting BOREN<1:0> = 10, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled. See Register 12-1 for the Configuration Word definition. A brown-out occurs when VDD falls below VBOR for greater than parameter TBOR (see Section 15.0 “Electrical Specifications”). The brown-out condition will reset the device. This will occur regardless of VDD slew rate. A Brown-out Reset may not occur if VDD falls below VBOR for less than parameter TBOR. On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 12-3). If enabled, the Power-up Timer will be invoked by the Reset and keep the chip in Reset an additional 64 ms. If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. 12.3.5 BOR CALIBRATION The PIC12F683 stores the BOR calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified bulk erase sequence in the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) and thus, does not require reprogramming. FIGURE 12-3: BROWN-OUT SITUATIONS Note: The Power-up Timer is enabled by the PWRTE bit in the Configuration Word register. Note: Address 2008h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming. See “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information. 64 ms(1) VBOR VDD Internal Reset VBOR VDD Internal Reset 64 ms(1) < 64 ms 64 ms(1) VBOR VDD Internal Reset Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’. PIC12F683 DS41211D-page 88 © 2007 Microchip Technology Inc. 12.3.6 TIME-OUT SEQUENCE On power-up, the time-out sequence is as follows: • PWRT time-out is invoked after POR has expired. • OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences. The device can execute code from the INTOSC while OST is active by enabling Two-Speed Start-up or Fail-Safe Monitor (see Section 3.7.2 “Two-Speed Start-up Sequence” and Section 3.8 “Fail-Safe Clock Monitor”). Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers. 12.3.7 POWER CONTROL (PCON) REGISTER The Power Control register PCON (address 8Eh) has two Status bits to indicate what type of Reset occurred last. Bit 0 is BOR (Brown-out). BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR = 0, indicating that a Brown-out has occurred. The BOR Status bit is a “don’t care” and is not necessarily predictable if the brown-out circuit is disabled (BOREN<1:0> = 00 in the Configuration Word register). Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent Reset, if POR is ‘0’, it will indicate that a Power-on Reset has occurred (i.e., VDD may have gone too low). For more information, see Section 4.2.4 “Ultra Low-Power Wake-up” and Section 12.3.4 “Brown-Out Reset (BOR)”. TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Oscillator Configuration Power-up Brown-out Reset Wake-up from PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Sleep XT, HS, LP TPWRT + 1024 • TOSC 1024 • TOSC TPWRT + 1024 • TOSC 1024 • TOSC 1024 • TOSC RC, EC, INTOSC TPWRT — TPWRT — — POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown Name Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets(1) CONFIG(2) BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — PCON — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are not used by BOR. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: See Configuration Word register (Register 12-1) for operation of all register bits. © 2007 Microchip Technology Inc. DS41211D-page 89 PIC12F683 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) TPWRT TOST VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset TPWRT TOST TPWRT TOST VDD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset PIC12F683 DS41211D-page 90 © 2007 Microchip Technology Inc. TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS Register Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out W — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu GPIO 05h --x0 x000 --x0 x000 --uu uuuu PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh/8Bh 0000 0000 0000 0000 uuuu uuuu(2) PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2) TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu T1CON 10h 0000 0000 uuuu uuuu -uuu uuuu TMR2 11h 0000 0000 0000 0000 uuuu uuuu T2CON 12h -000 0000 -000 0000 -uuu uuuu CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 14h xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 15h --00 0000 --00 0000 --uu uuuu WDTCON 18h ---0 1000 ---0 1000 ---u uuuu CMCON0 19h 0000 0000 0000 0000 uuuu uuuu CMCON1 20h ---- --10 ---- --10 ---- --uu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 00-- 0000 00-- 0000 uu-- uuuu OPTION_REG 81h 1111 1111 1111 1111 uuuu uuuu TRISIO 85h --11 1111 --11 1111 --uu uuuu PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PCON 8Eh --01 --0x --0u --uu(1,5) --uu --uu OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu PR2 92h 1111 1111 1111 1111 1111 1111 WPU 95h --11 -111 --11 -111 uuuu uuuu IOC 96h --00 0000 --00 0000 --uu uuuu VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu EEDAT 9Ah 0000 0000 0000 0000 uuuu uuuu EEADR 9Bh 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. © 2007 Microchip Technology Inc. DS41211D-page 91 PIC12F683 TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS EECON1 9Ch ---- x000 ---- q000 ---- uuuu EECON2 9Dh ---- ---- ---- ---- ---- ---- ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu ANSEL 9Fh -000 1111 -000 1111 -uuu uuuu TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Register Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently. 2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 12-5 for Reset value for specific condition. 5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u. Condition Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during Normal Operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu WDT Reset 000h 0000 uuuu --0u --uu WDT Wake-up PC + 1 uuu0 0uuu --uu --uu Brown-out Reset 000h 0001 1uuu --01 --10 Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution of PC + 1. PIC12F683 DS41211D-page 92 © 2007 Microchip Technology Inc. 12.4 Interrupts The PIC12F683 has multiple interrupt sources: • External Interrupt GP2/INT • Timer0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • CCP Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. The Global Interrupt Enable bit, GIE of the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIE1 register. GIE is cleared on Reset. When an interrupt is serviced, the following actions occur automatically: • The GIE is cleared to disable any further interrupt. • The return address is pushed onto the stack. • The PC is loaded with 0004h. The Return from Interrupt instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables unmasked interrupts. The following interrupt flags are contained in the INTCON register: • INT Pin Interrupt • GPIO Change Interrupt • Timer0 Overflow Interrupt The peripheral interrupt flags are contained in the PIR1 register. The corresponding interrupt enable bit is contained in the PIE1 register. The following interrupt flags are contained in the PIR1 register: • EEPROM Data Write Interrupt • A/D Interrupt • Comparator Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • Fail-Safe Clock Monitor Interrupt • CCP Interrupt For external interrupt events, such as the INT pin or GPIO change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (see Figure 12-8). The latency is the same for one or two-cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. For additional information on Timer1, Timer2, comparators, ADC, data EEPROM or Enhanced CCP modules, refer to the respective peripheral section. 12.4.1 GP2/INT INTERRUPT The external interrupt on the GP2/INT pin is edge-triggered; either on the rising edge if the INTEDG bit of the OPTION register is set, or the falling edge, if the INTEDG bit is clear. When a valid edge appears on the GP2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The GP2/INT interrupt can wake-up the processor from Sleep, if the INTE bit was set prior to going into Sleep. See Section 12.7 “Power-Down Mode (Sleep)” for details on Sleep and Figure 12-10 for timing of wake-up from Sleep through GP2/INT interrupt. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts, which were ignored, are still pending to be serviced when the GIE bit is set again. Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. © 2007 Microchip Technology Inc. DS41211D-page 93 PIC12F683 12.4.2 TIMER0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing the T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. 12.4.3 GPIO INTERRUPT An input change on GPIO change sets the GPIF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing the GPIE bit of the INTCON register. Plus, individual pins can be configured through the IOC register. FIGURE 12-7: INTERRUPT LOGIC Note: If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. TMR1IF TMR1IE CMIF CMIE T0IF T0IE INTF INTE GPIF GPIE GIE PEIE Wake-up (If in Sleep mode) Interrupt to CPU EEIE EEIF ADIF ADIE IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR2IF TMR2IE CCP1IF CCP1IE OSFIF OSFIE PIC12F683 DS41211D-page 94 © 2007 Microchip Technology Inc. FIGURE 12-8: INT PIN INTERRUPT TIMING TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 0000 0000 IOC — — IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 --00 0000 PIR1 EEIF ADIF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 PIE1 EEIE ADIE CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition. Shaded cells are not used by the interrupt module. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Interrupt Latency PC PC + 1 PC + 1 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (PC) Inst (PC + 1) Inst (PC – 1) Inst (PC) Dummy Cycle Inst (0004h) — Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. (1) (2) (3) (4) (5) (1) © 2007 Microchip Technology Inc. DS41211D-page 95 PIC12F683 12.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F683 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, makes it easier to context save and restore. The same code shown in Example 12-1 can be used to: • Store the W register. • Store the STATUS register. • Execute the ISR code. • Restore the Status (and Bank Select Bit register). • Restore the W register. EXAMPLE 12-1: SAVING STATUS AND W REGISTERS IN RAM Note: The PIC12F683 normally does not require saving the PCLATH. However, if computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR. MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W ;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W PIC12F683 DS41211D-page 96 © 2007 Microchip Technology Inc. 12.6 Watchdog Timer (WDT) The WDT has the following features: • Operates from the LFINTOSC (31 kHz) • Contains a 16-bit prescaler • Shares an 8-bit prescaler with Timer0 • Time-out period is from 1 ms to 268 seconds • Configuration bit and software controlled WDT is cleared under certain conditions described in Table 12-7. 12.6.1 WDT OSCILLATOR The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit of the OSCCON register does not reflect that the LFINTOSC is enabled. The value of WDTCON is ‘---0 1000’ on all Resets. This gives a nominal time base of 17 ms. 12.6.2 WDT CONTROL The WDTE bit is located in the Configuration Word register. When set, the WDT runs continuously. When the WDTE bit in the Configuration Word register is set, the SWDTEN bit of the WDTCON register has no effect. If WDTE is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC12F683 Family of microcontrollers. See Section 5.0 “Timer0 Module” for more information. FIGURE 12-9: WATCHDOG TIMER BLOCK DIAGRAM TABLE 12-7: WDT STATUS Note: When the Oscillator Start-up Timer (OST) is invoked, the WDT is held in Reset, because the WDT Ripple Counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled). Conditions WDT WDTE = 0 Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST 31 kHz PSA 16-bit WDT Prescaler From Timer0 Clock Source Prescaler(1) 8 PS<2:0> PSA WDT Time-out WDTPS<3:0> To Timer0 WDTE from Configuration Word register 1 0 1 0 SWDTEN from WDTCON LFINTOSC Clock Note 1: This is the shared Timer0/WDT prescaler. See Section 5.0 “Timer0 Module” for more information. © 2007 Microchip Technology Inc. DS41211D-page 97 PIC12F683 TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer(1) 1 = WDT is turned on 0 = WDT is turned off (Reset value) Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE Configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000 OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — — Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of all Configuration Word register bits. PIC12F683 DS41211D-page 98 © 2007 Microchip Technology Inc. 12.7 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). For lowest current consumption in this mode, all I/O pins should be either at VDD or VSS, with no external circuitry drawing current from the I/O pin and the comparators and CVREF should be disabled. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on GPIO should be considered. The MCLR pin must be at a logic high level. 12.7.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin. 2. Watchdog Timer wake-up (if WDT was enabled). 3. Interrupt from GP2/INT pin, GPIO change or a peripheral interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of a device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. TO bit is cleared if WDT wake-up occurred. The following peripheral interrupts can wake the device from Sleep: 1. Timer1 interrupt. Timer1 must be operating as an asynchronous counter. 2. ECCP Capture mode interrupt. 3. A/D conversion (when A/D clock source is FRC). 4. EEPROM write operation completion. 5. Comparator output changes state. 6. Interrupt-on-change. 7. External Interrupt from INT pin. Other peripherals cannot generate interrupts since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction, then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. 12.7.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will Immediately wake-up from Sleep. The SLEEP instruction is executed. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. See Figure 12-10 for more details. Note: It should be noted that a Reset generated by a WDT time-out does not drive MCLR pin low. Note: If the global interrupts are disabled (GIE is cleared) and any interrupt source has both its interrupt enable bit and the corresponding interrupt flag bits set, the device will immediately wake-up from Sleep. © 2007 Microchip Technology Inc. DS41211D-page 99 PIC12F683 FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT 12.8 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. 12.9 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTF flag (INTCON<1>) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC – 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(3) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) PC + 2 0004h 0005h Dummy Cycle TOST(2) PC + 2 Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information. PIC12F683 DS41211D-page 100 © 2007 Microchip Technology Inc. 12.10 In-Circuit Serial Programming™ The PIC12F683 microcontrollers can be serially programmed while in the end application circuit. This is simply done with five connections for: • clock • data • power • ground • programming voltage This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the GP0 and GP1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information. GP0 becomes the programming data and GP1 becomes the programming clock. Both GP0 and GP1 are Schmitt Trigger inputs in Program/Verify mode. A typical In-Circuit Serial Programming connection is shown in Figure 12-11. FIGURE 12-11: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION 12.11 In-Circuit Debugger Since in-circuit debugging requires access to three pins, MPLAB® ICD 2 development with a 14-pin device is not practical. A special 14-pin PIC12F683 ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. A special debugging adapter allows the ICD device to be used in place of a PIC12F683 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F683 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 12-9 shows which features are consumed by the background debugger. TABLE 12-9: DEBUGGER RESOURCES For more information, see “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” (DS51331), available on Microchip’s web site (www.microchip.com). FIGURE 12-12: 14-PIN ICD PINOUT External Connector Signals To Normal Connections To Normal Connections PIC12F683 VDD VSS MCLR/VPP/GP3 GP1 GP0 +5V 0V VPP CLK Data I/O * * * * * Isolation devices (as required) Resource Description Stack 1 level Program Memory Address 0h must be NOP 700h-7FFh 14-Pin PDIP PIC12F683-ICD In-Circuit Debug Device NC ICDMCLR VDD GP5 GP4 GP3 ICD ICDCLK ICDDATA GND GP0 GP1 GP2 NC 1 2 3 4 5 6 7 14 13 12 9 11 10 8 © 2007 Microchip Technology Inc. DS41211D-page 101 PIC12F683 13.0 INSTRUCTION SET SUMMARY The PIC12F683 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. Table 13-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the W register. If ‘d’ is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 μs. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 13.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag. TABLE 13-1: OPCODE FIELD DESCRIPTIONS FIGURE 13-1: GENERAL FORMAT FOR INSTRUCTIONS Field Description f Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. PC Program Counter TO Time-out bit C Carry bit DC Digit carry bit Z Zero bit PD Power-down bit Byte-oriented file register operations 13 8 7 6 0 d = 0 for destination W OPCODE d f (FILE #) d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 0 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations 13 8 7 0 OPCODE k (literal) k = 8-bit immediate value 13 11 10 0 OPCODE k (literal) k = 11-bit immediate value General CALL and GOTO instructions only PIC12F683 DS41211D-page 102 © 2007 Microchip Technology Inc. TABLE 13-2: PIC12F683 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode Status Affected Notes MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C, DC, Z Z Z Z Z Z Z Z Z C C C, DC, Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k – k k k – k – – k k Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk C, DC, Z Z TO, PD Z TO, PD C, DC, Z Z Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. 2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. © 2007 Microchip Technology Inc. DS41211D-page 103 PIC12F683 13.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. ADDWF Add W and f Syntax: [ label ] ADDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) → (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f Syntax: [ label ] ANDWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. BCF Bit Clear f Syntax: [ label ] BCF f,b Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: 0 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BSF Bit Set f Syntax: [ label ] BSF f,b Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: 1 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0 ≤ b ≤ 7 Operation: skip if (f) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. PIC12F683 DS41211D-page 104 © 2007 Microchip Technology Inc. BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 127 0 ≤ b < 7 Operation: skip if (f) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. CALL Call Subroutine Syntax: [ label ] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1 → Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h → (W) 1 → Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. COMF Complement f Syntax: [ label ] COMF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination) Status Affected: Z Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2007 Microchip Technology Inc. DS41211D-page 105 PIC12F683 DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Description: GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction. INCF Increment f Syntax: [ label ] INCF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination) Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a 2-cycle instruction. IORLW Inclusive OR literal with W Syntax: [ label ] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Status Affected: Z Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .OR. (f) → (destination) Status Affected: Z Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. PIC12F683 DS41211D-page 106 © 2007 Microchip Technology Inc. MOVF Move f Syntax: [ label ] MOVF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 MOVLW Move literal to W Syntax: [ label ] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Description: The eight-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction W = 0x5A MOVWF Move W to f Syntax: [ label ] MOVWF f Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example: MOVW F OPTION Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: NOP © 2007 Microchip Technology Inc. DS41211D-page 107 PIC12F683 RETFIE Return from Interrupt Syntax: [ label ] RETFIE Operands: None Operation: TOS → PC, 1 → GIE Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 RETLW Return with literal in W Syntax: [ label ] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W); TOS → PC Status Affected: None Description: The W register is loaded with the eight bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: TABLE CALL TABLE;W contains table ;offset value • ;W now has table value • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = 0x07 After Instruction W = value of k8 RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS → PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. PIC12F683 DS41211D-page 108 © 2007 Microchip Technology Inc. RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Words: 1 Cycles: 1 Example: RLF REG1,0 Before Instruction REG1 = 1110 0110 C = 0 After Instruction REG1 = 1110 0110 W = 1100 1100 C = 1 RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. C Register f C Register f SLEEP Enter Sleep mode Syntax: [ label ] SLEEP Operands: None Operation: 00h → WDT, 0 → WDT prescaler, 1 → TO, 0 → PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SUBLW Subtract W from literal Syntax: [ label ] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. C = 0 W > k C = 1 W ≤ k DC = 0 W<3:0> > k<3:0> DC = 1 W<3:0> ≤ k<3:0> © 2007 Microchip Technology Inc. DS41211D-page 109 PIC12F683 SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (destination) Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. C = 0 W > f C = 1 W ≤ f DC = 0 W<3:0> > f<3:0> DC = 1 W<3:0> ≤ f<3:0> XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f,d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. PIC12F683 DS41211D-page 110 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 111 PIC12F683 14.0 DEVELOPMENT SUPPORT The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. PIC12F683 DS41211D-page 112 © 2007 Microchip Technology Inc. 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process 14.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 14.5 MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • Support for the entire dsPIC30F instruction set • Support for fixed-point and floating-point data • Command line interface • Rich directive set • Flexible macro language • MPLAB IDE compatibility 14.6 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. © 2007 Microchip Technology Inc. DS41211D-page 113 PIC12F683 14.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 14.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC® and MCU devices. It debugs and programs PIC® and dsPIC® Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 14.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. PIC12F683 DS41211D-page 114 © 2007 Microchip Technology Inc. 14.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 14.12 PICkit 2 Development Programmer The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. 14.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/ development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart® battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. © 2007 Microchip Technology Inc. DS41211D-page 115 PIC12F683 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin ...................................................................................................................... 95 mA Maximum current into VDD pin ......................................................................................................................... 95 mA Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Maximum current sunk by GPIO...................................................................................................................... 90 mA Maximum current sourced GPIO...................................................................................................................... 90 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – Σ IOH} + Σ {(VDD – VOH) x IOH} + Σ(VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. PIC12F683 DS41211D-page 116 © 2007 Microchip Technology Inc. FIGURE 15-1: PIC12F683 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 15-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 Frequency (MHz) VDD (V) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 8 10 20 125 25 2.0 0 60 85 VDD (V) 4.0 4.5 5.0 Temperature (°C) 2.5 3.0 3.5 5.5 ± 1% ± 2% ± 5% © 2007 Microchip Technology Inc. DS41211D-page 117 PIC12F683 15.1 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions D001 D001C D001D VDD Supply Voltage 2.0 2.0 3.0 4.5 — — — — 5.5 5.5 5.5 5.5 V V V V FOSC < = 8 MHz: HFINTOSC, EC FOSC < = 4 MHz FOSC < = 10 MHz FOSC < = 20 MHz D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D003 VPOR VDD Start Voltage to ensure internal Power-on Reset signal — VSS — V See Section 12.3.1 “Power-on Reset” for details. D004* SVDD VDD Rise Rate to ensure internal Power-on Reset signal 0.05 — — V/ms See Section 12.3.1 “Power-on Reset” for details. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. PIC12F683 DS41211D-page 118 © 2007 Microchip Technology Inc. 15.2 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D010 Supply Current (IDD)(1, 2) — 11 16 μA 2.0 FOSC = 32 kHz — 18 28 μA 3.0 LP Oscillator mode — 35 54 μA 5.0 D011* — 140 240 μA 2.0 FOSC = 1 MHz — 220 380 μA 3.0 XT Oscillator mode — 380 550 μA 5.0 D012 — 260 360 μA 2.0 FOSC = 4 MHz — 420 650 μA 3.0 XT Oscillator mode — 0.8 1.1 mA 5.0 D013* — 130 220 μA 2.0 FOSC = 1 MHz — 215 360 μA 3.0 EC Oscillator mode — 360 520 μA 5.0 D014 — 220 340 μA 2.0 FOSC = 4 MHz — 375 550 μA 3.0 EC Oscillator mode — 0.65 1.0 mA 5.0 D015 — 8 20 μA 2.0 FOSC = 31 kHz — 16 40 μA 3.0 LFINTOSC mode — 31 65 μA 5.0 D016* — 340 450 μA 2.0 FOSC = 4 MHz — 500 700 μA 3.0 HFINTOSC mode — 0.8 1.2 mA 5.0 D017 — 410 650 μA 2.0 FOSC = 8 MHz — 700 950 μA 3.0 HFINTOSC mode — 1.30 1.65 mA 5.0 D018 — 230 400 μA 2.0 FOSC = 4 MHz EXTRC mode(3) — 400 680 μA 3.0 — 0.63 1.1 mA 5.0 D019 — 2.6 3.25 mA 4.5 FOSC = 20 MHz — 2.8 3.35 mA 5.0 HS Oscillator mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ. © 2007 Microchip Technology Inc. DS41211D-page 119 PIC12F683 15.3 DC Characteristics: PIC12F683-I (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020 Power-down Base Current(IPD)(2) — 0.05 1.2 μA 2.0 WDT, BOR, Comparators, VREF and — 0.15 1.5 μA 3.0 T1OSC disabled — 0.35 1.8 μA 5.0 — 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C D021 — 1.0 2.2 μA 2.0 WDT Current(1) — 2.0 4.0 μA 3.0 — 3.0 7.0 μA 5.0 D022 — 42 60 μA 3.0 BOR Current(1) — 85 122 μA 5.0 D023 — 32 45 μA 2.0 Comparator Current(1), both — 60 78 μA 3.0 comparators enabled — 120 160 μA 5.0 D024 — 30 36 μA 2.0 CVREF Current(1) (high range) — 45 55 μA 3.0 — 75 95 μA 5.0 D025* — 39 47 μA 2.0 CVREF Current(1) (low range) — 59 72 μA 3.0 — 98 124 μA 5.0 D026 — 4.5 7.0 μA 2.0 T1OSC Current(1), 32.768 kHz — 5.0 8.0 μA 3.0 — 6.0 12 μA 5.0 D027 — 0.30 1.6 μA 3.0 A/D Current(1), no conversion in — 0.36 1.9 μA 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. PIC12F683 DS41211D-page 120 © 2007 Microchip Technology Inc. 15.4 DC Characteristics: PIC12F683-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Param No. Device Characteristics Min Typ† Max Units Conditions VDD Note D020E Power-down Base Current (IPD)(2) — 0.05 9 μA 2.0 WDT, BOR, Comparators, VREF and — 0.15 11 μA 3.0 T1OSC disabled — 0.35 15 μA 5.0 D021E — 1 17.5 μA 2.0 WDT Current(1) — 2 19 μA 3.0 — 3 22 μA 5.0 D022E — 42 65 μA 3.0 BOR Current(1) — 85 127 μA 5.0 D023E — 32 45 μA 2.0 Comparator Current(1), both — 60 78 μA 3.0 comparators enabled — 120 160 μA 5.0 D024E — 30 70 μA 2.0 CVREF Current(1) (high range) — 45 90 μA 3.0 — 75 120 μA 5.0 D025E* — 39 91 μA 2.0 CVREF Current(1) (low range) — 59 117 μA 3.0 — 98 156 μA 5.0 D026E — 4.5 25 μA 2.0 T1OSC Current(1), 32.768 kHz — 5 30 μA 3.0 — 6 40 μA 5.0 D027E — 0.30 12 μA 3.0 A/D Current(1), no conversion in — 0.36 16 μA 5.0 progress * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. 2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. © 2007 Microchip Technology Inc. DS41211D-page 121 PIC12F683 15.5 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions VIL Input Low Voltage I/O Port: D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V D030A Vss — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V D031 with Schmitt Trigger buffer Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V D032 MCLR, OSC1 (RC mode)(1) VSS — 0.2 VDD V D033 OSC1 (XT and LP modes) VSS — 0.3 V D033A OSC1 (HS mode) VSS — 0.3 VDD V VIH Input High Voltage I/O ports: — D040 with TTL buffer 2.0 — VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25 VDD + 0.8 — VDD V 2.0V ≤ VDD ≤ 4.5V D041 with Schmitt Trigger buffer 0.8 VDD — VDD V 2.0V ≤ VDD ≤ 5.5V D042 MCLR 0.8 VDD — VDD V D043 OSC1 (XT and LP modes) 1.6 — VDD V D043A OSC1 (HS mode) 0.7 VDD — VDD V D043B OSC1 (RC mode) 0.9 VDD — VDD V (Note 1) IIL Input Leakage Current(2) D060 I/O ports — ± 0.1 ± 1 μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance D061 MCLR(3) — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD D063 OSC1 — ± 0.1 ± 5 μA VSS ≤ VPIN ≤ VDD, XT, HS and LP oscillator configuration D070* IPUR GPIO Weak Pull-up Current 50 250 400 μA VDD = 5.0V, VPIN = VSS VOL Output Low Voltage(5) D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) VOH Output High Voltage(5) D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. PIC12F683 DS41211D-page 122 © 2007 Microchip Technology Inc. D100 IULP Ultra Low-Power Wake-Up Current — 200 — nA See Application Note AN879, “Using the Microchip Ultra Low-Power Wake-up Module” (DS00879) Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101A* CIO All I/O pins — — 50 pF Data EEPROM Memory D120 ED Byte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C D120A ED Byte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write VMIN = Minimum operating voltage D122 TDEW Erase/Write Cycle Time — 5 6 ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF Number of Total Erase/Write Cycles before Refresh(4) 1M 10M — E/W -40°C ≤ TA ≤ +85°C Program Flash Memory D130 EP Cell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C D130A ED Cell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VPEW VDD for Erase/Write 4.5 — 5.5 V D133 TPEW Erase/Write cycle time — 2 2.5 ms D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated 15.5 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) (Continued) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Sym Characteristic Min Typ† Max Units Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. 2: Negative current is defined as current sourced by the pin. 3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. © 2007 Microchip Technology Inc. DS41211D-page 123 PIC12F683 15.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Typ Units Conditions TH01 θJA Thermal Resistance Junction to Ambient 84.6 °C/W 8-pin PDIP package 163.0 °C/W 8-pin SOIC package 52.4 °C/W 8-pin DFN-S 4x4x0.9 mm package 46.3 °C/W 8-pin DFN-S 6x5 mm package TH02 θJC Thermal Resistance Junction to Case 41.2 °C/W 8-pin PDIP package 38.8 °C/W 8-pin SOIC package 3.0 °C/W 8-pin DFN-S 4x4x0.9 mm package 2.6 °C/W 8-pin DFN-S 6x5 mm package TH03 TJ Junction Temperature 150 °C For derated power calculations TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD (NOTE 1) TH06 PI/O I/O Power Dissipation — W PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = (TJ - TA)/θJA (NOTE 2, 3) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power dissipation or derated power (PDER). PIC12F683 DS41211D-page 124 © 2007 Microchip Technology Inc. 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: FIGURE 15-3: LOAD CONDITIONS 1. TppS2ppS 2. TppS T F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O PORT t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (High-impedance) V Valid L Low Z High-impedance VSS CL Legend: CL = 50 pF for all pins 15 pF for OSC2 output Load Condition Pin © 2007 Microchip Technology Inc. DS41211D-page 125 PIC12F683 15.8 AC Characteristics: PIC12F683 (Industrial, Extended) FIGURE 15-4: CLOCK TIMING TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode DC — 4 MHz XT Oscillator mode DC — 20 MHz HS Oscillator mode DC — 20 MHz EC Oscillator mode Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 20 MHz HS Oscillator mode DC — 4 MHz RC Oscillator mode OS02 TOSC External CLKIN Period(1) 27 — • μs LP Oscillator mode 250 — • ns XT Oscillator mode 50 — • ns HS Oscillator mode 50 — • ns EC Oscillator mode Oscillator Period(1) — 30.5 — μs LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 250 — — ns RC Oscillator mode OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC OS04* TosH, TosL External CLKIN High, External CLKIN Low 2 — — μs LP oscillator 100 — — ns XT oscillator 20 — — ns HS oscillator OS05* TosR, TosF External CLKIN Rise, External CLKIN Fall 0 — • ns LP oscillator 0 — • ns XT oscillator 0 — • ns HS oscillator * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. OSC1/CLKIN OSC2/CLKOUT Q4 Q1 Q2 Q3 Q4 Q1 OS02 OS03 OS04 OS04 OSC2/CLKOUT (LP,XT,HS Modes) (CLKOUT Mode) PIC12F683 DS41211D-page 126 © 2007 Microchip Technology Inc. TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Freq. Tolerance Min Typ† Max Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 TSC Fail-Safe Sample Clock Period(1) — — 21 — ms LFINTOSC/64 OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C ±2% 7.84 8.0 8.16 MHz 2.5V ≤ VDD ≤ 5.5V, 0°C ≤ TA ≤ +85°C ±5% 7.60 8.0 8.40 MHz 2.0V ≤ VDD ≤ 5.5V, -40°C ≤ TA ≤ +85°C (Ind.), -40°C ≤ TA ≤ +125°C (Ext.) OS09* LFOSC Internal Uncalibrated LFINTOSC Frequency — 15 31 45 kHz OS10* TIOSC ST HFINTOSC Oscillator Wake-up from Sleep Start-up Time — 5.5 12 24 μs VDD = 2.0V, -40°C to +85°C — 3.5 7 14 μs VDD = 3.0V, -40°C to +85°C — 3 6 11 μs VDD = 5.0V, -40°C to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 3: By design. © 2007 Microchip Technology Inc. DS41211D-page 127 PIC12F683 FIGURE 15-5: CLKOUT AND I/O TIMING Fosc CLKOUT I/O pin (Input) I/O pin (Output) Q4 Q1 Q2 Q3 OS11 OS19 OS13 OS15 OS18, OS19 OS20 OS21 OS17 OS16 OS14 OS12 OS18 Old Value New Value Cycle Write Fetch Read Execute TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions OS11 TOSH2CKL FOSC↑ to CLKOUT↓ (1) — — 70 ns VDD = 5.0V OS12 TOSH2CKH FOSC↑ to CLKOUT↑ (1) — — 72 ns VDD = 5.0V OS13 TCKL2IOV CLKOUT↓ to Port out valid(1) — — 20 ns OS14 TIOV2CKH Port input valid before CLKOUT↑(1) TOSC + 200 ns — — ns OS15* TOSH2IOV FOSC↑ (Q1 cycle) to Port out valid — 50 70 ns VDD = 5.0V OS16 TOSH2IOI FOSC↑ (Q2 cycle) to Port input invalid (I/O in hold time) 50 — — ns VDD = 5.0V OS17 TIOV2OSH Port input valid to FOSC↑ (Q2 cycle) (I/O in setup time) 20 — — ns OS18 TIOR Port output rise time(2) — — 15 40 72 32 ns VDD = 2.0V VDD = 5.0V OS19 TIOF Port output fall time(2) — — 28 15 55 30 ns VDD = 2.0V VDD = 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TGPP GPIO interrupt-on-change new input level time TCY — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode. PIC12F683 DS41211D-page 128 © 2007 Microchip Technology Inc. FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD MCLR Internal POR PWRT Time-out OSC Start-Up Time Internal Reset(1) Watchdog Timer 33 32 30 31 34 I/O pins 34 Note 1: Asserted low. Reset(1) VBOR VDD (Device in Brown-out Reset) (Device not in Brown-out Reset) 33* 37 * 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. Reset (due to BOR) VBOR + VHYST © 2007 Microchip Technology Inc. DS41211D-page 129 PIC12F683 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — μs μs VDD = 5V, -40°C to +85°C VDD = 5V 31 TWDT Watchdog Timer Time-out Period (No Prescaler) 10 10 16 16 29 31 ms ms VDD = 5V, -40°C to +85°C VDD = 5V 32 TOST Oscillation Start-up Timer Period(1, 2) — 1024 — TOSC (NOTE 3) 33* TPWRT Power-up Timer Period 40 65 140 ms 34* TIOZ I/O High-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 μs 35 VBOR Brown-out Reset Voltage 2.0 — 2.2 V (NOTE 4) 36* VHYST Brown-out Reset Hysteresis — 50 — mV 37* TBOR Brown-out Reset Minimum Detection Period 100 — — μs VDD ≤ VBOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2: By design. 3: Period of the slower clock. 4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. PIC12F683 DS41211D-page 130 © 2007 Microchip Technology Inc. FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions 40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns With Prescaler 10 — — ns 42* TT0P T0CKI Period Greater of: 20 or TCY + 40 N — — ns N = prescale value (2, 4, ..., 256) 45* TT1H T1CKI High Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 46* TT1L T1CKI Low Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 47* TT1P T1CKI Input Period Synchronous Greater of: 30 or TCY + 40 N — — ns N = prescale value (1, 2, 4, 8) Asynchronous 60 — — ns 48 FT1 Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) — 32.768 — kHz 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment 2 TOSC — 7 TOSC — Timers in Sync mode * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. T0CKI T1CKI 40 41 42 45 46 47 49 TMR0 or TMR1 © 2007 Microchip Technology Inc. DS41211D-page 131 PIC12F683 FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP) TABLE 15-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns With Prescaler 20 — — ns CC03* TccP CCP1 Input Period 3TCY + 40 N — — ns N = prescale value (1, 4 or 16) * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Refer to Figure 15-3 for load conditions. (Capture mode) CC01 CC02 CC03 CCP1 PIC12F683 DS41211D-page 132 © 2007 Microchip Technology Inc. TABLE 15-7: COMPARATOR SPECIFICATIONS TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics Min Typ† Max Units Comments CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV (VDD - 1.5)/2 CM02 VCM Input Common Mode Voltage 0 — VDD – 1.5 V CM03* CMRR Common Mode Rejection Ratio +55 — — dB CM04* TRT Response Time Falling — 150 600 ns (NOTE 1) Rising — 200 1000 ns CM05* TMC2COV Comparator Mode Change to Output Valid — — 10 μs * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics Min Typ† Max Units Comments CV01* CLSB Step Size(2) — — VDD/24 VDD/32 — — V V Low Range (VRR = 1) High Range (VRR = 0) CV02* CACC Absolute Accuracy — — — — ± 1/2 ± 1/2 LSb LSb Low Range (VRR = 1) High Range (VRR = 0) CV03* CR Unit Resistor Value (R) — 2k — Ω CV04* CST Settling Time(1) — — 10 μs * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’. 2: See Section 8.11 “Comparator Voltage Reference” for more information. © 2007 Microchip Technology Inc. DS41211D-page 133 PIC12F683 TABLE 15-9: PIC12F683 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error — — ±1 LSb VREF = 5.12V AD07 EGN Gain Error — — ±1 LSb VREF = 5.12V AD06 AD06A VREF Reference Voltage(3) 2.2 2.7 — — VDD V Absolute minimum to ensure 1 LSb accuracy AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source — — 10 kΩ AD09* IREF VREF Input Current(3) 10 — 1000 μA During VAIN acquisition. Based on differential of VHOLD to VAIN. — — 50 μA During A/D conversion cycle. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input. 4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. PIC12F683 DS41211D-page 134 © 2007 Microchip Technology Inc. TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions AD130* TAD A/D Clock Period 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range A/D Internal RC Oscillator Period 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 μs At VDD = 5.0V AD131 TCNV Conversion Time (not including Acquisition Time)(1) — 11 — TAD Set GO/DONE bit to new data in A/D Result register. AD132* TACQ Acquisition Time 11.5 — μs AD133* TAMP Amplifier Settling Time — — 5 μs AD134 TGO Q4 to A/D Clock Start — — TOSC/2 TOSC/2 + TCY — — — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle. 2: See Section 9.3 “A/D Acquisition Requirements” for minimum conditions. © 2007 Microchip Technology Inc. DS41211D-page 135 PIC12F683 FIGURE 15-10: PIC12F683 A/D CONVERSION TIMING (NORMAL MODE) FIGURE 15-11: PIC12F683 A/D CONVERSION TIMING (SLEEP MODE) AD131 AD130 BSF ADCON0, GO Q4 A/D CLK A/D Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA 9 8 7 3 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1 TCY 6 AD134 (TOSC/2(1)) 1 TCY AD132 AD132 AD131 AD130 BSF ADCON0, GO Q4 A/D CLK A/D Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA 9 7 3 2 1 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. AD134 8 6 (TOSC/2 + TCY(1)) 1 TCY 1 TCY PIC12F683 DS41211D-page 136 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 137 PIC12F683 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. “Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range. FIGURE 16-1: TYPICAL IDD vs. FOSC OVER VDD (EC MODE) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 3.0V 4.0V 5.0V 5.5V 2.0V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC IDD (mA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 138 © 2007 Microchip Technology Inc. FIGURE 16-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) EC Mode 3.0V 4.0V 5.0V 2.0V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC IDD (mA) 5.5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Typical IDD vs. FOSC Over Vdd HS Mode 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC IDD (mA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) © 2007 Microchip Technology Inc. DS41211D-page 139 PIC12F683 FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) FIGURE 16-5: TYPICAL IDD vs. VDD OVER FOSC (XT MODE) Maximum IDD vs. FOSC Over Vdd HS Mode 3.5V 4.0V 4.5V 5.0V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC IDD (mA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0V 5.5V XT Mode 0 100 200 300 400 500 600 700 800 900 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 4 MHz 1 MHz PIC12F683 DS41211D-page 140 © 2007 Microchip Technology Inc. FIGURE 16-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) FIGURE 16-7: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) XT Mode 0 200 400 600 800 1,000 1,200 1,400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 4 MHz 1 MHz EXTRC Mode 0 100 200 300 400 500 600 700 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IDD (μA) 1 MHz Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 4 MHz © 2007 Microchip Technology Inc. DS41211D-page 141 PIC12F683 FIGURE 16-8: MAXIMUM IDD vs. VDD (EXTRC MODE) FIGURE 16-9: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz) EXTRC Mode 0 200 400 600 800 1,000 1,200 1,400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 4 MHz 1 MHz LFINTOSC Mode, 31KHZ Typical Maximum 0 10 20 30 40 50 60 70 80 VDD (V) IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 PIC12F683 DS41211D-page 142 © 2007 Microchip Technology Inc. FIGURE 16-10: IDD vs. VDD (LP MODE) FIGURE 16-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) LP Mode 0 10 20 30 40 50 60 70 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 32 kHz Maximum 32 kHz Typical HFINTOSC 2.0V 3.0V 4.0V 5.0V 5.5V 0 200 400 600 800 1,000 1,200 1,400 1,600 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) © 2007 Microchip Technology Inc. DS41211D-page 143 PIC12F683 FIGURE 16-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) FIGURE 16-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) HFINTOSC 2.0V 3.0V 4.0V 5.0V 5.5V 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC IDD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Typical (Sleep Mode all Peripherals Disabled) 0.0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 144 © 2007 Microchip Technology Inc. FIGURE 16-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) FIGURE 16-15: COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED) Maximum (Sleep Mode all Peripherals Disabled) Max. 125°C Max. 85°C 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Maximum: Mean + 3σ Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0 20 40 60 80 100 120 140 160 180 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Maximum Typical Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) © 2007 Microchip Technology Inc. DS41211D-page 145 PIC12F683 FIGURE 16-16: BOR IPD vs. VDD OVER TEMPERATURE FIGURE 16-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE 0 20 40 60 80 100 120 140 160 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Maximum Typical Typical 0.0 0.5 1.0 1.5 2.0 2.5 3.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) TTyyppicicaal:l: SSttaattisistticicaal l MMeeaann @@2255°°CC Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 146 © 2007 Microchip Technology Inc. FIGURE 16-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE FIGURE 16-19: WDT PERIOD vs. VDD OVER TEMPERATURE Maximum Max. 125°C Max. 85°C 0.0 5.0 10.0 15.0 20.0 25.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Minimum Typical 10 12 14 16 18 20 22 24 26 28 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (ms) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. (125°C) Max. (85°C) © 2007 Microchip Technology Inc. DS41211D-page 147 PIC12F683 FIGURE 16-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V) FIGURE 16-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) Vdd = 5V 10 12 14 16 18 20 22 24 26 28 30 -40°C 25°C 85°C 125°C Temperature (°C) Time (ms) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Maximum Typical Minimum High Range Typical Max. 85°C 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 148 © 2007 Microchip Technology Inc. FIGURE 16-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) FIGURE 16-23: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) Typical Max. 85°C 0 20 40 60 80 100 120 140 160 180 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (μA) Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) (VDD = 3V, -40×C TO 125×C) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL (V) Max. 85°C Max. 125°C Typical 25°C Min. -40°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) © 2007 Microchip Technology Inc. DS41211D-page 149 PIC12F683 FIGURE 16-24: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) FIGURE 16-25: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL (V) Typical: Statistical Mean @25×C Maximum: Mea n(s-4 +0 ×3C to 125×C) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 85°C Typ. 25°C Min. -40°C Max. 125°C 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) VOH (V) Typ. 25°C Max. -40°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 150 © 2007 Microchip Technology Inc. FIGURE 16-26: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) FIGURE 16-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (VDD = 5V, -40×C TO 125×C) 3.0 3.5 4.0 4.5 5.0 5.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) VOH (V) Max. -40°C Typ. 25°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) (TTL Input, -40×C TO 125×C) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) VIN (V) Typ. 25°C Max. -40°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) © 2007 Microchip Technology Inc. DS41211D-page 151 PIC12F683 FIGURE 16-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE FIGURE 16-29: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) (ST Input, -40×C TO 125×C) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) VIN (V) VIH Max. 125°C VIH Min. -40°C VIL Min. 125°C VIL Max. -40°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Typ. 25°C Max. 85°C Max. 125°C 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) IPD (mA) Maximum: Mea n(- 4+0 3×C to 125×C) Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 152 © 2007 Microchip Technology Inc. FIGURE 16-30: COMPARATOR RESPONSE TIME (RISING EDGE) FIGURE 16-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 531 806 0 100 200 300 400 500 600 700 800 900 1000 2.0 2.5 4.0 5.5 VDD (V) Response Time (nS) Max. 85°C Typ. 25°C Min. -40°C Max. 125°C Note: V- input = Transition from VCM + 100MV to VCM - 20MV V+ input = VCM VCM = VDD - 1.5V)/2 0 100 200 300 400 500 600 700 800 900 1000 2.0 2.5 4.0 5.5 VDD (V) Response Time (nS) Max. 85°C Typ. 25°C Min. -40°C Max. 125°C Note: V- input = Transition from VCM - 100MV to VCM + 20MV V+ input = VCM VCM = VDD - 1.5V)/2 © 2007 Microchip Technology Inc. DS41211D-page 153 PIC12F683 FIGURE 16-32: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) FIGURE 16-33: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE LFINTOSC 31Khz 0 5,000 10,000 15,000 20,000 25,000 30,000 35,000 40,000 45,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Frequency (Hz) Max. -40°C Typ. 25°C Min. 85°C Min. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0 2 4 6 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (μs) 25°C 85°C 125°C -40°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) PIC12F683 DS41211D-page 154 © 2007 Microchip Technology Inc. FIGURE 16-34: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE FIGURE 16-35: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (μs) 85°C 25°C -40°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) -40C to +85C 0 5 10 15 20 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (μs) -40°C 85°C 25°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) © 2007 Microchip Technology Inc. DS41211D-page 155 PIC12F683 FIGURE 16-36: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE FIGURE 16-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) -40C to +85C 0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Time (μs) -40°C 25°C 85°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) PIC12F683 DS41211D-page 156 © 2007 Microchip Technology Inc. FIGURE 16-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) © 2007 Microchip Technology Inc. DS41211D-page 157 PIC12F683 FIGURE 16-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Change from Calibration (%) PIC12F683 DS41211D-page 158 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 159 PIC12F683 17.0 PACKAGING INFORMATION 17.1 Package Marking Information * Standard PIC® device marking consists of Microchip part number, year code, week code and traceability code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. XXXXXNNN 8-Lead PDIP XXXXXXXX YYWW I/P 017 Example 12F683 0415 8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN Example 12F683 I/SN0415 017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e3 e3 XXXXXX 8-Lead DFN (4x4x0.9 mm) XXXXXX YYWW NNN 12F683 Example I/MD 0415 017 XXXXXXX 8-Lead DFN-S (6x5 mm) XXXXXXX XXYYWW NNN 12F683 Example I/MF 0415 017 e3 e3 e3 e3 PIC12F683 DS41211D-page 160 © 2007 Microchip Technology Inc. 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 N E1 NOTE 1 D 1 2 3 A A1 A2 L b1 b e E eB c Microchip Technology Drawing C04-018B © 2007 Microchip Technology Inc. DS41211D-page 161 PIC12F683 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – – 1.75 Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E 6.00 BSC Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° D N e E E1 NOTE 1 1 2 3 b A A1 A2 L L1 c h h φ β α Microchip Technology Drawing C04-057B PIC12F683 DS41211D-page 162 © 2007 Microchip Technology Inc. 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.80 BSC Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.20 REF Overall Length D 4.00 BSC Exposed Pad Width E2 0.00 2.20 2.80 Overall Width E 4.00 BSC Exposed Pad Length D2 0.00 3.00 3.60 Contact Width b 0.25 0.30 0.35 Contact Length L 0.30 0.55 0.65 Contact-to-Exposed Pad K 0.20 – – D N E NOTE 1 1 2 A3 A A1 NOTE 2 NOTE 1 D2 2 1 E2 L N e b K EXPOSED PAD TOP VIEW BOTTOM VIEW Microchip Technology Drawing C04-131C © 2007 Microchip Technology Inc. DS41211D-page 163 PIC12F683 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – 0.85 1.00 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 4.67 BSC Exposed Pad Length D2 3.85 4.00 4.15 Overall Width E 5.99 BSC Molded Package Width E1 5.74 BSC Exposed Pad Width E2 2.16 2.31 2.46 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12° φ NOTE 2 A3 A2 A1 A NOTE 1 NOTE 1 EXPOSED PAD BOTTOM VIEW 1 2 D2 2 1 E2 K L N e b E E1 D D1 N TOP VIEW Microchip Technology Drawing C04-113B PIC12F683 DS41211D-page 164 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 165 PIC12F683 APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B Rewrites of the Oscillator and Special Features of the CPU sections. General corrections to Figures and formatting. Revision C Revisions throughout document. Incorporated Golden Chapters. Revision D Replaced Package Drawings; Revised Product ID Section (SN package to 3.90 mm); Replaced PICmicro with PIC; Replaced Dev Tool Section. APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This discusses some of the issues in migrating from other PIC devices to the PIC12F683 device. B.1 PIC16F676 to PIC12F683 TABLE B-1: FEATURE COMPARISON Feature PIC16F676 PIC12F683 Max Operating Speed 20 MHz 20 MHz Max Program Memory (Words) 1024 2048 SRAM (bytes) 64 128 A/D Resolution 10-bit 10-bit Data EEPROM (Bytes) 128 256 Timers (8/16-bit) 1/1 2/1 Oscillator Modes 8 8 Brown-out Reset Y Y Internal Pull-ups RA0/1/2/4/5 GP0/1/2/4/5, MCLR Interrupt-on-change RA0/1/2/3/4/5 GP0/1/2/3/4/5 Comparator 1 1 ECCP N N Ultra Low-Power Wake-Up N Y Extended WDT N Y Software Control Option of WDT/BOR N Y INTOSC Frequencies 4 MHz 32 kHz- 8 MHz Clock Switching N Y Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. PIC12F683 DS41211D-page 166 © 2007 Microchip Technology Inc. NOTES: © 2007 Microchip Technology Inc. DS41211D-page 167 PIC12F683 INDEX A A/D Specifications.................................................... 133, 134 Absolute Maximum Ratings .............................................. 115 AC Characteristics Industrial and Extended ............................................ 125 Load Conditions ........................................................ 124 ADC .................................................................................... 61 Acquisition Requirements ........................................... 67 Associated registers.................................................... 69 Block Diagram............................................................. 61 Calculating Acquisition Time....................................... 67 Channel Selection....................................................... 61 Configuration............................................................... 61 Configuring Interrupt ................................................... 64 Conversion Clock........................................................ 62 Conversion Procedure ................................................ 64 GPIO Configuration..................................................... 61 Internal Sampling Switch (RSS) IMPEDANCE ................ 67 Interrupts..................................................................... 63 Operation .................................................................... 63 Operation During Sleep .............................................. 64 Reference Voltage (VREF)........................................... 62 Result Formatting........................................................ 63 Source Impedance...................................................... 67 Special Event Trigger.................................................. 64 Starting an A/D Conversion ........................................ 63 ADCON0 Register............................................................... 65 ADRESH Register (ADFM = 0) ........................................... 66 ADRESH Register (ADFM = 1) ........................................... 66 ADRESL Register (ADFM = 0)............................................ 66 ADRESL Register (ADFM = 1)............................................ 66 Analog Input Connection Considerations............................ 52 Analog-to-Digital Converter. See ADC ANSEL Register .................................................................. 33 Assembler MPASM Assembler................................................... 112 B Block Diagrams (CCP) Capture Mode Operation ................................. 76 ADC ............................................................................ 61 ADC Transfer Function ............................................... 68 Analog Input Model ............................................... 52, 68 CCP PWM................................................................... 78 Clock Source............................................................... 19 Comparator ................................................................. 51 Compare ..................................................................... 77 Crystal Operation........................................................ 22 External RC Mode....................................................... 23 Fail-Safe Clock Monitor (FSCM) ................................. 29 GP1 Pin....................................................................... 37 GP2 Pin....................................................................... 37 GP3 Pin....................................................................... 38 GP4 Pin....................................................................... 38 GP5 Pin....................................................................... 39 In-Circuit Serial Programming Connections.............. 100 Interrupt Logic ............................................................. 93 MCLR Circuit............................................................... 86 On-Chip Reset Circuit ................................................. 85 PIC12F683.................................................................... 5 Resonator Operation................................................... 22 Timer1......................................................................... 44 Timer2 ........................................................................ 49 TMR0/WDT Prescaler ................................................ 41 Watchdog Timer (WDT).............................................. 96 Brown-out Reset (BOR)...................................................... 87 Associated.................................................................. 88 Calibration .................................................................. 87 Specifications ........................................................... 129 Timing and Characteristics ....................................... 128 C C Compilers MPLAB C18.............................................................. 112 MPLAB C30.............................................................. 112 Calibration Bits.................................................................... 85 Capture Module. See Capture/Compare/PWM (CCP) Capture/Compare/PWM (CCP) .......................................... 75 Associated registers w/ Capture, Compare and Timer1 ......................................................... 81 Associated registers w/ PWM and Timer2.................. 81 Capture Mode............................................................. 76 CCPx Pin Configuration.............................................. 76 Compare Mode........................................................... 77 CCPx Pin Configuration...................................... 77 Software Interrupt Mode............................... 76, 77 Special Event Trigger ......................................... 77 Timer1 Mode Selection................................. 76, 77 Prescaler .................................................................... 76 PWM Mode................................................................. 78 Duty Cycle .......................................................... 79 Effects of Reset .................................................. 80 Example PWM Frequencies and Resolutions, 20 MHZ.................................. 79 Example PWM Frequencies and Resolutions, 8 MHz .................................... 79 Operation in Sleep Mode.................................... 80 Setup for Operation ............................................ 80 System Clock Frequency Changes .................... 80 PWM Period ............................................................... 79 Setup for PWM Operation .......................................... 80 Timer Resources ........................................................ 75 CCP. See Capture/Compare/PWM (CCP) CCP1CON Register............................................................ 75 Clock Sources External Modes........................................................... 21 EC ...................................................................... 21 HS ...................................................................... 22 LP....................................................................... 22 OST .................................................................... 21 RC ...................................................................... 23 XT....................................................................... 22 Internal Modes............................................................ 23 Frequency Selection........................................... 25 HFINTOSC ......................................................... 23 INTOSC.............................................................. 23 INTOSCIO.......................................................... 23 LFINTOSC.......................................................... 25 Clock Switching .................................................................. 27 Code Examples A/D Conversion .......................................................... 64 Assigning Prescaler to Timer0.................................... 42 Assigning Prescaler to WDT....................................... 42 Changing Between Capture Prescalers ..................... 76 Data EEPROM Read.................................................. 73 Data EEPROM Write.................................................. 73 PIC12F683 DS41211D-page 168 © 2007 Microchip Technology Inc. Indirect Addressing .....................................................18 Initializing GPIO .......................................................... 31 Saving STATUS and W Registers in RAM ................. 95 Ultra Low-Power Wake-up Initialization ...................... 35 Write Verify ................................................................. 73 Code Protection .................................................................. 99 Comparator ......................................................................... 51 C2OUT as T1 Gate .....................................................57 Configurations............................................................. 53 I/O Operating Modes...................................................53 Interrupts..................................................................... 55 Operation .............................................................. 51, 54 Operation During Sleep .............................................. 56 Response Time........................................................... 54 Synchronizing COUT w/Timer1 .................................. 57 Comparator Module Associated registers.................................................... 59 Comparator Voltage Reference (CVREF) Response Time........................................................... 54 Comparator Voltage Reference (CVREF) ............................58 Effects of a Reset........................................................ 56 Specifications............................................................ 132 Comparators C2OUT as T1 Gate .....................................................45 Effects of a Reset........................................................ 56 Specifications............................................................ 132 Compare Module. See Capture/Compare/PWM (CCP) CONFIG Register................................................................ 84 Configuration Bits................................................................ 83 CPU Features ..................................................................... 83 Customer Change Notification Service ............................. 171 Customer Notification Service........................................... 171 Customer Support ............................................................. 171 D Data EEPROM Memory Associated Registers .................................................. 74 Code Protection .................................................... 71, 74 Data Memory Organization ...................................................7 Map of the PIC12F683.................................................. 8 DC and AC Characteristics Graphs and Tables ...................................................137 DC Characteristics Extended and Industrial ............................................ 121 Industrial and Extended ............................................ 117 Development Support ....................................................... 111 Device Overview ................................................................... 5 E EEADR Register ................................................................. 71 EECON1 Register ............................................................... 72 EECON2 Register ............................................................... 72 EEDAT Register.................................................................. 71 EEPROM Data Memory Avoiding Spurious Write.............................................. 74 Reading....................................................................... 73 Write Verify ................................................................. 73 Writing......................................................................... 73 Effects of Reset PWM mode ................................................................. 80 Electrical Specifications .................................................... 115 Enhanced Capture/Compare/PWM (ECCP) Specifications............................................................ 131 Errata .................................................................................... 3 F Fail-Safe Clock Monitor ...................................................... 29 Fail-Safe Condition Clearing....................................... 29 Fail-Safe Detection ..................................................... 29 Fail-Safe Operation..................................................... 29 Reset or Wake-up from Sleep .................................... 29 Firmware Instructions ....................................................... 101 Fuses. See Configuration Bits G General Purpose Register File ............................................. 8 GPIO................................................................................... 31 Additional Pin Functions ............................................. 32 ANSEL Register ................................................. 32 Interrupt-on-Change ........................................... 32 Ultra Low-Power Wake-up............................ 32, 35 Weak Pull-up ...................................................... 32 Associated Registers.................................................. 39 GP0 ............................................................................ 36 GP1 ............................................................................ 37 GP2 ............................................................................ 37 GP3 ............................................................................ 38 GP4 ............................................................................ 38 GP5 ............................................................................ 39 Pin Descriptions and Diagrams .................................. 36 Specifications ........................................................... 127 GPIO Register .................................................................... 31 I ID Locations........................................................................ 99 In-Circuit Debugger........................................................... 100 In-Circuit Serial Programming (ICSP)............................... 100 Indirect Addressing, INDF and FSR Registers ................... 18 Instruction Format............................................................. 101 Instruction Set................................................................... 101 ADDLW..................................................................... 103 ADDWF..................................................................... 103 ANDLW..................................................................... 103 ANDWF..................................................................... 103 BCF .......................................................................... 103 BSF........................................................................... 103 BTFSC...................................................................... 103 BTFSS ...................................................................... 104 CALL......................................................................... 104 CLRF ........................................................................ 104 CLRW....................................................................... 104 CLRWDT .................................................................. 104 COMF ....................................................................... 104 DECF........................................................................ 104 DECFSZ ................................................................... 105 GOTO....................................................................... 105 INCF ......................................................................... 105 INCFSZ..................................................................... 105 IORLW...................................................................... 105 IORWF...................................................................... 105 MOVF ....................................................................... 106 MOVLW.................................................................... 106 MOVWF.................................................................... 106 NOP.......................................................................... 106 RETFIE..................................................................... 107 RETLW..................................................................... 107 RETURN................................................................... 107 RLF........................................................................... 108 RRF .......................................................................... 108 SLEEP ...................................................................... 108 © 2007 Microchip Technology Inc. DS41211D-page 169 PIC12F683 SUBLW..................................................................... 108 SUBWF..................................................................... 109 SWAPF ..................................................................... 109 XORLW..................................................................... 109 XORWF..................................................................... 109 INTCON Register ................................................................ 14 Internal Oscillator Block INTOSC Specifications............................................ 126, 127 Internal Sampling Switch (RSS) IMPEDANCE ........................ 67 Internet Address................................................................ 171 Interrupts............................................................................. 92 ADC ............................................................................ 64 Associated Registers .................................................. 94 Comparator ................................................................. 55 Context Saving............................................................ 95 Data EEPROM Memory Write .................................... 72 GP2/INT...................................................................... 92 GPIO Interrupt-on-change .......................................... 93 Interrupt-on-Change.................................................... 32 Timer0......................................................................... 93 TMR1 .......................................................................... 46 INTOSC Specifications ............................................. 126, 127 IOC Register ....................................................................... 34 L Load Conditions ................................................................ 124 M MCLR.................................................................................. 86 Internal ........................................................................ 86 Memory Organization Data EEPROM Memory.............................................. 71 Microchip Internet Web Site.............................................. 171 Migrating from other PIC Devices ..................................... 165 MPLAB ASM30 Assembler, Linker, Librarian ................... 112 MPLAB ICD 2 In-Circuit Debugger ................................... 113 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 113 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator .................................................... 113 MPLAB Integrated Development Environment Software .. 111 MPLAB PM3 Device Programmer .................................... 113 MPLINK Object Linker/MPLIB Object Librarian ................ 112 O OPCODE Field Descriptions............................................. 101 OPTION Register .......................................................... 13, 43 OSCCON Register .............................................................. 20 Oscillator Associated registers.............................................. 30, 48 Oscillator Module ................................................................ 19 EC............................................................................... 19 HFINTOSC.................................................................. 19 HS............................................................................... 19 INTOSC ...................................................................... 19 INTOSCIO................................................................... 19 LFINTOSC .................................................................. 19 LP................................................................................ 19 RC............................................................................... 19 RCIO........................................................................... 19 XT ............................................................................... 19 Oscillator Parameters ....................................................... 126 Oscillator Specifications.................................................... 125 Oscillator Start-up Timer (OST) Specifications............................................................ 129 Oscillator Switching Fail-Safe Clock Monitor .............................................. 29 Two-Speed Clock Start-up ......................................... 27 OSCTUNE Register............................................................ 24 P Packaging......................................................................... 159 Details....................................................................... 160 Marking..................................................................... 159 PCL and PCLATH............................................................... 18 Computed GOTO ....................................................... 18 Stack........................................................................... 18 PCON Register ............................................................. 17, 88 PICSTART Plus Development Programmer..................... 114 PIE1 Register ..................................................................... 15 Pin Diagram.......................................................................... 2 Pinout Descriptions PIC12F683 ................................................................... 6 PIR1 Register ..................................................................... 16 Power-Down Mode (Sleep)................................................. 98 Power-On Reset (POR) ...................................................... 86 Power-up Timer (PWRT) .................................................... 86 Specifications ........................................................... 129 Precision Internal Oscillator Parameters .......................... 127 Prescaler Shared WDT/Timer0................................................... 42 Switching Prescaler Assignment ................................ 42 Program Memory Organization............................................. 7 Map and Stack for the PIC12F683 ............................... 7 Programming, Device Instructions.................................... 101 R Reader Response............................................................. 172 Read-Modify-Write Operations ......................................... 101 Registers ADCON0 (ADC Control 0) .......................................... 65 ADRESH (ADC Result High) with ADFM = 0) ............ 66 ADRESH (ADC Result High) with ADFM = 1) ............ 66 ADRESL (ADC Result Low) with ADFM = 0).............. 66 ADRESL (ADC Result Low) with ADFM = 1).............. 66 ANSEL (Analog Select) .............................................. 33 CCP1CON (CCP1 Control) ........................................ 75 CMCON0 (Comparator Control) Register................... 56 CMCON1 (Comparator Control) Register................... 57 CONFIG (Configuration Word) ................................... 84 EEADR (EEPROM Address) ...................................... 71 EECON1 (EEPROM Control 1) .................................. 72 EECON2 (EEPROM Control 2) .................................. 72 EEDAT (EEPROM Data) ............................................ 71 GPIO........................................................................... 31 INTCON (Interrupt Control) ........................................ 14 IOC (Interrupt-on-Change GPIO) ............................... 34 OPTION_REG (OPTION)..................................... 13, 43 OSCCON (Oscillator Control)..................................... 20 OSCTUNE (Oscillator Tuning).................................... 24 PCON (Power Control Register)................................. 17 PCON (Power Control) ............................................... 88 PIE1 (Peripheral Interrupt Enable 1) .......................... 15 PIR1 (Peripheral Interrupt Register 1) ........................ 16 Reset Values .............................................................. 90 Reset Values (Special Registers)............................... 91 STATUS ..................................................................... 12 T1CON ....................................................................... 47 T2CON ....................................................................... 50 TRISIO (Tri-State GPIO) ............................................ 32 VRCON (Voltage Reference Control) ......................... 58 PIC12F683 DS41211D-page 170 © 2007 Microchip Technology Inc. WDTCON (Watchdog Timer Control).......................... 97 WPU (Weak Pull-Up GPIO) ........................................ 34 Resets ................................................................................. 85 Brown-out Reset (BOR) .............................................. 85 MCLR Reset, Normal Operation ................................. 85 MCLR Reset, Sleep .................................................... 85 Power-on Reset (POR) ............................................... 85 WDT Reset, Normal Operation ................................... 85 WDT Reset, Sleep ...................................................... 85 Revision History ................................................................ 165 S Sleep Power-Down Mode .....................................................98 Wake-up......................................................................98 Wake-up Using Interrupts ........................................... 98 Software Simulator (MPLAB SIM)..................................... 112 Special Event Trigger.......................................................... 64 Special Function Registers ...................................................8 STATUS Register................................................................ 12 T T1CON Register.................................................................. 47 T2CON Register.................................................................. 50 Thermal Considerations .................................................... 123 Time-out Sequence............................................................. 88 Timer0................................................................................. 41 Associated Registers .................................................. 43 External Clock............................................................. 42 Interrupt................................................................. 13, 43 Operation .............................................................. 41, 44 Specifications............................................................ 130 T0CKI ..........................................................................42 Timer1................................................................................. 44 Associated registers.................................................... 48 Asynchronous Counter Mode ..................................... 45 Reading and Writing ........................................... 45 Interrupt....................................................................... 46 Modes of Operation .................................................... 44 Operation During Sleep .............................................. 46 Oscillator ..................................................................... 45 Prescaler ..................................................................... 45 Specifications............................................................ 130 Timer1 Gate Inverting Gate .....................................................45 Selecting Source........................................... 45, 57 Synchronizing COUT w/Timer1 .......................... 57 TMR1H Register ......................................................... 44 TMR1L Register .......................................................... 44 Timer2 Associated registers.................................................... 50 Timers Timer1 T1CON................................................................ 47 Timer2 T2CON................................................................ 50 Timing Diagrams A/D Conversion......................................................... 135 A/D Conversion (Sleep Mode) .................................. 135 Brown-out Reset (BOR) ............................................ 128 Brown-out Reset Situations ........................................ 87 CLKOUT and I/O....................................................... 127 Clock Timing ............................................................. 125 Comparator Output .....................................................51 Enhanced Capture/Compare/PWM (ECCP) ............. 131 Fail-Safe Clock Monitor (FSCM) ................................. 30 INT Pin Interrupt ......................................................... 94 Internal Oscillator Switch Timing ................................ 26 Reset, WDT, OST and Power-up Timer ................... 128 Time-out Sequence on Power-up (Delayed MCLR) ... 89 Time-out Sequence on Power-up (MCLR with VDD) .. 89 Timer0 and Timer1 External Clock ........................... 130 Timer1 Incrementing Edge ......................................... 46 Two Speed Start-up.................................................... 28 Wake-up from Sleep Through Interrupt ...................... 99 Timing Parameter Symbology .......................................... 124 TRISIO Register ................................................................. 32 Two-Speed Clock Start-up Mode........................................ 27 U Ultra Low-Power Wake-up............................................ 32, 35 V Voltage Reference. See Comparator Voltage Reference (CVREF) Voltage References Associated registers ................................................... 59 VREF. SEE ADC Reference Voltage W Wake-up Using Interrupts ................................................... 98 Watchdog Timer (WDT)...................................................... 96 Associated Registers.................................................. 97 Clock Source .............................................................. 96 Modes......................................................................... 96 Period ......................................................................... 96 Specifications ........................................................... 129 WDTCON Register ............................................................. 97 WPU Register ..................................................................... 34 WWW Address ................................................................. 171 WWW, On-Line Support ....................................................... 3 © 2007 Microchip Technology Inc. DS41211D-page 171 PIC12F683 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer (FAE) • Technical Support • Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com PIC12F683 DS41211D-page 172 © 2007 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: FAX: (______) _________ - _________ PIC12F683 DS41211D 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? © 2007 Microchip Technology Inc. DS41211D-page 173 PIC12F683 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Temperature Package Pattern Range Device Device: PIC12F683(1), PIC12F683T(2) VDD range 2.0V to 5.5V Temperature Range: I = -40°C to +85°C(Industrial) E = -40°C to +125°C (Extended) Package: P = Plastic DIP MD = Dual-Flat, No Leads (DFN-S, 4x4x0.9 mm) MF = Dual-Flat, No Leads (DFN-S, 6x5 mm) SN = 8-lead Small Outline (3.90 mm) Pattern: 3-digit Pattern Code for QTP (blank otherwise) Examples: a) PIC12F683-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F683-I/SN = Industrial Temp., SOIC package, 20 MHz Note 1: F = Standard Voltage Range LF = Wide Voltage Range 2: T = in tape and reel PLCC, and TQFP packages only. DS41211D-page 174 © 2007 Microchip Technology Inc. AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 WORLDWIDE SALES AND SERVICE 12/08/06 8285ES–AVR–02/2013 Features • High performance, low power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC architecture – 130 powerful instructions – most single clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 16MIPS throughput at 16MHz (Atmel ATmega165PA/645P) – Up to 20MIPS throughput at 20MHz (Atmel ATmega165A/325A/325PA/645A/3250A/3250PA/6450A/6450P) – On-chip 2-cycle multiplier • High endurance non-volatile memory segments – In-system self-programmable flash program memory • 16KBytes (ATmega165A/ATmega165PA) • 32KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 64KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – EEPROM • 512Bytes (ATmega165A/ATmega165PA) • 1Kbytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 2Kbytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – Internal SRAM • 1KBytes (ATmega165A/ATmega165PA) • 2KBytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 4KBytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – Write/erase cycles: 10,000 flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25C (1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True read-while-write operation – Programming lock for software security • Atmel QTouch® library support – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels • JTAG (IEEE std. 1149.1 compliant) interface – Boundary-scan capabilities according to the JTAG standard – Extensive on-chip debug support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real time counter with separate oscillator – Four PWM channels – 8-channel, 10-bit ADC – Programmable serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition detector – Programmable Watchdog Timer with separate on-chip oscillator – On-chip Analog Comparator – Interrupt and Wake-up on pin change • Special microcontroller features – Power-on reset and programmable Brown-out detection – Internal calibrated oscillator – External and internal interrupt sources – Five sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down and Standby • I/O and packages – 54/69 programmable I/O lines – 64/100-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN • Speed grade: – ATmega 165A/165PA/645A/645P: 0 - 16MHz @ 1.8 - 5.5V – ATmega325A/325PA/3250A/3250PA/6450A/6450P: 0 - 20MHz @ 1.8 - 5.5V • Temperature range: – -40°C to 85C industrial • Ultra-low power consumption (picoPower® devices) – Active mode: • 1MHz, 1.8V: 215μA • 32kHz, 1.8V: 8μA (including oscillator) – Power-down mode: 0.1μA at 1.8V – Power-save mode: 0.6μA at 1.8V (Including 32kHz RTC) Note: 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. Atmel ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P 8-bit Atmel Microcontroller with 16/32/64KB In-System Programmable Flash SUMMARY ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 2 8285ES–AVR–02/2013 1. Pin configurations 1.1 Pinout - TQFP and QFN/MLF Figure 1-1. 64A (TQFP)and 64M1 (QFN/MLF) pinout Atmel ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P. Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 32 49 31 30 PC0 VCC GND PF0 (ADC0) PF7 (ADC7/TDI) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) AREF GND AVCC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 DNC (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC2A/PCINT15) PB7 (T1) PG3 (OC1B/PCINT14) PB6 (T0) PG4 (OC1A/PCINT13) PB5 PC1 PG0 PD7 PC2 PC3 PC4 PC5 PC6 PC7 PA7 PG2 PA6 PA5 PA4 PA3 PA0 PA1 PA2 PG1 PD6 PD5 PD4 PD3 PD2 (INT0) PD1 (ICP1) PD0 (TOSC1) XTAL1 (TOSC2) XTAL2 RESET/PG5 GND VCC INDEX CORNER ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 3 8285ES–AVR–02/2013 1.2 Pinout - 100A (TQFP) Figure 1-2. Pinout Atmel ATmega3250A/ATmega3250PA/ATmega6450A/ATmega6450P. (OC2A/PCINT15) PB7 DNC (T1) PG3 (T0) PG4 RESET/PG5 VCC GND (TOSC2) XTAL2 (TOSC1) XTAL1 DNC DNC (PCINT26) PJ2 (PCINT27) PJ3 (PCINT28) PJ4 (PCINT29) PJ5 (PCINT30) PJ6 DNC (ICP1) PD0 (INT0) PD1 PD2 PD3 PD4 PD5 PD6 PD7 AVCC AGND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) DNC DNC PH7 (PCINT23) PH6 (PCINT22) PH5 (PCINT21) PH4 (PCINT20) DNC DNC GND VCC DNC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PG2 PC7 PC6 DNC PH3 (PCINT19) PH2 (PCINT18) PH1 (PCINT17) PH0 (PCINT16) DNC DNC DNC DNC PC5 PC4 PC3 PC2 PC1 PC0 PG1 PG0 INDEX CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 VCC GND DNC (PCINT24) PJ0 (PCINT25) PJ1 DNC DNC DNC DNC (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 TQFP ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 4 8285ES–AVR–02/2013 2. Overview The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, this microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block diagram Figure 2-1. Block diagram. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH MCU CONTROL REGISTER SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTERS INSTRUCTION DECODER DATA DIR. REG. PORTB DATA DIR. REG. PORTE DATA DIR. REG. PORTA DATA DIR. REG. PORTD DATA REGISTER PORTB DATA REGISTER PORTE DATA REGISTER PORTA DATA REGISTER PORTD TIMING AND CONTROL OSCILLATOR INTERRUPT UNIT EEPROM USART SPI STATUS REGISTER Z Y X ALU PORTE DRIVERS PORTB DRIVERS PORTF DRIVERS PORTA DRIVERS PORTD DRIVERS PORTC DRIVERS PE0 - PE7 PB0 - PB7 PF0 - PF7 PA0 - PA7 GND VCC XTAL1 XTAL2 CONTROL LINES + - ANALOG COMPARATOR PC0 - PC7 8-BIT DATA BUS RESET CALIB. OSC DATA DIR. REG. PORTC DATA REGISTER PORTC ON-CHIP DEBUG JTAG TAP PROGRAMMING LOGIC BOUNDARYSCAN DATA DIR. REG. PORTF DATA REGISTER PORTF ADC PD0 - PD7 DATA DIR. REG. PORTG DATA REG. PORTG PORTG DRIVERS PG0 - PG4 AGND AREF AVCC UNIVERSAL SERIAL INTERFACE AVR CPU PORTH DRIVERS PH0 - PH7 DATA DIR. REG. PORTH DATA REGISTER PORTH PORTJ DRIVERS PJ0 - PJ6 DATA DIR. REG. PORTJ DATA REGISTER PORTJ ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 5 8285ES–AVR–02/2013 The Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the XTAL/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel devise is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/ Simulators, In-Circuit Emulators, and Evaluation kits. ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 6 8285ES–AVR–02/2013 2.2 Comparison between Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 2.3 Pin descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate functions of Port B” on page 68. 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate functions of Port B” on page 68. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are Table 2-1. Differences between: ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P. Device Flash EEPROM RAM MHz ATmega165A 16Kbyte 512Bytes 1Kbyte 16 ATmega165PA 16Kbyte 512Bytes 1Kbyte 16 ATmega325A 32Kbyte 1Kbyte 2Kbyte 20 ATmega325PA 32Kbyte 1Kbyte 2Kbyte 20 ATmega3250A 32Kbytes 1Kbyte 2Kbyte 20 ATmega3250PA 32Kbyte 1Kbyte 2Kbyte 20 ATmega645A 64Kbyte 2Kbyte 4Kbyte 16 ATmega645P 64Kbyte 2Kbyte 4Kbyte 16 ATmega6450A 64Kbyte 2Kbyte 4Kbyte 20 ATmega6450P 64Kbyte 2Kbyte 4Kbyte 20 ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 7 8285ES–AVR–02/2013 externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the Atmel ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate functions of Port D” on page 70. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate functions of Port D” on page 70. 2.3.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate functions of Port E” on page 71. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface, see ”Alternate functions of Port F” on page 73. 2.3.9 Port G (PG5:PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on page 75. 2.3.10 Port H (PH7:PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3250A/3250PA/6450A/6450P as listed on page 76. ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 8 8285ES–AVR–02/2013 2.3.11 Port J (PJ6:PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the Atmel ATmega3250A/3250PA/6450A/6450P as listed on page 78. 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 28-13 on page 297. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 9 8285ES–AVR–02/2013 3. Ordering Information 3.1 ATmega165A Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel 5. See characterization specifications at 105°C. Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 16 1.8 - 5.5V ATmega165A-AU ATmega165A-AUR(4) ATmega165A-MU ATmega165A-MUR(4) ATmega165A-MCH ATmega165A-MCHR(4) 64A 64A 64M1 64M1 64MC 64MC Industrial (-40C to 85C) ATmega165A-AN ATmega165A-ANR(4) ATmega165A-MN ATmega165A-MNR(4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) Package Type 64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 64MC 64-lead (2-row Staggered), 7 x 7 x 1.0 mm body, 4.0 x 4.0mm Exposed Pad, Quad Flat No-Lead Package (QFN) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 10 8285ES–AVR–02/2013 3.2 ATmega165PA Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel. 5. See characterization specifications at 105°C. Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 16 1.8 - 5.5V ATmega165PA-AU ATmega165PA-AUR(4) ATmega165PA-MU ATmega165PA-MUR(4) ATmega165PA-MCH ATmega165PA-MCHR(4) 64A 64A 64M1 64M1 64MC 64MC Industrial (-40C to 85C) ATmega165PA-AN ATmega165PA-ANR(4) ATmega165PA-MN ATmega165PA-MNR(4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) Package Type 64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 64MC 64-lead (2-row Staggered), 7 x 7 x 1.0mm body, 4.0 x 4.0 mm Exposed Pad, Quad Flat No-Lead Package (QFN) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 11 8285ES–AVR–02/2013 3.3 ATmega325A Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel 5. See characterizations specifications at 105°C. Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega325A-AU ATmega325A-AUR(4) ATmega325A-MU ATmega325A-MUR(4) 64A 64A 64M1 64M1 Industrial (-40C to 85C) ATmega325A-AN ATmega325A-ANR(4) ATmega325A-MN ATmega325A-MNR(4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) Package Type 64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 12 8285ES–AVR–02/2013 3.4 ATmega325PA Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel 5. See characterization specifications at 105°C. Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega325PA-AU ATmega325PA-AUR(4) ATmega325PA-MU ATmega325PA-MUR(4) 64A 64A 64M1 64M1 Industrial (-40C to 85C) ATmega325PA-AN ATmega325PA-ANR(4) ATmega325PA-MN ATmega325PA-MNR(4) 64A 64A 64M1 64M1 Extended (-40C to 105C)(5) Package Type 64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 13 8285ES–AVR–02/2013 3.5 ATmega3250A Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel 5. See characterization specifications at 105°C. Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega3250A-AU ATmega3250A-AUR(4) 100A 100A Industrial (-40C to 85C) ATmega3250A-AN ATmega3250A-ANR(4) 100A 100A Extended (-40C to 105C)(5) Package Type 100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 14 8285ES–AVR–02/2013 3.6 ATmega3250PA Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel 5. See characterization specifications at 105°C. Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega3250PA-AU ATmega3250PA-AUR(4) 100A 100A Industrial (-40C to 85C) ATmega3250PA-AN ATmega3250PA-ANR(4) 100A 100A Extended (-40C to 105C)(5) Package Type 100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 15 8285ES–AVR–02/2013 3.7 ATmega645A Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega645A-AU ATmega645A-AUR(4) ATmega645A-MU ATmega645A-MUR(4) 64A 64A 64M1 64M1 Industrial (-40C to 85C) Package Type 64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 16 8285ES–AVR–02/2013 3.8 ATmega645P Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega645P-AU ATmega645P-AUR(4) ATmega645P-MU ATmega645P-MUR(4) 64A 64A 64M1 64M1 Industrial (-40C to 85C) Package Type 64A 64-Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 17 8285ES–AVR–02/2013 3.9 ATmega6450A Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega6450A-AU ATmega6450A-AUR(4) 100A 100A Industrial (-40C to 85C) Package Type 100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 18 8285ES–AVR–02/2013 3.10 ATmega6450P Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 295. 4. Tape & Reel Speed (MHz)(3) Power Supply Ordering Code(2) Package(1) Operation Range 20 1.8 - 5.5V ATmega6450P-AU ATmega6450P-AUR(4) 100A 100A Industrial (-40C to 85C) Package Type 100A 100-lead, 14 x 14 x 1.0mm, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 19 8285ES–AVR–02/2013 4. Packaging Information 4.1 64A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. REV. 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64A C 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. REV. 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64A C 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A2 A D1 D e E1 E B COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 20 8285ES–AVR–02/2013 4.2 64M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, H 64M1 2010-10-19 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D D2 5.20 5.40 5.60 8.90 9.00 9.10 E 8.9 0 9.00 9.10 E2 5.20 5.40 5.60 e 0.50 BSC L 0.35 0.40 0.45 Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. TOP VIEW SIDE VIEW BOTTOM VIEW D E Marked Pin# 1 ID SEATING PLANE A1 C A 0.08 C 1 2 3 K 1.25 1.40 1.55 E2 D2 b e Pin #1 Corner L Pin #1 Triangle Pin #1 Chamfer (C 0.30) Option A Option B Pin #1 Notch (0.20 R) Option C K K 2325 Orchard Parkway 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) San Jose, CA 95131 TITLE DRAWING NO. R REV. 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, H 64M1 2010-10-19 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D D2 5.20 5.40 5.60 8.90 9.00 9.10 E 8.9 0 9.00 9.10 E2 5.20 5.40 5.60 e 0.50 BSC L 0.35 0.40 0.45 Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. TOP VIEW SIDE VIEW BOTTOM VIEW D E Marked Pin# 1 ID SEATING PLANE A1 C A 0.08 C 1 2 3 K 1.25 1.40 1.55 E2 D2 b e Pin #1 Corner L Pin #1 Triangle Pin #1 Chamfer (C 0.30) Option B Pin #1 Notch (0.20 R) Option C K K 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 21 8285ES–AVR–02/2013 4.3 64MC TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com ZXC 64MC A 64MC, 64QFN (2-Row Staggered), 7 x 7 x 1.00 mm Body, 4.0 x 4.0 mm Exposed Pad, Quad Flat No Lead Package 10/3/07 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.28 C 0.20 REF D 6.90 7.00 7.10 D2 3.95 4.00 4.05 E 6.90 7.00 7.10 E2 3.95 4.00 4.05 eT – 0.65 – eR – 0.65 – K 0.20 – – (REF) L 0.35 0.40 0.45 y 0.00 – 0.075 SIDE VIEW TOP VIEW BOTTOM VIEW Note: 1. The terminal #1 ID is a Laser-marked Feature. Pin 1 ID D E A1 A y C eT/2 R0.20 0.40 B1 A1 B30 A34 b A8 B7 eT D2 B16 A18 B22 A25 E2 K (0.1) REF B8 A9 (0.18) REF L B15 A17 L eR A26 B23 eT ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 22 8285ES–AVR–02/2013 4.4 100A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 100A, 100-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, 0.5mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 100A D 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e 0.50 TYP Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08mm maximum. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [SUMMARY] 23 8285ES–AVR–02/2013 5. Errata 5.1 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Rev. G No known errata. 5.2 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Rev. A to F Not sampled. Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81) (3) 6417-0300 Fax: (+81) (3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 8285ES–AVR–02/2013 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 1. Product profile 1.1 General description PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package. NPN complement: PBSS4160T. 1.2 Features 􀂄 Low collector-emitter saturation voltage VCEsat 􀂄 High collector current capability IC and ICM 􀂄 High efficiency due to less heat generation 􀂄 Reduces Printed-Circuit Board (PCB) area required 􀂄 Cost-effective replacement for medium power transistors BCP52 and BCX52 1.3 Applications 􀂄 Major application segments: 􀂋 Automotive 􀂋 Telecom infrastructure 􀂋 Industrial 􀂄 Power management: 􀂋 DC-to-DC conversion 􀂋 Supply line switching 􀂄 Peripheral driver: 􀂋 Driver in low supply voltage applications (e.g. lamps and LEDs) 􀂋 Inductive load drivers (e.g. relays, buzzers and motors) 1.4 Quick reference data [1] Pulse test: tp ≤ 300 μs; δ ≤ 0.02. PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor Rev. 04 — 15 January 2010 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −60 V IC collector current - - −1 A ICM peak collector current t = 1 ms or limited by Tj(max) - - −2 A RCEsat collector-emitter saturation resistance IC = −1 A; IB = −100 mA [1] - 220 330 mΩ PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 2 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor 2. Pinning information 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 base 2 emitter 3 collector 1 2 3 006aab259 2 1 3 Table 3. Ordering information Type number Package Name Description Version PBSS5160T - plastic surface-mounted package; 3 leads SOT23 Table 4. Marking codes Type number Marking code[1] PBSS5160T *U6 Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −80 V VCEO collector-emitter voltage open base - −60 V VEBO emitter-base voltage open collector - −5 V IC collector current [1] - −0.9 A [2] - −1 A ICM peak collector current t = 1 ms or limited by Tj(max) - −2 A IB base current - −300 mA IBM peak base current tp ≤ 300 μs; δ ≤ 0.02 - −1 A PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 3 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2. [3] Operated under pulse conditions: duty cycle δ ≤ 20 %, pulse width tp ≤ 10 ms. Ptot total power dissipation Tamb ≤ 25 °C [1] - 270 mW [2] - 400 mW [1][3] - 1.25 W Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C (1) FR4 PCB, mounting pad for collector 1 cm2 (2) FR4 PCB, standard footprint Fig 1. Power derating curves Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit 0 40 80 160 Ptot (mW) (1) (2) 500 0 400 120 300 200 100 mle128 Tamb (°C) PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 4 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2. [3] Operated under pulse conditions: duty cycle δ ≤ 20 %, pulse width tp ≤ 10 ms. Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1]- - 465 K/W [2]- - 312 K/W [1][3]- - 100 K/W FR4 PCB, standard footprint Fig 2. Transient thermal impedance as a function of pulse duration; typical values mle127 103 102 10 1 10−5 10−4 10−3 10−2 10−1 1 Zth (K/W) tp 10 10 (s) 2 103 δ = 1 0.75 0.33 0.05 0.02 0.01 0 0.5 0.2 0.1 PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 5 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor 7. Characteristics [1] Pulse test: tp ≤ 300 μs; δ ≤ 0.02. Table 7. Characteristics Tamb = 25°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = −60 V; IE = 0 A - - −100 nA VCB = −60 V; IE = 0 A; Tj = 150 °C - - −50 μA ICES collector-emitter cut-off current VCE = −60 V; VBE = 0 V - - −100 nA IEBO emitter-base cut-off current VEB = −5 V; IC = 0 A - - −100 nA hFE DC current gain VCE = −5 V IC = −1 mA 200 350 - IC = −500 mA [1] 150 250 - IC = −1 A [1] 100 160 - VCEsat collector-emitter saturation voltage IC = −100 mA; IB = −1 mA - −110 −160 mV IC = −500 mA; IB = −50 mA - −120 −175 mV IC = −1 A; IB = −100 mA [1] - −220 −330 mV RCEsat collector-emitter saturation resistance IC = −1 A; IB = −100 mA [1] - 220 330 mΩ VBEsat base-emitter saturation voltage IC = −1 A; IB = −50 mA - −0.95 −1.1 V VBEon base-emitter turn-on voltage VCE = −5 V; IC = −1 A - −0.82 −0.9 V fT transition frequency VCE = −10 V; IC = −50 mA; f = 100 MHz 150 220 - MHz Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 1 MHz - 9 15 pF PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 6 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor VCE = −5 V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 3. DC current gain as a function of collector current; typical values Fig 4. Collector current as a function of collector-emitter voltage; typical values VCE = −5 V (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C IC/IB = 20 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 5. Base-emitter voltage as a function of collector current; typical values Fig 6. Base-emitter saturation voltage as a function of collector current; typical values mle124 0 600 200 400 −10−1 −1 −10 IC (mA) hFE −102 −103 −104 (1) (2) (3) mle125 0 −5 −2 0 −0.4 −0.8 −1.2 −1.6 −1 VCE (V) IC (A) −2 −3 −4 −24 −28 −32 −36 −40 −12 −8 −16 −4 IB (mA) = − 20 mle122 0 −1.2 −0.4 −0.8 −10−1 −1 −10 IC (mA) VBE (V) −102 −103 −104 (1) (3) (2) −0.2 −1.2 −0.4 −0.6 −0.8 −1 mle123 −10−1 −1 (1) −10 IC (mA) VBEsat (V) −102 −103 −104 (3) (2) PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 7 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C IC/IB = 10 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 7. Collector-emitter saturation voltage as a function of collector current; typical values Fig 8. Collector-emitter saturation voltage as a function of collector current; typical values Tamb = 25 °C (1) IC/IB = 100 (2) IC/IB = 50 IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 9. Collector-emitter saturation voltage as a function of collector current; typical values Fig 10. Collector-emitter saturation resistance as a function of collector current; typical values mle126 −10 −1 −10−1 −10−2 −10−1 −1 −10 IC (mA) VCEsat (V) −102 −103 −104 (3) (2) (1) mle119 −1 −10−1 −10−2 −10−3 −10−1 −1 −10 IC (mA) VCEsat (V) −102 −103 −104 (3) (2) (1) mle120 −10 −1 −10−1 −10−2 −10−1 −1 −10 IC (mA) VCEsat (V) −102 −103 −104 (1) (2) mle121 103 102 1 10−1 10 −10−1 −1 RCEsat (Ω) IC (mA) −10 −102 −103 −104 (3) (1) (2) PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 8 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor 8. Package outline 9. Packing information [1] For further information and the availability of packing methods, see Section 12. Fig 11. Package outline SOT23 (TO-236AB) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 PBSS5160T SOT23 4 mm pitch, 8 mm tape and reel -215 -235 PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 9 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor 10. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PBSS5160T_4 20100115 Product data sheet - PBSS5160T_N_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 1 “Quick reference data”: amended • Section 4 “Marking”: amended • Figure 4: updated • Figure 11: superseded by minimized package outline drawing • Section 9 “Packing information”: added • Section 11 “Legal information”: updated PBSS5160T_N_3 20080718 Product data sheet - PBSS5160T_2 PBSS5160T_2 20040527 Product specification - PBSS5160T_1 PBSS5160T_1 20030623 Product specification - - PBSS5160T_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 15 January 2010 10 of 11 NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor 11. Legal information 11.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 11.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 11.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 11.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 12. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. NXP Semiconductors PBSS5160T 60 V, 1 A PNP low VCEsat (BISS) transistor © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 January 2010 Document identifier: PBSS5160T_4 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 13. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 Packing information . . . . . . . . . . . . . . . . . . . . . 8 10 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 11.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 11.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Contact information. . . . . . . . . . . . . . . . . . . . . 10 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OSLON SSL Ceramic package - 80° radiation pattern Lead (Pb) Free Product - RoHS Compliant Released 2011-12-23 1 Besondere Merkmale •Gehäusetyp: SMT-Keramikgehäuse mit Silikonverguss und Linse •Typischer Lichtstrom: 108 lm bei 350 mA und bis zu 185 lm bei 700 mA (4500 K) •Besonderheit des Bauteils: Kompakte Lichtquelle für platzsparende Designs •Farbtemperatur: 4000 K bis 5000 K •Farbwiedergabeindex: 70 (typ.) •Abstrahlwinkel: 80° •Typischer optischer Wirkungsgrad: 96 lm/W bei 350 mA (4500 K) •Gruppierungsparameter: Lichtstrom, Farbort, Durchlassspannung •Lötmethode: Reflow-Löten •Vorbehandlung: nach JEDEC Level 2 •Gurtung: 12-mm Gurt mit 600/Rolle, ø180 mm •ESD-Festigkeit: ESD-sicher bis 8 kV nach JESD22-A114-D •Erweiterte Korrosionsfestigkeit: Details siehe Seite 14 •Testergebnis zur Lichtstromerhaltung nach IESNA-LM-80 verfügbar Anwendungen •Industriebeleuchtung •Lampen- und Leuchten-Retrofits •Akzentbeleuchtung Features •package: SMT ceramic package with silicon resin with lens •typical Luminous Flux: 108 lm at 350 mA and up to 185 lm at 700 mA (4500 K) •feature of the device: small size high-flux LED for slim designs •typ. color temperature: 4000 K to 5000 K •color reproduction index: 70 (typ.) •viewing angle: 80° •typical optical efficiency: 96 lm/W at 350 mA (4500 K) •grouping parameter: luminous flux, color coordinates, forward voltage •soldering methods: reflow soldering •preconditioning: acc. to JEDEC Level 2 •taping: 12-mm tape with 600/reel, ø180 mm •ESD-withstand voltage: up to 8 kV acc. to JESD22-A114-D •Superior Corrosion Robustness: details see page 14 •Lumen maintanance test report according to IESNA LM-80 available • Applications •Industrial Lighting •LED retrofits & fixtures •Accent lights 2011-12-23 2 Released LCW CQ7P.PC Bestellinformation Ordering Information Typ Type Farb- temperatur color temperature Lichtstrom 1) Seite 21 Luminous Flux1) page 21 IF = 350 mA ΦV(lm) Lichtstärke 2) Seite 21 Luminous Intensity2) page 21 IF = 350 mA IV (cd) Bestellnummer Ordering Code LCW CQ7P.PC-KTLP-5L7N-1 LCW CQ7P.PC-KULQ-5L7N-1 4000 K )97.0... 121.0 104.2... 130.0 61.0 (typ.) 66.0 (typ.)) Q65111A1483 Q65111A1484 LCW CQ7P.PC-KTLP-5J7K-1 LCW CQ7P.PC-KULQ-5J7K-1 4500 K 97.0... 121.0 104.2... 130.0 61.0 (typ.) 66.0 (typ.) Q65111A1482 Q65111A1462 LCW CQ7P.PC-KTLP-5H7I-1 LCW CQ7P.PC-KULQ-5H7I-1 5000 K 97.0... 121.0 104.2... 130.0 61.0 (typ.) 66.0 (typ.) Q65111A1481 Q65111A1484 Released LCW CQ7P.PC 2011-12-23 3 Anm.:Die oben genannten Typbezeichnungen umfassen die bestellbaren Selektionen. Diese bestehen aus wenigen Helligkeitsgruppen (siehe Seite 9 für nähere Informationen). Es wird nur eine einzige Helligkeitsgruppe pro Gurt geliefert. Z.B.: LCW CQ7P.PC-KTLP-5L7N-1 bedeutet, dass auf dem Gurt nur eine der Helligkeitsgruppen KT, KU oder LP enthalten ist. Um die Liefersicherheit zu gewährleisten, können einzelne Helligkeitsgruppen nicht bestellt werden. Gleiches gilt für die Farben, bei denen Farbortgruppen gemessen und gruppiert werden. Pro Gurt wird nur eine Farbortgruppe geliefert. Z.B.: LCW CQ7P.PC-KTLP-5L7N-1 bedeutet, dass auf dem Gurt nur eine der Farbortgruppen -5L bis -7N enthalten ist (siehe Seite 6 für nähere Information). Um die Liefersicherheit zu gewährleisten, können einzelne Farbortgruppen nicht bestellt werden. Gleiches gilt für die LEDs, bei denen die Durchlassspannungsgruppen gemessen und gruppiert werden. Pro Gurt wird nur eine Durchlassspannungsgruppe geliefert. Z.B.: LCW CQ7P.PC-KTLP-5L7N-1 bedeutet, dass nach Durchlassspannung gruppiert wird. Auf einem Gurt ist nur eine der Durchlasspannungsgruppen -3, -4 oder -5 enthalten (siehe Seite 9 für nähere Information). Um die Liefersicherheit zu gewährleisten, können einzelne Durchlassspannungsgruppen nicht direkt bestellt werden. Note:The above Type Numbers represent the order groups which include only a few brightness groups (see page 9for explanation). Only one group will be shipped on each reel (there will be no mixing of two groups on each reel). E.g.LCW CQ7P.PC-KTLP-5L7N-1 means that only one group KT, KU or LP will be shippable for any one reel. In order to ensure availability, single brightness groups will not be orderable. In a similar manner for colors where chromaticity coordinate groups are measured and binned, single chromaticity coordinate groups will be shipped on any one reel. E.g. LCW CQ7P.PC-KTLP-5L7N-1 means that only 1 chromaticity coordinate group -5L to -7N will be shippable (see page 6 for explanation). In order to ensure availability, single chromaticity coordinate groups will not be orderable. In a similar manner for LED, where forward voltage groups are measured and binned, single forward voltage groups will be shipped on any one reel. E.g. LCW CQ7P.PC-KTLP-5L7N-1 means that only 1 forward voltage group -3, -4 or -5 will be shippable. In order to ensure availability, single forward voltage groups will not be orderable(see page 9 for explanation). 2011-12-23 4 Released LCW CQ7P.PC Grenzwerte Maximum Ratings Bezeichnung Parameter Symbol Symbol Wert Value Einheit Unit Betriebstemperatur Operating temperature range Top – 40 … + 120 °C Lagertemperatur Storage temperature range Tstg – 40 … + 120 °C Sperrschichttemperatur Junction temperature Tj 135 °C Durchlassstrom(min.) Forward current(max.) (TS=25°C) IF IF 100800 mA mA Stoßstrom Surge current t ≤ 50 ms, D = 0.016, TS=25°C IFM 2000 mA Reverse Current* Sperrstrom*(max.) IR 200 mA * A minimum of 10 h of reverse operation is permissable in total. Eine Gesamtbetriebszeit von wenigstens 10 h in Sperrrichtung ist gewährleistet. Released LCW CQ7P.PC 2011-12-23 5 Kennwerte Characteristics (TS = 25 °C) Bezeichnung Parameter Symbol Symbol WertValue Einheit Unit Farbtemperatur 2) Seite 21)(min.) Color temperature 2) page 21 IF = 350mA (max.) T T 40005000 K K Abstrahlwinkel bei 50 % ΙV (Vollwinkel)(typ.) Viewing angle at 50 % ΙV 2ϕ 80 Grad deg. Durchlassspannung 4) Seite 21)(min.) Forward voltage4) page 21(typ.) IF = 350mA (max.) VF VF VF 2.753.23.5 V V V Reverse Voltage3) page 21) Sperrspannung 3) Seite 23 IR = 20 mA(max.) VR 1.2 V Wärmewiderstand Thermal resistance Sperrschicht/Lötpad(typ.) Junction/solder point(max.) Rth el JS Rth el JS 79.4* K/W K/W *Rth(max) basiert auf statistischen Werten Rth(max) is based on statistic values 2011-12-23 6 Released LCW CQ7P.PC Farbortgruppen3) Seite 21 Chromaticity Coordinate Groups3) page 21 OHA04564520530540550560570580590600610620630000.10.20.30.40.50.60.70.80.90.10.20.30.40.50.60.70.80.9510500490450CxCyCxE4804604700.330.340.350.360.370.380.390.400.410.290.300.310.320.330.340.350.360.370.380.390.400.410.420.430.444H5678IJKLMN456785000 K4500 K4000 KCy Released LCW CQ7P.PC 2011-12-23 7 Color temperature 4000 K Farbtemperatur 4000 K Gruppe Group Cx Cy Gruppe Group Cx Cy Gruppe Group Cx Cy 4L 0.365 0.348 4M 0.372 0.352 4N 0.379 0.356 0.367 0.358 0.375 0.362 0.382 0.367 0.375 0.362 0.382 0.367 0.390 0.372 0.372 0.352 0.379 0.356 0.386 0.361 5L 0.367 0.358 5M 0.375 0.362 5N 0.382 0.367 0.369 0.368 0.377 0.373 0.385 0.376 0.377 0.373 0.385 0.378 0.393 0.383 0.375 0.362 0.382 0.367 0.390 0.372 6L 0.369 0.368 6M 0.377 0.373 6N 0.385 0.378 0.371 0.378 0.380 0.383 0.388 0.388 0.380 0.383 0.388 0.388 0.397 0.393 0.377 0.373 0.385 0.376 0.393 0.383 7L 0.371 0.378 7M 0.380 0.383 7N 0.388 0.388 0.374 0.387 0.383 0.393 0.392 0.399 0.383 0.393 0.392 0.399 0.401 0.404 0.380 0.383 0.388 0.388 0.397 0.393 8L 0.374 0.387 8M 0.383 0.393 8N 0.392 0.399 0.376 0.397 0.385 0.403 0.395 0.409 0.385 0.403 0.395 0.409 0.404 0.415 0.383 0.393 0.392 0.399 0.401 0.404 Color temperature 4500 K Farbtemperatur 4500 K Gruppe Group Cx Cy Gruppe Group Cx Cy Gruppe Group Cx Cy 4J 0.350 0.337 8J 0.355 0.374 7K 0.363 0.371 0.351 0.347 0.356 0.383 0.364 0.381 0.359 0.352 0.366 0.390 0.374 0.387 0.357 0.343 0.364 0.381 0.371 0.378 5J 0.351 0.347 4K 0.357 0.343 8K 0.364 0.381 0.352 0.356 0.359 0.352 0.366 0.390 0.361 0.362 0.367 0.358 0.376 0.397 0.359 0.352 0.365 0.348 0.374 0.387 6J 0.352 0.356 5K 0.359 0.352 0.354 0.365 0.361 0.362 0.363 0.371 0.369 0.368 0.361 0.362 0.367 0.358 7J 0.354 0.365 6K 0.361 0.362 0.355 0.374 0.363 0.371 0.364 0.381 0.371 0.378 0.363 0.371 0.369 0.368 2011-12-23 8 Released LCW CQ7P.PC Color temperature 5000 K Farbtemperatur 5000 K Gruppe Group Cx Cy Gruppe Group Cx Cy Gruppe Group Cx Cy 4H 0.336 0.329 8H 0.338 0.362 7I 0.346 0.360 0.337 0.337 0.338 0.370 0.346 0.369 0.344 0.343 0.347 0.378 0.355 0.376 0.343 0.334 0.346 0.369 0.354 0.367 5H 0.337 0.337 4I 0.343 0.334 8I 0.346 0.369 0.337 0.345 0.344 0.343 0.347 0.378 0.345 0.352 0.352 0.349 0.356 0.385 0.344 0.343 0.350 0.340 0.355 0.376 6H 0.337 0.345 5I 0.344 0.343 0.337 0.353 0.345 0.352 0.346 0.360 0.353 0.358 0.345 0.352 0.352 0.349 7H 0.337 0.353 6I 0.345 0.352 0.338 0.362 0.346 0.360 0.346 0.369 0.354 0.367 0.346 0.360 0.353 0.358 Released LCW CQ7P.PC 2011-12-23 9 Durchlaßspannungsgruppen6) Seite 21 Forward Voltage Groups6) page 21 Gruppe Group DurchlaßspannungForward voltage Einheit Unit min. max. 3 2.75 3.0 V 4 3.0 3.25 V 5 3.25 3.5 V Helligkeits-Gruppierungsschema Brightness Groups Helligkeitsgruppe Brightness Group Lichtstrom1) Seite 21 Luminous Flux1) page 21 ΦV (lm) Lichtstärke2) Seite 21 Luminous Intensity2) page 21 IV (cd) KS KT KU LP LQ 89.2 ...97.0 97.0 ...104.2 104.2 ...112.0 112.0 ...121.0 121.0 ...130.0 52.0 (typ.) 56.0 (typ.) 61.0 (typ.) 66.0 (typ.) 70.0 (typ.) Anm.:Die Standardlieferform von Serientypen beinhaltet eine Familiengruppe. Diese besteht aus nur wenigen Helligkeitsgruppen. Einzelne Helligkeitsgruppen sind nicht bestellbar. Note:The standard shipping format for serial types includes a family group of only a few individual brightness groups. Individual brightness groups cannot be ordered. Gruppenbezeichnung auf Etikett Group Name on Label Beispiel: KT-5L-3 Example: KT-5L-3 Helligkeitsgruppe Brightness Group Farbortgruppe Chromaticity Coordinate Group Durchlassspannung Forward Voltage KT 5L 3 Anm.:In einer Verpackungseinheit / Gurt ist immer nur eine Helligkeitsgruppe enthalten. Note:No packing unit / tape ever contains more than one brightness group. 2011-12-23 10 Released LCW CQ7P.PC Relative spektrale Emission2) Seite 21 Relative Spectral Emission2) page 21 V(λ) = spektrale Augenempfindlichkeit / Standard eye response curve Φrel = f (λ); TS = 25 °C; IF = 350 mA Abstrahlcharakteristik2) Seite 21 Radiation Characteristic2) page 21 Ιrel = f (ϕ); TS = 25 °C 04004020500600%8060relΦ100700nmλ800OHL04583λV OHL043250°20°40°60°80°100°120°0.40.60.81.0100°90°80°70°60°50°0°10°20°30°40°00.20.40.60.81.0ϕ Released LCW CQ7P.PC 2011-12-23 11 Durchlassstrom2) Seite 21 Forward Current2) page 21 IF = f (VF); TS = 25 °C Farbortverschiebung2) Seite 21 Chromaticity Coordinate Shift2) page 21 x, y = f (IF); TS = 25 °C Relative Lichtstrom2) Seite 21 Relative Luminous Flux2) page 21 ΦV/ΦV(350 mA) = f (IF); TS = 25 °C OHL04578FIVmA2.8FV3.03.23.43.63.8200400600800 -0.008OHL04579Cx, CyFICxCymA200400600800-0.006-0.004-0.00200.0020.006 OHL04581IFΦ(350 mA)VVΦ0mA2004006008000.51.01.52.0 Released LCW CQ7P.PC 2011-12-23 12 Relative Vorwärtsspannung2) Seite 21 Relative Forward Voltage2) page 21 ΔVF = VF - VF(25 °C) = f (Tj); IF = 350 mA Farbortverschiebung2) Seite 21 Chromaticity Coordinate Shift2) page 21 x, y = f (Tj); IF = 350 mA Relative Lichtstrom2) Seite 21 Relative Luminous Flux2) page 21 ΦV/ΦV(25 °C) = f (Tj); IF = 350 mA -40-0.3°CTjOHL04428VFVΔ-20020406080120-0.2-0.100.10.20.3 OHL04580Cx, Cy-40°CjT-200204060801200.30CyCx0.320.340.360.380.40 OHL04582-40°CjT-200204060801200VV(25 °C)ΦΦ0.20.40.60.81.2 Released LCW CQ7P.PC 2011-12-23 13 Maximal zulässiger Durchlassstrom Max. Permissible Forward Current IF = f (TS) Zulässige Impulsbelastbarkeit IF = f (tp) Permissible Pulse Handling Capability Duty cycle D = parameter, TS = 25 °C Zulässige Impulsbelastbarkeit IF = f (tp) Permissible Pulse Handling Capability Duty cycle D = parameter, TS = 85 °C 020406080100120140TS [°C]0100200300400500600700800ΙF [mA]Do not use current below 100 mA 10100-2-3-4-5101010FIAPt=DT210-110tp10s10OHL04611TtPIF0.050.20.10.510.020.01D0.20.40.60.81.01.21.41.61.82.20.005= 10100-2-3-4-5101010FIAPt=DT210-110tp10s10OHL04611TtPIF0.050.20.10.510.020.01D0.20.40.60.81.01.21.41.61.82.20.005= 2011-12-23 14 Released LCW CQ7P.PC Maßzeichnung5) Seite 21 Package Outlines5) page 21 Anm.:Die LED enthält ein ESD-Bauteil, das parallel zum Chip geschalten ist. Note:LED is protected by ESD device which is connected in parallel to LED-Chip. Anm.:Das Gehäuse ist für Ultraschallreinigung nicht geeignet Note:Package not suitable for ultra sonic cleaning Kathodenkennung:Markierung Cathode mark:mark Gewicht / Approx. weight:2.5 mg Korrosionsfestigkeit besser als EN 60068-2-60 (method 4): mit erweitertem Korrosionstest: 40°C / 90%rh / 15ppm H2S / 336h Corrosion robustness better than EN 60068-2-60 (method 4): with enhanced corrosion test: 40°C / 90%rh / 15ppm H2S / 336h Released LCW CQ7P.PC 2011-12-23 15 Gurtung / Polarität und Lage5) Seite 21Verpackungseinheit 600/Rolle, ø180 mm Method of Taping / Polarity and Orientation5) page 21Packing unit 600/reel, ø180 mm 2011-12-23 16 Released LCW CQ7P.PC Empfohlenes Lötpaddesign5) Seite 21 Reflow Löten Recommended Solder Pad5) page 21 Reflow Soldering Anm.:Um eine verbesserte Lötstellenkontaktierung zu erreichen, empfehlen wir, unter Standard- stickstoffatmosphäre zu löten. Weitere Informationen finden Sie in der Applikationsschrift „Handling and Processing Details for Ceramic LEDs“ Note:For superior solder joint connectivity results we recommend soldering under standard nitrogen atmosphere. For further information please refer to our Application Note „Handling and Processing Details for Ceramic LEDs“ Released LCW CQ7P.PC 2011-12-23 17 LötbedingungenVorbehandlung nach JEDEC Level 2 Soldering ConditionsPreconditioning acc. to JEDEC Level 2 Reflow Lötprofil für bleifreies Löten(nach J-STD-020D.01) Reflow Soldering Profile for lead free soldering(acc. to J-STD-020D.01) Profile Feature Pb-Free (SnAgCu) Assembly Recommendation Max. Ratings Ramp-up Rate to Preheat*) 25°C to 150°C 2 K / s 3 K/ s Time ts from TSmin to TSmax (150°C to 200°C 100 s min. 60 s max. 120 s Ramp-up Rate to Peak*) 180°C to TP 2 K / s 3 K / s Liquidus Temperature TL 217°C Time tL above TL 80 s max. 100 s Peak Temperature TP 245 °C max. 260 °C Time tP within 5°C of the specified peak temperature TP - 5K 20 s min. 10 s max. 30 s Ramp-down Rate* TP to 100°C 3 K / s 6 K / s maximum Time 25°C to Peak temperature max. 8 min. All temperatures refer to the center of the package, measured on the top of the component * slope calculation ΔT/Δt: Δt max. 5 sec; fulfillment for the whole T-range 00sOHA045255010015020025030050100150200250300tT°CSttPtTp240 °C217 °C245 °C25 °CL 2011-12-23 18 Released LCW CQ7P.PC Barcode-Produkt-Etikett (BPL) Barcode-Product-Label (BPL) Gurtverpackung Tape and Reel Tape dimensions in mm (inch) W P0 P1 P2 D0 E F 4 ± 0.1 (0.157 ± 0.004) 8 ± 0.1 (0.315 ± 0.004) 2 ± 0.05 (0.079 ± 0.002) 1.5 + 0.1 (0.059 + 0.004) 1.75 ± 0.1 (0.069 ± 0.004) 5.5 ± 0.05 (0.217 ± 0.002) Reel dimensions in mm (inch) A W Nmin W1 W2 max 180 (7) 12 (0.472) 60 (2.362) 12.4 + 2 (0.488 + 0.079) 18.4 (0.724) OHA04563(G) GROUP:1234567890(1T) LOT NO:(9D) D/C:1234(X) PROD NO:123456789(6P) BATCH NO:1234567890LX XXXXRoHS CompliantBIN1: XX-XX-X-XXX-XML2Temp ST260 °C RPack: R18DEMY 022B_R999_1880.1642 R9999(Q)QTY:SemiconductorsOSRAM OptoXX-XX-X-X D02PP01PWFEDirection of unreelingNW12WAOHAY0324LabelGurtvorlauf:Leader:Trailer:Gurtende:13.0Direction of unreeling±0.25160 mm160 mm400 mm400 mm 12+ 0.3– 0.1 Released LCW CQ7P.PC 2011-12-23 19 Trockenverpackung und Materialien Dry Packing Process and Materials Anm.:Feuchteempfindliche Produkte sind verpackt in einem Trockenbeutel zusammen mit einem Trockenmittel und einer Feuchteindikatorkarte Bezüglich Trockenverpackung finden Sie weitere Hinweise im Internet und in unserem Short Form Catalog im Kapitel “Gurtung und Verpackung” unter dem Punkt “Trockenverpackung”. Hier sind Normenbezüge, unter anderem ein Auszug der JEDEC-Norm, enthalten. Note:Moisture-sensitve product is packed in a dry bag containing desiccant and a humidity card. Regarding dry pack you will find further information in the internet and in the Short Form Catalog in chapter “Tape and Reel” under the topic “Dry Pack”. Here you will also find the normative references like JEDEC. Kartonverpackung und Materialien Transportation Packing and Materials Dimensions of transportation box in mm (inch) Breite / Width Länge / length Höhe / height 200 ±5 (7,874 ±0,1968) 200 ±5 (7,874 ±0,1968) 30 ±5 (1,1811 ±0,1968) OHA00539OSRAMMoisture-sensitive label or printBarcode labelDesiccantHumidity indicatorBarcode labelOSRAMPlease check the HIC immidiately afterbag opening.Discard if circles overrun.Avoid metal contact.WETDo not eat.Comparatorcheck dotparts still adequately dry.examine units, if necessaryexamine units, if necessary5%15%10%bake unitsbake unitsIf wet,change desiccantIf wet,Humidity IndicatorMIL-I-8835If wet,Moisture Level 3Floor time 168 HoursMoisture Level6Floor time 6 Hoursa) Humidity Indicator Card is > 10% when read at 23 °C ± 5 °C,orreflow, vapor-phasereflow, or equivalent processing (peak package2. After this bag is opened,devicesthat will be subjected to infrared1. Shelflife in sealed bag: 24 months at < 40 °C and < 90% relative humidity (RH).Moisture Level 5aat factory conditions of(if blank, sealdate isidentical with date code).a)Mounted withinb) Stored atbody temp.3.Devicesrequire baking, before mounting, if:BagsealdateMoisture Level1MoistureLevel2Moisture Level 2a4. If bakingis required, b) 2aor2b isnot met.Date and time opened:reference IPC/JEDEC J-STD-033 for bake procedure.Floortime see belowIfblank, see bar code labelFloor time > 1 YearFloor time 1 YearFloortime 4 Weeks10% RH._ 10% when read at 23 °C ± 5 °C, orreflow, vapor-phase reflow, or equivalent processing (peak package2. After this bag is opened, devices that will be subjected to infrared1. Shelf life in sealed bag: 24 months at < 40 °C and < 90% relative humidity (RH).Moisture Level 5aat factory conditions of(if blank, seal date is identical with date code).a) Mounted withinb) Stored atbody temp.3. Devices require baking, before mounting, if:Bag seal dateMoisture Level 1Moisture Level 2Moisture Level 2a4. If baking is required, b) 2a or 2b is not met.Date and time opened:reference IPC/JEDEC J-STD-033 for bake procedure.Floor time see belowIf blank, see bar code labelFloor time > 1 YearFloor time 1 YearFloor time 4 Weeks10% RH._ 470 nF) must be connected to the LCDCAP pin as shown in Figure 23-2 on page 236. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. 9 8018PS–AVR–08/10 ATmega169P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 10 8018PS–AVR–08/10 ATmega169P 5. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved – – – – – – – – (0xFE) LCDDR18 – – – – – – – SEG324 250 (0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 250 (0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 250 (0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 250 (0xFA) Reserved – – – – – – – – (0xF9) LCDDR13 – – – – – – – SEG224 250 (0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 250 (0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 250 (0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 250 (0xF5) Reserved – – – – – – – – (0xF4) LCDDR8 – – – – – – – SEG124 250 (0xF3) LCDDR7 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 250 (0xF2) LCDDR6 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 250 (0xF1) LCDDR5 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 250 (0xF0) Reserved – – – – – – – – (0xEF) LCDDR3 – – – – – – – SEG024 250 (0xEE) LCDDR2 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 250 (0xED) LCDDR1 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG09 SEG008 250 (0xEC) LCDDR0 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 250 (0xEB) Reserved – – – – – – – – (0xEA) Reserved – – – – – – – – (0xE9) Reserved – – – – – – – – (0xE8) Reserved – – – – – – – – (0xE7) LCDCCR LCDDC2 LCDDC1 LCDDC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 249 (0xE6) LCDFRR – LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 247 (0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 – LCDPM2 LCDPM1 LCDPM0 246 (0xE4) LCDCRA LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL 245 (0xE3) Reserved – – – – – – – – (0xE2) Reserved – – – – – – – – (0xE1) Reserved – – – – – – – – (0xE0) Reserved – – – – – – – – (0xDF) Reserved – – – – – – – – (0xDE) Reserved – – – – – – – – (0xDD) Reserved – – – – – – – – (0xDC) Reserved – – – – – – – – (0xDB) Reserved – – – – – – – – (0xDA) Reserved – – – – – – – – (0xD9) Reserved – – – – – – – – (0xD8) Reserved – – – – – – – – (0xD7) Reserved – – – – – – – – (0xD6) Reserved – – – – – – – – (0xD5) Reserved – – – – – – – – (0xD4) Reserved – – – – – – – – (0xD3) Reserved – – – – – – – – (0xD2) Reserved – – – – – – – – (0xD1) Reserved – – – – – – – – (0xD0) Reserved – – – – – – – – (0xCF) Reserved – – – – – – – – (0xCE) Reserved – – – – – – – – (0xCD) Reserved – – – – – – – – (0xCC) Reserved – – – – – – – – (0xCB) Reserved – – – – – – – – (0xCA) Reserved – – – – – – – – (0xC9) Reserved – – – – – – – – (0xC8) Reserved – – – – – – – – (0xC7) Reserved – – – – – – – – (0xC6) UDR0 USART0 I/O Data Register 190 (0xC5) UBRRH0 USART0 Baud Rate Register High 194 (0xC4) UBRRL0 USART0 Baud Rate Register Low 194 (0xC3) Reserved – – – – – – – – (0xC2) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 190 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 190 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190 11 8018PS–AVR–08/10 ATmega169P (0xBF) Reserved – – – – – – – – (0xBE) Reserved – – – – – – – – (0xBD) Reserved – – – – – – – – (0xBC) Reserved – – – – – – – – (0xBB) Reserved – – – – – – – – (0xBA) USIDR USI Data Register 207 (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 207 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 208 (0xB7) Reserved – – – – – – – (0xB6) ASSR – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB 156 (0xB5) Reserved – – – – – – – – (0xB4) Reserved – – – – – – – – (0xB3) OCR2A Timer/Counter2 Output Compare Register A 155 (0xB2) TCNT2 Timer/Counter2 (8-bit) 155 (0xB1) Reserved – – – – – – – – (0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 153 (0xAF) Reserved – – – – – – – – (0xAE) Reserved – – – – – – – – (0xAD) Reserved – – – – – – – – (0xAC) Reserved – – – – – – – – (0xAB) Reserved – – – – – – – – (0xAA) Reserved – – – – – – – – (0xA9) Reserved – – – – – – – – (0xA8) Reserved – – – – – – – – (0xA7) Reserved – – – – – – – – (0xA6) Reserved – – – – – – – – (0xA5) Reserved – – – – – – – – (0xA4) Reserved – – – – – – – – (0xA3) Reserved – – – – – – – – (0xA2) Reserved – – – – – – – – (0xA1) Reserved – – – – – – – – (0xA0) Reserved – – – – – – – – (0x9F) Reserved – – – – – – – – (0x9E) Reserved – – – – – – – – (0x9D) Reserved – – – – – – – – (0x9C) Reserved – – – – – – – – (0x9B) Reserved – – – – – – – – (0x9A) Reserved – – – – – – – – (0x99) Reserved – – – – – – – – (0x98) Reserved – – – – – – – – (0x97) Reserved – – – – – – – – (0x96) Reserved – – – – – – – – (0x95) Reserved – – – – – – – – (0x94) Reserved – – – – – – – – (0x93) Reserved – – – – – – – – (0x92) Reserved – – – – – – – – (0x91) Reserved – – – – – – – – (0x90) Reserved – – – – – – – – (0x8F) Reserved – – – – – – – – (0x8E) Reserved – – – – – – – – (0x8D) Reserved – – – – – – – – (0x8C) Reserved – – – – – – – – (0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 132 (0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 132 (0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 132 (0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 132 (0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 133 (0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 133 (0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 132 (0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 132 (0x83) Reserved – – – – – – – – (0x82) TCCR1C FOC1A FOC1B – – – – – – 131 (0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 130 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 128 (0x7F) DIDR1 – – – – – – AIN1D AIN0D 214 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 232 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 12 8018PS–AVR–08/10 ATmega169P (0x7D) Reserved – – – – – – – – (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 228 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 213, 232 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 230 (0x79) ADCH ADC Data Register High byte 231 (0x78) ADCL ADC Data Register Low byte 231 (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved – – – – – – – – (0x74) Reserved – – – – – – – – (0x73) Reserved – – – – – – – – (0x72) Reserved – – – – – – – – (0x71) Reserved – – – – – – – – (0x70) TIMSK2 – – – – – – OCIE2A TOIE2 156 (0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 133 (0x6E) TIMSK0 – – – – – – OCIE0A TOIE0 104 (0x6D) Reserved – – – – – – – – (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 63 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 64 (0x6A) Reserved – – – – – – – – (0x69) EICRA – – – – – – ISC01 ISC00 62 (0x68) Reserved – – – – – – – – (0x67) Reserved – – – – – – – – (0x66) OSCCAL Oscillator Calibration Register 38 (0x65) Reserved – – – – – – – – (0x64) PRR – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC 45 (0x63) Reserved – – – – – – – – (0x62) Reserved – – – – – – – – (0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 38 (0x60) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 54 0x3F (0x5F) SREG I T H S V N Z C 13 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 15 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 15 0x3C (0x5C) Reserved 0x3B (0x5B) Reserved 0x3A (0x5A) Reserved 0x39 (0x59) Reserved 0x38 (0x58) Reserved 0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 293 0x36 (0x56) Reserved – – – – – – – – 0x35 (0x55) MCUCR JTD – – PUD – – IVSEL IVCE 60, 88, 278 0x34 (0x54) MCUSR – – – JTRF WDRF BORF EXTRF PORF 278 0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE 45 0x32 (0x52) Reserved – – – – – – – – 0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 257 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 213 0x2F (0x4F) Reserved – – – – – – – – 0x2E (0x4E) SPDR SPI Data Register 167 0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 166 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 165 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 29 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 29 0x29 (0x49) Reserved – – – – – – – – 0x28 (0x48) Reserved – – – – – – – – 0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 104 0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 104 0x25 (0x45) Reserved – – – – – – – – 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 102 0x23 (0x43) GTCCR TSM – – – – – PSR2 PSR10 137, 157 0x22 (0x42) EEARH – – – – – – – EEAR8 27 0x21 (0x41) EEARL EEPROM Address Register Low Byte 27 0x20 (0x40) EEDR EEPROM Data Register 27 0x1F (0x3F) EECR – – – – EERIE EEMWE EEWE EERE 27 0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 29 0x1D (0x3D) EIMSK PCIE1 PCIE0 – – – – – INT0 62 0x1C (0x3C) EIFR PCIF1 PCIF0 – – – – – INTF0 63 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 13 8018PS–AVR–08/10 ATmega169P Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 0x1B (0x3B) Reserved – – – – – – – – 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – – OCF2A TOV2 156 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 134 0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 105 0x14 (0x34) PORTG – – PORTG5 PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 90 0x13 (0x33) DDRG – – DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 90 0x12 (0x32) PING – – PING5 PING4 PING3 PING2 PING1 PING0 90 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 90 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 90 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 90 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 89 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 89 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 90 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 89 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 89 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 89 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 89 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 89 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 89 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 88 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 88 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 88 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 88 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 88 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 88 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 14 8018PS–AVR–08/10 ATmega169P 6. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← k None 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 CALL k Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 15 8018PS–AVR–08/10 ATmega169P BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1 V 1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 Mnemonics Operands Description Operation Flags #Clocks 16 8018PS–AVR–08/10 ATmega169P PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks 17 8018PS–AVR–08/10 ATmega169P 7. Ordering Information Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 28-1 on page 331 and Figure 28-2 on page 332. Speed (MHz)(3) Power Supply Ordering Code Package(1)(2) Operation Range 8 1.8V - 5.5V ATmega169PV-8AU ATmega169PV-8MU ATmega169PV-8MCH 64A 64M1 64MC Industrial (-40°C to 85°C) 16 2.7V - 5.5V ATmega169P-16AU ATmega169P-16MU ATmega169P-16MCH 64A 64M1 64MC Industrial (-40°C to 85°C) Package Type 64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 64M1 64-pad, 9 × 9 × 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 64MC 64-lead (2-row Staggered), 7 × 7 × 1.0 mm body, 4.0 × 4.0 mm Exposed Pad, Quad Flat No-Lead Package (QFN) 18 8018PS–AVR–08/10 ATmega169P 8. Packaging Information 8.1 64A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64A B 10/5/2001 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP 19 8018PS–AVR–08/10 ATmega169P 8.2 64M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 64M1 G 5/25/06 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D D2 5.20 5.40 5.60 8.90 9.00 9.10 E 8.9 0 9.00 9.10 E2 5.20 5.40 5.60 e 0.50 BSC L 0.35 0.40 0.45 Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. TOP VIEW SIDE VIEW BOTTOM VIEW D E Marked Pin# 1 ID SEATING PLANE A1 C A 0.08 C 1 2 3 K 1.25 1.40 1.55 E2 D2 b e Pin #1 Corner L Pin #1 Triangle Pin #1 Chamfer (C 0.30) Option A Option B Pin #1 Notch (0.20 R) Option C K K 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) 20 8018PS–AVR–08/10 ATmega169P 8.3 64MC TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com ZXC 64MC A 64MC, 64QFN (2-Row Staggered), 7 x 7 x 1.00 mm Body, 4.0 x 4.0 mm Exposed Pad, Quad Flat No Lead Package 10/3/07 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.28 C 0.20 REF D 6.90 7.00 7.10 D2 3.95 4.00 4.05 E 6.90 7.00 7.10 E2 3.95 4.00 4.05 eT – 0.65 – eR – 0.65 – K 0.20 – – (REF) L 0.35 0.40 0.45 y 0.00 – 0.075 SIDE VIEW TOP VIEW BOTTOM VIEW Note: 1. The terminal #1 ID is a Laser-marked Feature. Pin 1 ID D E A1 A y C eT/2 R0.20 0.40 B1 A1 B30 A34 b A8 B7 eT D2 B16 A18 B22 A25 E2 K (0.1) REF B8 A9 (0.18) REF L B15 A17 L eR A26 B23 eT 21 8018PS–AVR–08/10 ATmega169P 9. Errata 9.1 ATmega169P Rev. G No known errata. 9.2 ATmega169P Rev. A to F Not sampled. 22 8018PS–AVR–08/10 ATmega169P 10. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 10.1 Rev. 8018P 08/10 10.2 Rev. 8018O 10/09 10.3 Rev. 8018N 08/09 10.4 Rev. 8018M 07/09 10.5 Rev. L 08/08 10.6 Rev. K 06/08 1. Status changed to active 2. EEPROM minimum wait delay, Table 27-15 on page 312, has been changed from 9.0 ms to 3.6 ms 3. Datasheet layout and technical terminology updated 1. Changed datasheet status to “Mature” 2. Added Capacitance for Low-frequency Crystal Oscillator, Table 8-5 on page 33. 1. Updated ”Ordering Information” on page 17, MCU replaced by MCH. 1. Updated the last page with new Atmel’s addresses. 1. Updated package information in ”Features” on page 1. 2. Added ”Pinout - DRQFN” on page 3: • The Staggered QFN is named Dual Row QFN (DRQFN). 1. Updated package information in ”Features” on page 1. 2. Removed “Disclaimer” from section ”Pin Configurations” on page 2 3. Added ”64MC (DRQFN) Pinout ATmega169P” on page 3 4. Added ”Data Retention” on page 9. 5. Updated ”Stack Pointer” on page 13. 6. Updated ”Low-frequency Crystal Oscillator” on page 34. 7. Updated ”USART Register Description” on page 194, register descriptions and tables. 8. Updated ”UCSRnB – USART Control and Status Register n B” on page 195. 9. Updated VIL2 in ”DC Characteristics” on page 329, by removing 0.2VCC from the table. 23 8018PS–AVR–08/10 ATmega169P 10.7 Rev. J 08/07 10.8 Rev. I 11/06 10.9 Rev. H 09/06 10.10 Rev. G 08/06 10.11 Rev. F 08/06 10.12 Rev. E 08/06 10. Replaced Figure 29-36 on page 357 by a correct one. 11. Updated ”Ordering Information” on page 17. 12. Added ”64MC” on page 20 package to ”Packaging Information” on page 18. 1. Updated ”Features” on page 1. 2. Added ”Minimizing Power Consumption” on page 237 in the LCD section. 3. Updated ”System and Reset Characteristics” on page 333. 1. Updated ”Low-frequency Crystal Oscillator” on page 34. 2. Updated Table 8-8 on page 35, Table 8-9 on page 35, Table 8-10 on page 35, Table 28-7 on page 336. 3. Updated note in Table 28-7 on page 336. 1. All characterization data moved to ”Electrical Characteristics” on page 329. 2. Updated ”Calibrated Internal RC Oscillator” on page 32. 3. Updated ”System Control and Reset” on page 47. 4. Added note to Table 27-16 on page 314. 5. Updated ”LCD Controller Characteristics” on page 337. 1. Updated ”LCD Controller Characteristics” on page 337. 1. Updated ”DC Characteristics” on page 329. 2. Updated Table 13-19 on page 84. 1. Updated ”Low-frequency Crystal Oscillator” on page 34. 2. Updated ”Device Identification Register” on page 260. 3. Updated ”Signature Bytes” on page 299. 4. Added Table 27-6 on page 299. 24 8018PS–AVR–08/10 ATmega169P 10.13 Rev. D 07/06 10.14 Rev. C 06/06 10.15 Rev. B 04/06 10.16 Rev. A 03/06 1. Updated ”Register Description for I/O-Ports” on page 88. 2. Updated ”Fast PWM Mode” on page 97. 3. Updated ”Fast PWM Mode” on page 120. 4. Updated Table 14-2 on page 102, Table 14-4 on page 103, Table 15-3 on page 129, Table 15-4 on page 130, Table 17-2 on page 153 and Table 17-4 on page 154. 5 Updated ”UCSRnC – USART Control and Status Register n C” on page 196. 6. Updated Features in ”USI – Universal Serial Interface” on page 199. 7. Added ”Clock speed considerations.” on page 206. 8. Updated Features in ”LCD Controller” on page 234. 9. Updated ”Register Summary” on page 10. 1. Updated typos. 2. Updated ”Calibrated Internal RC Oscillator” on page 32. 3. Updated ”OSCCAL – Oscillator Calibration Register” on page 38. 4. Added Table 28-2 on page 332. 1. Updated ”Calibrated Internal RC Oscillator” on page 32. 1. Initial revision. 8018PS–AVR–08/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en- Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR®, AVR® logo, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Windows® and others are registered trademarks or trademarks of Microsoft® Corporation in the US and/or other countries. Other terms and product names may be trademarks of others. PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Rev. 04 — 9 March 2011 Product data sheet LFPAK Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤175°C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 76 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 51 W Tj junction temperature -55 - 175 °C Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 15 A; Tj = 25 °C - 4.92 7 mΩ Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14; see Figure 15 - 2.9 - nC QG(tot) total gate charge - 10 - nC Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 65 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped - - 21 mJ PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 2 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK 2. Pinning information 3. Ordering information 4. Limiting values Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source SOT669 (LFPAK) 2 S source 3 S source 4 G gate mb D mounting base; connected to drain mb 1 2 3 4 S D G mbb076 Table 3. Ordering information Type number Package Name Description Version PSMN7R0-30YL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDSM peak drain-source voltage tp ≤ 25 ns; f ≤ 500 kHz; EDS(AL) ≤ 90 nJ; pulsed - 35 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 100 °C; see Figure 1 - 53 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 76 A IDM peak drain current pulsed; tp ≤ 10 μs; Tmb = 25 °C; see Figure 3 - 260 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 51 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 65 A ISM peak source current pulsed; tp ≤ 10 μs; Tmb = 25 °C - 260 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 65 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped - 21 mJ PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 3 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003aac720 0 20 40 60 80 100 0 50 100 150 200 Tmb (°C) ID (A) Tmb (°C) 0 50 100 150 200 03aa16 40 80 120 Pder (%) 0 003aac732 10-1 1 10 102 103 10-1 1 10 102 VDS (V) ID (A) DC Limit RDSon = VDS / ID 100 ms 10 ms 1 ms 100 μs 10 μs PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 4 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 1.4 2.45 K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration 003aac721 single shot 0.2 0.1 0.05 0.02 10-2 10-1 1 10 10-6 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Zth(j-mb) (K/W) δ = 0.5 tp T P t tp T δ = PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 5 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK 6. Characteristics Table 6. Characteristics Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 μA; VGS = 0 V; Tj=25°C 30 - - V ID = 250 μA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11; see Figure 12 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 12 0.65 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 12 - - 2.45 V IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj=25°C - - 1 μA VDS = 30 V; VGS = 0 V; Tj = 150 °C - - 100 μA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA RDSon drain-source on-state resistance VGS = 4.5 V; ID = 15 A; Tj = 25 °C - 6.97 9.1 mΩ VGS = 10 V; ID = 15 A; Tj = 150 °C; see Figure 13 - - 12.2 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C - 4.92 7 mΩ RG gate resistance f = 1 MHz - 0.6 1.5 Ω Dynamic characteristics QG(tot) total gate charge ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 10 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 20 - nC ID = 10 A; VDS = 12 V; VGS = 10 V; see Figure 14; see Figure 15 - 22 - nC QGS gate-source charge ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 3.7 - nC QGS(th) pre-threshold gate-source charge - 2.1 - nC QGS(th-pl) post-threshold gate-source charge - 1.6 - nC QGD gate-drain charge - 2.9 - nC VGS(pl) gate-source plateau voltage VDS = 12 V; see Figure 14; see Figure 15 - 2.6 - V Ciss input capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 1270 - pF Coss output capacitance - 255 - pF Crss reverse transfer capacitance - 145 - pF td(on) turn-on delay time VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG(ext) = 4.7 Ω - 24 - ns tr rise time - 39 - ns td(off) turn-off delay time - 30 - ns tf fall time - 11 - ns PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 6 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.88 1.2 V trr reverse recovery time IS = 20 A; dIS/dt = -100 A/μs; VGS = 0 V; VDS = 20 V - 30 - ns Qr recovered charge - 22 - nC Table 6. Characteristics …continued Tested to JEDEC standards where applicable. Symbol Parameter Conditions Min Typ Max Unit Fig 5. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 6. Forward transconductance as a function of drain current; typical values Fig 7. Drain-source on-state resistance as a function of gate-source voltage; typical values Fig 8. Output characteristics: drain current as a function of drain-source voltage; typical values 003aac729 0 20 40 60 80 0 1 2 3 VGS (V) 4 ID (A) Tj = 150 °C 25 °C 003aac728 30 40 50 60 0 10 20 30 I 40 D (A) gfs (S) 003aac727 4 6 8 10 12 14 2 4 6 8 V 10 GS (V) RDSon (mΩ) 003aac726 0 20 40 60 80 100 0 2 4 6 8 10 VDS (V) ID (A) VGS (V) = 4.5 10 3.2 3 2.8 2.6 2.4 2.2 PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 7 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Fig 9. Input and reverse transfer capacitances as a function of gate-source voltage; typical values Fig 10. Drain-source on-state resistance as a function of drain current; typical values Fig 11. Sub-threshold drain current as a function of gate-source voltage Fig 12. Gate-source threshold voltage as a function of junction temperature 003aac724 0 500 1000 1500 2000 2500 0 2 4 6 8 10 VGS (V) C (pF) Ciss Crss 003aac722 4 6 8 10 12 14 16 0 20 40 60 80 100 ID (A) RDSon (mΩ) VGS (V) = 4.5 10 3.2 003aab271 10-6 10-5 10-4 10-3 10-2 10-1 0 1 2 VGS (V) 3 ID (A) min typ max 003aac337 0 1 2 3 -60 0 60 120 180 Tj (°C) VGS(th) (V) max typ min PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 8 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 14. Gate charge waveform definitions Fig 15. Gate-source voltage as a function of gate charge; typical values Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 03aa27 0 0.5 1 1.5 2 −60 0 60 120 180 Tj (°C) a 003aaa508 VGS VGS(th) QGS1 QGS2 QGD VDS QG(tot) ID QGS VGS(pl) 003aac725 0 2 4 6 8 10 0 5 10 15 20 25 QG (nC) VGS (V) VDS = 19 (V) VDS = 12 (V) 003aac723 0 400 800 1200 1600 10-1 1 10 102 VDS (V) C (pF) Ciss Coss Crss PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 9 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values 003aac730 0 20 40 60 80 0.0 0.2 0.4 0.6 0.8 1.0 VSD (V) IS (A) Tj = 150 °C 25 °C PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 10 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK 7. Package outline Fig 18. Package outline SOT669 (LFPAK) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT669 MO-235 04-10-13 06-03-16 0 2.5 5 mm scale e E1 b c2 A2 UNIT A A2 b c e DIMENSIONS (mm are the original dimensions) mm 1.10 0.95 A1 A3 0.15 0.00 1.20 1.01 0.50 0.35 b2 4.41 3.62 b3 2.2 2.0 b4 0.9 0.7 0.25 0.19 c2 0.30 0.24 4.10 3.80 6.2 5.8 H 1.3 0.8 L2 0.85 0.40 L 1.3 0.8 L1 8° 0° D(1) w y 5.0 4.8 E(1) 3.3 3.1 E1 D1 (1) (1) max 0.25 4.20 1.27 0.25 0.1 1 2 3 4 mounting base D1 c Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E b2 b3 b4 H D L2 L1 A w M A C C X 1/2 e y C θ θ (A 3 ) L A A1 detail X Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 11 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN7R0-30YL v.4 20110309 Product data sheet - PSMN7R0-30YL v.3 Modifications: • Various changes to content. PSMN7R0-30YL v.3 20100104 Product data sheet - PSMN7R0-30YL v.2 PSMN7R0-30YL v.2 20090105 Product data sheet - PSMN7R0-30YL v.1 PSMN7R0-30YL v.1 20081015 Preliminary data sheet - - PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 12 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK 9. Legal information 9.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective Document status [1] [2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PSMN7R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 04 — 9 March 2011 13 of 14 NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors PSMN7R0-30YL N-channel 30 V 7 mΩ logic level MOSFET in LFPAK © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 March 2011 Document identifier: PSMN7R0-30YL Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. DPO4000 Series Digital Phosphor Oscilloscopes User Manual www.tektronix.com 071-1785-00 Copyright © Tektronix. All rights reserved. Licensed software products are owned by Tektronix or its subsidiaries or suppliers, and are protected by national copyright laws and international treaty provisions. Tektronix products are covered by U.S. and foreign patents, issued and pending. Information in this publication supersedes that in all previously published material. Specifications and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. e*Scope, iView, OpenChoice, TekSecure, and TekVPI are registered trademarks of Tektronix, Inc. Wave Inspector is a trademark of Tektronix, Inc. Contacting Tektronix Tektronix, Inc. 14200 SW Karl Braun Drive P.O. Box 500 Beaverton, OR 97077 USA For product information, sales, service, and technical support: In North America, call 1-800-833-9200. Worldwide, visit www.tektronix.com to find contacts in your area. Warranty 4 Tektronix warrants that this product will be free from defects in materials and workmanship for a period of three (3) years from the date of shipment. If any such product proves defective during this warranty period, Tektronix, at its option, either will repair the defective product without charge for parts and labor, or will provide a replacement in exchange for the defective product. Parts, modules and replacement products used by Tektronix for warranty work may be new or reconditioned to like new performance. All replaced parts, modules and products become the property of Tektronix. In order to obtain service under this warranty, Customer must notify Tektronix of the defect before the expiration of the warranty period and make suitable arrangements for the performance of service. Customer shall be responsible for packaging and shipping the defective product to the service center designated by Tektronix, with shipping charges prepaid. Tektronix shall pay for the return of the product to Customer if the shipment is to a location within the country in which the Tektronix service center is located. Customer shall be responsible for paying all shipping charges, duties, taxes, and any other charges for products returned to any other locations. This warranty shall not apply to any defect, failure or damage caused by improper use or improper or inadequate maintenance and care. Tektronix shall not be obligated to furnish service under this warranty a) to repair damage resulting from attempts by personnel other than Tektronix representatives to install, repair or service the product; b) to repair damage resulting from improper use or connection to incompatible equipment; c) to repair any damage or malfunction caused by the use of non-Tektronix supplies; or d) to service a product that has been modified or integrated with other products when the effect of such modification or integration increases the time or difficulty of servicing the product. THIS WARRANTY IS GIVEN BY TEKTRONIX WITH RESPECT TO THE PRODUCT IN LIEU OF ANY OTHER WARRANTIES, EXPRESS OR IMPLIED. TEKTRONIX AND ITS VENDORS DISCLAIM ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. TEKTRONIX’ RESPONSIBILITY TO REPAIR OR REPLACE DEFECTIVE PRODUCTS IS THE SOLE AND EXCLUSIVE REMEDY PROVIDED TO THE CUSTOMER FOR BREACH OF THIS WARRANTY. TEKTRONIX AND ITS VENDORS WILL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES IRRESPECTIVE OF WHETHER TEKTRONIX OR THE VENDOR HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. Table of Contents Table of Contents General Safety Summary ................................................................................................................... v Environmental Considerations ............................................................................................................ viii Preface....................................................................................................................................... x Key Features........................................................................................................................... x Where to Find More Information..................................................................................................... xii Conventions Used in This Manual................................................................................................... xiii Installation .................................................................................................................................. 1 Before Installation..................................................................................................................... 1 Operating Considerations ............................................................................................................ 6 Connecting Probes .................................................................................................................. 10 Powering On the Oscilloscope ...................................................................................................... 11 Powering Off the Oscilloscope ...................................................................................................... 14 Functional Check .................................................................................................................... 15 Compensating the Probe ............................................................................................................ 17 Installing an Application Module..................................................................................................... 19 Changing the User Interface Language ............................................................................................. 20 Changing the Date and Time ........................................................................................................ 23 Signal Path Compensation .......................................................................................................... 25 Upgrading Firmware ................................................................................................................. 28 Connecting Your Oscilloscope to a Computer ...................................................................................... 34 DPO4000 Series User Manual i Table of Contents Get Acquainted with the Instrument....................................................................................................... 45 Front-Panel Menus and Controls.................................................................................................... 45 Front-Panel Connectors ............................................................................................................. 66 Side-Panel Connector ............................................................................................................... 67 Rear-Panel Connectors.............................................................................................................. 68 Acquire the Signal ......................................................................................................................... 70 Setting Up Signal Input .............................................................................................................. 70 Using the Default Setup ............................................................................................................. 73 Using Autoset ........................................................................................................................ 74 Acquisition Concepts ................................................................................................................ 75 How the Acquisition Modes Work ................................................................................................... 78 Changing the Acquisition Mode and Record Length................................................................................ 80 Using Roll Mode ..................................................................................................................... 83 Defining a Serial Bus ................................................................................................................ 84 Trigger Setup and Run .................................................................................................................... 91 Triggering Concepts ................................................................................................................. 91 Choosing a Trigger................................................................................................................... 98 Selecting Triggers.................................................................................................................... 99 Triggering on Buses ................................................................................................................ 102 Checking Trigger Status ............................................................................................................ 107 Using A (Main) and B (Delayed) Triggers .......................................................................................... 107 Starting and Stopping an Acquisition............................................................................................... 111 ii DPO4000 Series User Manual Table of Contents Display Waveform Data .................................................................................................................. 112 Adding and Removing a Waveform ................................................................................................ 112 Setting the Display Style and Persistence ......................................................................................... 112 Setting Waveform and Graticule Intensity.......................................................................................... 115 Setting the Graticule Style .......................................................................................................... 117 Setting the LCD Backlight .......................................................................................................... 118 Scaling and Positioning a Waveform............................................................................................... 120 Setting Input Parameters ........................................................................................................... 122 Analyze Waveform Data.................................................................................................................. 129 Taking Automatic Measurements................................................................................................... 129 Selecting Automatic Measurements................................................................................................ 131 Customizing an Automatic Measurement .......................................................................................... 137 Taking Manual Measurements with Cursors ....................................................................................... 144 Using Math Waveforms ............................................................................................................. 150 Using FFT........................................................................................................................... 153 Using Advanced Math .............................................................................................................. 157 Using Reference Waveforms ....................................................................................................... 160 Managing Long Record Length Waveforms........................................................................................ 163 Save and Recall Information ............................................................................................................. 174 Saving a Screen Image............................................................................................................. 174 Saving and Recalling Waveform Data.............................................................................................. 176 Saving and Recalling Setups ....................................................................................................... 184 DPO4000 Series User Manual iii Table of Contents Saving with One Button Push ...................................................................................................... 187 Printing a Hard Copy................................................................................................................ 189 Erasing DPO4000 Memory ......................................................................................................... 196 Use Application Modules ................................................................................................................. 200 Application Examples..................................................................................................................... 201 Taking Simple Measurements ...................................................................................................... 201 Analyzing Signal Detail ............................................................................................................. 217 Triggering on a Video Signal ....................................................................................................... 226 Capturing a Single-Shot Signal..................................................................................................... 230 Correlating Data With a TLA5000 Logic Analyzer ................................................................................. 235 Tracking Down Bus Anomalies ..................................................................................................... 238 Index iv DPO4000 Series User Manual General Safety Summary General Safety Summary Review the following safety precautions to avoid injury and prevent damage to this product or any products connected to it. To avoid potential hazards, use this product only as specified. Only qualified personnel should perform service procedures. To Avoid Fire or Personal Injury Use Proper Power Cord. Use only the power cord specified for this product and certified for the country of use. Connect and Disconnect Properly. Do not connect or disconnect probes or test leads while they are connected to a voltage source. Connect and Disconnect Properly. De-energize the circuit under test before connecting or disconnecting the current probe. Ground the Product. This product is grounded through the grounding conductor of the power cord. To avoid electric shock, the grounding conductor must be connected to earth ground. Before making connections to the input or output terminals of the product, ensure that the product is properly grounded. Observe All Terminal Ratings. To avoid fire or shock hazard, observe all ratings and markings on the product. Consult the product manual for further ratings information before making connections to the product. The inputs are not rated for connection to mains or Category II, III, or IV circuits. Connect the probe reference lead to earth ground only. Do not apply a potential to any terminal, including the common terminal, that exceeds the maximum rating of that terminal. DPO4000 Series User Manual v General Safety Summary Power Disconnect. The power switch disconnects the product from the power source. See instructions for the location. Do not block the power switch; it must remain accessible to the user at all times. Do Not Operate Without Covers. Do not operate this product with covers or panels removed. Do Not Operate With Suspected Failures. If you suspect that there is damage to this product, have it inspected by qualified service personnel. Avoid Exposed Circuitry. Do not touch exposed connections and components when power is present. Do Not Operate in Wet/Damp Conditions. Do Not Operate in an Explosive Atmosphere. Keep Product Surfaces Clean and Dry. Provide Proper Ventilation. Refer to the manual’s installation instructions for details on installing the product so it has proper ventilation. Terms in this Manual These terms may appear in this manual: WARNING. Warning statements identify conditions or practices that could result in injury or loss of life. CAUTION. Caution statements identify conditions or practices that could result in damage to this product or other property. vi DPO4000 Series User Manual General Safety Summary Symbols and Terms on the Product These terms may appear on the product: DANGER indicates an injury hazard immediately accessible as you read the marking. WARNING indicates an injury hazard not immediately accessible as you read the marking. CAUTION indicates a hazard to property including the product. The following symbols may appear on the product: DPO4000 Series User Manual vii Environmental Considerations Environmental Considerations This section provides information about the environmental impact of the product. Product End-of-Life Handling Observe the following guidelines when recycling an instrument or component: Equipment Recycling. Production of this equipment required the extraction and use of natural resources. The equipment may contain substances that could be harmful to the environment or human health if improperly handled at the product’s end of life. In order to avoid release of such substances into the environment and to reduce the use of natural resources, we encourage you to recycle this product in an appropriate system that will ensure that most of the materials are reused or recycled appropriately. The symbol shown below indicates that this product complies with the European Union’s requirements according to Directive 2002/96/EC on waste electrical and electronic equipment (WEEE). For information about recycling options, check the Support/Service section of the Tektronix Web site (www.tektronix.com). Mercury Notification. This product uses an LCD backlight lamp that contains mercury. Disposal may be regulated due to environmental considerations. Please contact your local authorities or, within the United States, the Electronics Industries Alliance (www.eiae.org) for disposal or recycling information. viii DPO4000 Series User Manual Environmental Considerations Restriction of Hazardous Substances This product has been classified as Monitoring and Control equipment, and is outside the scope of the 2002/95/EC RoHS Directive. This product is known to contain lead, cadmium, mercury, and hexavalent chromium. DPO4000 Series User Manual ix Preface Preface This manual describes the installation and operation of the following DPO4000 Series Instruments: DPO4104 DPO4054 DPO4034 DPO4032 Key Features DPO4000 Series instruments can help you verify, debug, and characterize electronic designs. Key features include: 1 GHz, 500 MHz, and 350 MHz bandwidths 2 and 4 channel models Sample rates up to 5 GS/s on all channels 10 Megapoint record length on all channels I2C, SPI, and CAN serial triggering and analysis (Requires use of the DPO4EMBD (for I2C and SPI) or DPO4AUTO (for CAN) application modules) Wave Inspector controls for managing long record lengths, with zoom and pan, play and pause, search and mark 10.4 inch (264 mm) XGA color display Small footprint and lightweight, at 140 mm (5.5 inches) deep and 5 kg (11 pounds) USB and CompactFlash available for quick and easy storage Built-in Ethernet port USB 2.0 device port for direct PC control of the oscilloscope using USBTMC protocol x DPO4000 Series User Manual Preface OpenChoice documentation and analysis software Remote viewing with control (e*Scope and OpenChoice connectivity) TekVPI Versatile Probe Interface supports active, differential, and current probes for automatic scaling and units DPO4000 Series User Manual xi Preface Where to Find More Information The following information is available for your oscilloscope: To read about Use these documents Installation and Operation This DPO4000 User Manual English: 071-1785-XX French: 071-1799-XX Italian: 071-1800-XX German: 071-1801-XX Spanish: 071-1802-XX Japanese: 071-1803-XX Portuguese: 071-1804-XX Simplified Chinese: 071-1805-XX Traditional Chinese: 071-1806-XX Korean: 071-1807-XX Russian: 071-1808-XX Specifications and Performance Verification The DPO4000 Technical Reference (071-1843-XX) (PDF only) Programmer Commands The DPO4000 Programmer Manual (071-1845-XX) (PDF only) Analysis and Connectivity Tools The optional Getting Started with OpenChoice Solutions Manual (020-2514-XX) (includes a CD) xii DPO4000 Series User Manual Preface To read about Use these documents Servicing and calibration The optional DPO4000 Service Manual (071-1844-XX) Installing and testing application modules The DPO4000 Series Application Module Installation Instructions manual (071-1833-XX) (11 languages) Conventions Used in This Manual The following icons are used throughout this manual. Sequence Step Front panel power Connect power Network USB DPO4000 Series User Manual xiii Preface xiv DPO4000 Series User Manual Installation Installation Before Installation Unpack the oscilloscope and check that you received all items listed as standard accessories. The following pages list recommended accessories and probes, instrument options, and upgrades. Check the Tektronix Web site (www.tektronix.com) for the most current information. Standard Accessories Accessory Tektronix part number English (Option L0) 071-1785-XX French (Option L1) 071-1799-XX Italian (Option L2) 071-1800-XX German (Option L3) 071-1801-XX Spanish (Option L4) 071-1802-XX Japanese (Option L5) 071-1803-XX Portuguese (Option L6) 071-1804-XX Simple Chinese (Option L7) 071-1805-XX Traditional Chinese (Option L8) 071-1806-XX Korean (Option L9) 071-1807-XX DPO4000 User Manual Russian (Option L10) 071-1808-XX DPO4000 Series User Manual 1 Installation Standard Accessories (cont.) Accessory Tektronix part number DPO4000 Documentation Browser CD Electronic versions of DPO4000 documents, including the Programmer Manual and the Technical Reference. 063-1810-XX OpenChoice Desktop CD Applications that let you capture and transfer data from your oscilloscope to an external PC. Use the standalone OpenChoice Desktop, MS Word, or MS Excel Toolbars. 020-2514-XX Calibration certificate documenting traceability to national metrology institute(s), and ISO9001 quality system registration. —— One 500 MHz, 10x passive probe per channel P6139A Front Cover Hard plastic cover to help protect the instrument 200-4908-00 CompactFlash memory card Extra storage 156-9413-00 2 DPO4000 Series User Manual Installation Standard Accessories (cont.) Accessory Tektronix part number North America (Option A0) 161-0104-00 Universal Euro (Option A1) 161-0104-06 United Kingdom (Option A2) 161-0104-07 Australia (Option A3) 161-0104-05 Switzerland (Option A5) 161-0167-00 Japan (Option A6) 161-A005-00 China (Option A10) 161-0306-00 India (Option A11) 161-0400-00 Power Cord No power cord or AC adapter (Option A99) —— DPO4000 Series User Manual 3 Installation Optional Accessories Accessory Tektronix Part Number DPO4EMBD The embedded serial triggering and analysis module enables triggering on packet level information on I2C and SPI serial buses, as well as digital views of the signal, bus views, bus decoding, search tools, and packet decode tables with timestamp information DPO4EMBD DPO4AUTO The embedding automotive serial triggering and analysis module enables triggering on packet level information on CAN serial buses, as well as digital views of the signal, bus views, bus decoding, search tools, and packet decode tables with timestamp information DPO4AUTO TPA-BNC TekVPI to TekProbe 2 BNC Adapter TPA-BNC TEK-USB-488 Adapter GPIB to USB Adapter TEK-USB-488 Getting Started with OpenChoice Solutions Manual with CD Describes ways to develop host-computer software applications that work with your oscilloscope 020-2513-XX Rackmount kit Adds rackmount brackets RM4000 Soft transit case Case for carrying instrument AC4000 Hard transit case Traveling case, which requires use of the soft transit case (AC4000) HCTEK4321 4 DPO4000 Series User Manual Installation Optional Accessories (cont.) Accessory Tektronix Part Number CompactFlash memory card Extra storage 156-9413-00 CompactFlash to USB memory card reader Card reader 119-6827-00 DPO4000 Programmer Manual Describes commands for remote control of the DPO4000 oscilloscope. Available electronically on the Documentation Browser CD or for download from www.tektronix.com. 071-1845-XX DPO4000 Technical Reference Manual Describes the DPO4000 oscilloscope specifications and performance verification procedure. Available electronically on the Documentation Browser CD or for download from www.tektronix.com. 071-1809-XX DPO4000 Service manual Service information 071-1844-XX DPO4000 Module Installation Instructions Manual 071-1833-XX The DPO4000 oscilloscope works with multiple optional probes. (See page 10, Connecting Probes.) Check the Tektronix Web site (www.tektronix.com) for the most current information. DPO4000 Series User Manual 5 Installation Operating Considerations DPO4000 Series Oscilloscope Input Voltage: 100 V to 240 V ±10% Input Power Frequency: 47 Hz to 66 Hz (100 V to 240 V) 400 Hz (100 V to 132 V) Power Consumption: 250 W maximum Weight: 5 kg (11 lbs), stand-alone instrument Height, including feet but not handle: 229 mm (9.0 in) Width, from handle hub to handle hub: 439 mm (17.3 in) Depth, from feet to front of knobs: 137 mm (5.4 in) Depth, from feet to front of front cover: 145 mm (5.7 in) Clearance: 51 mm (2 in) Temperature: Operating: +0 °C to +50 °C Nonoperating: -20 °C to +60 °C 6 DPO4000 Series User Manual Installation Humidity: Operating: High: 40 °C to 50 °C, 10% to 60% RH Operating: Low: 0 °C to 40 °C, 10 to 90% RH Non-operating: High: 40 °C to 60 °C, 5 to 60% RH Non-operating: Low: 0 °C to 40 °C, 5 to 90% RH Altitude: Operating: 3,000 m (about 10,000 ft) Nonoperating Altitude: 12,192 m (40,000 ft) Random Vibration: Operating: 0.31 GRMS, 5 – 500 Hz, 10 minutes per axis, 3 axes (30 minutes total) Non-operating: 2.46 GRMS, 5 – 500 Hz, 10 minutes per axis, 3 axes (30 minutes total) Pollution Degree: 2, Indoor use only Acquisition System: 1 MΩ The maximum input voltage at the BNC, between center conductor and shield is 400 Vpeak (DF ≤ 39.2%), 250 VRMS to 130 kHz derated to 2.6 V RMS at 500 MHz. The maximum transient withstand voltage is ± 800 Vpeak. For steady-state sinusoidal waveforms, derate at 20 dB/decade above 200 kHz to 13 Vpk at 3 MHz and above. Acquisition System: 50Ω The maximum input voltage at the BNC, between center conductor and shield is 5 VRMS, with peaks ≤ ±20 V (DF ≤ 6.25%) DPO4000 Series User Manual 7 Installation External Trigger: 1 MΩ The maximum input voltage at the BNC, between center conductor and shield is 400 Vpeak (DF ≤ 39.2%), 250 VRMS to 2 MHz derated to 5 VRMS at 500 MHz. The maximum transient withstand voltage is ±800 Vpeak. For steady-state sinosoidal waveforms, derate at 20 dB/decade above 200 kHz to 13 Vpeak at 3 MHz and above. P6139A Passive Probe Input Voltage: 400 VRMS or 400 V DC; CAT I (2,500 Vpeak transient) 300 VRMS or 300 V DC; CAT II (2,500 Vpeak transient 150 VRMS or 150 V DC; CAT III (2,500 Vpeak transient) For steady-state, sinusoidal waveforms, derate at 20 dB/decade above 2.5 MHz to 50 VRMS at 20 MHz and above. Output Voltage (terminated into 1 MΩ): 40 VRMS or 40 V DC; CAT I (2,500 Vpeak impulse) 30 VRMS or 30 V DC; CAT I (250 Vpeak impulse) 15 VRMS or 15 V DC; CAT I (250 Vpeak impulse) Temperature: Operating: -15 °C to +65 °C ( +5 °F to +149 °F) Nonoperating: -62 °C to +85 °C ( -80 °F to +185 °F) Altitude: ≤ 2,000 meters 8 DPO4000 Series User Manual Installation Pollution Degree: 2, Indoor use only Humidity: Operating: High: 40 °C to 50 °C, 10% to 60% RH Operating: Low: 0 °C to 40 °C, 10 to 90% RH CAUTION. To ensure proper cooling, keep the sides and rear of the instrument clear of obstructions. Cleaning Inspect the oscilloscope and probes as often as operating conditions require. To clean the exterior surface, perform the following steps: 1. Remove loose dust on the outside of the oscilloscope and probes with a lint-free cloth. Use care to avoid scratching the clear glass display filter. 2. Use a soft cloth dampened with water to clean the oscilloscope. Use an aqueous solution of 75% isopropyl alcohol for more efficient cleaning. CAUTION. To avoid damage to the surface of the oscilloscope or probes, do not use any abrasive or chemical cleaning agents. DPO4000 Series User Manual 9 Installation Connecting Probes The DPO4000 oscilloscope supports probes with the following: 1. Tektronix Versatile Probe Interface (TekVPI) These probes support two-way communication with the oscilloscope through on-screen menus and remotely through programmable support. The remote control is useful in applications like ATE where you want the system to preset probe parameters. 2. TPA-BNC Adapter The TPA-BNC Adapter allows you to use TekProbe Level II probe capabilities, such as providing probe power and passing information to the oscilloscope on scaling and whether the units are volts or amperes. 3. Plain BNC interfaces These probes only pass the waveform signal to the oscilloscope. There is no other communication. 10 DPO4000 Series User Manual Installation For more information on the many probes available for use with DPO4000 oscilloscopes, refer to www.tektronix.com. Powering On the Oscilloscope Ground the Oscilloscope and Yourself Before pushing the power switch, connect the oscilloscope to an electrically neutral reference point, such as earth ground. Do this by plugging the three-pronged power cord into an outlet grounded to earth ground. Grounding the oscilloscope is necessary for safety and to take accurate measurements. The oscilloscope needs to share the same ground as any circuits that you are testing. DPO4000 Series User Manual 11 Installation If you are working with static sensitive components, ground yourself. Static electricity that builds up on your body can damage static-sensitive components. Wearing a grounding strap safely sends static charges on your body to earth ground. 12 DPO4000 Series User Manual Installation To connect the power cord and power on the oscilloscope: DPO4000 Series User Manual 13 Installation Powering Off the Oscilloscope To power off the oscilloscope and remove the power cord: 14 DPO4000 Series User Manual Installation Functional Check Perform this quick functional check to verify that your oscilloscope is operating correctly. 1. Connect the oscilloscope power cable as described above. 2. Power on the oscilloscope. DPO4000 Series User Manual 15 Installation 3. Connect the oscilloscope P6139A probe tip and reference lead to the PROBE COMP connectors. 4. Press Default Setup. 16 DPO4000 Series User Manual Installation 5. Push the Autoset button. The screen should now display a square wave, approximately 2.5 V at 1 kHz. If the signal appears but is misshapen, perform the procedures for compensating the probe. (See page 17, Compensating the Probe.) If no signal appears, rerun the procedure. If it no signal still appears, have the instrument serviced by qualified service personnel. Compensating the Probe Whenever you attach a passive voltage probe for the first time to any input channel, compensate the probe to match it to the corresponding oscilloscope input channel. To properly compensate your passive probe: 1. Follow the steps for the functional check. (See page 15, Functional Check.) DPO4000 Series User Manual 17 Installation 2. Check the shape of the displayed waveform to determine if your probe is properly compensated. Properly compensated Under compensated Over compensated 3. If necessary, adjust your probe. Repeat as needed. 18 DPO4000 Series User Manual Installation Quick Tips Use the shortest possible ground lead and signal path to minimize probe-induced ringing and distortion on the measured signal. Short ground lead Long ground lead Installing an Application Module CAUTION. To avoid damage to the oscilloscope or application module, observe ESD precautions. (See page 11, Powering On the Oscilloscope.) Turn off the oscilloscope power while removing or adding an application module. (See page 14, Powering Off the Oscilloscope.) DPO4000 Series User Manual 19 Installation Optional application module packages extend the capability of your oscilloscope. Install up to four application modules at one time into the two slots with windows in the upper right corner of the front panel and the two additional slots hidden behind the two you can see. Refer to the DPO4000 Series Application Module Installation Instructions that came with your application module for instructions on installing and testing an application module. NOTE. If you remove an application module, the features provided by the application module become unavailable. To restore the features, turn off the oscilloscope power, reinstall the module and turn on the oscilloscope power. Changing the User Interface Language To change the language of the oscilloscope user interface and the front-panel button labels: 1. Push Utility. 2. Push System repeatedly until you select Config from the pop-up menu. Config 20 DPO4000 Series User Manual Installation 3. Push Language from the resulting lower-bezel menu. System Config Language English Set Date & Time TekSecure Erase Memory Version v1.00 4. Push the side-bezel button corresponding to the desired language. Choose among: English, French, Italian, German, Spanish, Japanese, Brazilian Portuguese, Simplified Chinese, Traditional Chinese, Korean, and Russian. Language English Francais Deutsch Italiano -more- 1 of 3 DPO4000 Series User Manual 21 Installation 5. If you choose to use English, be sure that the plastic front-panel overlay is removed. If you choose a language other than English, place the plastic overlay for the language that you desire over the front panel to display labels in that language. 22 DPO4000 Series User Manual Installation Changing the Date and Time To set the internal clock with the current date and time: 1. Push Utility. 2. Push System repeatedly until you select Config from the pop-up menu. Config 3. Push Set Date & Time. System Config Language English Set Date & Time TekSecure Erase Memory Version DPO4000 Series User Manual 23 Installation Date Time Set Display Date/Time ON OFF 4. Push the side-panel buttons and rotate both multipurpose knobs (a and b) to set the time and date values. Hour: 4 Min: 1 Month: July Day: 19 Year: 2005 OK Enter Date & Time 5. Push OK Enter Date & Time. OK Enter Date & Time 24 DPO4000 Series User Manual Installation Signal Path Compensation Signal Path Compensation (SPC) corrects for DC inaccuracies caused by temperature variations and/or long-term drift. Run the compensation whenever the ambient temperature has changed by more than 10 °C or once a week if you use vertical settings of 5 mV/division or less. Failure to do so may result in the instrument not meeting warranted performance levels at those volts/div settings. To compensate the signal path: 1. Warm up the oscilloscope for at least 20 minutes. Remove all input signals (probes and cables) from channel inputs. Input signals with AC components adversely affect SPC. DPO4000 Series User Manual 25 Installation 2. Push Utility. 3. Push System repeatedly until you select Calibration from the resulting pop-up menu. Calibration 4. Push Signal Path from the lower-bezel menu. System Calibration Signal Path Pass Factory Pass 5. Push OK Compensate Signal path from the resulting side-bezel menu. OK Compensate Signal Path The calibration will take approximately 10 minutes to complete. 26 DPO4000 Series User Manual Installation 6. After calibration, verify that the status indicator on the lower-bezel menu displays Pass. System Calibration Signal Path Pass Factory Pass If it does not, then recalibrate the instrument or have the instrument serviced by qualified service personnel. 7. Service personnel use the factory calibration functions to calibrate the internal voltage references of the oscilloscope using external sources. Refer to your Tektronix field office or representative for assistance with factory calibration. NOTE. Signal Path Compensation does not include calibration to the probe tip. (See page 17, Compensating the Probe.) DPO4000 Series User Manual 27 Installation Upgrading Firmware To upgrade the firmware of the oscilloscope: 1. Open up a Web browser and go to www.tektronix.com. Proceed to the software finder. Download the latest firmware for your DPO4000 series oscilloscope onto a USB storage device. 28 DPO4000 Series User Manual Installation 2. Power off your DPO4000. DPO4000 Series User Manual 29 Installation 3. Insert the USB storage device into the front-panel USB port on your DPO4000. 30 DPO4000 Series User Manual Installation 4. Power on the DPO4000. The instrument automatically recognizes the replacement firmware and installs it. If the instrument does not install the firmware, rerun the procedure. It the problem continues, contact qualified service personnel. CAUTION. Do not power off the oscilloscope or remove the USB storage device until the oscilloscope finishes installing the firmware. DPO4000 Series User Manual 31 Installation 5. Power off the DPO4000 and remove the USB storage device. 32 DPO4000 Series User Manual Installation 6. Power on the DPO4000. 7. Push Utility. DPO4000 Series User Manual 33 Installation 8. Push Version. The oscilloscope displays the firmware version number. System Config Language English Set Date & Time TekSecure Erase Memory Version 9. Confirm that the version number matches that of the new firmware. Connecting Your Oscilloscope to a Computer You may want to document your work for future reference. Instead of saving screen images and waveform data to a CompactFlash or USB storage device, and then generating a report later, you may want to send it directly to a remote PC for analysis. You may also want to control an oscilloscope at a remote location from your computer. Two ways to connect your oscilloscope to a computer are the TekVISA-based OpenChoice and the e*Scope Web-enabled tool. Use OpenChoice to communicate with your oscilloscope from your computer through a software application. Use e*Scope to communicate with your oscilloscope through a Web browser. Using OpenChoice OpenChoice lets you use your MS-Windows computer to acquire data from your oscilloscope for use in an analysis package that runs on your PC, such as Microsoft Excel, National Instruments LabVIEW. or a program of your own creation. You can use a common communications protocol, such as USB, Ethernet, or GPIB to connect the computer to the oscilloscope. 34 DPO4000 Series User Manual Installation To set up OpenChoice communications between your oscilloscope and a computer: 1. Load the TekVISA drivers on your computer. Find these on the OpenChoice Desktop CD or at the Tektronix software finder Web page (www.tektronix.com). When done, the TekVISA icon appears in the Windows System Tray. Typically, this is the bottom right of the Windows desktop on your MS-Windows computer. DPO4000 Series User Manual 35 Installation 2. Connect the DPO4000 to your computer with the appropriate USB or Ethernet cable. To communicate between the DPO4000 and a GPIB system, connect the oscilloscope to the TEK-USB-488 GPIB-to-USB Adapter with a USB cable. Then connect the adapter to your GPIB system with a GPIB cable. 36 DPO4000 Series User Manual Installation 3. Push Utility. 4. Push System repeatedly to select I/O. I/O 5. To use Ethernet, push Ethernet Network Settings. System I/O USB Enabled Ethernet Network Settings GPIB 1 DPO4000 Series User Manual 37 Installation Network Configuration Change Instrument Settings DHCP/ BOOTP On Off On the side-bezel menu, if you are on a DHCP Ethernet network and using a through cable, set DHCP to On. If you are using a cross-over cable, set it to Off and set a hard coded TCPIP address. Test Connection 6. If you are using GPIB, push GPIB. 7. Enter the GPIB address on the side-bezel menu, using multipurpose knob a. Talk/Listen Address a 1 This will set the GPIB address on an attached TEK-USB-488 Adapter. 38 DPO4000 Series User Manual Installation 8. If you are using USB, the system sets itself up automatically for you, if USB is enabled. Check USB on the bottom-bezel menu to be sure that USB is enabled. If it is not enabled, push USB. Then push Enabled on the side-bezel menu. 9. Run your application software on your computer. 10. In case of problems getting oscilloscope-to-PC communications to work, refer to the networking troubleshooter. To bring up the troubleshooter, click the TekVISA icon on the System Tray of your MS-Windows computer. Then go to the online help. Quick Tips The DPO4000 comes with a variety of Windows-based software tools designed to ensure efficient connectivity between your oscilloscope and your computer. There are tool bars that speed connectivity with Microsoft Excel and Word. There is also a standalone acquisition program called the OpenChoice Desktop. The rear-panel USB 2.0 device port is the correct USB port for computer connectivity. Use the rear- and front-panel USB 2.0 host ports to connect your oscilloscope to storage devices and printers. DPO4000 Series User Manual 39 Installation Using e*Scope e*Scope lets you access any Internet-connected DPO4000 Series Oscilloscope from a browser on your workstation, PC, or laptop computer. No matter where you are, your DPO4000 is as close as the nearest browser. To set up e*Scope communications between your oscilloscope and a Web browser running on a remote computer: 1. Connect the DPO4000 to your computer network with the appropriate Ethernet cable. 2. Push Utility. 40 DPO4000 Series User Manual Installation 3. Push System repeatedly to select I/O. I/O 4. Push Ethernet Network Settings. System I/O USB Ethernet Network Settings GPIB DPO4000 Series User Manual 41 Installation Network Configuration 5. Push Change Instrument Settings to determine the Ethernet address and instrument name. On the side-bezel menu, if you are on a DHCP Ethernet network and using dynamic addressing, set DHCP to On. If you are using static addressing, set it to Off. Change Instrument Settings DHCP/ BOOTP On Off Test Connection 6. Start your browser on your remote computer. In the browser address line, enter the IP address or, if DHCP is set to On in the oscilloscope, simply enter the instrument name. 42 DPO4000 Series User Manual Installation 7. You should now see the e*Scope screen, with a copy of the oscilloscope display, on your Web browser. If e*Scope does not work, rerun the procedure. If it still does not work, contact qualified service personnel. DPO4000 Series User Manual 43 Installation 44 DPO4000 Series User Manual Get Acquainted with the Instrument Get Acquainted with the Instrument Front-Panel Menus and Controls The front panel has buttons and controls for the functions that you use most often. Use the menu buttons to access more specialized functions. DPO4000 Series User Manual 45 Get Acquainted with the Instrument Using the Menu System To use the menu system: 1. Push a front-panel menu button to display the menu that you want to use. 46 DPO4000 Series User Manual Get Acquainted with the Instrument 2. Push a lower-bezel button to select a menu item. If a pop-up menu appears, push the lower-bezel button repeatedly to select the desired choice. 3. Push a side-bezel button to choose a side-bezel menu item. If the menu item contains more than one choice, push the side-bezel button repeatedly to cycle through the choices. DPO4000 Series User Manual 47 Get Acquainted with the Instrument 4. To remove a side-bezel menu, push the lower-bezel button again or push Menu Off. 5. Certain menu choices require you to set a numerical value to complete the setup. Use the upper and lower multipurpose knobs a and b to adjust values. 6. Push Fine to turn off or on the ability to make smaller adjustments. 48 DPO4000 Series User Manual Get Acquainted with the Instrument Using the Menu Buttons Use the menu buttons to perform many functions in the oscilloscope. 1. Measure. Push to perform automated measurements on waveforms or to configure cursors. 2. Search. Push to search through an acquisition for user-defined events/criteria. 3. Test. Push to activate advanced or application-specific testing features. 4. Acquire. Push to set the acquisition mode and adjust the record length. 5. Autoset. Push to perform an automatic setup of oscilloscope settings. 6. Trigger Menu. Push to specify trigger settings. DPO4000 Series User Manual 49 Get Acquainted with the Instrument 7. Utility. Push to activate the system utility functions, such as selecting a language or setting the date/time. 8. Default Setup. Push to restore the oscilloscope to the default settings. 9. Save / Recall Menu. Push to save and recall setups, waveforms, and screen images to internal memory, a CompactFlash card, or a USB storage device. 10. Channel 1,2,3, or 4. Push to set vertical parameters for input waveforms and to display or remove the corresponding waveform from the display. 50 DPO4000 Series User Manual Get Acquainted with the Instrument 11. B1 or B2. Push to define and display a bus, if you have the appropriate module application keys. The DPO4AUTO module supports CAN. The DPO4EMBD module supports I2C and SPI. Also, push the B1 or B2 button to display or remove the corresponding bus from the display. 12. R. Push to manage reference waveforms, including the display or removal of each reference waveform from the display. 13. M. Push to manage the math waveform, including the display or removal of the math waveform from the display. DPO4000 Series User Manual 51 Get Acquainted with the Instrument Using Other Controls These buttons and knobs control waveforms, cursors and other data input. 1. Turn the upper multipurpose knob a, when activated, to move a cursor or set a numerical parameter value for a menu item. Push the nearby Fine button to toggle between coarse and fine adjustment. Screen icons tell you when a or b are active. 2. Cursors. Push once to activate the two vertical cursors. Push again to turn on the two vertical and two horizontal cursors. Push again to turn off all cursors. When the cursors are on, you can turn the multipurpose knobs to control their position. 52 DPO4000 Series User Manual Get Acquainted with the Instrument 3. Select. Push to activate special functions. For example, when using the two vertical cursors (and no horizontal ones are visible), you can push this button to link or unlink the cursors. When the two vertical and two horizontal cursors are both visible, you can push this button to make either the vertical cursors or the horizontal ones active. 4. Fine. Push to toggle between making coarse and fine adjustments with the vertical and horizontal position knobs, the trigger level knob, and many operations of multipurpose knobs a and b. 5. Waveform Intensity. Push to enable multipurpose knob a to control waveform display intensity and knob b to control graticule intensity. DPO4000 Series User Manual 53 Get Acquainted with the Instrument 6. Turn the lower multipurpose knob b, when activated, to move a cursor or set a numerical parameter value for a menu item. Push Fine to make adjustments more slowly. 7. Zoom button. Push to activate zoom mode. 8. Pan (outer knob). Turn to scroll the zoom window through the acquired waveform. 9. Zoom (inner knob). Turn to control the zoom factor. Turning it clockwise zooms in further. Turning it counterclockwise zooms out. 10. Play-pause button. Push to start or stop the automatic panning of a waveform. Control the speed and direction with the pan knob. 11. ← Prev. Push to jump to the previous waveform mark. 54 DPO4000 Series User Manual Get Acquainted with the Instrument 12. Set/Clear Mark. Push to establish or delete a waveform mark. 13. → Next. Push to jump to the next waveform mark. 14. Horizontal Position. Turn to adjust the trigger point location relative to the acquired waveforms. Push Fine to make smaller adjustments. 15. Horizontal Scale. Turn to adjust the horizontal scale (time/division). DPO4000 Series User Manual 55 Get Acquainted with the Instrument 16. Run/Stop. Push to start or stop acquisitions. 17. Single. Push to make a single acquisition. 18. Autoset. Push to automatically set the vertical, horizontal, and trigger controls for a usable, stable display. 19. Trigger Level. Turn to adjust the trigger level. 20. Set to 50%. Push to set the trigger level to the midpoint of the waveform. 21. Force Trig. Push to force an immediate trigger event. 56 DPO4000 Series User Manual Get Acquainted with the Instrument 22. Vertical Position. Turn to adjust the vertical position of the corresponding waveform. Push Fine to make smaller adjustments. 23. 1, 2, 3, 4. Push to display or remove the corresponding waveform from the display and access the vertical menu. 24. Vertical Scale. Turn to adjust the vertical scale factor of the corresponding waveform (volts/division). 25. Print. Push to initiate a hard copy using the printer selected in the Utility menu. 26. Power switch. Push to power on or off the instrument. DPO4000 Series User Manual 57 Get Acquainted with the Instrument 27. USB 2.0 host port. Insert a USB cable here to connect peripherals, such as printers and storage devices, to the oscilloscope. There are also two more USB 2.0 host ports on the rear panel. 28. CompactFlash Drive. Insert a CompactFlash card here. 29. CompactFlash Eject. Pops the CompactFlash card out of the CompactFlash drive. 30. Save. Push to perform an immediate save operation. The save operation uses the current save parameters, as defined in the Save / Recall menu. 31. Default Setup. Push to perform an immediate restore of the oscilloscope to the default settings. 32. Menu Off. Push to clear a displayed menu from the screen. 58 DPO4000 Series User Manual Get Acquainted with the Instrument Identifying Items in the Display The items shown to the right may appear in the display. Not all of these items are visible at any given time. Some readouts move outside the graticule area when menus are turned off. DPO4000 Series User Manual 59 Get Acquainted with the Instrument 1. The acquisition readout shows when an acquisition is running, stopped, or when acquisition preview is in effect. Icons are: Run: Acquisitions enabled Stop: Acquisitions not enabled Roll: In roll mode (40 ms/div or slower) PreVu: In this state, the oscilloscope is stopped or between triggers. You can change the horizontal or vertical position or scale to see approximately what the next acquisition will look like. RUN 60 DPO4000 Series User Manual Get Acquainted with the Instrument 2. The trigger position icon shows the trigger position in the acquisition. 3. The expansion point icon (an orange triangle) shows the point that the horizontal scale expands and compresses around. 4. The waveform record view shows the trigger location relative to the waveform record. The line color corresponds to the selected waveform color. DPO4000 Series User Manual 61 Get Acquainted with the Instrument 5. The trigger status readout shows trigger status. Status conditions are: Trig’d: Triggered Auto: Acquiring untriggered signal PrTrig: Acquiring pretrigger data Trig?: Waiting for trigger Trig’d 6. The cursor readout shows time, amplitude, and delta (Δ) values for each cursor. For FFT measurements, it shows frequency and magnitude. 62 DPO4000 Series User Manual Get Acquainted with the Instrument 7. The trigger level icon shows the trigger level on the waveform. The icon color corresponds to the trigger source channel color. 8. The edge trigger readout shows the trigger source, slope, and level. The trigger readouts for other trigger types show other parameters. 9. The top line of the record length/sampling rate readout shows the sampling rate (adjust with the Horizontal Scale knob). The bottom line shows the record length (adjust with the Acquire menu). DPO4000 Series User Manual 63 Get Acquainted with the Instrument 10. The horizontal position/scale readout shows on the top line the horizontal scale (adjust with the Horizontal Scale knob) and on the bottom line the time from the T symbol to the expansion point icon (adjust with the Horizontal Position knob). Use horizontal position to insert added delay between when the trigger occurs and when you actually capture the data. Insert a negative time to capture more pretrigger information. 11. The auxiliary waveform readouts show the vertical and horizontal scale factors of the math or reference waveforms. 12. The channel readout shows the channel scale factor (per division), coupling, and invert status. Adjust with the Vertical Scale knob and the channel 1, 2, 3, or 4 menus. 64 DPO4000 Series User Manual Get Acquainted with the Instrument 13. Measurement readouts show the selected measurements. You can select up to four measurements to display at one time. A symbol appears instead of the expected numerical measurement if a vertical clipping condition exists. Part of the waveform is above or below the display. To obtain a proper numerical measurement, turn the vertical scale and position knobs to make all of the waveform appear in the display. 14. The waveform baseline indicator shows the zero-volt level of a waveform (ignoring the effect of offset). The icon colors correspond to the waveform colors. DPO4000 Series User Manual 65 Get Acquainted with the Instrument Front-Panel Connectors 1. Channel 1, 2, (3, 4). Channel inputs with TekVPI Versatile Probe Interface. 2. Aux In. Trigger level range is adjustable from +8 V to –8 V. The maximum input voltage is 400V peak, 250V RMS. Input resistance is 1 MΩ ± 1% in parallel with 13 pF ±2 pF. 3. PROBE COMP. Square wave signal source to compensate probes. Output voltage: 0 – 2.5V, amplitude ± 1% behind 1k Ω ±2%. Frequency: 1 kHz. 4. Ground. 5. Application Module Slots. 66 DPO4000 Series User Manual Get Acquainted with the Instrument Side-Panel Connector 1. Ground strap connector. This is a receptacle for a grounding strap. DPO4000 Series User Manual 67 Get Acquainted with the Instrument Rear-Panel Connectors 1. Trigger Out. Use the trigger signal output to synchronize other test equipment with your oscilloscope. A LOW to HIGH transition indicates the trigger occurred. The logic level for Vout (HI) is ≥2.5V open circuit; ≥1.0 V into a 50Ω load to ground. The logic level for Vout (LO) is ≤0.7 V into a load of ≤4 mA; ≤0.25 V into a 50Ω load to ground. 2. XGA Out. Use the XGA Video port (DB-15 female connector) to show the oscilloscope display on an external monitor or projector. 3. LAN. Use the LAN (Ethernet) port (RJ-45 connector) to connect the oscilloscope to a 10/100 Base-T local area network. 4. Device. Use the USB 2.0 High speed device port to control the oscilloscope through USBTMC or GPIB with a TEK-USB-488 Adapter. The USBTMC protocol allows USB devices to communicate using IEEE488 style messages. This lets you run your GPIB software applications on USB hardware. 68 DPO4000 Series User Manual Get Acquainted with the Instrument 5. Host. Use the USB 2.0 Full speed host ports (two) to take advantage of USB mass storage devices and printers. 6. Power input. Attach to an AC power line with integral safety ground. (See page 6, Operating Considerations.) DPO4000 Series User Manual 69 Acquire the Signal Acquire the Signal This section describes concepts of and procedures for setting up the oscilloscope to acquire the signal as you want it to. Setting Up Signal Input Use front-panel buttons to set up your instrument to acquire the signal. 1. Connect the P6139A or VPI probe to the input signal source. 70 DPO4000 Series User Manual Acquire the Signal 2. Select the input channel by pushing the front-panel buttons. NOTE. If you are using a probe that does not supply probe encoding (not a P6139A nor a VPI probe), set the attenuation (probe factor) on the oscilloscope side-bezel menu. 3. Push Autoset. DPO4000 Series User Manual 71 Acquire the Signal 4. Push the desired channel button. Then adjust the vertical position and scale. 5. Adjust the horizontal position and scale. The horizontal position determines the number of pretrigger and posttrigger samples. The horizontal scale determines the size of the acquisition window relative to the waveform. You can scale the window to contain a waveform edge, a cycle, several cycles, or thousands of cycles. 72 DPO4000 Series User Manual Acquire the Signal Quick Tip Use the zoom feature to see multiple acquisition cycles in the upper part and a single cycle in the lower part of the display. (See page 163, Managing Long Record Length Waveforms.) Using the Default Setup To return the oscilloscope to its default settings: 1. Push Default Setup. 2. If you change your mind, push Undo Default Setup to undo the last default setup. Undo Default Setup Quick Tip The DPO4000 Technical Reference describes the default setup settings in detail. This manual is available on the accompanying CD or at www.tektronix.com. DPO4000 Series User Manual 73 Acquire the Signal Using Autoset Autoset adjusts the instrument (acquisition, horizontal, trigger, and vertical controls) such that it displays two or three waveform cycles with the trigger near the midlevel. 1. Connect the probe, and then select the input channel. (See page 70, Setting Up Signal Input.) 2. Push Autoset to execute an Autoset. 3. If desired, push Autoset Undo to undo the last Autoset. Undo Autoset 74 DPO4000 Series User Manual Acquire the Signal Quick Tips To position the waveform appropriately, Autoset may change the vertical position. Autoset always sets vertical offset to 0 V. If you use Autoset when no channels are displayed, the instrument turns on channel one (1) and scales it. Acquisition Concepts Before a signal can be displayed, it must pass through the input channel where it is scaled and digitized. Each channel has a dedicated input amplifier and digitizer. Each channel produces a stream of digital data from which the instrument extracts waveform records. Sampling Process Acquisition is the process of sampling an analog signal, converting it into digital data, and assembling it into a waveform record, which is then stored in acquisition memory. Input signal Sampled points Digital values DPO4000 Series User Manual 75 Acquire the Signal Real-time Sampling Record points DPO4000 series oscilloscopes use real-time sampling. In real-time sampling, the instrument digitizes all of the points it acquires using a single trigger event. Sampling rate 76 DPO4000 Series User Manual Acquire the Signal Waveform Record The instrument builds the waveform record through use of the following parameters: Sample interval: The time between recorded sample points. Adjust this by turning the Horizontal Scale knob. Record length: The number of samples required to fill a waveform record. Set this by pushing the Acquire button and using the resulting lower-bezel menu. Trigger point: The zero time reference in a waveform record. It is shown on the screen by an orange T. DPO4000 Series User Manual 77 Acquire the Signal Horizontal position: The time from the trigger point to the expansion point. Adjust this by turning the Horizontal Position knob. Use a positive time to acquire the record after the trigger point. Use a negative time to acquire it before the trigger point. Expansion point: The point that the horizontal scale expands and contracts around. It is shown by an orange triangle. How the Acquisition Modes Work Sample mode retains the first sampled point from each acquisition interval. Sample is the default mode. 78 DPO4000 Series User Manual Acquire the Signal Peak Detect mode uses the highest and lowest of all the samples contained in two consecutive acquisition intervals. This mode only works with real-time, noninterpolated sampling and is useful for catching high frequency glitches. Hi Res mode calculates the average of all the samples for each acquisition interval. This mode also only works with real-time, noninterpolated sampling. Hi-Res provides a higher-resolution, lower-bandwidth waveform. Envelope mode finds the highest and lowest record points over all acquisitions. Envelope uses Peak Detect for each individual acquisition. Average mode calculates the average value for each record point over a user-specified number of acquisitions. Average uses Sample mode for each individual acquisition. Use average mode to reduce random noise. DPO4000 Series User Manual 79 Acquire the Signal Changing the Acquisition Mode and Record Length Use this procedure to change the acquisition mode. 1. Push Acquire. 2. Push Mode. Mode Average Record Length 10k Reset Horizontal Position Waveform Display 80 DPO4000 Series User Manual Acquire the Signal Acquisition Mode Sample Peak Detect Hi Res Envelope 3. Then choose the acquisition mode from the side-bezel menu. You can chose from: Sample, Peak Detect, Hi Res, Envelope, or Average. NOTE. Peak Detect and High Res require more than one sample point per sample interval. If there is only one sample point, these two modes will appear the same as sample mode. Average 16 DPO4000 Series User Manual 81 Acquire the Signal 4. If you chose Average, turn multipurpose knob a to set the number of waveforms to average over. 5. Push Record Length. 6. Push the side-bezel menu, record length button. 1000 points Choose between: 1000, 10 k, 100 k, 1 M, and 10 M points. 82 DPO4000 Series User Manual Acquire the Signal Using Roll Mode Roll mode gives a display similar to a strip chart recorder for low-frequency signals. Roll mode lets you see acquired data points without waiting for the acquisition of a complete waveform record. Roll mode is enabled when the trigger mode is auto and the horizontal scale is set to 40 ms/div or slower. Quick Tips Switching to Envelope or Average acquisition mode, using math waveforms, or switching to normal trigger will disable Roll mode. Roll mode is disabled when you set the horizontal scale to 20 ms per division or faster. Push Run/Stop to halt Roll mode. DPO4000 Series User Manual 83 Acquire the Signal Defining a Serial Bus Your DPO4000 oscilloscope can trigger on I2C and SPI serial buses if the DPO4EMBD application module is installed. It can trigger on CAN serial buses if the DPO4AUTO application module is installed. It can display the physical layer of a bus (as analog waveforms), digital waveforms, and protocol level information (as symbolic waveforms). Plug in the DPO4EMBD application module to use the I2C and SPI features. Plug in the DPO4AUTO application module to use the CAN features. Using buses in two steps To quickly use serial bus triggering: 1. Push B1 or B2 and enter parameters of the bus to trigger on. You can separately use B1 and B2 to view two different buses. 2. Push Trigger Menu and enter trigger parameters. (See page 98, Choosing a Trigger.) You can display bus information without triggering on the bus signal. 84 DPO4000 Series User Manual Acquire the Signal Setting up serial bus parameters To set up bus parameters: 1. Push B1 or B2 to bring up the lower-bezel bus menu. I2C SPI 2. Push Bus as many times as needed to select the desired bus (I2C, SPI, or CAN) from the pop-up menu. CAN DPO4000 Series User Manual 85 Acquire the Signal 3. Push Define Inputs and use the side-bezel buttons to assign oscilloscope channels to the serial bus signal(s). Bus I2C Define Inputs Thresholds Display As Bus Bus Decode Hex For example, with an I2C bus, you might assign channel 1 to supply the SCLK signal and channel 2 to supply the SDA signal. You can assign any channel to a predefined bus signal. For all serial bus sources, use channel 1 to channel 4. Do not use the Aux In input. 4. Push Thresholds. Bus I2C Define Inputs Thresholds Display As Bus Decode 86 DPO4000 Series User Manual Acquire the Signal For each signal that makes up the serial bus, push the appropriate side-bezel menu button. Then turn the appropriate multipurpose knob to define the voltage level above which the oscilloscope treats the signal as high and below which as low. 5. If you selected CAN above, push Bit Rate and the desired side-bezel menu choice. Bus CAN Define Inputs Thresholds Bit Rate 500 Kbps Display As Bus Bus Decode Hex 6. If you selected SPI above, push Polarity and the desired side-bezel menu choice. Bus SPI Define Inputs Thresholds Polarity Display As Bus Bus Decode Hex Active High means when a signal is greater than the threshold value, it is considered a logical 1. Active Low means when the signal is lower than the threshold value, it is considered a logical 1. DPO4000 Series User Manual 87 Acquire the Signal 7. Push Display As and use the side-bezel menu to define how to display the serial bus. Display As Push Bus to display packet level information decoded for easy visual inspection, much like what you would see on a logic analyzer. Bus Push Waveforms to display the digital (high or low) representations of the waveforms. Waveforms Push Bus and Waveforms to display both views of the signal. Bus and Waveforms Push Event Table On to display a list of packets in the bus. Event Table On Off Sample bus information: 88 DPO4000 Series User Manual Acquire the Signal Sample waveforms: Sample event table: 8. Push Bus Decode and the desired side-bezel menu choice to display the bus data in hexadecimal or binary format. 9. Turn multipurpose knob a to move the bus display up or down on the screen. DPO4000 Series User Manual 89 Acquire the Signal You can also trigger on packet level information on your serial bus. (See page 102, Triggering on Buses.) NOTE. To acquire signals from two buses simultaneously, use this procedure once to define the parameters of the B1 bus and again to define the B2 bus. 90 DPO4000 Series User Manual Trigger Setup and Run Trigger Setup and Run This section contains concepts and procedures for setting up the oscilloscope to trigger on your signal. Triggering Concepts Trigger Event The trigger event establishes the time-reference point in the waveform record. All waveform record data is located in time with respect to that point. The instrument continuously acquires and retains enough sample points to fill the pretrigger portion of the waveform record. That is the part of the waveform that is displayed before, or to the left of, the triggering event on screen. When a trigger event occurs, the instrument starts acquiring samples to build the posttrigger portion of the waveform record, that is, the part displayed after or to the right of the trigger event. After a trigger is recognized, the instrument will not accept another trigger until the acquisition is complete and the holdoff time has expired. DPO4000 Series User Manual 91 Trigger Setup and Run Untriggered display Triggered display Trigger Modes The trigger mode determines how the instrument behaves in the absence of a trigger event: Normal trigger mode enables the instrument to acquire a waveform only when it is triggered. If no trigger occurs, the last waveform record acquired remains on the display. If no last waveform exists, no waveform is displayed. Auto trigger mode enables the instrument to acquire a waveform even if a trigger does not occur. Auto mode uses a timer that starts when the acquisition is started, and the pretrigger information is obtained. If a trigger event is not detected before the timer times out, the instrument forces a trigger. The length of time it waits for a trigger event depends on the time base setting. 92 DPO4000 Series User Manual Trigger Setup and Run Auto mode, when forcing triggers in the absence of valid triggering events, does not synchronize the waveform on the display. The waveform will appear to roll across the screen. If valid triggers occur, the display will become stable. You can also force the instrument to trigger by pushing the front-panel Force Trig button. Trigger Holdoff Adjust holdoff to obtain stable triggering when the instrument is triggering on undesired trigger events. Trigger holdoff can help stabilize triggering, since the oscilloscope does not recognize new triggers during the holdoff time. When the instrument recognizes a trigger event, it disables the trigger system until acquisition is complete. In addition, the trigger system remains disabled during the holdoff period that follows each acquisition. Holdoffs DPO4000 Series User Manual 93 Trigger Setup and Run Trigger Coupling Trigger coupling determines what part of the signal is passed to the trigger circuit. Edge triggering can use all available coupling types: DC, Low Frequency Rejection, High Frequency Rejection, and Noise Rejection. All other trigger types use DC coupling only. Horizontal Position Use horizontal position to acquire waveform detail in a region that is separated from the trigger location by a significant interval of time. 94 DPO4000 Series User Manual Trigger Setup and Run 1. Adjust the position (delay) time by rotating the Horizontal Position knob. 2. Turn horizontal SCALE to acquire the detail that you need around the position (delay) expansion point. DPO4000 Series User Manual 95 Trigger Setup and Run The part of the record that occurs before the trigger is the pretrigger portion. The part that occurs after the trigger is the posttrigger portion. Pretrigger data can help you troubleshoot. For example, to find the cause of an unwanted glitch in your test circuit, you can trigger on the glitch and make the pretrigger period large enough to capture data before the glitch. By analyzing what happens before the glitch, you may uncover information that helps you find the source of the glitch. Alternatively, to see what is happening in your system as a result of the trigger event, make the posttrigger period large enough to capture data after the trigger. Slope and Level The slope control determines whether the instrument finds the trigger point on the rising or the falling edge of a signal. The level control determines where on that edge the trigger point occurs. The DPO4000 provides a long horizontal bar or bars across the graticule to temporarily show the trigger level. 96 DPO4000 Series User Manual Trigger Setup and Run 1. Turn the front-panel Trigger Level knob to adjust the trigger level without going to a menu. 2. Push the front-panel Set to 50% button to quickly set the trigger level to the midpoint of the waveform. Delayed Trigger System Trigger with the A (Main) trigger system alone or, if using an edge trigger, combine the A (Main) trigger with the B (Delayed) trigger to trigger on sequential events. When using sequential triggering, the A trigger event arms the trigger system, and the B trigger event triggers the instrument when the B trigger conditions are met. A and B triggers can (and typically do) have separate sources. The B trigger condition can be based on a time delay or a specified number of events. (See page 107, Using A (Main) and B (Delayed) Triggers.) DPO4000 Series User Manual 97 Trigger Setup and Run Choosing a Trigger To select a trigger: 1. Push Trigger Menu. Edge Pulse Width Runt Logic Setup & Hold Rise/Fall Time Video 2. Push Type repeatedly to select the trigger type to use. NOTE. The bus trigger requires use of the DPO4EMBD or the DPO4AUTO application module. Bus 98 DPO4000 Series User Manual Trigger Setup and Run 3. Complete the trigger setup using the lower-bezel menu controls displayed for the trigger type. The controls to set up the trigger vary depending on the trigger type. Type Edge Source 1 Coupling DC Slope Level 100 mV Mode Auto & Holdoff Configure B Trigger Selecting Triggers Trigger Type Trigger Conditions Edge Trigger on a rising or falling edge, as defined by the slope control. Coupling choices are DC, LF Reject, HF Reject, and Noise Reject. Edge triggers are the simplest and most commonly used trigger type, with both analog and digital signals. An edge trigger event occurs when the trigger source passes through a specified voltage level in the specified direction. DPO4000 Series User Manual 99 Trigger Setup and Run Trigger Type Trigger Conditions Pulse/Width Trigger on pulses that are less than, greater than, equal to, or not equal to a specified time. You can trigger on positive or negative pulses. Pulse/width triggers are primarily used on digital signals. Runt Trigger on a pulse amplitude that crosses one threshold but fails to cross a second threshold before recrossing the first. You can detect positive or negative (or either) runts, or only those wider than, less than, greater than, equal to, or not equal to a specified width. Runt triggers are primarily used on digital signals. Logic Logic triggers are primarily used with digital signals. You can set each input to high, low, or don’t care. In addition, you can use one channel as a clock source set to either the rising or falling edge. Trigger when logic inputs cause the selected function to become True or False. You can also specify that the logic conditions be satisfied for a specific amount of time before triggering. 100 DPO4000 Series User Manual Trigger Setup and Run Trigger Type Trigger Conditions Setup and Hold Violation Trigger when a logic data input changes state inside of the setup or hold time relative to a clock edge. Setup is the amount of time that data should be stable and not change before a clock edge occurs. Hold is the time that data should be stable and not change after a clock edge occurs. Rise/Fall Time Trigger on rise and fall times. Trigger on pulse edges that traverse between two thresholds at faster or slower rates than the specified time. Specify pulse edges as positive or negative or either. Video Trigger on specified fields or lines of a composite video signal. Only composite signal formats are supported. Trigger on NTSC, PAL, or SECAM.Works with Macrovision signals. DPO4000 Series User Manual 101 Trigger Setup and Run Trigger Type Trigger Conditions Bus Optional: Trigger on common, serial-bus, packet-level information with the following application modules: DPO4EMBD — I2C and SPI DPO4AUTO — CAN Triggering on Buses You can use your DPO4000 oscilloscope to trigger on CAN, I2C, and SPI buses, if you have the DPO4AUTO or the DPO4EMBD application module installed. The DPO4000 can display both physical layer (as analog waveforms ) and protocol level information (as digital and symbolic waveforms). To set up the bus trigger: 1. If you have not already defined your bus using the front-panel B1 or B2 buttons, do so now. (See page 84, Defining a Serial Bus.) 102 DPO4000 Series User Manual Trigger Setup and Run 2. Push Trigger Menu. Bus 3. Push and keep pushing the Type button of the lower-bezel menu until you select Bus. Type Bus Source Bus B1 (I2C) Trigger On Address Address 07F Direction Write Mode Auto & Holdoff DPO4000 Series User Manual 103 Trigger Setup and Run 4. Push and keep pushing the Source Bus B1 (I2C) button of the lower-bezel menu until you select the bus that you want to trigger on. B2 (I2C) 5. Push and keep pushing the lower-bezel menu Trigger On button until you select the desired trigger on feature. If you are using the I2C bus trigger, you can trigger on Start, Repeated Start, Stop, Missing Ack, Address, Data, or Address/Data. If you are using the SPI bus trigger, you can trigger on SS Active, MOSI, MISO, or MOSI & MISO. If you are using the CAN bus trigger, you can trigger on Start of Frame, Type of Frame, Identifier, Data, Id & Data, End of Frame, and Missing Ack. 104 DPO4000 Series User Manual Trigger Setup and Run 6. If you are setting up an I2C trigger and have selected a Trigger On selection of Address or Address/Data, push the lower-bezel menu Address button to access the Address side-bezel menu. Press the side-bezel menu Address button. Enter the address parameters of interest with multipurpose knobs a and b. Then push the lower-bezel menu Direction button to enter the direction of interest. Choices are: Read, Write, and Read or Write. DPO4000 Series User Manual 105 Trigger Setup and Run Bus Trigger Data Matching Rolling window byte matching for I2C and SPI. You can use a rolling window to trigger on data with SPI and I2C buses. You define the number of bytes to match. Then the oscilloscope uses a rolling window to find any match within a packet, with the window rolling one byte at a time. For example, if the number of bytes is one, the oscilloscope will match the first byte, second byte, third, and so on within the packet. If the number of bytes is two, the oscilloscope will try to match any two consecutive bytes, such as one and two, two and three, three and four, and so on. If the oscilloscope finds a match, it will then trigger. Specific byte matching (non-rolling window matching) for CAN, I2C, and SPI. You can trigger on a specific byte for SPI and I2C in two ways: For I2C and SPI, enter the number of bytes to match the number of bytes in the signal. Then use don’t cares (X) to mask the bytes that you are not interested in. For I2C, push the bottom-bezel Trigger On to trigger on Address/Data. Push Address. On the side-bezel menu, push Address and rotate multipurpose knobs a and b as needed. Set the address to don’t cares (X) if you want to mask the address. The data will be matched starting at the first byte without using a rolling window. For CAN, triggering occurs when the user-selected data input matches the data and qualifier in the signal starting at the first byte. Set the number of bytes to match the number of bytes of interest. Use the data qualifier to perform: =, !=, <, >, >=, and <= operations. Triggering on identifier and data always matches the identifier and data selected by the user, with the data starting at the first byte. No rolling window is used. 106 DPO4000 Series User Manual Trigger Setup and Run Checking Trigger Status To quickly determine the settings of some key trigger parameters, check the Trigger readout at the bottom of the display. The readouts differ for edge and the advanced triggers. 1. Trigger source = channel 1. 2. Trigger slope = rising. 3. Trigger level = 0.00 V. Edge trigger readout Using A (Main) and B (Delayed) Triggers Combine an edge A Event (Main) trigger with the B Event (Delayed) trigger to capture more complex signals. After the A Event occurs, the trigger system looks for the B Event before triggering and displaying the waveform. To use the B trigger: 1. Push Trigger Menu. DPO4000 Series User Manual 107 Trigger Setup and Run 2. Press Type repeatedly to select a trigger type of Edge. 3. Push Configure B Trigger. This brings up the B trigger menu. The B Trigger Setup item only appears if the A trigger is set to edge trigger. Type Edge Source 1 Coupling DC Slope Level 0.00 V Mode Auto & Holdoff Configure B Trigger 4. Set the B trigger parameters as defined in the B trigger lower-bezel and side-bezel menu items. B Trigger On B Trigger After A Time Source 1 Coupling DC Slope Level 0.00V Configure A Trigger 108 DPO4000 Series User Manual Trigger Setup and Run Trigger on B Event The A trigger arms the instrument. Posttrigger acquisition starts on the nth B event. DPO4000 Series User Manual 109 Trigger Setup and Run B Trigger After Delay Time The A trigger arms the instrument. Posttrigger acquisition starts on the first B edge after the trigger delay time. Quick Tips B-trigger delay time and horizontal position are independent functions. When you establish a trigger condition using either the A trigger alone or the A and B triggers together, you can also use horizontal position to delay the acquisition by an additional amount. When using the B trigger, the A and B trigger types can only be Edge. 110 DPO4000 Series User Manual Trigger Setup and Run Starting and Stopping an Acquisition After you have defined the acquisition and trigger parameters, start the acquisition with Run/Stop or Single. Push Run/Stop to start the acquisition. Push it again to stop the acquisition. Push Single to take a single acquisition. Single sets the trigger mode to Normal for the single acquisition. DPO4000 Series User Manual 111 Display Waveform Data Display Waveform Data This section contains concepts and procedures for displaying the acquired waveform. Adding and Removing a Waveform 1. To add or remove an active waveform from the display, push the relevant front-panel channel button. You can use the channel as a trigger source whether or not it is displayed. Setting the Display Style and Persistence 1. To set the display style, push Acquire. 112 DPO4000 Series User Manual Display Waveform Data 2. Push Waveform Display. Mode Sample Record Length 10k Reset Horizontal Position Waveform Display DPO4000 Series User Manual 113 Display Waveform Data 3. Push Dots Only On Off from the side-bezel menu. Dots on will display the waveform record points as dots on the screen. Dots off connects the dots with vectors. Waveform Display Dots Only On Off 4. Push Persist Time, and turn multipurpose knob a to have waveform data remain on screen for a user-specified amount of time. Persist Time a Auto 5. Push Set to Auto to have the oscilloscope automatically determine a persistence time for you. Set to Auto 6. Push Clear Persistence to reset the persistence information. Clear Persistence 114 DPO4000 Series User Manual Display Waveform Data Quick Tips Variable persistence accumulates record points for a specified time interval. Each record point decays independently according to the time interval. Use variable persistence for displaying infrequently appearing signal anomalies, such as glitches. Infinite persistence continuously accumulates record points until you change one of the acquisition display settings. Use infinite persistence for displaying unique signal anomalies, such as glitches. Setting Waveform and Graticule Intensity 1. Push the front-panel Intensity button. This will bring up the intensity readout on the display. DPO4000 Series User Manual 115 Display Waveform Data 2. Rotate multipurpose knob a to select the desired waveform intensity. 3. Rotate multipurpose knob b to select the desired intensity for the graticule and text. 4. Push Intensity again to clear the intensity readout from the display. 116 DPO4000 Series User Manual Display Waveform Data Setting the Graticule Style 1. To set the graticule style, push Utility. 2. Push System repeatedly until you select Display from the pop-up menu. Display 3. Push Graticule from the lower-bezel menu. System Display Backlight Intensity High Graticule Full DPO4000 Series User Manual 117 Display Waveform Data 4. Select the desired style from the resulting side-bezel menu. Use the Full graticule for quick estimates of waveform parameters. Use the Grid graticule for full-screen measurements with cursors and automatic readouts when cross hairs are not needed. Use the Cross Hair graticule for making quick estimates of waveforms while leaving more room for automatic readouts and other data. Use the Frame graticule with automatic readouts and other screen text when display features are not needed. Setting the LCD Backlight 1. Push Utility. 118 DPO4000 Series User Manual Display Waveform Data 2. Push System repeatedly until you select Display. Display 3. Push Backlight Intensity. System Display Backlight Intensity High Graticule Full Backlight Intensity High Medium 4. Select the intensity level from the resulting side-bezel menu. Choices are: High, Medium, and Low. Low DPO4000 Series User Manual 119 Display Waveform Data Scaling and Positioning a Waveform Use the horizontal controls to adjust the time base, adjust the trigger point, and to examine waveform details more closely. Original waveform Scaled horizontally Positioned horizontally 120 DPO4000 Series User Manual Display Waveform Data Use the vertical controls to select waveforms, adjust the waveform vertical position and scale, and set input parameters. Push a channel button (1, 2, 3, or 4), the MATH button, or the REF button or the B1 or B2 button as many times as needed and the associated menu items to select, add, or remove a waveform. Original waveform Scaled vertically Positioned vertically Quick Tips Preview. If you change the Position or Scale controls when the acquisition is stopped or when it is waiting for the next trigger, the oscilloscope rescales and repositions the relevant waveforms in response to the new control settings. It simulates what you will see when you next push the RUN button. The oscilloscope uses the new settings for the next acquisition. You may see a clipped waveform if the original acquisition went off the screen. The math waveform, cursors, and automatic measurements remain active and valid when using preview. DPO4000 Series User Manual 121 Display Waveform Data Setting Input Parameters Use the vertical controls to select waveforms, adjust the waveform vertical position and scale, and set input parameters. 1. Push channel button 1, 2, 3, or 4 to bring up the vertical menu for the designated waveform. The vertical menu only affects the selected waveform. Pushing a channel button will also select or cancel that waveform selection. 2. Push Coupling. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1X 122 DPO4000 Series User Manual Display Waveform Data 3. Push DC, AC, or GND (ground). Use DC coupling to pass both AC and DC components. DC Use AC coupling to block the DC component and show only the AC signal. AC Use Ground (GND) to display the reference potential. GND 4. Push Ω. Ω 1M 50 Set the input impedance (termination) to 50 Ω or 1 MΩ if using DC or Gnd coupling. Input impedance is automatically set to 1 MΩ when using AC coupling. For more information on input impedance, see Quick Tips below. DPO4000 Series User Manual 123 Display Waveform Data 5. Push Invert to invert the signal. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1X Select Invert Off for normal operation and Invert On to invert the polarity of the signal in the preamplifier. 6. Push Bandwidth, and select the desired bandwidth from the resulting side-bezel menu. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1 X The set choices are: Full, 250 MHz, and 20 MHz. Additional choices may appear, depending on the probe that you use. Select Full to set the bandwidth to the full oscilloscope bandwidth. Select 250 MHz to set the bandwidth to 250 MHz. Select 20 MHz to set the bandwidth to 20 MHz. 124 DPO4000 Series User Manual Display Waveform Data 7. Push Fine Scale to enable multipurpose knob a to make fine vertical scale adjustments. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1 X 8. Push Offset to enable multipurpose knob a to make vertical offset adjustments. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1 X On the side-bezel menu, choose Set to 0 V to set the vertical offset to 0 V. For more information on offset, see the Quick Tips below. DPO4000 Series User Manual 125 Display Waveform Data 9. Push Position to enable multipurpose knob a to make vertical position adjustments. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1 X NOTE. You can also use the position knob on the front panel to do this. On the side-bezel menu, choose Set to 0 divs to set the vertical position to the center of the screen. For more information on vertical position, see the Quick Tips below. 126 DPO4000 Series User Manual Display Waveform Data 10. Push Probe Setup to define probe parameters. Coupling DC Invert Off Bandwidth Full Fine Scale 100mV/div Offset 0.00V Position 0.00 div Probe Setup 1 X On the resulting side-bezel menu: Select Voltage Probe or Current Probe to set the probe gain or attenuation for probes that do not have the TekProbe II or TekVPI interface. Push Deskew to set the time skew correction to zero. Turn multipurpose knob a to adjust the time skew (deskew) correction for the probe attached to the selected channel. This shifts acquisition and display of the waveform left or right, relative to the trigger time. Use this to compensate for differences in cable lengths or probe types. Select Attenuation to choose the probe attenuation. DPO4000 Series User Manual 127 Display Waveform Data Quick Tips Using Probes with the TekProbe II and TekVPI Interfaces. When you attach a probe with the TekProbe II or the TekVPI interface, the oscilloscope sets the channel sensitivity, coupling, and termination resistance automatically to match the probe requirements. Tek Probe II probes require use of the TPA-BNC Adapter. The Difference Between Vertical Position and Offset. Vertical position is a display function. Adjust the vertical position to place the waveforms where you want to see them. The waveform baseline locations track adjustments made to their positions. When you adjust vertical offset, you see a similar effect, but it is actually quite different. Vertical offset is applied before the oscilloscope preamplifier and can be used to increase the effective dynamic range of the inputs. For example, you can use vertical offset to look at small variations in a large DC voltage. Set the vertical offset to match the nominal DC voltage and the signal appears in the center of the screen. 50 Ω Protection. If you select 50 Ω termination, the maximum vertical scale factor is limited to 1 V/div. If you apply excessive input voltage, the oscilloscope automatically switches to 1 M Ω termination to protect the internal 50 Ω termination. For more details, refer to the specifications in the DPO4000 Technical Reference. 128 DPO4000 Series User Manual Analyze Waveform Data Analyze Waveform Data After having properly set up the acquisition, triggering, and display of your desired waveform, you can then analyze the results. Select from features such as cursors, automatic measurements, statistics, math, and FFT. Taking Automatic Measurements To take an automatic measurement: 1. Push Measure. 2. Push Select Measurement. Select Measurement Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors DPO4000 Series User Manual 129 Analyze Waveform Data 3. Turn multipurpose knob a to select the channel from which you want to measure. This step is only needed if you are acquiring data on more than one channel. 4. Select the specific measurement or measurements from the side-bezel menu. 5. To remove a measurement, push Remove Measurement and the specific measurement from the resulting side-bezel menu. Quick Tips To remove all measurements, select Remove All. A symbol appears instead of the expected numerical measurement if a vertical clipping condition exists. Part of the waveform is above or below the display. To obtain a proper numerical measurement, turn the vertical scale and position knobs to make all of the waveform appear in the display. 130 DPO4000 Series User Manual Analyze Waveform Data Selecting Automatic Measurements The following tables list each automatic measurement by category: amplitude or time. (See page 129, Taking Automatic Measurements.) Time Measurements Measurement Description Period The time required to complete the first cycle in a waveform or gated region. Period is the reciprocal of frequency and is measured in seconds. Frequency The first cycle in a waveform or gated region. Frequency is the reciprocal of the period; it is measured in hertz (Hz) where one Hz is one cycle per second. Delay The time between the mid reference (default 50%) amplitude point of two different waveforms. See also Phase. Rise Time The time required for the leading edge of the first pulse in the waveform or gated region to rise from the low reference value (default = 10%) to the high reference value (default = 90%) of the final value. Fall Time The time required for the falling edge of the first pulse in the waveform or gated region to fall from the high reference value (default = 90%) to the low reference value (default = 10%) of the final value. Positive Duty Cycle The ratio of the positive pulse width to the signal period expressed as a percentage. The duty cycle is measured on the first cycle in the waveform or gated region. DPO4000 Series User Manual 131 Analyze Waveform Data Time Measurements (cont.) Measurement Description Negative Duty Cycle The ratio of the negative pulse width to the signal period expressed as a percentage. The duty cycle is measured on the first cycle in the waveform or gated region. Positive Pulse Width The distance (time) between the mid reference (default 50%) amplitude points of a positive pulse. The measurement is made on the first pulse in the waveform or gated region. Negative Pulse Width The distance (time) between the mid reference (default 50%) amplitude points of a negative pulse. The measurement is made on the first pulse in the waveform or gated region. Burst Width The duration of a burst (a series of transient events) and is measured over the entire waveform or gated region. Phase The amount of time that one waveform leads or lags another waveform, expressed in degrees where 360° comprises one waveform cycle. See also Delay. 132 DPO4000 Series User Manual Analyze Waveform Data Amplitude Measurements Measurement Description Positive Overshoot This is measured over the entire waveform or gated region and is expressed as: Positive Overshoot = (Maximum – High) / Amplitude x 100%. Negative Overshoot This is measured over the entire waveform or gated region and is expressed as: Negative Overshoot = (Low – Minimum) / Amplitude x 100%. DPO4000 Series User Manual 133 Analyze Waveform Data Amplitude Measurements (cont.) Measurement Description Pk-Pk The absolute difference between the maximum and minimum amplitude in the entire waveform or gated region. Amplitude The high value less the low value measured over the entire waveform or gated region. High This value is used as 100% whenever high reference, mid reference, or low reference values are needed, such as in fall time or rise time measurements. Calculate using either the min/max or histogram method. The min/max method uses the maximum value found. The histogram method uses the most common value found above the midpoint. This value is measured over the entire waveform or gated region. Low This value is used as 0% whenever high reference, mid reference, or low reference values are needed, such as in fall time or rise time measurements. Calculate using either the min/max or histogram method. The min/max method uses the minimum value found. The histogram method uses the most common value found below the midpoint. This value is measured over the entire waveform or gated region. Max The most positive peak voltage. Max is measured over the entire waveform or gated region. Min The most negative peak voltage. Min is measured over the entire waveform or gated region. 134 DPO4000 Series User Manual Analyze Waveform Data Amplitude Measurements (cont.) Measurement Description Mean The arithmetic mean over the entire waveform or gated region. Cycle Mean The arithmetic mean over the first cycle in the waveform or the first cycle in the gated region. RMS The true Root Mean Square voltage over the entire waveform or gated region. Cycle RMS The true Root Mean Square voltage over the first cycle in the waveform or the first cycle in the gated region. DPO4000 Series User Manual 135 Analyze Waveform Data Miscellaneous Measurements Measurement Description Area Area measurement is a voltage over time measurement. It returns the area over the entire waveform or gated region in volt-seconds. Area measured above ground is positive; area measured below ground is negative. Cycle Area A voltage over time measurement. The measurement is the area over the first cycle in the waveform or the first cycle in the gated region expressed in volt-seconds. The area above the common reference point is positive while the area below the common reference point is negative. 136 DPO4000 Series User Manual Analyze Waveform Data Customizing an Automatic Measurement You can customize automatic measurements by using gating, modifying measurement statistics, adjusting the measurement reference levels, or taking a snapshot. Gating Gating confines the measurement to a certain portion of a waveform. To use: 1. Push Measure. 2. Push Gating. Select Measurement Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors DPO4000 Series User Manual 137 Analyze Waveform Data 3. Position the gates from the side-bezel menu options. Gating Off (Full record) Screen Between cursors Bring cursors on screen 138 DPO4000 Series User Manual Analyze Waveform Data Statistics Statistics characterize the stability of measurements. To adjust statistics: 1. Push Measure. 2. Push Statistics. Select Measurement Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors DPO4000 Series User Manual 139 Analyze Waveform Data Measurement Statistics On Off Mean & Std Dev Samples a 32 3. Push the side-bezel menu options. These include whether to turn statistics on or off and how many samples to use for mean and standard deviation calculations. Reset Statistics Snapshot To see all the single-sourced measurements at one moment in time: 1. Push Measure. 140 DPO4000 Series User Manual Analyze Waveform Data 2. Push Select Measurement. Select measurement Remove Measurement Gating Off Statistics Off High-Low Setup Reference Levels Indicators Off 3. Push Snapshot All Measurements. Snapshot All Measurements 4. View results. Snapshot on 1 Period: 588.0 ns Freq: 1.701 MHz +Width: 529.7 ns -Width: 58.33 ns BrstW: 39.91 μs Rise: 2.014 μs Fall: 1.522 μs ... ... ... ... DPO4000 Series User Manual 141 Analyze Waveform Data Reference Levels Reference levels determine how time-related measurements are taken. For example, they are used in calculating rise and fall times. 1. Push Measure. 2. Push Reference Levels. Select Measurement Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors 142 DPO4000 Series User Manual Analyze Waveform Data 3. Set the levels from the side-bezel menu. Reference Levels Set Levels in % units Use High and Low reference to calculate rise and fall times. High Ref a 90.0 % Use Mid reference primarily for measurements between edges such as pulse widths. Mid Ref a 50.0 % b 50.0 % Low Ref a 10.0 % - more - 1 of 2 DPO4000 Series User Manual 143 Analyze Waveform Data Taking Manual Measurements with Cursors Cursors are on-screen markers that you position in the waveform display to take manual measurements on acquired data. They appear as horizontal and/or as vertical lines. To use cursors: 1. Push Cursors. This changes the cursor state. The three states are: No cursors appear on the screen, Two vertical waveform cursors appear. They are attached to the selected waveform Four screen cursors appear. Two are vertical and two are horizontal. They are no longer specifically attached to a waveform For example, the first time you push Cursors the state might be off. 144 DPO4000 Series User Manual Analyze Waveform Data 2. Push Cursors again. In the example, two vertical cursors appear on the selected screen waveform. As you turn multipurpose knob a, you move one cursor to the right or left. As you turn knob b, you move the other cursor. If you change the selected waveform by pushing the front-panel 1, 2, 3, 4, M or R button, both cursors jump to the new selected waveform. 3. Push Select. This turns the cursor linking on and off. If linking is on, turning multipurpose knob a moves the two cursors together. Turning multipurpose knob b adjusts the time between the cursors. DPO4000 Series User Manual 145 Analyze Waveform Data 4. Push Fine to toggle between a coarse or a fine adjustment for multipurpose knobs a and b. Pushing Fine also changes the sensitivity of other knobs as well. 5. Push Cursors again. This will put the cursors into screen mode. Two horizontal bars and two vertical bars span the graticule. 6. Turn multipurpose knobs a and b to move the pair of horizontal cursors. 146 DPO4000 Series User Manual Analyze Waveform Data 7. Push Select. This makes the vertical cursors active and the horizontal ones inactive. Now, as you turn the multipurpose knobs, the vertical cursors will move. Push Select again to make the horizontal cursors active again. 8. View the cursor and the cursor readout. DPO4000 Series User Manual 147 Analyze Waveform Data 9. Push Cursors again. This will turn off the cursor mode. The screen will no longer display the cursors and the cursor readout. 148 DPO4000 Series User Manual Analyze Waveform Data Using cursor readouts Cursor readouts supply textual and numeric information relating to the current cursor positions. Readouts appear in the upper right corner of the graticule. If Zoom is on, the readout appears in the upper right corner of the zoom window. The oscilloscope always shows the readouts when the cursors are turned on. When a bus is the currently selected waveform, the readout is the decoded bus data in whatever format you have selected (hexadecimal or binary). Δ Readout: The Δ readouts indicate the difference between the cursor positions. a Readout: Indicates the value is controlled by multipurpose knob a. b Readout: Indicates the value is controlled by multipurpose knob b. The horizontal cursor lines on the display measure the vertical parameters, typically voltage. DPO4000 Series User Manual 149 Analyze Waveform Data The vertical cursor lines on the display measure horizontal parameters, typically time. Using Math Waveforms Create math waveforms to support the analysis of your channel and reference waveforms. By combining and transforming source waveforms and other data into math waveforms, you can derive the data view that your application requires. Use the following procedure for executing simple (+, –, *, ÷) math operations on two waveforms: 1. Push Math. 150 DPO4000 Series User Manual Analyze Waveform Data 2. Push Dual Wfm Math. Dual Wfm Math FFT Advanced Math 3. On the side-bezel menu, set the sources to either channel 1, 2, 3, 4, or reference waveforms R1, 2, 3, or 4. Choose the +, –, x, or ÷ operators. 4. For example, you might calculate power by multiplying a voltage waveform and a current waveform. DPO4000 Series User Manual 151 Analyze Waveform Data Quick Tips Math waveforms can be created from channel or reference waveforms or a combination of them. Measurements can be taken on math waveforms in the same way as on channel waveforms. Math waveforms derive their horizontal scale and position from the sources in their math expressions. Adjusting these controls for the source waveforms also adjusts the math waveform. You can zoom in on math waveforms using the inner knob of the Pan-Zoom control. Use the outer knob for positioning the zoomed area. (See page 163, Managing Long Record Length Waveforms.) 152 DPO4000 Series User Manual Analyze Waveform Data Using FFT An FFT breaks down signals into component frequencies, which the oscilloscope uses to display a graph of the frequency domain of a signal, as opposed to the oscilloscope’s standard time domain graph. You can match these frequencies with known system frequencies, such as system clocks, oscillators, or power supplies. 1. Push Math. 2. Push FFT. Dual Wfm Math FFT Advanced Math DPO4000 Series User Manual 153 Analyze Waveform Data 3. Push the side-bezel menu FFT Source button repeatedly to select the source to use. Choices are: channels 1, 2, 3, 4, reference waveforms 1, 2, 3, and 4. Math Definition FFT Source 1 4. Push the side-bezel Vertical Scale button repeatedly to select either Linear RMS or dBV RMS. Vertical Scale Linear RMS 5. Push the side-bezel Window button repeatedly to select the desired window. Window choices are: Rectangular, Hamming, Hanning, and Blackman-Harris. Window Hanning 6. Push the side-bezel Horizontal button to activate multipurpose knobs a and b to pan and zoom the FFT display. Horizontal 0.00 Hz 40.0 154 DPO4000 Series User Manual Analyze Waveform Data 7. The FFT will appear on the display. Quick Tips Use short record lengths for faster instrument response. Use long record lengths to lower the noise relative to the signal and increase the frequency resolution. DPO4000 Series User Manual 155 Analyze Waveform Data If desired, use the zoom feature along with the horizontal Position and Scale controls to magnify and position the FFT waveform. Use the default dBV RMS scale to see a detailed view of multiple frequencies, even if they have very different amplitudes. Use the linear RMS scale to see an overall view of how all frequencies compare to each other. The FFT feature provides four windows. Each is a trade-off between frequency resolution and magnitude accuracy. What you want to measure and your source signal characteristics help determine which window to use. Use the following guidelines to select the best window. Description Window Rectangular This is the best type of window for resolving frequencies that are very close to the same value but worst for accurately measuring the amplitude of those frequencies. It is the best type for measuring the frequency spectrum of nonrepetitive signals and measuring frequency components near DC. Use Rectangular for measuring transients or bursts where the signal level before and after the event are nearly equal. Also, use this window for equal-amplitude sine waves with frequencies that are very close and for broadband random noise with a relatively slow varying spectrum. Hamming This is a very good window for resolving frequencies that are very close to the same value with somewhat improved amplitude accuracy over the rectangular window. It has a slightly better frequency resolution than the Hanning. Use Hamming for measuring sine, periodic, and narrow band random noise. This window works on transients or bursts where the signal levels before and after the event are significantly different. 156 DPO4000 Series User Manual Analyze Waveform Data Description Window Hanning This is a very good window for measuring amplitude accuracy but less so for resolving frequencies. Use Hanning for measuring sine, periodic, and narrow band random noise. This window works on transients or bursts where the signal levels before and after the event are significantly different. Blackman-Harris: This is the best window for measuring the amplitude of frequencies but worst at resolving frequencies. Use Blackman-Harris for measuring predominantly single frequency waveforms to look for higher order harmonics. Using Advanced Math The advanced math feature lets you create a custom math waveform expression that can incorporate active and reference waveforms, measurements, and/or numeric constants. To use this feature: 1. Push Math. DPO4000 Series User Manual 157 Analyze Waveform Data 2. Push Advanced Math. Dual Wfm Math FFT Advanced Math 3. Use the side-bezel menu buttons to create custom expressions. 4. Push Edit Expression and use the multipurpose knobs and the resulting lower-bezel buttons to create an expression. When done, push the side-bezel menu OK Accept button. 158 DPO4000 Series User Manual Analyze Waveform Data For example, to use Edit Expression to take the integral of a square wave: 1. Push the lower-bezel Clear button 2. Turn multipurpose knob a to select INTG( 3. Push Enter Selection 4. Turn multipurpose knob a to select channel 1 5. Push Enter Selection 6. Turn multipurpose knob a to select ) 7. Push OK Accept. DPO4000 Series User Manual 159 Analyze Waveform Data Using Reference Waveforms Create a reference waveform to store a waveform. For example, you might do this to set up a standard against which to compare other waveforms. To use the reference waveforms: 1. Push Ref R. This brings up the lower-bezel reference menu. 2. Use the resulting lower-bezel menu selections to display or select a reference waveform. R 1 (On) 25–Oct- 2006 R 2 (Off) R 3 (Off) R 4 (Off) 160 DPO4000 Series User Manual Analyze Waveform Data 3. Use the side-bezel menu and the multipurpose knobs to adjust the vertical and horizontal settings of the reference waveform. R1 Vertical a 0.00 div b 100 mV/div Horizontal 0.00 s 4.00 μs/div Quick Tips Selecting and Displaying Reference Waveforms. You can display all the reference waveforms at the same time. Push the appropriate screen button to select a particular reference waveform. The selected waveform appears brighter than other displayed reference waveforms. Removing Reference Waveforms from the Display. To remove a reference waveform from the display, push the front-panel R button to access the lower-bezel menu. Then push the associated button from the lower-bezel menu to turn it off. Scaling and Positioning a Reference Waveform. You can position and scale a reference waveform independently from all other displayed waveforms. Select the reference waveform and then adjust it with a multipurpose knob. You can do this whether acquisition is running or not. DPO4000 Series User Manual 161 Analyze Waveform Data If a reference waveform is selected, scaling and repositioning of the reference waveform operates the same way whether zoom is turned on or off. Saving 10M Reference Waveforms. 10M reference waveforms are volatile and not saved when the oscilloscope power is turned off. To keep these waveforms, save them to external storage. Recalling Reference Waveforms from External Storage. 162 DPO4000 Series User Manual Analyze Waveform Data Managing Long Record Length Waveforms The DPO4000 Series Wave Inspector controls (zoom/pan, play/pause, marks, search) help you to efficiently work with long record length waveforms. To magnify a waveform horizontally, rotate the Zoom knob. To scroll through a zoomed waveform, rotate the Pan knob. The Pan-Zoom Control consists of: 1. An outer pan knob 2. An inner zoom knob DPO4000 Series User Manual 163 Analyze Waveform Data Zooming a Waveform To use zoom: 1. Rotate the inner knob on the Pan-Zoom control clockwise to zoom in on a selected portion of the waveform. Rotate the knob counterclockwise to zoom back out. 2. Alternatively, enable or disable the zoom mode by pushing the zoom button. 164 DPO4000 Series User Manual Analyze Waveform Data 3. Examine the zoomed view of the waveform that appears on the larger, lower portion of the display. The upper portion of the display will show the position and size of the zoomed portion in the waveform, within the context of the overall record. DPO4000 Series User Manual 165 Analyze Waveform Data Panning a Waveform While the zoom feature is on, you can use the pan feature to quickly scroll through the waveform. To use pan: 1. Rotate the pan (outer) knob of the pan-zoom controls to pan the waveform. Turn the knob clockwise to pan forward. Turn it counterclockwise to pan backwards. The further you turn the knob, the faster the zoom window pans. 166 DPO4000 Series User Manual Analyze Waveform Data Playing and Pausing a Waveform Use the play-pause feature to automatically pan through a waveform record. To use it: 1. Enable the play-pause mode by pushing the play-pause button. 2. Adjust the play speed by turning the pan (outer) knob further. The further you turn it, the faster it goes. DPO4000 Series User Manual 167 Analyze Waveform Data 3. Change the play direction by reversing the direction that you are turning the pan knob. 4. During play, up to a point, the more you turn the ring, the faster the waveform accelerates. If you rotate the ring as far as it can go, the play speed does not change, but the zoom box quickly moves in that direction. Use this maximum rotation feature to replay a portion of the waveform that you just saw and want to see again. 5. Pause the play-pause feature by pushing the play-pause button again. 168 DPO4000 Series User Manual Analyze Waveform Data Searching and Marking Waveforms You can mark locations of interest in the acquired waveform. These marks help you limit your analysis to particular regions of the waveform. You can mark areas of the waveform automatically, if they meet some special criteria, or you can manually mark each item of interest. You can use arrow keys to jump from mark to mark (area of interest to area of interest). You can automatically search and mark many of the same parameters that you can trigger on. Search marks provide a way to mark a waveform region for reference. You can set marks automatically with search criteria. You can search for and mark regions with particular edges, pulse widths, runts, logic states, rise/fall times, setup and hold, and bus search types. To manually set and clear (delete) marks: 1. Move (the zoom box) to the area on the waveform where you want to set (or clear) a search mark by turning the pan (outer) knob. Push the next ( →) or previous (←) arrow button to jump to an existing mark. 2. Push Set/Clear. If no search mark is at the screen center, the oscilloscope will add one. DPO4000 Series User Manual 169 Analyze Waveform Data 3. Now investigate your waveform by moving from search mark to search mark. Use the next ( →) or previous (←) arrow button to jump from one marked location to another, without adjusting any other controls. 4. Delete a mark. Push the next ( →) or previous (←) arrow button to jump to the mark you want to clear. To remove the current, center-positioned mark, just push Set/Clear. It works on both manually and automatically created marks. To automatically set and clear (delete) search marks: 1. Push Search. 170 DPO4000 Series User Manual Analyze Waveform Data 2. Select the search type desired from the lower-bezel menu. Search Off Search Type Edge Source 1 Slope Threshold 0.00V The search menu is similar to the trigger menu. 3. From the side-bezel menu, turn on the search. 4. On the screen, hollow triangles show the location of automatic marks and solid triangles show the custom (user-defined) locations. These appear on both normal and zoomed waveform views. DPO4000 Series User Manual 171 Analyze Waveform Data 5. Again, you can quickly investigate your waveform by moving from search mark to search mark with the next ( →) and previous (←) arrow buttons. No other adjustments are needed. Quick Tips. You can copy trigger settings to search for other locations in your acquired waveform that meet the trigger conditions. You can also copy search settings to your trigger. Custom (User) marks are saved with the waveform when the waveform is saved and when the setup is saved. Automatic search marks are not saved with the waveform when the waveform is saved. However, you can easily recapture them by re-using the search function. The search criteria are saved in the saved setup. With the optional DPO4EMBD and DPO4AUTO application modules installed, you can use the front-panel B1 and B2 buttons to define a combination of inputs to be either I2C, SPI, or CAN serial bus. Once set up, you can trigger on user-specified packet level content and have the DPO4000 automatically decode every packet in the acquisition into either binary or hex. The Wave Inspector includes the following search capabilities: Search Description Edge Searches for edges (rising or falling) with a user-specified threshold level. Pulse Width Searches for positive or negative pulse widths that are >, <, =, or ≠ a user specified pulse width. 172 DPO4000 Series User Manual Analyze Waveform Data Search Description Runt Searches for positive or negative pulses that cross one amplitude threshold but fail to cross a second threshold before crossing the first again. Search for all runt pulses or only those with a duration >, <, =, or ≠ a user specified time. Logic Search for a logic pattern (AND, OR, NAND, or NOR) across multiple waveforms with each input set to either High, Low, or Don’t Care. Search for when the event goes true, goes false, or stays valid for >, <, =, or ≠ a user specified time. Additionally, you can define one of the inputs as a clock for synchronous (state) searches. Setup & Hold Search for violations of user specified Setup and Hold times. Rise/Fall Time Search for rising and/or falling edges that are >, <, =, or ≠ a user specified time. Bus I2C: Search for Start, Repeated Start, Stop, Missing Ack, Address, Data, or Address and Data. SPI: Search for SS Active, MOSI, MISO, or MOSI & MISO CAN: Search for Start of Frame, Type of Frame (Data, Remote, Error, Overload), Identifier (standard or extended), Data, Identifier and Data, End of Frame, or Missing Ack. DPO4000 Series User Manual 173 Save and Recall Information Save and Recall Information The DPO4000 Series oscilloscope provides permanent storage for setups, waveforms, and screen images. Use the internal storage of the oscilloscope to save setups and reference waveform data. Use external storage, such as CompactFlash media and USB flash-memory storage devices to save setups, waveforms, and screen images. Use the external storage to carry data to remote computers for further analysis and for archiving. Saving a Screen Image A screen image consists of a graphical image of the oscilloscope screen. This is different from waveform data, which consists of numeric values for each point in the waveform. To save a screen image: 1. Push Save / Recall Menu. Do not yet push the Save button. 2. Push Save Screen Image from the lower-bezel menu. Save Screen Image Save Waveform Save Setup Recall Waveform Recall Setup Assign Save to Setup File Utilities 174 DPO4000 Series User Manual Save and Recall Information Save Screen Image 3. From the side-bezel menu, push File Format repeatedly to select among: .tif, .bmp, and .png formats. File Format .png 4. Push Orientation to select between saving the image in a landscape (horizontal) and a portrait (vertical) orientation. Orientation 5. Push Ink Saver to turn the Ink Saver mode on or off. When on, this mode provides a white background. Ink Saver On Off 6. Push Edit File Name to create a custom name for the screen image file. Skip this step to use a default name. Edit File Name 7. Push OK Save Screen Image to write the image to the selected media. OK Save Screen Image DPO4000 Series User Manual 175 Save and Recall Information For information on printing screen images of waveforms, go to Printing a Hardcopy. (See page 189, Printing a Hard Copy.) Saving and Recalling Waveform Data Waveform data consists of the numeric values for each point in the waveform. It copies the data, as opposed to a graphical image of the screen. To save the current waveform data or to recall previously stored waveform data: 1. Push Save / Recall Menu. 2. Push Save Waveform or Recall Waveform from the lower-bezel menu. Save Screen Image Save Waveform Save Setup Recall Waveform Recall Setup Assign Save to Waveform File Utilities 176 DPO4000 Series User Manual Save and Recall Information 3. From the resulting side-bezel menu, select the location to save the waveform data to or to recall it from. Save the information externally to a file on a CompactFlash card or USB memory stick. Alternatively, save the information internally to one of the four reference memories in the oscilloscope. 4. Push To File to save to a CompactFlash card or USB memory stick. To File This brings up the file manager screen. Use it to define a custom file name. Skip this step to use the default name and location. Editing File, Directory, Reference Waveform, or Instrument Setup Names. Give files descriptive names that you can recognize at a later date. To edit file names, directory names, reference waveform and instrument setup labels: 1. Push Save / Recall Menu. DPO4000 Series User Manual 177 Save and Recall Information 2. Push Save Screen Image, Save Waveform, or Save Setup. Save Screen Image Save Waveform Save Setup Recall Waveform Recall Setup Assign Save to Setup File Utilities 3. Enter the file manager by pushing the side-bezel menu To File item. To File 4. Turn multipurpose knob a to scroll through the file structure. D: is the CompactFlash drive. E: is the USB drive plugged into the USB port on the front of the oscilloscope. F: and G: are the USB drives plugged into the USB host ports on the rear of the oscilloscope. 178 DPO4000 Series User Manual Save and Recall Information 5. Push Select to open or close file folders. 6. Push the Menu Off button to cancel the save operation, or push a side-bezel menu OK Save. item to complete the operation. OK Save DPO4000 Series User Manual 179 Save and Recall Information Naming Your File. The oscilloscope gives all files it creates the default name tekxxxxx where xxxxx is an integer from 00000 to 99999. For example, the first time you save a file, that file is named tek00000. The next file is named tek00001. To define a file name of your own choosing: 1. Push Save / Recall Menu. 2. Push Save Screen Image, Save Waveform, or Save Setup. Save Screen Image Save Waveform Save Setup Recall Waveform Recall Setup Map Save Button File Utilities 3. Enter the file manager by pushing the side-bezel menu To File item. To File 180 DPO4000 Series User Manual Save and Recall Information 4. Push the front-panel Select or the lower-bezel menu Enter Character to select a character. 5. Push the Menu Off button to cancel the file naming operation or push a side-bezel menu Save to Selected File item to complete the operation. Save to Selected File DPO4000 Series User Manual 181 Save and Recall Information Saving a Waveform to File. When you push the To File side-bezel menu button, the oscilloscope changes the side- menu contents. The following table describes these side-bezel menu items for saving data to a mass storage file. Side-bezel menu button Description Internal File Format (.ISF) Sets the oscilloscope to save waveform data in internal waveform save file (.isf) format. This format is the fastest to write and creates the smallest-sized file. Use this format if you intend to recall a waveform to reference memory for viewing or measuring. Spreadsheet File Format (.CSV) Sets the oscilloscope to save waveform data as a comma-separated data file compatible with popular spreadsheet programs. This file cannot be recalled to reference memory. Saving a Waveform to Reference Memory. To save a waveform to nonvolatile memory inside the oscilloscope, first select the waveform that you want to save. Push the Save Waveform screen button. Then select one of the reference waveform locations. Four-channel models have four reference locations. Two-channel models have two reference locations. Saved waveforms contain only the most current acquisition. Gray-scale information, if any, is not saved. Displaying a Reference Waveform. To display a waveform stored in nonvolatile memory: 1. Push Ref R. 182 DPO4000 Series User Manual Save and Recall Information 2. Push R1, R2, R3, or R4. R 1 (On) R 2 (Off) R 3 (Off) R 4 (Off) Removing a Reference Waveform from the Display. To remove a reference waveform from the display: 1. Push Ref R. 2. Push the R1, R2, R3, or R4 screen button to select a reference waveform. R 1 (On) R 2 (Off) R 3 (Off) R 4 (Off) 3. Push the front-panel Ref or the appropriate lower-bezel R button again to remove the reference waveform from the display. The reference waveform is still in nonvolatile memory and can be displayed again. DPO4000 Series User Manual 183 Save and Recall Information Saving and Recalling Setups Setup information includes acquisition information, such as vertical, horizontal, trigger, cursor, and measurement information. It does not include communications information, such as GPIB addresses. To save the setup information: 1. Push Save / Recall Menu. 2. Push Save Setup or Recall Setup from the lower-bezel menu. Save Screen Image Save Waveform Save Setup Recall Waveform Recall Setup Assign Save to Setup File Utilities 184 DPO4000 Series User Manual Save and Recall Information Save Setup To File To Setup 1 3. From the resulting side-bezel menu, select the location to save the setup to or to recall it from. To save setup information to one of the ten internal setup memories in the oscilloscope, push the appropriate side-bezel button. To save setup information to a CompactFlash or USB file, push the To File button. To Setup 2 To Setup 3 – more – DPO4000 Series User Manual 185 Save and Recall Information 4. If you are saving information to a CompactFlash or USB memory device, turn multipurpose knob a to scroll through the file structure. D: is the CompactFlash drive. E: is the USB drive plugged into the USB port on the front of the oscilloscope. F: and G: are the USB drives plugged into the USB ports on the rear of the oscilloscope. Push Select to open or close file folders. Push the Menu Off button to cancel the save operation, or push a side-bezel menu Save to Selected File item to complete the operation. 186 DPO4000 Series User Manual Save and Recall Information Save 1 to Selected File Quick Tips Recalling the Default Setup. Push the front-panel Default Setup button to initialize the oscilloscope to a known setup. (See page 73, Using the Default Setup.) Saving with One Button Push After you have defined the save/recall parameters with the Save/Recall Menu button and menu, you can make saves to files with a single push of the Save button. For example, if you have defined the save operation to save waveform data to a USB drive, then each push of the Save button will save current waveform data to the defined USB drive. 1. To define the Save button behavior, push Save/Recall Menu. DPO4000 Series User Manual 187 Save and Recall Information 2. Push Assign Save button. Save Screen Image Save Waveform Save Setup Recall Waveform Recall Setup Assign Save to Setup File Utilities 3. Push the action to assign to the Save button. Assign Save to Screen Image Waveform Setup 4. From now on, when you push Save the button will perform the action that you just specified rather than having to navigate menus each time. 188 DPO4000 Series User Manual Save and Recall Information Printing a Hard Copy To print an image of what appears on the oscilloscope screen, do the following procedure. Connect a Printer to Your Oscilloscope Connect your printer to a USB port on the rear or front panel of the oscilloscope. Alternatively, you can print to networked printers through the Ethernet port. Set Up Print Parameters To set up the oscilloscope to print hard copies: 1. Push Utility. 2. Push System as many times as needed to select Print Setup from the resulting pop-up menu. Print Setup DPO4000 Series User Manual 189 Save and Recall Information System Print Setup Select Printer N/A Orientation Landscape Ink Saver On 3. Push Select Printer if you are changing the default printer. Turn multipurpose knob a to scroll through the list of available printers. Push Select to choose the desired printer. To add a USB printer to the list, plug the printer into the USB slot. The oscilloscope will automatically recognize it. To add an Ethernet printer to the list, use the instructions in the section titled Printing Over Ethernet. 190 DPO4000 Series User Manual Save and Recall Information 4. Select the image orientation (portrait or landscape). Landscape Portrait 5. Choose Ink Saver On or Off. The On selection will print out a copy with a clear (white) background. Ink Saver on Ink Saver off DPO4000 Series User Manual 191 Save and Recall Information Printing Over Ethernet To set up the oscilloscope to print over Ethernet: 1. Connect an Ethernet cable to the rear-panel Ethernet port. 2. Push Utility. 192 DPO4000 Series User Manual Save and Recall Information 3. Push System repeatedly until you select Print Setup. Print Setup 4. Push Select Printer. System Print Setup Select Printer (N/A) Orientation Landscape Ink Saver Off Select Printer 5. Push Add Network Printer. Add Network Printer Rename Printer DPO4000 Series User Manual 193 Save and Recall Information 6. Turn multipurpose knob a to scroll through the list of letters, numbers, and other characters to find the first character in the printer name that you want to enter. ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz 0123456789_=+-!@#$%^&*()[]{}<>/~’”\|:,.? 7. Push Select or Enter Character to let the oscilloscope know that you have picked the proper character to use. You can use the lower-bezel buttons to edit the name, as needed. Enter Character Back Space Delete Clear 8. Continue scrolling and pushing Select until you have entered all the desired characters. 194 DPO4000 Series User Manual Save and Recall Information 9. Push the down arrow key to move the character cursor down a row to the Server Name field. 10. Turn multipurpose knob a and push Select or Enter Character as often as needed to enter the name. 11. If desired, push the down arrow key to move the character cursor down a row to the Server IP Address: field. 12. Turn multipurpose knob a and push Select or Enter Character as often as needed to enter the name. Add Printer 13. When done, push OK Accept. OK Accept DPO4000 Series User Manual 195 Save and Recall Information NOTE. If you have multiple printers connected to the oscilloscope at the same time, the oscilloscope will print to the printer listed in the Utility > System > Print Setup > Select Printer menu item. Print to a Printer Once you have connected a printer to your oscilloscope and set up print parameters, you can print current screen images with a single push of a button: 1. Push the printer icon button in the lower left corner of the front panel. Erasing DPO4000 Memory You can erase all setup and waveform information saved in the nonvolatile memory with the TekSecure function. If you have acquired confidential data on your oscilloscope, you may want to execute the TekSecure function before you return the oscilloscope to general use. The TekSecure function: Replaces all waveforms in all reference memories with null values 196 DPO4000 Series User Manual Save and Recall Information Replaces the current front-panel setup and all stored setups with the default setup Displays a confirmation or warning message, depending on whether the verification is successful or unsuccessful To use TekSecure: 1. Push Utility. 2. Push System repeatedly until you select Config. Config 3. Push TekSecure. System Config Language English Set Date & Time TekSecure Erase Memory Version v1.00 DPO4000 Series User Manual 197 Save and Recall Information 4. Push OK Erase Setup and Ref Memory from the side-bezel menu. OK Erase Setup and Ref Memory To abort the procedure, push Menu Off. 198 DPO4000 Series User Manual Save and Recall Information 5. Power off the oscilloscope, and then power it back on to complete the process. DPO4000 Series User Manual 199 Use Application Modules Use Application Modules Optional application module packages extend the capability of your oscilloscope. Install up to four application modules at one time. Application modules go into the two slots with windows in the upper right corner of the front panel. Two additional slots are directly behind the two that you can see. Refer to the DPO4000 Series Application Module Installation Instructions that came with your application module for instructions on installing and testing an application module. Some modules are described below. Additional packages may be available. Contact your Tektronix representative or visit our Web site at www.tektronix.com for more information. Also, refer to Contacting Tektronix at the beginning of the manual. The DPO4EMBD Serial Triggering and Analysis Module adds triggering on packet level information in serial buses used in embedded designs (I2C and SPI), as well as analytical tools to help you efficiently analyze your serial bus. These include digital views of the signal, bus views, packet decoding, search tools, and event tables with timestamp information. The DPO4AUTO Serial Triggering and Analysis Module adds triggering on packet level information in serial buses used in automotive designs (CAN), as well as analytical tools to help you efficiently analyze your serial bus. These include digital views of the signal, bus views, packet decoding, search tools, and event tables with timestamp information. 200 DPO4000 Series User Manual Application Examples Application Examples This section contains ways to use your instrument in both common and advanced troubleshooting tasks. Taking Simple Measurements If you need to see a signal in a circuit, but you do not know the signal amplitude or frequency, connect the probe from channel 1 of the oscilloscope to the signal. Then display the signal and measure its frequency and peak-to-peak amplitude. DPO4000 Series User Manual 201 Application Examples Using Autoset To quickly display a signal: 1. Push Autoset. 202 DPO4000 Series User Manual Application Examples The oscilloscope sets vertical, horizontal, and trigger controls automatically. You can manually adjust any of these controls if you need to optimize the display of the waveform. When you are using more than one channel, the autoset function sets the vertical controls for each channel and uses the lowest-numbered active channel to set the horizontal and trigger controls. Selecting Automatic Measurements The oscilloscope can take automatic measurements of most displayed signals. To measure signal frequency and peak-to-peak amplitude: 1. Push Measure. 2. Push Select Measurement. Select Measurement a 1 Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors DPO4000 Series User Manual 203 Application Examples 3. Turn multipurpose knob a to select the channel from which you want to measure. For example, select channel 1. This step is only needed if you are acquiring data on more than one channel. 4. Select the Frequency measurement from the side-bezel menu. Frequency 5. Push -more- until you can select the Pk-Pk measurement. -more- 6. Push Menu Off. 204 DPO4000 Series User Manual Application Examples 7. Observe that the measurements appear on the screen and update as the signal changes. DPO4000 Series User Manual 205 Application Examples Measuring Two Signals In this example, you are testing a piece of equipment and need to measure the gain of its audio amplifier. You have an audio generator that can inject a test signal at the amplifier input. Connect two oscilloscope channels to the amplifier input and output as shown. Measure both signal levels and use these measurements to calculate the gain. 206 DPO4000 Series User Manual Application Examples To display the signals connected to channels 1 and 2: 1. Push channel 1 and channel 2 to activate both channels. 2. Push Autoset. To select measurements for the two channels: 1. Push Measure to see the measurement menu. DPO4000 Series User Manual 207 Application Examples 2. Push Select Measurement. Select Measurement a 1 Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors 3. Turn multipurpose knob a to select channel 1. 4. Page through the measurement menus until you find Amplitude. Select Amplitude. Amplitude 208 DPO4000 Series User Manual Application Examples 5. Turn multipurpose knob a to select channel 2. 6. Select Amplitude. Amplitude 7. Calculate the amplifier gain using the following equations: Gain = (output amplitude ÷ input amplitude) = (3.155 V ÷ 130.0 mV) = 24.27 Gain (dB) = 20 x log(24.27) = 27.7 dB DPO4000 Series User Manual 209 Application Examples Customizing Your Measurements In this example, you want to verify that the incoming signal to digital equipment meets its specifications. Specifically, the transition time from a low logic level (0.8 V) to a high logic level (2.0 V) must be 10 ns or less. To select the rise time measurement. 1. Push Measure. 210 DPO4000 Series User Manual Application Examples 2. Push Select Measurement. Select Measurement a 1 Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors 3. Turn multipurpose knob a to select channel 1. This step is only needed if you are acquiring data on more channels than just channel 1. 4. Select the Rise Time measurement from the side-bezel menu. Rise Time DPO4000 Series User Manual 211 Application Examples 5. Press Reference Levels. Reference Levels 6. Push Set Levels in to select units. Set Levels in % units 7. Push High Ref and turn multipurpose knob a to enter 2.00 V. If needed, push Fine to change the sensitivity of the multipurpose knob. High Ref a 2.00 V Mid Ref 8. Push Low Ref and turn multipurpose knob a to enter 800 mV. If needed, push Fine to change the sensitivity of the multipurpose knob. Low Ref a 800 mV 212 DPO4000 Series User Manual Application Examples Rise time is typically measured between the 10% and 90% amplitude levels of a signal. These are the default reference levels that the oscilloscope uses for rise time measurements, However, in this example, you need to measure the time that the signal takes to pass between the 0.8 V and 2.0 V levels. You can customize the rise time measurement to measure the signal transition time between any two reference levels. You can set each of these reference levels to a specific percent of the signal amplitude or to a specific level in vertical units (such as volts or amperes). Measuring Specific Events. Next you want to see the pulses in the incoming digital signal, but the pulse widths vary so it is hard to establish a stable trigger. To look at a snapshot of the digital signal, do this step: 1. Push Single to capture a single acquisition. Now you want to measure the width of each displayed pulse. You can use measurement gating to select a specific pulse to measure. To measure the second pulse: 1. Push Measure. DPO4000 Series User Manual 213 Application Examples 2. Push Select Measurement. Select measurement a 1 Remove Measurement Gating Statistics Reference Levels Indicators Configure Cursors 3. Turn multipurpose knob a to select channel 1. 4. Select Positive Pulse Width measurement. Positive Pulse Width 214 DPO4000 Series User Manual Application Examples 5. Push Gating. Select Measurement Remove Measurement Gating Off Statistics Off Reference Levels Indicators Configure Cursors 6. Select Between Cursors from the side-bezel menu to choose measurement gating using cursors. Between Cursors 7. Place one cursor to the left and one cursor to the right of the second pulse. DPO4000 Series User Manual 215 Application Examples 8. View the resulting width measurement (160 ms) for the second pulse. 216 DPO4000 Series User Manual Application Examples Analyzing Signal Detail In this example, you have a noisy signal displayed on the oscilloscope, and you need to know more about it. You suspect that the signal contains much more detail than you can currently see in the display. DPO4000 Series User Manual 217 Application Examples Looking at a Noisy Signal The signal appears noisy. You suspect that noise is causing problems in your circuit. To better analyze the noise: 1. Push Acquire. 2. Push Mode on the lower-bezel menu. Mode Record Length 10k Reset Horizontal Position Waveform Display 218 DPO4000 Series User Manual Application Examples 3. Push Peak Detect on the side-bezel menu. Sample Peak Detect Hi Res Envelope Average 4. Push Intensity and turn multipurpose knob a to see the noise more easily. DPO4000 Series User Manual 219 Application Examples 5. View the results on the display. Peak detect emphasizes noise spikes and glitches in your signal as narrow as 1 ns, even when the time base is set to a slow setting. 220 DPO4000 Series User Manual Application Examples Peak-detect and the other acquisition modes are explained earlier in this manual. (See page 75, Acquisition Concepts.) Separating the Signal from Noise Now you want to analyze the signal shape and ignore the noise. To reduce random noise in the oscilloscope display: 1. Push Acquire. 2. Push Mode. Mode Record Length Reset Horizontal Position Waveform Display 3. Push Average on the side-bezel menu. Average DPO4000 Series User Manual 221 Application Examples Averaging reduces random noise and makes it easier to see detail in a signal. In the example to the right, a ring shows on the rising and falling edges of the signal when the noise is removed. 222 DPO4000 Series User Manual Application Examples Taking Cursor Measurements You can use the cursors to take quick measurements on a waveform. To measure the ring frequency at the rising edge of the signal: 1. Push channel 1 to select the channel 1 signal. 2. Push Measure. 3. Push Configure Cursors. Select Measurement Remove Measurement Gating Statistics Reference Levels Indicators Configure Cursors DPO4000 Series User Manual 223 Application Examples 4. Push Vertical Bar Units repeatedly to select Hz (1/s). Vertical Bar Units Hz (1/s) 5. Push Cursors repeatedly until the two vertical bar cursors appear on the selected waveform. 6. Place one cursor on the first peak of the ring using multipurpose knob a. 7. If the cursor readout says that the cursors are linked, push Select to unlink them. 224 DPO4000 Series User Manual Application Examples 8. Place the other cursor on the next peak of the ring using multipurpose knob b. 9. The cursor Δ readout shows the measured ring frequency is 227 kHz. DPO4000 Series User Manual 225 Application Examples Triggering on a Video Signal The DPO4000 Series of oscilloscopes supports triggering on NTSC, SECAM, and PAL signals. In this example, you are testing the video circuit in a piece of medical equipment and need to display the video output signal. The video output is an NTSC standard signal. Use the video signal to obtain a stable display. To trigger on the video fields: 1. Push Trigger Menu. 226 DPO4000 Series User Manual Application Examples 2. Push Type repeatedly to select Video. Video 3. Push Standard repeatedly to select 525/NTSC. Type Video Standard 525/NTSC Source 1 Trigger on All Lines Mode Auto & Holdoff 4. Push Trigger On. 5. Select Odd Fields. Odd Fields If the signal had been noninterlaced, you could choose to trigger on All Fields. 6. Turn the Horizontal Scale knob to see a complete field across the screen. DPO4000 Series User Manual 227 Application Examples 7. View results. Triggering on Lines Triggering on Lines. To look at the video lines in the field: 1. Push Trigger Menu. 228 DPO4000 Series User Manual Application Examples 2. Push Type repeatedly to select Video. Video Type Video Standard 525/NTSC Source 1 Trigger On All Lines Mode Auto & Holdoff 3. Push Trigger On. 4. Select All Lines. All Lines 5. Adjust Horizontal Scale to see a complete video line across the screen. DPO4000 Series User Manual 229 Application Examples 6. Observe the results. Capturing a Single-Shot Signal In this example, the reliability of a reed relay in a piece of equipment has been poor, and you need to investigate the problem. You suspect that the relay contacts arc when the relay opens. The fastest you can open and close the relay is about once per minute, so you need to capture the voltage across the relay as a single-shot acquisition. To set up for a single-shot acquisition: 1. Adjust the Vertical Scale and Horizontal Scale to appropriate ranges for the signal you expect to see. 230 DPO4000 Series User Manual Application Examples 2. Push Acquire. 3. Push Mode. 4. Select Sample. 5. Push Trigger Menu. 6. Push Slope and . 7. Turn the Trigger Level knob to adjust the trigger level to a voltage midway between the open and closed voltages of the replay. DPO4000 Series User Manual 231 Application Examples 8. Push Single (single sequence). When the relay opens, the oscilloscope triggers and captures the event. The Single sequence button disables auto triggering so that only a valid triggered signal is acquired. 232 DPO4000 Series User Manual Application Examples Optimizing the Acquisition The initial acquisition shows the relay contact beginning to open at the trigger point. This is followed by large spikes that indicate contact bounce and inductance in the circuit. The inductance can cause contact arcing and premature relay failure. Before you take the next acquisition, you can adjust the vertical and horizontal controls to give you a preview of how the next acquisition might appear. As you adjust these controls, the current acquisition is repositioned, expanded, or compressed. This preview is useful to optimize the settings before the next single-shot event is captured. When the next acquisition is captured with the new vertical and horizontal settings, you can see more detail about the relay contact opening. You can now see that the contact bounces several times as it opens. DPO4000 Series User Manual 233 Application Examples Using the Horizontal Zoom Function To take a close look at a particular point on the acquired waveform, use the horizontal zoom function. To look closely at the point where the relay contact first begins to open: 1. Turn the Zoom knob. 2. Turn the Pan knob to place the center of the zoom box close to where the relay contact begins to open. 3. Turn the Zoom knob to magnify the waveform in the zoom window. 234 DPO4000 Series User Manual Application Examples The ragged waveform and the inductive load in the circuit suggest that the relay contact may be arcing as it opens. The zoom function works equally well when the acquisition is running or is stopped. Horizontal position and scale changes affect only the display, not the next acquisition. Correlating Data With a TLA5000 Logic Analyzer To troubleshoot designs with fast clock edges and data rates, it helps to view analog characteristics of digital signals in relation to complex digital events in the circuit. You can do that with iView, which lets you transfer analog waveforms from the oscilloscope to the logic analyzer display. You can then view time-correlated analog and digital signals side-by-side and use this to pinpoint sources of glitches and other problems. DPO4000 Series User Manual 235 Application Examples The iView External Oscilloscope Cable allows you to connect your logic analyzer to a Tektronix oscilloscope. This enables communication between the two instruments. The Add External Oscilloscope wizard, which is available from the TLA application System menu, guides you through the process of connecting the iView cable between your logic analyzer and oscilloscope. The TLA also provides a setup window to assist you in verifying, changing, and testing the oscilloscope settings. Before acquiring and displaying a waveform you must establish a connection between your Tektronix logic analyzer and oscilloscope using the Add External Oscilloscope wizard. To do this: 1. Select Add iView External Oscilloscope ... from the logic analyzer System menu. 236 DPO4000 Series User Manual Application Examples 2. Select your model of oscilloscope. 3. Follow the on-screen instructions, and then click Next. 4. See your Tektronix Logic Analyzer documentation for more information on correlating data between a DPO4000 Series Oscilloscope and a Tektronix Logic Analyzer. DPO4000 Series User Manual 237 Application Examples Tracking Down Bus Anomalies In this example, you are testing your new I2C circuit. Something is not working. You tell the master IC to send a message to the slave IC. Then you expect to receive data back and an LED to light. The light never goes on. Where in the ten or so commands that were sent out did the problem occur? Once you locate the problem location, how do you determine what went wrong? You can use your DPO4000 Series oscilloscope, with its serial triggering and long-record length management features, to track down the problem in both the physical layer and in the protocol layer of the bus. Basic strategy First, you will display and acquire the bus signal by setting up the bus parameters and trigger. Then, you will search through each packet with the search/mark functions. NOTE. Triggering on bus signals requires use of the DPO4EMBD or the DPO4AUTO Serial Triggering and Analysis Module. 238 DPO4000 Series User Manual Application Examples 1. Connect the channel 1 probe to the clock line. 2. Connect the channel 2 probe to the data line. 3. Push Autoset. DPO4000 Series User Manual 239 Application Examples 4. Push the B1 button and enter the parameters of your I2C bus in the resulting screen menus. 5. Push Trigger Menu. 6. Push Type to select Bus. Enter trigger parameters in the resulting screen menus. Type Bus Source Bus B1 (I2C) Trigger On Address Address 07F Direction Read Mode Auto & Holdoff 240 DPO4000 Series User Manual Application Examples 7. Analyze the physical layer. For example, you can use the cursors for manual measurements. (See page 144, Taking Manual Measurements with Cursors.) You can also use the automated measurements. (See page 129, Taking Automatic Measurements.) 8. Push Search. Set Search Marks to On. Enter a search type, source, and other parameters as relevant on the lower-bezel menu and associated side-bezel menus. (See page 163, Managing Long Record Length Waveforms.) 9. Jump ahead to the next search point by pushing the right arrow key. Push it again and again until you see all the events. Jump back with the left arrow key. Do you have all the packets that you expected to have? If not, at least you have narrowed your search down to the last packet sent. DPO4000 Series User Manual 241 Application Examples 10. Analyze the decoded packets in the protocol layer. Did you send the data bytes in the correct order? Did you use the correct address? 242 DPO4000 Series User Manual Index Index Symbols and Numbers 50 Ω protection, 128 A Accessories, 1 Acquire button, 49, 80, 112, 218, 221 Acquisition input channels and digitizers, 75 modes defined, 78 readout, 60 sampling, 75 Adapter TEK-USB-488, 4 TPA-BNC, 4, 10 Adding waveform, 112 Advanced math, 157 Altitude DPO4000, 7 P6139A, 8 Analysis and Connectivity, xii Application module DPO4AUTO, 84 DPO4EMBD, 84 Application Module, xiii, 19 Applications modules, 200 Attenuation, 127 Auto trigger mode, 92 Autoset, 74, 202 Autoset button, 17, 49, 56, 71, 74, 202, 207 Autoset undo, 74 Auxiliary readout, 64 Average acquisition mode, 79 BB Trigger, 109 B1 / B2 button, 51, 84, 85, 102 Backlight intensity, 119 Bandwidth, x Before Installation, 1 Blackman-Harris FFT window, 157 BNC interface, 10 Bus button, 84, 85, 102 menu, 51, 85 Bus trigger, defined, 102 Buses, 84, 102 Button Acquire, 49, 80, 112, 218, 221 Autoset, 17, 49, 56, 71, 74, 202, 207 B1 / B2, 51, 84, 85, 102 bus, 84, 85, 102 Channel, 50 Cursors, 52, 144, 224 Default Setup, 50, 58, 73 Fine, 48, 52, 53, 54, 55, 57 Force Trig, 56, 93 hard copy, 57, 196 Intensity, 115 M, 51, 150, 153 Math, 51, 150, 153 Measure, 49, 129, 139, 140, 203, 207, 210, 213 Menu Off, 58, 204 Next, 55 play-pause, 167 Play-pause, 54 Previous, 54 printer icon, 57, 196 Ref, 51, 160, 182 DPO4000 Series User Manual 243 Index Run/Stop, 56, 83, 111 Save / Recall, 50, 58, 174 Search, 49, 170 Select, 53, 224 Set / Clear Mark, 55, 169 Set to 50%, 56, 97 Single, 56, 111, 213, 232 Test, 49 Trigger, 49 Trigger level, 56 Trigger menu, 226 Trigger Menu, 98 Utility, 20, 23, 26, 50, 117, 118, 189 Vertical, 50 Zoom, 54 C Calibration, 25, 27 Calibration certificate, 2 CAN, 51, 84, 102 Channel button, 50 Channel readout, 64 Clearance, DPO4000, 6 Communications, 35, 40 CompactFlash, x, 2, 5, 50, 58, 174 Compensate probe, 17 Compensate signal path, 25 Confidential data, 196 Connectivity, 2, 35, 40 Connector, side-panel, 67 Connectors front-panel, 66 rear-panel, 68 Controls, 45 Coupling, trigger, 94 Cover, front, 2 Cross Hair graticule style, 118 Cursor readout, 62, 149 Cursor, measurements, 144 Cursors, 144 button, 52, 144, 224 linking, 145 Cursors menu, 144 D Date and time, changing, 23 Default setup, 187 Default Setup, 73 button, 50, 58, 73 menu, 50 Undo, 73 Delayed trigger, 107 Depth, DPO4000, 6 Deskew, 127 Display persistence, 112 style, 112 Displaying, reference waveforms, 182 Documentation, xii DPO4AUTO, 84 DPO4EMBD, 84 Drivers, 35, 39 Dual waveform math, 150 Ee *Scope, 40 Edge trigger, defined, 99 Envelope acquisition mode, 79 Erase setup and ref memory, 196 Ethernet, x, 37, 40, 41 port, 68 printing, 192 Event Table, 88, 89 Excel, 34 Expansion point icon, 61 244 DPO4000 Series User Manual Index FF actory calibration, 27 FFT Blackman-Harris, 157 controls, 153 Hamming, 156 Hanning, 157 Rectangular, 156 File format, 175 Internal File Format (ISF), 182 Spreadsheet file format (.CSV), 182 File system, 174, 177, 180 Fine, 53 Fine button, 48, 52, 54, 55, 57 Firmware upgrade, 28 Force Trig button, 56, 93 Frame graticule style, 118 Frequency, Input power DPO4000, 6 Front cover, 2 Front panel, 45 Front-panel connectors, 66 Front-panel overlay, 22 Full graticule style, 118 Functional check, 15 G Gating, 137 GPIB, 36, 38, 68 GPIB address, 38 Graticule Cross Hair, 118 Frame, 118 Full, 118 Grid, 118 intensity, 115 styles, 117 Grid graticule style, 118 Ground, 11 Ground lead, 19 Ground strap, 67 H Hamming FFT window, 156 Hanning FFT window, 157 Hard copy, 57, 189 Height, DPO4000, 6 Hi Res acquisition mode, 79 Holdoff, trigger, 93 Horizontal delay, 94 Horizontal position, 55, 94, 95, 120, 156, 234, 235 and math waveforms, 152 defined, 72 Horizontal position/scale readout, 64 Horizontal scale, 55, 120, 156, 227, 229, 230, 234 and math waveforms, 152 defined, 72 How to erase memory, 196 print a hard copy, 189 recall setups, 184 recall waveforms, 174 save screen images, 174 save setups, 184 save waveforms, 174 Humidity DPO4000, 7 P6139A, 9 I I2C, 51, 84, 102 DPO4000 Series User Manual 245 Index Icon Expansion point, 61 Trigger level, 63 Trigger position, 61 Image orientation, 175, 191 Impedance, 123 Indicator, waveform baseline, 65 Infinite persistence, 115 Ink Saver, 175, 191 Inner knob, 54, 152 Installing, application modules, xiii Intensity button, 115 Internal File Format, 182 K Knob inner, 54, 152 Multipurpose, 24, 48, 53, 54, 80, 86, 177, 224, 225 outer, 54 pan, 54, 166, 169 Trigger level, 97 Vertical position, 57, 72 Vertical scale, 57, 72 zoom, 54, 152, 164 LL abView, 34 Landscape, 175, 191 Language change, 20 overlay, 22 Level, trigger, 96 Logic trigger, defined, 100 Long record length, 238 Long record length management, 163 MM button, 51, 150, 153 Main trigger, 107 Mark, 169 Math Advanced, 157 button, 51, 150, 153 Dual waveform, 150 FFT, 153 menu, 51 waveforms, 150 Measure button, 49, 129, 139, 140, 203, 207, 210, 213 Measurement menu, 49 Measurements automatic, 129 cursor, 144 defined, 131 reference levels, 142 snapshot, 140 statistics, 139 Memory, erasure of, 196 Menu Bus, 51, 85 Cursors, 144 Default Setup, 50 Math, 51 Measurement, 49 Reference, 51, 160, 161 Save / Recall, 50, 58, 174 Trigger, 49, 98, 108, 226 Utility, 20, 23, 50, 57, 117, 189 Vertical, 50, 122 Menu buttons, 49 Menu Off button, 58, 204 Menus, 45 Mode, roll, 83 Multipurpose knob, 48, 53, 54, 80, 86, 177, 224, 225 246 DPO4000 Series User Manual Index N Network printing, 192 Next button, 55 Normal trigger mode, 92 O Offset and position, 128 OpenChoice, 2, 35 Operating specifications, 6 Orientation of the image, 175, 191 Outer knob, 54 Overlay, 22 P Pan, 164, 166 knob, 54, 166, 169 Pause, 166 Peak detect acquisition mode, 79 Performance verification, xii Persistence display, 112 infinite, 115 variable, 115 Play, 166 Play-pause button, 54, 167 Play-pause mode, 167 Pollution Degree DPO4000, 7 P6139A, 9 Portrait, 175, 191 Position Horizontal, 94, 95, 120, 156, 234, 235 Vertical, 121 Position and offset, 128 Posttrigger, 91, 96 Power cord, 3 input, 69 off, 14 removing, 14 supply, 11 switch, 57 Power consumption, DPO4000, 6 Predefined math expressions, 150 Pretrigger, 91, 96 Previous button, 54 Print, 57, 189 Printing a hard copy, 189 Printing, Ethernet, 192 Probe Comp, 16 Probe compensation, 17 Probes BNC, 10 connecting, 10 ground lead, 19 TEK-USB-488 Adapter, 4 TekVPI, 10 TPA-BNC Adapter, 4, 10 Programmer Commands, xii Pulse/Width trigger, defined, 100 R Rackmount, 4 Readout Acquisition, 60 Auxiliary, 64 Channel, 64 Cursor, 62, 149 Horizontal position/scale, 64 Record length/sampling rate, 63 Trigger, 63, 107 Trigger status, 62 Rear-panel connectors, 68 Recalling setups, 184 waveforms, 174 Record length, x DPO4000 Series User Manual 247 Index Record length/sampling rate readout, 63 Rectangular FFT window, 156 Ref button, 51, 160 Ref R, 182 Reference button, 182 Reference levels, 142 Reference menu, 51, 160, 161 Reference waveforms, 160 displaying, 182 removing, 161, 183 saving, 182 saving 10M waveforms, 162 Related documents, xii Removing reference waveforms, 183 Removing reference waveforms, 161 Removing waveform, 112 Rise/Fall trigger, defined, 101 Roll mode, 83 Run/Stop button, 56, 83, 111 Runt trigger, defined, 100 SS afety Summary, v Sample acquisition mode, 78 Sample rates, x Sampling process, defined, 75 Sampling, real-time, 76 Save / Recall menu, 50, 58, 174 Save / Recall Menu button, 50 Save / Recall Save button, 58, 174 Saving reference waveforms, 182 screen images, 174 waveforms, 174 Saving and recalling Information, 174 Saving setups, 184 Scale Horizontal, 55, 120, 156, 227, 229, 230, 234 Vertical, 121, 230 Search, 169 Search / Mark, 238 Search button, 49, 170 Securing DPO4000 memory, 196 Select button, 53, 224 Sequential triggering, 107 Serial, 84, 102, 238 Service information, xiii Set / Clear Mark button, 55, 169 Set to 50% button, 56, 97 Setup default, 58, 187 Default, 73 Setup and Hold trigger, defined, 101 Side panel connector, 67 Signal path compensation, 25 Single button, 56, 111, 213, 232 Single sequence, 83, 111 Slope, trigger, 96 Snapshot, 140 Software drivers, 35, 39 Software, optional, 200 SPC, 25 Specifications, xii operating, 6 power supply, 11 SPI, 51, 84, 102 Spreadsheet file format (.CSV), 182 Start an acquisition, 111 Statistics, 139 Stop an acquisition, 111 Switch, power, 57 T Table, Event, 88, 89 TDSPCS1, 35 248 DPO4000 Series User Manual Index TEK-USB-488 Adapter, 36, 38, 68 TEK-USB–488 Adapter, 4 TekSecure, 196 TekVPI, 10 Temperature DPO4000, 6 P6139A, 8 Termination, 123 Test button, 49 TPA-BNC Adapter, 4, 10 Transit case, 4 Transition trigger, defined, 101 Trigger concepts, 91 coupling, 94 delayed, 107 event, defined, 91 forcing, 92 holdoff, 93 level, 96 modes, 92, 98 posttrigger, 91, 96 pretrigger, 91, 96 readout, 107 sequential, 107 Serial, 84, 102, 238 slope, 96 Trigger level button, 56 Icon, 63 knob, 97 Trigger menu, 49, 98, 108, 226 Trigger menu button, 226 Trigger Menu button, 98 Trigger modes Auto, 92 Normal, 92 Trigger position icon, 61 Trigger readout, 63 Trigger status readout, 62 Trigger types, defined, 99 U Undo Autoset, 74 Default Setup, 73 Upgrading firmware, 28 USB, x, 5, 36, 39, 50, 58, 69, 174, 189 port, 68 USBTMC, 68 User marks, 169 Utility button, 20, 23, 26, 50, 117, 118, 189 Utility menu, 20, 23, 50, 57, 117 V Variable persistence, 115 Versatile Probe Interface, 10 Vertical button, 50 menu, 50, 122 Position, 121 position and autoset, 75 position and offset, 128 Position knob, 57, 72 Scale, 121, 230 Scale knob, 57, 72 Vibration, DPO4000, 7 Video lines, 228 port, 68 Video trigger, defined, 101 View waveform record, 61 Voltage, Input DPO4000, 6 P6139A, 8 DPO4000 Series User Manual 249 Index Voltage, Output, P6139A, 8 W Waveform adding, 112 display style, 112 intensity, 115 pan, 164, 166 pause, 166 play, 166 play-pause, 167 record defined, 77 removing, 112 search and mark, 169 user marks, 169 zoom, 164 Waveform baseline indicator, 65 Waveform record, 77 Waveform record view, 61 Weight DPO4000, 6 Width DPO4000, 6 ZZ oom, 164 button, 54 graticule size, 166 Horizontal, 234 knob, 54, 164 PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor Rev. 03 — 11 December 2009 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −100 V IC collector current - - −1 A ICM peak collector current single pulse; tp ≤ 1 ms - - −3 A RCEsat collector-emitter saturation resistance IC = −1 A; IB = −100 mA [1] - 170 320 mΩ PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 2 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Symbol 1 base 2 collector 3 emitter 4 collector 1 2 3 4 sym028 2, 4 3 1 Table 3. Ordering information Type number Package Name Description Version PBSS9110Z SC-73 plastic surface-mounted package with increased heat sink; 4 leads SOT223 Table 4. Marking codes Type number Marking code PBSS9110Z PB9110 Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −120 V VCEO collector-emitter voltage open base - −100 V VEBO emitter-base voltage open collector - −5 V IC collector current - −1 A ICM peak collector current single pulse; tp ≤ 1 ms - −3 A IB base current - −0.3 A Ptot total power dissipation Tamb ≤ 25 °C [1] - 0.65 W [2] - 1 W [3] - 1.4 W PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 3 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1cm2. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6cm2. 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1cm2. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6cm2. Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C (1) FR4 PCB, mounting pad for collector 6cm2 (2) FR4 PCB, mounting pad for collector 1cm2 (3) FR4 PCB, standard footprint Fig 1. Power derating curves Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb (°C) 0 40 80 120 160 001aaa508 0.8 0.4 1.2 1.6 Ptot (W) 0 (1) (2) (3) Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1]- - 192 K/W [2]- - 125 K/W [3]- - 89 K/W Rth(j-sp) thermal resistance from junction to solder point - - 17 K/W PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 4 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor FR4 PCB, standard footprint Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values FR4 PCB, mounting pad for collector 1cm2 Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aaa819 10 1 102 103 Zth(j-a) (K/W) 10−1 10−5 10−4 10−2 10−1 10 102 tp (s) 10−3 1 103 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 006aaa820 10 1 102 103 Zth(j-a) (K/W) 10−1 10−5 10−4 10−2 10−1 10 102 tp (s) 10−3 1 103 duty cycle = 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 1 PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 5 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor FR4 PCB, mounting pad for collector 6cm2 Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aaa821 10 1 102 103 Zth(j-a) (K/W) 10−1 10−5 10−4 10−2 10−1 10 102 tp (s) 10−3 1 103 duty cycle = 1 0.75 0.5 0.33 0.2 0.1 0.05 0.02 0.01 0 PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 6 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 7. Characteristics [1] Pulse test: tp ≤ 300 μs; δ ≤ 0.02. Table 7. Characteristics Tamb = 25°C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = −80 V; IE = 0 A - - −100 nA VCB = −80 V; IE = 0 A; Tj = 150 °C - - −50 μA ICES collector-emitter cut-off current VCE = −80 V; VBE = 0 V - - −100 nA IEBO emitter-base cut-off current VEB = −4 V; IC = 0 A - - −100 nA hFE DC current gain VCE = −5 V; IC = −1 mA 150 - - VCE = −5 V; IC = −250 mA 150 - - VCE = −5 V; IC = −0.5 A [1] 150 - 450 VCE = −5 V; IC = −1 A [1] 125 - - VCEsat collector-emitter saturation voltage IC = −250 mA; IB = −25 mA - - −120 mV IC = −500 mA; IB = −50 mA [1]- - −180 mV IC = −1 A; IB = −100 mA [1]- - −320 mV RCEsat collector-emitter saturation resistance IC = −1 A; IB = −100 mA [1] - 170 320 mΩ VBEsat base-emitter saturation voltage IC = −1 A; IB = −100 mA [1]- - −1.1 V VBEon base-emitter turn-on voltage VCE = −5 V; IC = −1 A [1]- - −1.0 V td delay time VCC = −10 V; IC = −0.5 A; IBon = −0.025 A; IBoff = 0.025 A - 20 - ns tr rise time - 60 - ns ton turn-on time - 80 - ns ts storage time - 290 - ns tf fall time - 120 - ns toff turn-off time - 410 - ns fT transition frequency VCE = −10 V; IC = −50 mA; f = 100 MHz 100 - - MHz Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 1 MHz - - 17 pF PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 7 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor VCE = −10 V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 5. DC current gain as a function of collector current; typical values Fig 6. Collector current as a function of collector-emitter voltage; typical values VCE = −10 V (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C IC/IB = 10 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 7. Base-emitter voltage as a function of collector current; typical values Fig 8. Base-emitter saturation voltage as a function of collector current; typical values 001aaa376 200 400 600 hFE 0 IC (mA) −10−1 −1 −10 −102 −103 −104 (1) (2) (3) VCE (V) 0 −1 −2 −3 −4 −5 001aaa384 −0.8 −1.2 −0.4 −1.6 −2 IC (A) 0 IB (mA) = −45 −40.5 −36 −31.5 −27 −22.5 −18 −13.5 −9 −4.5 001aaa377 −0.4 −0.8 −1.2 VBE (V) 0 IC (mA) −10−1 −1 −10 −102 −103 −104 (1) (2) (3) 001aaa381 IC (mA) −10−1 −1 −10 −102 −103 −104 −1 −10 VBEsat (V) −10−1 (1) (2) (3) PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 8 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor IC/IB = 10 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C (1) IC/IB = 50 (2) IC/IB = 20 Fig 9. Collector-emitter saturation voltage as a function of collector current; typical values Fig 10. Collector-emitter saturation voltage as a function of collector current; typical values IC/IB = 10 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Tamb = 25 °C (1) IC/IB = 50 (2) IC/IB = 20 Fig 11. Collector-emitter saturation resistance as a function of collector current; typical values Fig 12. Collector-emitter saturation resistance as a function of collector current; typical values 001aaa378 IC (mA) −10−1 −1 −10 −102 −103 −104 −10−1 −1 VCEsat (V) −10−2 (1) (2) (3) 001aaa380 IC (mA) −10−1 −1 −10 −102 −103 −104 −10−1 −1 VCEsat (V) −10−2 (1) (2) 001aaa382 IC (mA) −10−1 −1 −10 −102 −103 −104 1 10 102 103 RCEsat (Ω) 10−1 (1) (2) (3) 001aaa383 IC (mA) −10−1 −1 −10 −102 −103 −104 1 10 102 103 RCEsat (Ω) 10−1 (1) (2) PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 9 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 8. Test information Fig 13. BISS transistor switching time definition VCC = −10 V; IC = −0.5 A; IBon = −0.025 A; IBoff = 0.025 A Fig 14. Test circuit for switching times 006aaa266 −IBon (100 %) −IB input pulse (idealized waveform) −IBoff 90 % 10 % −IC (100 %) −IC td ton 90 % 10 % tr output pulse (idealized waveform) tf t ts toff RC R2 R1 DUT mgd624 Vo RB (probe) 450 Ω (probe) 450 Ω oscilloscope oscilloscope VBB VI VCC PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 10 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. Fig 15. Package outline SOT223 (SC-73) Dimensions in mm 04-11-10 6.7 6.3 3.1 2.9 1.8 1.5 7.3 6.7 3.7 3.3 1.1 0.7 1 2 3 4 4.6 2.3 0.8 0.6 0.32 0.22 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 1000 4000 PBSS9110Z SOT223 8 mm pitch, 12 mm tape and reel -115 -135 PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 11 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 11. Soldering Fig 16. Reflow soldering footprint SOT223 (SC-73) Fig 17. Wave soldering footprint SOT223 (SC-73) sot223_fr 1.2 (4×) 1.2 (3×) 1.3 (4×) 1.3 (3×) 6.15 7 3.85 3.6 3.5 0.3 3.9 7.65 2.3 2.3 6.1 4 1 2 3 solder lands solder resist occupied area solder paste Dimensions in mm sot223_fw 1.9 6.7 8.9 8.7 1.9 (3×) 1.9 1.1 (2×) 6.2 2.7 2.7 2 4 1 3 solder lands solder resist occupied area preferred transport direction during soldering Dimensions in mm PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 12 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PBSS9110Z_3 20091211 Product data sheet - PBSS9110Z_2 Modifications: • This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content. • Figure 16 “Reflow soldering footprint SOT223 (SC-73)”: updated • Figure 17 “Wave soldering footprint SOT223 (SC-73)”: updated PBSS9110Z_2 20060724 Product data sheet - PBSS9110Z_1 PBSS9110Z_1 20040609 Product data sheet - - PBSS9110Z_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 11 December 2009 13 of 14 NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. NXP Semiconductors PBSS9110Z 100 V, 1 A PNP low VCEsat (BISS) transistor © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 December 2009 Document identifier: PBSS9110Z_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. This document was generated on 01/06/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 43020-1200 Status: Active Overview: Micro-Fit 3.0™ Connectors Description: Micro-Fit 3.0™ Plug Housing, Dual Row, with Panel Mount Ears, 12 Circuits Documents: 3D Model Test Summary TS-43045-001 (PDF) Drawing (PDF) RoHS Certificate of Compliance (PDF) Product Specification PS-43045 (PDF) Product Literature (PDF) Packaging Specification PK-43020-001 (PDF) Agency Certification CSA LR19980 TUV R72081037 UL E29179 General Product Family Crimp Housings Series 43020 Application Power, Wire-to-Wire Comments Glow Wire Equivalent Part Number 43020-1208 Overview Micro-Fit 3.0™ Connectors Product Literature Order No 987650-5984 Product Name Micro-Fit 3.0™ UPC 800754383530 Physical Circuits (maximum) 12 Circuits Detail 12 Color - Resin Black Flammability 94V-0 Gender Male Glow-Wire Compliant No Lock to Mating Part Yes Material - Resin Polyester Net Weight 1.476/g Number of Rows 2 Packaging Type Bag Panel Mount Yes Pitch - Mating Interface 3.00mm Pitch - Termination Interface 3.00mm Polarized to Mating Part Yes Stackable No Temperature Range - Operating -40°C to +105°C Electrical Current - Maximum per Contact 5A Material Info Reference - Drawing Numbers Packaging Specification PK-43020-001 Product Specification PS-43045, RPS-43045-003, RPS-43045-004 Sales Drawing SDA-43020-**** Test Summary TS-43045-001 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 43020Series Mates With 43025 Micro-Fit 3.0™ Receptacle Housing Use With Micro-Fit 3.0™ Crimp Terminal, MaleThis document was generated on 01/06/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 07/03/2013 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 87439-0800 Status: Active Overview: Pico-Spox™ Description: 1.50mm Pitch Pico-SPOX™ Wire-to-Board Housing, 8 Circuits, Off-White Housing Documents: 3D Model RoHS Certificate of Compliance (PDF) Drawing (PDF) Product Literature (PDF) Product Specification PS-87437 (PDF) Agency Certification CSA LR19980 UL E29179 General Product Family Crimp Housings Series 87439 Application Signal, Wire-to-Board MolexKits Yes Overview Pico-Spox™ Product Literature Order No USA-235 Product Name Pico-SPOX™ UPC 800754313278 Physical Circuits (maximum) 8 Color - Resin Natural Flammability 94V-0 Gender Female Glow-Wire Compliant No Lock to Mating Part Yes Material - Resin Nylon Net Weight 0.120/g Number of Rows 1 Packaging Type Bag Panel Mount No Pitch - Mating Interface 1.50mm Polarized to Mating Part Yes Stackable No Temperature Range - Operating -55°C to +105°C Electrical Current - Maximum per Contact 2.5A Material Info Reference - Drawing Numbers Product Specification PS-87437, RPS-87437, RPS-87437-001, RPS-87437-200 Sales Drawing SD-87439-**00 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 87439Series Mates With Pico-SPOX™ Wire-to-Board Header 87437 , 87438 Use With 87421 Pico-SPOX™ Crimp Terminal This document was generated on 07/03/2013 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 01/08/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 43160-3102 Status: Active Overview: Sabre™ Power Connector Description: 7.50mm Pitch Sabre™ Header, Right Angle, 2 Circuits, Glow Wire Compatible. Recommended PCB Thickness 1.60mm, with Board Lock Documents: 3D Model RoHS Certificate of Compliance (PDF) Drawing (PDF) Product Literature (PDF) Product Specification PSX-44441-9999 (PDF) Agency Certification CSA LR19980 TUV R72130381 UL E29179 General Product Family PCB Headers Series 43160 Application Power, Wire-to-Board Comments "Fully Polarized, high power wire to board and wire to wire connector system

This Molex product is manufactured from material that has the following ratings, tested by independent agencies:. a) A Glow Wire Ignition Temperature (GWIT) of at least 775 deg C per IEC 60695-2-13.. b) A Glow Wire Flammability Index (GWFI) above 850 deg C per IEC 60695-2-12.and hence complies with the requirements set out in the International Standard IEC 60335-1 5th edition - household and similar electrical appliances - safety, section 30 Resistance to heat and fire.

The customers using this product must determine its suitability for use in their particular application through testing or other acceptable means as described in end-product glow-wire flammability test standard IEC 60695-2-11 and any applicable product end-use standard(s).

If it is determined during the customer’s evaluation of suitability, that higher performance is required, please contact Molex for possible product options." Overview Sabre™ Power Connector Product Literature Order No 987650-5662 Product Name Sabre™ UPC 800754378185 Physical Breakaway No Circuits (Loaded) 2 Circuits (maximum) 2 Color - Resin Black Durability (mating cycles max) 25 First Mate / Last Break No Flammability 94V-0 Glow-Wire Compliant Yes Guide to Mating Part No Keying to Mating Part Yes Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Not Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 43160Series Mates With 44441-2002 Sabre™ Receptacle Housing Lock to Mating Part Yes Material - Metal Brass Material - Plating Mating Tin Material - Plating Termination Tin Material - Resin High Temperature Thermoplastic Net Weight 3.331/g Number of Rows 1 Orientation Right Angle PC Tail Length 3.81mm PCB Locator Yes PCB Retention Yes PCB Thickness - Recommended 1.60mm Packaging Type Tray Pitch - Mating Interface 7.50mm Pitch - Termination Interface 7.50mm Plating min - Mating 0.889μm Plating min - Termination 0.889μm Polarized to Mating Part Yes Polarized to PCB Yes Shrouded Fully Stackable No Surface Mount Compatible (SMC) No Temperature Range - Operating -40°C to +75°C Termination Interface: Style Through Hole Electrical Current - Maximum per Contact 18A Voltage - Maximum 600V Solder Process Data Duration at Max. Process Temperature (seconds) 5 Lead-free Process Capability Wave Capable (TH only) Max. Cycles at Max. Process Temperature 1 Process Temperature max. C 235 Material Info Reference - Drawing Numbers Product Specification PSX-44441-9999 Sales Drawing SDA-43160-**** This document was generated on 01/08/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 01/06/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 39-00-0038 Status: Active Overview: Mini-Fit Jr.™ Power Connectors Description: Mini-Fit® Female Crimp Terminal, Tin (Sn) over Copper (Cu) Plated Brass, 18-24 AWG, Reel Documents: Drawing (PDF) Product Specification PS-52034-003 (PDF) Product Specification PS-51010-005 (PDF) Product Specification PS-52034-004 (PDF) Product Specification PS-51010-006 (PDF) Product Specification PS-5556-001 (PDF) Product Specification PS-51045-001 (PDF) Product Specification PS-5556-002 (PDF) Product Specification PS-51045-002 (PDF) Packaging Specification PK-5556-001 (PDF) Product Specification PS-51045-004 (PDF) Test Summary TS-5556-002 (PDF) Product Specification PS-51096-001 (PDF) RoHS Certificate of Compliance (PDF) General Product Family Crimp Terminals Series 5556 Application Power Crimp Quality Equipment Yes Overview Mini-Fit Jr.™ Power Connectors Packaging Alternative 39-00-0039 (Loose) Product Name Mini-Fit® UPC 800753585010 Physical Durability (mating cycles max) 30 Gender Receptacle Material - Metal Brass Material - Plating Mating Tin Material - Plating Termination Tin Net Weight 0.130/g Packaging Type Reel Plating min - Mating 0.889μm Plating min - Termination 0.889μm Termination Interface: Style Crimp or Compression Wire Insulation Diameter 1.30-3.10mm Wire Size AWG 18, 20, 22, 24 Wire Size mm² N/A Electrical Current - Maximum per Contact 9A Voltage - Maximum 600V Material Info Old Part Number 5556T Reference - Drawing Numbers Packaging Specification PK-5556-001 Product Specification PS-51010-005, PS-51010-006, PS-51045-001, PS-51045-002, PS-51045-004, PS-51096-001, PS-52034-003, PS-52034-004, PS-5556-001, PS-5556-002, RPS-30067-001, RPS-30067-002, RPS-42474-001, RPS-51045-001, RPS-5557-008, RPS-5557-024, RPS-5557-031, RPS-5557-036, RPS-5557-037, RPS-5557-045, RPS-5557-046, RPS-5566-002 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 5556Series Mates With 5558 Mini-Fit® Crimp Male Terminals. Mini- Fit Jr.™ Header, Dual Row, 5566 , 5569 Use With 5557 Mini-Fit Jr.™ Receptacle Housing, 30067 Mini-Fit® TPA, 42474 Mini-Fit® BMI Panel Mount, 5559 Mini-Fit Jr.™ Plug Housing, Dual Row Application Tooling | FAQ Tooling specifications and manuals are found by selecting the products below. Crimp Height Specifications are then contained in the Application Tooling Specification document. Global Description Product # FineAdjust™ Applicator for Insulation OD 0639023900 Sales Drawing SD-5556**** Test Summary TS-5556-002 1.40-1.70mm - 18-24 AWG Extraction Tool 0011030044 Hand Crimp Tool for Male and Female Crimp Terminals, 16-24 AWG Wire 0638190900 FineAdjust™ Applicator for Insulation OD 2.50-2.95mm - 18-24 AWG 0639002600 FineAdjust™ Applicator for Insulation OD 1.65-2.05mm - 18-24 AWG 0639002900 FineAdjust™ Applicator for Insulation OD 1.90-2.30mm - 18-24 AWG 0639015600 FineAdjust™ Applicator for Insulation OD 2.50-2.95mm Optimized for 18 AWG Only 0639024800 FineAdjust™ Applicator for Insulation OD 2.30-2.60mm - 18-24 AWG 0639024900 T2 Terminator™ for insulation OD 2.50-2.95mm - 18-24 AWG 0639102600 T2 Terminator™ for insulation OD 1.65 – 2.05mm – 18 – 24 AWG 0639102900 T2 Terminator™ for insulation OD 1.90-2.30mm - 18-24 AWG 0639115600 T2 Terminator™ for insulation OD 1.40-1.70mm - 18-24 AWG 0639123900 T2 Terminator™ for insulation OD 2.50-2.95mm optimized for 18 AWG only 0639124800 T2 Terminator™ for insulation OD 2.30-2.60mm - 18-24 AWG 0639124900 Japan Description Product # Applicator for M211A Bench Press, 18-24 AWG Wire 0570223000 Side-Feed Applicator For Full-Auto Machine 0570223200 Hand Extraction Tool 0570316000 This document was generated on 01/06/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION For more complete information on any product, please visit our web site: www.aimtti.com Measurably better value manual & bus programmable - Laboratory Power Supplies Mixed-mode Regulation Mixed-mode regulation with linear output stage 4 digit voltage and current meters on each output * Constant voltage or constant current operation Variable auxiliary output (1.5-5V@5A) on triple model Switched remote sensing (not EX355P or EX752M) Silent fan-free cooling ** DC output switches        Compact bench power supplies Single, dual or triple outputs Mixed-mode regulation Power from 175W to 420W Switched remote sense terminals RS-232 interface model available       EX-R series Model Outputs Voltage / Current Power Interfaces EX355R One 0 to 35V / 0 to 5A 175W - EX355P One 0 to 35V / 0 to 5A 175W RS232 EX355P-USB One 0 to 35V / 0 to 5A 175W USB EX1810R One 0 to 18V / 0 to 10A 180W - EX2020R One 0 to 20V / 0 to 20A 400W - EX4210R One 0 to 42V / 0 to 10A 420W - EX354RD Two 2 x (0 to 35V / 0 to 4A) 280W - EX354RT Three 2 x (0 to 35V / 0 to 4A) plus 1.5 to 5.0V @ 5A 305W EX752M Two 2 x (0 to 75V / 0 to 2A) or 0 to 75V / 0 to 4A or 0 to 150V / 0 to 2A 300W Brief specifications for main outputs: Line & load regulation: <0.01%. Output noise: < 2mV rms. Meter accuracies: voltage - 0.3% ± 1digit, current - 0.6% ± 1digit. Sizes: singles - 140 x 160 x 295mm; dual/triple - 260 x 160 x 295mm (WxHxD) The EX752M is a dual output 300 watt PSU with Multi-Mode capability. This enables it to operate as a dual power supply with two independent and isolated outputs, or as a single power supply of double the power.  As a dual, each output provides 0 to 75V at 0 to 2A (mode A). As a single, the output can be selected as either 0 to 75V at 0 to 4A (mode B) or 0 to 150V at 0 to 2A (mode C). In single modes, the unused half of the unit becomes completely inoperative and its displays are blanked. For those requiring a basic bus controllable power supply, versions with an RS-232 interface (EL302P) or a USB interface (EL302P-USB) are available.  The EX series is the value-for-money PSU for users who require higher power levels. Mixed-mode regulation gives excellent performance combined with compact size and low weight. Dual output and triple output models are available in a similar casing style. The EX354RT triple (illustrated) has a variable voltage auxiliary output which can be set using the digital displays.  ** Note that the EX2020R and EX4210R use fan assisted cooling. All-linear regulation becomes impractical at higher power levels, so Aim-TTi have developed a technology that combines HF switch-mode pre-regulation with linear final regulation. This technique combines exceptional efficiency with noise levels that are close to that of pure linears. Mixed-mode regulation is used in the EX-R and TSX series. * Note that 3 digit current meters are used on the EX355P and EX752M and that voltmeter resolution on the EX752M is 0.1V. * Note that a 3 digit current meters is used on the EL302P & EL302P-USB, and that these models do not have remote sense terminals. http://www.farnell.com/datasheets/1796748.pdf SS-331 LCD Desoldering Station User’s Manual 1st Edition, ©2014 Copyright by Prokit’s Industries Co., Ltd. 1 Description SS‐331 designed for lead free desoldering especially. The quick heating and strong power are for convenient and clear soldering / desoldering all types of DIP components. Reasonable structure, single hand operation and strong absorbing power can be easy removal of the residual solder from the one‐sided or two sided of the PCB. This tool is used in the fields of electronic research, teaching and production, especially in the repairing and desoldering on the electronic appliances and communication equipments. 1. Control Unit The desoldering iron gun is controlled automatically by the micro‐processor. The digital control electronics and high‐quality sensor and heat exchange system guarantee precise temperature control at the soldering tip. The highest degree of temperature precision and optimal dynamic thermal behavior under load conditions is obtained by the quick and accurate recording of the measured values in a closed control circuit, and this design is especially for the lead‐free production techniques. 2. Desoldering Iron gun Desoldering iron gun with a power of 60W(Heat up rating 130W)and a wide spectrum of soldering tips can be used anywhere in the electronics field. The high power and gun type design make this iron gun suitable for fine desoldering work. The heating element is made of ceramic and the sensor on the desoldering tip can control the desoldering temperature quickly and accurately. 2 Technical Specification Voltage 220~240V AC Power Consumption 140W Temperature 160°C ~ 480°C Vacuum Pressure 600mm Hg Heating Element Ceramic Heater Accessories Spare tip x 3 ( 0.8(on the gun)1.0/  1.3mm) Cleaning tool x 3 (0.7/0.9/ 1.2mm) Filter sponge x 4 (φ20.8x1 +φ16.8x3) Certificate CE, GS, RoHS Station Size (mm) 225 x 160 x 130 Weight (kgs) 2.5 Operating Instruction Caution:Make sure that the four screws which are used to fasten the Diaphragm pump are removed from the control system before use. Otherwise serious damages may be caused to the user and the system. 1. Place the desoldering iron gun in the holder separately. Then connect the plug to the receptacle on the station and turn clockwise to tighten the plug nut. Check that the power supply is corresponding to the specification on the type plate and the power switch is on the “OFF” position. Connect the control unit to the power supply and switch on the power. Then a self‐test is carried out in which all display elements are switched on briefly. The electronic system then switches on automatically to the set temperature and displays this value. 2. The display and temperature setting ①. Shows the actual temperature of the desoldering tip. ②. Shows the setting temperature: Pressing the “UP” or “DOWN” button can switch the digital display to the set point display. The set‐point can be changed for ±1℃ by tapping the “UP” or “DOWN” button. Pressing the button will change the set‐point quickly. The digital display will return automatically to the actual value and the iron will reach to the setting temperature quickly. ③. ℃/℉ display: Switching the temperature display from ℃ to ℉ by pressing the “℃/℉”button and then the electronic system will display the actual temperature① and setting temperature② in ℉, and vice versa. ④. When the actual temperature on the soldering tip is less than the set‐point, “HEAT ON” will display and make the desoldering tip heating up. ⑤. When the absolute offset is more than ±10℃ between the actual temperature and the set‐point on the soldering tip or the nozzle, “WAIT” will display. It means that the temperature electronic control system is not in the stable situation, we should wait a moment to let the “WAIT” disappear. ⑥. When “ERROR” display, there may be a trouble on the 3 4 Safety Instruction 1. The manufacturer assumes no liability for uses other than those described in the operating instructions or for unauthorized alterations. 2. The operating instructions and cautions should be read carefully and kept in an easily visible location in the vicinity of the control system. Non‐observance of the cautions will result in accidents, injury or risks to health. Caution 1. The power cord only can be inserted in approved power sockets or adapters. 2. High Temperature The temperature of the soldering tip will reach as high as around 400℃(752℉) when the power switch is on. Since mishandling may lead to burns and fire, be sure to comply with the following precautions: ①. Do not touch metallic parts near the soldering tip/ nozzle. ②. Do not use this system near the flammable items. ③. Advise other people in the work area that the unit can reach a very high temperature and should be considered potentially dangerous. ④. Turn off the power switch while taking breaks and when finishing using. ⑤. Before replacing parts or storing the system, turn off the power and let it cool down to the room temperature. ⑥. Warning: this tool must be placed on its stand when not in use. 5 ⑦. A fire may result if the appliance is not used with care, therefore: 1) Be careful when using the appliance in places where there is combustible material. 2) Do not apply to the same place for a long time. 3) Do not use in presence of an explosive atmosphere. 4) Be aware heat may be conducted to combustible materials that out of sight. 5) Place the appliance on its stand after use and allow it to cool down before storage. 6) Do not leave the appliance unattended when it is switched on. 3. Take care of your tools Do not use the tools for any applications other than soldering or desoldering. Do not rap the iron against the work bench or otherwise subject the iron to severe shocks. Do not file the soldering tip to remove the oxide, please wipe the tip on the cleaning sponge. Use only accessories or attachments which are listed in the operation manual. Use of other tools and other accessories can lead to a danger of injury. Please turn off the power before connecting or disconnecting the soldering iron. 4. Maintenance Before further use, safety devices or slightly damaged parts must be carefully checked for error‐free and intended operation. Inspect moving parts for error‐free operation and that they don’t bind, or whether any parts are damaged. Damaged safety devices and parts must be repaired or replaced by a qualified technician, so long as nothing else is indicated in the operation manual. Use only accessories or 6 attachments which are listed in the operation manual. Use of other tools and other accessories can lead to a danger of injury. 5. Keep children at a distance Warning: this appliance is not intended for use by young children and infirm persons unless they have been adequately supervised by a responsible person to ensure that they can use the appliance safely. Warning: Young children should be supervised to ensure that they do not play with the appliance. Unused soldering tools should be stored in a dry location which is out of the reach of children. Switch off all unused soldering tools. 6. Protect yourself against electrical shocks Avoid touching grounded parts with your body, e.g. pipes, heating radiators and so on. The grip of antistatic designed soldering tool is conductive. 7. Work environment Do not use the soldering tool in a moist or wet environment. The soldering iron should be placed on the holder after finished using. 8. Observe the valid safety regulations at your work place. SS-331數顯吸焊台 概述 SS-331 特別為無鉛吸焊而設計。快速升溫和大功率的特點使其可以方便快速的焊接/拆焊所有類型的DIP元器件。 合理的結構,單手操作和強大的吸焊功率能夠輕鬆的從PCB一面或兩面除去殘餘錫渣。 目前已廣泛的應用於電子科研,教學以及生產等單位,特別是家電維修和通訊器材維修人員所不可缺少的首選專用工具。 1. 控制單元 吸焊槍由微處理器自動控制。數位控制裝置和高品質的感測器及加熱交換系統保證對烙鐵頭的溫度進行精確的控制。通過快速準確的記錄閉和控制回路測量可以獲得作高的溫度精度和帶負載狀況下最佳熱量轉遞性能,特別適合用於無鉛制程工藝。 2. 吸焊槍 (5SS-331-DG) 吸焊槍的功率為 60W(額定加熱功率 130W),可以配各種尺寸的烙鐵頭(U系列),廣泛應用於電子領域。 大功率和細長外形設計使這個電烙鐵適合做精密的焊接操作,發熱芯採用陶瓷發熱材料製作,頂端溫度感測器設計其特點在於能夠快速並準確的控制焊接溫度。 7 技術規範. 電壓 220~240V AC 消耗功率 140W 溫度 160°C ~ 480°C 真空吸力 600mm Hg 發熱原件 陶磁發熱芯 配件 吸嘴 x 3(0.8(裝在吸槍上)1.0/  1.3mm) 通針 x 3( 0.7/  0.9/  1.2mm) 過濾棉 x 4 ( 20.8mm x1 +  16.8mm x3) 認證 CE, GS, RoHS 尺寸(mm) 225 x 160 x 130 重量(kgs ) 2.5 操作說明: 1 將吸焊槍放置在支架上。然後將插頭插入插座順時針方向鎖緊螺母。檢查供電電源符合本產品的規格並確認總電源開關處於OFF的位置。接通控制系統的電源並打開電源開關。系統進行自檢,所有的液晶顯示都暫時被點亮。電子系統自動打開並迅速達到設定的溫度值。 2 顯示幕和溫度設置: 數位顯示說明: ① . 顯示吸焊烙鐵頭的實際溫度。 8 9 ② . 顯示的是設定溫度,通過按“UP"或“DOWN"鍵來改變設定值。輕壓單下“UP"或“DOWN"鍵設定值將以±1℃變化,持續按下“UP"或“DOWN"鍵設定值將會快速改變。改變設定值後,電子系統自動工作,顯示溫度會迅速到達設定值。 ③ . ℃或℉溫度,通過按“℃/℉"按鈕切換攝氏或華氏溫度,切換後電子系統會自動顯示的攝氏或華氏實際溫度①和設定溫度②數值。 ④ . 當烙鐵頭實際溫度小於設定溫度時顯示“HEAT ON"表示電子系統對烙鐵正在加熱。 ⑤ . 當烙鐵頭實際溫度與設定溫度的絕對偏差大於±10℃時顯示“WAIT",表示電子控溫系統還沒到達穩定狀態,請稍做等待,待“WAIT"不顯示時即可正常使用了。 ⑥ . 顯示“---"則表示系統有故障,或者是電烙鐵沒有正確連接到控制系統。 3 安全操作說明 3.1 製造商對於超出操作說明中所到的其他使用或未經授權的更改,不負任何責任。 3.2 應仔細閱讀操作說明及警告並將其放置在控制系統附近,如不遵守這些警告,將有可能發生意外事故,人體傷害或健康傷害。 4 警告及注意事項 4.1 電源線只能插入經認證過的電源插座或適配器中。 4.2 小心高溫:在開機狀態下,烙鐵頭或熱風槍焊嘴的溫度可以達到大約400℃(752℉)左右,由於不正確的操作可能會造成燒傷或引起火災,故應確保遵守以下預防措施:  不要讓金屬部件接觸到焊嘴和烙鐵頭;  不要在易燃物品附近使用該系統;  告知工作區域中的其他人員此設備會達到非常高的溫度應注意識別其潛在的危險性;  在休息及使用完後應關閉總電源  在更換零件或儲存前,應關閉總電源並讓其冷卻到 10 室溫  警告:不用時一定要將此工具放置在特定的支架上。  如使用不當可能會引起火災,因此  在有易燃物品的場所使用該設備一定要小心;  不要長時間在同一位置使用該設備;  不要在有爆炸性氣體的場所使用;  要知道熱量有可能會引燃不在視線範圍內的可燃物質;  使用完畢後要將器具放置在特定的支架上,且要在冷卻後方可收藏起來;  離開時必須要關閉電源開關。 4.3 愛護工具  不要將此設備用於焊接或脫焊以外的其他操作。  不要在工作臺上敲打電烙鐵或熱風筒或其他嚴重的撞擊。  不要銼烙鐵頭上的氧化層,請使用浸水的清潔棉擦除氧化層。  確保使用操作說明上列明的附件或配件,使用其他的工具或其他配件使本系統損壞或會有受傷的危險。  在接通或斷開錫槍前應先關閉電源。 4.4 工具保養 在使用前,應仔細檢查安全裝置或有輕微損害的零件無故障及在指定操作狀態。檢查活動的零件無故障操作,並且沒有繞線及零件損壞。已損壞的安全設備及零件都應由有資格的專業人員進行維修或更換。只使用操作說明中列出的配件。如果使用其他工具或配件有可能對操作人員造成傷害。 4.5 放置在兒童接觸不到的地方 警告:老人和兒童必須在監護人在場確保可安全使用的情況下方可使用該設備。警告:應確保兒童在沒有監護的情況下無法接觸到該設 備。 4.6 不用的焊接工具應存放在乾燥的,兒童接觸不到的地方。而且應該關閉所有未在使用狀態下的焊接工具的電源。 4.7 避免遭受電擊 避免用身體接觸接地零件,如:烙鐵管,散熱器等。抗靜電設計的焊接工具的把手是導電的。 4.8 工作環境 不要在潮濕的環境中使用焊接工具。電烙鐵及熱風槍用完後要放回到支架上。 4.9 遵守工作場所中的安全操作規定。 寶工實業股份有限公司 PROKIT’S INDUSTRIES CO., LTD. http://www.prokits.com.tw E-mail:pk@mail.prokits.com.tw ©2014 Prokit’s Industries Co., LTD. All rights reserved 2014001(C) Connections to a Wider Range of Slaves Ensured by Upgraded Models Master Conventional models New models C200HW-SRM21 CQM1-SRM21 SRM1-C01 SRM1-C02 SRM1-C01-V1 SRM1-C02-V1 3G8B3-SRM00 3G8B3-SRM01 C200PC-ISA02-SRM C200PC-ISA12-SRM C200HW-SRM21-V1 CQM1-SRM21-V1 SRM1-C01-V2 SRM1-C02-V2 NKE-made Uniwire C B /SS d Communications mode Slave ade U e CompoBus/S Send Unit SDD-CS1 High-speed communications mode Long-distance communications mode SRT1 Series FND-X􀀀-SRT Yes Yes Yes Yes No No Products from other companies SMC Solenoid valve for SI manifold use VQ Series SX Series SY Series Yes Yes Yes Yes Yes Yes No No No CKD Solenoid valve for saving wiring effort 4TB1 and 4TB2 Series 4TB3 and 4TB4 Series 4G Series MN4SO Series Yes Yes Yes Yes Yes Yes Yes Yes No No No No Koganei Valve for saving wiring effort YS1A1, A2 YS2A1, A2 Yes Yes Yes Yes No No New product SRT2-AD02 SRT2-DA02 No No Yes Yes Yes Yes SRT2-VID08S(-1) SRT2-VOD08S(-1) SRT2-VID16ML(-1) SRT2-VOD16ML(-1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes SRT2-ID16(-1) SRT2-OD16(-1) SRT2-ID08(-1) SRT2-OD08(-1) SRT2-ROC16 SRT2-ROF16 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes CPM1A-SRT21 Yes Yes Yes Products to be released soon SRT2-ID04(-1) SRT2-OD04(-1) SRT2-ID16T(-1) SRT2-OD16T(-1) SRT2-MD16T(-1) SRT2-ROC08 SRT2-ROF08 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note: 1. In high-speed communications mode, the maximum transmission distance is 100 m at a baud rate of 750 kbps. In long-distance communications mode (i.e., a newly available mode), the maximum transmission distance is 500 m at a baud rate of 93.75 kbps. 2. The SRT2-AD04 and SRT2-DA02 are available for 16-bit synchronous communications. 11 Master Control Unit SRM1-C01-V2/C02-V2 Subminiature, Stand-alone Model with CompoBus/S Master and SYSMAC Controller Functions Maximum number of Remote I/O points per Master: 256 Maximum number of Slaves per Master: 32 Communications cycle time: 0.5 ms max. (at baud rate 750 kbps). Communications distance: Extended to 500 m max. (at baud rate 93.75 kbps). Additional instructions (PID, SCL, NEG, ZCP) ensure analog compatibility. RS-232C port incorporated (SRM1-C02-V2). RC Ordering Information Specifications Model Buuilt-in sstaandd-aaloonee ccoontroolleer fuuncctioonss Without RS-232C SRM1-C01-V2 With RS-232C SRM1-C02-V2 Specifications Master Specifications Number of I/O points 256 points (128 inputs/128 outputs) 128 points (64 inputs/64 outputs) Selectable by DM setting. The default setting is 256 points. Max. number of Slaves per Master 256 points: 32 128 points: 16 I/O words Input words: 000 to 007 Output words: 010 to 017 Programming language Ladder diagram Types of instruction 14 basic and 72 special instructions (123 instructions in total) Execution time LD instruction: 0.97 ms MOV instruction: 9.1 ms Program capacity 4,096 words Data memory 2,048 + 512 (read-only) words Timers/Counters 128 timers/counters Work bits 640 bits Memory backup Flash memory (without battery): User programs Super capacitor: Data memory (backed up for 20 days at an ambient temperature of 25°C) Peripheral port 1 point RS-232C port 1 point (SRM1-C02-V1 only) Host Link, NT Link, 1:1 Link, or no protocol Programming tool Programming Consoles: CQM1-PRO01-E, C200H-PRO27-E SYSMAC-CPT: WS01-CPTB1-E (CD-ROM/FD) SYSMAC Support Software (MS-DOS version): C500-ZL3AT1-E Note: PID, SCL, NEG, and ZCP instructions are not supported by the SYSMAC-CPT. SRM1-C01-V2/C02-V2 SRM1-C01-V2/C02-V2 12 Communications Specifications Communications method CompoBus/S protocol Coding method Manchester coding method Connection method Multi-drop method and T-branch method (see note 1) Communications baud rate 750,000 bps/93,750 bps (see note 2) Communications cycle time High-speed comm nications 0.5 ms with 8 Slaves for inputs and 8 Slaves for outputs communications mode 0.8 ms with 16 Slaves for inputs and 16 Slaves for outputs Long-distance comm nications 4.0 ms with 8 Slaves for inputs and 8 Slaves for outputs communications mode 6.0 ms with 16 Slaves for inputs and 16 Slaves for outputs Communications cable 2-conductor VCTF cable (0.75 x 20) Dedicated flat cable Communications distance High-speed communications mode VCTF cable: Main line length: 100 m max. Branch line length: 3 m max. Total branch line length: 50 m max. Flat cable: Main line length: 30 m max. Branch line length: 3 m max. Total branch line length: 30 m max. (When flat cable is used to connect fewer than 16 Slaves, the main line can be up to 100 m long and the total branch line length can be up to 50 m.) Long-distance communications mode VCTF cable: Main line length: 500 m max. Branch line length: 6 m max. Total branch line length: 120 m max. Max. number of connecting nodes 32 Error control checks Manchester code check, frame length check, and parity check Note: 1. A terminator must be connected to the point in the system farthest from the Master. 2. The communications baud rate is switched using DM settings (default setting is 750,000 bps). General Specifications Supply voltage 24 VDC Allowable supply voltage 20.4 to 26.4 VDC Power consumption 3.5 W max. Inrush current 12.0 A max. Noise immunity Conforms to IEC61000-4-4, 2 kV (power lines) Vibration resistance 10 to 57 Hz, 0.075-mm amplitude, 57 to 150 Hz, acceleration: 9.8 m/s2 in X, Y, and Z directions for 80 minutes each (Time coefficient; 8 minutes × coefficient factor 10 = total time 80 minutes) Shock resistance 147 m/s2 three times each in X, Y, and Z directions Ambient temperature Operating: 0°C to 55°C Storage: –20°C to 75°C Humidity 10% to 90% (with no condensation) Atmosphere Must be free from corrosive gas. Terminal screw size M3 Power interrupt time DC type: 2 ms min. Weight 150 g max. SRM1-C01-V2/C02-V2 SRM1-C01-V2/C02-V2 13 Nomenclature SRM1-C01-V2 SRM1-C02-V2 CPU Unit status indicator CompoBus/S communications status indicator Indicates the status of the Compo- Bus/S in operation and in communication with Slaves. Peripheral port communications status indicator Flashes when the peripheral port or RS-232C port is in communication. Connector cover Peripheral port Connect this port to programming tools through dedicated cables. Terminal block Connector cover RS-232C port Connect this port to the RS-232C interfaces of personal computers and Programmable Terminals. Dimensions Note: All units are in millimeters unless otherwise indicated. SRM1-C01/C02-V2 The above dimensions apply to the SRM1-C02-V2. The SRM-C01-V2 has no RS-232C port. 14 Master Unit C200HW-SRM21-V1 Master Unit for CS1, C200HX, C200HG, C200HE, and C200HS A maximum of 256 I/O points available. Connects to a maximum of 32 Slaves. Communications cycle time: 0.5 ms max. (at baud rate 750 kbps). Communications distance: Extended to 500 m max. (at baud rate 93.75 kbps). Connection to Analog Terminals now supported. RC Ordering Information PC Max. number of I/O points Model C200HX (-Z), C200HG (-Z), C200HE (-Z), C200HS, CS1 256 points (128 inputs/128 outputs) C200HW-SRM21-V1 Specifications Communications Specifications Communications method CompoBus/S protocol Coding method Manchester coding method Connection method Multi-drop method and T-branch method (see note 1) Communications baud rate 750,000 bps, 93,750 bps (see note 2) Communications cycle time High-speed comm nications 0.5 ms with 8 Slaves for inputs and 8 Slaves for outputs communications mode 0.8 ms with 16 Slaves for inputs and 16 Slaves for outputs Long-distance comm nications 4.0 ms with 8 Slaves for inputs and 8 Slaves for outputs communications mode 6.0 ms with 16 Slaves for inputs and 16 Slaves for outputs Communications cable 2-conductor VCTF cable (0.75 x 20) Dedicated flat cable Communications distance High-speed communications mode VCTF cable: Main line length: 100 m max. Branch line length: 3 m max. Total branch line length: 50 m max. Flat cable: Main line length: 30 m max. Branch line length: 3 m max. Total branch line length: 30 m max. (When flat cable is used to connect fewer than 16 Slaves, the main line can be up to 100 m long and the total branch line length can be up to 50 m.) Long-distance communications mode VCTF cable: Main line length: 500 m max. Branch line length: 6 m max. Total branch line length: 120 m max. Max. number of connecting nodes 32 Error control checks Manchester code check, frame length check, and parity check Note: 1. A terminator must be connected to the point in the system farthest from the Master. 2. The communications baud rate is switched with the DIP switch. C200HW-SRM21-V1 C200HW-SRM21-V1 15 Unit Specifications Current consumption 150 mA max. at 5 VDC Number of I/O points 256 points (128 inputs/128 outputs), 128 points (64 inputs/64 outputs) (switchable) Number of occupied words 256 points: 20 words (8 input words/8 output words, 4 status data) 128 points: 10 words (4 input words/4 output words, 2 status data) PC CS1, C200HX (-ZE), C200HG (-ZE), C200HE (-ZE), C200HS Number of points per node number 8 points Max. number of Slaves per Master 32 Status data Communications Error Flag and Active Slave Node (see note) Weight 200 g max. Approved standards UL 508 (E95399), CSA C22.2 No. 142 (LR51460) Note: These flags use the AR area. Ratings The ratings of the Unit are the same as those of the CS1, C200HX, C200HG, C200HE, and C200HS. Nomenclature Indicators Indicates the operating status of the Master Unit and the status of communications with the Slaves. Rotary Switch This switch sets the Master’s one-digit hexadecimal unit number. DIP Switch These pins have the following functions: Pin 1: Max. number of Slaves setting Pin 2: Baud rate setting Pins 3 to 4: Reserved (Always OFF.) Communications Terminals Connect the Slaves’ transmission cable to these terminals. C200HW-SRM21-V1 C200HW-SRM21-V1 16 Dimensions Note: All units are in millimeters unless otherwise indicated. C200HW-SRM21-V1 Note: Refer to the C200HX, C200HG, C200HE, C200HS, or CS1 Operation Manual for details on the dimensions when the Master Unit is installed in the PC’s Backplane. Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Unit. 17 Master Unit CQM1-SRM21-V1 Master Unit for CQM1 A maximum of 128 I/O points available (Possible to set 32, 64, or 128 I/O points). Connects to a maximum of 16/32 Slaves. Communications cycle time: 0.5 ms max. (at baud rate 750 kbps). Communications distance: Extended to 500 m max. (at baud rate 93.75 kbps). Connection to Analog Terminals now supported. RC Ordering Information PC Max. number of I/O points Model CQM1-series PC 128 points (64 inputs/64 outputs) CQM1-SRM21-V1 Specifications Communications Specifications Communications method CompoBus/S protocol Coding method Manchester coding method Connection method Multi-drop method and T-branch method (see note 1) Communications baud rate 750,000 bps, 93,750 bps (see note 2) Communications cycle time High-speed comm nications 0.5 ms with 8 Slaves for inputs and 8 Slaves for outputs communications mode 0.8 ms with 16 Slaves for inputs and 16 Slaves for outputs Long-distance comm nications 4.0 ms with 8 Slaves for inputs and 8 Slaves for outputs communications mode 6.0 ms with 16 Slaves for inputs and 16 Slaves for outputs Communications cable 2-conductor VCTF cable (0.75 x 20) Dedicated flat cable Communications distance High-speed communications mode VCTF cable: Main line length: 100 m max. Branch line length: 3 m max. Total branch line length: 50 m max. Flat cable: Main line length: 30 m max. Branch line length: 3 m max. Total branch line length: 30 m max. (When flat cable is used to connect fewer than 16 Slaves, the main line can be up to 100 m long and the total branch line length can be up to 50 m.) Long-distance communications mode VCTF cable:: Main line length: 500 m max. Branch line length: 6 m max. Total branch line length: 120 m max. Max. number of connecting nodes 32 Error control checks Manchester code check, frame length check, and parity check Note: 1. A terminator must be connected to the point in the system farthest from the Master. 2. The communications baud rate is switched with the DIP switch. CQM1-SRM21-V1 CQM1-SRM21-V1 18 Unit Specifications Current consumption 180 mA max. at 5 VDC Number of I/O points 128 points (64 inputs/64 outputs), 64 points (32 inputs/32 outputs), 32 points (16 inputs/16 outputs) (switchable) Number of occupied words 128 points: 4 input words/4 output words 64 points: 2 input words/2 output words 32 points: 1 input word/1 output word PC 128 points: CQM1-CPU41-EV1/CPU42-EV1/CPU43-EV1/CPU44-EV1 64 points: CQM1-CPU11-E/CPU21-E/CPU41-EV1/CPU42-EV1/CPU43-EV1/CPU44-EV1 32 points: CQM1-CPU11-E/CPU21-E/CPU41-EV1/CPU42-EV1/CPU43-EV1/CPU44-EV1 Number of points per node number 4/8 points (switchable) Max. number of Slaves per Master 32 (4 points per node number) Status data Alarm terminal output Weight 200 g max. Approved standards UL 508 (E95399), CSA C22.2 No. 142 (LR51460) Alarm Output Specifications Maximum switching capacity 2 A at 24 VDC Minimum switching capacity 10 mA at 5 VDC Relay G6D-1A Minimum ON time 100 ms Circuit configuration 2 A at 24 VDC max. Internal circuit CQM1-SRM21-V1 Ratings The ratings of the Unit are the same as those for the CQM1. Nomenclature Indicators Indicates the operating status of the Master Unit and the status of communications with the Slaves. DIP Switch These pins have the following functions: Pins 1 and 2: PC word allocation setting Pin 3: Number of points setting Pin 4: Baud rate setting Pins 5 to 6: Reserved (Always OFF.) Alarm Output Terminals These terminals are shorted when an error occurs. Connect to a warning device. Communications Terminals Connect the Slaves’ transmission cable to these terminals. Terminal block screws These screws attach the terminal block. The terminal block can be removed when these screws are loosened. CQM1-SRM21-V1 CQM1-SRM21-V1 19 Dimensions Note: All units are in millimeters unless otherwise indicated. CQM1-SRM21-V1 Note: Refer to the CQM1 Operation Manual for details on the dimensions when the Master Unit is installed in the PC’s Backplane. Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Unit. 20 SYSMAC Board C200PC-ISA􀀀2-SRM SYSMAC C200HX/HG/HE and CompoBus/S Master Functions Integrated into a Single PCB Operates as a Programmable Controller to be built into personal computers. Programming is possible through Programming Devices like the programming on C200HX/HG. An optional Expansion Board is available for serial communications. Dedicated library in C is available for control. Driver for Windows use is available. Connects to a maximum of three Expansion I/O Racks. CompoBus/S Slave data is automatically read. Ordering Information PC Max. number of I/O points Model C200HG-CPU43 256 points ( 128 inputs/128 outputs) C200PC-ISA02-SRM C200HX-CPU64 56 o s 8 u s/ 8 ou u s) C200PC-ISA12-SRM Specifications Communications Specifications Communications method CompoBus/S protocol Coding method Manchester coding method Connection method Multi-drop method and T-branch method (see note) Communications baud rate 750,000 bps Communications cycle time 0.5 ms with 8 Slaves for inputs and 8 Slaves for outputs 0.8 ms with 16 Slaves for inputs and 16 Slaves for outputs Communications cable 2-conductor VCTF cable (0.75 x 20) Dedicated flat cable Communications distance VCTF cable: Main line length: 100 m max. Branch line length: 3 m max. Total branch line length: 50 m max. Flat cable: Main line length: 30 m max. Branch line length: 3 m max. Total branch line length: 30 m max. (When flat cable is used to connect fewer than 16 Slaves, the main line can be up to 100 m long and the total branch line length can be up to 50 m.) Max. number of connecting nodes 32 Error control checks Manchester code check, frame length check, and parity check Note: A terminator must be connected to the point in the system farthest from the Master. C200PC-ISA􀀀2-SRM C200PC-ISA􀀀2-SRM 21 Unit Specifications Power supply voltage 4.875 to 5.25 VDC Current consumption 0.5 A max. (see note 1) Number of I/O points 256 points (128 inputs/128 outputs), 128 points (64 inputs/64 outputs), (switchable) Number of occupied words 256 points: 20 words (8 input words, 8 output words, and 4 status data words) (see note 2) 128 points: 10 words (4 input words, 4 output words, and 2 status data words) Number of points per node number 8 points Max. number of Slaves per Master 32 Status data Communications Error Flag and Active Slave Node (see note 2) Weight 200 g max. Note: 1. The current consumption will be 0.8 A max. if the Programming Console is connected through the optional Expansion Board. 2. The occupied words are in the IR area. 22 I/O Link Unit CPM1A-SRT21 I/O Link Unit for CPM2A/CPM1A Operates as a Slave of the CompoBus/S Master Unit. Exchanges eight inputs and eight outputs with the Master. Approved by UL and CSA standards, and bears the CE marking. RC Ordering Information CPU Units I/O configuration Power supply Output method Input Output Model 30-point I/O model AC Relay 18 12 CPM1A-30CDR-A* DC Relay CPM1A-30CDR-D* Transistor (sink) CPM1A-30CDT-D Transistor (source) CPM1A-30CDT1-D AC Relay CPM2A-30CDR-A DC Relay CPM2A-30CDR-D Transistor (sink) CPM2A-30CDT-D Transistor (source) CPM2A-30CDT1-D 40-point I/O model AC Relay 24 16 CPM1A-40CDR-A* DC Relay CPM1A-40CDR-D* Transistor (sink) CPM1A-40CDT-D Transistor (source) CPM1A-40CDT1-D AC Relay CPM2A-40CDR-A DC Relay CPM2A-40CDR-D Transistor (sink) CPM2A-40CDT-D Transistor (source) CPM2A-40CDT1-D 60-point I/O model AC Relay 36 24 CPM2A-60CDR-A DC Relay CPM2A-60CDR-D Transistor (sink) CPM2A-60CDT-D Transistor (source) CPM2A-60CDT1-D Note: Models marked with asterisks do not bear CE markings. Expansion Units Product Number of connectable Units per CPU Unit Output method Input Output Model Expansion I/O Units 3 max. (see note) Relay 12 8 CPM1A-20EDR1 Transistor (sink) CPM1A-20EDT Transistor (source) CPM1A-20EDT1 --- 8 --- CPM1A-8ED Relay --- 8 CPM1A-8ER Transistor (sink) --- 8 CPM1A-8ET Transistor (source) CPM1A-8ET1 Analog I/O Unit 3 max. (see note) Analog 2 1 CPM1A-MAD01 CompoBus/S I/O Link Unit 3 max. (see note) --- 8 I/O link points 8 I/O link points CPM1A-SRT21 Note: Only a single Unit will be connectable if the NT-AL001 is connected to the RS-232C port. CPM1A-SRT21 CPM1A-SRT21 23 Specifications Slave CompoBus/S Slave Number of I/O points 8 inputs and 8 outputs Number of occupied I/O memory words of CPM2A 1 input word and 1 output word (same as other Expansion Units in allocation) Node address setting DIP switch Dimensions Note: All units are in millimeters unless otherwise indicated. CPM1A-SRT21 Installation Connection Examples CompoBus/S Master Unit or SRM1 CompoBus/S Master Control Unit CPM1A or CPM2A CPU Unit CPM1A-SRT21 CompoBus/S I/O Link Unit CS1􀀀 C200H􀀀 CQM1 SRM1 Dedicated flat cable or VCTF cable Connectable to 16 Units max. (Eight CQM1-SRM21 Units max.) Note: A single CompoBus/S I/O Link Unit together with a maximum of two other Expansion I/O Units can be connected to the CPM1A or CPM2A CPU Unit. 24 Transistor Remote Terminal SRT-ID/OD Long-distance Communications Supported by SRT2 Models (Long-distance/High-speed Communications Selection) SRT1 models support high-speed communications only. SRT2 models support long-distance communications and high-speed communications. Ultra-compact at 80 x 48 x 50 (W x H x D) mm for 4-point and 8-point terminals and 105 x 48 x 50 (W x H x D) mm for 16-point terminals. Two independent power supplies can be used because the I/O terminals are insulated from the internal circuits. DIN track mounting and screw mounting are both supported. RC Ordering Information I/O classification Internal I/O circuit common I/O points Rated voltage I/O rated voltage Model Input NPN (+ common) 4 24 VDC 24 VDC SRT1-ID04 PNP (– common) C C SRT1-ID04-1 Output NPN (– common) SRT1-OD04 PNP (+ common) SRT1-OD04-1 Input NPN (+ common) 8 SRT2-ID08 PNP (– common) SRT2-ID08-1 Output NPN (– common) SRT2-OD08 PNP (+ common) SRT2-OD08-1 Input NPN (+ common) 16 SRT2-ID16 PNP (– common) 6 SRT2-ID16-1 Output NPN (– common) SRT2-OD16 PNP (+ common) SRT2-OD16-1 Note: For more details about connections supported by the Master Unit, refer to page 10. Specifications Ratings Inputs Input current 6 mA max./point ON delay time 1.5 ms max. OFF delay time 1.5 ms max. ON voltage 15 VDC min. between each input terminal and V OFF voltage 5 VDC max. between each input terminal and V OFF current 1 mA max. Insulation method Photocoupler Input indicators LED (yellow) SRT-ID/OD SRT-ID/OD 25 Outputs Rated output current 0.3 A/point Residual voltage 0.6 V max. Leakage current 0.1 mA max. Insulation method Photocoupler Output indicators LED (yellow) Characteristics Communications power supply voltage 14 to 26.4 VDC I/O power supply voltage 24 VDC +10%/–15% I/O power supply current 1 A max. Current consumption (see note) 50 mA max. at 24 VDC Connection method Multi-drop method and T-branch method Secondary branches cannot be connected to T-branch lines. Connecting Units 4-point and 8-point Terminals: 16 Input Terminals and 16 Output Terminals per Master 16-point Terminals: 8 Input Terminals and 8 Output Terminals per Master Dielectric strength 500 VAC for 1 min (1-mA sensing current between insulated circuits) Noise immunity Conforms to IEC61000-4-4, 2 kV (power lines) Vibration resistance 10 to 55 Hz, 1.5-mm double amplitude Shock resistance Malfunction: 200 m/s2 Destruction: 300 m/s2 Mounting strength No damage when 50 N pull load was applied for 10 s in all directions Terminal strength No damage when 50 N pull load was applied for 10 s Screw tightening torque 0.6 to 1.18 N 􀀀 m Ambient temperature Operating: 0°C to 55°C (with no icing or condensation) Storage: –20°C to 65°C (with no icing or condensation) Ambient humidity Operating: 35% to 85% Weight 4-point and 8-point Terminals: 80 g max. 16-point Terminals: 110 g max. Approved standards (4/8 points) UL 508, CSA C22.2 No. 14 Note: The above current consumption is the value with all 4 and 8 and 16 points turned ON excluding the current consumption of the external sensor connected to the input Remote Terminal and the current consumption of the load connected to the output Remote Terminal. SRT-ID/OD SRT-ID/OD 26 Nomenclature I/O Terminals I/O Power Supply Terminals Connect 24-VDC power supply Communications Power Supply Terminals Connect 14- to 26.4-VDC power supply. CompoBus/S Terminal Connect the CompoBus/S DIP Switch communications cable. Used for node number setting and holding or clearing outputs for communications error. Refer to the Compobus/S Operation Manual (W266) for details on DIP switch settings. Baud rate setting 0 to 7 ERR COMM PWR Node Number Settings Output HOLD/CLEAR settings (Output Terminals only) Screw mounting hole Indicators Indicator Display Color Meaning PWR Lit Green The communications power supply is ON. Not lit The communications power supply is OFF. COMM Lit Yellow Normal communications Not lit A communications error has occurred or the Unit is in standby status. ERR Lit Red A communications error has occurred. Not lit Normal communications or the Unit is in standby status. 0 to 7 Lit Yellow The corresponding I/O signal is ON. Not lit The corresponding I/O signal is OFF. Output HOLD/CLEAR Mode Mode Pin 1 Setting HOLD ON Output status is maintained. CLEAR OFF Output status is cleared when a communications error occurs. Note: 1. Pin 1 is factory-set to OFF. 2. This function is available to Output Terminals only. SRT-ID/OD SRT-ID/OD 27 Node Number Settings Node number Pin 3 Pin 4 Pin 5 Pin 6 8 4 2 1 0 OFF OFF OFF OFF 1 OFF OFF OFF ON 2 OFF OFF ON OFF 3 OFF OFF ON ON 4 OFF ON OFF OFF 5 OFF ON OFF ON 6 OFF ON ON OFF 7 OFF ON ON ON 8 ON OFF OFF OFF 9 ON OFF OFF ON 10 ON OFF ON OFF 11 ON OFF ON ON 12 ON ON OFF OFF 13 ON ON OFF ON 14 ON ON ON OFF 15 ON ON ON ON Note: 1. The node number is factory-set to 0. 2. For node number settings, refer to the CompoBus/S Operation Manual (W266). Dimensions Note: All units are in millimeters unless otherwise indicated. SRT1-ID04 (-1) SRT1-OD04 (-1) SRT2-ID08 (-1) SRT2-OD08 (-1) (54) 27 80 48 65 Two, 4.2 dia. or M4 Sixteen, M3 Mounting Holes (20.5) (11) SRT-ID/OD SRT-ID/OD 28 SRT2-ID16 (-1) SRT2-OD16 (-1) 48 Two, 4.2 dia. or M4 (50) (28) Mounting Holes (54) 27 50 (20.5) (11) 105 22–M3 Installation Internal Circuit Configuration SRT1-ID04 SRT1-ID04-1 Photocoupler Photocoupler Internal circuit Internal circuit 24 VDC(+) Photocoupler Photocoupler (–) SRT1-OD04 Internal circuit 24 VDC Photocoupler Photocoupler Voltage stepdown SRT1-OD04-1 Internal circuit Photocoupler Photocoupler 24 VDC (P) (P) 24 VDC (P) (P) Voltage stepdown V V V 1 G 0 2 G G V V V 1 V 0 2 G SRT-ID/OD SRT-ID/OD 29 SRT2-OD08-1 Internal circuit Photocoupler Photocoupler SRT2-ID08 SRT2-ID08-1 Photocoupler Photocoupler Internal circuit 24 VDC(+) Internal circuit Photocoupler Photocoupler (–) SRT2-OD08 Internal circuit 24 VDC Photocoupler Photocoupler Voltage stepdown SRT2-ID16 Photocoupler Internal Photocoupler circuit SRT2-ID16-1 Internal circuit Photocoupler Photocoupler Internal circuit SRT2-OD16 Photocoupler Photocoupler Voltage stepdown SRT2-OD16-1 Internal circuit Photocoupler Photocoupler Voltage stepdown 24 VDC (P) 24 VDC (P) (P) Voltage stepdown (P) 24 VDC (P) (P) 24 VDC (P) (P) V V 1 0 2 G G V V 1 0 2 G V V 1 0 2 G SRT-ID/OD SRT-ID/OD 30 External Connections (NPN Models) Input Sensor 1 Blue Brown Black Sensor 2 Blue Brown Black Sensor 1 Blue Brown Black Sensor 2 Blue Brown Black Three-wired Sensors SRT1-ID04 with NPN Output SRT2-ID08 and SRT2-ID16 with NPN Output Two-wired Sensors SRT1-ID04 SRT2-ID08 and SRT2-ID16 Sensor 1 Blue Brown Sensor 2 Blue Brown Sensor 1 Blue Brown Sensor 2 Blue Brown Output SRT1-OD04 SRT2-OD08 and SRT2-ID16 L 1 L 2 L 1 L 2 Terminal Arrangement and I/O Device Connection Example (PNP Models) Note: The connections examples shown are for PNP models. Input SRT1-ID04 SRT2-ID08 Output SRT1-OD04 SRT2-OD08 Blue Brown Blue Brown Blue Brown Brown Blue Communications path Communications power supply power supply power supply Communications path Communications power supply Communications path Communications power supply power supply Photoelectric sensor or proximity sensor (threewired sensor with a builtin- amplifier) Limit switch (two-wired sensor) Solenoid, valve Solenoid I/O Communications path Communications power supply Photoelectric sensor or proximity sensor (threewired sensor with a builtin- amplifier) Limit switch (two-wired sensor) Black Black SRT2-ID16 SRT2-OD16 Communications path Communications power supply I/O power supply Photoelectric sensor or proximity sensor (threewired sensor with a builtin- amplifier) Limit switch (two-wired sensor) I/O power supply Communications path Communications power supply Solenoid Valve Valve power supply I/O Blue Brown Blue Brown Black I/O I/O SRT-ID/OD SRT-ID/OD 31 External Connections (PNP Models) Input Three-wired Sensors SRT1-ID04-1 with NPN Output SRT2-ID08-1 and SRT2-ID16-1 with NPN Output Two-wired Sensors SRT1-ID04-1 SRT2-ID08-1 and SRT2-ID16-1 Sensor 1 Blue Brown Black Sensor 2 Blue Brown Black Sensor 1 Blue Brown Black Sensor 2 Blue Brown Black Sensor 1 Blue Brown Sensor 2 Blue Brown Sensor 1 Blue Brown Sensor 2 Blue Brown Output SRT1-OD04-1 SRT2-OD08-1 and SRT2-ID16-1 L 1 L 2 L 1 L 2 Terminal Arrangement and I/O Device Connection Example (PNP Models) Note: The connections examples shown are for NPN models. Input SRT1-ID04-1 SRT2-ID08-1 Output SRT1-OD04-1 SRT2-OD08-1 Blue Brown Blue Brown Blue Brown Brown Blue Communications path Communications power supply power supply power supply Communications path Communications power supply Communications path Communications power supply power supply Photoelectric sensor or proximity sensor (three-wired sensor with a built-in-amplifier) Limit switch (two-wired sensor) Solenoid, valve Solenoid I/O Communications path Communications power supply Photoelectric sensor or proximity sensor (three-wired sensor with a built-in-amplifier) Limit switch (two-wired sensor) Black Black SRT2-ID16-1 SRT2-OD16-1 Communications path Communications power supply I/O power supply Photoelectric sensor or proximity sensor (three-wired sensor with a built-in-amplifier) Limit switch (two-wired sensor) I/O power supply Communications path Communications power Valve supply Solenoid Valve power supply I/O Blue Brown Blue Brown Black I/O I/O Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Unit. For general precautions refer to page 80. 32 Remote I/O Terminal SRT1-D16T(-1) Models with 3-tier Terminals (16 Points) are Added to the Remote I/O Terminal Series. Six Models are Available Depending on the NPN or PNP Configuration, Input Points, I/O Points, or Output Points. Incorporates easy-to-wire terminals each connecting to a single wire. Reduces designing and wiring effort. Incorporates a removable circuit block of cassette construction. Ordering Information I/O classification Internal I/O circuit common I/O points I/O connection method Model Digital input NPN (+ common) 16 M3 terminal block SRT1-ID16T PNP (– common) 6 3 e a boc SRT1-ID16T-1 Digital I/O NPN (+ common) SRT1-MD16T PNP (– common) SRT1-MD16T-1 Digital output NPN (– common) SRT1-OD16T PNP (+ common) SRT1-OD16T-1 Specifications Ratings Inputs Input current 6 mA max./point at 24 V and 3 mA min./point at 17 V ON delay time 1.5 ms max. OFF delay time 1.5 ms max. ON voltage NPN: 15 VDC min. between V terminals and each input terminal PNP: 15 VDC min. between G terminals and each input terminal OFF voltage NPN: 5 VDC max. between V terminals and each input terminal PNP: 5 VDC max. between G terminals and each input terminal OFF current 1 mA max. Insulation method Photocoupler Outputs Rated output current 0.5 A max./point Residual voltage 1.2 V max. ON delay time 0.5 ms max. OFF delay time 1.0 ms max. Leakage current 0.1 mA max. Insulation method Photocoupler SRT1-D16T(-1) SRT1-D16T(-1) 33 Characteristics Communications power supply voltage 14 to 26.4 VDC I/O power supply voltage 24 VDC +10%/–15% I/O power supply current 4 A max./common Current consumption (see note) 50 mA max. at 24 VDC Connection method Multi-drop method and T-branch method Secondary branches cannot be connected to T-branch lines. Dielectric strength 500 VAC between insulated circuits Noise immunity Conforms to IEC61000-4-4, 2 kV (power lines) Vibration resistance 10 to 150 Hz, 1.0-mm double amplitude or 70 m/s2 Shock resistance 200 m/s2 Mounting strength No damage with 100 N pull load applied in all directions. Terminal strength No damage with 100 N pull load applied Screw tightening torque 0.3 to 0.5 N 􀀀 m Ambient temperature Operating: –10°C to 55°C Storage: –25°C to 65°C Ambient humidity Operating: 25% to 85% (with no condensation) Weight 300 g max. Note: The above current consumption is the value with all points turned ON excluding the current consumption of the external sensor connected to the input Remote Terminal and the current consumption of the load connected to the output Remote Terminal. Nomenclature ERR Indicator: Indicates communications errors. COMM Indicator: ON while the Unit is in data communication. Power Indicator HOLD/CLR DIP Switch The DIP switch is on the left-hand side under the cover on the upper part of the Remote I/O Terminal. Holding or clearing output when a communications error occurs. Address Setting Switch Set the rotary switch to the node address by referring to the following table. I/O Indicators M4 Mounting Screw Terminal Cover The Unit stops operating with the cover opened. I/O and I/O Device Power Supply Terminals 8 to 15 These terminals will be used as output terminals 0 through 7 if the connected device handles both input and output signals. I/O and I/O Device Power Supply Terminals 0 to 7 These terminals will be used as input terminals if the connected device handles both input and output signals. I/O Power Supply Terminals Connect 24-VDC I/O power supply Fixture Track Used for DIN track mounting. CompoBus/S Internal Power Supply Terminals (BS+ and BS–) CompoBus/S Communications Cable Terminals (BDH and BDL) Address Setting Switch Node address Setting (Hex) 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Node address Setting (Hex) 8 8 9 9 10 A 11 B 12 C 13 D 14 E 15 F SRT1-D16T(-1) SRT1-D16T(-1) 34 Dimensions Note: All units are in millimeters unless otherwise indicated. SRT1-ID16T (-1) SRT1-MD16T (-1) SRT1-OD16T (-1) Mounting Holes Two, 4.2 dia. or M4 Two, 4.2 dia. or M4 Installation Internal Circuit Configuration SRT1-ID16T SRT1-MD16T SRT1-ID16T-1 SRT1-MD16T-1 SRT1-OD16T SRT1-OD16T-1 DC-DC converter (isolated type) Photocoupler Photocoupler Inputs (0 to 7) Inputs (8 to 15) DC-DC converter (isolated type) Photocoupler Photocoupler Inputs (0 to 7) Inputs (0 to 7) DC-DC converter (isolated type) Photocoupler Photocoupler Inputs (0 to 7) Inputs (8 to 15) DC-DC converter (isolated type) Photocoupler Photocoupler Inputs (0 to 7) Inputs (8 to 15) DC-DC converter (isolated type) Photocoupler Photocoupler Inputs (0 to 7) Outputs (0 to 7) DC-DC converter (isolated type) Photocoupler Photocoupler Outputs (0 to 7) Outputs (8 to 15) I/O power supply I/O power supply I/O power supply Internal circuit Internal circuit Internal circuit Internal circuit Internal circuit Internal circuit Voltage drop Voltage drop Voltage drop Voltage drop Voltage drop Voltage drop SRT1-D16T(-1) SRT1-D16T(-1) 35 External Connections Input (NPN Models) SRT1-ID16T SRT1-MD16T Output (NPN Models) SRT1-OD16T SRT1-MD16T Input (PNP Models) SRT1-ID16T-1 SRT1-MD16T-1 Output (PNP Models) SRT1-OD16T-1 SRT1-MD16T-1 Two-wired sensor Three-wired sensor Three-wired sensor Solenoid, valve, etc. Solenoid, valve, etc. Blue (Black) Brown (White) Blue (Black) Brown (Red) Black (White) Black (Black) Blue (Red) Brown (White) 36 Relay-mounted Remote Terminal SRT-R Ultra-miniature 8-point and 16-point Relay-mounted Terminals Ultra-compact (8-point models: 101 x 51 x 51 mm (W x H x D); 16-point models: 156 x 51 x 51 mm (W x H x D)) Power MOS FET Relay and Relay models. DIN track mounting and screw mounting are available. RC Ordering Information Classification I/O points Rated voltage Relay coil rating Model Applicable relay Relay output 8 points 24 VDC 24 VDC SRT1-ROC08 G6D-1A 16 points SRT2-ROC16 Power MOS FET l t t o e OS 8 points SRT1-ROF08 G3DZ-2R6PL relay output 16 points SRT2-ROF16 Note: For details about connections to the Master Unit, refer to page 10. Specifications Ratings Relay Output Item SRT1-ROC08, SRT2-ROC16 Applicable relay G6D-1A (one for each output point) Rated load 3 A at 250 VAC, 3 A at 30 VDC (resistive load) Rated carry current 3 A (see note 1) Max. contact voltage 250 VAC, 30 VDC Max. contact current 3 A Max. switching capacity 730 VA (AC), 90 W (DC) Min. permissible load (see note 2) 10 mA at 5 VDC Life expectancy Electrical: 100,000 operations min. (rated load, at 1,800 operations/h) Mechanical: 20,000,000 operations min. (at 18,000 operations/h) Note: 1. The maximum permissible current of COM0 to COM7 is 3 A. 2. This value fulfills the P reference value of opening/closing at a rate of 120 times per min (ambient operating environment and determination criteria according to JIS C5442). Power MOS FET Relay Output Item SRT1-ROF08, SRT2-ROF16 Applicable relay G3DZ-2R6PL (one for each output point) Load voltage 3 to 264 VAC, 3 to 125 VDC Load current 100 mA to 0.3 A Inrush current 6 A (10 ms) SRT-R SRT-R 37 Characteristics Power supply voltage 24 VDC +10%/–15% Current consumption (see note) 350 mA max. at 24 VDC Connection method Multi-drop method and T-branch method Secondary branches cannot be connected to T-branch lines. Connecting Units 8-point Units: 16 per Master 16-point Units: 8 per Master Dielectric strength 2,000 VAC for 1 min (1-mA sensing current) between all output terminals and power supply, between communication terminals, and between contacts of different polarities 500 VAC for 1 min (1-mA sensing current) between all output terminals and power supply, between communication terminals, and between all power supply terminals and communications terminals Noise immunity Conforms to IEC61000-4-4, 2 kV (power lines) Vibration resistance 10 to 55 Hz, 0.75-mm double amplitude Shock resistance Malfunction: 100 m/s2 Destruction: 300 m/s2 Mounting strength No damage when 50 N pull load was applied for 10 s in all directions Terminal strength No damage when 50 N pull load was applied for 10 s Screw tightening torque 0.6 to 1.18 N 􀀀 m Ambient temperature Operating: 0°C to 55°C (with no icing or condensation) Storage: –20°C to 65°C (with no icing or condensation) Ambient humidity Operating: 35% to 85% Weight 8-point models: 145 g max., 16-point models: 240 g max. Approved standards UL 508, CSA C22.2 No. 14 Note: The above current consumption is a value with all the points turned ON including the current consumption of the G6D coil for the Remote Output Terminal. SRT-R SRT-R 38 Nomenclature SRT2-ROC16 SRT2-ROF16 SRT1-ROC08 SRT1-ROF08 Mounting Holes Output Terminals I/O Power Supply Terminals Connect 24-VDC power supply Communications Power Supply Terminals Connect 24-VDC power supply. CompoBus/S Terminals Connect the CompoBus/S communications cable. Mounting Holes DIP Switch Used for node number setting and holding or clearing outputs for communications error. Note: Always turn off the Unit before changing DIP switch settings. Mounting Holes Output Terminals I/O Power Supply Terminals Connect 24-VDC power supply Communications Power Supply Terminals Connect 24-VDC power supply. CompoBus/S Terminals Connect the CompoBus/S communications cable. Mounting Holes DIP Switch Used for node number setting and holding or clearing outputs for communications error. 0 to 15 ERR COMM PWR Output HOLD/CLEAR setting (Output model only) Baud rate setting Node address setting Indicators Indicator Display Color Meaning PWR Lit Green The communications power supply is ON. Not lit The communications power supply is OFF. COMM Lit Yellow Normal communications Not lit A communications error has occurred or the Unit is in standby status. ERR Lit Red A communications error has occurred. Not lit Normal communications or the Unit is in standby status. 0 to 15 (see note) Lit Yellow The corresponding I/O signal is ON. Not lit The corresponding I/O signal is OFF. Note: The SRT1-RO08 does not have indicators 8 to 15. SRT-R SRT-R 39 Output HOLD/CLEAR Mode Mode Pin 1 Setting HOLD ON Output status is maintained when a communications error occurs. CLEAR OFF Output status is cleared when a communications error occurs. Note: 1. Pin 1 is factory-set to OFF. 2. This function is available to the Output Terminal only. Node Number Settings Node number Pin 3 Pin 4 Pin 5 Pin 6 8 4 2 1 0 OFF OFF OFF OFF 1 OFF OFF OFF ON 2 OFF OFF ON OFF 3 OFF OFF ON ON 4 OFF ON OFF OFF 5 OFF ON OFF ON 6 OFF ON ON OFF 7 OFF ON ON ON 8 ON OFF OFF OFF 9 ON OFF OFF ON 10 ON OFF ON OFF 11 ON OFF ON ON 12 ON ON OFF OFF 13 ON ON OFF ON 14 ON ON ON OFF 15 ON ON ON ON Note: 1. The node number is factory-set to 0. 2. For node number setting, refer to the CompoBus/S Operation Manual (W266). SRT-R SRT-R 40 Dimensions Note: All units are in millimeters unless otherwise indicated. SRT1-ROC08 SRT1-ROF08 Mounting Holes SRT2-ROC16 SRT2-ROF16 Mounting Holes 100 50 Two, 4.2 dia. or M4 Two, 4.2 dia. or M4 50 50 155 Thirty two, M3 Sixteen, M3 50 50 50 80 40 135 40 SRT-R SRT-R 41 Installation Internal Circuit Configuration SRT1-ROC08 SRT2-ROC16 Note: The G3DZ-2R6PL Power MOS FET Relay is inserted into this portion of the SRT1-ROF08 and SRT2-ROF16. Relay driver circuit Internal circuit Later blocks (See note) * Relay driver circuit Relay driver circuit Relay driver circuit External Connections Lamp Lamp Lamp Lamp Load power supply Terminal Arrangement and I/O Device Connection Example Output SRT2-ROC16 SRT2-ROF16 Note: 1. Dotted lines indicate internal connections. SRT1-ROC08 and SRT1-ROF08 have the 0 to 7 and COM0 to COM3 terminals only. 2. The above is a connection example of the SRT2-ROC16 with G6D Relays mounted. G3DZ Power MOS FET Relays are mounted to the SRT1-ROF08 and SRT2-ROF16. 24-VDC power supply Communications path Load Power supply Load Power supply Load Load Load Power supply Load Power supply Load Load Load Power supply Load Power supply Load Load Load Power supply Load Power supply Load Load *(see note 2) Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Unit. Refer to page 80 for details. 42 Connector Terminal SRT2-VID/VOD Compact Connector Terminals Save Wiring Effort and Enable Long-distance Communications Long-distance or high-speed communications mode is selectable. Incorporates I/O connectors making it possible to minimize the size. I/O connectors save wiring effort. Flexible DIN track mounting is possible through a DIN track attachment. Eight-point sensor connector models and 16-point MIL connector models are the same size. Features Vertical or horizontal DIN track mounting according to the available space is possible. Saves space and easily connects to other devices without wiring effort. Standard mounting (Sensor connector model) Mounting with DIN track attachment Standard mounting (MIL connector model) Communications and power supply connector DIN track G7TC Sensor connector Indicators Setting switch DIN track mounting hook MIL connector Ordering Information I/O classification Internal I/O circuit common I/O points I/O connection method Model Digital input NPN (+ common) 8 Sensor connector SRT2-VID08S PNP (– common) Se so co ec o SRT2-VID08S-1 Digital output NPN (– common) SRT2-VOD08S PNP (+ common) SRT2-VOD08S-1 Digital input NPN (+ common) 16 MIL connector SRT2-VID16ML PNP (– common) 6 co ec o SRT2-VID16ML-1 Digital output NPN (– common) SRT2-VOD16ML PNP (+ common) SRT2-VOD16ML-1 Mounting hook A SRT2-ATT01 Mounting hook B SRT2-ATT02 Note: For details about connecting the SRT2-VID or SRT2-VOD to the Master Unit, refer to page 10. SRT2-VID/VOD SRT2-VID/VOD 43 Specifications Ratings Inputs Item SRT2-VID08S SRT2-VID08S-1 SRT2-VID16ML SRT2-VID16ML-1 Input current 6 mA max./point at 24 V, 3 mA max./point at 17 V ON delay time 1.5 ms max. OFF delay time 1.5 ms max. ON voltage 15 VDC min. (Between each input terminal and V: NPN. Between each input and G: PNP.) OFF voltage 5 VDC max. (Between each input terminal and V: NPN. Between each input and G: PNP.) OFF current 1 mA max. Insulation method Photocoupler Maximum number of inputs 8 12 Number of circuits 8 points/common, 1 circuit 16 points/common, 1 circuit Outputs Item SRT2-VID08S SRT2-VID08S-1 SRT2-VID16ML SRT2-VID16ML-1 Rated output current 0.3 A/point 0.3 A/point (2-A common) (See note.) Residual voltage 1.2 V max. ON delay time 0.5 ms max. OFF delay time 1.5 ms max. Leakage current 0.1 mA max. Insulation method Photocoupler Number of circuits 8 points/common, 1 circuit 16 points/common, 1 circuit Note: When using V/G terminals in an MIL connector, ensure that the current per terminal for the V/G terminals does not exceed 1 A. Characteristics Communications power supply voltage 14 to 26.4 VDC I/O power supply voltage 20.4 to 26.4 VDC (24 VDC +10%/–15%) I/O power supply current Sensor connector: 2.4 A max., MIL connector: 2.0 A max. Current consumption (see note) 50 mA max. at 24 VDC Noise immunity Conforms to IEC61000-4-4, 2 kV (power lines) Vibration resistance 10 to 150 Hz, 1.0-mm double amplitude or 70 m/s2 (50 m/s2 for SRT2-ATT02) Shock resistance 200 m/s2 Dielectric strength 500 VAC (between insulated circuits) Ambient temperature Operating: –10°C to 55°C (with no icing or condensation) Storage: –25°C to 65°C Ambient humidity Operating: 25% to 85% (with no condensation) Storage: 25% to 85% Mounting strength No damage when 100 N pull load was applied in all directions (40 N load for SRT2-ATT02) Terminal strength No damage when the following loads were applied: Communications connector: 100 N Sensor connector: 40 N MIL connector: 100 N Screw tightening torque Communications connector: 0.25 N 􀀀 m Node address setting Settings made at DIP switch (set before supplying power for Slave communications) Weight Approx. 75 g max. Note: The above current consumption is the value with all points turned ON excluding the current consumption of the external sensor connected to the input Remote Terminal and the current consumption of the load connected to the output Remote Terminal. SRT2-VID/VOD SRT2-VID/VOD 44 Nomenclature SRT2-VID08S/SRT2-VID08S-1 SRT2-VOD08S/SRT2-VOD08S-1 (Sensor Connector Models) SRT2-VID16ML/SRT2-VID16ML-1 SRT2-VOD16ML/SRT2-VOD16ML-1 (MIL Connector Models) Communications Connectors I/O Connectors Indicators DIP Switch Communications Connectors I/O Connectors Output HOLD/CLEAR Mode Setting Communications Mode Setting Node Address Setting Reserved for System Use (Always OFF) Indicators Indicator Color Display Meaning PWR Green Lit The communications power supply is ON. Not lit The communications power supply is OFF. COMM Yellow Lit Normal communications Not lit A communications error has occurred or the Unit is in standby status. ERR Red Lit A communications error has occurred. Not lit Normal communications or the Unit is in standby status. 0 to 7 (for 8-point I/O) 0 to 15 (for 16-point I/O) Yellow Lit The corresponding I/O signal is ON. Not lit The corresponding I/O signal is OFF. Name Power Communications Communications error Input (output) Output HOLD/CLEAR Mode SW8 (HOLD) Setting OFF Output status is cleared. ON Output status is maintained. Communications Mode SW7 (HOLD) Setting OFF High-speed communications mode ON Long-distance communications mode Node Number Settings Node number Pin 4 Pin 3 Pin 2 Pin 1 8 4 2 1 0 OFF OFF OFF OFF 1 OFF OFF OFF ON 2 OFF OFF ON OFF 3 OFF OFF ON ON 4 OFF ON OFF OFF 5 OFF ON OFF ON 6 OFF ON ON OFF 7 OFF ON ON ON 8 ON OFF OFF OFF 9 ON OFF OFF ON 10 ON OFF ON OFF 11 ON OFF ON ON 12 ON ON OFF OFF 13 ON ON OFF OFF 14 ON ON ON OFF 15 ON ON ON ON Note: Be sure to perform settings with the Slave power supply OFF. SRT2-VID/VOD SRT2-VID/VOD 45 Dimensions Note: All units are in millimeters unless otherwise indicated. SRT2-VID08S SRT2-VID08S-1 SRT2-VOD08S SRT2-VOD08S-1 SRT2-VID16ML SRT2-VID16ML-1 SRT2-VOD16ML SRT2-VOD16ML-1 SRT2-ATT01 SRT2-ATT02 Dimensions when Unit is mounted. SRT2-VID/VOD SRT2-VID/VOD 46 Installation Internal Circuit Configuration SRT2-VOD08S-1 SRT2-VID08S SRT2-VID08S-1 SRT2-VOD08S SRT2-VID16ML SRT2-VID16ML-1 SRT2-VOD16ML SRT2-VOD16ML-1 Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Photocoupler Internal circuit Internal circuit Internal circuit Internal circuit Internal circuit Internal circuit Internal circuit Internal circuit Voltage drop Voltage drop Voltage drop Voltage drop SRT2-VID/VOD SRT2-VID/VOD 47 Terminal Arrangement and I/O Device Connection Examples SRT2-VID08S SRT2-VID08S-1 SRT2-VID16ML SRT2-VID16ML-1 SRT2-VOD08S SRT2-VOD16ML SRT2-VOD08S-1 SRT2-VOD16ML-1 CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers CompoBus/S communications CompoBus/S communications power supply I/O power supply Pin numbers Sensor Brown (Red) Black (White) Blue (Black) Three-wired sensor Sensor Brown (White) Blue (Black) Two-wired sensor Sensor Three-wired sensor Sensor Two-wired sensor Sensor Three-wired sensor Sensor Two-wired sensor Sensor Three-wired sensor Sensor Two-wired sensor Output device Solenoid etc. Output device Valve etc. Output device Solenoid etc. Output device Valve etc. Output device Solenoid etc. Output device Valve etc. Output device Solenoid etc. Output device Valve etc. Brown (Red) Black (White) Blue (Black) Brown (White) Blue (Black) Brown (Red) Black (White) Blue (Black) Brown (White) Blue (Black) Brown (Red) Black (White) Blue (Black) Brown (White) Blue (Black) Note: 1. V terminals and G terminals are respectively connected internally. When supplying power for I/O from communications connectors, power can be supplied to the sensor output devices from V and G terminals. 2. When using an inductive load (solenoid, valve etc.), either use one with an internal reverse electromotive force absorption diode or attach a diode externally. SRT2-VID/VOD SRT2-VID/VOD 48 Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Unit. Refer to page 80 for common precautions. Communications Connector Pin Arrangement 24-VDC communications power supply 24-VDC I/O power supply CompoBus/S communications The following solderless terminals are recommended. • Manufacturer: Weidmuller Sleeve (Part No. 046290) Solderless terminal Cable Two-wire insertion (Part No. 901851) Solderless terminal Cable The following product is a dedicated tool. • Manufacturer: Weidmuller PZ1.5 Crimper (Part No. 900599) Sensor Connector Pin Arrangement SRT2-VID08S/VID08S-1 SRT2-VOD08S/VOD08S-1 Model Cable conductor size XS8A-0441 0.3 to 0.5 mm2 XS8A-0442 0.14 to 0.2 mm2 Note: The XS8A-0441 or XS8A-0442 Connector is not provided with the SRT-VID or SRT2-VOD. Place an order for the connector separately. Calculate the cable conductor size as follows. The following information is given on each sensor cable: Cable dia. (Number of conductors/Conductor dia.) Conductor size (mm2) = (Conductor dia./2)2 x p x Number of conductors Example: E3S-A 4 dia. (18/0.12) Conductor size (mm2) = (0.12/2)2 x 3.14 x 18 􀀀 0.20 The conductor size is 0.2 mm2. Therefore, use the XS8A-0442. MIL Connector Pin Arrangement SRT2-VID16ML/VID16ML-1 Function Pin No. Pin No. OUT0 IN0 OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 G G V V 20 20 18 18 16 16 14 14 12 12 10 10 8 8 6 6 4 4 2 2 Function Function Pin No. Pin No. OUT8 IN8 OUT9 IN9 OUT10 IN10 OUT11 IN11 OUT12 IN12 OUT13 IN13 OUT14 IN14 OUT15 IN15 G G V V 19 19 17 17 15 15 13 13 11 11 9 9 7 7 5 5 3 3 1 1 SRT2-VOD16ML/VOD16ML-1 Function Note: 1. No cable connector is provided. Order the connector separately. • Applicable Connector XG4M-2030-T • Applicable Connector Cables G79-O50C G79-O25C G79-I50C G79-I25C 2. Refer to the following table for ordering information on the applicable Cables. SRT2-VID/VOD SRT2-VID/VOD 49 Applicable Cables Connectable product Model Applicable Cable I/O Block G7TC-OC16 G7TC-OC08 G7TC-ID16-5 G7TC-IA16-5 G79-O50C (L = 500 mm) G7TC IA16 G7VC Series G70A Series G70D Series e G79-O25C (L = 250 mm) Connector-Terminal Conversion Unit XW2B Series Digital Display Unit M7F I/O Block G7TC-ID16 G7TC-IA16 e G79-I50C (L = 500 mm) G7TC-OC16-1 G79-I25C (L = 250 mm) 50 Sensor Terminal SRT1-D08S Connector Connection Models that Allows Easy Connection to Sensors and Output Devices Sensors with easy-to-wire connectors are easily attached or detached. Connects to 2-wired sensors. Remote teaching of the Sensor Terminal is possible with the PC by using output signals of the Sensor Terminal. DIN track mounting and screw mounting are available. Ordering Information Classification Internal I/O circuit common I/O points Model For input NPN (– common) 8 input points SRT1-ID08S For I/O NPN (– common) 4 input/4 output points SRT1-ND08S For output NPN (– common) 8 output points SRT1-OD08S Specifications Ratings Input Item SRT1-ID08S/-ND08S Input current 10 mA max./point ON delay time 1 ms max. OFF delay time 1.5 ms max. ON voltage 12 VDC min. between each input terminal and VCC, the external sensor power supply OFF voltage 4 VDC max. between each input terminal and VCC, the external sensor power supply OFF current 1 mA max. Insulation method Photocoupler Input indicator LED (yellow) Output Item SRT1-ND08S SRT1-OD08S Rated output current 20 mA/point 30 mA/point Residual voltage 1 V max. 0.6 V max. ON delay time 1 ms max. --- OFF delay time 1.5 ms max. --- Leakage current 0.1 mA max. Insulation method Photocoupler Output indicator LED (yellow) SRT1-D08S SRT1-D08S 51 Characteristics Communications power supply voltage (see note 1) 14 to 26.4 VDC Current consumption (see note 2) 50 mA max. at 24 VDC Connection method Multi-drop method and T-branch method Secondary branches cannot be connected to T-branch lines. Dielectric strength 500 VAC for 1 min (1-mA sensing current between insulated circuits) Noise immunity Power supply normal: ±600 V for 10 minutes with a pulse width of 100 ns to 1 ms Power supply common: ±1,500 V for 10 minutes with a pulse width of 100 ns to 1 ms Vibration resistance 10 to 55 Hz, 1.5-mm double amplitude Shock resistance Malfunction: 200 m/s2 Destruction: 300 m/s2 Mounting method M4 screw mounting or 35-mm DIN track mounting Mounting strength No damage when 50 N pull load was applied for 10 s in all directions (except the DIN track directions and a pulling force of 10 N Terminal strength No damage when 50 N pull load was applied for 10 s in all directions Tighten each screw to a torque of 0.6 to 1.18 N 􀀀 m Ambient temperature Operating: 0°C to 55°C (with no icing or condensation) Storage: –20°C to 65°C (with no icing or condensation) Ambient humidity Operating: 35% to 85% Weight SRT1-ID08S/OD08S: 100 g max., SRT1-ND08S: 80 g max. Note: 1. The communications power supply voltage must be 20.4 to 26.4 VDC if the Unit is connected to 2-wired proximity sensors. 2. The above current consumption is a value with all the points turned OFF excluding the current consumption of the sensor connected to the Sensor Terminal. External Sensor Power Supply Power supply voltage 13.5 to 26.4 VDC Current consumption 500 mA max. in total Nomenclature SRT1-ID08S SRT1-ND08S CompoBus/S Terminals Connect the CompoBus/S communications cable. Sensor Terminal I/O Connectors Connect the cables from the sensors here. I/O Indicators Indicate the status of each point. (Lit when the input or output is ON.) The SRT1-ID08S has 8 input indicators and the SRT1-ND08S has 4 input indicators and 4 output indicators. DIP Switch The DIP switch’s pins have the following functions: Pins 1 to 4: Node number setting Pin 5: Reserved (Always OFF.) Pin 6: Hold/clear outputs for communications error DIN Track Mounting Hook Used when mounting the Unit to a DIN track. CompoBus/S Indicators Indicate the operating status of the Slave and the status of communications. Mounting Screw Holes Used when screwing the Unit to a control panel. Indicators PWR COMM ERR IN0 to 3 IN0 to 7 OUT0 to 3 Communications Power Supply Terminals Connect the communications power supply. SRT1-D08S SRT1-D08S 52 Indicators Indicator Name Display Color Meaning PWR Power supply Lit Green The communications power supply is ON. Not lit The communications power supply is OFF. COMM Communication Lit Yellow Normal communications Not lit A communications error has occurred or the Unit is in standby status. ERR Communication Lit Red A communications error has occurred. error Not lit Normal communications or the Unit is in standby status. 0 to 3 (4 inputs/outputs) Input Lit Yellow The corresponding input is ON. 0 to 7 (8 inputs) Not lit The corresponding input is OFF or the Unit is in standby status. 0 to 3 (4i t / t t ) o Output Lit Yellow The corresponding output is ON. 4 inputs/outputs) Not lit The corresponding output is OFF or the Unit is in standby status. Switch Setting All pins are factory-set to OFF. Hold/Clear outputs for Node number communications error settings Reserved (OFF) Pin 5 (Reserved) Always set pin 5 to OFF. Output HOLD/CLEAR Mode (SRT-ND16S) HOLD Function OFF Output status is cleared when a communications error occurs. ON Output status is maintained when a communications error occurs. Node Number Settings Node number 1 2 4 8 0 OFF OFF OFF OFF 1 ON OFF OFF OFF 2 OFF ON OFF OFF 3 ON ON OFF OFF 4 OFF OFF ON OFF 5 ON OFF ON OFF 6 OFF ON ON OFF 7 ON ON ON OFF 8 OFF OFF OFF ON 9 ON OFF OFF ON 10 OFF ON OFF ON 11 ON ON OFF ON 12 OFF OFF ON ON 13 ON OFF ON ON 14 OFF ON ON ON 15 ON ON ON ON SRT1-D08S SRT1-D08S 53 SRT1-OD08S DIP Switch Mounting Screw Holes Used when screwing the Unit to a control panel. CompoBus/S Indicators Indicate the operating status of the Slave and the status of communications. Output Indicators Indicate the output status of each channel. Communications Terminals Communications Power Supply Terminals Connect the communications cable. DIN Track Mounting Hook Used when mounting the Unit to a DIN track. Output Connectors Connect the cables from the output device. Switch Setting All pins are factory-set to OFF. Hold/Clear outputs for Node number communications error settings Reserved (OFF) Pin 5 (Reserved) Always set pin 5 to OFF. Output HOLD/CLEAR Mode (SRT-ND16S) HOLD Function OFF Output status is cleared when a communications error occurs. ON Output status is maintained when a communications error occurs. Node Number Settings Node number 4 3 2 1 0 OFF OFF OFF OFF 1 OFF OFF OFF ON 2 OFF OFF ON OFF 3 OFF OFF ON ON 4 OFF ON OFF OFF 5 OFF ON OFF ON 6 OFF ON ON OFF 7 OFF ON ON ON 8 ON OFF OFF OFF 9 ON OFF OFF ON 10 ON OFF ON OFF 11 ON OFF ON ON 12 ON ON OFF OFF 13 ON ON OFF ON 14 ON ON ON OFF 15 ON ON ON ON SRT1-D08S SRT1-D08S 54 Dimensions Note: All units are in millimeters unless otherwise indicated. SRT1-ID08S Mounting Holes SRT1-ND08S Mounting Holes 100 Cover opening and closing directions Two, 4.2 dia or M4 Four, M3 50 50 70 max. Four, M3 Cover opening and closing directions Two, 4.2 dia or M4 (75) (75) SRT1-D08S SRT1-D08S 55 SRT1-OD08S 100 Cover opening and closing directions (75) 2.8 37 Two, 4.2 dia. or M4 7 Four, M3 50 40 92 40±0.2 92±0.2 Mounting Holes 4 6 Cable Connector for SRT1-OD08S Applicable conductor size (mm2) Model 0.3 to 0.5 XS8A-0441 0.14 to 0.2 XS8A-0442 0.3 to 0.5 XS8B-0443 XS8B-0443 (Relay Socket ) XS8A-044 (Cable Connector) Plug connector Cover Model number Pin number Check window Calculate the cable conductor size as explained below. The following information is given on each sensor cable: Cable dia. (Number of conductors/Conductor dia.) Conductor size (mm2) = (Conductor dia./2)2 x p x Number of conductors Example: E3S-A 4 dia. (18/0.12) Conductor size (mm2) = (0.12/2)2 x 3.14 x 18 􀀀 0.20 The conductor size is 0.2 mm2. Therefore, use the XS8A-0442. SRT1-D08S SRT1-D08S 56 Installation Internal Circuit Configuration SRT1-ID08S SRT1-ND08S Internal circuit Photocoupler Internal circuit Photocoupler Photocoupler SRT1-OD08S Internal circuit For one output External Connections SRT1-ID08S SRT1-ND08S Three-wired Sensor Two-wired Sensor Sensor with Teaching Function Sensor with External Diagnostic function Sensor with Bank-switching Function Three-wired Sensor Brown Black Blue Sensor Brown Blue Sensor Brown Black Pink Blue Sensor Brown Black Blue Sensor Two-wired Sensor Brown Blue Sensor SRT1-D08S SRT1-D08S 57 Terminal Arrangement and I/O Device Connection Example Input SRT1-ID08S I/O SRT1-ND08S Photoelectric Sensor Proximity Sensor (Sensor with Teaching Function, Sensor with External Diagnostic function, Sensor with Bank-switching Function) 24 VDC Communications power supply CompoBus/S communications CompoBus/S communications Communications power supply Blue Brown Blue Black Brown Photoelectric Sensor Proximity Sensor (3-wired Sensor) Proximity Sensor (2-wired Sensor) CompoBus/S communications Communications power supply CompoBus/S communications Communications power supply Brown Brown Blue 24 VDC Orange CompoBus/S CompoBus/S Output SRT1-OD08S CompoBus/S SOURCE 24 VDC BDL BDH – + CompoBus/S communications Communications power supply Output connector Pin number Solenoid, etc. Valve, etc. Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Unit. General Safety Precautions Installation Environment Do not install the Unit in the following places. • Places with water, oil, or chemical sprayed on the Unit. • Places with rapid temperature changes. • Places with high humidity resulting in condensation. • Places with intense electric and magnetic fields. • Places with excessive vibration or shock. Wiring To prevent inductive noise, do not wire power lines or high-tension lines along with or near the cables. Make sure that the polarity of each terminal is correct. Make sure that the communications path and power line are connected correctly. Secure the cables properly. Do not pull the cables with strong force, otherwise the cables may be disconnected from the terminals or connectors of the Unit. Do not touch the Unit when the Unit is used in places with high ambient temperatures because the surface temperature of the Unit may be high. Do not use paint thinner to clean the surface of the Unit, otherwise the surface will be damaged or discolored. SRT1-D08S SRT1-D08S 58 Correct Use Use the Unit under its rated conditions. Mount the Unit with M4 screws or to DIN tracks securely. Typical Causes of Communications Errors • The cables are not connected correctly. • The node number setting is incorrect. • The baud rate setting is incorrect. • There is a strong noise source, such as an inverter motor, near the Unit. Install the Unit as far as possible from the noise source or shield the noise source. Others Use OMRON’s XS8A-0441 or XS8A-0442 Connectors with the Unit. Insert each connector into the Unit until the connector snaps in place. Make sure that terminal number 1 of the connector is on the lock lever side when inserting the connector. Refer to the CompoBus/S Operation Manual (W266) for wiring the Unit. 59 Sensor Amplifier Terminal SRT1-D04S Snap On to Connect and Save Wiring Effort The 4-channel fiber photoelectric amplifiers in Terminals with connectors offer a low cost and space savings. The product lineup included Terminal Block Units for easy connection to sensors with amplifiers, limit switches, etc. Connect to up to eight channels of sensors by using Expansion Blocks. Features Low Cost and Space Savings with Four-channel Fiber Connectors Just Snap On to Connect Connector Units Fiber connector (1 channel) Fiber connector (4 channels) Terminal Block Unit Photoelectric sensor Various input units can be connected. Proximity sensor Basic switch and limit switch SRT1-D04S SRT1-D04S 60 Ordering Information CompoBus/S Sensor Amplifier Terminals Classification I/O points Model Communications 4 SRT1-TID04S SRT1-TKD04S Expansion SRT1-XID04S SRT1-XKD04S Connector Units Classification Specifications Model E3X-N Connector Type General-purpose, 1 channel E3X-NT16 Multi-functional, 1 channel E3X-NT26 Long distance, high accuracy, 1 channel E3X-NH16 Multi-functional, 4 channels E3X-NM16 Terminal Block Unit One input point E39-JID01 SRT1-D04S SRT1-D04S 61 Specifications Characteristics CompoBus/S Sensor Amplifier Terminals Item Communication Terminals Expansion Terminals Model SRT1-TID04S SRT1-TKD04S SRT1-XID04S SRT1-XKD04S Communications power supply voltage 14 to 26.4 VDC (See note 1) --- --- I/O points 4 input points Connected sensors Total of four E3X-NT6 or E39-JID01 (See note 2) One E3X-NM16 (See note 2) Total of four E3X-NT6 or E39-JID01 One E3X-NM16 Current consumption 60 mA max. (See note 3) 10 mA max. (See note 3) Dielectric strength 500 VAC for 1 min (1-mA sensing current between insulated circuits) Noise immunity Power supply normal: ±600 V for 10 minutes with a pulse width of 100 ns to 1 ms Power supply common: ±1,500 V for 10 minutes with a pulse width of 100 ns to 1 ms Vibration resistance 10 to 55 Hz, 1.5-mm double amplitude Shock resistance Malfunction: 200 m/s2 Destruction: 300 m/s2 Mounting method M4 screw mounting or 35-mm DIN track mounting Mounting strength No damage when 50 N pull load was applied for 10 s in all directions (except the DIN track directions and a pulling force of 10 N Terminal strength No damage when 49 N pull load was applied for 10 s in all directions. Tighten each screw to a torque of 0.6 to 1.18 N 􀀀 m. Ambient temperature Operating: 0°C to 55°C (with no icing or condensation) Storage: –20°C to 65°C (with no icing or condensation) Ambient humidity Operating: 35% to 85% Weight 70 g max. 65 g max. 45 g max. 35 g max. Note: 1. The communications power supply voltage must be 20.4 to 26.4 VDC if the Terminal is connected to 2-wired proximity sensors. 2. When adding Connector Units, use SRT1-XID04S or SRT1-XKD04S. 3. The value doesn’t include the current consumption of Connector Units. With E3X-N Connectors Model E3X-NH16 E3X-NT16 E3X-NT26 E3X-NM16 Current consumption 75 mA max. 50 mA max. 150 mA Response time 1 ms max. (4.0 ms max. when connected to the SRM1-D04S) 500 mS max. (2.0 ms max. when connected to the SRT1-D04S) Timer function Not available OFF-delay timer (fixed to 40 ms) Remote teaching input Not available Available (Remote teaching disabled) Indicator Orange LED: Lit during output operation Green LED: Lit with stable light reception or no light Teaching confirmation function Indicators (red/green LED) and buzzer Output Light ON and Dark ON switch selectable Ambient illumination Sunlight: 10,000 lux max.; incandescent lamp: 3,000 lux max. Insulation resistance 20 MW max. (at 500 VDC) Dielectric strength 1,000 VAC at 50/60 Hz for 1 min Vibration resistance Destruction:10 to 55 Hz, 1.5-mm double amplitude Shock resistance Destruction:500 m/s2 Mounting method Connector connection to the SRT1-D04S Mounting strength No damage when 49 N pull load was applied for 10 s in all directions Ambient temperature Operating: 0°C to 55°C (with no icing or condensation) Storage: –20°C to 65°C (with no icing or condensation) Ambient humidity Operating: 35% to 85% Weight 30 g max. 30 g max. 30 g max. 60 g max. SRT1-D04S SRT1-D04S 62 Terminal Block Units Model E39-JID01 Input current 10 mA max. ON voltage 12 VDC min. between input terminal and external sensor power supply OFF voltage 4 VDC max. between input terminal and external sensor power supply OFF current 1 mA max. ON delay time 1 ms max. (connected to SRT1-D04S) OFF delay time 1.5 ms max. (connected to SRT1-D04S) Input indicators LED (Orange) External sensor current capacity 50 mA max. Vibration resistance 10 to 55 Hz, 1.5-mm double amplitude Shock resistance Malfunction: 200 m/s2 Destruction: 300 m/s2 Mounting method M4 screws or 35-mm DIN track mounting Mounting strength No damage when 50 N pull load was applied for 10 s in all directions (except the DIN track directions and a pulling force of 10 N Terminal strength No damage when 49 N pull load was applied for 10 s in all directions. Tighten each screw to a torque of 0.6 to 1.18 N 􀀀 m. Ambient temperature Operating: 0°C to 55°C (with no icing or condensation) Storage: –20°C to 65°C (with no icing or condensation) Ambient humidity Operating: 35% to 85% Weight 25 g max. SRT1-D04S SRT1-D04S 63 Nomenclature SRT1-TID04S SRT1-TKD04S Mounting Screw Holes Communications Terminals Communications Power Supply Terminals Contact 0 Contact 1 Contact 2 Contact 3 DIN Track Mounting Hook Node Number Settings Refer to the CompoBus/S Operation Manual (W266) for details on DIP switch settings. Mounting Screw Holes DIN Track Mounting Hook Contacts 0 to 3 Communications Power Supply Terminals Connect a 24-VDC power supply. Communications Terminals Connect a communications cable. DIP Switch Indicators Indicator Name Display Color Meaning PWR Power supply Lit Green The communications power supply is ON. Not lit G ee The communications power supply is OFF. COMM Communications Lit Yellow Normal communications. Not lit e o A communications error has occurred or the Unit is in standby status. ERR Communications Lit Red A communications error has occurred. error Not lit ed Normal communications or the Unit is in standby status. SRT1-D04S SRT1-D04S 64 Dimensions Note: All units are in millimeters unless otherwise indicated. SRT1-TID04 Two, 4.2 dia. or M4 Two, 4.5 dia. Mounting Holes (75) 3.4 Two, 4.2 dia. or M4 Two, 4.5 dia. SRT1-XID04S Mounting Holes (75) 3.4 SRT1-D04S SRT1-D04S 65 SRT1-TKD04S Two, 4.2 dia. or M4 Two, 4.5 dia. Mounting Holes (75) 3.4 SRT1-XKD04S Two, 4.2 dia. or M4 Two, 4.5 dia. Mounting Holes (75) 3.4 SRT1-D04S SRT1-D04S 66 E3X-NM16 Output indicator Stability indicator Eight, 2.4 dia. E3X-NT6 Output indicator Stability indicator Two, 2.4 dia. SRT1-D04S SRT1-D04S 67 E3X-NH16 Light level indicators Threshold indicators Output indicator Two, 2.4 dia. E39-JID01 Output indicator Installation Internal Circuit Configuration E39-JID01 Internal circuit SRT1-D04S SRT1-D04S 68 Precautions Refer to the CompoBus/S Operation Manual (W266) before using the Terminal. Refer to page 80 for precautions common to all SRT1 Terminals. General Safety Precautions Connector Units Use only the Connector Units listed in this data sheet for the Sensor Amplifier Units. E39-JID01 Terminal Block Unit Do not apply any voltage to the Terminal Block Unit. Correct Use Expanding Sensor Amplifier Terminals 1. Remove the cover from the side of the SRT1-TD04S. (See Figure 1.) 2. When the cover is removed, you can see the expansion connector inside. 3. Connect this expansion connector to the connector located on the side of the SRT1-XD04S. (See Figure 2.) Figure 1 Cover Figure 2 Connector Attaching and Removing Connector Units (SRT1-TID04S, SRT1-XID04S, E3X-NT6, E39-JID01) Attaching Connector Units 1. Hook Section A of the Connector Unit onto Section B of the Sensor Amplifier Terminal. 2. Push in the Connector Unit until Section C locks inside Section D of the Sensor Amplifier Terminal. Section C Section D Section A Section B Bottom View Section A Removing Connector Units 1. While pushing Section D, pull the Connector Unit in direction E. 2. When Section D releases from the lock, the Connector Unit can be removed. Push here Section D SRT1-D04S SRT1-D04S 69 Attaching or Removing Connector Unit (SRT1-TKD04S, SRT1-XKD04S, E3X-NM16) Attaching Connector Unit 1. Hook Section A of the Connector Unit onto Section B of the Sensor Amplifier Terminal. 2. Push in the Connector Unit until Section C locks inside Section D of the Sensor Amplifier Terminal. Bottom View Section A Section C Section D Section A Section B Removing Connector Unit 1. While pushing Section D, pull the Connector Unit in direction E. 2. When Section D releases from the lock, the Connector Unit can be removed. Push here Section D Channel Numbers Channel numbers 1 to 4 of the E3X-NM16 correspond to contact numbers 0 to 3 of the SRT1-TKD04S, and to contact numbers 4 to 7 of the SRT1-XKD04S. 70 Analog Input Terminal SRT2-AD04 Compact Analog Input Model is the Same Shape as 16-point Remote I/O Terminals Allows flexible input point settings up to a maximum of four points. Resolution: 1/6,000 Takes only 1 ms to exchange each input point. Wide input ranges available. 105 x 48 x 50 (W x H x D) Ordering Information Classification I/O points Model Analog Input Terminal 1 to 4 (selectable with DIP switch) SRT2-AD04 Note: For details about connecting the SRT2-AD04 to the Master Unit. Refer to page 10. Specifications Ratings Input Item Voltage input Current input Max. signal input ±15 V ±30 mA Input impedance 1 MW