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cree® Xlamp® mK-r leds - PDF - Farnell Element 14

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CLD-DS60 Rev 5A Product family data sheet Cree® XLamp® MK-R LEDs WWW.CREE.COM/XLAMP Copyright © 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. Product Description Built on Cree’s revolutionary SC³ Technology™ platform, the XLamp MK‑R LED brings new levels of price and performance to directional LED arrays, enabling lighting manufacturers to create the next generation of high-lumen indoor and outdoor LED lighting systems. In single-LED systems, the XLamp MK‑R, with EasyWhite® color binning, provides the LED industry’s tightest unit-to-unit color consistency. For systems using multiple LEDs, the MK-R enables manufacturers to use fewer LEDs while maintaining light output and color consistency, which translates to lower system cost. The XLamp MK‑R is optimized for directional lighting applications and is a welcome addition to applications requiring high lumen output, a compact optical source and a broad palette of color temperature and CRI values. FEATURES • Available in ANSI white bins as well as 4-step and 2-step EasyWhite bins at 2700 K, 3000 K, 3500 K, 4000 K, 4500 K and 5000 K CCT • Two voltage options: 6 V & 12 V • Low thermal resistance: 1.7 °C/W • Maximum junction temperature: 150 °C • Binned at 85 °C • Viewing angle: 120° • Available in cool white, 70-, 80- and 90‑CRI minimums • Unlimited floor life at ≤ 30 ºC/85% RH • Reflow solderable - JEDEC J‑STD‑020C • Electrically neutral thermal path • RoHS‑ and REACh‑compliant • UL-recognized component (E349212) Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 www.cree.com/xlamp Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Table of Contents Characteristics....................................2 Flux Characteristics, Standard Order Codes and Bins - 6 V............................3 Flux Characteristics, ANSI White Order Codes and Bins - 6 V............................4 Flux Characteristics, Standard Order Codes and Bins -12 V...........................5 Flux Characteristics, ANSI White Order Codes and Bins - 12 V..........................6 Relative Spectral Power Distribution.......7 Relative Flux vs. Junction Temperature...7 Electrical Characteristics.......................8 Relative Flux vs. Current......................9 Relative Chromaticity vs. Current - Warm White......................................10 Relative Chromaticity vs. Temperature - Warm White......................................11 Typical Spatial Distribution..................11 Thermal Design.................................12 Performance Groups - Brightness.........13 Performance Groups - Chromaticity......14 Cree EasyWhite Bins Plotted on the 1931 CIE Color Space........................17 Cree ANSI White Bins Plotted on the 1931 CIE Color Space........................18 Bin and Order Code Formats...............19 Reflow Soldering Characteristics..........20 Notes...............................................21 Mechanical Dimensions......................22 Tape and Reel...................................23 Packaging.........................................24 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 2 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Characteristics Characteristics Unit Minimum Typical Maximum Thermal resistance, junction to solder point °C/W 1.7 Viewing angle - full width half maximum (FWHM) degrees 120 Temperature coefficient of voltage (6 V, 1400 mA, 85 °C) mV/°C -4 Temperature coefficient of voltage (12 V, 700 mA, 85 °C) mV/°C -8 ESD withstand voltage (HBM per Mil-Std-883D) V 8000 DC forward current (6 V, 1400 mA, 85 °C) mA 2500 DC forward current (12 V, 700 mA, 85 °C) mA 1250 Reverse voltage V -5 Forward voltage (6 V, 1400 mA, 85 °C) V 5.85 7 Forward voltage (12 V, 700 mA, 85 °C) V 11.7 14 LED junction temperature °C 150 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 3 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Flux Characteristics, Standard Order Codes and Bins - 6 V (If = 1400 mA, TJ = 85 °C) The following tables provide order codes for XLamp MK‑R EasyWhite LEDs. For a complete description of the order code nomenclature, please reference Bin and Order Code Formats (page 19). Color CCT Range Base Order Codes Min. Luminous Flux @ 1400 mA 2-Step Order Code 4-Step Order Code Group Flux (lm) @ 85 °C Flux (lm) @ 25 °C* Chromaticity Region Chromaticity Region 80-CRI EasyWhite 5000 K H2 900 1044 50H MKRAWT-00-0000-0B0HH250H 50F MKRAWT-00-0000-0B0HH250F G4 840 974 MKRAWT-00-0000-0B0HG450H MKRAWT-00-0000-0B0HG450F 4500 K H2 900 1044 45H MKRAWT-00-0000-0B0HH245H 45F MKRAWT-00-0000-0B0HH245F G4 840 974 MKRAWT-00-0000-0B0HG445H MKRAWT-00-0000-0B0HG445F 4000 K H2 900 1044 40H MKRAWT-00-0000-0B0HH240H 40F MKRAWT-00-0000-0B0HH240F G4 840 974 MKRAWT-00-0000-0B0HG440H MKRAWT-00-0000-0B0HG440F 3500 K G4 840 974 35H MKRAWT-00-0000-0B0HG435H 35F MKRAWT-00-0000-0B0HG435F G2 780 905 MKRAWT-00-0000-0B0HG235H MKRAWT-00-0000-0B0HG235F 3000 K G4 840 974 30H MKRAWT-00-0000-0B0HG430H 30F MKRAWT-00-0000-0B0HG430F G2 780 905 MKRAWT-00-0000-0B0HG230H MKRAWT-00-0000-0B0HG230F 2700 K G2 780 905 27H MKRAWT-00-0000-0B0HG227H 27F MKRAWT-00-0000-0B0HG227F F4 730 847 MKRAWT-00-0000-0B0HF427H MKRAWT-00-0000-0B0HF427F 90-CRI EasyWhite 3000 K E4 635 737 30H MKRAWT-00-0000-0B0UE430H 30F MKRAWT-00-0000-0B0UE430F E2 590 684 MKRAWT-00-0000-0B0UE230H MKRAWT-00-0000-0B0UE230F 2700 K E2 590 684 27H MKRAWT-00-0000-0B0UE227H 27F MKRAWT-00-0000-0B0UE227F D4 550 638 MKRAWT-00-0000-0B0UD427H MKRAWT-00-0000-0B0UD427F Notes: • Cree maintains a tolerance of ± 7% on flux and power measurements, ± 0.005 on chromaticity (CCx, CCy) measurements and ± 2 on CRI measurements. • Minimum CRI for 80-CRI White is 80. • Minimum CRI for 90-CRI White is 90. * Flux values @ 25 °C are calculated and for reference only. xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 4 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Flux Characteristics, ANSI White Order Codes and Bins - 6 V (If = 1400 mA, TJ = 85 °C) XLamp MK-R Standard ANSI Kit Codes Chromaticity Minimum Luminous Flux (lm) @ 1400 mA** Order Codes Kit CCT Code Flux (lm)@ 85 °C Flux (lm) @ 25 °C* 65 CRI Typical 70 CRI Minimum 80 CRI Minimum 90 CRI Minimum ANSI White (2700 K - 8300 K) 51 6200 K J2 1040 1206 MKRAWT-00-0000-0B00J2051 H4 970 1125 MKRAWT-00-0000-0B00H4051 MKRAWT-00-0000-0B0BH4051 H2 900 1044 MKRAWT-00-0000-0B0BH2051 E1 6500 K J2 1040 1206 MKRAWT-00-0000-0B00J20E1 H4 970 1125 MKRAWT-00-0000-0B00H40E1 MKRAWT-00-0000-0B0BH40E1 H2 900 1044 MKRAWT-00-0000-0B0BH20E1 E2 5700 K H4 970 1125 MKRAWT-00-0000-0B00H40E2 MKRAWT-00-0000-0B0BH40E2 H2 900 1044 MKRAWT-00-0000-0B0BH20E2 E3 5000 K H4 970 1125 MKRAWT-00-0000-0B00H40E3 MKRAWT-00-0000-0B0BH40E3 H2 900 1044 MKRAWT-00-0000-0B00H20E3 MKRAWT-00-0000-0B0BH20E3 MKRAWT-00-0000-0B0HH20E3 G4 840 974 MKRAWT-00-0000-0B0HG40E3 E4 4500 K H4 970 1125 MKRAWT-00-0000-0B00H40E4 MKRAWT-00-0000-0B0BH40E4 H2 900 1044 MKRAWT-00-0000-0B00H20E4 MKRAWT-00-0000-0B0BH20E4 MKRAWT-00-0000-0B0HH20E4 G4 840 974 MKRAWT-00-0000-0B0HG40E4 E5 4000 K H2 900 1044 MKRAWT-00-0000-0B00H20E5 MKRAWT-00-0000-0B0BH20E5 MKRAWT-00-0000-0B0HH20E5 G4 840 974 MKRAWT-00-0000-0B00G40E5 MKRAWT-00-0000-0B0BG40E5 MKRAWT-00-0000-0B0HG40E5 E6 3500 K H2 900 1044 MKRAWT-00-0000-0B0BH20E6 G4 840 974 MKRAWT-00-0000-0B0BG40E6 MKRAWT-00-0000-0B0HG40E6 G2 780 905 MKRAWT-00-0000-0B0HG20E6 E7 3000 K G4 840 974 MKRAWT-00-0000-0B0HG40E7 G2 780 905 MKRAWT-00-0000-0B0HG20E7 F4 730 847 F2 680 789 E4 635 737 MKRAWT-00-0000-0B0UE40E7 E2 590 684 MKRAWT-00-0000-0B0UE20E7 E8 2700 K G2 780 905 MKRAWT-00-0000-0B0HG20E8 F4 730 847 MKRAWT-00-0000-0B0HF40E8 F2 680 789 E4 635 737 E2 590 684 MKRAWT-00-0000-0B0UE20E8 D4 550 638 MKRAWT-00-0000-0B0UD40E8 ** Cree XLamp MK‑R order codes specify only a minimum flux bin and not a maximum. Cree may ship reels in flux bins higher than the minimum specified by the order code without advance notice. Shipments will always adhere to the chromaticity restrictions specified by the order code. * Flux values @ 25 °C are calculated and for reference only. • For information on chromaticity bins contained in the kits listed above, please reference the Performance Groups - Chromaticity section starting on page 13. • Minimum CRI for 70-CRI White is 70. xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 5 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Flux Characteristics, Standard Order Codes and Bins -12 V (If = 700 mA, TJ = 85 °C) The following tables provide order codes for XLamp MK‑R EasyWhite LEDs. For a complete description of the order code nomenclature, please reference Bin and Order Code Formats (page 19). Color CCT Range Base Order Codes Min. Luminous Flux @ 700 mA 2-Step Order Code 4-Step Order Code Group Flux (lm) @ 85 °C Flux (lm) @ 25 °C* Chromaticity Region Chromaticity Region 80-CRI EasyWhite 5000 K H2 900 1044 50H MKRAWT-00-0000-0D0HH250H 50F MKRAWT-00-0000-0D0HH250F G4 840 974 MKRAWT-00-0000-0D0HG450H MKRAWT-00-0000-0D0HG450F 4500 K H2 900 1044 45H MKRAWT-00-0000-0D0HH245H 45F MKRAWT-00-0000-0D0HH245F G4 840 974 MKRAWT-00-0000-0D0HG445H MKRAWT-00-0000-0D0HG445F 4000 K H2 900 1044 40H MKRAWT-00-0000-0D0HH240H 40F MKRAWT-00-0000-0D0HH240F G4 840 974 MKRAWT-00-0000-0D0HG440H MKRAWT-00-0000-0D0HG440F 3500 K G4 840 974 35H MKRAWT-00-0000-0D0HG435H 35F MKRAWT-00-0000-0D0HG435F G2 780 905 MKRAWT-00-0000-0D0HG235H MKRAWT-00-0000-0D0HG235F 3000 K G4 840 974 30H MKRAWT-00-0000-0D0HG430H 30F MKRAWT-00-0000-0D0HG430F G2 780 905 MKRAWT-00-0000-0D0HG230H MKRAWT-00-0000-0D0HG230F 2700 K G2 780 905 27H MKRAWT-00-0000-0D0HG227H 27F MKRAWT-00-0000-0D0HG227F F4 730 847 MKRAWT-00-0000-0D0HF427H MKRAWT-00-0000-0D0HF427F 90-CRI EasyWhite 3000 K E4 635 737 30H MKRAWT-00-0000-0D0UE430H 30F MKRAWT-00-0000-0D0UE430F E2 590 684 MKRAWT-00-0000-0D0UE230H MKRAWT-00-0000-0D0UE230F 2700 K E2 590 684 27H MKRAWT-00-0000-0D0UE227H 27F MKRAWT-00-0000-0D0UE227F D4 550 638 MKRAWT-00-0000-0D0UD427H MKRAWT-00-0000-0D0UD427F Notes: • Cree maintains a tolerance of ± 7% on flux and power measurements, ± 0.005 on chromaticity (CCx, CCy) measurements and ± 2 on CRI measurements. • Minimum CRI for 80-CRI White is 80. • Minimum CRI for 90-CRI White is 90. * Flux values @ 25 °C are calculated and for reference only. xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 6 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Flux Characteristics, ANSI White Order Codes and Bins - 12 V (If = 700 mA, TJ = 85 °C) XLamp MK-R Standard ANSI Kit Codes Chromaticity Minimum Luminous Flux (lm) @ 700 mA** Order Codes Kit CCT Code Flux (lm)@ 85 °C Flux (lm) @ 25 °C* 65 CRI Typical 70 CRI Minimum 80 CRI Minimum 90 CRI Minimum ANSI White (2700 K - 8300 K) 51 6200 K J2 1040 1206 MKRAWT-00-0000-0D00J2051 H4 970 1125 MKRAWT-00-0000-0D00H4051 MKRAWT-00-0000-0D0BH4051 H2 900 1044 MKRAWT-00-0000-0D0BH2051 E1 6500 K J2 1040 1206 MKRAWT-00-0000-0D00J20E1 H4 970 1125 MKRAWT-00-0000-0D00H40E1 MKRAWT-00-0000-0D0BH40E1 H2 900 1044 MKRAWT-00-0000-0D0BH20E1 E2 5700 K H4 970 1125 MKRAWT-00-0000-0D00H40E2 MKRAWT-00-0000-0D0BH40E2 H2 900 1044 MKRAWT-00-0000-0D0BH20E2 E3 5000 K H4 970 1125 MKRAWT-00-0000-0D00H40E3 MKRAWT-00-0000-0D0BH40E3 H2 900 1044 MKRAWT-00-0000-0D00H20E3 MKRAWT-00-0000-0D0BH20E3 MKRAWT-00-0000-0D0HH20E3 G4 840 974 MKRAWT-00-0000-0D0HG40E3 E4 4500 K H4 970 1125 MKRAWT-00-0000-0D00H40E4 MKRAWT-00-0000-0D0BH40E4 H2 900 1044 MKRAWT-00-0000-0D00H20E4 MKRAWT-00-0000-0D0BH20E4 MKRAWT-00-0000-0D0HH20E4 G4 840 974 MKRAWT-00-0000-0D0HG40E4 E5 4000 K H2 900 1044 MKRAWT-00-0000-0D00H20E5 MKRAWT-00-0000-0D0BH20E5 MKRAWT-00-0000-0D0HH20E5 G4 840 974 MKRAWT-00-0000-0D00G40E5 MKRAWT-00-0000-0D0BG40E5 MKRAWT-00-0000-0D0HG40E5 E6 3500 K H2 900 1044 MKRAWT-00-0000-0D0BH20E6 G4 840 974 MKRAWT-00-0000-0D0BG40E6 MKRAWT-00-0000-0D0HG40E6 G2 780 905 MKRAWT-00-0000-0D0HG20E6 E7 3000 K G4 840 974 MKRAWT-00-0000-0D0HG40E7 G2 780 905 MKRAWT-00-0000-0D0HG20E7 F4 730 847 F2 680 789 E4 635 737 MKRAWT-00-0000-0D0UE40E7 E2 590 684 MKRAWT-00-0000-0D0UE20E7 E8 2700 K G2 780 905 MKRAWT-00-0000-0D0HG20E8 F4 730 847 MKRAWT-00-0000-0D0HF40E8 F2 680 789 E4 635 737 E2 590 684 MKRAWT-00-0000-0D0UE20E8 D4 550 638 MKRAWT-00-0000-0D0UD40E8 ** Cree XLamp MK‑R order codes specify only a minimum flux bin and not a maximum. Cree may ship reels in flux bins higher than the minimum specified by the order code without advance notice. Shipments will always adhere to the chromaticity restrictions specified by the order code. * Flux values @ 25 °C are calculated and for reference only. • For information on chromaticity bins contained in the kits listed above, please reference the Performance Groups - Chromaticity section starting on page 13. • Minimum CRI for 70-CRI White is 70. xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 7 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Relative Spectral Power Distribution (6 V, 1400 mA; 12 V, 700 mA; TJ= 85 °C) Relative Flux vs. Junction Temperature (6 V, IF = 1400 mA; 12 V, IF = 700 mA) Relative Spectral Power 0 20 40 60 80 100 380 430 480 530 580 630 680 730 780 Relative Radiant Power (%) Wavelength (nm) Cool White Neutral White Warm White Relative Flux Output vs. Junction Temperature 0 20 40 60 80 100 120 25 50 75 100 125 150 Relative Luminous Flux (%) Junction Temperature (ºC) xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 8 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Electrical Characteristics (TJ = 85 °C) Electrical Characteristics (Tj = 85ºC) 0 500 1000 1500 2000 2500 5.25 5.50 5.75 6.00 6.25 Forward Current (mA) Forward Voltage (V) 6 V Electrical Characteristics (Tj = 85ºC) 0 250 500 750 1000 1250 10.5 11.0 11.5 12.0 12.5 Forward Current (mA) Forward Voltage (V) 12 V xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 9 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Relative Flux vs. Current (TJ = 85 °C) Relative Intensity vs. Current (Tj = 85ºC) 0 30 60 90 120 150 180 0 500 1000 1500 2000 2500 Relative Luminous Flux (%) Forward Current (mA) 6 V Relative Intensity vs. Current (Tj = 85ºC) 0 30 60 90 120 150 180 0 250 500 750 1000 1250 Relative Luminous Flux (%) Forward Current (mA) 12 V xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 10 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Relative Chromaticity vs. Current - Warm White (TJ = 85 °C) -0.006 -0.004 -0.002 0.000 0.002 0.004 0.006 0 500 1000 1500 2000 2500 Current (mA) ΔCCx ΔCCy 6 V Relative Chromaticity Vs. Current - Warm White -0.006 -0.004 -0.002 0.000 0.002 0.004 0.006 0 250 500 750 1000 1250 Current (mA) ΔCCx ΔCCy 12 V xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 11 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Relative Chromaticity vs. Temperature - Warm White (6 V, IF = 1400 mA; 12 V, IF = 700 mA) Typical Spatial Distribution Relative Chromaticity Vs. Temperature - Warm White ΔCCx -0.006 -0.004 -0.002 0.000 0.002 0.004 0.006 0 25 50 75 100 125 150 Tsp (°C) ΔCCx ΔCCy Typical Spatial Radiation Pattern 0 20 40 60 80 100 -100 -80 -60 -40 -20 0 20 40 60 80 100 Relative Luminous Intensity (%) Angle (º) xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 12 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Thermal Design The maximum forward current is determined by the thermal resistance between the LED junction and ambient. It is crucial for the end product to be designed in a manner that minimizes the thermal resistance from the solder point to ambient in order to optimize lamp life and optical characteristics. 0 500 1000 1500 2000 2500 3000 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 2°C/W Rj-a = 4°C/W Rj-a = 6°C/W Rj-a = 8°C/W 6 V Thermal Design 0 200 400 600 800 1000 1200 1400 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 2°C/W Rj-a = 4°C/W Rj-a = 6°C/W Rj-a = 8°C/W 12 V xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 13 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Performance Groups - Brightness (Tj = 85 °C) XLamp MK-R LEDs are tested for luminous flux and placed into one of the following bins. Group Code Min. Luminous Flux Max. Luminous Flux D2 510 550 D4 550 590 E2 590 635 E4 635 680 F2 680 730 F4 730 780 G2 780 840 G4 840 900 H2 900 970 H4 970 1040 J2 1040 1120 J4 1120 1200 K2 1200 1290 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 14 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Performance Groups - Chromaticity (Tj = 85 °C) XLamp MK‑R LEDs are tested for chromaticity and placed into one of the regions defined by the following bounding coordinates. EasyWhite Color Temperatures – 4-Step Code CCT x y 50F 5000 K 0.3407 0.3459 0.3415 0.3586 0.3499 0.3654 0.3484 0.3521 45F 4500 K 0.3674 0.3772 0.3582 0.3710 0.3562 0.3573 0.3642 0.3625 40F 4000 K 0.3744 0.3685 0.3782 0.3837 0.3912 0.3917 0.3863 0.3758 35F 3500 K 0.3981 0.3800 0.4040 0.3966 0.4186 0.4037 0.4116 0.3865 30F 3000 K 0.4242 0.3919 0.4322 0.4096 0.4449 0.4141 0.4359 0.3960 27F 2700 K 0.4475 0.3994 0.4573 0.4178 0.4695 0.4207 0.4589 0.4021 EasyWhite Color Temperatures – 2-Step Code CCT x y 50H 5000 K 0.3429 0.3507 0.3434 0.3571 0.3475 0.3604 0.3469 0.3539 45H 4500 K 0.3643 0.3720 0.3597 0.3689 0.3587 0.3620 0.3628 0.3647 40H 4000 K 0.3784 0.3741 0.3804 0.3818 0.3867 0.3857 0.3844 0.3778 35H 3500 K 0.4030 0.3857 0.4061 0.3941 0.4132 0.3976 0.4099 0.3890 30H 3000 K 0.4291 0.3973 0.4333 0.4062 0.4395 0.4084 0.4351 0.3994 27H 2700 K 0.4528 0.4046 0.4578 0.4138 0.4638 0.4152 0.4586 0.4060 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 15 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Performance Groups - Chromaticity (Tj = 85 °C) - cONTINUED ANSI White Bins Code CCT Bin Code x y Bin Code x y Bin Code x y Bin Code x y 051 6200 K 0A0 0.2920 0.3060 0R0 0.2950 0.2970 1A0 0.3048 0.3207 1R0 0.3068 0.3113 0.2984 0.3133 0.3009 0.3042 0.3130 0.3290 0.3144 0.3186 0.3009 0.3042 0.3037 0.2937 0.3144 0.3186 0.3161 0.3059 0.2950 0.2970 0.2980 0.2880 0.3068 0.3113 0.3093 0.2993 0B0 0.2895 0.3135 0S0 0.2870 0.3210 1B0 0.3028 0.3304 1S0 0.3005 0.3415 0.2962 0.3220 0.2937 0.3312 0.3115 0.3391 0.3099 0.3509 0.2984 0.3133 0.2962 0.3220 0.3130 0.3290 0.3115 0.3391 0.2920 0.3060 0.2895 0.3135 0.3048 0.3207 0.3028 0.3304 0C0 0.2962 0.3220 0T0 0.2937 0.3312 1C0 0.3115 0.3391 1T0 0.3099 0.3509 0.3028 0.3304 0.3005 0.3415 0.3205 0.3481 0.3196 0.3602 0.3048 0.3207 0.3028 0.3304 0.3213 0.3373 0.3205 0.3481 0.2984 0.3133 0.2962 0.3220 0.3130 0.3290 0.3115 0.3391 0D0 0.2984 0.3133 0U0 0.3009 0.3042 1D0 0.3130 0.3290 1U0 0.3144 0.3186 0.3048 0.3207 0.3068 0.3113 0.3213 0.3373 0.3221 0.3261 0.3068 0.3113 0.3093 0.2993 0.3221 0.3261 0.3231 0.3120 0.3009 0.3042 0.3037 0.2937 0.3144 0.3186 0.3161 0.3059 ANSI White Bins Code CCT Bin Code x y Bin Code x y Bin Code x y 051 6200 K 2A0 0.3215 0.3350 2R0 0.3222 0.3243 3A0 .3371 .3490 0.3290 0.3417 0.3290 0.3300 .3451 .3554 0.3290 0.3300 0.3290 0.3180 .3440 .3427 0.3222 0.3243 0.3231 0.3120 .3366 .3369 2B0 0.3207 0.3462 2S0 0.3196 0.3602 3B0 .3376 .3616 0.3290 0.3538 0.3290 0.3690 .3463 .3687 0.3290 0.3417 0.3290 0.3538 .3451 .3554 0.3215 0.3350 0.3207 0.3462 .3371 .3490 2C0 0.3290 0.3538 2T0 0.3290 0.3690 3C0 .3463 .3687 0.3376 0.3616 0.3381 0.3762 .3551 .3760 0.3371 0.3490 0.3376 0.3616 .3533 .3620 0.3290 0.3417 0.3290 0.3538 .3451 .3554 2D0 0.3290 0.3417 2U0 0.3290 0.3300 3D0 .3451 .3554 0.3371 0.3490 0.3366 0.3369 .3533 .3620 0.3366 0.3369 0.3361 0.3245 .3515 .3487 0.3290 0.3300 0.3290 0.3180 .3440 .3427 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 16 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Performance Groups - Chromaticity (Tj = 85 °C) - cONTINUED ANSI White Bins Code CCT Bin Code x y 0E3 5000 K 3A0 .3371 .3490 .3451 .3554 .3440 .3427 .3366 .3369 3B0 .3376 .3616 .3463 .3687 .3451 .3554 .3371 .3490 3C0 .3463 .3687 .3551 .3760 .3533 .3620 .3451 .3554 3D0 .3451 .3554 .3533 .3620 .3515 .3487 .3440 .3427 ANSI White Bins Code CCT Bin Code x y 0E2 5700 K 2A0 0.3215 0.3350 0.3290 0.3417 0.3290 0.3300 0.3222 0.3243 2B0 0.3207 0.3462 0.3290 0.3538 0.3290 0.3417 0.3215 0.3350 2C0 0.3290 0.3538 0.3376 0.3616 0.3371 0.3490 0.3290 0.3417 2D0 0.3290 0.3417 0.3371 0.3490 0.3366 0.3369 0.3290 0.3300 ANSI White Bins Code CCT Bin Code x y 0E1 6500 K 1A0 0.3048 0.3207 0.3130 0.3290 0.3144 0.3186 0.3068 0.3113 1B0 0.3028 0.3304 0.3115 0.3391 0.3130 0.3290 0.3048 0.3207 1C0 0.3115 0.3391 0.3205 0.3481 0.3213 0.3373 0.3130 0.3290 1D0 0.3130 0.3290 0.3213 0.3373 0.3221 0.3261 0.3144 0.3186 ANSI White Bins Code CCT Bin Code x y 0E5 4000 K 5A0 .3670 .3578 .3702 .3722 .3825 .3798 .3783 .3646 5B0 .3702 .3722 .3736 .3874 .3869 .3958 .3825 .3798 5C0 .3825 .3798 .3869 .3958 .4006 .4044 .3950 .3875 5D0 .3783 .3646 .3825 .3798 .3950 .3875 .3898 .3716 ANSI White Bins Code CCT Bin Code x y 0E6 3500 K 6A0 .3889 .3690 .3941 .3848 .4080 .3916 .4017 .3751 6B0 .3941 .3848 .3996 .4015 .4146 .4089 .4080 .3916 6C0 .4080 .3916 .4146 .4089 .4299 .4165 .4221 .3984 6D0 .4017 .3751 .4080 .3916 .4221 .3984 .4147 .3814 ANSI White Bins Code CCT Bin Code x y 0E4 4500 K 4A0 .3530 .3597 .3615 .3659 .3590 .3521 .3512 .3465 4B0 .3548 .3736 .3641 .3804 .3615 .3659 .3530 .3597 4C0 .3641 .3804 .3736 .3874 .3702 .3722 .3615 .3659 4D0 .3668 .3957 .3771 .4034 .3736 .3874 .3641 .3804 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 17 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Performance Groups - Chromaticity (Tj = 85 °C) - cONTINUED Cree EasyWhite Bins Plotted on the 1931 CIE Color Space (Tj = 85 °C) ANSI White Bins Code CCT Bin Code x y 0E7 3000 K 7A0 .4147 .3814 .4221 .3984 .4342 .4028 .4259 .3853 7B0 .4221 .3984 .4299 .4165 .4430 .4212 .4342 .4028 7C0 .4342 .4028 .4430 .4212 .4562 .4260 .4465 .4071 7D0 .4259 .3853 .4342 .4028 .4465 .4071 .4373 .3893 ANSI White Bins Code CCT Bin Code x y 0E8 2700 K 8A0 .4373 .3893 .4465 .4071 .4582 .4099 .4483 .3919 8B0 .4465 .4071 .4562 .4260 .4687 .4289 .4582 .4099 8C0 .4582 .4099 .4687 .4289 .4813 .4319 .4700 .4126 8D0 .4483 .3919 .4582 .4099 .4700 .4126 .4593 .3944 2700K 3000K 3500K 4000K 4500K 5000K 5700K 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 0.45 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49 CCy CCx ANSI C78.377 Quadrangle EasyWhite 4-step EasyWhite 2-step xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 18 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Cree ANSI White Bins Plotted on the 1931 CIE Color Space (Tj = 85 °C) 2600K 2900K 2700K 3000K 3200K 3500K 3700K 4000K 4300K 4500K 4750K 5000K 5300K 3A 3B 3C 3D 4A 4B 4C 4D 5A 5B 5C 5D 6A 6B 6C 6D 7A 7B 7C 7D 8A 8B 8C 8D 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 0.45 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49 CCy CCx ANSI C78.377A 5000K 5700K 6500K 8000K 0A 0B 0C 0D 0R 0S 0T 0U 1A 1B 1C 1D 2A 2B 2C 2D 3A 3B 1R 1S 1T 1U 2R 2S 2T 2U 3R 3S 0.28 0.29 0.30 0.31 0.32 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.40 0.28 0.29 0.30 0.31 0.32 0.33 0.34 0.35 0.36 CCy CCx ANSI C78.377A xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 19 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Bin and Order Code Formats Bin codes and order codes are configured as follows. Order Code B in Code SSSCCC-HH-HHHH-GHKLNNNNN Series = MKR Internal code Forward voltage class B = 6 V D = 12 V CRI specification B = 70-CRI minimum H = 80-CRI minimum U = 90-CRI minimum 0 = No minimum Kit code Internal code Color AWT = White SSSCCC-E-DDD-MM-HK-L-PP Series = MKR Internal code Luminous flux group Internal code CRI specification B = 70-CRI minimum H = 80-CRI minimum U = 90-CRI minimum 0 = No minimum Forward voltage class B = 6 V D = 12 V Chromaticity bin Color AWT = White xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 20 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Reflow Soldering Characteristics In testing, Cree has found XLamp MK-R LEDs to be compatible with JEDEC J-STD-020C, using the parameters listed below. As a general guideline, Cree recommends that users follow the recommended soldering profile provided by the manufacturer of solder paste used. Note that this general guideline may not apply to all PCB designs and configurations of reflow soldering equipment. Profile Feature Lead-Based Solder Lead-Free Solder Average Ramp-Up Rate (Tsmax to Tp) 3 °C/second max. 3 °C/second max. Preheat: Temperature Min (Tsmin) 100 °C 150 °C Preheat: Temperature Max (Tsmax) 150 °C 200 °C Preheat: Time (tsmin to tsmax) 60-120 seconds 60-180 seconds Time Maintained Above: Temperature (TL) 183 °C 217 °C Time Maintained Above: Time (tL) 60-150 seconds 60-150 seconds Peak/Classification Temperature (Tp) 215 °C 260 °C Time Within 5 °C of Actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-Down Rate 6 °C/second max. 6 °C/second max. Time 25 °C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to the topside of the package, measured on the package body surface. xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 21 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Notes Lumen Maintenance Projections Cree now uses standardized IES LM-80-08 and TM-21-11 methods for collecting long-term data and extrapolating LED lumen maintenance. For information on the specific LM‑80 data sets available for this LED, refer to the public LM-80 results document at www.cree.com/xlamp_app_notes/LM80_results. Please read the XLamp Long-Term Lumen Maintenance application note at www.cree.com/xlamp_app_notes/lumen_ maintenance for more details on Cree’s lumen maintenance testing and forecasting. Please read the XLamp Thermal Management application note at www.cree.com/xlamp_app_notes/thermal_management for details on how thermal design, ambient temperature, and drive current affect the LED junction temperature. Moisture Sensitivity In testing, Cree has found XLamp MK‑R LEDs to have unlimited floor life in conditions ≤30 ºC/85% relative humidity (RH). Moisture testing included a 168-hour soak at 85 ºC/85% RH followed by 3 reflow cycles, with visual and electrical inspections at each stage. Cree recommends keeping XLamp LEDs in their sealed moisture-barrier packaging until immediately prior to use. Cree also recommends returning any unused LEDs to the resealable moisture-barrier bag and closing the bag immediately after use. RoHS Compliance The levels of RoHS restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2011/65/EC (RoHS2), as implemented January 2, 2013. RoHS Declarations for this product can be obtained from your Cree representative or from the Product Documentation sections of www.cree.com. REAC h Compliance REACh substances of high concern (SVHCs) information is available for this product. Since the European Chemical Agency (ECHA) has published notice of their intent to frequently revise the SVHC listing for the foreseeable future, please contact a Cree representative to insure you get the most up-to-date REACh SVHC Declaration. REACh banned substance information (REACh Article 67) is also available upon request. UL Recognized Component Level 4 enclosure consideration. The LED package or a portion thereof has been investigated as a fire and electrical enclosure per ANSI/UL 8750. Vision Advisory Claim WARNING: Do not look at exposed lamp in operation. Eye injury can result. See the Eye Safety application note at www. cree.com/xlamp_app_notes/led_eye_safety. xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 22 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Mechanical Dimensions All measurements are ±.13 mm unless otherwise indicated. CHECK FINAL PROTECTIVE MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION A B C D 6 5 4 3 6 5 4 3 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 7.000 7.000 .73 4.08 R3.250 6.76 .70 6.70 .70 3.90 6.55 5.27 .55 3.00 1.23 6.70 6.70 .70 .70 3.90 D. CRONIN REV B RECOMMENDED STENCIL PATTERN SHADED AREA IS OPEN RECOMMENDED PCB SOLDER PAD Top View Side View Bottom View Recommended PCB Solder Pad Recommended Stencil Pattern (Shaded Area Is Open) Anode SIZE TITLE SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 6 5 4 3 2 6 5 4 3 2 Phone Fax 4600 Durham, PERSON WITHOUT THE WRITTEN CONSENT COPIED, REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL. THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 7.000 7.000 .73 4.08 R3.250 6.76 .70 .70 6.70 .70 3.90 6.55 5.27 .55 3.00 1.23 6.70 .70 .70 3.90 11.000 2610-00031 MKR Marketing Spec D. CRONIN 11/7/12 REVISONS REV DESCRIPTION BY B VIEWS SHOW LATEST REVISION DC RECOMMENDED STENCIL PATTERN SHADED AREA IS OPEN RECOMMENDED PCB SOLDER PAD SIZE TITLE SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 6 5 4 3 2 1 6 5 4 3 2 1 Phone (Fax (919) 4600 Silicon Durham, PERSON WITHOUT THE WRITTEN CONSENT REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT ARE THE PROPRIETARY AND THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 7.000 7.000 .73 4.08 R3.250 6.76 .70 .70 6.70 .70 3.90 6.55 5.27 .55 3.00 1.23 6.70 .70 .70 3.90 11.000 2610-00031 MKR Marketing Spec D. CRONIN 11/7/12 REVISONS REV DESCRIPTION BY DATE B VIEWS SHOW LATEST REVISION DC 8/RECOMMENDED STENCIL PATTERN SHADED AREA IS OPEN RECOMMENDED PCB SOLDER PAD xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 23 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Tape and Reel All Cree carrier tapes conform to EIA-481D, Automated Component Handling Systems Standard. All dimensions in mm. SIZE TITLE OF REV. SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION X° ± .5 ° .XXX ± .010 .XX ± .03 .X ± .06 FOR SHEET METAL PARTS ONLY .XX ± .01 .XXX ± .005 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SCALE A B C D 6 5 4 3 2 1 6 5 4 3 2 1 A B C D Phone (919) 313-5300 Fax (919) 313-5558 4600 Silicon Drive Durham, N.C 27703 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTANED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE SURFACE FINISH: 63 330 +.25 -.75 12.4 +1.0 -.5 MEASURED AT EDGE 16.4 +0.2 .0 MEASURED AT HUB 12.4 +.2 .0 MEASURED AT HUB 13.1 ±.2 1.9±.4 21±.4 60° 60° 0.500 1 /1 2400-00009 A REEL, 13" X 12MM, 3 PIECE SNAP - ANTI-STATIC HIPS -- -- -- -- D. CRONIN 09/29/09 2400-00009 INDEX QTY ITEM COMMENTS 1 1 2400-00009-CORE 2 2 2400-00009-REEL REVISONS REV DESCRIPTION BY DATE APP'D SIZE TITLE OF REV. SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE A B C D 6 5 4 3 2 1 6 5 4 3 2 1 A B C D Phone (919) 313-5300 Fax (919) 313-5558 4600 Silicon Drive Durham, N.C 27703 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 Trailer 180mm (min) of empty pockets sealed with tape (15 pockets min.) Loaded Pockets (1000 Lamps) 12±.1 4.31 16 +.3 -.0 1.75 4±.10 ±.10 Leader 420mm (min) of empty pockets sealed with tape (35 pockets min.) 7.4 0.36 13" 13mm 3.000 1 /1 2402-00025 A MKR LOADING SPEC -- -- -- -- -- -- D. CRONIN 12/7/12 REVISONS REV DESCRIPTION BY DATE APP'D A Initial Release DC 12/7/12 END START User Feed Direction CATHODE SIDE ANODE SIDE User Feed Direction 1.5± .1 xlamp MK-R leds 2010 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo and XLamp are registered trademarks of Cree, Inc. 24 Copyright © 2012-2014 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo, XLamp® and EasyWhite® are registered trademarks and SC3 Technology™ is a trademark of Cree, Inc. Packaging Label with Cree Bin Code, Qty, Lot # Vacuum-Sealed Moisture Barrier Bag Dessicant (inside bag) Humidity Indicator Card (inside bag) Patent Label Label with Customer Code, Qty, Reel Patent Label Label with Cree Bin Code, Qty, Reel ID Label with Cree Bin Code, Qty, Reel ID Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Bin Code, Qty, Reel ID Unpackaged Reel Packaged Reel Boxed Reel Precision Instrumentation Amplifier AD524 Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. FEATURES Low noise: 0.3 μV p-p at 0.1 Hz to 10 Hz Low nonlinearity: 0.003% (G = 1) High CMRR: 120 dB (G = 1000) Low offset voltage: 50 μV Low offset voltage drift: 0.5 μV/°C Gain bandwidth product: 25 MHz Pin programmable gains of 1, 10, 100, 1000 Input protection, power-on/power-off No external components required Internally compensated MIL-STD-883B and chips available 16-lead ceramic DIP and SOIC packages and 20-terminal leadless chip carrier available Available in tape and reel in accordance with EIA-481A standard Standard military drawing also available FUNCTIONAL BLOCK DIAGRAM AD524 20kΩ – INPUT G = 10 + INPUT G = 100 G = 1000 4.44kΩ 404Ω 40Ω PROTECTION 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ SENSE REFERENCE PROTECTION RG1 RG2 1 13 12 11 16 3 2 Vb OUTPUT 00500-001 Figure 1. GENERAL DESCRIPTION The AD524 is a precision monolithic instrumentation amplifier designed for data acquisition applications requiring high accu- racy under worst-case operating conditions. An outstanding combination of high linearity, high common-mode rejection, low offset voltage drift, and low noise makes the AD524 suitable for use in many data acquisition systems. The AD524 has an output offset voltage drift of less than 25 μV/°C, input offset voltage drift of less than 0.5 μV/°C, CMR above 90 dB at unity gain (120 dB at G = 1000), and maximum nonlinearity of 0.003% at G = 1. In addition to the outstanding dc specifications, the AD524 also has a 25 kHz bandwidth (G = 1000). To make it suitable for high speed data acquisition systems, the AD524 has an output slew rate of 5 V/μs and settles in 15 μs to 0.01% for gains of 1 to 100. As a complete amplifier, the AD524 does not require any exter- nal components for fixed gains of 1, 10, 100 and 1000. For other gain settings between 1 and 1000, only a single resistor is required. The AD524 input is fully protected for both power-on and power-off fault conditions. The AD524 IC instrumentation amplifier is available in four different versions of accuracy and operating temperature range. The economical A grade, the low drift B grade, and lower drift, higher linearity C grade are specified from −25°C to +85°C. The S grade guarantees performance to specification over the extended temperature range −55°C to +125°C. The AD524 is available in a 16-lead ceramic DIP, 16-lead SBDIP, 16-lead SOIC wide packages, and 20-terminal leadless chip carrier. PRODUCT HIGHLIGHTS 1. The AD524 has guaranteed low offset voltage, offset voltage drift, and low noise for precision high gain applications. 2. The AD524 is functionally complete with pin program- mable gains of 1, 10, 100, and 1000, and single resistor programmable for any gain. 3. Input and output offset nulling terminals are provided for very high precision applications and to minimize offset voltage changes in gain ranging applications. 4. The AD524 is input protected for both power-on and power-off fault conditions. 5. The AD524 offers superior dynamic performance with a gain bandwidth product of 25 MHz, full power response of 75 kHz and a settling time of 15 μs to 0.01% of a 20 V step (G = 100). MPXV7002 Rev 2, 1/2009 Freescale Semiconductor © Freescale Semiconductor, Inc., 2005, 2009. All rights reserved. Pressure + Integrated Silicon Pressure Sensor On-Chip Signal Conditioned, Temperature Compensated and Calibrated The MPXV7002 series piezoresistive transducers are state-of-the-art monolithic silicon pressure sensors designed for a wide range of applications, but particularly those employing a microcontroller or microprocessor with A/D inputs. This transducer combines advanced micromachining techniques, thinfilm metallization, and bipolar processing to provide an accurate, high level analog output signal that is proportional to the applied pressure. Features • 2.5% Typical Error over +10°C to +60°C with Auto Zero • 6.25% Maximum Error over +10°C to +60°C without Auto Zero • Ideally Suited for Microprocessor or Microcontroller-Based Systems • Thermoplastic (PPS) Surface Mount Package • Temperature Compensated over +10° to +60°C • Patented Silicon Shear Stress Strain Gauge • Available in Differential and Gauge Configurations ORDERING INFORMATION Device Name Package Options Case No. # of Ports Pressure Type Device None Single Dual Gauge Differential Absolute Marking Small Outline Package (MPXV7002 Series) MPXV7002GC6U Rails 482A • • MPXV7002G MPXV7002GC6T1 Tape & Reel 482A • • MPXV7002G MPXV7002GP Trays 1369 • • MPXV7002G MPXV7002DP Trays 1351 • • MPXV7002DP MPXV7002 Series -2 to 2 kPa (-0.3 to 0.3 psi) 0.5 to 4.5 V Output SMALL OUTLINE PACKAGE MPXV7002GC6U/C6T1 CASE 482A-01 MPXV7002DP CASE 1351-01 MPXV7002GP CASE 1369-01 Application Examples • Hospital Beds • HVAC • Respiratory Systems • Process Control MPXV7002 Sensors 2 Freescale Semiconductor Pressure Operating Characteristics Table 1. Operating Characteristics (VS = 5.0 Vdc, TA = 25°C unless otherwise noted. Decoupling circuit shown in Figure 3 required to meet specification.) Characteristic Symbol Min Typ Max Unit Pressure Range(1) 1. 1.0 kPa (kiloPascal) equals 0.145 psi. POP –2.0 — 2.0 kPa Supply Voltage(2) 2. Device is ratiometric within this specified excitation range. VS 4.75 5.0 5.25 Vdc Supply Current Io — — 10 mAdc Pressure Offset(3) (10 to 60°C) @ VS = 5.0 Volts 3. Offset (Voff) is defined as the output voltage at the minimum rated pressure. Voff 2.25 2.5 2.75 Vdc Full Scale Output(4) (10 to 60°C) @ VS = 5.0 Volts 4. Full Scale Output (VFSO) is defined as the output voltage at the maximum or full rated pressure. VFSO 4.25 4.5 4.75 Vdc Full Scale Span(5) (10 to 60°C) @ VS = 5.0 Volts 5. Full Scale Span (VFSS) is defined as the algebraic difference between the output voltage at full rated pressure and the output voltage at the minimum rated pressure. VFSS 3.5 4.0 4.5 V Vdc Accuracy(6) (10 to 60°C) 6. Accuracy (error budget) consists of the following: Linearity: Output deviation from a straight line relationship with pressure over the specified pressure range. Temperature Hysteresis: Output deviation at any temperature within the operating temperature range, after the temperature is cycled to and from the minimum or maximum operating temperature points, with zero differential pressure applied. Pressure Hysteresis: Output deviation at any pressure within the specified range, when this pressure is cycled to and from the minimum or maximum rated pressure, at 25°C. TcSpan: Output deviation over the temperature range of 10° to 60°C, relative to 25°C. TcOffset: Output deviation with minimum rated pressure applied, over the temperature range of 10° to 60°C, relative to 25°C. Variation from Nominal: The variation from nominal values, for Offset or Full Scale Span, as a percent of VFSS, at 25°C. — — ±2.5(7) 7. Auto Zero at Factory Installation: Due to the sensitivity of the MPXV7002 Series, external mechanical stresses and mounting position can affect the zero pressure output reading. Auto zero is defined as storing the zero pressure output reading and subtracting this from the device's output during normal operations. Reference AN1636 for specific information. The specified accuracy assumes a maximum temperature change of ± 5°C between auto zero and measurement. ±6.25 %VFSS Sensitivity V/P — 1.0 —- V/kPa Response Time(8) 8. Response Time is defined as the time for the incremental change in the output to go from 10% to 90% of its final value when subjected to a specified step change in pressure. tR — 1.0 —- ms Output Source Current at Full Scale Output IO+ — 0.1 —- mAdc Warm-Up Time(9) 9. Warm-up Time is defined as the time required for the product to meet the specified output voltage after the Pressure has been stabilized. — — 20 —- ms MPXV7002 Sensors Freescale Semiconductor 3 Pressure Maximum Ratings Figure 1 shows a block diagram of the internal circuitry integrated on a pressure sensor chip. Figure 1. Integrated Pressure Sensor Schematic Table 2. Maximum Ratings(1) 1. Exposure beyond the specified limits may cause permanent damage or degradation to the device. Rating Symbol Value Unit Maximum Pressure (P1 > P2) Pmax 75 kPa Storage Temperature Tstg –30 to +100 °C Operating Temperature TA 10 to 60 °C Sensing Element Thin Film Temperature Compensation and Gain Stage #1 Gain Stage #2 and Ground Reference Shift Circuitry VS Vout GND Pins 1, 5, 6, 7, and 8 are NO CONNECTS for Small Outline Package Device 2 4 3 MPXV7002 Sensors 4 Freescale Semiconductor Pressure ON-CHIP TEMPERATURE COMPENSATION, CALIBRATION AND SIGNAL CONDITIONING The performance over temperature is achieved by integrating the shear-stress strain gauge, temperature compensation, calibration and signal conditioning circuitry onto a single monolithic chip. Figure 2 illustrates the Differential or Gauge configuration in the basic chip carrier (Case 482). A gel die coat isolates the die surface and wire bonds from the environment, while allowing the pressure signal to be transmitted to the sensor diaphragm. The MPXV7002 series pressure sensor operating characteristics, and internal reliability and qualification tests are based on use of dry air as the pressure media. Media, other than dry air, may have adverse effects on sensor performance and long-term reliability. Contact the factory for information regarding media compatibility in your application. Figure 3 shows the recommended decoupling circuit for interfacing the integrated sensor to the A/D input of a microprocessor or microcontroller. Proper decoupling of the power supply is recommended. Figure 4 shows the sensor output signal relative to pressure input. Typical, minimum, and maximum output curves are shown for operation over a temperature range of 10° to 60°C using the decoupling circuit shown in Figure 3. The output will saturate outside of the specified pressure range. Figure 2. Cross-Sectional Diagram SOP (not to scale) Figure 3. Recommended Power Supply Decoupling and Output Filtering (For additional output filtering, please refer to Application Note AN1646.) Fluoro Silicone Gel Die Coat Wire Bond Die P1 Stainless Steel Cap Thermoplastic Case Differential Sensing Die Bond Element P2 Lead Frame +5 V 1.0 μF 0.01 μF GND 470 pF Vs Vout IPS OUTPUT MPXV7002 Sensors Freescale Semiconductor 5 Pressure Figure 4. Output versus Pressure Differential PRESSURE (P1)/VACUUM (P2) SIDE IDENTIFICATION TABLE Freescale designates the two sides of the pressure sensor as the Pressure (P1) side and the Vacuum (P2) side. The Pressure (P1) side is the side containing a gel die coat which protects the die from harsh media. The Pressure (P1) side may be identified by using the following table: MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the surface mount packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct footprint, the packages will self align when subjected to a solder reflow process. It is always recommended to design boards with a solder mask layer to avoid bridging and shorting between solder pads. Figure 5. Small Outline Package Footprint Differential Pressure (kPa) Output Voltage (V) 5.0 4.0 3.0 2.0 1.0 0 0 2 TYPICAL MIN -2 -1 1 Transfer Function: Vout = VS × (0.2 × P(kPa)+0.5) ± 6.25% VFSS VS = 5.0 Vdc TA = 10 to 60°C MAX Part Number Case Type Pressure (P1) Side Identifier MPXV7002GC6U/GC6T1 482A-01 Side with Port Attached MPXV7002GP 1369-01 Side with Port Attached MPXV7002DP 1351-01 Side with Part Marking 0.660 16.76 0.060 TYP 8X 1.52 0.100 TYP 8X 2.54 0.100 TYP 8X 2.54 0.300 7.62 inch mm SCALE 2:1 MPXV7002 Sensors 6 Freescale Semiconductor Pressure PACKAGE DIMENSIONS CASE 482A-01 ISSUE A SMALL OUTLINE PACKAGE PIN 1 IDENTIFIER H SEATING PLANE -TW C M J K V DIM MIN MAX MIN MAX INCHES MILLIMETERS A 0.415 0.425 10.54 10.79 B 0.415 0.425 10.54 10.79 C 0.500 0.520 12.70 13.21 D 0.038 0.042 0.96 1.07 G 0.100 BSC 2.54 BSC H 0.002 0.010 0.05 0.25 J 0.009 0.011 0.23 0.28 K 0.061 0.071 1.55 1.80 M 0° 7° 0° 7° N 0.444 0.448 11.28 11.38 S 0.709 0.725 18.01 18.41 V 0.245 0.255 6.22 6.48 W 0.115 0.125 2.92 3.17 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006). 5. ALL VERTICAL SURFACES 5° TYPICAL DRAFT. S D 8 PL G 4 5 8 1 0.25 (0.010) M T B S A -A- N -BS MPXV7002 Sensors Freescale Semiconductor 7 Pressure PACKAGE DIMENSIONS CASE 1351-01 ISSUE A SMALL OUTLINE PACKAGE MPXV7002 Sensors 8 Freescale Semiconductor Pressure PACKAGE DIMENSIONS MPXV7002 Sensors Freescale Semiconductor 9 Pressure PACKAGE DIMENSIONS CASE 1369-01 ISSUE B SMALL OUTLINE PACKAGE MPXV7002 Sensors 10 Freescale Semiconductor Pressure PACKAGE DIMENSIONS CASE 1369-01 ISSUE B SMALL OUTLINE PACKAGE MPXV7002 Rev. 2 1/2009 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. Product family data sheet Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 CLD-DS51 Rev 8A Cree® XLamp® XP-G2 LEDs Product Description The XLamp XP-G2 LED builds on the unprecedented performance of the original XP-G by increasing lumen output up to 20% while providing a single die LED point source for precise optical control. The XP-G2 LED shares the same footprint as the original XP-G, providing a seamless upgrade path and shortening the design cycle. XLamp XP-G2 LEDs are the ideal choice for lighting applications where high light output and maximum efficacy are required, such as LED light bulbs, outdoor lighting, portable lighting, indoor lighting and solar-powered lighting. FEATURES • Available in white, outdoor white and 80-, 85- and 90-CRI white • ANSI-compatible chromaticity bins • Binned at 85 °C • Maximum drive current: 1500 mA • Low thermal resistance: 4 °C/W • Wide viewing angle: 115° • Unlimited floor life at ≤ 30 ºC/85% RH • Reflow solderable - JEDEC J‑STD‑020C • Electrically neutral thermal path • RoHS- and REACh‑ compliant • UL-recognized component (E349212) www.cree.com/Xlamp Table of Contents Characteristics........................... 2 Flux Characteristics..................... 3 Relative Spectral Power Distribution............................... 4 Relative Flux vs. Junction Temperature.............................. 4 Electrical Characteristics.............. 5 Relative Flux vs. Current............. 5 Relative Chromaticity vs Current and Temperature........................ 6 Typical Spatial Distribution........... 7 Thermal Design.......................... 7 Reflow Soldering Characteristics... 8 Notes........................................ 9 Mechanical Dimensions..............10 Tape and Reel...........................11 Packaging.................................12 Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 2 XLamp xp-g2 leds Characteristics Characteristics Unit Minimum Typical Maximum Thermal resistance, junction to solder point °C/W 4 Viewing angle (FWHM) degrees 115 Temperature coefficient of voltage mV/°C -1.8 ESD withstand voltage (HBM per Mil-Std-883D) V 8000 DC forward current mA 1500 Reverse voltage V 5 Forward voltage (@ 350 mA, 85 °C) V 2.8 3.15 Forward voltage (@ 700 mA, 85 °C) V 2.9 Forward voltage (@ 1000 mA, 85 °C) V 3.0 Forward voltage (@ 1500 mA, 85 °C) V 3.1 LED junction temperature °C 150 Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 3 XLamp xp-g2 leds Flux Characteristics (TJ = 85 °C) The following table provides several base order codes for XLamp XP-G2 LEDs. It is important to note that the base order codes listed here are a subset of the total available order codes for the product family. Color CCT Range Base Order Codes Min. Luminous Flux @ 350 mA Calculated Minimum Luminous Flux (lm)** @ 85 °C Order Code Min. Max. Group Flux (lm) @ 85 °C Flux (lm) @ 25 °C* 700 mA 1.0 A 1.5 A Cool White 5000 K 8300 K R3 122 138 223 297 402 XPGBWT-L1-0000-00F51 R4 130 147 237 316 429 XPGBWT-L1-0000-00G51 R5 139 158 254 338 458 XPGBWT-L1-0000-00H51 Outdoor White 3200 K 5300 K R2 114 129 208 277 376 XPGBWT-01-0000-00EC2 R3 122 138 223 297 402 XPGBWT-01-0000-00FC2 R4 130 147 237 316 429 XPGBWT-01-0000-00GC2 Neutral White 3700 K 5300 K Q5 107 121 195 260 353 XPGBWT-L1-0000-00DE4 R2 114 129 208 277 376 XPGBWT-L1-0000-00EE4 R3 122 138 223 297 402 XPGBWT-L1-0000-00FE4 80-CRI White 2600 K 4300 K Q4 100 113 182 243 330 XPGBWT-H1-0000-00CE7 Q5 107 121 195 260 353 XPGBWT-H1-0000-00DE7 R2 114 129 208 277 376 XPGBWT-H1-0000-00EE7 R3 122 138 223 297 402 XPGBWT-H1-0000-00FE7 Warm White 2600 K 3700 K Q4 100 113 182 243 330 XPGBWT-L1-0000-00CE7 Q5 107 121 195 260 353 XPGBWT-L1-0000-00DE7 R2 114 129 208 277 376 XPGBWT-L1-0000-00EE7 R3 122 138 223 297 402 XPGBWT-L1-0000-00FE7 R4 130 147 237 316 429 XPGBWT-L1-0000-00GE7 85-CRI White 2600 K 3200 K P3 73.9 83.8 135 180 244 XPGBWT-P1-0000-008E7 P4 80.6 91.4 147 196 266 XPGBWT-P1-0000-009E7 Q2 87.4 99.1 160 213 288 XPGBWT-P1-0000-00AE7 Q3 93.9 106 172 228 310 XPGBWT-P1-0000-00BE7 90-CRI White 2600 K 3200 K P3 73.9 83.8 135 180 244 XPGBWT-U1-0000-008E7 P4 80.6 91.4 147 196 266 XPGBWT-U1-0000-009E7 Q2 87.4 99.1 160 213 288 XPGBWT-U1-0000-00AE7 Notes: • Cree maintains a tolerance of ±7% on flux and power measurements, ±0.005 on chromaticity (CCx, CCy) measurements and ±2 on CRI measurements. • Typical CRI for Cool White (5000 K - 8300 K CCT) is 70. • Typical CRI for Neutral White (3700 K - 5300 K CCT) is 75. • Typical CRI for Outdoor White (4000 K - 5300 K CCT) is 70. • Typical CRI for Warm White (2600 K - 3700 K CCT) is 80. • Minimum CRI for 80-CRI White is 80. • Minimum CRI for 85-CRI White is 85. • Minimum CRI for 90-CRI White is 90. • Flux values @ 25 °C are calculated and for reference only. ** Calculated flux values at 700 mA, 1 A and 1.5 A are for reference only. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 4 XLamp xp-g2 leds Relative Spectral Power Distribution Relative Flux vs. Junction Temperature (IF = 350 mA) Relative Spectral Power 0% 20% 40% 60% 80% 100% 380 430 480 530 580 630 680 730 780 Relative Radiant Power (%) Wavelength (nm) 5000K - 8300K CCT 3700K - 5000K CCT 2600K - 3700K CCT Relative Flux Output vs. Junction Temperature 0% 20% 40% 60% 80% 100% 120% 25 50 75 100 125 150 Relative Luminous Flux Junction Temperature (ºC) Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 5 XLamp xp-g2 leds Electrical Characteristics (TJ = 85 °C) Relative Flux vs. Current (TJ = 85 °C) Electrical Characteristics (Tj = 25ºC) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 2.50 2.75 3.00 3.25 Forward Current (mA) Forward Voltage (V) Relative Intensity vs. Current (Tj = 25ºC) 0% 50% 100% 150% 200% 250% 300% 350% 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 Relative Luminous Flux (%) Forward Current (mA) Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 6 XLamp xp-g2 leds Relative Chromaticity vs Current and Temperature (Warm White*) * Warm White XLamp XP-G2 LEDs have a typical CRI of 80. Delta CCT vs. Current -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 100 300 500 700 900 1100 1300 1500 Current (mA) ΔCCx ΔCCy Delta CCT vs Temp -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 25 50 75 100 125 150 Tsp (°C) ΔCCx ΔCCy Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 7 XLamp xp-g2 leds Typical Spatial Distribution Thermal Design The maximum forward current is determined by the thermal resistance between the LED junction and ambient. It is crucial for the end product to be designed in a manner that minimizes the thermal resistance from the solder point to ambient in order to optimize lamp life and optical characteristics. Typical Spatial Radiation Pattern 0% 20% 40% 60% 80% 100% -100 -80 -60 -40 -20 0 20 40 60 80 100 Relative Luminous Intensity (%) Angle (º) Thermal Design Cool White 0 200 400 600 800 1000 1200 1400 1600 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 8 XLamp xp-g2 leds Reflow Soldering Characteristics In testing, Cree has found XLamp XP-G2 LEDs to be compatible with JEDEC J-STD-020C, using the parameters listed below. As a general guideline, Cree recommends that users follow the recommended soldering profile provided by the manufacturer of solder paste used. Note that this general guideline may not apply to all PCB designs and configurations of reflow soldering equipment. Profile Feature Lead-Based Solder Lead-Free Solder Average Ramp-Up Rate (Tsmax to Tp) 3 °C/second max. 3 °C/second max. Preheat: Temperature Min (Tsmin) 100 °C 150 °C Preheat: Temperature Max (Tsmax) 150 °C 200 °C Preheat: Time (tsmin to tsmax) 60-120 seconds 60-180 seconds Time Maintained Above: Temperature (TL) 183 °C 217 °C Time Maintained Above: Time (tL) 60-150 seconds 60-150 seconds Peak/Classification Temperature (Tp) 215 °C 260 °C Time Within 5 °C of Actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-Down Rate 6 °C/second max. 6 °C/second max. Time 25 °C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package, measured on the package body surface. TP TL Temperature Time t 25˚C to Peak Preheat ts tS tP 25 Ramp-down Ramp-up Critical Zone TL to TP Tsmax Tsmin Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 9 XLamp xp-g2 leds Notes Lumen Maintenance Projections Cree now uses standardized IES LM-80-08 and TM-21-11 methods for collecting long-term data and extrapolating LED lumen maintenance. For information on the specific LM-80 data sets available for this LED, refer to the public LM-80 results document at www.cree.com/xlamp_app_notes/LM80_results. Please read the XLamp Long-Term Lumen Maintenance application note at www.cree.com/xlamp_app_notes/lumen_ maintenance for more details on Cree’s lumen maintenance testing and forecasting. Please read the XLamp Thermal Management application note at www.cree.com/xlamp_app_notes/thermal_management for details on how thermal design, ambient temperature, and drive current affect the LED junction temperature. Moisture Sensitivity In testing, Cree has found XLamp XP-G2 LEDs to have unlimited floor life in conditions ≤ 30 ºC/85% relative humidity (RH). Moisture testing included a 168-hour soak at 85 ºC/85% RH followed by 3 reflow cycles, with visual and electrical inspections at each stage. Cree recommends keeping XLamp LEDs in their sealed moisture-barrier packaging until immediately prior to use. Cree also recommends returning any unused LEDs to the resealable moisture-barrier bag and closing the bag immediately after use. RoHS Compliance The levels of RoHS restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2011/65/EC (RoHS2), as implemented January 2, 2013. RoHS Declarations for this product can be obtained from your Cree representative or from the Product Documentation sections of www.cree.com. REAC h Compliance REACh substances of high concern (SVHCs) information is available for this product. Since the European Chemical Agency (ECHA) has published notice of their intent to frequently revise the SVHC listing for the foreseeable future, please contact a Cree representative to insure you get the most up-to-date REACh Declaration. REACh banned substance information (REACh Article 67) is also available upon request. UL Recognized Component Level 4 enclosure consideration. The LED package or a portion thereof has been investigated as a fire and electrical enclosure per ANSI/UL 8750. Vision Advisory Claim WARNING: Do not look at exposed lamp in operation. Eye injury can result. See LED Eye Safety at www.cree.com/ xlamp_app_notes/led_eye_safety. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 10 XLamp xp-g2 leds Mechanical Dimensions (TA = 25 °C) All measurements are ±.13 mm unless otherwise indicated. .60 1.65 1.60 .65 3.45 2.00 3.45 .40 .60 3.20 1.20 .40 .40 3.20 (HATCHED AREA IS OPENING) RECOMMENDED STENCIL PATTERN RECOMMENDED PCB SOLDER PAD 3.30 3.30 .50 1.30 .50 .50 .40 2.30 3.30 .50 1.30 .50 .73 2.6 Top View Side View Bottom View All Measurements are .13mm unless otherwise indicated Anode THIRD ANGLE PROJECTION A B C D 6 5 4 3 6 5 4 3 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE X° ± .5 .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS .XX ± .25 .XXX ± .125 X° ± .5 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE MILLIMETERS AND AFTER TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 .83 .65 R1.53 3.30 2.30 .50 1.30 2.36 RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE OF REV. SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 3 2 1 A B C Phone (919) 313-5300 Fax (919) 313-5558 4600 Silicon Drive Durham, N.C 27703 X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 1.20 .60 3.20 1.60 3.20 .40 .65 3.30 1.30 22.000 1 /1 2610-00024 A OUTLINE DRAWING XPG G2 D. CRONIN 05/09/12 RECOMMENDED STENCIL PATTERN AREA IS OPENING) SIZE TITLE DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 6 5 4 3 2 6 5 4 3 2 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL. THIS PLOT AND THE INFORMATION INC. NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 .83 .65 R1.53 3.30 3.30 2.30 .50 1.30 2.36 D. CRONIN 05/09/12 REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 6 5 4 3 2 6 5 4 3 2 PERSON WITHOUT THE WRITTEN CONSENT COPIED, REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT ARE THE PROPRIETARY AND CONFIDENTIAL. THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 .83 .65 R1.53 3.30 3.30 2.30 .50 1.30 2.36 22.000 OUTLINE D. CRONIN 05/09/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 5 4 3 2 5 4 3 2 WITHOUT THE WRITTEN CONSENT REPRODUCED OR DISCLOSED TO ANY CREE, INC. THIS PLOT PROPRIETARY AND AND THE INFORMATION X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 1.30 3.30 3.30 1.15 1.65 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 .83 .65 R1.53 3.30 3.30 2.30 .50 1.30 2.36 22.000 2610-OUTLINE DRAWING D. CRONIN 05/09/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) Anode Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 11 XLamp xp-g2 leds Tape and Reel All Cree carrier tapes conform to EIA-481D, Automated Component Handling Systems Standard. All dimensions in mm. SIZE TITLE OF REV. SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE A B C D 6 5 4 3 2 1 6 5 4 3 2 1 A B C D Phone (919) 313-5300 Fax (919) 313-5558 4600 Silicon Drive Durham, N.C 27703 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 Trailer 160mm (min) of empty pockets sealed with tape (20 pockets min.) Loaded Pockets (1000 Lamps) Leader 400mm (min.) of empty pockets with at least 100mm sealed by tape (50 empty pockets min.) 12.0 +.3 -.0 1.75 ±.10 4±.1 8±.1 2.5±.1 3.000 1 /1 2402-00014 B XP HEW LOADING SPEC -- -- -- -- -- -- D. CRONIN 11/29/10 REVISONS REV DESCRIPTION BY DATE APP'D B ADDED CATHODE AND ANODE NOTE REORIENTED DEVICE DC 2/26/12 END START User Feed Direction CATHODE SIDE ANODE SIDE User Feed Direction 7" 1.5± .1 13mm Pocket Tape Carrier Tape 13 61 12.40 0 +2.00 MEASURED AT HUB 12.40 MEASURED AT INSIDE EDGE 16.40 2400-00005 SIZE TITLE REV. C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION .X ± 0.3 .XX ± .10 .X ± .25 FOR SHEET METAL PARTS ONLY .XX ± .13 X° ± 1° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS & BEFORE FINISH. TOLERANCE UNLESS SPECIFIED: A B C D 6 5 4 3 2 1 A B C D Phone (919) 361-4770 4600 Silicon Drive Durham, N.C 27703 NOTICE CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT OF CREE, INC. Reel, 7" x 12mm Wide B LIUDEZHI 2012/5/25 +/-0.5 PS 190 ½öÓÃÓÚÆÀ¹À¡£ °æȨËùÓÐ (c) by Foxit Software Company, 2004 ÓÉ Foxit PDF Editor ±à¼- OD 7.5'' 13 61 12.40 0 +2.00 MEASURED AT HUB 12.40 MEASURED AT INSIDE EDGE 16.40 B C D 6 5 4 3 2 1 B C D NOTICE CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT OF CREE, INC. +/-0.5 190 ½öÓÃÓÚÆÀ¹À¡£ °æȨËùÓÐ (c) by Foxit Software Company, 2004 ÓÉ Foxit PDF Editor ±à¼- OD 7.5'' Y X X REF 0.59 F(III) D1 P1 1.5 MIN. Bo Ao R0.2 TYPICAL REF 4.375 Ko (IV) Other material available. (III) (II) (I) hole to centerline of pocket. Measured from centerline of sprocket holes is ± 0.20. Cumulative tolerance of 10 sprocket to centerline of pocket. Measured from centerline of sprocket hole SECTION Y-Y SECTION X-X REF R 2.24 Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 Y Y X X REF 0.59 W F(III) D1 P1 1.5 MIN. Bo Ao R0.2 TYPICAL REF 4.375 Ko (IV) Other material available. (III) (II) (I) hole to centerline of pocket. Measured from centerline of sprocket holes is ± 0.20. Cumulative tolerance of 10 sprocket to centerline of pocket. Measured from centerline of sprocket hole SECTION Y-Y SECTION X-X 2.0 ±0.05 (I) P2 1.55 ±0.05 Do 4.0 ±0.1 (II) Po 1.75 ±0.1 E1 T 0.30 ±0.05 REF R 2.24 Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 Y D1 1.5 MIN. Bo R0.2 TYPICAL REF 4.375 Ko SECTION Y-Y REF Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 CATHODE SIDE ANODE SIDE Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 12 XLamp xp-g2 leds Packaging Patent Label (on bottom of box) Label with Cree Bin Code, Qty, Reel ID Label with Cree Bin Code, Qty, Reel ID Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Bin Code, Qty, Reel ID Unpackaged Reel Packaged Reel Boxed Reel CREE Bin Code & Barcode Label Vacuum-Sealed Moisture Barrier Bag Label with Customer P/N, Qty, Lot #, PO # Label with Cree Bin Code, Qty, Lot # Label with Cree Bin Code, Qty, Lot # Vacuum-Sealed Moisture Barrier Bag Patent Label Label with Customer Order Code, Qty, Reel ID, PO # SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. SHARC Processors ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com SUMMARY High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—3M bits of on-chip SRAM Code compatible with all other members of the SHARC family The ADSP-2136x processors are available with up to 333 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, DTCP (digital transmission content protection protocol), serial ports, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 56. DEDICATED AUDIO COMPONENTS S/PDIF-compatible digital audio receiver/transmitter 8 channels of asynchronous sample rate converters (SRC) 16 PWM outputs configured as four groups of four outputs ROM-based security features include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/ divider ratios Available in 136-ball CSP_BGA and 144-lead LQFP_EP packages Figure 1. Functional Block Diagram Internal Memory I/F Block 0 RAM/ROM B0D 64-BIT Instruction Cache 5 stage Sequencer PEx PEy PMD 64-BIT Core Bus Cross Bar Block 1 RAM/ROM Block 2 RAM Block 3 RAM DAG1/2 Timer IOD BUS MTM/ DTCP PERIPHERAL BUS 32-BIT Internal Memory DMD 64-BIT PERIPHERAL BUS B1D 64-BIT B2D 64-BIT B3D 64-BIT DAI Peripherals Peripherals SIMD Core S Core SPI Flags PWM 3-0 PP PP Pin MUX PDAP/ IDP7-0 ASRC 3-0 TIMER 2-0 CORE FLAGS S/PDIF Tx/Rx PCG A-B SPI B SPORT 5-0 DAI Routing/Pins IOD 32-BIT FLAGx/IRQx/ TMREXP JTAG PMD 64-BIT DMD 64-BIT Rev. J | Page 2 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 TABLE OF CONTENTS Summary ............................................................... 1 Dedicated Audio Components .................................... 1 General Description ................................................. 3 SHARC Family Core Architecture ............................ 4 Family Peripheral Architecture ................................ 6 I/O Processor Features ........................................... 8 System Design ...................................................... 8 Development Tools ............................................... 9 Additional Information ........................................ 10 Related Signal Chains .......................................... 10 Pin Function Descriptions ....................................... 11 Specifications ........................................................ 14 Operating Conditions .......................................... 14 Electrical Characteristics ....................................... 15 Package Information ........................................... 16 ESD Caution ...................................................... 16 Maximum Power Dissipation ................................. 16 Absolute Maximum Ratings ................................... 16 Timing Specifications ........................................... 16 Output Drive Currents ......................................... 46 Test Conditions .................................................. 46 Capacitive Loading .............................................. 46 Thermal Characteristics ........................................ 47 144-Lead LQFP_EP Pin Configurations ....................... 48 136-Ball BGA Pin Configurations ............................... 50 Package Dimensions ............................................... 53 Surface-Mount Design .......................................... 54 Automotive Products .............................................. 55 Ordering Guide ..................................................... 56 REVISION HISTORY 7/13—Revision I to Revision J Updated Development Tools .......................................9 Added Nominal Value column in Operating Conditions .. 14 Changed Max values in Table 30 in Pulse-Width Modulation Generators ............................................................ 35 Updated Ordering Guide .......................................... 56 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 3 of 60 | July 2013 GENERAL DESCRIPTION The ADSP-2136x SHARC® processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices, Inc., Super Harvard Architecture. The processor is source code-compatible with the ADSP-2126x and ADSP-2116x DSPs, as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode. The ADSP-2136x are 32-/40-bit floating-point processors optimized for high performance automotive audio applications. They contain a large on-chip SRAM and ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital audio interface (DAI). As shown in the functional block diagram on Page 1, the ADSP-2136x uses two computational units to deliver a significant performance increase over the previous SHARC processors on a range of signal processing algorithms. With its SIMD computational hardware, the ADSP-2136x can perform two GFLOPS running at 333 MHz. Table 1 shows performance benchmarks for these devices. Table 2 shows the features of the individual product offerings. The diagram on Page 1 shows the two clock domains that make up the ADSP-2136x processors. The core clock domain contains the following features: • Two processing elements, each of which comprises an ALU, multiplier, shifter, and data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle • One periodic interval timer with pinout • On-chip SRAM (3M bit) • On-chip mask-programmable ROM (4M bit) • JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints, which allow flexible exception handling. The diagram on Page 1 also shows the following architectural features: • I/O processor that handles 32-bit DMA for the peripherals • Six full duplex serial ports • Two SPI-compatible interface ports—primary on dedicated pins, secondary on DAI pins • 8-bit or 16-bit parallel port that supports interfaces to offchip memory peripherals • Digital audio interface that includes two precision clock generators (PCG), an input data port with eight serial interfaces (IDP), an S/PDIF receiver/transmitter, 8-channel asynchronous sample rate converter (ASRC), DTCP cipher, six serial ports, a 20-bit parallel input data port (PDAP), 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) Table 1. Benchmarks (at 333 MHz) Benchmark Algorithm Speed (at 333 MHz) 1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs FIR Filter (per tap)1 1Assumes two files in multichannel SIMD mode. 1.5 ns IIR Filter (per biquad)1 6.0 ns Matrix Multiply (pipelined) [3×3] × [3×1] [4×4] × [4×1] 13.5 ns 23.9 ns Divide (y/x) 10.5 ns Inverse Square Root 16.3 ns Table 2. ADSP-2136x Family Features Feature ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366 RAM ROM 3M bit 4M bit 3M bit 4M bit 3M bit 4M bit 3M bit 4M bit 3M bit 4M bit Audio Decoders in ROM1 No No No Yes Yes Pulse-Width Modulation Yes Yes Yes Yes Yes S/PDIF Yes No Yes Yes Yes DTCP2 Yes No No Yes No SRC SNR Performance –128 dB No SRC –140 dB –128 dB –128 dB 1 Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Pro Logic IIx, DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. Rev. J | Page 4 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARC FAMILY CORE ARCHITECTURE The ADSP-2136x is code-compatible at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2136x shares architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. SIMD Computational Engine The processor contains two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY can be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive signal processing algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. Independent, Parallel Computation Units Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit, single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats. Figure 2. SHARC Core Block Diagram S SIMD Core INTERRUPT CACHE 5 STAGE PROGRAM SEQUENCER PM ADDRESS 32 DM ADDRESS 32 DM DATA 64 PM DATA 64 DAG1 16x32 MRF 80-BIT MULTIPLIER SHIFTER ALU RF Rx/Fx PEx 16x40-BIT JTAG DMD/PMD 64 PM DATA 48 ASTATx STYKx ASTATy STYKy TIMER RF Sx/SFx PEy 16x40-BIT MRB 80-BIT MSB 80-BIT MSF 80-BIT FLAG SYSTEM I/F USTAT 4x32-BIT PX 64-BIT DAG2 16x32 ALU SHIFTER MULTIPLIER DATA SWAP PM ADDRESS 24 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 5 of 60 | July 2013 Data Register File Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) files, combined with the ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Context Switch Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result register all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. Universal Registers The universal registers are general purpose registers. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all system registers (control/status) of the core. The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference. Timer A core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal. Single-Cycle Fetch of Instruction and Four Operands The processor features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2). With the its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. Instruction Cache The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the processor can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. On-Chip Memory The processor contains 3M bits of internal SRAM and 4M bits of internal ROM. Each block can be configured for different combinations of code and data storage (see Table 3). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The processor’s memory architecture, in combination with its separate on-chip buses, allows two data transfers from the core and one from the I/O processor, in a single cycle. The SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 3M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. On-Chip Memory Bandwidth The internal memory architecture allows three accesses at the same time to any of the four blocks, assuming no block conflicts. The total bandwidth is gained with DMD and PMD buses (2 × 64-bits, core CLK) and the IOD bus (32-bit, PCLK). ROM-Based Security The processor has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processor does not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG Rev. J | Page 6 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 or test access port, is assigned to each customer. The device ignores a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. FAMILY PERIPHERAL ARCHITECTURE The ADSP-2136x family contains a rich set of peripherals that support a wide variety of applications, including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, monitor control, imaging, and other applications. Parallel Port The parallel port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15–0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8-bit or 16-bit, the maximum data transfer rate is fPCLK/4. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (address latch enable) pins are the control pins for the parallel port. Serial Peripheral (Compatible) Interface The processors contain two serial peripheral interface ports (SPIs). The SPI is an industry-standard synchronous serial link, enabling the processor’s SPI-compatible port to communicate with other SPI-compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes and can operate at a maximum baud rate of fPCLK/4. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-2136x SPIcompatible peripheral implementation also features programmable baud rate, clock phase, and polarities. The SPIcompatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. Pulse-Width Modulation The entire PWM module has four groups of four PWM outputs each. Therefore, this module generates 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs. The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can Table 3. ADSP-2136x Internal Memory Space IOP Registers 0x0000 0000–0003 FFFF Long Word (64 Bits) Extended Precision Normal or Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits) Block 0 ROM 0x0004 0000–0x0004 7FFF Block 0 ROM 0x0008 0000–0x0008 AAA9 Block 0 ROM 0x0008 0000–0x0008 FFFF Block 0 ROM 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 BFFF Reserved 0x0009 0000–0x0009 7FFF Reserved 0x0012 0000–0x0012 FFFF Block 0 SRAM 0x0004 C000–0x0004 FFFF Block 0 SRAM 0x0009 0000–0x0009 5554 Block 0 SRAM 0x0009 8000–0x0009 FFFF Block 0 SRAM 0x0013 0000–0x0013 FFFF Block 1 ROM 0x0005 0000–0x0005 7FFF Block 1 ROM 0x000A 0000–0x000A AAA9 Block 1 ROM 0x000A 0000–0x000A FFFF Block 1 ROM 0x0014 0000–0x0015 FFFF Reserved 0x0005 8000–0x0005 BFFF Reserved 0x000B 0000–0x000B 7FFF Reserved 0x0016 0000–0x0016 FFFF Block 1 SRAM 0x0005 C000–0x0005 FFFF Block 1 SRAM 0x000B 0000–0x000B 5554 Block 1 SRAM 0x000B 8000–0x000B FFFF Block 1 SRAM 0x0017 0000–0x0017 FFFF Block 2 SRAM 0x0006 0000–0x0006 1FFF Block 2 SRAM 0x000C 0000–0x000C 2AA9 Block 2 SRAM 0x000C 0000–0x000C 3FFF Block 2 SRAM 0x0018 0000–0x0018 7FFF Reserved 0x0006 2000–0x0006 FFFF Reserved 0x000C 4000–0x000D FFFF Reserved 0x0018 8000–0x001B FFFF Block 3 SRAM 0x0007 0000–0x0007 1FFF Block 3 SRAM 0x000E 0000–0x000E 2AA9 Block 3 SRAM 0x000E 0000–0x000E 3FFF Block 3 SRAM 0x001C 0000–0x001C 7FFF Reserved 0x0007 2000–0x0007 FFFF Reserved 0x000E 4000–0x000F FFFF Reserved 0x001C 8000–0x001F FFFF Reserved 0x0020 0000–0xFFFF FFFF ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 7 of 60 | July 2013 generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms). The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode, the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in 3-phase PWM inverters. Digital Audio Interface (DAI) The digital audio interface (DAI) provides the ability to connect various peripherals to any of the DSP’s DAI pins (DAI_P20–1). Programs make these connections using the signal routing unit (SRU, shown in Figure 1). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI-associated peripherals for a wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI includes six serial ports, an S/PDIF receiver/transmitter, a DTCP cipher, a precision clock generator (PCG), eight channels of asynchronous sample rate converters, an input data port (IDP), an SPI port, six flag outputs and six flag inputs, and three timers. The IDP provides an additional input path to the ADSP-2136x core, configurable as either eight channels of I2S serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports. Serial Ports The processor features six synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixedsignal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and a frame sync and they can operate at maximum fPCLK/4. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel. Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 receive channels of audio data when all six SPORTs are enabled, or six full duplex TDM streams of 128 channels per frame. Serial port data can be automatically transferred to and from on-chip memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: • Standard DSP serial mode • Multichannel (TDM) mode • I2S mode • Left-justified sample pair mode S/PDIF-Compatible Digital Audio Receiver/Transmitter The S/PDIF transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a biphase encoded signal. The serial data input to the transmitter can be formatted as left-justified, I2S, or right-justified with word widths of 16, 18, 20, or 24 bits. The serial data, clock, and frame sync inputs to the S/PDIF transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the sample rate converters (SRC) and are controlled by the SRU control registers. Digital Transmission Content Protection (DTCP) The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system. This feature is available on the ADSP-21362 and ADSP-21365 processors only. Licensing through DTLA is required for these products. Visit www.dtcp.com for more information. Memory-to-Memory (MTM) If the DTCP module is not used, the memory-to-memory DMA module allows internal memory copies for a standard DMA. Synchronous/Asynchronous Sample Rate Converter (SRC) The sample rate converter (SRC) contains four SRC blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 140 dB SNR. The SRC block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. The S/PDIF and SRC are not available on the ADSP-21363 models. Input Data Port (IDP) The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive Rev. J | Page 8 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 audio channels in I2S, left-justified sample pair, or right-justified mode. One frame sync cycle indicates one 64-bit left/right pair, but data is sent to the FIFO as 32-bit words (that is, onehalf of a frame at a time). The processor supports 24- and 32-bit I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justified formats. Precision Clock Generator (PCG) The precision clock generators (PCG) consist of two units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A and B, are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Peripheral Timers The following three general-purpose timers can generate periodic interrupts and be independently set to operate in one of three modes: • Pulse waveform generation mode • Pulse width count/capture mode • External event watchdog mode Each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general-purpose timers independently. I/O PROCESSOR FEATURES The processor’s I/O provides many channels of DMA and controls the extensive set of peripherals described in the previous sections. DMA Controller The processor’s on-chip DMA controllers allow data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP), or the parallel port (PP). See Table 4. SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues. Program Booting The internal memory of the processor boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave, or an internal boot. Booting is determined by the boot configuration (BOOT_CFG1–0) pins in Table 5. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Phase-Locked Loop The processors use an on-chip phase-locked loop (PLL) to generate the internal clock for the core. On power-up, the CLK_CFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 64 and software configurable divisor values of 1, 2, 4, and 8. Power Supplies The processor has a separate power supply connection for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement for K, B, and Y grade models, and the 1.0 V requirement for Y models. (For information on the temperature ranges offered for this product, see Operating Conditions on Page 14, Package Information on Page 16, and Ordering Guide on Page 56.) The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply pin (AVDD) powers the processor’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Place the filter components as close as possible to the AVDD/AVSS pins. For an example circuit, see Figure 3. (A recommended ferrite chip is the muRata BLM18AG102SN1D.) To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for VDDINT and GND. Use wide traces to connect the bypass capacitors to the analog power (AVDD) and ground (AVSS) pins. Note that the AVDD and AVSS pins specified in Figure 3 are inputs to the processor and not the analog ground plane on the board—the AVSS pin should connect directly to digital ground (GND) at the chip. Table 4. DMA Channels Peripheral ADSP-2136x SPORTs 12 IDP/PDAP 8 SPI 2 MTM/DTCP 2 Parallel Port 1 Total DMA Channels 25 Table 5. Boot Mode Selection BOOT_CFG1–0 Booting Mode 00 SPI Slave Boot 01 SPI Master Boot 10 Parallel Port Boot via EPROM 11 No booting occurs. Processor executes from internal ROM after reset. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 9 of 60 | July 2013 Target Board JTAG Emulator Connector Analog Devices’ DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processor to monitor and control the target board processor during emulation. Analog Devices’ DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’s JTAG interface ensures that the emulator does not affect target system loading or timing. For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, refer to the appropriate emulator user’s guide. DEVELOPMENT TOOLS Analog Devices supports its processors with a complete line of software and hardware development tools, including integrated development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products, emulators, and a wide variety of software add-ins. Integrated Development Environments (IDEs) For C/C++ software writing and editing, code generation, and debug support, Analog Devices offers two IDEs. The newest IDE, CrossCore Embedded Studio, is based on the EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors, including multicore devices. CrossCore Embedded Studio seamlessly integrates available software add-ins to support real time operating systems, file systems, TCP/IP stacks, USB stacks, algorithmic software modules, and evaluation hardware board support packages. For more information visit www.analog.com/cces. The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore Embedded Studio. This IDE includes the Analog Devices VDK real time operating system and an open source TCP/IP stack. For more information visit www.analog.com/visualdsp. Note that VisualDSP++ will not support future Analog Devices processors. EZ-KIT Lite Evaluation Board For processor evaluation, Analog Devices provides wide range of EZ-KIT Lite® evaluation boards. Including the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. Also available are various EZ-Extenders®, which are daughter cards delivering additional specialized functionality, including audio and video processing. For more information visit www.analog.com and search on “ezkit” or “ezextender”. EZ-KIT Lite Evaluation Kits For a cost-effective way to learn more about developing with Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT Lite evaluation board, directions for downloading an evaluation version of the available IDE(s), a USB cable, and a power supply. The USB controller on the EZ-KIT Lite board connects to the USB port of the user’s PC, enabling the chosen IDE evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also supports in-circuit programming of the on-board Flash device to store user-specific boot code, enabling standalone operation. With the full version of Cross- Core Embedded Studio or VisualDSP++ installed (sold separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices processors. Software Add-Ins for CrossCore Embedded Studio Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities and reduce development time. Add-ins include board support packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through the CrossCore Embedded Studio IDE once the add-in is installed. Board Support Packages for Evaluation Hardware Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called Board Support Packages (BSPs). The BSPs contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. A download link for a specific BSP is located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download area of the product web page. Middleware Packages Analog Devices separately offers middleware add-ins such as real time operating systems, file systems, USB stacks, and TCP/IP stacks. For more information see the following web pages: • www.analog.com/ucos3 • www.analog.com/ucfs • www.analog.com/ucusbd • www.analog.com/lwip Algorithmic Modules To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are available for use with both CrossCore Embedded Studio and Figure 3. Analog Power (AVDD) Filter Circuit HIGH-Z FERRITE BEAD CHIP LOCATE ALL COMPONENTS CLOSE TO AVDD AND AVSS PINS AVDD AVSS 100nF 10nF 1nF ADSP-213xx VDDINT Rev. J | Page 10 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 VisualDSP++. For more information visit www.analog.com and search on “Blackfin software modules” or “SHARC software modules”. Designing an Emulator-Compatible DSP Board (Target) For embedded system test and debug, Analog Devices provides a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The processor must be halted to send data and commands, but once an operation is completed by the emulator, the DSP system is set to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports connection of the DSP’s JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the Engineer-to-Engineer Note “Analog Devices JTAG Emulation Technical Reference” (EE-68) on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the processor’s architecture and functionality. For detailed information on the ADSP-2136x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference. RELATED SIGNAL CHAINS A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the Glossary of EE Terms on the Analog Devices website. Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the www.analog.com website. The Circuits from the LabTM site (http://www.analog.com/signalchains) provides: • Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications • Drill down links for components in each chain to selection guides and application information • Reference designs applying best practice design techniques ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 11 of 60 | July 2013 PIN FUNCTION DESCRIPTIONS The processor’s pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS and TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI, and AD15–0. Note: These pins have pull-up resistors. Table 6. Pin Descriptions Pin Type State During and After Reset Function AD15–0 I/O/T (pu) Three-state with pull-up enabled Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. For details about the AD pin operation, refer to the ADSP-2136x SHARC Processor Hardware Reference. For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, ADDR23–8; ALE is used in conjunction with an external latch to retain the values of the ADDR23–8. For detailed information on I/O operations and pin multiplexing, refer to the ADSP-2136x SHARC Processor Hardware Reference. RD O (pu) Three-state, driven high1 Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or 16- bit data from an external memory device. When AD15–0 are flags, this pin remains deasserted. RD has a 22.5 kΩ internal pull-up resistor. WR O (pu) Three-state, driven high1 Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. When AD15–0 are flags, this pin remains deasserted. WR has a 22.5 kΩ internal pull-up resistor. ALE O (pd) Three-state, driven low1 Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives a new address on the parallel port address pins. On reset, ALE is active high. However, it can be reconfigured using software to be active low. When AD15–0 are flags, this pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor. FLAG[0]/IRQ0/SPI FLG[0] I/O FLAG[0] INPUT FLAG0/Interrupt Request0/SPI0 Slave Select. FLAG[1]/IRQ1/SPI FLG[1] I/O FLAG[1] INPUT FLAG1/Interrupt Request1/SPI1 Slave Select. FLAG[2]/IRQ2/SPI FLG[2] I/O FLAG[2] INPUT FLAG2/Interrupt Request 2/SPI2 Slave Select. FLAG[3]/TMREXP/ SPIFLG[3] I/O FLAG[3] INPUT FLAG3/Timer Expired/SPI3 Slave Select. DAI_P20–1 I/O/T (pu) Three-state with programmable pull-up Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the SRU can be routed to any of these pins. The SRU provides the connection from the serial ports, input data port, precision clock generators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins have internal 22.5 kΩ pull-up resistors that are enabled on reset. These pull-ups can be disabled using the DAI_PIN_PULLUP register. The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Rev. J | Page 12 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPICLK I/O (pu) Three-state with pull-up enabled, driven high in SPImaster boot mode Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master can transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (high). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor. SPIDS I Input only Serial Peripheral Interface Slave Device Select. An active low signal used to select the processor as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode the processor’s SPIDS signal can be driven by a slave device to signal to the processor (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For processor to processor SPI interaction, any of the master processor’s flag pins can be used to drive the SPIDS signal on the SPI slave device. MOSI I/O (O/D) (pu) Three-state with pull-up enabled, driven low in SPImaster boot mode SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the processor is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal pullup resistor. MISO I/O (O/D) (pu) Three-state with pull-up enabled SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the processor is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI slaves, the processor’s MISO pin can be disabled by setting Bit 5 (DMISO) of the SPICTL register equal to 1. CLKIN I Input only Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input. It configures the ADSP-2136x to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLK_CFG1–0 pin settings. CLKIN should not be halted, changed, or operated below the specified frequency. XTAL O Output only2 Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. CLK_CFG1–0 I Input only Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are: 00 = 6:1 01 = 32:1 10 = 16:1 11 = reserved. Table 6. Pin Descriptions (Continued) Pin Type State During and After Reset Function The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 13 of 60 | July 2013 BOOT_CFG1–0 I Input only Boot Configuration Select. This pin is used to select the boot mode for the processor. The BOOT_CFG pins must be valid before reset is asserted. For a description of the boot mode, refer to Table 5, Boot Mode Selection. RESETOUT O Output only Reset Out. Drives out the core reset signal to an external device. RESET I/A Input only Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. TCK I Input only3 Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed low) after power-up or held low for proper operation of the processors. TMS I/S (pu) Three-state with pull-up enabled Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ internal pull-up resistor. TDI I/S (pu) Three-state with pull-up enabled Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 kΩ internal pull-up resistor. TDO O Three-state4 Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I/A (pu) Three-state with pull-up enabled Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2136x. TRST has a 22.5 kΩ internal pull-up resistor. EMU O (O/D) (pu) Three-state with pull-up enabled Emulation Status. Must be connected to the processor’s JTAG emulators target board connector only. EMU has a 22.5 kΩ internal pull-up resistor. VDDINT P Core Power Supply. Supplies the processor’s core. VDDEXT P I/O Power Supply. AVDD P Analog Power Supply. Supplies the processor’s internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on Page 8. AVSS G Analog Power Supply Return. GND G Power Supply Return. 1RD, WR, and ALE are three-stated (and not driven) only when RESET is active. 2Output only is a three-state driver with its output path always enabled. 3 Input only is a three-state driver with both output path and pull-up disabled. 4Three-state is a three-state driver with pull-up disabled. Table 6. Pin Descriptions (Continued) Pin Type State During and After Reset Function The following symbols appear in the Type column of Table 6: A = asynchronous, G = ground, I = input, O = output, P = power supply, S = synchronous, (A/D) = active drive, (O/D) = open drain, and T = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. Rev. J | Page 14 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPECIFICATIONS Specifications are subject to change without notice. OPERATING CONDITIONS K Grade B Grade Y Grade Parameter Description Min Nom Max Min Nom Max Min Nom Max Unit VDDINT Internal (Core) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V AVDD Analog (PLL) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 0.95 1.0 1.05 V VDDEXT External (I/O) Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V VIH 1 1 Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, and TRST. High Level Input Voltage @ VDDEXT = Max 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 2.0 VDDEXT + 0.5 V VIL 1 Low Level Input Voltage @ VDDEXT = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V VIH_CLKIN 2 2 Applies to input pin CLKIN. High Level Input Voltage @ VDDEXT = Max 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 1.74 VDDEXT + 0.5 V VIL_CLKIN Low Level Input Voltage @ VDDEXT = Min –0.5 +1.19 –0.5 +1.19 –0.5 +1.19 V TJ 3, 4 3 See Thermal Characteristics on Page 47 for information on thermal specifications. 4 See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information. Junction Temperature 136-Ball CSP_BGA 0 +110 –40 +125 –40 +125 °C TJ 3, 4 Junction Temperature 144-Lead LQFP_EP 0 +110 –40 +125 –40 +125 °C ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 15 of 60 | July 2013 ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min Max Unit VOH 1 High Level Output Voltage @ VDDEXT = Min, IOH = –1.0 mA2 2.4 V VOL 1 Low Level Output Voltage @ VDDEXT = Min, IOL = 1.0 mA2 0.4 V IIH 3, 4 High Level Input Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μA IIL 3 Low Level Input Current @ VDDEXT = Max, VIN = 0 V 10 μA IILPU 4 Low Level Input Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μA IOZH 5, 6 Three-State Leakage Current @ VDDEXT = Max, VIN = VDDEXT Max 10 μA IOZL 5 Three-State Leakage Current @ VDDEXT = Max, VIN = 0 V 10 μA IOZLPU 6 Three-State Leakage Current Pull-Up @ VDDEXT = Max, VIN = 0 V 200 μA IDD-INTYP 7, 8 Supply Current (Internal) tCCLK = Min, VDDINT = Nom 800 mA IAVDD 9 Supply Current (Analog) AVDD = Max 10 mA CIN 10, 11 Input Capacitance fIN = 1 MHz, TCASE = 25°C, VIN = 1.2 V 4.7 pF 1 Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, and XTAL. 2 See Output Drive Currents on Page 46 for typical drive current capabilities. 3 Applies to input pins: SPIDS, BOOT_CFGx, CLK_CFGx, TCK, RESET, and CLKIN. 4 Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI. 5 Applies to three-stateable pins: FLAG3–0. 6 Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, and MOSI. 7Typical internal current data reflects nominal operating conditions. 8 See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for further information. 9Characterized, but not tested. 10Applies to all signal pins. 11Guaranteed, but not tested. Rev. J | Page 16 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 PACKAGE INFORMATION The information presented in Figure 4 provides details about the package branding for the ADSP-2136x processor. For a complete listing of product availability, see Ordering Guide on Page 56. ESD CAUTION MAXIMUM POWER DISSIPATION See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal Characteristics on Page 47. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 8 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TIMING SPECIFICATIONS Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. For voltage reference levels, see Figure 39 on Page 46 under Test Conditions. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Core Clock Requirements The processor’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1–0 pins. The processor’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the processor uses an internal phase-locked loop (PLL, see Figure 5). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the processor’s internal clock. Voltage Controlled Oscillator In application designs, the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fVCO specified in Table 11. Figure 4. Typical Package Brand Table 7. Package Brand Information Brand Key Field Description t Temperature Range pp Package Type Z RoHS Compliant Designation cc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision # RoHS Compliant Designation yyww Date Code tppZ-cc S ADSP-2136x a #yyww country_of_origin vvvvvv.x n.n ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Table 8. Absolute Maximum Ratings Parameter Rating Internal (Core) Supply Voltage (VDDINT) –0.3 V to +1.5 V Analog (PLL) Supply Voltage (AVDD) –0.3 V to +1.5 V External (I/O) Supply Voltage (VDDEXT) –0.3 V to +4.6 V Input Voltage –0.5 V to +3.8 V Output Voltage Swing –0.5 V to VDDEXT + 0.5 V Load Capacitance 200 pF Storage Temperature Range –65°C to +150°C Junction Temperature While Biased 125°C ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 17 of 60 | July 2013 • The product of CLKIN and PLLM must never exceed 1/2 fVCO (max) in Table 11 if the input divider is not enabled (INDIV = 0). • The product of CLKIN and PLLM must never exceed fVCO (max) in Table 11 if the input divider is enabled (INDIV = 1). The VCO frequency is calculated as follows: fVCO = 2 × PLLM × fINPUT fCCLK = (2 × PLLM × fINPUT) ÷ (2 × PLLN) where: fVCO = VCO output PLLM = Multiplier value programmed in the PMCTL register. During reset, the PLLM value is derived from the ratio selected using the CLK_CFG pins in hardware. PLLN = 1, 2, 4, 8 based on the PLLD value programmed on the PMCTL register. During reset this value is 1. fINPUT = Input frequency to the PLL. fINPUT = CLKIN when the input divider is disabled or fINPUT = CLKIN ÷ 2 when the input divider is enabled Note the definitions of the clock periods that are a function of CLKIN and the appropriate ratio control shown in Table 9. All of the timing specifications for the ADSP-2136x peripherals are defined in relation to tPCLK. Refer to the peripheral specific section for each peripheral’s timing information. Figure 5 shows core to CLKIN relationships with external oscillator or crystal. The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference. Table 9. Clock Periods Timing Requirements Description tCK CLKIN Clock Period tCCLK Processor Core Clock Period tPCLK Peripheral Clock Period = 2 × tCCLK Figure 5. Core Clock and System Clock Relationship to CLKIN CLKOUT (TEST ONLY)* LOOP FILTER PLL fVCO ÷ (2 × PLLM) VCO PLL DIVIDER PMCTL (2 × PLLN) fVCO fCCLK CLK_CFGx/ PMCTL (2 × PLLM) CLKIN PCLK XTAL CLKIN DIVIDER RESETOUT DELAY OF 4096 CLKIN CYCLES RESET BUF BUF PMCTL (INDIV) PMCTL (PLLBP) BYPASS MUX PIN MUX DIVIDE BY 2 RESETOUT PMCTL (CLKOUTEN) CCLK CORERST *CLKOUT (TEST ONLY) FREQUENCY IS THE SAME AS fINPUT. THIS SIGNAL IS NOT SPECIFIED OR SUPPORTED FOR ANY DESIGN. fINPUT Rev. J | Page 18 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Power-Up Sequencing The timing requirements for processor startup are given in Table 10. Note that during power-up, when the VDDINT power supply comes up after VDDEXT, a leakage current of the order of three-state leakage current pull-up, pull-down, may be observed on any pin, even if that is an input only (for example the RESET pin) until the VDDINT rail has powered up. Table 10. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Min Max Unit Timing Requirements tRSTVDD RESET Low Before VDDINT/VDDEXT On 0 ns tIVDDEVDD VDDINT On Before VDDEXT –50 +200 ms tCLKVDD 1 CLKIN Valid After VDDINT/VDDEXT Valid 0 200 ms tCLKRST CLKIN Valid Before RESET Deasserted 102 μs tPLLRST PLL Control Setup Before RESET Deasserted 20 μs Switching Characteristic tCORERST Core Reset Deasserted After RESET Deasserted 4096tCK + 2 tCCLK 3, 4 1Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds, depending on the design of the power supply subsystem. 2Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate default states at all I/O pins. 4The 4096 cycle count depends on tSRST specification in Table 12. If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles maximum. Figure 6. Power-Up Sequencing tRSTVDD tCLKVDD tCLKRST tPLLRST tCORERST VDDEXT VDDINT CLKIN CLK_CFG1–0 RESET RESETOUT tIVDDEVDD ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 19 of 60 | July 2013 Clock Input Clock Signals The processor can use an external clock or a crystal. Refer to the CLKIN pin description in Table 6 on Page 11. The user application program can configure the processor to use its internal clock generator by connecting the necessary components to the CLKIN and XTAL pins. Figure 8 shows the component connections used for a fundamental frequency crystal operating in parallel mode. Note that the clock rate is achieved using a 16.67 MHz crystal and a PLL multiplier ratio 16:1. (CCLK:CLKIN achieves a clock speed of 266.72 MHz.) To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. Table 11. Clock Input Parameter 200 MHz1 1 Applies to all 200 MHz models. See Ordering Guide on Page 56. 333 MHz2 2 Applies to all 333 MHz models. See Ordering Guide on Page 56. Min Max Min Max Unit Timing Requirements tCK CLKIN Period 303 3 Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in the PMCTL register. 100 18 100 ns tCKL CLKIN Width Low 12.5 7.5 ns tCKH CLKIN Width High 12.5 7.5 ns tCKRF CLKIN Rise/Fall (0.4 V to 2.0 V) 3 3 ns tCCLK 4 4 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK. CCLK Period 5.0 10 3.0 10 ns tVCO 5 5 See Figure 5 on Page 17 for VCO diagram. VCO Frequency 200 600 200 800 MHz tCKJ 6, 7 6 Actual input jitter should be combined with AC specifications for accurate timing analysis. 7 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter. CLKIN Jitter Tolerance –250 +250 –250 +250 ps Figure 7. Clock Input CLKIN tCK tCKH tCKL tCKJ Figure 8. Recommended Circuit for Fundamental Mode Crystal Operation C1 22pF Y1 R1 1M * CLKIN XTAL C2 22pF 24.576MHz R2 * ADSP-2136x R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER. REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS. *TYPICAL VALUES 47Ω Ω Rev. J | Page 20 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Reset Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Table 12. Reset Parameter Min Unit Timing Requirements tWRST 1 RESET Pulse Width Low 4 × tCK ns tSRST RESET Setup Before CLKIN Low 8 ns 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). Figure 9. Reset CLKIN RESET tWRST tSRST Table 13. Interrupts Parameter Min Unit Timing Requirement tIPW IRQx Pulse Width 2 × tPCLK +2 ns Figure 10. Interrupts INTERRUPT INPUTS tIPW ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 21 of 60 | July 2013 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (TMREXP pin). Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 14. Core Timer Parameter Min Unit Switching Characteristic tWCTIM TMREXP Pulse Width 2 × tPCLK – 1 ns Figure 11. Core Timer FLAG3 (TMREXP) tWCTIM Table 15. Timer PWM_OUT Timing Parameter Min Max Unit Switching Characteristic tPWMO Timer Pulse Width Output 2 × tPCLK – 1 2 × (231 – 1) × tPCLK ns Figure 12. Timer PWM_OUT Timing PWM OUTPUTS tPWMO Rev. J | Page 22 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specification provided below are valid at the DAI_P20–1 pins. DAI Pin to Pin Direct Routing For direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 16. Timer Width Capture Timing Parameter Min Max Unit Timing Requirement tPWI Timer Pulse Width 2 × tPCLK 2 × (231– 1) × tPCLK ns Figure 13. Timer Width Capture Timing TIMER CAPTURE INPUTS tPWI Table 17. DAI Pin to Pin Routing Parameter Min Max Unit Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns Figure 14. DAI Pin to Pin Direct Routing DAI_Pn DAI_Pm tDPIO ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 23 of 60 | July 2013 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing parameters and switching characteristics apply to external DAI pins (DAI_P01 through DAI_P20). Table 18. Precision Clock Generator (Direct Pin Routing) K and B Grade Y Grade Parameter Min Max Max Unit Timing Requirements tPCGIP Input Clock Period tPCLK × 4 ns tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input Clock 4.5 ns tHTRIG PCG Trigger Hold After Falling Edge of PCG Input Clock 3 ns Switching Characteristics tDPCGIO PCG Output Clock and Frame Sync Active Edge Delay After PCG Input Clock 2.5 10 10 ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2.5 + (2.5 × tPCGIP) 10 + (2.5 × tPCGIP) 12 + (2.5 × tPCGIP) ns tDTRIGFS PCG Frame Sync Delay After PCG Trigger 2.5 + ((2.5 + D – PH) × tPCGIP) 10 + ((2.5 + D – PH) × tPCGIP) 12 + ((2.5 + D – PH) × tPCGIP) ns tPCGOP 1 Output Clock Period 2 × tPCGIP – 1 ns D = FSxDIV, PH = FSxPHASE. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter. 1 In normal mode, tPCGOP (min) = 2 × tPCGIP. Figure 15. Precision Clock Generator (Direct Pin Routing) DAI_Pn PCG_TRIGx_I DAI_Pm PCG_EXTx_I (CLKIN) DAI_Py PCG_CLKx_O DAI_Pz PCG_FSx_O tDTRIGFS tDTRIGCLK tDPCGIO tSTRIG tHTRIG tDPCGIO tPCGOP tPCGIP Rev. J | Page 24 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface (SPI). See Table 6 on Page 11 for more information on flag use. Table 19. Flags Parameter Min Unit Timing Requirement tFIPW FLAG3–0 IN Pulse Width 2 × tPCLK + 3 ns Switching Characteristic tFOPW FLAG3–0 OUT Pulse Width 2 × tPCLK – 1 ns Figure 16. Flags FLAG INPUTS FLAG OUTPUTS tFOPW tFIPW ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 25 of 60 | July 2013 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter K and B Grade Y Grade Min Max Min Max Unit Timing Requirements tDRS AD7–0 Data Setup Before RD High 3.3 4.5 ns tDRH AD7–0 Data Hold After RD High 0 0 ns tDAD AD15–8 Address to AD7–0 Data Valid D + tPCLK – 5.0 D + tPCLK – 5.0 ns Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 2 × tPCLK – 2.0 ns tADAS 1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tPCLK – 2.5 ns tRRH Delay Between RD Rising Edge to Next Falling Edge H + tPCLK – 1.4 H + tPCLK – 1.4 ns tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 2 × tPCLK – 3.8 ns tRWALE Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns tADAH 1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tPCLK – 2.3 ns tALEHZ 1 ALE Deasserted to AD7–0 Address in High-Z tPCLK tPCLK + 3.0 tPCLK tPCLK + 3.8 ns tRW RD Pulse Width D – 2.0 D – 2.0 ns tRDDRV AD7–0 ALE Address Drive After Read High F + H + tPCLK – 2.3 F + H + tPCLK – 2.3 ns tADRH AD15–8 Address Hold After RD High H H ns tDAWH AD15–8 Address to RD High D + tPCLK – 4.0 D + tPCLK – 4.0 ns D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0) 1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low. Figure 17. Read Cycle for 8-Bit Memory Timing ALE RD WR AD15–8 AD7–0 tALEW tALERW tRWALE tRW tRRH tRDDRV tDAWH tADAS tADAH VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID DATA VALID DATA tADRH tDAD tDRS tDRH tALEHZ NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION. Rev. J | Page 26 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 21. 16-Bit Memory Read Cycle Parameter K and B Grade Y Grade Min Max Min Max Unit Timing Requirements tDRS AD15–0 Data Setup Before RD High 3.3 4.5 ns tDRH AD15–0 Data Hold After RD High 0 0 ns Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 2 × tPCLK – 2.0 ns tADAS 1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tPCLK – 2.5 ns tALERW ALE Deasserted to Read Asserted 2 × tPCLK – 3.8 2 × tPCLK – 3.8 ns tRRH 2 Delay Between RD Rising Edge to Next Falling Edge H + tPCLK – 1.4 H + tPCLK – 1.4 ns tRWALE Read Deasserted to ALE Asserted F + H + 0.5 F + H + 0.5 ns tRDDRV ALE Address Drive After Read High F + H + tPCLK – 2.3 F + H + tPCLK – 2.3 ns tADAH 1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tPCLK – 2.3 ns tALEHZ1 ALE Deasserted to Address/Data15–0 in High-Z tPCLK tPCLK + 3.0 tPCLK tPCLK + 3.8 ns tRW RD Pulse Width D – 2.0 D – 2.0 ns D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0) 1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low. 2This parameter is only available when in EMPP = 0 mode. Figure 18. Read Cycle for 16-Bit Memory Timing tRWALE tRDDRV VALID VALID ADDRESS VALID DATA VALID DATA ADDRESS ALE RD WR AD15–0 tADAS tADAH tALEHZ tDRS tDRH tALEW tALERW tRW tRRH NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP  0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 27 of 60 | July 2013 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the processor is accessing external memory space. Table 22. 8-Bit Memory Write Cycle Parameter K and B Grade Y Grade Min Min Unit Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 2 × tPCLK – 2.0 ns tADAS 1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.8 tPCLK – 2.8 ns tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 2 × tPCLK – 3.8 ns tRWALE Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns tWRH Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 F + H + tPCLK – 2.3 ns tADAH 1 AD15–0 Address Hold After ALE Deasserted tPCLK – 0.5 tPCLK – 0.5 ns tWW WR Pulse Width D – F – 2.0 D – F – 2.0 ns tADWL AD15–8 Address to WR Low tPCLK – 2.8 tPCLK – 3.5 ns tADWH AD15–8 Address Hold After WR High H H ns tDWS AD7–0 Data Setup Before WR High D – F + tPCLK – 4.0 D – F + tPCLK – 4.0 ns tDWH AD7–0 Data Hold After WR High H H ns tDAWH AD15–8 Address to WR High D – F + tPCLK – 4.0 D – F + tPCLK – 4.0 ns D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK. H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be  9 × tPCLK. 1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low. Figure 19. Write Cycle for 8-Bit Memory Timing AD15-8 VALID ADDRESS VALID ADDRESS tADAS AD7-0 ALE RD WR tADAH tADWH tADWL VALID DATA tDAWH tWRH tRWALE VALID ADDRESS VALID DATA tALEW tALERW tWW tDWS tDWH VALID ADDRESS NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY TWO MEMORY WRITES TO PROVIDE THE NECESSARY TIMING INFORMATION. Rev. J | Page 28 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 23. 16-Bit Memory Write Cycle Parameter K and B Grade Y Grade Min Min Unit Switching Characteristics tALEW ALE Pulse Width 2 × tPCLK – 2.0 2 × tPCLK – 2.0 ns tADAS 1 AD15–0 Address Setup Before ALE Deasserted tPCLK – 2.5 tPCLK – 2.5 ns tALERW ALE Deasserted to Write Asserted 2 × tPCLK – 3.8 2 × tPCLK – 3.8 ns tRWALE Write Deasserted to ALE Asserted H + 0.5 H + 0.5 ns tWRH 2 Delay Between WR Rising Edge to Next WR Falling Edge F + H + tPCLK – 2.3 F + H + tPCLK – 2.3 ns tADAH 1 AD15–0 Address Hold After ALE Deasserted tPCLK – 2.3 tPCLK – 2.3 ns tWW WR Pulse Width D – F – 2.0 D – F – 2.0 ns tDWS AD15–0 Data Setup Before WR High D – F + tPCLK – 4.0 D – F + tPCLK – 4.0 ns tDWH AD15–0 Data Hold After WR High H H ns D = (the value set by the PPDUR Bits (5–1) in the PPCTL register) × tPCLK. H = tPCLK (if a hold cycle is specified, else H = 0) F = 7 × tPCLK (if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be  9 × tPCLK. tPCLK = (peripheral) clock period = 2 × tCCLK 1 On reset, ALE is an active high cycle. However, it can be configured by software to be active low. 2This parameter is only available when in EMPP = 0 mode. Figure 20. Write Cycle for 16-Bit Memory Timing AD15-0 VALID ADDRESS VALID DATA tADAS ALE RD WR tADAH tWRH tRWALE tALEW tALERW tWW tDWS tDWH VALID DATA VALID ADDRESS NOTE: FOR 16-BIT MEMORY WRITES, WHEN EMPP 􀂏 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES. WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION, SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 29 of 60 | July 2013 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync (FS) delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SCLK) width. Serial port signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 24. Serial Ports—External Clock K and B Grade Y Grade Parameter Min Max Max Unit Timing Requirements tSFSE 1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns tHFSE 1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns tSDRE 1 Receive Data Setup Before Receive SCLK 2.5 ns tHDRE 1 Receive Data Hold After SCLK 2.5 ns tSCLKW SCLK Width (tPCLK × 4) ÷ 2 – 2 ns tSCLK SCLK Period tPCLK × 4 ns Switching Characteristics tDFSE 2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 9.5 11 ns tHOFSE 2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 2 ns tDDTE 2 Transmit Data Delay After Transmit SCLK 9.5 11 ns tHDTE 2 Transmit Data Hold After Transmit SCLK 2 ns 1 Referenced to sample edge. 2 Referenced to drive edge. Table 25. Serial Ports—Internal Clock K and B Grade Y Grade Parameter Min Max Max Unit Timing Requirements tSFSI 1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 7 ns tHFSI 1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 2.5 ns tSDRI 1 Receive Data Setup Before SCLK 7 ns tHDRI 1 Receive Data Hold After SCLK 2.5 ns Switching Characteristics tDFSI 2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 3 3.5 ns tHOFSI 2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1.0 ns tDFSIR 2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 8 9.5 ns tHOFSIR 2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1.0 ns tDDTI 2 Transmit Data Delay After SCLK 3 4.0 ns tHDTI 2 Transmit Data Hold After SCLK –1.0 ns tSCLKIW Transmit or Receive SCLK Width 2 × tPCLK – 2 2 × tPCLK + 2 2 × tPCLK + 2 ns 1 Referenced to the sample edge. 2 Referenced to drive edge. Rev. J | Page 30 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 21. Serial Ports DRIVE EDGE SAMPLE EDGE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (FS) DAI_P20–1 (SCLK) tHOFSI tHFSI tHDRI DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (FS) DAI_P20–1 (SCLK) tHFSI tDDTI DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (FS) DAI_P20–1 (SCLK) tHOFSI tHOFSE tHDTI tHFSE tHDTE tDDTE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (FS) DAI_P20–1 (SCLK) tHOFSE tHFSE tHDRE DATA RECEIVE—EXTERNAL CLOCK tSCLKIW tDFSI tSFSI tSDRI tSCLKW tDFSE tSFSE tSDRE tDFSE tSFSI tSFSE tDFSI tSCLKIW tSCLKW ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 31 of 60 | July 2013 Table 26. Serial Ports—External Late Frame Sync K and B Grade Y Grade Parameter Min Max Max Unit Switching Characteristics tDDTLFSE 1 Data Delay from Late External Transmit Frame Sync or External Receive FS with MCE = 1, MFD = 0 9 10.5 ns tDDTENFS 1 Data Enable for MCE = 1, MFD = 0 0.5 ns 1The tDDTLFSE and tDDTENFS parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0. Figure 22. External Late Frame Sync DRIVE SAMPLE EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 2ND BIT DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) 1ST BIT DRIVE tDDTE/I tHDTE/I tDDTLFSE tDDTENFS tSFSE/I DRIVE SAMPLE LATE EXTERNAL TRANSMIT FS 2ND BIT DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) 1ST BIT DRIVE tDDTE/I tHDTE/I tDDTLFSE tDDTENFS tSFSE/I tHFSE/I tHFSE/I Rev. J | Page 32 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Table 27. Serial Ports—Enable and Three-State K and B Grade Y Grade Parameter Min Max Max Unit Switching Characteristics tDDTEN 1 Data Enable from External Transmit SCLK 2 ns tDDTTE 1 Data Disable from External Transmit SCLK 7 8.5 ns tDDTIN 1 Data Enable from Internal Transmit SCLK –1 ns 1 Referenced to drive edge. Figure 23. Enable and Three-State DRIVE EDGE DRIVE EDGE DRIVE EDGE tDDTIN tDDTEN tDDTTE DAI_P20–1 (SCLK, INT) DAI_P20–1 (DATA CHANNEL A/B) DAI_P20–1 (SCLK, EXT) DAI_P20–1 (DATA CHANNEL A/B) ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 33 of 60 | July 2013 Input Data Port (IDP) The timing requirements for the IDP are given in Table 28. IDP signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. IDP Parameter Min Unit Timing Requirements tSISFS 1 Frame Sync Setup Before Clock Rising Edge 3 ns tSIHFS 1 Frame Sync Hold After Clock Rising Edge 3 ns tSISD 1 Data Setup Before Clock Rising Edge 3 ns tSIHD 1 Data Hold After Clock Rising Edge 3 ns tIDPCLKW Clock Width (tPCLK × 4) ÷ 2 – 1 ns tIDPCLK Clock Period tPCLK × 4 ns 1 The data, clock, and frame sync signals can come from any of the DAI pins. Clock and frame sync can also come via the PCGs or SPORTs. The PCG’s input can be either CLKIN or any of the DAI pins. Figure 24. IDP Master Timing DAI_P20–1 (SCLK) SAMPLE EDGE DAI_P20–1 (FS) DAI_P20–1 (SDATA) tIDPCLK tIDPCLKW tSISFS tSIHFS tSIHD tSISD Rev. J | Page 34 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Input Data Port” chapter. Note that the most significant 16 bits of external 20-bit PDAP data can be provided through either the parallel port AD15–0 pins or the DAI_P20–5 pins. The remaining 4 bits can only be sourced through DAI_P4–1. The timing below is valid at the DAI_P20–1 pins or at the AD15–0 pins. Table 29. Parallel Data Acquisition Port (PDAP) Parameter Min Unit Timing Requirements tSPCLKEN 1 PDAP_CLKEN Setup Before PDAP_CLK Sample Edge 2.5 ns tHPCLKEN 1 PDAP_CLKEN Hold After PDAP_CLK Sample Edge 2.5 ns tPDSD 1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge 3.0 ns tPDHD 1 PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge 2.5 ns tPDCLKW Clock Width (tPCLK × 4) ÷ 2 – 3 ns tPDCLK Clock Period tPCLK × 4 ns Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 × tPCLK – 1 ns tPDSTRB PDAP Strobe Pulse Width 2 × tPCLK – 1.5 ns 1Data source pins are AD15–0 and DAI_P4–1, or DAI pins. Source pins for serial clock and frame sync are DAI pins. Figure 25. PDAP Timing DAI_P20–1 (PDAP_CLK) SAMPLE EDGE DAI_P20–1 (PDAP_HOLD) DAI_P20–1 (PDAP_STROBE) tPDHLDD tPDSTRB tPDSD tPDHD tSPHOLD tHPHOLD tPDCLK tPDCLKW DAI_P20–1/ ADDR23–4 (PDAP_DATA) ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 35 of 60 | July 2013 Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port The SRC input signals are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided in Table 31 are valid at the DAI_P20–1 pins. This feature is not available on the ADSP-21363 models. Table 30. PWM Timing1 Parameter Min Max Unit Switching Characteristics tPWMW PWM Output Pulse Width tPCLK – 2 (216 – 2) × tPCLK ns tPWMP PWM Output Period 2 × tPCLK – 1.5 (216 – 1) × tPCLK ns 1Note that the PWM output signals are shared on the parallel port bus (AD15-0 pins). Figure 26. PWM Timing PWM OUTPUTS tPWMW tPWMP Table 31. SRC, Serial Input Port Parameter Min Unit Timing Requirements tSRCSFS 1 Frame Sync Setup Before Serial Clock Rising Edge 3 ns tSRCHFS 1 Frame Sync Hold After Serial Clock Rising Edge 3 ns tSRCSD 1 SDATA Setup Before Serial Clock Rising Edge 3 ns tSRCHD 1 SDATA Hold After Serial Clock Rising Edge 3 ns tSRCCLKW Clock Width 36 ns tSRCCLK Clock Period 80 ns 1 The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via the PCGs or SPORTs. The PCG’s input can be either CLKIN or any of the DAI pins. Rev. J | Page 36 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 27. SRC Serial Input Port Timing DAI_P20–1 (SCLK) SAMPLE EDGE DAI_P20–1 (FS) DAI_P20–1 (SDATA) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS tSRCSD tSRCHD ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 37 of 60 | July 2013 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and should meet setup and hold times with regard to the serial clock on the output port. The serial data output has a hold time and delay specification with regard to serial clock. Note that the serial clock rising edge is the sampling edge and the falling edge is the drive edge. Table 32. SRC, Serial Output Port K and B Grade Y Grade Parameter Min Max Max Unit Timing Requirements tSRCSFS 1 Frame Sync Setup Before Serial Clock Rising Edge 3 ns tSRCHFS 1 Frame Sync Hold After Serial Clock Rising Edge 3 ns Switching Characteristics tSRCTDD 1 Transmit Data Delay After Serial Clock Falling Edge 10.5 12.5 ns tSRCTDH 1 Transmit Data Hold After Serial Clock Falling Edge 2 ns 1 The data, serial clock, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. Figure 28. SRC Serial Output Port Timing DAI_P20–1 (SCLK) SAMPLE EDGE DAI_P20–1 (FS) DAI_P20–1 (SDATA) tSRCCLK tSRCCLKW tSRCSFS tSRCHFS tSRCTDD tSRCTDH Rev. J | Page 38 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as left justified, I2S, or right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 29 shows the right-justified mode. Frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is delayed the minimum in 24-bit output mode or the maximum in 16-bit output mode from a frame sync transition, so that when there are 64 serial clock periods per frame sync period, the LSB of the data is rightjustified to the next frame sync transition. Table 33. S/PDIF Transmitter Right-Justified Mode Parameter Nominal Unit Timing Requirement tRJD FS to MSB Delay in Right-Justified Mode 16-Bit Word Mode 18-Bit Word Mode 20-Bit Word Mode 24-Bit Word Mode 16 14 12 8 SCLK SCLK SCLK SCLK Figure 29. Right-Justified Mode MSB LEFT/RIGHT CHANNEL LSB MSB–1 MSB–2 LSB+2 LSB+1 LSB DAI_P20–1 FS DAI_P20–1 SCLK DAI_P20–1 SDATA tRJD ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 39 of 60 | July 2013 Figure 30 shows the default I2S-justified mode. The frame sync is low for the left channel and high for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition but with a delay. Figure 31 shows the left-justified mode. The frame sync is high for the left channel and low for the right channel. Data is valid on the rising edge of serial clock. The MSB is left-justified to the frame sync transition with no delay. Table 34. S/PDIF Transmitter I2S Mode Parameter Nominal Unit Timing Requirement tI2SD FS to MSB Delay in I2S Mode 1 SCLK Figure 30. I2S-Justified Mode MSB LEFT/RIGHT CHANNEL MSB–1 MSB–2 LSB+2 LSB+1 LSB DAI_P20–1 FS DAI_P20–1 SCLK DAI_P20–1 SDATA tI2SD Table 35. S/PDIF Transmitter Left-Justified Mode Parameter Nominal Unit Timing Requirement tLJD FS to MSB Delay in Left-Justified Mode 0 SCLK Figure 31. Left-Justified Mode MSB LEFT/RIGHT CHANNEL MSB–1 MSB–2 LSB+2 LSB+1 LSB DAI_P20–1 FS DAI_P20–1 SCLK DAI_P20–1 SDATA tLJD Rev. J | Page 40 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 36. Input signals are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Oversampling Clock (TxCLK) Switching Characteristics The S/PDIF transmitter requires an oversampling clock input. This high frequency clock (TxCLK) input is divided down to generate the internal biphase clock. Table 36. S/PDIF Transmitter Input Data Timing K Grade Y Grade Parameter Min Max Min Max Unit Timing Requirements tSISFS 1 Frame Sync Setup Before Serial Clock Rising Edge 3 3 ns tSIHFS 1 Frame Sync Hold After Serial Clock Rising Edge 3 3 ns tSISD 1 Data Setup Before Serial Clock Rising Edge 3 3 ns tSIHD 1 Data Hold After Serial Clock Rising Edge 3 3 ns tSITXCLKW Transmit Clock Width 9 9.5 ns tSITXCLK Transmit Clock Period 20 20 ns tSISCLKW Clock Width 36 36 ns tSISCLK Clock Period 80 80 ns 1 The serial clock, data and frame sync signals can come from any of the DAI pins.The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. Figure 32. S/PDIF Transmitter Input Timing SAMPLE EDGE DAI_P20–1 (TxCLK) DAI_P20–1 (SCLK) DAI_P20–1 (FS) DAI_P20–1 (SDATA) tSITXCLKW tSITXCLK tSISCLKW tSISCLK tSISFS tSIHFS tSISD tSIHD Table 37. Oversampling Clock (TxCLK) Switching Characteristics Parameter Max Unit Frequency for TxCLK = 384 × Frame Sync Oversampling Ratio × Frame Sync <= 1/tSITXCLK MHz Frequency for TxCLK = 256 × Frame Sync 49.2 MHz Frame Rate (FS) 192.0 kHz ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 41 of 60 | July 2013 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. This feature is not available on the ADSP-21363 processors. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode) Parameter Min Max Unit Switching Characteristics tDFSI Frame Sync Delay After Serial Clock 5 ns tHOFSI Frame Sync Hold After Serial Clock –2 ns tDDTI Transmit Data Delay After Serial Clock 5 ns tHDTI Transmit Data Hold After Serial Clock –2 ns tSCLKIW 1 Transmit Serial Clock Width 38 ns 1 Serial clock frequency is 64 ×FS where FS = the frequency of frame sync. Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing DAI_P20–1 (SCLK) SAMPLE EDGE DAI_P20–1 (FS) DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE tSCLKIW tDFSI tHOFSI tDDTI tHDTI Rev. J | Page 42 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SPI Interface—Master The processor contains two SPI ports. The primary has dedicated pins and the secondary is available through the DAI. The timing provided in Table 39 and Table 40 applies to both ports. Table 39. SPI Interface Protocol—Master Switching and Timing Specifications Parameter K and B Grade Y Grade Min Max Min Max Unit Timing Requirements tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) 5.2 6.2 ns tSSPIDM Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2) 8.2 9.5 ns tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid 2 2 ns Switching Characteristics tSPICLKM Serial Clock Cycle 8 × tPCLK – 2 8 × tPCLK – 2 ns tSPICHM Serial Clock High Period 4 × tPCLK – 2 4 × tPCLK – 2 ns tSPICLM Serial Clock Low Period 4 × tPCLK – 2 4 × tPCLK – 2 ns tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) 3.0 3.0 ns tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2) 8.0 9.5 ns tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 4 × tPCLK – 2 4 × tPCLK – 2 ns tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge 4 × tPCLK – 2.5 4 × tPCLK – 3.0 ns tSDSCIM FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2) 4 × tPCLK – 2.5 4 × tPCLK – 3.0 ns tHDSM Last SPICLK Edge to FLAG3–0IN High 4 × tPCLK – 2 4 × tPCLK – 2 ns tSPITDM Sequential Transfer Delay 4 × tPCLK – 1 4 × tPCLK – 1 ns Figure 34. SPI Master Timing tSDSCIM tSPICHM tSPICLM tSPICLKM tHDSM tSPITDM tDDSPIDM tSSPIDM tHSPIDM DPI (OUTPUT) MOSI (OUTPUT) MISO (INPUT) MOSI (OUTPUT) MISO (INPUT) CPHASE = 1 CPHASE = 0 tHDSPIDM tHSPIDM tHSPIDM tSSPIDM tSSPIDM tDDSPIDM tHDSPIDM SPICLK (CP = 0, CP = 1) (OUTPUT) ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 43 of 60 | July 2013 SPI Interface—Slave Table 40. SPI Interface Protocol—Slave Switching and Timing Specifications K and B Grade Y Grade Parameter Min Max Max Unit Timing Requirements tSPICLKS Serial Clock Cycle 4 × tPCLK – 2 ns tSPICHS Serial Clock High Period 2 × tPCLK – 2 ns tSPICLS Serial Clock Low Period 2 × tPCLK – 2 ns tSDSCO SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 2 × tPCLK 2 × tPCLK ns ns tHDS Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 2 × tPCLK ns tSSPIDS Data Input Valid to SPICLK Edge (Data Input Setup Time) 2 ns tHSPIDS SPICLK Last Sampling Edge to Data Input Not Valid 2 ns tSDPPW SPIDS Deassertion Pulse Width (CPHASE = 0) 2 × tPCLK ns Switching Characteristics tDSOE SPIDS Assertion to Data Out Active 0 5 5 ns tDSOE 1 SPIDS Assertion to Data Out Active (SPI2) 0 8 9 ns tDSDHI SPIDS Deassertion to Data High Impedance 0 5 5.5 ns tDSDHI 1 SPIDS Deassertion to Data High Impedance (SPI2) 0 8.6 10 ns tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) 9.5 11.0 ns tHDSPIDS SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 2 × tPCLK ns tDSOV SPIDS Assertion to Data Out Valid (CPHASE = 0) 5 × tPCLK 5 × tPCLK ns 1The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, refer to the ADSP-2136x SHARC Processor Hardware Reference, “Serial Peripheral Interface Port” chapter. Rev. J | Page 44 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 35. SPI Slave Timing tSPICHS tSPICLS tSPICLKS tHDS tSDPPW tSDSCO tDSOE tDDSPIDS tDDSPIDS tDSDHI tHDSPIDS tSSPIDS tHSPIDS tDSDHI tDSOV tHSPIDS tHDSPIDS SPIDS (INPUT) MISO (OUTPUT) MOSI (INPUT) MISO (OUTPUT) MOSI (INPUT) CPHASE = 1 CPHASE = 0 SPICLK (CP = 0, CP = 1) (INPUT) tSSPIDS ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 45 of 60 | July 2013 JTAG Test Access Port and Emulation Table 41. JTAG Test Access Port and Emulation Parameter Min Max Unit Timing Requirements tTCK TCK Period tCK ns tSTAP TDI, TMS Setup Before TCK High 5 ns tHTAP TDI, TMS Hold After TCK High 6 ns tSSYS 1 System Inputs Setup Before TCK High 7 ns tHSYS 1 System Inputs Hold After TCK High 18 ns tTRSTW TRST Pulse Width 4 × tCK ns Switching Characteristics tDTDO TDO Delay from TCK Low 7 ns tDSYS 2 System Outputs Delay After TCK Low tCK ÷ 2 + 7 ns 1 System Inputs = ADDR15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, and FLAG3–0. 2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, ADDR15–0, RD, WR, FLAG3–0, EMU, and ALE. Figure 36. IEEE 1149.1 JTAG Test Access Port TCK TMS TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS tTCK tSTAP tHTAP tDTDO tSSYS tHSYS tDSYS Rev. J | Page 46 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 OUTPUT DRIVE CURRENTS Figure 37 shows typical I-V characteristics for the output drivers of the processor. The curves represent the current drive capability of the output drivers as a function of output voltage. TEST CONDITIONS The ac signal specifications (timing parameters) appear in Table 12 on Page 20 through Table 41 on Page 45. These include output disable time, output enable time, and capacitive loading. The timing specifications for the SHARC apply for the voltage reference levels in Figure 38. Timing is measured on signals when they cross the 1.5 V level as described in Figure 39. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V. CAPACITIVE LOADING Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 38). Figure 42 shows graphically how output delays and holds vary with load capacitance. The graphs of Figure 40, Figure 41, and Figure 42 may not be linear outside the ranges shown for Typical Output Delay versus Load Capacitance and Typical Output Rise Time (20% to 80%, V = Min) versus Load Capacitance. Figure 37. ADSP-2136x Typical Drive Figure 38. Equivalent Device Loading for AC Measurements (Includes All Fixtures) Figure 39. Voltage Reference Levels for AC Measurements SWEEP (VDDEXT) VOLTAGE (V) -20 0 0.5 1.5 2.5 3.5 0 -40 -30 20 40 -10 SOURCE (VDDEXT) CURRENT (mA) VOL 3.11V, +125°C 3.3V, +25°C 3.47V, -45°C 30 VOH 10 3.11V, +125°C 3.3V, +25°C 3.47V, -45°C 1.0 2.0 3.0 TO OUTPUT PIN 􀀘􀀓􀈍 VLOAD 30pF INPUT 1.5V OR OUTPUT 1.5V Figure 40. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Max) Figure 41. Typical Output Rise/Fall Time (20% to 80%, VDDEXT = Min) LOAD CAPACITANCE (pF) 8 0 0 100 250 12 4 2 10 6 RISE AND FALL TIMES (ns) 50 150 200 FALL y = 0.0467x + 1.6323 y = 0.045x + 1.524 RISE LOAD CAPACITANCE (pF) 12 0 50 100 150 200 250 10 8 6 4 RISE AND FALL TIMES (ns) 2 0 RISE y = 0.049x + 1.5105 FALL y = 0.0482x + 1.4604 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 47 of 60 | July 2013 THERMAL CHARACTERISTICS The processor is rated for performance over the temperature range specified in Operating Conditions on Page 14. Table 42 through Table 44 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. Test board and thermal via design comply with JEDEC standards JESD51-9 (BGA) and JESD51-5 (LQFP_EP). The junction-to-case measurement complies with MIL-STD-883. All measurements use a 2S2P JEDEC test board. Industrial applications using the BGA package require thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-9 for printed circuit board thermal ball land and thermal via design information. Industrial applications using the LQFP_EP package require thermal trace squares and thermal vias, to an embedded ground plane, in the PCB. Refer to JEDEC standard JESD51-5 for more information. To determine the junction temperature of the device while on the application PCB, use: where: TJ = junction temperature (°C) TT = case temperature (°C) measured at the top center of the package ΨJT = junction-to-top (of package) characterization parameter is the typical value from Table 42 through Table 44. PD = power dissipation. See the Engineer-to-Engineer Note “Estimating Power for the ADSP-21362 SHARC Processors” (EE-277) for more information. Values of θJA are provided for package comparison and PCB design considerations. Values of θJC are provided for package comparison and PCB design considerations when an exposed pad is required. Note that the thermal characteristics values provided in Table 42 through Table 44 are modeled values. Figure 42. Typical Output Delay or Hold versus Load Capacitance (at Ambient Temperature) LOAD CAPACITANCE (pF) 0 50 100 150 200 10 8 OUTPUT DELAY OR HOLD (ns) 6 0 4 2 -2 y = 0.0488x - 1.5923 -4 TJ TT JT PD = +    Table 42. Thermal Characteristics for BGA (No Thermal vias in PCB) Parameter Condition Typical Unit θJA Airflow = 0 m/s 25.40 °C/W θJMA Airflow = 1 m/s 21.90 °C/W θJMA Airflow = 2 m/s 20.90 °C/W θJC 5.07 °C/W ΨJT Airflow = 0 m/s 0.140 °C/W ΨJMT Airflow = 1 m/s 0.330 °C/W ΨJMT Airflow = 2 m/s 0.410 °C/W Table 43. Thermal Characteristics for BGA (Thermal vias in PCB) Parameter Condition Typical Unit θJA Airflow = 0 m/s 23.40 °C/W θJMA Airflow = 1 m/s 20.00 °C/W θJMA Airflow = 2 m/s 19.20 °C/W θJC 5.00 °C/W ΨJT Airflow = 0 m/s 0.130 °C/W ΨJMT Airflow = 1 m/s 0.300 °C/W ΨJMT Airflow = 2 m/s 0.360 °C/W Table 44. Thermal Characteristics for LQFP_EP (with Exposed Pad Soldered to PCB) Parameter Condition Typical Unit θJA Airflow = 0 m/s 16.80 °C/W θJMA Airflow = 1 m/s 14.20 °C/W θJMA Airflow = 2 m/s 13.50 °C/W θJC 7.25 °C/W ΨJT Airflow = 0 m/s 0.51 °C/W ΨJMT Airflow = 1 m/s 0.72 °C/W ΨJMT Airflow = 2 m/s 0.80 °C/W Rev. J | Page 48 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 144-LEAD LQFP_EP PIN CONFIGURATIONS The following table shows the processor’s pin names and, when applicable, their default function after reset in parentheses. Table 45. LQFP_EP Pin Assignments Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. VDDINT 1 VDDINT 37 VDDEXT 73 GND 109 CLK_CFG0 2 GND 38 GND 74 VDDINT 110 CLK_CFG1 3 RD 39 VDDINT 75 GND 111 BOOT_CFG0 4 ALE 40 GND 76 VDDINT 112 BOOT_CFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113 GND 6 AD14 42 DAI_P11 (SD3A) 78 VDDINT 114 VDDEXT 7 AD13 43 DAI_P12 (SD3B) 79 GND 115 GND 8 GND 44 DAI_P13 (SCLK3) 80 VDDEXT 116 VDDINT 9 VDDEXT 45 DAI_P14 (SFS3) 81 GND 117 GND 10 AD12 46 DAI_P15 (SD4A) 82 VDDINT 118 VDDINT 11 VDDINT 47 VDDINT 83 GND 119 GND 12 GND 48 GND 84 VDDINT 120 VDDINT 13 AD11 49 GND 85 RESET 121 GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122 FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123 FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 VDDINT 124 AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK5) 89 SPICLK 125 GND 18 VDDINT 54 VDDINT 90 MISO 126 VDDINT 19 GND 55 GND 91 MOSI 127 GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128 VDDEXT 21 DAI_P3 (SCLK0) 57 VDDEXT 93 VDDINT 129 GND 22 GND 58 DAI_P20 (SFS5) 94 VDDEXT 130 VDDINT 23 VDDEXT 59 GND 95 Avdd 131 AD6 24 VDDINT 60 VDDINT 96 Avss 132 AD5 25 GND 61 FLAG2 97 GND 133 AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 RESETOUT 134 VDDINT 27 DAI_P5 (SD1A) 63 VDDINT 99 EMU 135 GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136 AD3 29 DAI_P7 (SCLK1) 65 VDDINT 101 TDI 137 AD2 30 VDDINT 66 GND 102 TRST 138 VDDEXT 31 GND 67 VDDINT 103 TCK 139 GND 32 VDDINT 68 GND 104 TMS 140 AD1 33 GND 69 VDDINT 105 GND 141 AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142 WR 35 DAI_P9 (SD2A) 71 VDDINT 107 XTAL 143 VDDINT 36 VDDINT 72 VDDINT 108 VDDEXT 144 GND 145* *The ePAD is electrically connected to GND inside the chip (see Figure 43 and Figure 44), therefore connecting the pad to GND is optional. For better thermal performance the ePAD should be soldered to the board and thermally connected to the GND plane with vias. ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 49 of 60 | July 2013 Figure 43 shows the top view of the 144-lead LQFP_EP pin configuration. Figure 44 shows the bottom view of the 144-lead LQFP_EP lead configuration. Figure 43. 144-Lead LQFP_EP Lead Configuration (Top View) Figure 44. 144-Lead LQFP_EP Lead Configuration (Bottom View) LEAD 1 LEAD 36 LEAD 108 LEAD 73 LEAD 144 LEAD 109 LEAD 37 LEAD 72 LEAD 1 INDICATOR ADSP-2136x 144-LEAD LQFP_EP TOP VIEW LEAD 108 LEAD 73 LEAD 1 LEAD 36 LEAD 109 LEAD 144 LEAD 72 LEAD 37 LEAD 1 INDICATOR GND PAD (LEAD 145) ADSP-2136x 144-LEAD LQFP_EP BOTTOM VIEW Rev. J | Page 50 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 136-BALL BGA PIN CONFIGURATIONS The following table shows the processor’s ball names and, when applicable, their default function after reset in parentheses. Table 46. BGA Pin Assignments Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. CLK_CFG0 A01 CLK_CFG1 B01 BOOT_CFG1 C01 VDDINT D01 XTAL A02 GND B02 BOOT_CFG0 C02 GND D02 TMS A03 VDDEXT B03 GND C03 GND D04 TCK A04 CLKIN B04 GND C12 GND D05 TDI A05 TRST B05 GND C13 GND D06 RESETOUT A06 AVSS B06 VDDINT C14 GND D09 TDO A07 AVDD B07 GND D10 EMU A08 VDDEXT B08 GND D11 MOSI A09 SPICLK B09 GND D13 MISO A10 RESET B10 VDDINT D14 SPIDS A11 VDDINT B11 VDDINT A12 GND B12 GND A13 GND B13 GND A14 GND B14 VDDINT E01 FLAG1 F01 AD7 G01 AD6 H01 GND E02 FLAG0 F02 VDDINT G02 VDDEXT H02 GND E04 GND F04 VDDEXT G13 DAI_P18 (SD5B) H13 GND E05 GND F05 DAI_P19 (SCLK5) G14 DAI_P17 (SD5A) H14 GND E06 GND F06 GND E09 GND F09 GND E10 GND F10 GND E11 GND F11 GND E13 FLAG2 F13 FLAG3 E14 DAI_P20 (SFS5) F14 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 51 of 60 | July 2013 Figure 45 and Figure 46 show BGA pin assignments from the bottom and top, respectively. Note: Use the center block of ground pins to provide thermal pathways to your printed circuit board’s ground plane. AD5 J01 AD3 K01 AD2 L01 AD0 M01 AD4 J02 VDDINT K02 AD1 L02 WR M02 GND J04 GND K04 GND L04 GND M03 GND J05 GND K05 GND L05 GND M12 GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13 GND J09 GND K09 GND L09 DAI_P13 (SCLK3) M14 GND J10 GND K10 GND L10 GND J11 GND K11 GND L11 VDDINT J13 GND K13 GND L13 DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS3) L14 AD15 N01 AD14 P01 ALE N02 AD13 P02 RD N03 AD12 P03 VDDINT N04 AD11 P04 VDDEXT N05 AD10 P05 AD8 N06 AD9 P06 VDDINT N07 DAI_P1 (SD0A) P07 DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08 VDDEXT N09 DAI_P5 (SD1A) P09 DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10 VDDINT N11 DAI_P7 (SCLK1) P11 VDDINT N12 DAI_P8 (SFS1) P12 GND N13 DAI_P9 (SD2A) P13 DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14 Table 46. BGA Pin Assignments (Continued) Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Rev. J | Page 52 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Figure 45. BGA Pin Assignments (Bottom View, Summary) AVSS VDDINT VDDEXT I/O SIGNALS GND AVDD KEY 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P N M L K J H G F E D C B A Figure 46. BGA Pin Assignments (Top View, Summary) AVSS VDDINT VDDEXT I/O SIGNALS GND AVDD KEY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P N M L K J H G F E D C B A ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 53 of 60 | July 2013 PACKAGE DIMENSIONS The processor is available in 136-ball BGA and 144-lead exposed pad (LQFP_EP) packages. Figure 47. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP1] (SW-144-1) Dimensions shown in millimeters 1For information relating to the exposed pad on the SW-144-1 package, see the table endnote on Page 48. COMPLIANT TO JEDEC STANDARDS MS-026-BFB-HD 0.27 0.22 0.17 0.75 0.60 0.45 0.50 BSC LEAD PITCH 20.20 20.00 SQ 19.80 22.20 22.00 SQ 21.80 EXPOSED* PAD 1 36 1 36 37 73 72 72 37 108 73 108 144 109 109 144 PIN 1 1.60 MAX SEATING PLANE *EXPOSED PAD IS COINCIDENT WITH BOTTOM SURFACE AND DOES NOT PROTRUDE BEYOND IT. EXPOSED PAD IS CENTERED. 8.80 SQ 0.15 0.10 0.05 0.08 COPLANARITY 0.20 0.15 0.09 1.45 1.40 1.35 7° 3.5° 0° VIEW A ROTATED 90° CCW TOP VIEW (PINS DOWN) BOTTOM VIEW (PINS UP) VIEW A Rev. J | Page 54 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SURFACE-MOUNT DESIGN Table 47 is provided as an aid to PCB design. For industry standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Figure 48. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-136-1) Dimensions shown in millimeters 0.25 MIN *0.50 0.45 0.40 1.31 1.21 1.70 MAX 1.10 A B C D EF G J H KL M 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NP 12.10 12.00 SQ 11.90 10.40 BSC SQ *COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1 WITH EXCEPTION TO BALL DIAMETER. COPLANARITY 0.12 BALL DIAMETER 0.80 BSC DETAIL A A1 BALL A1 BALL CORNER CORNER DETAIL A TOP VIEW BOTTOM VIEW SEATING PLANE Table 47. BGA Data for Use with Surface-Mount Design Package Package Ball Attach Type Package Solder Mask Opening Package Ball Pad Size 136-Ball CSP_BGA (BC-136-1) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 55 of 60 | July 2013 AUTOMOTIVE PRODUCTS Some ADSP-2136x models are available for automotive applications with controlled manufacturing. Note that these special models may have specifications that differ from the general release models. The automotive grade products shown in Table 48 are available for use in automotive applications. Contact your local ADI account representative or authorized ADI product distributor for specific product ordering information. Note that all automotive products are RoHS compliant. Table 48. Automotive Products Model Notes Temperature Range1 Instruction Rate On-Chip SRAM ROM Package Description Package Option AD21362WBBCZ1xx 2 –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 AD21362WBSWZ1xx 2 –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21362WYSWZ2xx 2 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21363WBBCZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 AD21363WBSWZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21363WYSWZ2xx –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21364WBBCZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 AD21364WBSWZ1xx –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21364WYSWZ2xx –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21365WBSWZ1xxA 2, 3, 4 –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21365WBSWZ1xxF 2, 3, 4 –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21365WYSWZ2xxA 2, 3, 4 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21366WBBCZ1xxA 3, 4 –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 AD21366WBSWZ1xxA 3, 4 –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 AD21366WYSWZ2xxA 3, 4 –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 1 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ) specification which is the only temperature specification. 2 License from DTLA required for these products. 3Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/sharc. 4 License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products. Rev. J | Page 56 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ORDERING GUIDE Model1 1 Z = RoHS compliant part. Notes Temperature Range2 2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 14 for junction temperature (TJ) specification which is the only temperature specification. Instruction Rate On-Chip SRAM ROM Package Description Package Option ADSP-21363KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21363BBC-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21363BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21363YSWZ-2AA 3 3 License from Dolby Laboratories, Inc., and Digital Theater Systems (DTS) required for these products. –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21364KBCZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21364KSWZ-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21364BBCZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21364BSWZ-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21364YSWZ-2AA –40°C to +105°C 200 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21366KBCZ-1AR 3, 4, 5 4Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/sharc. 5 R = Tape and reel. 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21366KBCZ-1AA 3, 4 0°C to +70°C 333 MHz 3M Bit 4M Bit 136-Ball CSP_BGA BC-136-1 ADSP-21366KSWZ-1AA 3, 4 0°C to +70°C 333 MHz 3M Bit 4M Bit 144-Lead LQFP_EP SW-144-1 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 57 of 60 | July 2013 Rev. J | Page 58 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 Rev. J | Page 59 of 60 | July 2013 Rev. J | Page 60 of 60 | July 2013 ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06359-0-7/13(J) Product family data sheet Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. CLD-DS56 Rev 4 Cree® XLamp® XP-E2 LEDs Product Description The XLamp XP-E2 LED builds on the unprecedented performance of the original XP-E by increasing lumen output up to 20% while providing a single die LED point source for precise optical control. The XP‑E2 LED shares the same footprint as the original XP‑E, providing a seamless upgrade path to more lumens and/or greater efficiency while shortening the design cycle for existing XP customers. XLamp XP-E2 LEDs are the ideal choice for lighting applications where high light output and maximum efficacy are required, such as LED retrofit lamps, outdoor, portable, indoor directional, emergency vehicle or architectural. FEATURES • Available in white, outdoor white, 80-CRI, 85-CRI, 90-CRI white, royal blue, blue, green, amber, red-orange & red • ANSI-compatible chromaticity bins • White binned at 85 °C • Maximum drive current: 1 A • Low thermal resistance: as low as 5 °C/W • Wide viewing angle: 110°-135° • Unlimited floor life at ≤ 30 °C/85% RH • Reflow solderable - JEDEC J-STD-020C compatible • Electrically neutral thermal path • UL-recognized component (E349212) www.cree.com/Xlamp Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 Table of Contents Characteristics........................... 2 Flux Characteristics - White......... 3 Flux Characteristics - Color.......... 4 Relative Spectral Power Distribution............................... 6 Relative Flux vs. Junction Temperature.............................. 7 Electrical Characteristics.............. 8 Relative Flux vs. Current............. 9 Relative Chromaticity vs. Current and Temperature.......................10 Typical Spatial Distribution..........11 Thermal Design.........................12 Reflow Soldering Characteristics..13 Notes.......................................14 Mechanical Dimensions..............15 Tape and Reel...........................16 Packaging.................................17 Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 2 xlamp xp-e2 leds Characteristics Characteristics Unit Minimum Typical Maximum Thermal resistance, junction to solder point - white, royal blue, blue °C/W 9 Thermal resistance, junction to solder point - green °C/W 15 Thermal resistance, junction to solder point - amber °C/W 7 Thermal resistance, junction to solder point - red-orange, red °C/W 5 Viewing angle (FWHM) - white degrees 110 Viewing angle (FWHM) - royal blue, blue, green degrees 135 Viewing angle (FWHM) - amber, red-orange, red degrees 130 Temperature coefficient of voltage - white mV/°C -2.3 Temperature coefficient of voltage - royal blue, blue mV/°C -3.3 Temperature coefficient of voltage - green mV/°C -3.8 Temperature coefficient of voltage - amber, red-orange, red mV/°C -1.8 ESD withstand voltage (HBM per Mil-Std-883D)- white, royal blue, blue, green V 8000 ESD classification (HBM per Mil-Std-883D) - amber, red-orange, red Class 2 DC forward current mA 1000 Reverse voltage V 5 Forward voltage (@ 350 mA, 85 °C) - white V 2.9 3.25 Forward voltage (@ 700 mA, 85 °C) - white 3.05 Forward voltage (@ 1000 mA, 85 °C) - white 3.15 Forward voltage (@ 350 mA, 25 °C) - royal blue, blue V 3.1 3.5 Forward voltage (@ 350 mA, 25 °C) - green V 3.2 3.6 Forward voltage (@ 350 mA, 25 °C) - amber, red-orange, red V 2.2 2.6 Forward voltage (@ 1000 mA, 25 °C) - royal blue, blue V 3.4 Forward voltage (@ 1000 mA, 25 °C) - green V 3.7 Forward voltage (@ 1000 mA, 25 °C) - amber, red-orange, red V 2.65 LED junction temperature °C 150 Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 3 xlamp xp-e2 leds Flux Characteristics (TJ = 85 °C) - White The following table provides several base order codes for XLamp XP-E2 LEDs. It is important to note that the base order codes listed here are a subset of the total available order codes for the product family. For more order codes, as well as a complete description of the order-code nomenclature, please consult the XLamp XP Family Binning and Labeling document. Color CCT Range Base Order Codes Min. Luminous Flux (lm) @ 350 mA Calculated Minimum Luminous Flux (lm)** @ 85 °C Order Code Min. Max. Group Flux (lm) @ 85 °C Flux (lm) @ 25 °C* 700 mA 1.0 A Cool White 5000 K 10,000 K Q4 100 116 171 218 XPEBWT-L1-0000-00C51 Q5 107 124 183 233 XPEBWT-L1-0000-00D51 R2 114 132 195 249 XPEBWT-L1-0000-00E51 R3 122 142 209 266 XPEBWT-L1-0000-00F51 Outdoor White 4000 K 5300 K Q4 100 116 171 218 XPEBWT-01-0000-00CC2 Q5 107 124 183 233 XPEBWT-01-0000-00DC2 R2 114 132 195 249 XPEBWT-01-0000-00EC2 R3 122 142 209 266 XPEBWT-01-0000-00FC2 Neutral White 3700 K 5300 K Q4 100 116 171 218 XPEBWT-L1-0000-00CE4 Q5 107 124 183 233 XPEBWT-L1-0000-00DE4 R2 114 132 195 249 XPEBWT-L1-0000-00EE4 80-CRI White 2200 K 4300 K Q2 87.4 101 150 191 XPEBWT-H1-0000-00AE7 Q3 93.9 109 161 205 XPEBWT-H1-0000-00BE7 Warm White 2200 K 3700 K Q2 87.4 101 150 191 XPEBWT-L1-0000-00AE7 Q3 93.9 109 161 205 XPEBWT-L1-0000-00BE7 Q4 100 116 171 218 XPEBWT-L1-0000-00CE7 85-CRI White 2600 K 3200 K P2 67.2 78.0 115 147 XPEBWT-P1-0000-007E7 P3 73.9 85.7 127 161 XPEBWT-P1-0000-008E7 P4 80.6 93.5 138 176 XPEBWT-P1-0000-009E7 Q2 87.4 101 150 191 XPEBWT-P1-0000-00AE7 90-CRI White 2600 K 3200 K P2 67.2 78.0 115 147 XPEBWT-U1-0000-007E7 P3 73.9 85.7 127 161 XPEBWT-U1-0000-008E7 P4 80.6 93.5 138 176 XPEBWT-U1-0000-009E7 Notes: • Cree maintains a tolerance of ± 7% on flux and power measurements, ±0.005 on chromaticity (CCx, CCy) measurements and ±2 on CRI measurements. • Typical CRI for Cool White (5000 K – 10,000 K CCT) is 70. • Typical CRI for Neutral White (3700 K – 5300 K CCT) is 75. • Typical CRI for Outdoor White (4000 K - 5300 K CCT) is 70. • Typical CRI for Warm White (2200 K – 3700 K CCT) is 80. • Minimum CRI for 80-CRI White is 80. • Minimum CRI for 85-CRI White is 85. • Minimum CRI for 90-CRI White is 90. * Flux values @ 25 °C are calculated and for reference only. ** Calculated flux values at 700 mA and 1 A are for reference only. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 4 xlamp xp-e2 leds Flux Characteristics (TJ = 25 °C) - Color The following table provides several base order codes for XLamp XP-E2 color LEDs. It is important to note that the base order codes listed here are a subset of the total available order codes for the product family. For more order codes, as well as a complete description of the order-code nomenclature, please consult the XLamp XP Family Binning and Labeling document. Color Minimum Radiant Flux @ 350 mA Dominant Wavelength Range Order Codes, Group Flux (mW) Min. Max. Group DWL (nm) Group DWL (nm) Royal Blue 30 450 D3 450 D5 465 XPEBRY-L1-0000-00J01 31 475 D3 450 D5 465 XPEBRY-L1-0000-00K01 32 500 D3 450 D5 465 XPEBRY-L1-0000-00L01 33 525 D3 450 D5 465 XPEBRY-L1-0000-00M01 34 550 D3 450 D5 465 XPEBRY-L1-0000-00N01 35 575 D3 450 D5 465 XPEBRY-L1-0000-00P01 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Blue B3 465 B6 485 K2 30.6 XPEBBL-L1-0000-00Y01 K3 35.2 XPEBBL-L1-0000-00Z01 M2 39.8 XPEBBL-L1-0000-00201 M3 45.7 XPEBBL-L1-0000-00301 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Green G2 520 G4 535 Q2 87.4 XPEBGR-L1-0000-00A01 Q3 93.9 XPEBGR-L1-0000-00B01 Q4 100 XPEBGR-L1-0000-00C01 Q5 107 XPEBGR-L1-0000-00D01 R2 114 XPEBGR-L1-0000-00E01 R3 122 XPEBGR-L1-0000-00F01 Note: Cree maintains a tolerance of ± 7% on flux and power measurements and ± 1 nm on dominant wavelength measurements. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 5 xlamp xp-e2 leds Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Amber A2 585 A3 595 N4 62.0 XPEBAM-L1-0000-00601 P2 67.2 XPEBAM-L1-0000-00701 P3 73.9 XPEBAM-L1-0000-00801 P4 80.6 XPEBAM-L1-0000-00901 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Red- Orange O3 610 O4 620 P2 67.2 XPEBRO-L1-0000-00701 P3 73.9 XPEBRO-L1-0000-00801 P4 80.6 XPEBRO-L1-0000-00901 Q2 87.4 XPEBRO-L1-0000-00A01 Q3 93.9 XPEBRO-L1-0000-00B01 Color Dominant Wavelength Range Base Order Codes Min. Luminous Flux Min. Max. (lm) @ 350 mA Order Code Group DWL (nm) Group DWL (nm) Group Flux (lm) Red R2 620 R3 630 N3 56.8 XPEBRD-L1-0000-00501 N4 62.0 XPEBRD-L1-0000-00601 P2 67.2 XPEBRD-L1-0000-00701 P3 73.9 XPEBRD-L1-0000-00801 Note: Cree maintains a tolerance of ± 7% on flux and power measurements and ± 1 nm on dominant wavelength measurements. Flux Characteristics (TJ = 25 °C) - Color (Continued) Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 6 xlamp xp-e2 leds Relative Spectral Power Distribution Relative Spectral Power 0 10 20 30 40 50 60 70 80 90 100 380 430 480 530 580 630 680 730 780 Relative Radiant Power (%) Wavelength (nm) Cool White Warm White Relative Spectral Power 0 20 40 60 80 100 380 430 480 530 580 630 680 730 780 Relative Radiant Power (%) Wavelength (nm) Royal Blue Blue Green Amber Red-Orange Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 7 xlamp xp-e2 leds Relative Flux vs. Junction Temperature (IF = 350 mA) Relative Flux Output vs. Junction Temperature 0 20 40 60 80 100 120 25 50 75 100 125 150 Relative Luminous Flux (%) Junction Temperature (ºC) White Relative Flux Output vs. Junction Temperature 0 10 20 30 40 50 60 70 80 90 100 25 50 75 100 125 150 Relative Radiant Flux (%) Junction Temperature (ºC) Royal Blue Relative Flux Output vs. Junction Temperature 0 10 20 30 40 50 60 70 80 90 100 25 50 75 100 125 150 Relative Luminous Flux (%) Junction Temperature (ºC) Blue Green Amber Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 8 xlamp xp-e2 leds Electrical Characteristics (TJ = 85 °C) Electrical Characteristics (TJ = 25 °C) Electrical Characteristics (Tj = 25ºC) 0 100 200 300 400 500 600 700 800 900 1000 2.7 2.8 2.9 3.0 3.1 3.2 Forward Current (mA) Forward Voltage (V) White Electrical Characteristics (Tj = 85ºC) 0 100 200 300 400 500 600 700 800 900 1000 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 Forward Current (mA) Forward Voltage (V) Royal Blue, Blue Green Amber, Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 9 xlamp xp-e2 leds Relative Flux vs. Current (TJ = 85 °C) Relative Flux vs. Current (TJ = 25 °C) Relative Intensity vs. Current (Tj = 85ºC) 0 50 100 150 200 250 0 100 200 300 400 500 600 700 800 900 1000 Relative Luminous Flux (%) Forward Current (mA) White Relative Intensity vs. Current (Tj = 85ºC) 0 50 100 150 200 250 0 100 200 300 400 500 600 700 800 900 1000 Relative Radiant Flux (%) Forward Current (mA) Royal Blue Relative Intensity vs. Current (Tj = 85ºC) 0 50 100 150 200 250 300 0 100 200 300 400 500 600 700 800 900 1000 Relative Luminous Flux (%) Forward Current (mA) Blue Green Amber Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 10 xlamp xp-e2 leds Relative Chromaticity vs. Current and Temperature - Warm White* * Warm White XLamp XP-E2 LEDs have a typical CRI of 80. Relative Chromaticity Vs. Current, WW -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0 100 200 300 400 500 600 700 800 900 1000 Current (mA) ΔCCx ΔCCy T J = 85 °C Relative Chromaticity Vs. Temperature WW -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 0.015 0.020 0 20 40 60 80 100 120 140 160 Tsp (°C) ΔCCx ΔCCy I F = 350 mA Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 11 xlamp xp-e2 leds Typical Spatial Distribution Typical Spatial Radiation Pattern 0 20 40 60 80 100 -90 -70 -50 -30 -10 10 30 50 70 90 Relative Luminous Intensity (%) Angle (°) White Typical Spatial Radiation Pattern 0 20 40 60 80 100 -90 -70 -50 -30 -10 10 30 50 70 90 Relative Luminous Intensity (%) Angle (º) Royal Blue, Blue, Green Amber, Red-Orange, Red Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 12 xlamp xp-e2 leds Thermal Design The maximum forward current is determined by the thermal resistance between the LED junction and ambient. It is crucial for the end product to be designed in a manner that minimizes the thermal resistance from the solder point to ambient in order to optimize lamp life and optical characteristics. White R oyal Blue, Blue Green A mber, Red-Orange, Red 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Thermal Design - royal blue - same as blue 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Thermal Design - amber, red-orange, red 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 10°C/W Rj-a = 15°C/W Rj-a = 20°C/W Rj-a = 25°C/W Thermal Design - green 0 200 400 600 800 1000 1200 0 20 40 60 80 100 120 140 Maximum Current (mA) Ambient Temperature (ºC) Rj-a = 20°C/W Rj-a = 25°C/W Rj-a = 30°C/W Rj-a = 35°C/W Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 13 xlamp xp-e2 leds Reflow Soldering Characteristics In testing, Cree has found XLamp XP-E2 LEDs to be compatible with JEDEC J-STD-020C, using the parameters listed below. As a general guideline, Cree recommends that users follow the recommended soldering profile provided by the manufacturer of solder paste used. Note that this general guideline may not apply to all PCB designs and configurations of reflow soldering equipment. Profile Feature Lead-Based Solder Lead-Free Solder Average Ramp-Up Rate (Tsmax to Tp) 3 °C/second max. 3 °C/second max. Preheat: Temperature Min (Tsmin) 100 °C 150 °C Preheat: Temperature Max (Tsmax) 150 °C 200 °C Preheat: Time (tsmin to tsmax) 60-120 seconds 60-180 seconds Time Maintained Above: Temperature (TL) 183 °C 217 °C Time Maintained Above: Time (tL) 60-150 seconds 60-150 seconds Peak/Classification Temperature (Tp) 215 °C 260 °C Time Within 5 °C of Actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-Down Rate 6 °C/second max. 6 °C/second max. Time 25 °C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package, measured on the package body surface. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 14 xlamp xp-e2 leds Notes Lumen Maintenance Projections Cree now uses standardized IES LM-80-08 and TM-21-11 methods for collecting long-term data and extrapolating LED lumen maintenance. For information on the specific LM-80 data sets available for this LED, refer to the public LM-80 results document at www.cree.com/xlamp_app_notes/LM80_results. Please read the XLamp Long-Term Lumen Maintenance application note at www.cree.com/xlamp_app_notes/lumen_ maintenance for more details on Cree’s lumen maintenance testing and forecasting. Please read the XLamp Thermal Management application note at www.cree.com/xlamp_app_notes/thermal_management for details on how thermal design, ambient temperature, and drive current affect the LED junction temperature. Moisture Sensitivity In testing, Cree has found XLamp XP-E2 LEDs to have unlimited floor life in conditions ≤ 30 ºC/85% relative humidity (RH). Moisture testing included a 168-hour soak at 85 ºC/85% RH followed by 3 reflow cycles, with visual and electrical inspections at each stage. Cree recommends keeping XLamp LEDs in their sealed moisture-barrier packaging until immediately prior to use. Cree also recommends returning any unused LEDS to the resealable moisture-barrier bag and closing the bag immediately after use. UL Recognized Component Level 4 enclosure consideration. The LED package or a portion thereof has been investigated as a fire and electrical enclosure per ANSI/UL 8750. Vision Advisory Claim WARNING: Do not look at exposed lamp in operation. Eye injury can result. See LED Eye Safety at www.cree.com/ xlamp_app_notes/led_eye_safety. Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 15 xlamp xp-e2 leds Mechanical Dimensions All measurements are ±.13 mm unless otherwise indicated. Anode Anode THIRD ANGLE PROJECTION A B C D 6 5 4 3 6 5 4 3 UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT CONTAINED WITHIN ARE THE PROPRIETARY AND CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION OF CREE INC. NOTICE X° ± .5 .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS .XX ± .25 .XXX ± .125 X° ± .5 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 2.36 RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION 6 5 4 3 2 PERSON WITHOUT THE WRITTEN CONSENT COPIED, REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL. THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: .50 .50 .40 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 3.30 .50 2.30 3.30 1.30 2.36 OUTLINE D. CRONIN 07/19/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DRAWING DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION 6 5 4 3 2 PERSON WITHOUT THE WRITTEN CONSENT REPRODUCED OR DISCLOSED TO ANY INFORMATION OF CREE, INC. THIS PLOT ARE THE PROPRIETARY AND THIS PLOT AND THE INFORMATION NOTICE X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: .50 1.30 3.30 3.30 1.15 .65 1.65 .50 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 3.30 .50 2.30 3.30 1.30 2.36 OUTLINE D. CRONIN 07/19/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION 5 4 3 2 WITHOUT THE WRITTEN CONSENT REPRODUCED OR DISCLOSED TO ANY OF CREE, INC. THIS PLOT PROPRIETARY AND PLOT AND THE INFORMATION X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: .50 1.30 3.30 3.30 1.15 .65 1.65 1.20 .60 .60 3.20 1.60 3.20 .40 .40 .40 3.45 3.45 R1.53 .65 .83 3.30 .50 2.30 3.30 1.30 2.36 2610-OUTLINE DRAWING D. CRONIN 07/19/12 REVISONS REV DESCRIPTION RECOMMENDED PCB SOLDER PAD RECOMMENDED STENCIL PATTERN (HATCHED AREA IS OPENING) SIZE TITLE OF REV. SHEET C DRAWING NO. DATE DATE DATE CHECK FINAL PROTECTIVE FINISH MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION SCALE 3 2 1 A B C Phone (919) 313-5300 Fax (919) 313-5558 4600 Silicon Drive Durham, N.C 27703 X° ± .5 ° .XXX ± .25 .XX ± .75 .X ± 1.5 FOR SHEET METAL PARTS ONLY .XX ± .25 .XXX ± .125 X° ± .5 ° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND AFTER FINISH. TOLERANCE UNLESS SPECIFIED: SURFACE FINISH: 1.6 1.20 .60 3.20 1.60 3.20 .40 .65 1.30 22.000 1 /1 2610-00029 A OUTLINE DRAWING XPE G2 D. CRONIN 07/19/12 RECOMMENDED STENCIL PATTERN AREA IS OPENING) Top View Side View Bottom View Recommended PCB Solder Pad Recommended Stencil Pattern Hatched Area is Opening Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 16 xlamp xp-e2 leds Tape and Reel All Cree carrier tapes conform to EIA-481D, Automated Component Handling Systems Standard. All dimensions in mm. Loaded Pockets (1,000 Lamps) Leader 400mm (min) of empty pockets with at least 100mm sealed by tape (50 empty pockets min.) Trailer 160mm (min) of empty pockets sealed with tape (20 pockets min.) END START Cathode Side Anode Side (denoted by + and circle) 2.5±.1 1.5±.1 8.0±.1 4.0±.1 1.75±.10 12.0 .0 +.3 DETAIL B SCALE 2 : 1 13mm 7" Cover Tape Pocket Tape User Feed Direction User Feed Direction 13 61 12.40 0 +2.00 MEASURED AT HUB 12.40 MEASURED AT INSIDE EDGE 16.40 TITLE DATE DATE DATE CHECK MATERIAL APPROVED DRAWN BY THIRD ANGLE PROJECTION .X ± 0.3 .XX ± .13 X° ± 1° UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS & BEFORE FINISH. TOLERANCE UNLESS SPECIFIED: A B C D 6 5 4 3 2 1 A B C D Phone (919) 361-4770 4600 Silicon Drive Durham, N.C 27703 NOTICE CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT OF CREE, INC. Reel, 7" x 12mm Wide LIUDEZHI 2012/5/25 +/-0.5 190 ½öÓÃÓÚÆÀ¹À¡£ °æȨËùÓÐ (c) by Foxit Software Company, 2004 ÓÉ Foxit PDF Editor ±à¼- OD 7.5'' 13 61 12.40 0 +2.00 MEASURED AT HUB 12.40 16.40 B C D 6 5 4 3 2 1 B C D NOTICE CREE CONFIDENTIAL. THIS PLOT AND THE INFORMATION CONTAINED WITHIN ARE THE PROPRIETARY AND CONFIDENTIAL INFORMATION OF CREE, INC. THIS PLOT MAY NOT BE COPIED, REPRODUCED OR DISCLOSED TO ANY UNAUTHORIZED PERSON WITHOUT THE WRITTEN CONSENT OF CREE, INC. +/-0.5 190 ½öÓÃÓÚÆÀ¹À¡£ °æȨËùÓÐ (c) by Foxit Software Company, 2004 ÓÉ Foxit PDF Editor ±à¼- OD 7.5'' Y Y X X REF 0.59 F(III) D1 P1 1.5 MIN. Bo Ao R0.2 TYPICAL REF 4.375 Ko (IV) Other material available. (III) (II) (I) hole to centerline of pocket. Measured from centerline of sprocket holes is ± 0.20. Cumulative tolerance of 10 sprocket to centerline of pocket. Measured from centerline of sprocket hole SECTION Y-Y SECTION X-X ±0.05 Do 1.75 E1 REF R 2.24 Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 Y Y X X REF 0.59 W F(III) D1 P1 1.5 MIN. Bo Ao R0.2 TYPICAL REF 4.375 Ko (IV) Other material available. (III) (II) (I) hole to centerline of pocket. Measured from centerline of sprocket holes is ± 0.20. Cumulative tolerance of 10 sprocket to centerline of pocket. Measured from centerline of sprocket hole SECTION Y-Y SECTION X-X 2.0 ±0.05 (I) P2 1.55 ±0.05 Do 4.0 ±0.1 (II) Po 1.75 ±0.1 E1 T 0.30 ±0.05 REF R 2.24 Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 Y Y D1 1.5 MIN. Bo R0.2 TYPICAL REF 4.375 Ko SECTION Y-Y 0.05 REF Ko 2.40 +0.0/-0.1 3.70 1 W F P +/- 0.05 +/- 0.1 +0.3/-0.1 5.50 8.00 12.00 Ao 3.70 +/- 0.1 Bo +/- 0.1 CATHODE SIDE ANODE SIDE Copyright © 2012-2013 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree®, the Cree logo and XLamp® are registered trademarks of Cree, Inc. 17 xlamp xp-e2 leds Packaging Patent Label (on bottom of box) Label with Cree Bin Code, Qty, Reel ID Label with Cree Bin Code, Qty, Reel ID Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Order Code, Qty, Reel ID, PO # Label with Cree Bin Code, Qty, Reel ID Unpackaged Reel Packaged Reel Boxed Reel CREE Bin Code & Barcode Label Vacuum-Sealed Moisture Barrier Bag Label with Customer P/N, Qty, Lot #, PO # Label with Cree Bin Code, Qty, Lot # Label with Cree Bin Code, Qty, Lot # Vacuum-Sealed Moisture Barrier Bag Patent Label Label with Customer Order Code, Qty, Reel ID, PO # Ideal for power supply 1a/1c/2a/2c/5A/10A power relays JW RELAYS VDE RoHS compliant FEATURES • Miniature package with universal terminal footprint • High dielectric withstanding for transient protection: 10,000 V surge in μs between coil and contact • Sealed construction • Class B coil insulation types available • TV rated (TV-5) types available (only for 1 Form A type) • VDE, TÜV, SEMKO, SEV, FIMKO, TV-5 also approved • Sockets are available. TYPICAL APPLICATIONS 1. Home appliances TV sets, VCR, Microwave ovens 2. Office machines Photocopiers, Vending machines 3. Industrial equipment NC machines, Robots, Temperature controllers Contact arrangement 1: 1a: 2: 2a: 1 Form C 1 Form A 2 Form C 2 Form A Contact capacity Nil: F: Standard (5 A) High capacity (10 A)* JW N Protective construction S: H: Sealed type Flux-resistant type Coil insulation class Nil: B: Class E insulation Class B insulation Pick-up voltage N: 70% of nominal voltage Nominal coil voltage DC5V, DC6V, DC9V, DC12V, DC24V, DC48V Contact material F: AgSnO2 type (1a) Nil: AgNi type (1c, 2a, 2c) *Only for 1 Form A and 1 Form C type Certified by UL, CSA, VDE, SEMKO, FIMKO and SEV Note: When ordering TV rated (TV-5) types, add suffix-TV (available only for 1 Form A type). Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T TYPES * For sockets, see page 140. RATING 1. Coil data Nominal coil voltage Pick-up voltage (at 20°C 68°F) Drop-out voltage (at 20°C 68°F) Nominal operating current [±10%] (at 20°C 68°F) Coil resistance [±10%] (at 20°C 68°F) Nominal operating power Max. applied voltage (at 20°C 68°F) 5V DC 70%V or less of nominal voltage (Initial) 10%V or more of nominal voltage (Initial) 106mA 47Ω 530mW 130%V of nominal voltage (at 60°C 140°F) 120%V of nominal voltage (at 85°C 185°F)*4 6V DC 88mA 68Ω 9V DC 58mA 155Ω 12V DC 44mA 270Ω 24V DC 22mA 1,100Ω 48V DC 11mA 4,400Ω 1) 1 Form A Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. 2) 1 Form A High capacity (10 A) type Standard packing: Carton 100 pcs. Case 500 pcs. Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1aSN-DC5V-F JW1aHN-DC5V-F 6V DC JW1aSN-DC6V-F JW1aHN-DC6V-F 9V DC JW1aSN-DC9V-F JW1aHN-DC9V-F 12V DC JW1aSN-DC12V-F JW1aHN-DC12V-F 24V DC JW1aSN-DC24V-F JW1aHN-DC24V-F 48V DC JW1aSN-DC48V-F JW1aHN-DC48V-F Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1aFSN-DC5V-F JW1aFHN-DC5V-F 6V DC JW1aFSN-DC6V-F JW1aFHN-DC6V-F 9V DC JW1aFSN-DC9V-F JW1aFHN-DC9V-F 12V DC JW1aFSN-DC12V-F JW1aFHN-DC12V-F 24V DC JW1aFSN-DC24V-F JW1aFHN-DC24V-F 48V DC JW1aFSN-DC48V-F JW1aFHN-DC48V-F 3) 1 Form C Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. 4) 1 Form C High capacity (10 A) type Standard packing: Carton 100 pcs. Case 500 pcs. Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1SN-DC5V JW1HN-DC5V 6V DC JW1SN-DC6V JW1HN-DC6V 9V DC JW1SN-DC9V JW1HN-DC9V 12V DC JW1SN-DC12V JW1HN-DC12V 24V DC JW1SN-DC24V JW1HN-DC24V 48V DC JW1SN-DC48V JW1HN-DC48V Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW1FSN-DC5V JW1FHN-DC5V 6V DC JW1FSN-DC6V JW1FHN-DC6V 9V DC JW1FSN-DC9V JW1FHN-DC9V 12V DC JW1FSN-DC12V JW1FHN-DC12V 24V DC JW1FSN-DC24V JW1FHN-DC24V 48V DC JW1FSN-DC48V JW1FHN-DC48V 5) 2 Form A Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. 6) 2 Form C Standard (5A) type Standard packing: Carton 100 pcs. Case 500 pcs. Note: Class B coil insulation type is available. Ex) JW1aSN-B-DC12V-F Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW2aSN-DC5V JW2aHN-DC5V 6V DC JW2aSN-DC6V JW2aHN-DC6V 9V DC JW2aSN-DC9V JW2aHN-DC9V 12V DC JW2aSN-DC12V JW2aHN-DC12V 24V DC JW2aSN-DC24V JW2aHN-DC24V 48V DC JW2aSN-DC48V JW2aHN-DC48V Nominal coil voltage Sealed type Flux-resistant type Part No. Part No. 5V DC JW2SN-DC5V JW2HN-DC5V 6V DC JW2SN-DC6V JW2HN-DC6V 9V DC JW2SN-DC9V JW2HN-DC9V 12V DC JW2SN-DC12V JW2HN-DC12V 24V DC JW2SN-DC24V JW2HN-DC24V 48V DC JW2SN-DC48V JW2HN-DC48V Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T 2. Specifications * Specifications will vary with foreign standards certification ratings. Notes: *1. This value can change due to the switching frequency, environmental conditions, and desired reliability level, therefore it is recommended to check this with the actual load. *2. Wave is standard shock voltage of ±1.2×50μs according to JEC-212-1981 *3. The upper limit of the ambient temperature is the maximum temperature that can satisfy the coil temperature rise value. Refer to Usage, transport and storage conditions in NOTES. *4. The pick-up and drop out voltages rise approximately 0.4% for every 1°C 33.8°F given a standard ambient temperature of 20°C 68°F. Therefore, when using relays where the ambient temperature is high, please take into consideration the rise in pick-up and drop out voltages and keep the coil applied voltage within the maximum applied voltage. REFERENCE DATA Characteristics Item Specifications Standard type High capacity type Contact Contact material 1 Form A: AgSnO2 type 1 Form C, 2 Form A and 2 Form C: AgNi type Arrangement 1 Form A, 1 Form C, 2 Form A and 2 Form C 1 Form A and 1 Form C Contact resistance (Initial) Max. 100 mΩ (By voltage drop 6 V DC 1A) Rating Nominal switching capacity (resistive load) 5A 250V AC, 5A 30V DC 10A 250V AC, 10A 30V DC Max. switching power (resistive load) 1,250VA, 150W 2,500VA, 300W Max. switching voltage 250V AC, 30V DC Max. switching current 5A 10A Min. switching capacity (reference value)*1 100mA, 5V DC Electrical characteristics Insulation resistance (Initial) Min. 1,000MΩ (at 500V DC) Measurement at same location as “Breakdown voltage” section. Breakdown voltage (Initial) Between open contacts 1,000 Vrms for 1 min. (Detection current: 10 mA) Between contact and coil 5,000 Vrms for 1 min. (Detection current: 10 mA) Between contact sets 3,000 Vrms for 1 min. (2 Form A, 2 Form C) (Detection current: 10 mA) Temperature rise (coil) 1 Form A: Max. 45°C 113°F, 1 Form C, 2 Form A and 2 Form C: Max. 55°C 131°F (resistive method, with nominal coil voltage and at nominal switching capacity, at 20°C 68°F) 1 Form A: Max. 45°C 113°F, 1 Form C: Max. 55°C 131°F (resistive method, with nominal coil voltage and at nominal switching capacity, at 20°C 68°F) Surge breakdown voltage*2 (Between contact and coil) (Initial) 10,000 V Operate time (at nominal voltage) (at 20°C 68°F) Max. 15 ms (excluding contact bounce time.) Release time (at nominal voltage) (at 20°C 68°F) Max. 5 ms (excluding contact bounce time) (Without diode) Mechanical characteristics Shock resistance Functional 98 m/s2 (Half-wave pulse of sine wave: 11 ms; detection time: 10μs.) Destructive 980 m/s2 (Half-wave pulse of sine wave: 6 ms.) Vibration resistance Functional 10 to 55 Hz at double amplitude of 1.6 mm (Detection time: 10μs.) Destructive 10 to 55 Hz at double amplitude of 2.0 mm Expected life Mechanical (at 180 times/min.) Min. 5×106 Electrical (at 6 times/min.) Min. 105 (at resistive load) Conditions Conditions for operation, transport and storage*3 Ambient temperature*4: –40°C to +60°C –40°F to 140°F (Class E), (Class B: –40°C to +85°C –40°F to 185°F) Humidity: 5 to 85% R.H. (Not freezing and condensing at low temperature) Max. operating speed (at nominal switching capacity) Flux-resistant type: 20 times/min., Sealed type: 6 times/min. Unit weight Approx. 13 g .46 oz JW 1 Form A Standard (5A) type 1. Maximum operating power 2. Operate/release time Sample: JW1aSN-DC12V-F, 10 pcs. Ambient temperature: 20°C 68°F 3. Life curve 1 Form A Standard (5 A) type 10 100 10 100 1,000 1 Contact voltage, V AC resistive load DC resistive load Contact current, A 80 90 100 110 120 5 0 10 Min. Max. Min. x - x - Max. Coil applied voltage, %V Operate/release time, ms Operate time Release time 100 10 5 10 15 Contact current, A Life, ×104 250 V AC resistive load 30 V DC resistive load Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T JW 1 Form A High Capacity (10 A) type 1. Maximum operating power 2. Operate/release time Sample: JW1aFSN-DC12V, 10 pcs. Ambient temperature: 20°C 68°F 3. Life curve 10 100 10 100 1,000 1 Contact voltage, V AC resistive load DC resistive load Contact current, A 80 90 100 110 120 5 0 10 Min. Max. Min. x - x - Max. Coil applied voltage, %V Operate/release time, ms Operate time Release time 100 10 1 0 2 4 6 8 10 12 Contact current, A Life, ×104 250 V AC resistive load 30 V DC resistive load 4-(1). Coil temperature rise (Contact carrying current: 5A) Sample JW1aFSN-DC12V-F, 6 pcs. Point measured: Inside the coil 4-(2). Coil temperature rise (Contact carrying current: 10 A) Sample: JW1aFSN-DC12V-F, 6 pcs. Point measured: Inside the coil 100 120 140 160 10 20 30 40 50 60 70 0 Coil applied voltage, %V Temperature rise, °C 85°C 60°C 25°C 100 120 140 160 10 20 30 40 50 60 70 0 Coil applied voltage, %V Temperature rise, °C 85°C 60°C 25°C JW 1 Form C Standard (5 A) type 1-(3). Maximum operating power 2. Operate/release time Sample: JW1SN-DC12V-F, 6 pcs. Ambient temperature: 20°C 68°F JW 1 Form C High Capacity (10 A) type 1. Maximum operating power 10 10 100 1,000 1 0 Contact voltage, V AC resistive load (cosϕ = 1.0) Contact current, A Max. Min. 13 12 11 10 9 6 4 100 8 7 3 2 1 5 80 90 110 120 130 Max. Min. x - x - Coil applied voltage, %V Operate/release time, ms 10 10 100 1,000 1 0 Contact voltage, V AC resistive load (cosϕ = 1.0) Contact current, A JW 2 Form A Standard (5 A) type 1. Maximum operating power 2. Operate/release time Sample: JW2aSN-DC24V-F, 6 pcs. Ambient temperature: 20°C 68°F 10 10 100 1,000 1 0 Contact voltage, V AC resistive load (cosϕ = 1.0) Contact current, A 14 13 12 10 8 6 4 2 80 90 100 110 120 Min. x - x - Coil applied voltage, %V Operate/release time, ms Operate time Release time Max. Max. Min. Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T DIMENSIONS (mm inch) JW 2 Form C Standard (5 A) type 1. Maximum operating power 2. Operate/release time Sample: JW2SN-DC12V-F, 6 pcs. Ambient temperature: 20°C 68°F 10 10 100 1,000 1 0 Contact voltage, V Contact current, A AC resistive load (cosϕ = 1.0) 9 8 7 6 5 4 3 2 1 0 80 90 100 110 120 130 Max. Coil applied voltage, %V Operate/release time, ms Operate time Release time Min. Min. Max. x - x - The CAD data of the products with a CAD Data mark can be downloaded from: http://industrial.panasonic.com/ac/e/ JW 1 Form A External dimensions 0.3 0.3 0.5 0.4 12.8 7.6 1.1 2.4 3.5 0.9 28.6 20 20 3.6 .012 .012 .020 .016 .504 .299 .043 .094 .138 .035 1.126 .787 .787 .142 Wiring diagram (Bottom view) Note: Terminal numbers are not indicated on the relay. PC board pattern (Bottom view) Tolerance: ±0.1 ±.004 COM N.O. Coil 4 6 1 8 Relay outline 12.8 .504 7.6 .299 20.0 .787 2.4 .094 4-1.5 dia. 4-.059 dia. 3.5 .138 CAD Data Dimension: Less than 1mm .039inch: Min. 1mm .039inch less than 3mm .118 inch: Min. 3mm .118 inch: General tolerance ±0.1 ±.004 ±0.2 ±.008 ±0.3 ±.012 JW 1 Form C External dimensions 20 .787 0.4 .016 3.6 .142 0.5 .020 0.3 0.5 .012 .020 0.3 .012 1.1 .043 2.4 .094 3.5 .138 3.5 .138 16.5 .650 28.6 1.128 0.8 .031 7.6 .299 12.8 .504 Wiring diagram (Bottom view) Note: Terminal numbers are not indicated on the relay. PC board pattern (Bottom view) Tolerance: ±0.1 ±.004 COM N.C. N.O. Coil 4 2 6 1 8 Relay outline 5-1.5 dia. 5-.059 dia. 16.5 .650 3.5 .138 3.5 .138 2.4 .094 7.6 .299 CAD Data Dimension: Less than 1mm .039inch: Min. 1mm .039inch less than 3mm .118 inch: Min. 3mm .118 inch: General tolerance ±0.1 ±.004 ±0.2 ±.008 ±0.3 ±.012 Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ JW ASCTB190E 201210-T SAFETY STANDARDS Item UL/C-UL (Recognized) CSA (Certified) VDE (Certified) TV rating (UL/CSA) TÜV (Certified) SEMKO (Certified) FIMKO SEV File No. Contact rating File No. Contact rating File No. Contact rating File No. Rating File No. Rating File No. Contact rating File No. Contact rating File No. Contact rating Standard type 1 Form A E43028 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC LR26550 etc. 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 40013854 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) Standard type 5A 30V DC (0ms) UL E43028 CSA LR26550 etc. 1a➝TV-5 B 11 05 13461 305 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) 5A 30V DC (0ms) 817817 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 24965 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 11. 0262 5A 250V AC (cosφ =1.0) Standard type 1 Form C E43028 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC LR26550 etc. 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 40013854 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) Standard type 5A 30V DC (0ms) — — B 11 05 13461 305 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) 5A 30V DC (0ms) 817817 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 24965 5A 250V AC (cosφ =1.0) 5A 30V DC (0ms) 11. 0262 5A 250V AC (cosφ =1.0) Standard type 2 Form A E43028 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 LR26550 etc. 5A 277V AC 5A 30V DC 1/8HP 125V AC 1/8HP 250V AC B300 40013854 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) Standard type 5A 30V DC (0ms) — — B 11 05 13461 305 5A 250V AC (cosφ =1.0) 3A 250V AC (cosφ =0.4) 5A 30V DC (0ms) Tantalum-Polymer Solid Capacitors New Capacitors Panasonic New Product Introduction Stable Capacitance at High Frequency and Temperature, with Low ESR/ESL Panasonic, a worldwide leader in Capacitor Products, introduces POSCAP Tantalum-Polymer Solid Capacitors to their Capacitor product line. The POSCAP product line spans several series of Solid Electrolyte Chip Capacitors which include the TPE, TQC, TPF, TPSF, TPB, TPC, TPG, and TPU Series. These capacitors utilize a sintered tantalum anode and a proprietary high conductivity polymer for a cathode. Panasonic’s innovative construction and processing yields the lowest ESR level in polymer tantalum technology, and exhibits excellent performance in high frequency applications. Offering a high volumetric efficiency for capacitance, POSCAP Capacitors is available in various, compact package sizes for a small PCB footprint. Additionally, POSCAP parts demonstrate a high reliability and high heat resistance, making them the ideal Chip Capacitor for digital, high-frequency devices and more. • Low Profile Package Size: 0.9mm Height (TPU) • Very Low ESR (Down to 5mΩ) • Large Capacitance (Up to 1500μF) • High Temp Reflow Solder Capable (up to 260°C) • RoHS Compliant • High Volumetric Efficiency for Capacitance • Safe Alternative to Generic Tantalum Capacitors • Variety of Low Profile Packages Opens up PCB Space • Wide Application Coverage • Consumer Electronics • Industrial Electronics • Telecommunications • Appliances • PC/Server • Set Top Box • Audio/Video Equipment • FPGA Power Delivery • Router/Switch/Base Station • Test and Measurement Website: www.panasonic.com/industrial industrial@us.panasonic.com 1-800-344-2112 Copyright © 2013 Panasonic Corporation of North America. All Rights Reserved. Specifications are subject to change without notice. POSCAP NPI, FY13-038-XXX Features Benefits Industries Applications Part Number Information Additional Information For detailed specification information on the POSCAP Line of Tantalum Solid Capacitors, visit our website at: www.panasonic.com/industrial/electronic-components/capacitive-products/ RoHS COMPLIANT Series Information TPE, TQC, TPF, TPSF, TPB, TPC, TPG, TPU Series 2 R 5 Rated Voltage Series Rated Capacitance Cap. Tol. T P E 3 3 0 M Special Code A Z B Series Voltage Capacitance ESR TPE 2-10 VDC 47-1500 μF 7-35 mΩ TQC 16-35 VDC 3.9-150 μF 40-400 mΩ TPF 2-10 VDC 150-1000 μF 5-15 mΩ TPSF 2 VDC 270 μF 6-9 mΩ TPB 4-10 VDC 33-470 μF 35-70 mΩ TPC 6.3-12.5 VDC 10-330 μF 40-80 mΩ TPG 2.5-12.5 VDC 33-220 μF 30-70 mΩ TPU 2.5-10 VDC 4.7-150 μF 100-300 mΩ Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-63 – 0d±0.05 010􀀝 Sleeve L􀀽 14 min. 3 min. (􀀽08􀁌15, 016􀁌15, 018􀁌15 : L±1.5) Pressure relief 06.3􀀝 But exclude 7 mm height 􀀽􀀀L􀀝16 : L±1.0 L􀀟20 : L±2.0 + – 04 to 08 0D±0.5 F±0.5 0D±0.5 ■ Features ● Endurance : 105 °C 1000 h to 5000 h ● Low impedance ● RoHS directive compliant Radial Lead Type Series: FC Type: A ■ Specifi cations Category Temp. Range –55 °C to +105 °C Rated W.V. Range 6.3 V.DC to 100 V.DC Nominal Cap. Range 2.2 μF to 15000 μF Capacitance Tolerance ±20 % (120 Hz/+20 °C) DC Leakage Cur rent I < 0.01 CV or 3 (μA) After 2 minutes (Whichever is greater) tan d W.V. (V) 6.3 10 16 25 35 50 63 100 (120 Hz/+20 °C) tan d 0.22 0.19 0.16 0.14 0.12 0.10 0.08 0.07 For capacitance value > 1000 μF, add 0.02 per every 1000 μF. Endurance After following life test with DC voltage and +105 °C±2 °C ripple current value applied (The sum of DC and ripple peak voltage shall not exceed the rated working voltage) when the capacitors are restored to 20 °C, the capacitors shall meet the limits specifi ed bellow. Duration : 04 to 06.3: 1000 hours, 08: 2000 hours , 010: 3000 hours , 012.5 to 018: 5000 hours Capacitance change ±20 % of initial measured value tan d < 200 % of initial specifi ed value DC leakage current < initial specifi ed value Shelf Life After storage for 1000 hours at +105 °C±2 °C with no voltage applied and then being stabilized at +20 °C, capacitors shall meet the limits specifi ed in Endurance. (With voltage treatment) W.V.(V.DC) Cap (μF) Frequency (Hz) 60 120 1 k 10 k 100 k 6.3 to 100 2.2 to 330 0.55 0.65 0.85 0.90 1.00 390 to 1000 0.70 0.75 0.90 0.95 1.00 1200 to 2200 0.75 0.80 0.90 0.95 1.00 2700 to 15000 0.80 0.85 0.95 1.00 1.00 ■ Frequency correction factor for ripple current L>11 L=7 Body Dia. 0D 4 5 6.3 8 10 12.5 16 18 4 5 6.3 Body Length L 15 to 25 30 to 40 Lead Dia. 0d 0.45 0.5 0.5 0.6 0.6 0.6 0.8 0.8 0.8 0.45 0.45 0.45 Lead space F 1.5 2.0 2.5 3.5 5.0 5.0 5.0 7.5 7.5 1.5 2.0 2.5 ■ Di men sions in mm (not to scale) (Unit : mm) 02 Dec. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-64 – ■ Case size/ Impedance/ Ripple Current W.V(V.DC) 6.3 V to 35 V 50 V 63 V 100 V Case size (0D×L) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) /(100 kHz) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) /(100 kHz) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) /(100 kHz) Imped ance (Ω)/(100 kHz) Ripple Current (mA r.m.s) 20 °C –10 °C 20 °C –10 °C 20 °C –10 °C 20 °C –10 °C /(100 kHz) 4 × 7 2.00 5.00 65 5 × 7 0.950 2.40 120 6.3 × 7 0.450 1.20 200 4 × 11 1.30 2.60 120 2.50 5.00 90 3.50 7.00 80 5 × 11 0.800 1.60 175 ✽ ✽ ✽ 2.00 4.00 145 4.10 8.20 80 5 × 15 0.500 1.00 235 0.900 1.80 215 1.30 2.60 200 2.80 5.60 90 6.3 × 11.2 0.350 0.700 290 0.600 1.20 260 1.00 2.00 240 1.80 3.60 114 6.3 × 15 0.250 0.500 400 0.400 0.800 360 0.700 1.40 330 1.10 2.20 155 8 × 11.5 0.117 0.234 555 0.234 0.468 485 0.342 0.684 405 0.680 1.36 260 8 × 15 0.085 0.170 730 0.155 0.310 635 0.230 0.460 535 0.450 0.900 340 8 × 20 0.065 0.130 995 0.120 0.240 860 0.178 0.356 690 0.330 0.660 455 10 × 12.5 0.090 0.180 755 0.162 0.324 615 0.256 0.512 535 0.530 1.06 306 10 × 16 0.068 0.136 1050 0.119 0.238 850 0.194 0.388 600 0.360 0.720 400 10 × 20 0.052 0.104 1220 0.090 0.180 1030 0.147 0.294 885 0.240 0.480 463 10 × 25 0.045 0.090 1440 0.082 0.164 1200 0.130 0.260 1050 0.210 0.420 599 10 × 30 0.035 0.070 1815 0.060 0.120 1610 0.090 0.180 1300 0.150 0.300 698 12.5 × 15 0.065 0.130 1205 0.110 0.220 1150 0.150 0.300 1020 0.230 0.460 511 12.5 × 20 0.038 0.076 1655 0.063 0.126 1480 0.085 0.170 1285 0.180 0.360 671 12.5 × 25 0.030 0.060 1945 0.050 0.100 1832 0.070 0.140 1720 0.110 0.220 807 12.5 × 30 0.025 0.050 2310 0.040 0.080 2215 0.055 0.110 2090 0.098 0.196 937 12.5 × 35 0.022 0.044 2510 0.034 0.068 2285 0.047 0.094 2265 0.087 0.174 1040 12.5 × 40 0.018 0.036 2655 0.030 0.060 2590 0.042 0.084 2560 0.072 0.144 1130 16 × 15 0.043 0.086 1690 0.080 0.160 1610 0.090 0.180 1410 0.140 0.280 793 16 × 20 0.029 0.058 2205 0.048 0.096 1835 0.059 0.118 1765 0.110 0.220 995 16 × 25 0.022 0.044 2555 0.034 0.068 2235 0.050 0.100 2160 0.089 0.178 1170 16 × 31.5 0.018 0.036 3010 0.028 0.056 2700 0.043 0.086 2670 0.062 0.124 1520 16 × 35.5 0.016 0.032 3150 0.025 0.050 2790 0.036 0.072 2770 0.053 0.106 1730 16 × 40 0.015 0.030 3360 0.023 0.046 2845 0.030 0.060 2825 0.047 0.094 1920 18 × 15 0.038 0.076 2000 0.068 0.136 1900 0.086 0.172 1690 0.120 0.240 917 18 × 20 0.028 0.056 2490 0.042 0.084 2420 0.055 0.110 2290 0.080 0.160 1230 18 × 25 0.020 0.040 2740 0.029 0.058 2610 0.043 0.086 2585 0.070 0.140 1420 18 × 31.5 0.016 0.032 3635 0.025 0.050 3000 0.032 0.064 2950 0.062 0.124 1600 18 × 35.5 0.015 0.030 3680 0.023 0.046 3100 0.030 0.060 3095 0.041 0.082 1770 18 × 40 0.014 0.028 3735 – – – 0.025 0.050 3205 0.036 0.072 2300 ✽ Case size (0D×L) Capacitance (μF) Imped ance (Ω)/(100 kHz) Ripple Current 20 °C –10 °C (mA r.m.s)(100 kHz) 5 × 11 1.0 2.40 4.80 20 2.2 1.80 3.60 45 3.3 1.30 2.60 65 4.7 1.30 2.60 95 10 1.30 2.60 125 12 1.30 2.60 135 15 1.30 2.60 145 18 1.30 2.60 155 22 1.30 2.60 155 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-65 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 6.3 27 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC0J270( ) 200 2000 56 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC0J560( ) 200 2000 68 4 11 120 1.300 1000 0.45 1.5 5.0 2.5 EEUFC0J680( ) 200 2000 100 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC0J101( ) 200 2000 120 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC0J121( ) 200 2000 150 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC0J151( ) 200 2000 220 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC0J221( ) 200 2000 270 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC0J271( ) 200 2000 330 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC0J331S( ) 200 2000 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC0J331( ) 200 2000 390 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC0J391( ) 200 1000 470 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC0J471( ) 200 1000 560 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC0J561( ) 200 1000 820 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC0J821L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC0J821( ) 200 500 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC0J102( ) 200 500 1200 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC0J122L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC0J122( ) 200 500 1500 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC0J152( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC0J152S( ) 200 500 1800 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC0J182( ) 200 500 2200 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC0J222( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC0J222S( ) 100 250 2700 10 30 1815 0.035 3000 0.60 5.0 EEUFC0J272L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC0J272( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC0J272S( ) 100 250 3300 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC0J332( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC0J332S( ) 100 250 3900 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC0J392( ) 200 500 4700 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC0J472 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC0J472S( ) 100 250 5600 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC0J562L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC0J562( ) 100 250 6800 12.5 40 2655 0.018 5000 0.80 5.0 EEUFC0J682L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC0J682( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC0J682S( ) 100 250 8200 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC0J822 100 10000 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC0J103 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC0J103S( ) 100 250 12000 16 40 3360 0.015 5000 0.80 7.5 EEUFC0J123L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC0J123 50 15000 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC0J153 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-66 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 10 22 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1A220( ) 200 2000 39 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1A390( ) 200 2000 47 4 11 120 1.300 1000 0.45 1.5 5.0 2.5 EEUFC1A470( ) 200 2000 82 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1A820( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1A820( ) 200 2000 100 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1A101S( ) 200 2000 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1A101( ) 200 2000 150 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1A151( ) 200 2000 180 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1A181( ) 200 2000 220 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1A221S( ) 200 2000 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1A221( ) 200 2000 330 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1A331( ) 200 1000 390 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1A391( ) 200 1000 470 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1A471( ) 200 1000 560 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1A561( ) 200 500 680 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1A681L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1A681( ) 200 500 820 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1A821( ) 200 500 1000 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1A102L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1A102( ) 200 500 1200 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1A122( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1A122S( ) 200 500 1500 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1A152( ) 200 500 1800 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1A182( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1A182S( ) 100 250 2200 10 30 1815 0.035 3000 0.60 5.0 EEUFC1A222L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1A222( ) 200 500 2700 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1A272( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1A272S( ) 100 250 3300 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1A332 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1A332S( ) 100 250 3900 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1A392L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1A392( ) 100 250 4700 12.5 40 2655 0.018 5000 0.80 5.0 EEUFC1A472L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1A472( ) 100 250 5600 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1A562( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1A562S( ) 100 250 6800 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1A682 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1A682S( ) 100 250 8200 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1A822L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1A822 50 10000 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1A103 50 12000 18 40 3735 0.014 5000 0.80 7.5 EEUFC1A123 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-67 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 16 15 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1C150( ) 200 2000 27 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1C270( ) 200 2000 39 4 11 120 1.30 1000 0.45 1.5 5.0 2.5 EEUFC1C390( ) 200 2000 47 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1C470( ) 200 2000 56 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1C560( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1C560( ) 200 2000 68 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1C680( ) 200 2000 82 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1C820( ) 200 2000 100 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1C101( ) 200 2000 120 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1C121( ) 200 2000 180 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1C181( ) 200 2000 220 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1C221( ) 200 1000 270 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1C271( ) 200 1000 330 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1C331( ) 200 1000 390 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1C391( ) 200 500 470 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1C471L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1C471( ) 200 500 560 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1C561( ) 200 500 680 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1C681L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1C681( ) 200 500 820 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1C821( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1C821S( ) 200 500 1000 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1C102S( ) 200 500 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1C102( ) 200 500 1200 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1C122( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1C122S( ) 100 250 1500 10 30 1815 0.035 3000 0.60 5.0 EEUFC1C152L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1C152( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1C152S( ) 100 250 1800 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1C182( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1C182S( ) 100 250 2200 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1C222( ) 200 500 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1C222S( ) 100 250 2700 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1C272L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1C272( ) 100 250 3300 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1C332 100 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1C332S( ) 100 250 3900 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1C392( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1C392S( ) 100 250 4700 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1C472 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1C472S( ) 100 250 5600 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1C562L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1C562 50 6800 16 40 3360 0.015 5000 0.80 7.5 EEUFC1C682 100 8200 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1C822 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-68 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 25 10 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1E100( ) 200 2000 22 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1E220( ) 200 2000 27 4 11 120 1.30 1000 0.45 1.5 5.0 2.5 EEUFC1E270( ) 200 2000 39 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1E390( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1E390( ) 200 2000 47 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1E470( ) 200 2000 56 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1E560( ) 200 2000 82 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1E820( ) 200 2000 100 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1E101S( ) 200 2000 120 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1E121( ) 200 2000 180 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1E181( ) 200 1000 220 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1E221( ) 200 1000 270 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1E271( ) 200 500 330 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1E331L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1E331( ) 200 500 390 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1E391( ) 200 500 470 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1E471L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1E471( ) 200 500 560 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1E561( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1E561S( ) 200 500 680 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1E681( ) 200 500 820 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1E821( ) 200 500 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1E821S( ) 200 500 1000 10 30 1815 0.035 3000 0.60 5.0 EEUFC1E102L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1E102( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1E102S( ) 100 250 1200 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1E122( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1E122S( ) 100 250 1500 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1E152( ) 200 500 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1E152S( ) 100 250 1800 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1E182L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1E182( ) 100 250 2200 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1E222 100 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1E222S( ) 100 250 2700 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1E272( ) 100 250 3300 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1E332 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1E332S( ) 100 250 3900 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1E392L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1E392 50 4700 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1E472 50 5600 18 40 3735 0.014 5000 0.80 7.5 EEUFC1E562 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-69 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) () (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 35 6.8 4 7 65 2.000 1000 0.45 1.5 5.0 2.5 EEAFC1V6R8( ) 200 2000 12 5 7 120 0.950 1000 0.45 2.0 5.0 2.5 EEAFC1V120( ) 200 2000 18 4 11 120 1.300 1000 0.45 1.5 5.0 2.5 EEUFC1V180( ) 200 2000 22 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1V220( ) 200 2000 27 5 11 175 0.800 1000 0.50 2.0 5.0 2.5 EEUFC1V270( ) 200 2000 6.3 7 200 0.450 1000 0.45 2.5 5.0 2.5 EEAFC1V270( ) 200 2000 33 5 11 175 0.080 1000 0.50 2.0 5.0 2.5 EEUFC1V330( ) 200 2000 39 5 15 235 0.500 1000 0.50 2.0 5.0 2.5 EEUFC1V390( ) 200 2000 47 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1V470( ) 200 2000 56 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1V560( ) 200 2000 68 6.3 11.2 290 0.350 1000 0.50 2.5 5.0 2.5 EEUFC1V680( ) 200 2000 82 6.3 15 400 0.250 1000 0.50 2.5 5.0 2.5 EEUFC1V820( ) 200 2000 100 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1V101( ) 200 1000 120 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1V121( ) 200 1000 150 8 11.5 555 0.117 2000 0.60 3.5 5.0 EEUFC1V151( ) 200 1000 180 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1V181( ) 200 500 220 8 15 730 0.085 2000 0.60 3.5 5.0 EEUFC1V221L( ) 200 1000 10 12.5 755 0.090 3000 0.60 5.0 5.0 EEUFC1V221( ) 200 500 270 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1V271( ) 200 500 330 8 20 995 0.065 2000 0.60 3.5 5.0 EEUFC1V331L( ) 200 1000 10 16 1050 0.068 3000 0.60 5.0 5.0 EEUFC1V331( ) 200 500 390 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1V391( ) 200 500 12.5 15 1205 0.065 5000 0.60 5.0 5.0 EEUFC1V391S( ) 200 500 470 10 20 1220 0.052 3000 0.60 5.0 5.0 EEUFC1V471( ) 200 500 560 10 25 1440 0.045 3000 0.60 5.0 5.0 EEUFC1V561( ) 200 500 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1V561S( ) 200 500 680 10 30 1815 0.035 3000 0.60 5.0 EEUFC1V681L 100 12.5 20 1655 0.038 5000 0.60 5.0 5.0 EEUFC1V681( ) 200 500 16 15 1690 0.043 5000 0.80 7.5 7.5 EEUFC1V681S( ) 100 250 820 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1V821L( ) 200 500 18 15 2000 0.038 5000 0.80 7.5 7.5 EEUFC1V821( ) 100 250 1000 12.5 25 1945 0.030 5000 0.60 5.0 5.0 EEUFC1V102( ) 200 500 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1V102S( ) 100 250 1200 12.5 30 2310 0.025 5000 0.80 5.0 EEUFC1V122L 100 16 20 2205 0.029 5000 0.80 7.5 7.5 EEUFC1V122( ) 100 250 1500 12.5 35 2510 0.022 5000 0.80 5.0 EEUFC1V152L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1V152( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1V152S( ) 100 250 1800 12.5 40 2655 0.018 5000 0.80 5.0 EEUFC1V182L 100 16 25 2555 0.022 5000 0.80 7.5 7.5 EEUFC1V182( ) 100 250 18 20 2490 0.028 5000 0.80 7.5 7.5 EEUFC1V182S( ) 100 250 2200 16 31.5 3010 0.018 5000 0.80 7.5 EEUFC1V222 100 18 25 2740 0.020 5000 0.80 7.5 7.5 EEUFC1V222S( ) 100 250 2700 16 35.5 3150 0.016 5000 0.80 7.5 EEUFC1V272L 100 18 31.5 3635 0.016 5000 0.80 7.5 EEUFC1V272 50 3300 18 35.5 3680 0.015 5000 0.80 7.5 EEUFC1V332 50 3900 18 40 3735 0.014 5000 0.80 7.5 EEUFC1V392 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C φ4 to φ6.3=1000 h, φ8=2000 h, φ10=3000 h, φ12.5 to φ18=5000 h 00 Nov. 2012 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-70 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 50 1.0 5 11 20 2.400 1000 0.50 2.0 5.0 2.5 EEUFC1H1R0( )✽✽✽ 200 2000 2.2 5 11 45 1.800 1000 0.50 2.0 5.0 2.5 EEUFC1H2R2( ) 200 2000 3.3 5 11 65 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H3R3( ) 200 2000 4.7 5 11 95 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H4R7( ) 200 2000 10 4 11 90 2.500 1000 0.45 1.5 5.0 2.5 EEUFC1H100( ) 200 2000 5 11 125 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H100L( ) 200 2000 12 5 11 135 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H120( ) 200 2000 15 5 11 145 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H150( ) 200 2000 18 5 11 155 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H180( ) 200 2000 22 5 11 155 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1H220( ) 200 2000 27 5 15 215 0.900 1000 0.50 2.0 5.0 2.5 EEUFC1H270( ) 200 2000 33 6.3 11.2 260 0.600 1000 0.50 2.5 5.0 2.5 EEUFC1H330( ) 200 2000 39 6.3 11.2 260 0.600 1000 0.50 2.5 5.0 2.5 EEUFC1H390( ) 200 2000 47 6.3 11.2 260 0.600 1000 0.50 2.5 5.0 2.5 EEUFC1H470( ) 200 2000 56 6.3 15 360 0.400 1000 0.50 2.5 5.0 2.5 EEUFC1H560( ) 200 2000 68 8 11.5 485 0.234 2000 0.60 3.5 5.0 EEUFC1H680( ) 200 1000 82 8 11.5 485 0.234 2000 0.60 3.5 5.0 EEUFC1H820( ) 200 1000 100 10 12.5 615 0.162 3000 0.60 5.0 5.0 EEUFC1H101( ) 200 500 120 8 15 635 0.155 2000 0.60 3.5 5.0 EEUFC1H121L( ) 200 1000 10 12.5 615 0.162 3000 0.60 5.0 5.0 EEUFC1H121( ) 200 500 150 10 16 850 0.119 3000 0.60 5.0 5.0 EEUFC1H151( ) 200 500 180 8 20 860 0.120 2000 0.60 3.5 5.0 EEUFC1H181L( ) 200 1000 10 16 850 0.119 3000 0.60 5.0 5.0 EEUFC1H181( ) 200 500 220 10 20 1030 0.090 3000 0.60 5.0 5.0 EEUFC1H221( ) 200 500 12.5 15 1150 0.110 5000 0.60 5.0 5.0 EEUFC1H221S( ) 200 500 270 10 25 1200 0.082 3000 0.60 5.0 5.0 EEUFC1H271( ) 200 500 330 10 30 1610 0.060 3000 0.60 5.0 EEUFC1H331L 100 12.5 20 1480 0.063 5000 0.60 5.0 5.0 EEUFC1H331( ) 200 500 390 12.5 20 1480 0.063 5000 0.60 5.0 5.0 EEUFC1H391( ) 200 500 16 15 1610 0.080 5000 0.80 7.5 7.5 EEUFC1H391S( ) 100 250 470 10 30 1610 0.060 3000 0.60 5.0 EEUFC1H471L 100 12.5 25 1832 0.050 5000 0.60 5.0 5.0 EEUFC1H471( ) 200 500 560 12.5 25 1832 0.050 5000 0.60 5.0 5.0 EEUFC1H561( ) 200 500 18 15 1900 0.068 5000 0.80 7.5 7.5 EEUFC1H561S( ) 100 250 680 12.5 30 2215 0.040 5000 0.80 5.0 EEUFC1H681L 100 16 20 1835 0.048 5000 0.80 7.5 7.5 EEUFC1H681( ) 100 250 820 12.5 35 2285 0.034 5000 0.80 5.0 EEUFC1H821L 100 18 20 2420 0.042 5000 0.80 7.5 7.5 EEUFC1H821( ) 100 250 1000 12.5 40 2590 0.030 5000 0.80 5.0 EEUFC1H102L 100 16 25 2235 0.034 5000 0.80 7.5 7.5 EEUFC1H102( ) 100 250 1200 16 31.5 2700 0.028 5000 0.80 7.5 EEUFC1H122 100 18 25 2610 0.029 5000 0.80 7.5 7.5 EEUFC1H122S( ) 100 250 1500 16 35.5 2790 0.025 5000 0.80 7.5 EEUFC1H152L 100 1800 16 40 2845 0.023 5000 0.80 7.5 EEUFC1H182L 100 18 31.5 3000 0.025 5000 0.80 7.5 EEUFC1H182 50 2200 18 35.5 3100 0.023 5000 0.80 7.5 EEUFC1H222 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. ✽✽✽ Please kindly accept last shipment : 31/Mar/2015 Endurance : 105 °C 04 to 06.3=1000 h, 08=2000 h, 010=3000 h, 012.5 to 018=5000 h 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-71 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 63 6.8 4 11 80 3.500 1000 0.45 1.5 5.0 2.5 EEUFC1J6R8( ) 200 2000 12 5 11 145 2.000 1000 0.50 2.0 5.0 2.5 EEUFC1J120( ) 200 2000 18 5 15 200 1.300 1000 0.50 2.0 5.0 2.5 EEUFC1J180( ) 200 2000 22 6.3 11.2 240 1.000 1000 0.50 2.5 5.0 2.5 EEUFC1J220( ) 200 2000 33 6.3 11.2 240 1.000 1000 0.50 2.5 5.0 2.5 EEUFC1J330( ) 200 2000 39 6.3 15 330 0.700 1000 0.50 2.5 5.0 2.5 EEUFC1J390( ) 200 2000 47 8 11.5 405 0.342 2000 0.60 3.5 5.0 EEUFC1J470( ) 200 1000 56 8 11.5 405 0.342 2000 0.60 3.5 5.0 EEUFC1J560( ) 200 1000 68 8 11.5 405 0.342 2000 0.60 3.5 5.0 EEUFC1J680( ) 200 1000 82 10 12.5 535 0.256 3000 0.60 5.0 5.0 EEUFC1J820( ) 200 500 100 8 15 535 0.230 2000 0.60 3.5 5.0 EEUFC1J101L( ) 200 1000 10 12.5 535 0.256 3000 0.60 5.0 5.0 EEUFC1J101( ) 200 500 120 10 16 600 0.194 3000 0.60 5.0 5.0 EEUFC1J121( ) 200 500 150 8 20 690 0.178 2000 0.60 3.5 5.0 EEUFC1J151( ) 200 1000 180 10 20 885 0.147 3000 0.60 5.0 5.0 EEUFC1J181( ) 200 500 12.5 15 1020 0.150 5000 0.60 5.0 5.0 EEUFC1J181S( ) 200 500 220 10 20 885 0.147 3000 0.60 5.0 5.0 EEUFC1J221X( ) 200 500 10 25 1050 0.130 3000 0.60 5.0 5.0 EEUFC1J221( ) 200 500 12.5 20 1285 0.085 5000 0.60 5.0 5.0 EEUFC1J221S( ) 200 500 270 16 15 1410 0.090 5000 0.80 7.5 7.5 EEUFC1J271( ) 100 250 330 10 30 1300 0.090 3000 0.60 5.0 EEUFC1J331L 100 12.5 20 1285 0.085 5000 0.60 5.0 5.0 EEUFC1J331( ) 200 500 390 12.5 25 1720 0.070 5000 0.60 5.0 5.0 EEUFC1J391( ) 200 500 18 15 1690 0.086 5000 0.80 7.5 7.5 EEUFC1J391S( ) 100 250 470 12.5 30 2090 0.055 5000 0.80 5.0 EEUFC1J471L 100 16 20 1765 0.059 5000 0.80 7.5 7.5 EEUFC1J471( ) 100 250 560 16 25 2160 0.050 5000 0.80 7.5 7.5 EEUFC1J561( ) 100 250 680 12.5 35 2265 0.047 5000 0.80 5.0 EEUFC1J681L 100 16 25 2160 0.050 5000 0.80 7.5 7.5 EEUFC1J681( ) 100 250 18 20 2290 0.055 5000 0.80 7.5 7.5 EEUFC1J681S( ) 100 250 820 12.5 40 2560 0.042 5000 0.80 5.0 EEUFC1J821L 100 16 31.5 2670 0.043 5000 0.80 7.5 EEUFC1J821 100 18 25 2585 0.043 5000 0.80 7.5 7.5 EEUFC1J821S( ) 100 250 1000 16 31.5 2670 0.043 5000 0.80 7.5 EEUFC1J102U 100 16 35.5 2770 0.036 5000 0.80 7.5 EEUFC1J102 100 1200 16 40 2825 0.030 5000 0.80 7.5 EEUFC1J122L 100 18 31.5 2950 0.032 5000 0.80 7.5 EEUFC1J122 50 1500 18 35.5 3095 0.030 5000 0.80 7.5 EEUFC1J152 50 1800 18 40 3205 0.025 5000 0.80 7.5 EEUFC1J182 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C 04 to 06.3=1000 h, 08=2000 h, 010=3000 h, 012.5 to 018=5000 h 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FC – EEE-72 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 100 5.6 5 11 80 4.10 1000 0.5 2.0 5.0 2.5 EEUFC2A5R6( ) 200 2000 8.2 5 15 90 2.80 1000 0.5 2.0 5.0 2.5 EEUFC2A8R2( ) 200 2000 12 6.3 11.2 114 1.80 1000 0.5 2.5 5.0 2.5 EEUFC2A120( ) 200 2000 18 6.3 15 155 1.10 1000 0.5 2.5 5.0 2.5 EEUFC2A180( ) 200 2000 22 8 11.5 260 0.680 2000 0.6 3.5 5.0 EEUFC2A220( ) 200 1000 33 8 15 340 0.450 2000 0.6 3.5 5.0 EEUFC2A330L( ) 200 1000 10 12.5 306 0.530 3000 0.6 5.0 5.0 EEUFC2A330( ) 200 500 39 8 20 455 0.330 2000 0.6 5.0 5.0 EEUFC2A390L( ) 200 1000 10 16 400 0.360 3000 0.6 5.0 5.0 EEUFC2A390( ) 200 500 56 10 20 463 0.240 3000 0.6 5.0 5.0 EEUFC2A560( ) 200 500 68 10 25 599 0.210 3000 0.6 5.0 5.0 EEUFC2A680L( ) 200 500 12.5 15 511 0.230 5000 0.6 5.0 5.0 EEUFC2A680( ) 200 500 100 10 30 698 0.150 3000 0.6 5.0 EEUFC2A101L 100 12.5 20 671 0.180 5000 0.6 5.0 5.0 EEUFC2A101( ) 200 500 120 16 15 793 0.140 5000 0.8 7.5 7.5 EEUFC2A121S( ) 100 250 150 12.5 25 807 0.110 5000 0.6 5.0 5.0 EEUFC2A151( ) 200 500 18 15 917 0.120 5000 0.8 7.5 7.5 EEUFC2A151S( ) 100 250 180 12.5 30 937 0.098 5000 0.8 5.0 EEUFC2A181L 100 16 20 995 0.110 5000 0.8 7.5 7.5 EEUFC2A181( ) 100 250 220 12.5 35 1040 0.087 5000 0.8 5.0 EEUFC2A221L 100 16 25 1170 0.089 5000 0.8 7.5 7.5 EEUFC2A221( ) 100 250 270 12.5 40 1130 0.072 5000 0.8 5.0 EEUFC2A271L 100 18 20 1230 0.080 5000 0.8 7.5 7.5 EEUFC2A271S( ) 100 250 330 16 31.5 1520 0.062 5000 0.8 7.5 EEUFC2A331 100 18 25 1420 0.070 5000 0.8 7.5 7.5 EEUFC2A331S( ) 100 250 390 16 35.5 1730 0.053 5000 0.8 7.5 EEUFC2A391L 100 18 31.5 1600 0.062 5000 0.8 7.5 EEUFC2A391 50 470 16 40 1920 0.047 5000 0.8 7.5 EEUFC2A471 100 560 18 35.5 1770 0.041 5000 0.8 7.5 EEUFC2A561 50 680 18 40 2300 0.036 5000 0.8 7.5 EEUFC2A681 50 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. Endurance : 105 °C 04 to 06.3=1000 h, 08=2000 h, 010=3000 h, 012.5 to 018=5000 h 01 Oct. 2013 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. 􀊵 􀀧􀀤􀀘􀀔 􀊵 Plastic Film Capacitors Metallized Polypropylene Film Capacitors Type: EZPE Series ■Features •High safety, Self-healing and Self-protecting function built-in •Long product life, High reliability •Low loss, Low ESR •Flame retardant (Case and sealing resin) •RoHS directive compliant ■Recommended Applications For DC filtering, DC link circuit •Solar inverters •Wind power generation •Industrial power supplies •Inverter circuit in appliances (Air Conditioners etc.) ■Construction •Dielectric : Polypropylene film •Electrodes : Metallized dielectric with segmented pattern •Plastic case : UL94 V-0 •Sealing : UL94 V-0 •Terminals : Tinned wires,2-pin and 4-pin versions ■Explanation of Part Numbers 1 2 3 4 5 6 7 8 9 10 11 12 E Z P E Product code Dielectric & construction Rated voltage Capacitance T Pin type Suffix A Suffix 50 500 VDC 80 800 VDC 1B 1100 VDC 1D 1300 VDC L 2-pin type M 4-pin type ■Specifications Category temperature range (TC) (*1) Rated voltage(VR) (*2) Rated capacitance (CR) Capacitance tolerance Withstanding DC voltage Insulation resistance (CR) –40 °C to +85 °C 500 VDC, 800 VDC, 1100 VDC, 1300 VDC (Derating of rated voltage by more than 70 °C (*3)) 500 VDC 800 VDC 1100 VDC 1300 VDC 10 μF to 110 μF 10 μF to 60 μF 10 μF to 40 μF 10 μF to 25 μF ±10 % Between terminals:Rated voltage. (VDC)✕150 % 10 s Terminal to case:2110 VAC 10 s CR>=10000 Ω · F (20 °C, 500 VDC, 60 s) *1:The temperature of capacitor surface (case) *2:Use for DC voltage only *3:Refer to the page of “ DC voltage derating ” Metallized Film Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. 􀊵 􀀧􀀤􀀘􀀕 􀊵 Plastic Film Capacitors ■Dimensions in mm (not to scale) 􀀮􀁂􀁓􀁌􀁊􀁏􀁈􀀁 􀀱􀀒􀊶􀀒􀀁 􀀭􀊶􀀑􀀏􀀖􀀁 􀀱􀀓􀊶􀀒􀀁 􀐟􀊶􀀑􀀏􀀓􀀁 􀀕􀀏􀀑􀊶􀀓􀀏􀀑􀀁 􀀸􀊶􀀑􀀏􀀖􀀁 􀀩􀊶􀀑􀀏􀀖􀀁 􀀮􀁂􀁓􀁌􀁊􀁏􀁈􀀁 􀀱􀀒􀊶􀀒􀀁 􀀕􀀏􀀑􀊶􀀓􀀏􀀑􀀁 􀀩􀊶􀀑􀀏􀀖􀀁 􀐟􀊶􀀑􀀏􀀓􀀁 􀀭􀊶􀀑􀀏􀀖􀀁 􀀸􀊶􀀑􀀏􀀖􀀁 􀀥􀀤􀀁 􀀉􀁂􀀊􀀁 􀀷􀀁 􀐖􀀧􀀁 􀀉􀁂􀀊􀉹􀀳􀁂􀁕􀁆􀁅􀀁􀁗􀁐􀁍􀁕􀁂􀁈􀁆 􀀉􀁃􀀊􀉹􀀤􀁂􀁑􀁂􀁄􀁊􀁕􀁂􀁏􀁄􀁆 􀀉􀁄􀀊􀀁 􀀉􀁄􀀊􀉹􀀭􀁐􀁕􀀁􀀯􀁐􀀏􀀁 􀀉􀁃􀀊􀀁 􀀱􀁂􀁏􀁂􀁔􀁐􀁏􀁊􀁄􀀁 􀀮􀁂􀁓􀁌􀁊􀁏􀁈􀀉􀁆􀁙􀀏􀀊􀀁 ■Rating, Dimensions & Quantity / Ammo Box ●Type EZPE Rated voltage : 500 VDC at 70 􀋆 ( 450VDC at 85 􀋆 ) EZPE50106LTA 10 20 42 41.5 37.5 - 1.2 21 210 5.0 22.0 0.28 45 EZPE50156LTA 15 20 42 41.5 37.5 - 1.2 21 315 7.5 14.8 0.28 45 EZPE50206LTA 20 20 42 41.5 37.5 - 1.2 21 420 9.5 11.0 0.28 44 EZPE50256LTA 25 20 42 41.5 37.5 - 1.2 21 525 11.0 8.8 0.28 43 EZPE50306MTA 30 20 42 41.5 37.5 10.2 1.2 21 630 12.5 7.0 0.28 43 EZPE50356MTA 35 30 51 41.5 37.5 10.2 1.2 21 735 13.5 6.2 0.28 83 EZPE50406MTA 40 30 51 41.5 37.5 10.2 1.2 21 840 14.5 5.4 0.28 82 EZPE50456MTA 45 30 51 41.5 37.5 10.2 1.2 21 945 15.2 4.9 0.28 81 EZPE50506MTA 50 30 51 41.5 37.5 20.3 1.2 21 1050 16.0 4.4 0.28 80 EZPE50556MTA 55 30 51 41.5 37.5 20.3 1.2 21 1155 16.3 4.1 0.28 79 EZPE50606MTA 60 30 51 41.5 37.5 20.3 1.2 21 1260 16.5 3.9 0.28 77 EZPE50656MTA 65 30 51 57.5 52.5 10.2 1.2 14 910 15.0 6.8 0.44 111 EZPE50706MTA 70 30 51 57.5 52.5 10.2 1.2 14 980 15.5 6.5 0.44 109 EZPE50756MTA 75 30 51 57.5 52.5 20.3 1.2 14 1050 16.0 6.0 0.44 108 EZPE50806MTA 80 30 51 57.5 52.5 20.3 1.2 14 1120 16.5 5.7 0.44 106 EZPE50856MTA 85 35 56 57.5 52.5 20.3 1.2 14 1190 16.7 5.4 0.44 142 EZPE50906MTA 90 35 56 57.5 52.5 20.3 1.2 14 1260 17.0 5.1 0.44 141 EZPE50956MTA 95 35 56 57.5 52.5 20.3 1.2 14 1330 17.5 4.9 0.44 140 EZPE50107MTA 100 35 56 57.5 52.5 20.3 1.2 14 1400 18.0 4.7 0.44 139 EZPE50117MTA 110 35 56 57.5 52.5 20.3 1.2 14 1540 18.5 4.4 0.44 138 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 600 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) *1:When rising temperature of capacitor surface by continuous peak current (included pulse current), use within limit specified for temperature of capacitor surface and self heating temperature rise. *2:Maximum RMS current @ 70 􀋆, 10 kHz Use within limit for self heating temperature rise at capacitor surface. *3:Typical values @ 20􀋆, 10 kHz ESR : less than 2.5 􀊷 ESRtyp *4:Maximum dissipation factor @20􀋆, 1 kHz *5:Minimum order quantity consists of 4 packing units. Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. 􀊵 􀀧􀀤􀀘􀀖 􀊵 Plastic Film Capacitors ■Rating, Dimensions & Quantity / Ammo Box ●Type EZPE Rated voltage : 800 VDC at 70 􀋆 ( 700VDC at 85 􀋆 ) EZPE80106LTA 10 20 42 41.5 37.5 - 1.2 22 220 7.0 15.8 0.22 44 EZPE80156MTA 15 20 42 41.5 37.5 10.2 1.2 22 330 9.0 10.5 0.22 43 EZPE80206MTA 20 30 51 41.5 37.5 10.2 1.2 22 440 11.0 7.7 0.22 82 EZPE80256MTA 25 30 51 41.5 37.5 10.2 1.2 22 550 13.0 6.4 0.22 80 EZPE80306MTA 30 30 51 41.5 37.5 20.3 1.2 22 660 15.0 5.3 0.22 78 EZPE80356MTA 35 30 51 57.5 52.5 10.2 1.2 15 525 12.0 9.7 0.33 110 EZPE80406MTA 40 30 51 57.5 52.5 20.3 1.2 15 600 13.0 8.3 0.33 107 EZPE80456MTA 45 30 51 57.5 52.5 20.3 1.2 15 675 14.0 7.0 0.33 104 EZPE80506MTA 50 35 56 57.5 52.5 20.3 1.2 15 750 15.0 6.3 0.33 140 EZPE80556MTA 55 35 56 57.5 52.5 20.3 1.2 15 825 16.0 5.9 0.33 138 EZPE80606MTA 60 35 56 57.5 52.5 20.3 1.2 15 900 17.0 5.6 0.33 136 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 600 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) ●Type EZPE Rated voltage : 1100 VDC at 70 􀋆 ( 920VDC at 85 􀋆 ) EZPE1B106MTA 10 20 42 41.5 37.5 10.2 1.2 54 540 7.0 12.3 0.20 43 EZPE1B156MTA 15 30 51 41.5 37.5 10.2 1.2 54 810 8.5 8.2 0.20 80 EZPE1B206MTA 20 30 51 41.5 37.5 20.3 1.2 54 1080 10.0 6.3 0.20 76 EZPE1B256MTA 25 30 51 57.5 52.5 10.2 1.2 35 875 8.0 10.7 0.28 107 EZPE1B306MTA 30 30 51 57.5 52.5 20.3 1.2 35 1050 9.0 8.5 0.28 103 EZPE1B356MTA 35 35 56 57.5 52.5 20.3 1.2 35 1225 10.0 7.2 0.28 137 EZPE1B406MTA 40 35 56 57.5 52.5 20.3 1.2 35 1400 11.0 6.5 0.28 134 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 600 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) ●Type EZPE Rated voltage : 1300 VDC at 70 􀋆 ( 1100VDC at 85 􀋆 ) EZPE1D106MTA 10 30 51 41.5 37.5 10.2 1.2 73 730 12.0 10.0 0.17 80 EZPE1D156MTA 15 30 51 57.5 52.5 10.2 1.2 50 750 10.0 14.5 0.22 109 EZPE1D206MTA 20 30 51 57.5 52.5 20.3 1.2 50 1000 14.0 11.1 0.22 103 EZPE1D256MTA 25 35 56 57.5 52.5 20.3 1.2 50 1250 17.0 8.5 0.22 136 Part No. Dimensions (mm) Permissible current W H L P1 P2 􀐟 400 200 ESRtyp [m􀐊] (*3) tan􀐎 [%] (*4) Mass [􀌶] MOQ [pcs] (*5) dv/dt [V/μs] Peak Current [Ao-p] (*1) RMS Current [Arms] (*2) CR. (μF) *1:When rising temperature of capacitor surface by continuous peak current (included pulse current), use within limit specified for temperature of capacitor surface and self heating temperature rise. *2:Maximum RMS current @ 70 􀋆, 10 kHz Use within limit for self heating temperature rise at capacitor surface. *3:Typical values @ 20􀋆, 10 kHz ESR : less than 2.5 􀊷 ESRtyp *4:Maximum dissipation factor @20􀋆, 1 kHz *5:Minimum order quantity consists of 4 packing units. Metallized Film Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Permissible Conditions ●Permissible Voltage ・These capacitors are designed only for DC voltage, so should not be used for AC line. ・Use the peak voltage (Vo-p) within the rated voltage. ・Use the peak to peak voltage (Vp-p) within 0.2 x VR . ●DC Voltage, Peak current and RMS current derating Derating of voltage (Vo-p), RMS current (Arms), and peak current (Ao-p) according to the following diagram when the temperature of the capacitor surface exceeds 70 ℃. ●Permissible self heating temperature rise ●Total cycles applied peak current 60 65 70 75 80 85 90 95 100 Voltage ① Voltage ② Permissible voltage (Vo-p) Temperature of capacitor surface TC (℃) DC Voltage derating Percentage to the permissible current (%) Current derating Temperature of capacitor surface TC (℃) Total cycles applied peak current (Ao-p) (including pulse current) are within following diagram. Permissible self heating temperature rise is within following diagram when the temperature of the capacitor surface exceeds 70 ℃. Please consult Panasonic if your condition exceeds the above spec. Vp-p = 0.2 × VR VR ≧ Vo-p Vo 0% 20% 40% 60% 80% 100% 120% 60 65 70 75 80 85 90 95 100 Part Number Voltage ① Voltage ② EZPE50 □□□□ TA DC500V DC450V EZPE80 □□□□ TA DC800V DC700V EZPE1B □□□□ TA DC1100V DC920V EZPE1D □□□□ TA DC1300V DC1100V Total cycles Percentage to the permissible peak current (%) Permissible self temp. rise(℃) Temperature of capacitor surface TC (℃) 0% 20% 40% 60% 80% 100% 120% 60 65 70 75 80 85 90 95 100 0% 20% 40% 60% 80% 100% 10 100 1000 10000 100000 Part Number 100% at70℃ 36% at85℃ EZPE50 □□□□ TA 12 ℃ 4.3 ℃ EZPE80 □□□□ TA 10 ℃ 3.6 ℃ EZPE1B □□□□ TA 5 ℃ 1.8 ℃ EZPE1D □□□□ TA 9 ℃ 3.2 ℃ Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 500 VDC at 70 ℃ ( 450VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 60uF 20uF 110uF 100uF Dissipation factor (typical curve) tanδ (%) Temperature (℃) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) Permissible voltage (Vo-p) Lifetime expectancy (h) Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 20uF 60uF 110uF 200 250 300 350 400 450 500 550 1000 10000 100000 1000000 Tc=85℃ Tc=105℃ (I=0Arms) Tc=70℃ Unpredictable life time area Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 800 VDC at 70 ℃ ( 700VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 30uF 10uF 60uF 45uF Dissipation factor (typical curve) tanδ (%) Temperature (℃) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 30uF 10uF 45uF 60uF Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) 300 400 500 600 700 800 900 1000 10000 100000 1000000 Tc=85℃ Tc=105℃ (I=0Arms) Tc=70℃ Unpredictable life time area Permissible voltage (Vo-p) Lifetime expectancy (h) Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 1100 VDC at 70 ℃ ( 920VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy at 1kHz 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 20uF 10uF 40uF Dissipation factor (typical curve) tanδ (%) Temperature (℃) -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 20uF 10uF 40uF Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) 400 500 600 700 800 900 1000 1100 1200 1000 10000 100000 1000000 Unpredictable life time area Tc=85℃ Tc=105℃ ( I = 0Arms) Tc=70℃ Permissible voltage (Vo-p) Lifetime expectancy (h) Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage Plastic Film Capacitors Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. ■Characteristics <Reference> ●Type EZPE Rated voltage : 1300 VDC at 70 ℃ ( 1100VDC at 85 ℃ ) ●Temperature Characteristics ●Frequency Characteristics ●Lifetime expectancy -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 120 ⊿C/C (%) Temperature (℃) Capacitance (typical curve) at 1kHz Dissipation factor (typical curve) tanδ (%) Temperature (℃) at 1kHz 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 -60 -40 -20 0 20 40 60 80 100 120 C・R (Ω・F) Temperature (℃) at 500VDC Insulation resistance (typical curve) Impedance vs. Frequency (typical curve) Impedance (Ω) Frequency (kHz) Permissible voltage (Vo-p) Lifetime expectancy (h) 500 600 700 800 900 1000 1100 1200 1300 1400 1000 10000 100000 1000000 Unpredictable life time area Tc=85℃ Tc=105℃ (I=0Arms) Tc=70℃ 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -60 -40 -20 0 20 40 60 80 100 120 25uF 15uF 10uF 0.001 0.01 0.1 1 10 100 1 10 100 1000 10000 10uF 15uF 25uF Lifetime expectancy (Reference) * Life time : Reach ⊿C/C = - 10 % , Judgement of Panasonic * 105℃ : Not guarantee voltage Panasonic Corporation Automation Controls Business Division industrial.panasonic.com/ac/e/ AYF33 ACCTB47E 201303-T ORDERING INFORMATION For FPC Y3B/Y3BW Series FPC connectors (0.3mm pitch) Back lock Y3BW is added. FEATURES 1. Slim and low profile design (Pitch: 0.3 mm) Back lock type and the slim body with a 3.15 mm depth (with the lever). 2. Mechanical design freedom is achieved with double top and bottom contacts Top and bottom double contacts eliminate the need of using different connectors (with either top or bottom contacts) depending on the FPC wiring conditions. 3. Easy-to-handle back lock structure 4. Man-hours of assembly time can be reduced by delivering the connectors with their levers opened. 5. Wiring patterns can be placed underneath the connector. 6. Ni barrier with high resistance to solder creepage 7. Y3BW features advanced functionality, including a structure to temporarily hold the FPC and a higher holding force. The FPC holding contacts located on both ends of the connector facilitate positioning of FPC and further enhance the FPC holding force. (1) The inserted FPC can be temporarily held until the lever is closed. (2) When the lever is closed, the holding contacts lock the FPC by its notches, enhancing the FPC holding force. APPLICATIONS Mobile devices, such as cellular phones, smartphones, digital still cameras and digital video cameras. Y3B Y3BW RoHS compliant Unit: mm 0.9 3.15 Structure to lock notches on both ends of the FPC with holding contacts Applicable FPC shapes New 33: FPC Connector 0.3 mm pitch (Back lock) AYF 3 3 5 Number of pins (2 digits) Contact direction 3: Top and bottom double contacts (Y3B) 6: Top and bottom double contacts, lock holding type (Y3BW) Surface treatment (Contact portion / Terminal portion) 5: Au plating/Au plating (Ni barrier) Panasonic Corporation Automation Controls Business Unit industrial.panasonic.com/ac/e/ GN (AGN) ASCTB13E 201209-T ORDERING INFORMATION High Sensitivity, with 100mW nominal operating power, in a compact and space saving case GN RELAYS (AGN) RoHS compliant FEATURES 1. Compact slim body saves space Thanks to the small surface area of 5.7 mm × 10.6 mm .224 inch × .417 inch and low height of 9.0 mm .354 inch, the packaging density can be increased to allow for much smaller designs. 2. High sensitivity single side stable type (Nominal operating power: 100mW) is available 3. Outstanding surge resistance. Surge breakdown voltage between contacts and coil: 2,500 V 2×10 μs (Telcordia) Surge breakdown voltage between open contacts: 1,500 V 10×160 μs (FCC part 68) 4. The use of twin crossbar contacts ensures high contact reliability. AgPd contact is used because of its good sulfide resistance. Adopting lowgas molding material. Coil assembly molding technology which avoids generating volatile gas from coil. 5. Increased packaging density Due to highly efficient magnetic circuit design, leakage flux is reduced and changes in electrical characteristics from components being mounted close-together are minimized. This all means a packaging density higher than ever before. 6. Nominal operating power: 140 mW 7. Outstanding vibration and shock resistance. Functional shock resistance: 750 m/s2 Destructive shock resistance: 1,000 m/s2 Functional vibration resistance: 10 to 55 Hz (at double amplitude of 3.3 mm .130 inch) Destructive vibration resistance: 10 to 55 Hz (at double amplitude of 5 mm .197 inch) 8. Sealed construction allows automatic washing. TYPICAL APPLICATIONS 1. Telephonic equipment 2. Telecommunications equipment 3. Security equipment 4. Test and Measurement equipment 5. Electronic Consumer and Audio Visual equipment Nominal coil voltage (DC) 1H: 1.5V 03: 3V 4H: 4.5V 06: 6V 09: 9V 12: 12V 24: 24V Contact arrangement 2: 2 Form C Type of operation 0: Standard type (B.B.M.) AGN 2 0 Operating function 0: Single side stable 1: 1 coil latching 6: High sensitivity single side stable type Terminal shape Nil: A: S: Standard PC board terminal Surface-mount terminal A type Surface-mount terminal S type Packing style Nil: X: Z: Tube packing Tape and reel packing (picked from 1/2/3/4 pin side) Tape and reel packing (picked from 5/6/7/8 pin side) Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-99 – 05 to 08 0D±0.5 0d±0.05 F±0.5 Sleeve L􀀽 14 min. 3 min. 􀀽􀀀L􀀝16 : L±1.0 L􀀟20 : L±2.0 Pressure relief 06.3􀀝 + – 010􀀝 0D±0.5 ■ Features ● Endurance : 105 °C 1000 h to 2000 h ● RoHS directive compliant Radial Lead Type Series: NHG Type: A ■ Specifi cations Category Temp. Range –55 °C to +105 °C –25 °C to +105 °C Rated W.V. Range 6.3 V.DC to 100 V.DC 160 V.DC to 450 V.DC Nominal Cap. Range 2.2 μF to 22000 μF 1 μF to 330 μF Capacitance Tolerance ±20 % (120 Hz/+20 °C) DC Leakage Cur rent I < 0.01 CV or 3 (μA) After 2 minutes (Which is greater) I < 0.06 CV +10 (μA) After 2 minutes tan d Please see the attached standard products list Endurance After following life test with DC voltage and +105 °C±2 °C ripple current value applied (The sum of DC and ripple peak voltage shall not exceed the rated working voltage), When the capacitors are restored to 20 °C, the capacitors shall meet the limits specifi ed below. Duration : 6.3 V.DC to 100 V.DC : (05 to 08)=1000 hours, (010 to 018)=2000 hours 160 V.DC to 450 V.DC : 2000 hours Capacitance change ±20 % of initial measured value tan d < 200 % of initial specifi ed value DC leakage current < initial specifi ed value Shelf Life After storage for 1000 hours at +105 °C±2 °C with no voltage applied and then being stabilized at +20 °C, capacitors shall meet the limits specifi ed in Endurance. (With voltage treatment) ■ Di men sions in mm (not to scale) W.V.(V.DC) Cap. (μF) Frequency (Hz) 60 120 1 k 10 k 100 k 6.3 to 100 2.2 to 33 0.75 1.00 1.55 1.80 2.00 47 to 470 0.80 1.00 1.35 1.50 1.50 1000 to 22000 0.85 1.00 1.10 1.15 1.15 160 to 450 1 to 330 0.80 1.00 1.35 1.50 1.50 ■ Frequency correction factor for ripple current Body Dia. 0D 5 6.3 8 10 12.5 16 18 Lead Dia. 0d 0.5 0.5 0.6 0.6 0.6 0.8 0.8 Lead space F 2.0 2.5 3.5 5.0 5.0 7.5 7.5 (Unit : mm) 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-100 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 6.3 220 5 11 140 0.28 1000 0.5 2.0 5.0 2.5 ECA0JHG221( ) 200 2000 470 6.3 11.2 230 0.28 1000 0.5 2.5 5.0 2.5 ECA0JHG471( ) 200 2000 1000 8 11.5 380 0.28 1000 0.6 3.5 5.0 ECA0JHG102( ) 200 1000 2200 10 16 710 0.30 2000 0.6 5.0 5.0 ECA0JHG222( ) 200 500 3300 10 20 840 0.32 2000 0.6 5.0 5.0 ECA0JHG332( ) 200 500 4700 12.5 20 1090 0.34 2000 0.6 5.0 5.0 ECA0JHG472( ) 200 500 6800 12.5 25 1350 0.38 2000 0.6 5.0 5.0 ECA0JHG682( ) 200 500 10000 16 25 1650 0.46 2000 0.8 7.5 7.5 ECA0JHG103( ) 100 250 15000 16 31.5 2010 0.56 2000 0.8 7.5 ECA0JHG153 100 22000 18 35.5 2350 0.70 2000 0.8 7.5 ECA0JHG223 50 10 330 6.3 11.2 200 0.24 1000 0.5 2.5 5.0 2.5 ECA1AHG331( ) 200 2000 470 8 11.5 250 0.24 1000 0.6 3.5 5.0 ECA1AHG471( ) 200 1000 1000 10 12.5 460 0.24 2000 0.6 5.0 5.0 ECA1AHG102( ) 200 500 2200 10 20 760 0.26 2000 0.6 5.0 5.0 ECA1AHG222( ) 200 500 3300 12.5 20 1000 0.28 2000 0.6 5.0 5.0 ECA1AHG332( ) 200 500 4700 12.5 25 1260 0.30 2000 0.6 5.0 5.0 ECA1AHG472( ) 200 500 6800 16 25 1570 0.34 2000 0.8 7.5 7.5 ECA1AHG682( ) 100 250 10000 16 31.5 1890 0.42 2000 0.8 7.5 ECA1AHG103 100 15000 18 35.5 2180 0.52 2000 0.8 7.5 ECA1AHG153 50 16 100 5 11 110 0.20 1000 0.5 2.0 5.0 2.5 ECA1CHG101( ) 200 2000 220 6.3 11.2 180 0.20 1000 0.5 2.5 5.0 2.5 ECA1CHG221( ) 200 2000 330 8 11.5 260 0.20 1000 0.6 3.5 5.0 ECA1CHG331( ) 200 1000 470 8 11.5 310 0.20 1000 0.6 3.5 5.0 ECA1CHG471( ) 200 1000 1000 10 16 560 0.20 2000 0.6 5.0 5.0 ECA1CHG102( ) 200 500 2200 12.5 20 920 0.22 2000 0.6 5.0 5.0 ECA1CHG222( ) 200 500 3300 12.5 25 1170 0.24 2000 0.6 5.0 5.0 ECA1CHG332( ) 200 500 4700 16 25 1480 0.26 2000 0.8 7.5 7.5 ECA1CHG472( ) 100 250 6800 16 31.5 1780 0.30 2000 0.8 7.5 ECA1CHG682 100 10000 18 35.5 2060 0.38 2000 0.8 7.5 ECA1CHG103 50 25 47 5 11 91 0.16 1000 0.5 2.0 5.0 2.5 ECA1EHG470( ) 200 2000 100 6.3 11.2 130 0.16 1000 0.5 2.5 5.0 2.5 ECA1EHG101( ) 200 2000 220 8 11.5 230 0.16 1000 0.6 3.5 5.0 ECA1EHG221( ) 200 1000 330 8 11.5 310 0.16 1000 0.6 3.5 5.0 ECA1EHG331( ) 200 1000 470 10 12.5 380 0.16 2000 0.6 5.0 5.0 ECA1EHG471( ) 200 500 1000 10 20 680 0.16 2000 0.6 5.0 5.0 ECA1EHG102( ) 200 500 2200 12.5 25 1090 0.18 2000 0.6 5.0 5.0 ECA1EHG222( ) 200 500 3300 16 25 1400 0.20 2000 0.8 7.5 7.5 ECA1EHG332( ) 100 250 4700 16 31.5 1750 0.22 2000 0.8 7.5 ECA1EHG472 100 6800 18 35.5 2040 0.26 2000 0.8 7.5 ECA1EHG682 50 35 47 5 11 90 0.14 1000 0.5 2.0 5.0 2.5 ECA1VHG470( ) 200 2000 100 6.3 11.2 150 0.14 1000 0.5 2.5 5.0 2.5 ECA1VHG101( ) 200 2000 220 8 11.5 270 0.14 1000 0.6 3.5 5.0 ECA1VHG221( ) 200 1000 330 10 12.5 350 0.14 2000 0.6 5.0 5.0 ECA1VHG331( ) 200 500 470 10 16 460 0.14 2000 0.6 5.0 5.0 ECA1VHG471( ) 200 500 1000 12.5 20 810 0.14 2000 0.6 5.0 5.0 ECA1VHG102( ) 200 500 2200 16 25 1260 0.16 2000 0.8 7.5 7.5 ECA1VHG222( ) 100 250 3300 16 31.5 1610 0.18 2000 0.8 7.5 ECA1VHG332 100 4700 18 35.5 1910 0.20 2000 0.8 7.5 ECA1VHG472 50 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-101 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 50 0.1 5 11 1.1 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG0R1( )✽✽✽ 200 2000 0.22 5 11 2.3 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHGR22( )✽✽✽ 200 2000 0.33 5 11 3.5 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHGR33( )✽✽✽ 200 2000 0.47 5 11 5 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHGR47( )✽✽✽ 200 2000 1 5 11 10 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG010( )✽✽✽ 200 2000 2.2 5 11 18 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG2R2( ) 200 2000 3.3 5 11 22 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG3R3( ) 200 2000 4.7 5 11 26 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG4R7( ) 200 2000 10 5 11 39 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG100( ) 200 2000 22 5 11 65 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG220( ) 200 2000 33 5 11 90 0.12 1000 0.5 2.0 5.0 2.5 ECA1HHG330( ) 200 2000 47 6.3 11.2 110 0.12 1000 0.5 2.5 5.0 2.5 ECA1HHG470( ) 200 2000 100 8 11.5 180 0.12 1000 0.6 3.5 5.0 ECA1HHG101( ) 200 1000 220 10 12.5 300 0.12 2000 0.6 5.0 5.0 ECA1HHG221( ) 200 500 330 10 16 410 0.12 2000 0.6 5.0 5.0 ECA1HHG331( ) 200 500 470 10 20 530 0.12 2000 0.6 5.0 5.0 ECA1HHG471( ) 200 500 1000 12.5 25 950 0.12 2000 0.6 5.0 5.0 ECA1HHG102( ) 200 500 2200 16 31.5 1470 0.14 2000 0.8 7.5 ECA1HHG222 100 3300 18 35.5 1770 0.16 2000 0.8 7.5 ECA1HHG332 50 63 10 5 11 46 0.10 1000 0.5 2.0 5.0 2.5 ECA1JHG100( ) 200 2000 22 5 11 71 0.10 1000 0.5 2.0 5.0 2.5 ECA1JHG220( ) 200 2000 33 6.3 11.2 100 0.10 1000 0.5 2.5 5.0 2.5 ECA1JHG330( ) 200 2000 47 6.3 11.2 120 0.10 1000 0.5 2.5 5.0 2.5 ECA1JHG470( ) 200 2000 100 10 12.5 215 0.10 2000 0.6 5.0 5.0 ECA1JHG101( ) 200 500 220 10 16 335 0.10 2000 0.6 5.0 5.0 ECA1JHG221( ) 200 500 330 10 20 510 0.10 2000 0.6 5.0 5.0 ECA1JHG331( ) 200 500 470 12.5 20 640 0.10 2000 0.6 5.0 5.0 ECA1JHG471( ) 200 500 1000 16 25 930 0.10 2000 0.8 7.5 7.5 ECA1JHG102( ) 100 250 2200 18 35.5 1610 0.12 2000 0.8 7.5 ECA1JHG222 50 100 0.47 5 11 9 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHGR47( )✽✽✽ 200 2000 1 5 11 14 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG010( )✽✽✽ 200 2000 2.2 5 11 21 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG2R2( ) 200 2000 3.3 5 11 31 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG3R3( ) 200 2000 4.7 5 11 38 0.08 1000 0.5 2.0 5.0 2.5 ECA2AHG4R7( ) 200 2000 10 6.3 11.2 54 0.08 1000 0.5 2.5 5.0 2.5 ECA2AHG100( ) 200 2000 22 6.3 11.2 93 0.08 1000 0.5 2.5 5.0 2.5 ECA2AHG220( ) 200 2000 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. ✽✽✽ Please kindly accept last shipment : 31/Mar/2015 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-102 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 100 33 8 11.5 130 0.08 1000 0.6 3.5 5.0 ECA2AHG330( ) 200 1000 47 10 12.5 165 0.08 2000 0.6 5.0 5.0 ECA2AHG470( ) 200 500 100 10 20 265 0.08 2000 0.6 5.0 5.0 ECA2AHG101( ) 200 500 220 12.5 25 440 0.08 2000 0.6 5.0 5.0 ECA2AHG221( ) 200 500 330 16 25 540 0.08 2000 0.8 7.5 7.5 ECA2AHG331( ) 100 250 470 16 25 715 0.08 2000 0.8 7.5 7.5 ECA2AHG471( ) 100 250 1000 18 35.5 985 0.08 2000 0.8 7.5 ECA2AHG102 50 160 1 6.3 11.2 17 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG010( ) 200 2000 2.2 6.3 11.2 25 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG2R2( ) 200 2000 3.3 6.3 11.2 36 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG3R3( ) 200 2000 4.7 6.3 11.2 43 0.15 2000 0.5 2.5 5.0 2.5 ECA2CHG4R7( ) 200 2000 10 10 12.5 70 0.15 2000 0.6 5.0 5.0 ECA2CHG100( ) 200 500 22 10 20 130 0.15 2000 0.6 5.0 5.0 ECA2CHG220( ) 200 500 33 10 20 180 0.15 2000 0.6 5.0 5.0 ECA2CHG330( ) 200 500 47 12.5 20 220 0.15 2000 0.6 5.0 5.0 ECA2CHG470( ) 200 500 100 16 25 335 0.15 2000 0.8 7.5 7.5 ECA2CHG101( ) 100 250 220 16 31.5 540 0.15 2000 0.8 7.5 ECA2CHG221 100 330 18 31.5 705 0.15 2000 0.8 7.5 ECA2CHG331 50 200 1 6.3 11.2 17 0.15 2000 0.5 2.5 5.0 2.5 ECA2DHG010( ) 200 2000 2.2 6.3 11.2 25 0.15 2000 0.5 2.5 5.0 2.5 ECA2DHG2R2( ) 200 2000 3.3 6.3 11.2 36 0.15 2000 0.5 2.5 5.0 2.5 ECA2DHG3R3( ) 200 2000 4.7 8 11.5 50 0.15 2000 0.6 3.5 5.0 ECA2DHG4R7( ) 200 1000 10 10 16 80 0.15 2000 0.6 5.0 5.0 ECA2DHG100( ) 200 500 22 10 20 140 0.15 2000 0.6 5.0 5.0 ECA2DHG220( ) 200 500 33 12.5 20 190 0.15 2000 0.6 5.0 5.0 ECA2DHG330( ) 200 500 47 12.5 20 220 0.15 2000 0.6 5.0 5.0 ECA2DHG470( ) 200 500 100 16 25 335 0.15 2000 0.8 7.5 7.5 2.5 ECA2DHG101( ) 100 250 220 18 31.5 575 0.15 2000 0.8 7.5 ECA2DHG221 50 250 1 6.3 11.2 17 0.15 2000 0.5 2.5 5.0 2.5 ECA2EHG010( ) 200 2000 2.2 6.3 11.2 29 0.15 2000 0.5 2.5 5.0 2.5 ECA2EHG2R2( ) 200 2000 3.3 8 11.5 42 0.15 2000 0.6 3.5 5.0 ECA2EHG3R3 200 1000 4.7 8 11.5 50 0.15 2000 0.6 3.5 5.0 ECA2EHG4R7( ) 200 1000 10 10 16 88 0.15 2000 0.6 5.0 5.0 ECA2EHG100( ) 200 500 22 12.5 20 155 0.15 2000 0.6 5.0 5.0 ECA2EHG220( ) 200 500 33 12.5 20 190 0.15 2000 0.6 5.0 5.0 ECA2EHG330( ) 200 500 47 12.5 25 230 0.15 2000 0.6 5.0 5.0 ECA2EHG470( ) 200 500 100 16 31.5 365 0.15 2000 0.8 7.5 ECA2EHG101 100 350 1 6.3 11.2 18 0.20 2000 0.5 2.5 5.0 2.5 ECA2VHG010( ) 200 2000 2.2 8 11.5 31 0.20 2000 0.6 3.5 5.0 ECA2VHG2R2( ) 200 1000 3.3 10 12.5 38 0.20 2000 0.6 5.0 5.0 ECA2VHG3R3( ) 200 500 4.7 10 16 50 0.20 2000 0.6 5.0 5.0 ECA2VHG4R7( ) 200 500 10 10 20 82 0.20 2000 0.6 5.0 5.0 ECA2VHG100( ) 200 500 22 12.5 20 130 0.20 2000 0.6 5.0 5.0 ECA2VHG220( ) 200 500 33 16 25 195 0.20 2000 0.8 7.5 7.5 ECA2VHG330( ) 100 250 47 16 25 230 0.20 2000 0.8 7.5 7.5 ECA2VHG470( ) 100 250 100 18 31.5 375 0.20 2000 0.8 7.5 ECA2VHG101 50 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. 01 Oct. 2013 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ NHG – EEE-103 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (120 Hz) (+105 °C) tan d (120 Hz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽i (V) (μF) (mm) (mm) (mA r.m.s.) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 400 1 6.3 11.2 18 0.24 2000 0.5 2.5 5.0 2.5 ECA2GHG010( ) 200 2000 2.2 8 11.5 30 0.24 2000 0.6 3.5 5.0 ECA2GHG2R2( ) 200 1000 3.3 10 12.5 40 0.24 2000 0.6 5.0 5.0 ECA2GHG3R3( ) 200 500 4.7 10 16 50 0.24 2000 0.6 5.0 5.0 ECA2GHG4R7( ) 200 500 10 10 20 80 0.24 2000 0.6 5.0 5.0 ECA2GHG100( ) 200 500 22 12.5 25 145 0.24 2000 0.6 5.0 5.0 ECA2GHG220( ) 200 500 33 16 25 195 0.24 2000 0.8 7.5 7.5 ECA2GHG330( ) 100 250 47 16 31.5 250 0.24 2000 0.8 7.5 ECA2GHG470 100 450 1 8 11.5 18 0.24 2000 0.6 3.5 5.0 ECA2WHG010( ) 200 1000 2.2 10 12.5 29 0.24 2000 0.6 5.0 5.0 ECA2WHG2R2( ) 200 500 3.3 10 16 41 0.24 2000 0.6 5.0 5.0 ECA2WHG3R3( ) 200 500 4.7 10 20 49 0.24 2000 0.6 5.0 5.0 ECA2WHG4R7( ) 200 500 10 12.5 20 75 0.24 2000 0.6 5.0 5.0 ECA2WHG100( ) 200 500 22 16 25 115 0.24 2000 0.8 7.5 7.5 ECA2WHG220( ) 100 250 33 16 31.5 155 0.24 2000 0.8 7.5 ECA2WHG330 100 · When requesting taped product, please put the letter "B" or "i" between the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, i=2.5 mm. · Please refer to the page of “Taping Dimensions”. 01 Oct. 2013  Highest ripple current capability for demanding inverter applications  2 and 3 pin versions available  3000 hour life at 105ºC Part Number System Voltage Capacitance Code Code 2 3 4.0mm 4.0mm H P J Q K R L S TS-ED Standard Ratings (part numbers shown with 6.3mm length terminal and top vinyl plate) Cap. Panasonic Cap. Panasonic (μF) 120Hz 10kHz~ 120Hz 20kHz Part Number (μF) 120Hz 10kHz~ 120Hz 20kHz Part Number 270 22 x 25 1.42 2.03 0.553 0.249 EETED2D271BA 390 22 x 40 1.72 2.45 0.383 0.172 EETED2E391BA 330 22 x 30 1.56 2.23 0.452 0.203 EETED2D331BA 25 x 30 1.71 2.44 0.383 0.172 EETED2E391CA 390 22 x 30 1.71 2.44 0.383 0.172 EETED2D391BA 30 x 25 1.71 2.44 0.383 0.172 EETED2E391DA 25 x 25 1.71 2.44 0.383 0.172 EETED2D391CA 470 22 x 45 1.85 2.64 0.317 0.143 EETED2E4