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Microchip Creating-Your-First-Project-MPLAB-Harmony-Integrated-Software-Framework Manuel

Microchip- Creating-Your-First-Project-MPLAB-Harmony-Integrated-Software-Framework - Manuel

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Creating Your First Project MPLAB Harmony Integrated Software Framework © 2013-2018 Microchip Technology Inc. All rights reserved. Volume I: Getting Started With MPLAB Harmony Libraries and Applications This volume introduces the MPLAB® Harmony Integrated Software Framework. Description MPLAB Harmony is a layered framework of modular libraries that provide flexible and interoperable software "building blocks" for developing embedded PIC32 applications. MPLAB Harmony is also part of a broad and expandable ecosystem, providing demonstration applications, third-party offerings, and convenient development tools, such as the MPLAB Harmony Configurator (MHC), which integrate with the MPLAB X IDE and MPLAB XC32 language tools. Legal Notices Please review the Software License Agreement prior to using MPLAB Harmony. It is the responsibility of the end-user to know and understand the software license agreement terms regarding the Microchip and third-party software that is provided in this installation. A copy of the agreement is available in the /doc folder of your MPLAB Harmony installation. The OPENRTOS® demonstrations provided in MPLAB Harmony use the OPENRTOS evaluation license, which is meant for demonstration purposes only. Customers desiring development and production on OPENRTOS must procure a suitable license. Please refer to one of the following documents, which are located in the /third_party/rtos/OPENRTOS/Documents folder of your MPLAB Harmony installation, for information on obtaining an evaluation license for your device: • OpenRTOS Click Thru Eval License PIC32MXxx.pdf • OpenRTOS Click Thru Eval License PIC32MZxx.pdf TIP! Throughout this documentation, occurrences of refer to the default MPLAB Harmony installation path: • Windows: C:/microchip/harmony/ • Mac OS/Linux: ~/microchip/harmony/ Volume I: Getting Started With MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 2 Creating Your First Project This tutorial guides you through the process of using the MPLAB Harmony Configurator (MHC) and MPLAB Harmony libraries to develop your first MPLAB Harmony project. Part I: Creating Your First MPLAB Harmony Application in MHC This section provides information on creating your first project in MPLAB Harmony. Overview Lists the basic steps necessary to create a MPLAB Harmony application using the MHC. Description MPLAB Harmony provides a convenient MPLAB X IDE plug-in configuration utility, the MPLAB Harmony Configurator (MHC), which you can use to easily create MPLAB Harmony-based projects. This tutorial will show you how to use the MHC to quickly create your first project. It also shows how to create a simple "heartbeat" LED application that flashes an LED. The project created can then serve as a test bed for understanding additional features of MPLAB Harmony, including error handling, system console, and debugging services, and using MPLAB Harmony Middleware and Drivers. You can also reuse the heartbeat LED application in future projects as a simple indicator of system health. Getting Started Provides information on getting started with creating your first project. Description Before beginning this tutorial, ensure that you have installed the MPLAB X IDE and necessary language tools as described in Volume I: Getting Started With MPLAB Harmony > Prerequisites. In addition, ensure that you have installed MPLAB Harmony on your hard drive and that you have the correct MHC plug-in installed in the MPLAB X IDE. You may want to check out your development board by first loading and running a MPLAB Harmony example that uses your board. Follow the instructions in Volume I: Getting Started With MPLAB Harmony > Applications Help > Examples for the demonstration you chose. Set up the board as detailed in the related User’s Guide. The example project in this tutorial can be used with any of the following boards: • PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Starter Kit (DM320007). • PIC32 USB Starter Kit III (DM320003-3) • Explorer 16 Development Board (DM240001-2 ) with PIC32MX795F512L PIM (MA320003) The tutorial steps are equally valid on any other development board, but may be slightly different. In the event you do not have any of these boards, refer to Volume II: Supported Hardware > Supported Development Boards for a list of available development boards that you could use to complete this tutorial. If you are using some other development board, you will need to know what processor is on the board to select the correct Board Support Package. Finally, this tutorial assumes that you have some familiarity with the following: • MPLAB X IDE development and debugging fundamentals • C language programming • PIC32 product family and supported development boards What You Will Learn • How to set up your hardware • How to create a new MPLAB Harmony project from within MPLAB X IDE • How to use System Services, in this case Timer System Services • How to use the Board Support Package (BSP) to toggle an LED • How to add new application states to the application task loop • How to run and build your project Tutorial Steps Describes the necessary steps to create your project. Step 1: Setting Up Your Hardware Provides information for setting up your hardware. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 3 Description PIC32MZ Embedded Connectivity (EF) Starter Kit Connect the "USB Debug" port on the starter kit board to a USB port on your PC using a Mini-B to Type-A USB cable. See PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Starter Kit for additional information on this hardware. PIC32 USB Starter Kit III Connect the debug port on the upper left side of the board to your PIC using a Mini-B to Type-A USB cable. Refer to the PIC32 USB Starter Kit III for additional information on this hardware. Explorer 16 Development Board with the PIC32MX795F512L Plug-in Module (PIM) Mount the PIC32MX795F512L PIM to PIM socket. Set switch S2 to PIM. Power the board with 9V to 15V DC using the J12 connector. Attach a REAL ICE In-circuit Emulator to the RJ12 jack on the board. Other Boards Consult the Information Sheet or User's Guide for your hardware. Refer to Volume II: Supported Hardware > Supported Development Boards for the list of hardware supported by MPLAB Harmony. Step 2: Create a New MPLAB X IDE Project Provides the required steps to create a new MPLAB X IDE project. Description Note: Prior to starting this tutorial, please ensure that the software requirements are met, as described in Volume I: Getting Started With MPLAB Harmony >Prerequisites. 1. Start MPLAB X IDE and select File > New Project. The New Project dialog appears. 2. In the New Project dialog, ensure that Microchip Embedded is selected, and that the project type is 32-bit MPLAB Harmony Project, and then click Next. Note: If the option “32-Bit MPLAB Harmony Project” is not visible, you need to stop and download/install MPLAB Harmony before continuing with this tutorial. 4. In the updated New Project dialog, make the following changes: • Harmony Path: Ensure that the path you enter is the path to your installation of MPLAB Harmony • Project Name: Enter heartbeat (all lowercase) • Device Family: Select the device family that includes your board’s processor. • For the PIC32MZ EF Starter Kit board, select PIC32MZ Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 4 • For the PIC32 USB Starter Kit III and the Explorer 16 Development Board with PIC32MX795F512L PIM, select PIC32MX • Target Board: Select the board you are using (alternately, you can choose the Target Device first, and then look through a smaller list of Target Boards): • For the PIC32MZ EF Starter Kit board, select PIC32MZ (EF) Starter Kit. You will have to scroll down the list to find this board. • For the PIC32 USB Starter Kit III, select PIC32MX USB Starter Kit III. • For the Explorer 16 Development Board with PIC32MX795F512L Plug In Module, select PIC32MX795F512L PIM w/Explorer 16 Development Board. 5. The New Project dialog should appear, as follows. Descriptions of each field follow the image. 1: The path to your installation of MPLAB Harmony. 2: The location of your MPLAB project. 3: The name of the MPLAB project (the name must be all lowercase characters). 4: The path to the MPLAB project file. 5: The MPLAB project configuration name. 6: The selected device family (PIC32MZ or PIC32MX). 7: The selected target device. 8: The selected target board (PIC32MZ EF Starter Kit, PIC32MZ USB Starter Kit III, or PIC32MX795F5123L with the Explorer 16 Development Board). 6. Click Finish when done. A new empty project named heartbeat will be created in MPLAB X IDE, which opens the MPLAB Harmony Configurator (MHC) plug-in. Note: The selected Board Support Package (BSP) assigns device pins to various board functions and sets up the device’s clock tree based on the board’s clock source. You can review the pin assignments using the Pin Diagram or Pin Settings tabs in MHC. The Clock Diagram tab shows the board and application clock setup. Step 3: Configure MPLAB Harmony and the Application Describes how to configure MPLAB Harmony and the application. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 5 Description Within the MPLAB Harmony Configurator window, change the Application Name from “app” to “heartbeat”. Be sure to make the new application name all lowercase. The name is reused in source code for function and data type definitions and using lowercase will stay consistent with the naming conventions used in MPLAB Harmony code. Step 4: Generate the Configured Source Code Describes how to generate the configured source code. Description 1. In MHC, click Generate Code to generate the application’s code for the first time. 2. In the Modified Configuration dialog, click Save to save the project’s configuration. The Generate Project dialog appears. 3. Next, in the Generate Project dialog, click Generate. At this point, the project’s initial software has been configured. Let’s examine the software just created in the Projects panel of MPLAB X IDE, by expanding the Header Files and Source Files folders. Note the icons used in this image of the project’s organization make it seem like the files of the project are organized this way. Actually, this is a virtual organization of these files, not an actual one. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 6 If you click the Files tab you will see the actual organization of these files on your drive. Step 5: Use a Delay Timer to Toggle an LED on the Target Board Describes how to use a delay timer to toggle an LED. Description In this project we will use a delay timer to toggle an LED on the board using a delay of 500 milliseconds and LED1 on the PIC32MZ EF Starter Kit. 1. Double click system_config.h to open the file in an editor. 2. Add the following code to the end of the file, immediately after the line /*** Application Instance 0 Configuration ***/. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 7 // CUSTOM CODE - DO NOT DELETE #define HEARTBEAT_LED BSP_LED_1 #define HEARTBEAT_DELAY 500 // milliseconds // END OF CUSTOM CODE 2. In the system_config.h file within the editor, hold down the CTRL key and click BSP_LED_1. The editor will locate where this token is defined in the Board Support Package bsp.h file for the PIC32MZ EF Starter Kit. Step 6: Add the Timer System Service to Your Project Describes how to add the Timer System Service to your project. Description Next, the Timer System Service needs to be selected in MHC. 1. Select the MHC tab, expand Harmony Framework Configuration > System Services > Timer, and then select Use Timer System Service? 2. As observed in the Help window, the documentation for the Timer System Service is displayed. Using the Help, we can explore what this library provides and choose how to implement the timer delay we need to blink LED1. Click Library Interface and scroll down to Timed Delay Functions. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 8 The SYS_TMR_DelayMS function can be used to create a one-shot delay timer, and then poll that timer status using SYS_TMR_DElayStatusGet. When the timer times out, we can then toggle the LED. 3. Click SYS_TMR_DelayMS to open the related Help for this function. The code example in the documentation provides all that is needed to create the delay. First, the SYS_TMR_HANDLE variable is needed, which is assigned when the timer is created. Then, use SYS_TMR_DelayStatusGet to poll whether the timer has timed out using this handle. So now, we know what to do. Step 7: Add the Timer System Service Source Code to Your Project Describes how to add the source code for the Timer System Service to your project. Description 1. Before adding the Timer to the application, we need to regenerate the application to add the Timer System Service library to our code, using the same process as described in Generate the Configured Source Code. The merge will open a difference window for system_config.h that was modified, as described in Add the Timer System Service to Your Project. Accept all the changes using the icon shown in the following Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 9 figure. • The next figure shows the customer code that was added previously, which we want to retain. Therefore, do not click the icon for this merge. Step 8: Use the Timer System Service in Your Application Describes how to use the Timer System Service in your application. Description 1. Next, from the Project tab in MPLAB X IDE, double-click the heartbeat.h file to open it in the editor. 2. Then, add the new state, HEARTBEAT_RESTART_TIMER, to the application's state enumeration, as shown in the following figure. We will show how that state is used later in the tutorial. // HEARTBEAT_STATES: HEARTBEAT_RESTART_TIMER Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 10 3. Now, add the delay timer handle, SYS_TMR_HANDLE hDelayTimer; // Handle for delay timer, to the application's data structure, as shown in the following figure. // HEARTBEAT_DATA SYS_TMR_HANDLE hDelayTimer; // Handle for delay timer 4. Close and save heartbeat.h by clicking the 'x', and then clicking Save. 5. Next, from the Projects tab in MPLAB X IDE, double-click heartbeat.c from the Source Files > app folder to open it in the editor. We need to update heartbeat.c to add the first timer delay, execute the time-out wait, and restart timer code. Refer to the following figure for the locations to insert the different code blocks. • Insert the following code to start the first delay timer heartbeatData.hDelayTimer = SYS_TMR_DelayMS(HEARTBEAT_DELAY); if (heartbeatData.hDelayTimer != SYS_TMR_HANDLE_INVALID) { // Valid handle returned BSP_LEDOn(HEARTBEAT_LED); heartbeatData.state = HEARTBEAT_STATE_SERVICE_TASKS; } • Insert the following code to wait for a time-out if (SYS_TMR_DelayStatusGet(heartbeatData.hDelayTimer)) { // Single shot timer has now timed out. BSP_LEDToggle(HEARTBEAT_LED); heartbeatData.state = HEARTBEAT_RESTART_TIMER; } • Finally, insert the following code to add the state to the restart timer. case HEARTBEAT_RESTART_TIMER: { // Create a new timer heartbeatData.hDelayTimer = SYS_TMR_DelayMS(HEARTBEAT_DELAY); if (heartbeatData.hDelayTimer != SYS_TMR_HANDLE_INVALID) { // Valid handle returned heartbeatData.state = HEARTBEAT_STATE_SERVICE_TASKS; } break; } Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 11 6. Once you have finished inserting the code blocks, the heartbeat.c file should appear like the following figure. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 12 7. After updating the code, close and save heartbeat.c. Step 9: Build and Run Your Project Describes how to build and run your project. Description 1. For the PIC32MZ EF Starter Kit, click the Run Main Project icon to build and run your project in MPLAB X IDE. If prompted, select the on-board debugger to load the project. • For the PIC32 USB Starter Kit III, select the PICkit On Board (PKOB) debugger • For the Explorer 16 Development Board, select REAL ICE Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part I: Creating Your First MPLAB Harmony © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 13 3. After making these selections click OK and close the Properties window. 4. Run the project using the Run Main Project button. For both boards, the LED should flash with a one second period. Part II: Debugging With Your Project This section discusses how to debug problems in your project from within MPLAB’s debugger Overview This section discusses how to debug problems in your project from within the MPLAB X IDE debugger. Part III: Debugging While Running Stand-alone discusses how to debug problems when running without the debugger, including using diagnostic messages to a HyperTerminal equivalent application on your computer. Description Two important tools in debugging any embedded software application are asserts and exception handling. By default, asserts in the PIC32 code write out an error message to USART2, and then jump into a while(1){} loop. However, if you have not set up USART2 you have no information. Even with USART2 set up, you can miss the message if your HyperTerminal isn’t set up correctly. By default, exceptions (e.g., divide by zero) cause the application to jump into a while(1){} loop, preventing the application from continuing, but providing no additional information. Therefore, in both cases your application stops working and you have no idea why. As a first step in developing any new application, you will be writing code and debugging it using the MPLAB debugger. This lesson shows you how to enable asserts and exception handling while running the debugger, so that you don’t have to setup USART2. The next tutorial will show how to support asserts and exception handling outside of the debugger. It will also show how to add other diagnostic messages to aid in debugging. Getting Started Provides information on getting started with project debugging. Description The following steps can be applied to any MPLAB Harmony-based project, but for the sake of clarity it is assumed that you have completed Part I: Creating Your First MPLAB Harmony Application in MHC. The project created in Part I will be used as the basis for this lesson, s it will be necessary to set up your board using the instructions from that tutorial. What You Will Learn • How to enable asserts from the debugger • How to enable Harmony’s built-in exception handler • How to decode the information reported by the exception handler to find where exception occurred in your code and what type of exception it was • How to test asserts and the exception handler Tutorial Steps This part of the tutorial explores how to use the debugger with your project. Asserts Under the Debugger This section explores how to use the debugger with asserts. Description 1. Launch MPLAB X IDE and load the project you created in Part I: Creating Your First MPLAB Harmony Application in MHC. 2. Open heartbeat.c. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part II: Debugging With Your Project © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 14 3. Add assert(0); to the start of the HEARTBEAT_Initialize function, as shown in red in the following code example. void HEARTBEAT_Initialize ( void ) { assert(0); /* Place the App state machine in its initial state. */ heartbeatData.state = HEARTBEAT_STATE_INIT; 4. Build and run the application. You will see that the LED no longer flashes. This is because the assert(0) fired, and the application is now in an infinite loop within the compiler’s built-in assert function. However, if we hadn’t installed an assert(0) in the code in the first place, how would we know what happened? This is where the debugger can help. 5. As shown in the following figure, if you press and hold the Ctrl key and hover your cursor over the assert call, the Macro assert appears. However, where is this #define located? 6. Press and hold the Ctrl key and click the assert call. This will open the assert.h file that provides the definition of the assert. As shown in the next example, in the header file you can see how the assert is defined. extern void __attribute__((noreturn)) _fassert(int, const char *, const char *, const char*); #define __assert(line,file,expression,func) \ _fassert(line,file,expression,func) #define assert(expr) \ ((void)((expr) ? 0 : (__assert (__LINE__, __FILE__, #expr, __ASSERT_FUNC), 0))) 7. The function _fassert is the built-in assert handler provided by the compiler. Modify the file to allow the debugger to fire a breakpoint when running the debugger (when defined(__DEBUG) is true) by adding the code shown in red in the following example. #if defined(NDEBUG) || !defined(__DEBUG) # define __conditional_software_breakpoint(X) ((void)0) #else # define __conditional_software_breakpoint(X) \ ((X) ? \ (void) 0 : \ __builtin_software_breakpoint()) // Added to support debugger: # undef assert # define assert(expr) __conditional_software_breakpoint(expr) // End of addition #endif 8. Save your edits to assert.h by pressing Ctrl+S and closing the window. 9. Build and run the project under the debugger by clicking Debug Project. 10. The debugger should now stop at the assert(0) call. So by a slight modification to the compiler’s assert.h file, the debugger now stops with a breakpoint at the location of the failing assert. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part II: Debugging With Your Project © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 15 For more information on how to use the built-in debugger in the MPLAB X IDE, refer to the IDE’s built-in help (Help Menu > Tool Help Contents > MPLAB X IDE >)for these topics: • Tutorial > Running and Debugging Code • Basic Tasks > Debug Run code • Basic Tasks > Control Program Execution with Breakpoints • Basic Tasks > Step Through Code • Basic Tasks > Watch Symbol Value Change • Basic Tasks > Watch Local Variable Values Change SYS_ASSERT Macro MPLAB Harmony uses a SYS_ASSERT macro in many places. Other libraries may have a localized assert. For example, the Graphics Library has its own macro GFX_ASSERT, which can help with debugging graphics development. By default, these macros are not defined. You can turn SYS_ASSERT on by the simply including the following code in your system_config.h file, which is located in Header Files > app > system_config > default). /*** Application Instance 0 Configuration ***/ // CUSTOM CODE - DO NOT DELETE #define HEARTBEAT_LED BSP_LED_1 #define HEARTBEAT_DELAY 500 // milliseconds #if defined( SYS_ASSERT ) #undef SYS_ASSERT #endif #define SYS_ASSERT(test,message) assert(test) // END OF CUSTOM CODE This code converts all of the MPLAB Harmony SYS_ASSERTs found into simple assert calls. However, this can greatly affect how the code works, depending on where the SYS_ASSERTs are located. Therefore, this method is best used sparingly. For more information on the SYS_ASSERT macro, refer to Volume V: MPLAB Harmony Framework > System Services Library Help > System Service Overview > Using the SYS_ASSERT Macro. By default, SYS_ASSERT is not defined. There are two alternatives provided in the MPLAB Harmony documentation, one for the debugger and a second for running outside of the debugger (stand-alone). Combining these two yields: #include "system/debug/sys_debug.h" #if !defined(NDEBUG) /*** SYS_DEBUG_Breakpoint Definition ***/ #if defined(__DEBUG) #define SYS_DEBUG_Breakpoint() __asm__ volatile (" sdbbp 0") #else #define SYS_DEBUG_BreakPoint() #endif//defined(__DEBUG) /*** SYS_ASSERT Definition ***/ #if defined( SYS_ASSERT ) //Remove prior definition – necessary to prevent ugly builds #undef SYS_ASSERT #endif #if defined(__DEBUG) //SYS_ASSERT for the debugger #define SYS_ASSERT(test, message) \ do{ if(!(test)) SYS_DEBUG_Breakpoint(); }while(false) #else //SYS_ASSERT for Standalone: #define SYS_ASSERT(test, message) \ do{ if(!(test)){ \ SYS_MESSAGE((message)); \ SYS_MESSAGE("\r\n"); \ while(1);} \ Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part II: Debugging With Your Project © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 16 }while(false) #endif//defined(__DEBUG) #endif//!defined(NDEBUG) The details of how to enable SYS_MESSAGE to allow output to a HyperTerminal are discussed in Part II: Debugging With Your First Project > Part III: Debugging While Running Stand-alone. Exception Handling in the Debugger This section explores how the debugger can be used in exception handling. Description 1. The first step in exploring how MPLAB Harmony handles exceptions is to verify that the exception handler is enabled. Before launching MHC, the project must be the Main Project within the MPLAB X IDE. To set the project as the Main Project, right click the project name, and select Set as Main Project. 2. Start MHC by clicking the MPLAB Harmony icon ( ). If this icon is not visible, this indicates the MHC plug-in is not installed (refer to Volume III: MPLAB harmony Configurator (MHC) > MPLAB Harmony Configurator User's Guide > Installing MHC to install MHC). 3. Verify that the MPLAB Harmony Exception Handler will be used. If correctly configured, the project should have the file system_exception.c within Source Files > app > system_config > default in the MPLAB X IDE Project tab. If this file is missing, go to MHC and select Use MPLAB Harmony Exception Handler Template? to enable MPLAB Harmony’s exception handler. Then, regenerate the application’s code to add Harmony’s exception handler. 4. Next, we need to create an exception in the code to observe how exceptions are handled. Replace the assert(0); in HEARTBEAT_Initialize with the following code. However, if we jump to trying out this code in the debugger, nothing will happen. Under the default optimization level (-01) the compiler will recognize that this code does not do anything useful, and will not include it in the build. Therefore, we will have to change the optimization level for the file to zero before proceeding. // Test out error handling under Optimization Level Zero for system_init.c { uint8_t x, y, z; x = 1; y = 0; z = x/y; } 5. Right click heartbeat.c and choose Properties from the resulting menu and make the following selections: • In File Properties, select Override build options ( ) • Next, select the compiler ( ) • Within the Optimization category ( ), set the optimization level to zero After making the selections, click OK to close the window 6. Next, build and run the application under the debugger. The application should stop at the debugger breakpoint in system_exceptions.c. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part II: Debugging With Your Project © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 17 Hovering your cursor above the variable, _excep_code, will reveal the exception code. In this case, 0xD or 13, corresponds to an arithmetic trap (see the following table for a list of PIC32 Exception Codes. Hovering your cursor over the variable, _excep_addr, will reveal where in the code the exception occurred. Now we need to find out where 0x9D00_25D8 is located in the code (this address may be different for your appliation). Before going to the next step, stop the debugger session by pressing Shift+F5 or by clicking the Finish Debugger Session icon ( ). Exception Codes for PIC32 typedef enum { EXCEP_IRQ = 1, // interrupt (coded as zero) EXCEP_AdEL = 4, // address error exception (load or ifetch) EXCEP_AdES = 5, // address error exception (store) EXCEP_IBE = 6, // bus error (ifetch) EXCEP_DBE = 7, // bus error (load/store) EXCEP_Sys = 8, // syscall EXCEP_Bp = 9, // breakpoint EXCEP_RI = 10, // reserved instruction EXCEP_CpU = 11, // coprocessor unusable EXCEP_Overflow = 12, // arithmetic overflow EXCEP_Trap = 13, // trap (possible divide by zero) EXCEP_IS1 = 16, // implementation specfic 1 EXCEP_CEU = 17, // CorExtend Unuseable EXCEP_C2E = 18, // coprocessor 2 } EXCEPTION_CODES; 7. If the debugger is inside of a function, you can look at a disassembly of the code, but this is impractical when you don’t know where to look for the cause of the exception. Instead, you can build a list of all the application’s assembly code at build time. (Of course, this step can cause the build to take longer, so only use it when trying to debug an exception.) • Right click the project name and select Properties • Within the Building properties, enable Excecute this line after build, and enter the following text (Windows): • ${MP_CC_DIR}\xc32-objdump -S ${ImageDir}\${PROJECTNAME}.${IMAGE_TYPE}.elf > disassembly.lst • For Linux: ${MP_CC_DIR}/xc32-objdump -S ${ImageDir}/${PROJECTNAME}.${IMAGE_TYPE}.elf > disassembly.lst • At the end, the window should show: • Click OK to finish. 8. Run the project under the debugger again. When the breakpoint fires verify that the address is the same as before. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part II: Debugging With Your Project © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 18 9. Now we need to examine the disassembly.lst file that was just generated. This file is located in the ./heartbeat/firmware/heartbeat.X folder. Load the file with your favorite text editor and search for 9D0025D8 (or the address you found) in the listing. The following example illustrates what you should see: void HEARTBEAT_Initialize ( void ) { 9d0025b4: 27bdfff0 addiu sp,sp,-16 9d0025b8 <.LCFI0>: 9d0025b8: afbe000c sw s8,12(sp) 9d0025bc: 03a0f021 move s8,sp 9d0025c0 <.LBB2>: // Test out error handling under Optimization Level Zero for system_init.c { uint8_t x, y, z; x = 1; 9d0025c0: 24020001 li v0,1 9d0025c4: a3c20000 sb v0,0(s8) 9d0025c8 <.LVL0>: y = 0; 9d0025c8: a3c00001 sb zero,1(s8) 9d0025cc <.LVL1>: z = x/y; 9d0025cc: 93c30000 lbu v1,0(s8) 9d0025d0: 93c20001 lbu v0,1(s8) 9d0025d4 <.LVL2>: 9d0025d4: 0062001b divu zero,v1,v0 9d0025d8: 004001f4 teq v0,zero,0x7 <----- Exception Address 9d0025dc: 00001010 mfhi v0 9d0025e0: 00001012 mflo v0 9d0025e4: a3c20002 sb v0,2(s8) 9d0025e8 <.LBE2>: } So the exception occurred during the assembly execution of the C instruction z = x/y, as expected. 10. Before proceeding, comment out the exception code in the heartbeat.c file. You could delete it from the file, but leaving it in as a comment provides a convenient way to validate that the exception handler is working; just uncomment and run to verify it still works as expected. 11. You should also remove the Override build options from heartbeat.c, returning it back to the projects default of Optimization Level One (-O1). Note: You might expect from the code in system_exceptions.c that it would also print out a message reporting the exception, but pressing and holding the Ctrl key while hovering your cursor reveals that SYS_DEBUG_PRINT is not defined, so nothing really happens in the code. Enabling this feature is discussed in the next tutorial. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 19 Part III: Debugging While Running Stand-alone This section discusses how to debug problems when running without the debugger, including using diagnostic messages to a HyperTerminal or equivalent application on your computer. Description While the debugger in the MPLAB X IDE can help identify many bugs, there are cases where running the application outside of the debugger (i.e., Stand-alone mode), is necessary. The ability to dump error messages from failing asserts or from the exception handler is key to debugging an application outside of the debugger. Transmitting diagnostic or debug messages can also be key, both with and without the debugger. Getting Started Provides information on getting started with project debugging while running stand-alone. Description The steps outlined in this section can be applied to any MPLAB Harmony-based project, but for the sake of clarity we assume you have completed Part I: Creating Your First MPLAB Harmony Application in MHC. We will use the project from the this tutorial as the basis for this lesson. Board setup will be different than in the prior tutorials, primarily because of the need to support a USART connection to a COM port on your PC. Setting Up the Hardware PIC32MZ Embedded Connectivity (EF) Starter Kit Setting up this board is easy, since it has an on-board MCP2221A USART-to-USB Bridge. Therefore, all that is required to connect the device to a COM port is to plug in a mini-B to Type-A cable from the mini-B port beneath the Ethernet PHY to a USB port on your PC. PIC32 USB Starter Kit III As an older board design, there is no MCP2221A on this board, so you will need the following additional hardware: • MCP2221 Breakout Module (ADM00559) • Mini-B to Type-A USB cable for the Breakout Module • Starter Kit I/O Expansion Board (DM320002) • Jumper Wires • 0.1” Pitch Header Pins to connect jumpers between the breakout module and I/O expansion board. The hardware is set up as follows: Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 20 Explorer 16 Development Board with the PIC32MX795F512L Plug-in Module (PIM) As an older board design, there is no MCP2221A on this board, so you will need the following additional hardware: • MCP2221 Breakout Module (ADM00559) • Mini-B to Type-A USB cable for the Breakout Module • Prototype PICTail Plus Daughter Board (AC164126 for a three pack) • Jumper Wires • 0.1” Pitch Header Pins to connect jumpers between the breakout module and I/O expansion board. The hardware is set up as follows: Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 21 What You Will Learn • How the MPLAB Harmony Configurator (MHC) configures USARTs and device pins for USARTS • How MHC configures the Console System Service and the Debug System Service to support output via a USART • How to output diagnostic and debug messages via these system services • How to customize the assert handler and exception handler used in the application Tutorial Steps This part of the tutorial explores how to debug when running without the debugger (i.e., stand-alone). Enabling USART Output Using System Console and Debug System Services This section describes how to set up the System Console and Debug System Services using a USART port. Description 1. Launch the MPLAB X IDE and load the project you created in the Part I: Creating Your First MPLAB Harmony Application in MHC. 2. Set the project as the IDE’s Main Project and launch the MPLAB Harmony Configurator (MHC). 3. If you are using a board with a built-in MCP2221A USART-to-USB Bridge, in the BSP Configuration enable the USART-to-USB Bridge. This will assign device pins for use by the USART connected to the bridge. 4. Within Harmony Framework Configuration > Drivers > USART, configure USART 2. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 22 Note: There are many options on how the USART driver is configured, but the simplest is always the best in this situation, since the USART must work after an assert has failed or an exception has fired. Therefore, the simplest set up is best. 5. Within Harmony Framework Configuration > System Services, configure the application to use the Console System Service. (The STATIC configuration is hard-wired to use USART Driver Instance 0 (the first one defined), which we set up in the previous step. To use another USART Driver Instance you must use the DYNAMIC service mode.) Again, the simplest setup is the best approach to handle asserts and exceptions. 6. Also under System Services, configure the application to use the Debug System Service. Set the System Error Level to SYS_ERROR_DEBUG to support SYS_DEBUG_PRINT. The pull-down menu for System Error Level has the options shown in the second figure. Note: The System Error Level determines which SYS_DEBUG_PRINT messages are actually printed on the USART port. Set to SYS_ERROR_DEBUG, all levels are printed. 7. Open the Pin Settings Tab in MHC. For boards with a MCP2221A, verify that the BSP has correctly set the USART pins. For boards without a MCP2221A, set the USART pins as shown. (Click the Function column to select the correct pin function.) • PIC32 USB Starter Kit III: Pin Number Pin ID Voltagea Tolerance Name Function 49 RF4 5V U2RX U2RX 50 RF5 5V U2TX U2TX • PIC32MZ EF Starter Kit: Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 23 Pin Number Pin ID Voltagea Tolerance Name Function 14 RG6 N/A USART-to-USB Bridge (USB) U2RX 61 RB14 N/A USART-to-USB Bridge (BSP) U2TX • Explorer 16 Development Board with PIC32MX795F512L Plug In Module: Pin Number Pin ID Voltagea Tolerance Name Function 49 RF4 5V U2RX U2RX 50 RF5 5V U2TX U2TX 8. Generate this new code configuration. For system_config.h, accept the changes, but do not discard the // CUSTOM CODE segment that you added in Part I: Creating Your First MPLAB Harmony Application in MHC. 9. Open heartbeat.c and add the following code shown in red to HEARTBEAT_Initialize. void HEARTBEAT_Initialize ( void ) { SYS_MESSAGE( "\r\nApplication created " __DATE__ " " __TIME__ " initialized!\r\n"); //Test out error handling // assert(0); // { // uint8_t x, y, z; // x = 1; // y = 0; // z = x/y; // SYS_DEBUG_PRINT(SYS_ERROR_DEBUG,"x: %d, y: %d, z: %d\r\n",x,y,z); // } /* Place the App state machine in its initial state. */ heartbeatData.state = HEARTBEAT_STATE_INIT; /* TODO: Initialize your application's state machine and other * parameters. */ } 10. Save the file by pressing Ctrl+S, and then close the window. Note: The portion of this addition that is commented can be uncommented to support testing that asserts and exceptions are correctly reported. Since we have enabled the Debug System Service, SYS_DEBUG_PRINT here actually works. Therefore, the compiler will not drop this this code when it is enabled, thereby eliminating the need to modify the code’s optimization level as before. 11. Set up your PC’s HyperTerminal to 115200 baud, 8 bits, 1 Stop Bit, No Parity. 12. Run the project. If you have correctly setup you HyperTerminal application you should see something similar to the following on its display: Application created Aug 8 2017 12:14:04 initialized! Getting the HyperTerminal to correctly identify the COM port belonging to the MCP2221A (either on-board or in a Breakout Module) can be a fussy and frustrating process. There will be times when you can’t find the COM port. In those cases, at least on a Windows PC, try the following: • In the Control Panel, select System > Device Manager • Within Ports (COM & LPT), identify the COM port belonging to the MCP2221A. Double click on this port to open its Properties window. • Select the Driver tab and disable, and then enable the driver • Close the window. This should allow your HyperTerminal to see the port. Note: If all else fails, you may need to put the SYS_DEBUG_PRINT statement in a while(1) loop and, worst case, use an oscilloscope to make sure the USART TX signal is getting to the MCP2221A and that the USB data lines are working as well. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 24 If your board has a built-in MCP2221A but does not have an independent power supply, as with the PIC32MZ EF Starter Kit, where power is supplied by the debug port, you will not see the initial startup message when power cycling the application by unplugging and plugging in the debug port. When power is supplied to the board, the application starts, but the MCP2221A has to enumerate as a USB device with your PC before COM port output is accepted. So, the initial message has long since passed on the port before the COM port is working. If your board has a Master Clear (MCLR) button, you can simply press the button to reset the application after the MCP2221A enumerates. Then, the initial message will be seen on your HyperTerminal application. If your board does not have a MCLR button, you can still assert a Master Clear by grounding pin 1 of the ICSP header. The following figure show how this is done on the PIC32MZ EF Starter Kit. Adding Customized Assert and Exception Handling This section describes how to add customized assert and exception handling without a debugger. Description The default assert function provided by the PIC32 compiler is called _fassert. It is “weakly” defined, meaning that you can provide a customized replacement for it in your project. You may want to replace the default (compiler) assert for two reasons: • The default function is hardwired to use USART2 and you want to use another USART • You have a lot of asserts in your code, but do not need them to report out the line number, file name, failed expression, and function name in the message, because storing all of these string constants for every assert uses too much memory. Instead, you can invent a customized _fassert that only reports out, for example, only the line number and function name to save memory. The default exception handler is hardwired to USART2, so using MPLAB Harmony’s replacement handler, as we did in Part I: Creating Your First MPLAB Harmony Application in MHC, will at least give you the flexibility to control which USART is used. However, both handlers only report out the cause and program address of the exception, nothing more. Please note that there will be cases where this information is not sufficient to locate what went wrong. MHC provides two additional, advanced exception handlers that can be used instead. 1. The MHC menu Advanced Exception and Error Handling shows the options available. Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 25 2. Select the Advanced Harmony Exception Handler. (The other advanced handler shown supports filtering by saturating rather than overflowing integer arithmetic.) Select the MPLAB Harmony Assert Handler to replace the compiler’s built-in assert handler. By default, output uses SYS_DEBUG_PRINT, but using SYS_CONSOLE_Write can be chosen instead since it is a more robust way of reporting exceptions and errors. 3. Generate this configuration by clicking Generate Code. After completing this, your default project folder should contain the files shown in the following figure. Note the assembly (.S) file is required to report out extra information via the new exception handler. 4. Double click the new exception handler, general_exception_handler.c, to see what it reports. void __attribute__((nomips16)) _general_exception_handler (XCPT_FRAME* const pXFrame) { register uint32_t _localStackPointerValue asm("sp"); _excep_addr = pXFrame->epc; _excep_code = pXFrame->cause; // capture exception type _excep_code = (_excep_code & 0x0000007C) >> 2; _CP0_StatusValue = _CP0_GET_STATUS(); _StackPointerValue = _localStackPointerValue; _BadVirtualAddress = _CP0_GET_BADVADDR(); _ReturnAddress = pXFrame->ra; sprintf(msgBuffer,"**EXCEPTION:*\r\n" " ECode: %d, EAddr: 0x%08X, CPO Status: 0x%08X\r\n" " Stack Ptr: 0x%08X, Bad Addr: 0x%08X, Return Addr: 0x%08X\r\n" "**EXCEPTION:*\r\n", _excep_code,_excep_addr,_CP0_StatusValue, _StackPointerValue,_BadVirtualAddress,_ReturnAddress); SYS_CONSOLE_Write(SYS_CONSOLE_INDEX_0,STDOUT_FILENO,msgBuffer,strlen(msgBuffer)); SYS_DEBUG_BreakPoint(); // Stop here if in debugger. while(1) { //Do Nothing } } So, in addition to the cause (ECode) and address (EAddr) of the exception, this exception handler also reports the Core Register CP0 value (CPO Status), the Stack Pointer value (Stack Ptr), Bad Address value (Bad Addr), and the Return Address value (Return Addr). For more information on the bit fields in the CP0 register refer to one of these PIC32 Family Reference Manual sections: • PIC32MX: Section 02. "CPU for Devices with M4K Core" (DS6000113) • PIC32MK and PIC32MZ: Section 50. "CPU for Devices with microAptiv Core" (DS60001192) Both of these documents are available for download from the Microchip website at: www.microchip.com. 5. Add post processing to the project’s configuration to produce a disassembly listing. • Right click the project name and selecting Properties • Within the Building ( ) properties, enable Execute this line after build and enter the following text: • ${MP_CC_DIR}\xc32-objdump -S ${ImageDir}\${PROJECTNAME}.${IMAGE_TYPE}.elf > disassembly.lst • At the end the window should show: • Click OK to close the window 6. To explore how we can use the extra information reported by the new exception handler, make the following modifications shown in red text to heartbeat.c: void DivideByZero(void) { uint8_t x, y, z; x = 1; y = 0; Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 26 z = x/y; SYS_DEBUG_PRINT(SYS_ERROR_DEBUG,"x: %d, y: %d, z: %d\r\n",x,y,z); } void Dereference_Bad_Address(void) { uint32_t * pointer; uint32_t value; pointer = (uint32_t *)0xDEADBEEF; value = *pointer; SYS_DEBUG_PRINT(SYS_ERROR_DEBUG,"Value: %d\r\n",value); } void HEARTBEAT_Initialize ( void ) { SYS_MESSAGE( "\r\nApplication created " __DATE__ " " __TIME__ " initialized!\r\n"); // Test out error handling // assert(0); // { // uint8_t x, y, z; // x = 1; // y = 0; // z = x/y; // SYS_DEBUG_PRINT(SYS_ERROR_DEBUG,"x: %d, y: %d, z: %d\r\n",x,y,z); // } //assert(0); //DivideByZero(); //Dereference_Bad_Address(); /* Place the App state machine in its initial state. */ heartbeatData.state = HEARTBEAT_STATE_INIT; /* TODO: Initialize your application's state machine and other * parameters. */ } 7. Uncomment the //assert(0);, abd then build and run the application. In your HyperTerminal application, you should see something similar to the following: Application created Aug 8 2017 16:51:05 initialized! ASSERTION '0' FAILED! File: ../src/heartbeat.c, Line: 148, Function: HEARTBEAT_Initialize 8. Now comment out the assert and uncomment the call to DivideByZero, and then build and run. In your HyperTerminal application, you should see something similar to the following: Application created Aug 8 2017 16:37:51 initialized! **EXCEPTION:* ECode: 13, EAddr: 0x9D006CAC, CPO Status: 0x25000003 Stack Ptr: 0x8007FED8, Bad Addr: 0x25651D53, Return Addr: 0x9D007020 **EXCEPTION:* In the disassembly listing you will see: void DivideByZero(void) { uint8_t x, y, z; x = 1; y = 0; z = x/y; 9d006ca0: 24070001 li a3,1 Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 27 9d006ca4: 00001021 move v0,zero 9d006ca8: 00e2001b divu zero,a3,v0 9d006cac: 004001f4 teq v0,zero,0x7 <<------------------- EAddr 9d006cb0: 00003812 mflo a3 SYS_DEBUG_PRINT(SYS_ERROR_DEBUG,"x: %d, y: %d, z: %d\r\n",x,y,z); 9d006cb4: 3c049d00 lui a0,0x9d00 9d006cb8: 24846968 addiu a0,a0,26984 9d006cbc: 24050001 li a1,1 9d006cc0: 00003021 move a2,zero 9d006cc4: 0f4015fd jal 9d0057f4 9d006cc8: 30e700ff andi a3,a3,0xff 9d006ccc <.LVL2>: } //assert(0); DivideByZero(); 9d007018: 0f401b22 jal 9d006c88 <.LFE1152> 9d00701c: 00000000 nop 9d007020 <.LVL9>: <<------------ Return Address //Dereference_Bad_Address(); /* Place the App state machine in its initial state. */ heartbeatData.state = HEARTBEAT_STATE_INIT; 9d007020: af808054 sw zero,-32684(gp) <<---- Return Address In this example we see, as before, that the exception address correctly identifies the instruction that caused the exception. Note also that the return address points to the instruction after the call to the DivideByZero function. Note: The actual addresses may vary depending on the target device. 9. Now comment out the DivideByZero and uncomment the call to Dereference_Bad_Address, and then build and run. In your HyperTerminal application you should see something similar to the following: Application created Aug 8 2017 16:43:01 initialized! **EXCEPTION:* ECode: 4, EAddr: 0x9D006F38, CPO Status: 0x25000003 Stack Ptr: 0x8007FED8, Bad Addr: 0xDEADBEEF, Return Addr: 0x9D006F40 **EXCEPTION:* In the disassembly listing you will see: void Dereference_Bad_Address(void) { 9d006f24: 27bdffe8 addiu sp,sp,-24 9d006f28: afbf0014 sw ra,20(sp) 9d006f2c: afb00010 sw s0,16(sp) uint32_t * pointer; uint32_t value; pointer = (uint32_t *)0xDEADBEEF; value = *pointer; 9d006f30: 3c02dead lui v0,0xdead 9d006f34: 3442beef ori v0,v0,0xbeef 9d006f38 <.LVL4>: <<------------ EAddr SYS_DEBUG_PRINT(SYS_ERROR_DEBUG,"Value: %d\r\n",value); 9d006f38: 0f40003e jal 9d0000f8 <.LFE1164> 9d006f3c: 8c500000 lw s0,0(v0) 9d006f40 <.LVL5>: <<----- Return Address 9d006f40: 10400006 beqz v0,9d006f5c <.LVL6+0x4> <<-- 9d006f44: 8fbf0014 lw ra,20(sp) 9d006f48: 3c049d00 lui a0,0x9d00 9d006f4c: 24846980 addiu a0,a0,27008 9d006f50: 0f4015fd jal 9d0057f4 9d006f54: 02002821 move a1,s0 9d006f58 <.LVL6>: } Volume I: Getting Started With MPLAB Harmony Creating Your First Project Part III: Debugging While Running Stand-alone © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 28 The exception code reported, 4, corresponds to an “address error exception (load or ifetch)”. In this example, the return address didn’t provide much information but we see that the bad address used in the pointer dereference was correctly reported. As an additional step, replace value = *pointer with *pointer = value in the code and verify that an exception code of 5, “address error exception (store)”, is reported instead. Tips Provides tips for effective use. Description Warnings All Compiler Switch It is recommended that you enable the compiler switch, –Wall (Warnings-All), for your project. This will warn you of potential problems that may turn into bugs. In the configuration’s properties, select the compiler compiler and select Additional Warnings. Project Locations on Your Hard Drive In the first tutorial of this series, the project was created in the following folder (for Windows): C:\microchip\harmony\\apps. In reality, you can create a MPLAB Harmony project anywhere on the same hard drive that contains the MPLAB Harmony installation you are using. For MAC OS and Linux, that is the only limitation. For Windows, there is an operating system limitation that all paths in the project must be less than 256 characters in length. Therefore, you may run into trouble on Windows if the project is created too deep into the drive’s directory tree. Moving and Copying Projects All of files in your project are referenced by their relative path from the “.X” directory (heartbeat\firmware\heartbeat.X), which contains the Makefile make file and nbproject sub-directory. This provides flexibility in relocating and copying projects, since as long as the relative paths to files in the MPLAB Harmony installation (typically C:\microchip\harmony\) still work the project can be anywhere. Example You can move/copy a project: • Old Location: C:\MyWork\MyProject\heartbeat • New Location: C:\MyWork\MyNewProject\heartbeat (Good) However, neither of these new locations work, since it breaks the project’s relative paths: • Old Location: C:\MyWork\MyProject\heartbeat • New Location: C:\MyProject\heartbeat (Not Good), or • New Location: C:\MyWork \MyNewProject\Rev2\heartbeat (Not Good) Next Steps Provides information on where to find additional resources. Description To learn more about MPLAB Harmony, refer to Volume I: Getting Started With MPLAB Harmony > What is MPLAB Harmony? Revisit Volume I: Getting Started With MPLAB Harmony > Guided Tour for suggestions on where to begin learning more. Try an existing MPLAB Harmony demonstration that runs on a PIC32MZ EF Starter Kit: Peripheral Examples (/apps/examples/): Volume I: Getting Started With MPLAB Harmony Creating Your First Project Next Steps © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 29 peripheral Basic Bootloader (/apps/bootloader/): basic Graphics with MEB II Display (/apps/gfx/): • aria_quickstart • aria_showcase • aria_weather_forecast TCP/IP Stack (/apps/tcpip/): • tcpip_client_server • tcpip_tcp_server • tcpip_udp_client • tcpip_udp_client_server • tcpip_udp_server USB Device (/apps/usb/device/): • cdc_msd_basic • cdc_serial_emulator • hid_basic • hid_joystick • hid_msd_basic • msd_basic • hid_mouse USB Host (/apps/usb/host): • audio_speaker • cdc_basic • cdc_msd • hid_basic_keyboard • hid_basic_mouse_usart • hub_msd • msd_basic Volume I: Getting Started With MPLAB Harmony Creating Your First Project Next Steps © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 30 Index A Adding Customized Assert and Exception Handling 25 Asserts Under the Debugger 14 C Creating Your First Project 3 Overview 3 E Enabling USART Output Using System Console and Debug System Services 22 Exception Handling in the Debugger 17 G Getting Started 3, 14, 20 N Next Steps 29 O Overview 3, 14 P Part I: Creating Your First MPLAB Harmony Application in MHC 3 Part II: Debugging With Your Project 14 Part III: Debugging While Running Stand-alone 20 S Step 1: Setting Up Your Hardware 3 Step 2: Create a New MPLAB X IDE Project 4 Step 3: Configure MPLAB Harmony and the Application 5 Step 4: Generate the Configured Source Code 6 Step 5: Use a Delay Timer to Toggle an LED on the Target Board 7 Step 6: Add the Timer System Service to Your Project 8 Step 7: Add the Timer System Service Source Code to Your Project 9 Step 8: Use the Timer System Service in Your Application 10 Step 9: Build and Run Your Project 13 T Tips 29 Tutorial Steps 3, 14, 22 V Volume I: Getting Started With MPLAB Harmony Libraries and Applications 2 Index © 2013-2017 Microchip Technology Inc. MPLAB Harmony v2.06 31

 2004 Microchip Technology Inc. DS51471A dsPICDEM.net™ 1 and dsPICDEM.net™ 2 Connectivity Development Board User’s Guide DS51471A-page ii  2004 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. dsPICDEM.net™ 1 AND dsPICDEM.net 2 CONNECTIVITY DEVELOPMENT BOARD USER’S GUIDE  2004 Microchip Technology Inc. DS51471A-page iii Table of Contents Preface ........................................................................................................................... 1 Chapter 1. Introduction 1.1 Introduction ..................................................................................................... 7 1.2 Highlights ........................................................................................................ 7 1.3 Overview ........................................................................................................ 7 1.4 dsPICDEM.net Package Contents ................................................................. 8 1.5 dsPICDEM.net Board Functionality ................................................................ 8 1.6 dsPICDEM.net Demonstration Programs ..................................................... 10 1.7 Reference Documents .................................................................................. 11 Chapter 2. Tutorial 2.1 Introduction ................................................................................................... 13 2.2 Highlights ...................................................................................................... 13 2.3 Tutorial Overview ......................................................................................... 13 2.4 Creating the Project ...................................................................................... 13 2.5 Building the Code ......................................................................................... 19 2.6 Device Configuration and Programming ...................................................... 22 2.7 Debugging the Code .................................................................................... 27 2.8 Summary ...................................................................................................... 30 Chapter 3. Quick Start Program 3.1 Introduction ................................................................................................... 31 3.2 Highlights ...................................................................................................... 31 3.3 Quick Start Program Overview ..................................................................... 31 3.4 Creating the Project ...................................................................................... 32 3.5 Building the Code ......................................................................................... 38 3.6 Device Configuration and Programming ...................................................... 40 3.7 Interacting with the Code .............................................................................. 45 3.8 Quick Start Demonstration Features and Peripherals .................................. 45 3.9 Data and Control Flow .................................................................................. 46 3.10 Summary .................................................................................................... 48 Chapter 4. HTTP Web Server Demonstration 4.1 Introduction ................................................................................................... 49 4.2 Highlights ...................................................................................................... 49 4.3 Demonstration Overview .............................................................................. 49 4.4 Demonstration Setup .................................................................................... 50 4.5 Configuring your Laptop or Desktop PC ....................................................... 51 4.6 HTTP Web Server Demonstration ............................................................... 52 dsPICDEM.net 1 and dsPICDEM.net 2 Connectivity Dev Board User’s Guide DS51471A-page iv  2004 Microchip Technology Inc. 4.7 Debugging Tips ............................................................................................ 57 4.8 Troubleshooting ........................................................................................... 58 4.9 Using HTTP Web Server in Your Application ............................................... 59 Chapter 5. FTP Server 5.1 Introduction ................................................................................................... 61 5.1 Highlights ...................................................................................................... 61 5.2 Application Overview .................................................................................... 61 5.3 Demonstration Setup .................................................................................... 62 5.4 Configuring your Laptop or Desktop PC ....................................................... 63 5.5 FTP Server Demonstration ........................................................................... 64 5.6 Summary ...................................................................................................... 70 Chapter 6. V.22bis Soft Modem Demonstration 6.1 Introduction ................................................................................................... 71 6.1 Highlights ...................................................................................................... 71 6.2 Demonstration Overview .............................................................................. 71 6.3 Demonstration Configurations ...................................................................... 72 6.4 Demonstration Procedures ........................................................................... 74 6.5 Reprogramming the dsPIC30F6014 ............................................................. 76 6.6 Description of dsPIC30F Soft Modem .......................................................... 78 6.7 dsPIC30F Soft Modem AT Command Set ................................................... 79 6.8 Troubleshooting the Connection .................................................................. 81 6.9 Regulatory Compliance Reference Information ........................................... 84 6.10 ITU-T Specifications ................................................................................... 86 Chapter 7. dsPICDEM.net Development Hardware 7.1 dsPICDEM.net Hardware Components ........................................................ 87 Appendix A. Hardware Schematics A.1 Board Layout and Schematics ..................................................................... 93 Index ...........................................................................................................................107 Worldwide Sales and Service ...................................................................................109  2004 Microchip Technology Inc. DS51471A-page 1 dsPICDEM.net™ 1 AND dsPICDEM.net 2 CONNECTIVITY DEVELOPMENT BOARD USER’S GUIDE Preface INTRODUCTION This user’s guide supports the dsPICDEM.net 1 and dsPICDEM.net 2 connectivity development boards. These boards provide basic platforms that enable the application developer to create and evaluate both connectivity and non-connectivity based solutions. This chapter previews the contents of the manual, tells you how to obtain valuable customer support and recommends useful reference information. HIGHLIGHTS Items discussed in this chapter are: • About This Guide • Warranty Registration • Recommended Reading • The Microchip Web Site • Development Systems Customer Notification Service • Customer Support ABOUT THIS GUIDE This user’s guide describes how to use the dsPICDEM.net 1 and dsPICDEM.net 2 connectivity development boards. The document is organized as follows: • Chapter 1: Introduction – This chapter introduces the dsPICDEM.net 1 and dsPICDEM.net 2 connectivity development board and provides a brief description of the hardware. • Chapter 2: Tutorial – This chapter presents a step-by-step process for getting your dsPICDEM.net 1 and dsPICDEM.net 2 connectivity development board up and running with the MPLAB® In-Circuit Debugger 2 (MPLAB ICD 2). • Chapter 3: Quick Start Program – This chapter describes the operational functionality of a demonstration program included on the dsPICDEM.net Development Kit Software CD. The demonstration program exercises several capabilities of the dsPIC30F by interacting with peripheral devices on the development board. • Chapter 4: HTTP Web Server Demonstration – This chapter describes the operational functionality of a sample HTTP Web Server based embedded application that is included on the dsPICDEM.net Development Kit Software CD. • Chapter 5: FTP Server Demonstration – This chapter describes the operational functionality of a sample FTP Server based embedded application that is included on the dsPICDEM.net Development Kit Software CD. • Chapter 6: V.22bis Soft Modem Demonstration – This chapter describes the operational functionality of a sample PSTN based application that is preprogrammed into the dsPIC30F6014 device. • Chapter 7: dsPICDEM.net™ Development Hardware – This chapter describes the hardware included on the of the dsPICDEM.net 1 and dsPICDEM.net 2 boards. • Appendix A: Hardware Schematics – This Appendix contains hardware layout and schematic diagrams of the dsPICDEM.net 1 and dsPICDEM.net 2. PICDEM.net™ 1 and dsPICDEM.net 2 Connectivity Dev Board User’s Guide DS51471A-page 2  2004 Microchip Technology Inc. Conventions Used in This Guide This User's Guide uses the following documentation conventions: DOCUMENTATION CONVENTION Documentation Updates All documentation becomes dated, and this user’s guide is no exception. Since Microchip tools are constantly evolving to meet customer needs, some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site to obtain the latest documentation available. Documentation Numbering Conventions Documents are numbered with a “DS” number. The number is located on the bottom of each page, in front of the page number. The numbering convention for the DS Number is DSXXXXXA, where: WARRANTY REGISTRATION Please complete the enclosed Warranty Registration Card and mail it promptly. Sending in your Warranty Registration Card entitles you to receive new product updates. Interim software releases are available at the Microchip web site. Description Represents Examples Code (Courier font): Plain characters Sample code Filenames and paths #define START c:\autoexec.bat Angle brackets: < > Variables

SAM L10/L11 Family Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone, Crypto, and Enhanced PTC Features • Operating Conditions: 1.62V to 3.63V, -40ºC to +125ºC, DC to 32 MHz • Core: 32 MHz (2.62 CoreMark/MHz and up to 31 DMIPS) ARM® Cortex®-M23 with: – Single-cycle hardware multiplier – Hardware divider – Nested Vector Interrupt Controller (NVIC) – Memory Protection Unit (MPU) – Stack Limit Checking – TrustZone® for ARMv8-M (optional) • System – Power-on Reset (POR) and programmable Brown-out Detection (BOD) – 8-channel Direct Memory Access Controller (DMAC) – 8-channel event system for Inter-peripheral Core-independent Operation – CRC-32 generator • Memory – 64/32/16 KB Flash – 16/8/4 KB SRAM – 2 KB Data Flash Write-While-Read (WWR) section for non-volatile data storage – 256 bytes TrustRAM with physical protection features • Clock Management – Flexible clock distribution optimized for low power – 32.768 kHz crystal oscillator – 32.768 kHz ultra low-power internal RC oscillator – 0.4 to 32 MHz crystal oscillator – 16/12/8/4 MHz low-power internal RC oscillator – Ultra low-power digital Frequency-Locked Loop (DFLLULP) – 48-96 MHz fractional digital Phase-Locked Loop (FDPLL96M) – One frequency meter • Low Power and Power Management – Active, Idle, Standby with partial or full SRAM retention and off sleep modes: • Active mode (< 25 μA/MHz) • Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 1 • Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time • Off mode (< 100 nA) – Static and dynamic power gating architecture – Sleepwalking peripherals – Two performance levels – Embedded Buck/LDO regulator with on-the-fly selection • Security – Up to four tamper pins for static and dynamic intrusion detections – Data Flash • Optimized for secrets storage • Data Scrambling with user-defined key (optional) • Rapid Tamper erase on scrambling key and on one user-defined row • Silent access for side channel attack resistance – TrustRAM • Address and Data scrambling with user-defined key • Chip-level tamper detection on physical RAM to resist microprobing attacks • Rapid Tamper Erase on scrambling key and RAM data • Silent access for side channel attack resistance • Data remanence prevention – Peripherals • One True Random Generator (TRNG) • AES-128, SHA-256, and GCM cryptography accelerators (optional) • Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional) – TrustZone for flexible hardware isolation of memories and peripherals (optional) • Up to six regions for the Flash • Up to two regions for the Data Flash • Up to two regions for the SRAM • Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel – Secure Boot with SHA-based authentication (optional) – Up to three debug access levels – Up to three Chip Erase commands to erase part of or the entire embedded memories – Unique 128-bit serial number • Advanced Analog and Touch – One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels – Two Analog Comparators (AC) with window compare function – One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs – Three Operational Amplifiers (OPAMP) – One enhanced Peripheral Touch Controller (PTC): • Up to 20 self-capacitance channels • Up to 100 (10 x 10) mutual-capacitance channels • Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 2 • Hardware noise filtering and noise signal desynchronization for high conducted immunity • Driven Shield Plus for better noise immunity and moisture tolerance • Parallel Acquisition through Polarity control • Supports wake-up on touch from Standby Sleep mode • Communication Interfaces – Up to three Serial Communication Interfaces (SERCOM) that can operate as: • USART with full-duplex and single-wire half-duplex configuration • I2C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance • Serial Peripheral Interface (SPI) • ISO7816 on one instance • RS-485 on one instance • LIN Slave on one instance • Timers/Output Compare/Input Capture – Three 16-bit Timers/Counters (TC), each configurable as: • One 16-bit TC with two compare/capture channels • One 8-bit TC with two compare/capture channels • One 32-bit TC with two compare/capture channels, by using two TCs – 32-bit Real-Time Counter (RTC) with clock/calendar functions – Watchdog Timer (WDT) with Window mode • Input/Output (I/O) – Up to 25 programmable I/O lines – Eight external interrupts (EIC) – One non-maskable interrupt (NMI) – One Configurable Custom Logic (CCL) that supports: • Combinatorial logic functions, such as AND, NAND, OR, and NOR • Sequential logic functions, such as Flip-Flop and Latches • Qualification and Class-B Support – AEC-Q100 REVH (Grade 1 [-40ºC to +125ºC]) (planned) – Class-B safety library, IEC 60730 (future) • Debugger Development Support – Two-pin Serial Wire Debug (SWD) programming and debugging interface • Packages Type VQFN TQFP SSOP WLCSP(1) Pin Count 24 32 32 24 32 I/O Pins (up to) 17 25 25 17 25 Contact/Lead Pitch 0.5 mm 0.5 mm 0.8 mm 0.65 mm 0.4 mm Dimensions 4x4x0.9 mm 5x5x1 mm 7x7x1.2 mm 8.2x5.3x2.0 mm 2.79x2.79x0.482 mm Note:  1. Contact local sales for availability. SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 3 Table of Contents Features.......................................................................................................................... 1 1. Configuration Summary...........................................................................................14 2. Ordering Information................................................................................................16 3. Block Diagram......................................................................................................... 17 4. Pinouts.....................................................................................................................18 4.1. Multiplexed Signals.................................................................................................................... 19 4.2. Oscillators Pinout....................................................................................................................... 21 4.3. Serial Wire Debug Interface Pinout............................................................................................21 4.4. SERCOM Configurations........................................................................................................... 22 4.5. General Purpose I/O (GPIO) Clusters........................................................................................23 5. Signal Descriptions List .......................................................................................... 24 6. Power Considerations............................................................................................. 26 6.1. Power Supplies.......................................................................................................................... 26 6.2. Power Supply Constraints..........................................................................................................26 6.3. Power-On Reset and Brown-Out Detectors............................................................................... 27 6.4. Voltage Regulator.......................................................................................................................27 6.5. Typical Powering Schematic...................................................................................................... 27 7. Analog Peripherals Considerations......................................................................... 29 7.1. Reference Voltages....................................................................................................................30 7.2. Analog On Demand Feature...................................................................................................... 30 8. Device Startup......................................................................................................... 32 8.1. Clocks Startup............................................................................................................................32 8.2. Initial Instructions Fetching.........................................................................................................32 8.3. I/O Pins.......................................................................................................................................32 8.4. Performance Level Overview..................................................................................................... 32 9. Product Mapping..................................................................................................... 34 10. Memories.................................................................................................................36 10.1. Embedded Memories................................................................................................................. 36 10.2. NVM Rows................................................................................................................................. 38 10.3. Serial Number............................................................................................................................ 44 11. Processor and Architecture..................................................................................... 45 11.1. Cortex-M23 Processor............................................................................................................... 45 11.2. Nested Vector Interrupt Controller..............................................................................................47 11.3. High-Speed Bus System............................................................................................................ 50 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 4 11.4. SRAM Quality of Service............................................................................................................52 12. Peripherals Configuration Summary........................................................................54 13. SAM L11 Security Features.....................................................................................57 13.1. Features..................................................................................................................................... 57 13.2. ARM TrustZone Technology for ARMv8-M.................................................................................58 13.3. Crypto Acceleration....................................................................................................................69 13.4. True Random Number Generator (TRNG).................................................................................72 13.5. Secure Boot................................................................................................................................72 13.6. Secure Pin Multiplexing on SERCOM........................................................................................72 13.7. Data Flash .................................................................................................................................72 13.8. TrustRAM (TRAM)......................................................................................................................72 14. Boot ROM................................................................................................................73 14.1. Features..................................................................................................................................... 73 14.2. Block Diagram............................................................................................................................74 14.3. Product Dependencies...............................................................................................................74 14.4. Functional Description................................................................................................................74 15. PAC - Peripheral Access Controller.........................................................................96 15.1. Overview.................................................................................................................................... 96 15.2. Features..................................................................................................................................... 96 15.3. Block Diagram............................................................................................................................96 15.4. Product Dependencies...............................................................................................................96 15.5. Functional Description................................................................................................................98 15.6. Register Summary....................................................................................................................102 15.7. Register Description.................................................................................................................103 16. DSU - Device Service Unit.................................................................................... 127 16.1. Overview.................................................................................................................................. 127 16.2. Features................................................................................................................................... 127 16.3. Block Diagram..........................................................................................................................128 16.4. Signal Description.................................................................................................................... 128 16.5. Product Dependencies.............................................................................................................128 16.6. Debug Operation......................................................................................................................130 16.7. Programming............................................................................................................................131 16.8. Security Enforcement...............................................................................................................132 16.9. Device Identification................................................................................................................. 134 16.10. Functional Description..............................................................................................................135 16.11. Register Summary....................................................................................................................141 16.12. Register Description.................................................................................................................143 17. Clock System.........................................................................................................172 17.1. Clock Distribution..................................................................................................................... 172 17.2. Synchronous and Asynchronous Clocks..................................................................................173 17.3. Register Synchronization......................................................................................................... 174 17.4. Enabling a Peripheral...............................................................................................................177 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 5 17.5. On Demand Clock Requests....................................................................................................177 17.6. Power Consumption vs. Speed................................................................................................178 17.7. Clocks after Reset....................................................................................................................178 18. GCLK - Generic Clock Controller.......................................................................... 179 18.1. Overview.................................................................................................................................. 179 18.2. Features................................................................................................................................... 179 18.3. Block Diagram..........................................................................................................................179 18.4. Signal Description.................................................................................................................... 180 18.5. Product Dependencies.............................................................................................................180 18.6. Functional Description..............................................................................................................181 18.7. Register Summary....................................................................................................................187 18.8. Register Description.................................................................................................................189 19. MCLK – Main Clock...............................................................................................199 19.1. Overview.................................................................................................................................. 199 19.2. Features................................................................................................................................... 199 19.3. Block Diagram..........................................................................................................................199 19.4. Signal Description.................................................................................................................... 199 19.5. Product Dependencies.............................................................................................................199 19.6. Functional Description..............................................................................................................201 19.7. Register Summary....................................................................................................................206 19.8. Register Description.................................................................................................................206 20. FREQM – Frequency Meter.................................................................................. 222 20.1. Overview.................................................................................................................................. 222 20.2. Features................................................................................................................................... 222 20.3. Block Diagram..........................................................................................................................222 20.4. Signal Description.................................................................................................................... 222 20.5. Product Dependencies.............................................................................................................222 20.6. Functional Description..............................................................................................................224 20.7. Register Summary....................................................................................................................227 20.8. Register Description.................................................................................................................227 21. RSTC – Reset Controller.......................................................................................237 21.1. Overview.................................................................................................................................. 237 21.2. Features................................................................................................................................... 237 21.3. Block Diagram..........................................................................................................................237 21.4. Signal Description.................................................................................................................... 237 21.5. Product Dependencies.............................................................................................................237 21.6. Functional Description..............................................................................................................239 21.7. Register Summary....................................................................................................................241 21.8. Register Description.................................................................................................................241 22. PM – Power Manager............................................................................................243 22.1. Overview.................................................................................................................................. 243 22.2. Features................................................................................................................................... 243 22.3. Block Diagram..........................................................................................................................244 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 6 22.4. Signal Description.................................................................................................................... 244 22.5. Product Dependencies.............................................................................................................244 22.6. Functional Description..............................................................................................................245 22.7. Register Summary....................................................................................................................263 22.8. Register Description.................................................................................................................263 23. OSCCTRL – Oscillators Controller........................................................................271 23.1. Overview.................................................................................................................................. 271 23.2. Features................................................................................................................................... 271 23.3. Block Diagram..........................................................................................................................272 23.4. Signal Description.................................................................................................................... 272 23.5. Product Dependencies.............................................................................................................272 23.6. Functional Description..............................................................................................................274 23.7. Register Summary....................................................................................................................285 23.8. Register Description.................................................................................................................286 24. OSC32KCTRL – 32KHz Oscillators Controller......................................................319 24.1. Overview.................................................................................................................................. 319 24.2. Features................................................................................................................................... 319 24.3. Block Diagram..........................................................................................................................320 24.4. Signal Description.................................................................................................................... 320 24.5. Product Dependencies.............................................................................................................320 24.6. Functional Description..............................................................................................................322 24.7. Register Summary....................................................................................................................327 24.8. Register Description.................................................................................................................327 25. SUPC – Supply Controller.....................................................................................339 25.1. Overview.................................................................................................................................. 339 25.2. Features................................................................................................................................... 339 25.3. Block Diagram..........................................................................................................................340 25.4. Signal Description.................................................................................................................... 340 25.5. Product Dependencies.............................................................................................................340 25.6. Functional Description..............................................................................................................341 25.7. Register Summary....................................................................................................................348 25.8. Register Description.................................................................................................................349 26. WDT – Watchdog Timer........................................................................................ 366 26.1. Overview.................................................................................................................................. 366 26.2. Features................................................................................................................................... 366 26.3. Block Diagram..........................................................................................................................367 26.4. Signal Description.................................................................................................................... 367 26.5. Product Dependencies.............................................................................................................367 26.6. Functional Description..............................................................................................................368 26.7. Register Summary....................................................................................................................374 26.8. Register Description.................................................................................................................374 27. RTC – Real-Time Counter.....................................................................................386 27.1. Overview.................................................................................................................................. 386 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 7 27.2. Features................................................................................................................................... 386 27.3. Block Diagram..........................................................................................................................387 27.4. Signal Description.................................................................................................................... 388 27.5. Product Dependencies.............................................................................................................388 27.6. Functional Description..............................................................................................................390 27.7. Register Summary - Mode 0 - 32-Bit Counter..........................................................................402 27.8. Register Description - Mode 0 - 32-Bit Counter....................................................................... 403 27.9. Register Summary - Mode 1 - 16-Bit Counter..........................................................................426 27.10. Register Description - Mode 1 - 16-Bit Counter....................................................................... 427 27.11. Register Summary - Mode 2 - Clock/Calendar.........................................................................450 27.12. Register Description - Mode 2 - Clock/Calendar......................................................................451 28. DMAC – Direct Memory Access Controller........................................................... 476 28.1. Overview.................................................................................................................................. 476 28.2. Features................................................................................................................................... 476 28.3. Block Diagram..........................................................................................................................478 28.4. Signal Description.................................................................................................................... 478 28.5. Product Dependencies.............................................................................................................478 28.6. Functional Description..............................................................................................................480 28.7. Register Summary....................................................................................................................500 28.8. Register Description.................................................................................................................501 28.9. Register Summary - SRAM......................................................................................................532 28.10. Register Description - SRAM................................................................................................... 532 29. EIC – External Interrupt Controller........................................................................ 540 29.1. Overview.................................................................................................................................. 540 29.2. Features................................................................................................................................... 540 29.3. Block Diagram..........................................................................................................................540 29.4. Signal Description.................................................................................................................... 541 29.5. Product Dependencies.............................................................................................................541 29.6. Functional Description..............................................................................................................543 29.7. Register Summary....................................................................................................................550 29.8. Register Description.................................................................................................................551 30. NVMCTRL – Nonvolatile Memory Controller.........................................................572 30.1. Overview.................................................................................................................................. 572 30.2. Features................................................................................................................................... 572 30.3. Block Diagram..........................................................................................................................573 30.4. Signal Description.................................................................................................................... 573 30.5. Product Dependencies.............................................................................................................573 30.6. Functional Description..............................................................................................................575 30.7. Register Summary....................................................................................................................586 30.8. Register Description.................................................................................................................587 31. TRAM - TrustRAM................................................................................................. 614 31.1. Overview.................................................................................................................................. 614 31.2. Features................................................................................................................................... 614 31.3. Block Diagram..........................................................................................................................614 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 8 31.4. Signal Description.................................................................................................................... 614 31.5. Product Dependencies.............................................................................................................615 31.6. Functional Description..............................................................................................................616 31.7. Register Summary....................................................................................................................620 31.8. Register Description.................................................................................................................626 32. PORT - I/O Pin Controller......................................................................................638 32.1. Overview.................................................................................................................................. 638 32.2. Features................................................................................................................................... 638 32.3. Block Diagram..........................................................................................................................639 32.4. Signal Description.................................................................................................................... 639 32.5. Product Dependencies.............................................................................................................639 32.6. Functional Description..............................................................................................................641 32.7. Register Summary....................................................................................................................648 32.8. Register Description.................................................................................................................650 33. EVSYS – Event System........................................................................................ 685 33.1. Overview.................................................................................................................................. 685 33.2. Features................................................................................................................................... 685 33.3. Block Diagram..........................................................................................................................686 33.4. Product Dependencies.............................................................................................................686 33.5. Functional Description..............................................................................................................688 33.6. Register Summary....................................................................................................................695 33.7. Register Description.................................................................................................................698 34. SERCOM – Serial Communication Interface.........................................................724 34.1. Overview.................................................................................................................................. 724 34.2. Features................................................................................................................................... 724 34.3. Block Diagram..........................................................................................................................725 34.4. Signal Description.................................................................................................................... 725 34.5. Product Dependencies.............................................................................................................725 34.6. Functional Description..............................................................................................................727 35. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter.............................................................................................................733 35.1. Overview.................................................................................................................................. 733 35.2. USART Features......................................................................................................................733 35.3. Block Diagram..........................................................................................................................734 35.4. Signal Description.................................................................................................................... 734 35.5. Product Dependencies.............................................................................................................734 35.6. Functional Description..............................................................................................................736 35.7. Register Summary....................................................................................................................751 35.8. Register Description.................................................................................................................752 36. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................778 36.1. Overview.................................................................................................................................. 778 36.2. Features................................................................................................................................... 778 36.3. Block Diagram..........................................................................................................................779 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 9 36.4. Signal Description.................................................................................................................... 779 36.5. Product Dependencies.............................................................................................................779 36.6. Functional Description..............................................................................................................781 36.7. Register Summary....................................................................................................................790 36.8. Register Description.................................................................................................................791 37. SERCOM I2C – SERCOM Inter-Integrated Circuit................................................ 811 37.1. Overview...................................................................................................................................811 37.2. Features................................................................................................................................... 811 37.3. Block Diagram..........................................................................................................................812 37.4. Signal Description.................................................................................................................... 812 37.5. Product Dependencies.............................................................................................................812 37.6. Functional Description..............................................................................................................814 37.7. Register Summary - I2C Slave.................................................................................................833 37.8. Register Description - I2C Slave...............................................................................................833 37.9. Register Summary - I2C Master...............................................................................................851 37.10. Register Description - I2C Master............................................................................................ 852 38. TC – Timer/Counter...............................................................................................873 38.1. Overview.................................................................................................................................. 873 38.2. Features................................................................................................................................... 873 38.3. Block Diagram..........................................................................................................................874 38.4. Signal Description.................................................................................................................... 874 38.5. Product Dependencies.............................................................................................................875 38.6. Functional Description..............................................................................................................876 38.7. Register Description.................................................................................................................891 39. TRNG – True Random Number Generator............................................................965 39.1. Overview.................................................................................................................................. 965 39.2. Features................................................................................................................................... 965 39.3. Block Diagram..........................................................................................................................965 39.4. Signal Description.................................................................................................................... 965 39.5. Product Dependencies.............................................................................................................965 39.6. Functional Description..............................................................................................................967 39.7. Register Summary....................................................................................................................969 39.8. Register Description.................................................................................................................969 40. CCL – Configurable Custom Logic........................................................................977 40.1. Overview.................................................................................................................................. 977 40.2. Features................................................................................................................................... 977 40.3. Block Diagram..........................................................................................................................978 40.4. Signal Description.................................................................................................................... 978 40.5. Product Dependencies.............................................................................................................978 40.6. Functional Description..............................................................................................................980 40.7. Register Summary....................................................................................................................990 40.8. Register Description.................................................................................................................990 41. ADC – Analog-to-Digital Converter........................................................................995 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 10 41.1. Overview.................................................................................................................................. 995 41.2. Features................................................................................................................................... 995 41.3. Block Diagram..........................................................................................................................996 41.4. Signal Description.................................................................................................................... 996 41.5. Product Dependencies.............................................................................................................996 41.6. Functional Description..............................................................................................................998 41.7. Register Summary..................................................................................................................1011 41.8. Register Description...............................................................................................................1012 42. AC – Analog Comparators...................................................................................1040 42.1. Overview................................................................................................................................ 1040 42.2. Features................................................................................................................................. 1040 42.3. Block Diagram........................................................................................................................1041 42.4. Signal Description.................................................................................................................. 1041 42.5. Product Dependencies...........................................................................................................1041 42.6. Functional Description............................................................................................................1043 42.7. Register Summary..................................................................................................................1053 42.8. Register Description...............................................................................................................1053 43. DAC – Digital-to-Analog Converter......................................................................1071 43.1. Overview................................................................................................................................ 1071 43.2. Features................................................................................................................................. 1071 43.3. Block Diagram........................................................................................................................1071 43.4. Signal Description.................................................................................................................. 1071 43.5. Product Dependencies...........................................................................................................1071 43.6. Functional Description............................................................................................................1073 43.7. Register Summary..................................................................................................................1078 43.8. Register Description...............................................................................................................1078 44. OPAMP – Operational Amplifier Controller..........................................................1093 44.1. Overview................................................................................................................................ 1093 44.2. Features................................................................................................................................. 1093 44.3. Block Diagram........................................................................................................................1094 44.4. Signal Description.................................................................................................................. 1094 44.5. Product Dependencies...........................................................................................................1095 44.6. Functional Description............................................................................................................1097 44.7. Register Summary.................................................................................................................. 1111 44.8. Register Description................................................................................................................1111 45. PTC - Peripheral Touch Controller.......................................................................1120 45.1. Overview.................................................................................................................................1120 45.2. Features................................................................................................................................. 1120 45.3. Block Diagram........................................................................................................................ 1121 45.4. Signal Description...................................................................................................................1122 45.5. System Dependencies............................................................................................................1122 45.6. Functional Description............................................................................................................1124 46. Electrical Characteristics .................................................................................... 1125 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 11 46.1. Disclaimer...............................................................................................................................1125 46.2. Thermal Considerations......................................................................................................... 1125 46.3. Absolute Maximum Ratings....................................................................................................1126 46.4. General Operating Ratings.....................................................................................................1126 46.5. Supply Characteristics............................................................................................................1127 46.6. Maximum Clock Frequencies................................................................................................. 1127 46.7. Power Consumption............................................................................................................... 1129 46.8. Wake-Up Time........................................................................................................................1133 46.9. I/O Pin Characteristics............................................................................................................1134 46.10. Injection Current.....................................................................................................................1135 46.11. Analog Characteristics............................................................................................................1136 46.12. NVM Characteristics...............................................................................................................1152 46.13. Oscillators Characteristics......................................................................................................1153 46.14. Timing Characteristics............................................................................................................1160 47. 125°C Electrical Characteristics.......................................................................... 1166 47.1. Disclaimer...............................................................................................................................1166 47.2. General Operating Ratings.....................................................................................................1166 47.3. Power Consumption............................................................................................................... 1166 47.4. Analog Characteristics............................................................................................................1170 47.5. Oscillators Characteristics...................................................................................................... 1183 47.6. Timing Characteristics............................................................................................................ 1186 48. AC and DC Characteristics Graphs..................................................................... 1192 48.1. Typical Power Consumption over Temperature in Sleep Modes - 85°C.................................1192 48.2. Typical Power Consumption over Temperature in Sleep Modes - 125°C...............................1194 49. Packaging Information.........................................................................................1196 49.1. Package Marking Information.................................................................................................1196 49.2. Package Drawings..................................................................................................................1197 49.3. Soldering Profile.....................................................................................................................1204 50. Schematic Checklist............................................................................................ 1205 50.1. Introduction.............................................................................................................................1205 50.2. Power Supply......................................................................................................................... 1205 50.3. External Analog Reference Connections............................................................................... 1207 50.4. External Reset Circuit.............................................................................................................1209 50.5. Unused or Unconnected Pins.................................................................................................1210 50.6. Clocks and Crystal Oscillators................................................................................................1210 50.7. Programming and Debug Ports..............................................................................................1212 50.8. Peripherals Considerations.................................................................................................... 1215 51. Conventions.........................................................................................................1216 51.1. Numerical Notation.................................................................................................................1216 51.2. Memory Size and Type...........................................................................................................1216 51.3. Frequency and Time...............................................................................................................1216 51.4. Registers and Bits.................................................................................................................. 1217 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 12 52. Acronyms and Abbreviations...............................................................................1218 53. Datasheet Revision History................................................................................. 1221 53.1. Rev A - 09/2017..................................................................................................................... 1221 53.2. Rev B - 6/2018....................................................................................................................... 1221 The Microchip Web Site............................................................................................ 1222 Customer Change Notification Service......................................................................1222 Customer Support..................................................................................................... 1222 Product Identification System....................................................................................1223 Microchip Devices Code Protection Feature............................................................. 1223 Legal Notice...............................................................................................................1223 Trademarks............................................................................................................... 1224 Quality Management System Certified by DNV.........................................................1224 Worldwide Sales and Service....................................................................................1226 SAM L10/L11 Family © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 13 1. Configuration Summary Table 1-1. SAM L10/L11 Device-specific Features Device Flash + Data Flash Memory (KB) SRAM (KB) Pins SERCOM ADC Channels Analog Comparators Inputs PTC Selfcapacitance/ Mutualcapacitance Channels I/O Pins Tamper Pins Packages SAML10D14 16+2 4 SAML10D15 32+2 8 24 2 5 2 16/64 17 3 VQFN, SSOP SAML10D16 64+2 16 SAML10E14 16+2 4 32 3 10 4 20/100 25 4 VQFN, TQFP, WLCSP SAML10E15 32+2 8 SAML10E16 64+2 16 SAML11D14 16+2 8 SAML11D15 32+2 8 24 2 5 2 16/64 17 3 VQFN, SSOP SAML11D16 64+2 16 SAML11E14 16+2 8 32 3 10 4 20/100 25 4 VQFN, TQFP, WLCSP SAML11E15 32+2 8 SAML11E16 64+2 16 Table 1-2. SAM L10/L11 Family Features Feature SAM L10 Family SAM L11 Family MPU 1 2 TrustZone for ARMv8-M No Yes Secure Boot No Yes TrustRAM (Bytes) 256 256 DMA Channels 8 8 Data Scrambling TrustRAM TrustRAM, Data Flash Event System Channels 8 8 External Interrupt Lines/NMI 8/1 8/1 Brown-out Detection VDDIO and VDDCORE VDDIO and VDDCORE Secure Pin Multiplexing (on SERCOM) No Yes TC/Compare 3 3 RTC 1 1 Watchdog 1 1 DAC Channels 1 1 OPAMP 3 3 CCL Look-up Tables 2 2 Frequency Meter 1 1 Crypto Accelerators No Yes TRNG Yes Yes SAM L10/L11 Family Configuration Summary © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 14 Feature SAM L10 Family SAM L11 Family CRC Yes Yes Debug Access Levels (DAL) 2 3 SAM L10/L11 Family Configuration Summary © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 15 2. Ordering Information ATSAML 11 D 14 A M U T No character = Tray or Tube 16 = 64 KB 15 = 32 KB 14 = 16 KB D = 24 Pins E = 32 Pins 10 = Cortex-M23 CPU 11 = Cortex-M23 CPU with TrustZone Enabled A = TQFP M = VQFN Y = SSOP U = -40 - +85°C Matte Sn Plating F = -40 - +125°C Matte Sn Plating (Flash) SAML = Ultra Low Power Microcontroller U = WLCSP Note:  1. Devices in the WLCSP package include a factory programmed bootloader. Contact your local Microchip sales office for more information. 2. Devices can be factory programmed with securely key provisioned software. Contact your local Microchip sales office for more information. SAM L10/L11 Family Ordering Information © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 16 3. Block Diagram Figure 3-1. SAM L10/L11 Block Diagram 6 x SERCOM 8 x Timer Counter AHB-APB BRIDGE C M M High-Speed Bus Matrix PORT PORT SERIAL SWDIO WIRE S Cortex-M23 PROCESSOR Fmax 32 MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A 10-CHANNEL 12-bit ADC 1MSPS AIN[9..0] VREFA AIN[3..0] S SRAM CONTROLLER 16/8/8 KB RAM (SAM L11) - 16/8/4 KB RAM (SAM L10) M 3x TIMER / COUNTER EVENT SYSTEM S 3x SERCOM 2x ANALOG COMPARATORS PERIPHERAL TOUCH CONTROLLER AHB-APB BRIDGE B S PAD[0] WO[1] PAD[1] PAD[2] PAD[3] WO[0] VREFB 2KB Data Flash NVM CONTROLLER M DMA IOBUS DMA DMA DMA S REAL-TIME COUNTER WATCHDOG TIMER RESET OSCILLATORS CONTROLLER XOUT XIN XOUT32 XIN32 OSCULP32K OSC16M XOSC32K XOSC EXTERNAL INTERRUPT CONTROLLER MAIN CLOCKS CONTROLLER EXTINT[7..0] NMI GCLK_IO[4..0] FDPLL96M GENERIC CLOCK CONTROLLER POWER MANAGER RESET CONTROLLER OSC32K CONTROLLER SUPPLY CONTROLLER VREF BOD33 TRNG IN[5..0] CCL OUT[1..0] FREQUENCY METER DMA IN[3:0] VOUT 10-bit DAC 350kSPS DMA 256 Bytes TrustRAM PERIPHERAL ACCESS CONTROLLER DFLLULP OUT[3:0] CMP[1..0] VREFA 8 KB ROM S IDAU TrustZone for ARMv8-M Crypto Accelerators (AES128, SHA256, GCM) Secure Boot 64/32/16 KB Flash with Cache Data Scrambling EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT CRC-32 3x OPAMP OA0OUT / OA2OUT OA[0..2]POS OA[0..2]NEG SAM L11 Added Features MPU Voltage Regulators BOD12 XY[19..0] 128-bit Unique ID Note:  Number of SERCOM instances, PTC/ADC channels, Tamper input pins, and Analog Compare inputs differ on the packages pinout. SAM L10/L11 Family Block Diagram © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 17 4. Pinouts Figure 4-1. SAM L10/L11 24-pin VQFN Pinout 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 24 23 22 21 20 19 6 Figure 4-2. SAM L10/L11 24-pin SSOP Pinout 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 6 Figure 4-3. SAM L10/L11 32-pin VQFN and TQFP Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 SAM L10/L11 Family Pinouts © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 18 Figure 4-4. SAM L10/L11 32-pin WLCSP Pinout 4.1 Multiplexed Signals Each pin is controlled by the I/O Pin Controller (PORT) as a general purpose I/O and alternatively can be assigned to one of the peripheral functions: A, B, C, D, E, G, H, or I. The following table describes the peripheral signals multiplexed to the PORT I/O pins. The column “Reset State” indicates the reset state of the line with mnemonics: • "I/O" or "Function" indicates whether the I/O pin resets in I/O mode or in peripheral function mode. • “I” / ”O” / "Hi-Z" indicates whether the I/O is configured as an input, output or is tri-stated. • “PU” / “PD” indicates whether pullup, pulldown or nothing is enabled. Table 4-1. Pinout Multiplexing Pin Pin Name Supply A B(1) C(2)(3) D(2)(3) E G H I Reset State SSOP2 4 VQFN2 4 WLCSP 32 TQFP32 / VQFN3 2 EIC REF ADC AC PTC DAC OPAMP SERCO M SERCO M ALTER NATIVE TC RTC/ Debug AC/ GCLK CCL 5 2 A2 1 PA00 / XIN32 VDDAN A EXTIN T[0] XY[0] OA1NE G SERCO M1/ PAD[0] TC2/ WO[0] I/O, Hi-Z 6 3 A3 2 PA01 / XOUT3 2 VDDAN A EXTIN T[1] XY[1] OA1PO S SERCO M1/ PAD[1] TC2/ WO[1] I/O, Hi-Z 7 4 A4 3 PA02 VDDAN A EXTIN T[2] AIN[0] XY[2] VOUT OA0NE G SERCO M0/ PAD(2] I/O, Hi-Z 8 5 B3 4 PA03 VDDAN A EXTIN T[3] VREFA AIN[1] XY[3] OA2NE G SERCO M0/ PAD[3] I/O, Hi-Z 9 6 B4 5 PA04 VDDAN A EXTIN T[4] VREFB AIN[2] AIN[0] OA2OU T SERCO M0/ PAD[0] TC0/ WO[0] IN[0] I/O, Hi-Z 10 7 A5 6 PA05 VDDAN A EXTIN T[5] AIN[3] AIN[1] XY[4] OA2PO S SERCO M0/ PAD(1] TC0/ WO[1] IN[1] I/O, Hi-Z SAM L10/L11 Family Pinouts © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 19 Pin Pin Name Supply A B(1) C(2)(3) D(2)(3) E G H I Reset State SSOP2 4 VQFN2 4 WLCSP 32 TQFP32 / VQFN3 2 EIC REF ADC AC PTC DAC OPAMP SERCO M SERCO M ALTER NATIVE TC RTC/ Debug AC/ GCLK CCL C4 7 PA06 VDDAN A EXTIN T[6] AIN[4] AIN[2] XY[5] OA0PO S SERCO M0/ PAD[2] TC1/ WO[0] IN[2] I/O, Hi-Z B5 8 PA07 VDDAN A EXTIN T[7] AIN[5] AIN[3] OA0OU T SERCO M0/ PAD[3] TC1/ WO[1] OUT[0] I/O, Hi-Z 11 8 B6 9 VDDAN A - 12 9 C6 10 GNDAN A - 13 10 D4 11 PA08 VDDIO NMI AIN[6] XY[6] SERCO M1/ PAD[0] SERCO M2/ PAD[0] RTC/ IN[0] IN[3] I/O, Hi-Z D6 12 PA09 VDDIO EXTIN T[0] AIN[7] XY[7] SERCO M1/ PAD[1] SERCO M2/ PAD[1] RTC/ IN[1] IN[4] I/O, Hi-Z C5 13 PA10 VDDIO EXTIN T[1] AIN[8] XY[8] SERCO M1/ PAD[2] SERCO M2/ PAD[2] GCLK_I O[4] IN[5] I/O, Hi-Z D5 14 PA11 VDDIO EXTIN T[2] AIN[9] XY[9] SERCO M1/ PAD[3] SERCO M2/ PAD[3] GCLK_I O[3] OUT[1] I/O, Hi-Z 14 11 E6 15 PA14 / XOSC VDDIO EXTIN T[3] XY[10] SERCO M2/ PAD[2] SERCO M0/ PAD[2] TC0/ WO[0] GCLK_I O[0] I/O, Hi-Z 15 12 E5 16 PA15 / XOUT VDDIO EXTIN T[4] XY[11] SERCO M2/ PAD[3] SERCO M0/ PAD[3] TC0/ WO[1] GCLK_I O[1] I/O, Hi-Z 16 13 D3 17 PA16(4) VDDIO EXTIN T[5] XY[12] SERCO M1/ PAD[0] SERCO M0/ PAD[0] RTC/ IN[2] GCLK_I O[2] IN[0] I/O, Hi-Z 17 14 F5 18 PA17(4) VDDIO EXTIN T[6] XY[13] SERCO M1/ PAD[1] SERCO M0/ PAD[1] RTC/ IN[3] GCLK_I O[3] IN[1] I/O, Hi-Z 18 15 E4 19 PA18 VDDIO EXTIN T[7] XY[14] SERCO M1/ PAD[2] SERCO M0/ PAD[2] TC2/ WO[0] RTC/ OUT[0] AC/ CMP[0] IN[2] I/O, Hi-Z 19 16 E3 20 PA19 VDDIO EXTIN T[0] XY[15] SERCO M1/ PAD[3] SERCO M0/ PAD[3] TC2/ WO[1] RTC/ OUT[1] AC/ CMP[1] OUT[0] I/O, Hi-Z 20 17 F4 21 PA22(4) VDDIO EXTIN T[1] XY[16] SERCO M0/ PAD[0] SERCO M2/ PAD[0] TC0/ WO[0] RTC/ OUT[2] GCLK_I O[2] I/O, Hi-Z 21 18 F3 22 PA23(4) VDDIO EXTIN T[2] XY[17] SERCO M0/ PAD[1] SERCO M2/ PAD[1] TC0/ WO[1] RTC/ OUT[3] GCLK_I O[1] I/O, Hi-Z F2 23 PA24 VDDIO EXTIN T[3] SERCO M0/ PAD[2] SERCO M2/ PAD[2] TC1/ WO[0] I/O, Hi-Z E2 24 PA25 VDDIO EXTIN T[4] SERCO M0/ PAD[3] SERCO M2/ PAD[3] TC1/ WO[1] I/O, Hi-Z D2 25 PA27 VDDIO EXTIN T[5] GCLK_I O[0] I/O, Hi-Z 22 19 C2 26 RESET VDDIO I, PU 23 20 E1 27 VDDCO RE - 24 21 D1 28 GND - 1 22 C1 29 VDDOU T - 2 23 B1 30 VDDIO - SAM L10/L11 Family Pinouts © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 20 Pin Pin Name Supply A B(1) C(2)(3) D(2)(3) E G H I Reset State SSOP2 4 VQFN2 4 WLCSP 32 TQFP32 / VQFN3 2 EIC REF ADC AC PTC DAC OPAMP SERCO M SERCO M ALTER NATIVE TC RTC/ Debug AC/ GCLK CCL 3 24 B2 31 PA30 / SWCLK VDDIO EXTIN T[6] XY[18] SERCO M1/ PAD[2] TC1/ WO[0] SWCLK GCLK_I O[0] IN[3] SWCLK , I, PU 4 1 C3 32 PA31 / SWDIO( 4) VDDIO EXTIN T[7] XY[19] SERCO M1/ PAD[3] TC1/ WO[1] OUT[1] I/O, Hi-Z 1. All analog pin functions are on the peripheral function B. The peripheral function B must be selected to disable the digital control of the pin. 2. Refer to SERCOM Configurations to get the list of the supported features for each SERCOM instance. 3. 24-pin packages only have two SERCOM instances: SERCOM0 and SERCOM1. 4. The following pins are High Sink pins and have different properties than standard pins: PA16, PA17, PA22, PA23 and PA31. 4.2 Oscillators Pinout The oscillators are not mapped to the I/O Pin Controller (PORT) functions and their multiplexing is controlled by the Oscillators Controller (OSCCTRL) and 32 kHz Oscillators Controller (OSC32KCTRL) registers. Table 4-2. Oscillator Pinout Oscillator Supply Signal I/O pin XOSC VDDIO XIN PA14 XOUT PA15 XOSC32K VDDANA XIN32 PA00 XOUT32 PA01 To improve the cycle-to-cycle jitter of the XOSC32 oscillator, it is recommended to keep the neighboring pins of XIN32 and the following pins of XOUT32 as static as possible: Table 4-3. XOSC32 Jitter Minimization Package Pin Count Static Signal Recommended 32 PA02, PA03 24 PA02, PA03 4.3 Serial Wire Debug Interface Pinout The SWCLK pin is by default assigned to the SWCLK peripheral function G to allow debugger probe detection. A debugger probe detection (cold-plugging or hot-plugging) will automatically switch the SWDIO I/O pin to the SWDIO function, as long as the SWLCK peripheral function is selected. SAM L10/L11 Family Pinouts © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 21 Table 4-4. Serial Wire Debug Interface Pinout Signal Supply I/O pin SWCLK VDDIO PA30 SWDIO VDDIO PA31 4.4 SERCOM Configurations The following table lists the supported features for each SERCOM instance: Table 4-5. SERCOM Features Summary SERCOM Instance Protocol SERCOM0 SERCOM1 SERCOM2 SPI Yes Yes Yes I 2C (1) Yes High-speed mode (≤ 3,4 Mbit/s) Yes Fast plus Mode (≤ 1 Mbit/s) No USART Yes including: Hardware Handshaking IrDA Yes including: Hardware Handshaking IrDA Yes including: Hardware Handshaking IrDA RS-485 Auto-baud mode LIN Slave ISO7816 USART/SPI Receive Buffer Size Two-level Four-level Two-level Secure Pin Multiplexing (SAM L11 only) No Yes No Note:  1. I2C is not supported on all SERCOM pins. Refer to the SERCOM I2C Pins table for more details. 4.4.1 SERCOM I2C Pins The following table lists the SERCOM pins which support I2C: Table 4-6. SERCOM I2C Pins Pin Name SERCOM0 I2C Pad Name SERCOM1 I2C Pad Name PA16 SERCOM0/PAD[0] SERCOM1/PAD[0] PA17 SERCOM0/PAD[1] SERCOM1/PAD[1] PA22 SERCOM0/PAD[0] N/A PA23 SERCOM0/PAD[1] N/A 4.4.2 Secure Pin Multiplexing (on SERCOM) Pins The Secure Pin Multiplexing feature can be used on dedicated SERCOM I/O pins to isolate a secure communication with external devices from the non-secure application. Refer to 13.6 Secure Pin Multiplexing on SERCOM for more details. The following table lists the SERCOM pins that support the Secure Pin Multiplexing feature: SAM L10/L11 Family Pinouts © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 22 Table 4-7. Secure Pin Multiplexing on SERCOM Pins Pin Name Secure Pin Multiplexing Pad Name PA16 SERCOM1/PAD[0] PA17 SERCOM1/PAD[1] PA18 SERCOM1/PAD[2] PA19 SERCOM1/PAD[3] 4.5 General Purpose I/O (GPIO) Clusters Table 4-8. GPIO Clusters Package Cluster GPIO Supply Pins Connected to the Cluster 32-pin 1 PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 VDDANA/GNDANA 2 PA08 PA09 PA10 PA11 PA14 PA15 PA16 PA17 PA18 PA19 PA22 PA23 PA24 PA25 PA27 PA30 PA31 VDDIO/GND 24-pin 1 PA00 PA01 PA02 PA03 PA04 PA05 VDDANA/GND 2 PA08 PA14 PA15 PA16 PA17 PA18 PA19 PA22 PA23 PA30 PA31 VDDIO/GND SAM L10/L11 Family Pinouts © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 23 5. Signal Descriptions List The following table provides details on signal names classified by peripherals. Table 5-1. Signal Descriptions List Signal Name Function Type Generic Clock Generator - GCLK GCLK_IO[4:0] Generators Clock Source (Input) or Generic Clock Signal (Output) Digital I/O Oscillators Control - OSCCTRL XIN Crystal Oscillator or External Clock Input Analog Input (Crystal Oscillator)/Digital Input (External Clock) XOUT Crystal Oscillator Output Analog Output 32 kHz Oscillators Control - OSC32KCTRL XIN32 32.768 kHz Crystal Oscillator or External Clock Input Analog Input (Crystal Oscillator)/Digital Input (External Clock) XOUT32 32.768 kHz Crystal Oscillator Output Analog Output Serial Communication Interface - SERCOMx PAD[3:0] General SERCOM Pins Digital I/O Timer Counter - TCx WO[1:0] Capture Inputs or Waveform Outputs Digital I/O Real Timer Clock - RTC IN[3:0] Tamper Detection Inputs Digital Input OUT[3:0] Tamper Detection Outputs Digital Output Analog Comparators - AC AIN[3:0] AC Comparator Inputs Analog Input CMP[1:0] AC Comparator Outputs Digital Output Analog Digital Converter - ADC AIN[9:0] ADC Input Channels Analog Input VREFA(1) ADC External Reference Voltage A Analog Input VREFB ADC External Reference Voltage B Analog Input Digital Analog Converter - DAC VOUT DAC Voltage Output Analog Output VREFA(1) DAC External Reference Voltage A Analog Input Operational Amplifier - OPAMP OA[2:0]NEG OPAMP Negative Inputs Analog Input OA[2:0]POS OPAMP Positive Inputs Analog Input OA0OUT / OA2OUT OPAMP Outputs Analog Output Peripheral Touch Controller - PTC XY[19:0] X-lines and Y-lines Digital Output (X-line) /Analog I/O (Y-line) Custom Control Logic - CCL IN[5:0] Inputs to lookup table Digital Output OUT[1:0] Outputs from lookup table Digital Input SAM L10/L11 Family Signal Descriptions List © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 24 Signal Name Function Type External Interrupt Controller - EIC EXTINT[7:0] External Interrupts Pins Digital Input NMI Non-Maskable Interrupt Pin Digital Input General Purpose I/O - PORT PA11-PA00 / PA19-PA14 / PA25-PA22 / PA27 / PA31-PA30 General Purpose I/O Pin in Port A Digital I/O Reset Controller - RSTC RESET External Reset Pin (Active Level: LOW) Digital Input Debug Service Unit - DSU SWCLK Serial Wire Clock Digital Input SWDIO Serial Wire Bidirectional Data Pin Digital I/O 1. VREFA is shared between the ADC and DAC peripherals. SAM L10/L11 Family Signal Descriptions List © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 25 6. Power Considerations 6.1 Power Supplies The SAM L10/L11 have three different power supply pins: Table 6-1. SAM L10/L11 Power Supplies Name Associated Ground Powers VDDIO GND OSC16M, XOSC, the internal voltage regulator and BOD12 I/O lines: PA[11:08], PA[19:14], PA[25:22], PA[27] and PA[31:30] Voltage range, nominal: 1.62V - 3.63V, 3.3V VDDANA GNDANA OSCULP32K, XOSC32K, the POR/BOD33, the analog peripherals (ADC, AC, DAC, PTC, OPAMP) I/O lines: PA[07:00] Voltage range, nominal: 1.62V - 3.63V, 3.3V VDDCORE GND Core, embedded memories, peripherals, the FDPLL96M and the DFLLULP Voltage range: 0.9V - 1.2V Figure 6-1. Power Domain Overview VDDCORE VDDOUT VDDIO DAC AC ADC PTC V D D A N A G N D A N A BOD33 POR XOSC32K OSCULP32K OSC16MPA[19:14] VDDANA DFLLULP Digital Logic CPU, Peripherals, Memories VDDCORE XOSC PA[11:08] OPAMP PA[25:22] PA[27] PA[31:30] FDPLL96M VDDIO PA[07:00] BUCK LDO BOD12 GND 6.2 Power Supply Constraints The same voltage source must be applied to both VDDIO and VDDANA. Note:  This common voltage is referred to as VDD in the Data Sheet. The maximum supply falling and rising rates of the different power supplies must not exceed the values described in the Supply Characteristics section of the Electrical Characteristics chapters. SAM L10/L11 Family Power Considerations © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 26 6.3 Power-On Reset and Brown-Out Detectors The SAM L10/L11 embed three features to monitor, warn and reset the device: • A Power-on Reset (POR) on VDD (VDDANA and VDDIO): – Monitoring is always activated, including during device startup or during any sleep modes. – Having VDD below a fixed threshold voltage will reset the whole device. Note:  Refer to 46.11.2 Power-On Reset (POR) Characteristics for the rising and falling threshold voltages. • A Brown-out Detector (BOD33) on VDD (VDDANA and VDDIO): – The BOD33 can monitor VDD continuously (continuous mode) or periodically (sampled mode) with a programmable sample frequency in active mode as in any sleep modes. – A programmable threshold loaded from the NVM User Row is used to trigger an interrupt and/or reset the whole device. • A Brown-out Detector (BOD12) on VDDCORE. Note:  BOD12 is calibrated in production and its calibration parameters are stored in the NVM User Row. These data must not be changed to ensure correct device behavior. 6.4 Voltage Regulator The embedded voltage regulator is used to provide VDDCORE to the device. The SAM L10/L11 Voltage Regulator has three modes: • Linear (LDO) mode: The default mode after reset. • Switching (BUCK) mode: The most power efficient mode when the CPU and peripherals are running (Active mode). Note:  In Active mode, the voltage regulator can be selected on the fly between LDO (low-dropout) type regulator and Buck converter using the Supply Controller (SUPC) • Low-Power mode (LPVREG): The default mode, used when the device is in Standby Sleep mode. 6.5 Typical Powering Schematic The SAM L10/L11 requires a single supply from 1.62V to 3.63V. The following figures show the recommended power supply connections for two voltage regulators use cases: • LDO mode only • LDO/BUCK modes Note:  By default the LDO voltage regulator is enabled after any reset. Switching to BUCK mode is then required to benefit from its power efficiency. SAM L10/L11 Family Power Considerations © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 27 Figure 6-2. Power Supply Connections for Linear (LDO) Mode Only VDDANA VDDIO VDDCORE GND GNDANA VDDOUT (1.62V — 3.63V) Main Supply Note:  Refer to "Schematic Checklist" chapter for additional information. Figure 6-3. Power Supply Connections for Switching (BUCK) / Linear (LDO) Modes VDDANA VDDIO VDDCORE GND GNDANA VDDOUT (1.62V — 3.63V) Main Supply Note:  Refer to "Schematic Checklist" chapter for additional information. SAM L10/L11 Family Power Considerations © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 28 7. Analog Peripherals Considerations This chapter provides a global view of the analog system, which is composed of the following analog peripherals: AC, ADC, DAC, OPAMP. The analog peripherals can be connected to each other as illustrated in the following block diagram. Important:  When an analog peripheral is enabled, each analog output of the peripheral will be prevented from using the alternative functions of the output pads. This is also true even when the peripheral is used for internal purposes. Analog inputs do not interfere with alternate pad functions. Figure 7-1. Analog Signal Components Interconnections OPAMP0 GND DAC/REFBUF OA0TAP ADC OA0NEG shared with DAC Output OA0TAP OA0POS OA0NEG DAC/REFBUF GND VDDANA DAC/REFBUF UG GND OA0OUT OA1TAP OA1POS OA1OUT OA1TAP OA1POS OA1NEG OA0OUT GND DAC/REFBUF UG OPAMP2 GND OA1OUT OA0TAP OA2OUT OA0NEG OA2TAP OA2POS OA2NEG OA1OUT GND UG OA0POS OA1POS OA1NEG OA2NEG DAC/REFBUF R2 R1 R2 R1 R2 R1 + - + - GND VDDANA GND VDDANA GND VDDANA ADC/ AC VDDANA VDDANA DAC output buffer VREFA VOUT DAC Internal Input. INTREF VDDANA ENABLE ENABLE HYSTERESIS HYSTERESIS VDD SCALER BANDGAP + - + - CMP0 CMP1 AIN3 AIN2 AIN1 AIN0 COMP0 COMP1 COMPCTRLn DAC OPAMP2 ADC AIN0 OPAMP01 AIN0 AIN7 INTREF 1/1.6 VDDANA VREFB POST PROCESSING PRESCALER VREFA OPAMP1 + - MUXNEG MUXPOS OPAMP2 ADC OA0POS OA2POS OA1NEG AIN2 AIN5 AIN9 ... OA0OUT Rg_CONN DAC/REFBUF Rg_CONN OA2TAP DAC/REFBUF RES3TAP DAC Output REFBUF R2 R1 OA0OUT RES3TAP DAC/REFBUF DAC GND ... 1/2 VDDANA VDDANA 1/4 VDDIO 1/4 VDDCORE INTREF Temp Sensor 1/4 VDDANA SAM L10/L11 Family Analog Peripherals Considerations © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 29 Note:  Some OPAMP Outputs (OAxOUT) can be connected directly to specific Analog Comparator or ADC Inputs (AINx) if they share the same pad: as an example, OA0OUT can be connected to the Analog Comparator AIN3 or ADC AIN5 input (PA07 pin). 7.1 Reference Voltages Some analog peripherals require a reference voltage for proper operation. Apart from external voltages (that is, VDDANA or VREFx), the device has a DETREF module that provides two different internal voltage references: • BANDGAP: A stable voltage reference, fixed at 1.1V. • INTREF: A variable voltage reference, configured by the Voltage References System Control register in the Supply Controller (SUPC.VREF). The respective reference voltage source must be selected within each dedicated analog peripheral register: • ADC: Reference Control register (ADC.REFCTRL) • DAC: Reference Selection bits in the Control B register (DAC.CTRLB.REFSEL) Note:  AC has a fixed reference voltage to BANDGAP value. 7.2 Analog On Demand Feature The Analog On Demand feature allows the ADC and the AC analog peripherals to automatically enable the OPAMPx only when it is needed, thereby allowing a reduction in power consumption. It also allows the ADC analog block to be powered-off when a conversion is completed. Note:  The Analog On Demand is independent from the On Demand Clock request feature, which is used by peripherals to automatically request a source clock which was previously stopped. OPAMP case The Analog On Demand feature of the OPAMPx is activated by writing a '1' to the OPAMP.OPAMPCTRLx.ONDEMAND bit. In that case, the OPAMPx is automatically enabled when the ADC or the AC requests it (as an input) and is automatically disabled when no more requests are coming from these peripherals. CAUTION The Analog On Demand feature is not fully supported on cascaded OPAMPs. If several OPAMPs are cascaded together, only the OPAMPx that is connected to the ADC or AC can be enabled/disabled automatically. Upstream OPAMPs will not benefit from this feature. In Standby Sleep mode, the Analog On Demand feature is still supported if OPAMP.OPAMPCTRLx.RUNSTDBY=1. If OPAMP.OPAMPCTRLx.RUNSTDBY=0, the OPAMPx will be disabled entering this Sleep mode. ADC case For the ADC peripheral, Analog On Demand feature is enabled by writing the ADC.CTRLA.ONDEMAND bit to '1'. When this feature is activated, the analog block is powered-off when the conversion is complete. In Sleep mode, when an ADC start request is detected, the analog block is powered-on again and the ADC starts a new conversion after the start-up time delay. SAM L10/L11 Family Analog Peripherals Considerations © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 30 Note:  If the OPAMPx is set to accept Analog On Demand requests but the ADC is not, the ADC will send continuous requests to the OPAMPx keeping it enabled until the ADC is switching on another input. AC case For the AC peripheral,there is no explicit ONDEMAND bit. Analog On Demand requests are issued either when the AC is used in Single-Shot mode, or when comparisons are triggered by events from the Event System. Related Links 44. OPAMP – Operational Amplifier Controller 41. ADC – Analog-to-Digital Converter 42. AC – Analog Comparators SAM L10/L11 Family Analog Peripherals Considerations © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 31 8. Device Startup This section summarizes the SAM L10/L11 device startup sequence which starts after device power-up. After power-up, the device is kept in reset until the power has stabilized throughout the device. Once VDDIO/VDDANA and VDDCORE voltages reach a stable value, the internal reset is released. 8.1 Clocks Startup The device selects the OSC16M oscillator which is enabled by default after reset and configured at 4MHz. This 4MHz clock is also the default time base for the Generic Clock Generator 0 which provides the main clock (CLK_MAIN) to the system through the GLCK_MAIN clock. Note:  Other generic clocks are disabled to optimize power consumption. Some synchronous clocks require also to be active after startup. Note:  These active synchronous clocks also receive the 4MHz clock from Generic Clock Generator 0. Refer to the Clock Mask Register section in the Main Clock (MCLK) chapter to obtain the list of clocks that are running by default. 8.2 Initial Instructions Fetching After reset is released, the CPU starts fetching from the Boot ROM. Unless a debugger is connected and places the Boot ROM in a specific mode called Boot Interactive mode, the CPU will jump to the Flash memory loading the Program Counter (PC) and Stack Pointer (SP) values and start fetching flash user code. Before jumping to the Flash, the Boot ROM resets the two first 2kB of SRAM. The Clocks remain unchanged. Note:  SAM L10/L11 Boot Interactive mode allows a debugger to perform several actions on the device such as NVM areas integrity check, chip erase, etc. Refer to 14. Boot ROM for more information. In addition, the SAM L11 Boot ROM has extra security features, such as device integrity checks, memories and peripherals security attributions, and secure boot that can be executed before jumping to the Flash in Secure state. 8.3 I/O Pins After reset, the I/O pins are tri-stated except PA30 pin (configured as an input with pull-up enabled) which is by default assigned to the SWCLK peripheral function to allow debugger probe detection. 8.4 Performance Level Overview The SAM L10/L11 support two different performance levels: PL0 and PL2. The default performance level after reset is PL0. This performance level is aiming for the lowest power consumption by limiting logic speeds and CPU frequency. As a consequence, some peripherals and clock sources will work with limited capabilities. Full device functionality and performance will be ensured with PL2 mode. SAM L10/L11 Family Device Startup © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 32 Please refer to the Electrical Characteristics sections for more information. SAM L10/L11 Family Device Startup © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 33 9. Product Mapping Figure 9-1. SAM L10 Product Mapping AHB-APB Bridge C EVSYS SERCOM0 SERCOM1 SERCOM2 TC0 TC1 TC2 ADC DAC PTC TRNG CCL OPAMP TRAM 0x42000000 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42001C00 0x42002000 0x42002400 0x42002800 0x42002C00 0x42003000 0x42003400 0x42003800 0x42FFFFFF Reserved AHB-APB Bridge B Reserved DSU NVMCTRL DMAC HMATRIXHS Reserved 0x41000000 0x41002000 0x41004000 0x41006000 0x41008000 0x41010000 0x41FFFFFF AHB-APB Bridge A PAC PM MCLK RSTC OSCCTRL OSC32KCTRL SUPC GCLK WDT RTC EIC FREQM PORT AC 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40002000 0x40002400 0x40002800 0x40002C00 0x40003000 0x40003400 0x40003800 0x40FFFFFF Reserved Code Flash Reserved 0x00000000 0x00010000 0x00400000 AHB-APB AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C 0x40000000 0x41000000 0x42000000 Global Memory Space Code SRAM Reserved Peripherals Reserved Undefined Cortex-M23 Private Peripheral Bus (PPB) 0x00000000 0x20000000 0x20004000 0x40000000 0x60000000 0x80000000 0xE0000000 0xFFFFFFFF Data Flash 0x00400000 0x00400800 Boot ROM 0x02000000 0x02002000 Reserved 0x60000800 IOBUS Reserved IOBUS PORT 0x60000000 0x60000400 NVM Rows Reserved Reserved User row 0x00804000 0x00806020 0x00806038 0x0080C000 Temperature Log row Software Calibration row Boot Configuration row SAM L10/L11 Family Product Mapping © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 34 Figure 9-2. SAM L11 Product Mapping AHB-APB Bridge C EVSYS SERCOM0 SERCOM1 SERCOM2 TC0 TC1 TC2 ADC DAC PTC TRNG CCL OPAMP TRAM 0x42000000 0x42000400 0x42000800 0x42000C00 0x42001000 0x42001400 0x42001800 0x42001C00 0x42002000 0x42002400 0x42002800 0x42002C00 0x42003000 0x42003400 0x42003800 0x42FFFFFF Reserved AHB-APB Bridge B Reserved DSU NVMCTRL DMAC HMATRIXHS Reserved 0x41000000 0x41002000 0x41004000 0x41006000 0x41008000 0x41010000 0x41FFFFFF AHB-APB Bridge A PAC PM MCLK RSTC OSCCTRL OSC32KCTRL SUPC GCLK WDT RTC EIC FREQM PORT AC 0x40000000 0x40000400 0x40000800 0x40000C00 0x40001000 0x40001400 0x40001800 0x40001C00 0x40002000 0x40002400 0x40002800 0x40002C00 0x40003000 0x40003400 0x40003800 0x40FFFFFF Reserved Code Flash Reserved 0x00000000 0x00010000 0x00400000 AHB-APB AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C 0x40000000 0x41000000 0x42000000 Global Memory Space Code SRAM Reserved Peripherals Reserved Undefined Cortex-M23 Private Peripheral Bus (PPB) 0x00000000 0x20000000 0x20004000 0x40000000 0x60000000 0x80000000 0xE0000000 0xFFFFFFFF Data Flash 0x00400000 0x00400800 Boot ROM 0x02000000 0x02002000 Reserved 0x60000800 IOBUS Reserved IOBUS PORT 0x60000000 0x60000400 NVM Rows Reserved Reserved User row 0x00804000 0x00806020 0x00806038 0x0080C000 Temperature Log row Software Calibration row Boot Configuration row EIC Secure(1) 0x40002A00 PORT Secure(1) 0x40003200 PAC Secure(1) EVSYS Secure(1) NVMCTRL Secure(1) 0x41005000 0x40000200 0x42000200 Note:  1. This peripheral secure memory region will only appear if the peripheral is secured using PAC. Refer to Mix-Secure Peripherals for details. SAM L10/L11 Family Product Mapping © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 35 10. Memories 10.1 Embedded Memories The 32-bit physical memory address space is mapped as follows: Table 10-1. Memory Sizes Memory Base Address Size [KB] SAM L11x16(1) SAM L10x16(1) SAM L11x15(1) SAM L10x15(1) SAM L11x14 (1) SAM L10x14 (1) Flash 0x00000000 64 32 16 16 Data Flash 0x00400000 2 2 2 2 SRAM 0x20000000 16 8 8 4 Boot ROM 0x02000000 8 8 8 8 Note:  1. x = E or D. 10.1.1 Flash SAM L10/L11 devices embed 16 KB, 32 KB or 64 KB of internal Flash mapped at address 0x0000 0000. The Flash has a 512-byte (64 lines of 8 bytes) direct-mapped cache which is disabled by default after power up. The Flash is organized into rows, where each row contains four pages. The Flash has a row-erase and a page-write granularity. Table 10-2. Flash Memory Parameters Device Memory Size [KB] Number of Rows Row size [Bytes] Number of Pages Page size [Bytes] SAM L11x16 / SAM L10x16 (1) 64 256 256 1024 64 SAM L11x15 / SAM L10x15 (1) 32 128 256 512 64 SAM L11x14 / SAM L10x14 (1) 16 64 256 256 64 Note:  1. x = E or D. The Flash is divided in different regions. Each region has a dedicated lock bit preventing from writing and erasing pages on it. Refer to the NVM Memory Organization figures in the NVMCTRL chapter to get the different regions definition. Note:  The regions size is configured by the Boot ROM at device startup by reading the NVM Boot Configuration Row (BOCOR). Please refer to the 14. Boot ROM chapter for more information. Table 10-3. Flash Lock Regions Parameters Device SAM L10 SAM L11 Number of FLASH Lock Regions 2 4 Regions Name Flash Boot / Flash Application Flash Boot Secure / Flash Boot Non-Secure Flash Application Secure / Flash Application Non-Secure SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 36 10.1.2 Data Flash SAM L10/L11 devices embed 2 KB of internal Data Flash with Write-While-Read (WWR) capability mapped at address 0x0040 0000. The Data Flash can be programmed or erased while reading the Flash memory. It is not possible to read the Data Flash while writing or erasing the Flash. Note:  The Data Flash memory can be executable but requires more cycles to be read which may affect system performance. The Data Flash cannot be cached. The Data Flash is organized into rows, where each row contains four pages. The Data Flash has a rowerase and a page-write granularity. Table 10-4. Data Flash Memory Parameters Device Memory Size [KB] Number of Rows Row size [Bytes] Number of Pages Page size [Bytes] SAM L10/L11 2 8 256 32 64 The Data Flash is divided into one or two regions. Each region has a dedicated lock bit preventing from writing and erasing pages on it. Refer to the NVM Memory Organization figures in the NVMCTRL chapter to obtain the definitions of the different regions. Note:  The regions size is configured by the Boot ROM at device startup by reading the NVM Boot Configuration Row (BOCOR). Table 10-5. Data Flash Lock Regions Parameters Device SAM L10 SAM L11 Number of Data FLASH Lock Regions 1 2 Regions Name Data Flash Data Flash Secure / Data Flash Non-Secure 10.1.3 SRAM SAM L10/L11 devices embed 4 KB, 8 KB, or 16 KB of internal SRAM mapped at address 0x2000 0000. Table 10-6. SRAM Memory Parameters Device Memory Size [KB] SAM L11x16 / SAM L10x16 (1) 16 SAM L11x15 / SAM L10x15 (1) 8 SAM L11x14 (1) 8 SAM L10x14 (1) 4 Note:  1. x = E or D. SRAM is composed of 4KB sub-blocks which can be retained or not in STANDBY Low-Power mode to optimize power consumption. By default, all sub-blocks are retained, but it is possible to switch them off using the Power Manager (PM). SRAM retention is guaranteed for Watchog, External and System Reset resets. However, the two first 2kB of SRAM are reset by the Boot ROM. SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 37 Important:  SRAM retention is not guaranteed after Power Supply Resets (POR, BOD12 and BOD33). 10.1.4 Boot ROM SAM L10/L11 devices embed 8 KB of internal ROM mapped at address 0x0200 0000. Note:  Please refer to 14. Boot ROM for more details. 10.2 NVM Rows SAM L10 and SAM L11 have different Non Volatile Memory (NVM) rows which contain device configuration data that can be used by the system: Table 10-7. NVM Rows Mapping NVM Rows Address User Row (UROW) 0x00804000 Software Calibration Row 0x00806020 Temperature Log Row 0x00806038 Boot Configuration Row (BOCOR) 0x0080C000 10.2.1 NVM User Row (UROW) The Non Volatile Memory User Row (UROW) contains device configuration data that are automatically read at device power-on. This row can be updated using the NVMCTRL peripheral. When writing to the NVM User Row, the new values are not loaded by the other peripherals on the device until a device reset occurs. The NVM User Row can be read at the address 0x00804000. SAM L10 and SAM L11 have different NVM User Row mappings. Related Links 30. NVMCTRL – Nonvolatile Memory Controller 25. SUPC – Supply Controller 25.8.5 BOD33 26. WDT – Watchdog Timer 26.8.1 CTRLA 26.8.2 CONFIG 26.8.3 EWCTRL 10.2.1.1 SAM L10 User Row Table 10-8. SAM L10 UROW Bitfields Definition Bit Pos. Name Usage Factory Setting Related Peripheral Register 2:0 Reserved Reserved Reserved Reserved 5:3 NSULCK NVM UnLock Bits 0x7 NVMCTRL.NSULCK SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 38 Bit Pos. Name Usage Factory Setting Related Peripheral Register 6 Reserved Reserved Reserved Reserved 12:7 BOD33 Level BOD33 threshold level at power-on 0x6 SUPC.BOD33 13 BOD33 Disable BOD33 Disable at power-on 0x0 SUPC.BOD33 15:14 BOD33 Action BOD33 Action at power-on 0x1 SUPC.BOD33 24:16 BOD12 Calibration Parameters DO NOT CHANGE(1) 0x08F Reserved 25 WDT_RUNSTDBY WDT Runstdby at power-on 0x0 WDT.CTRLA 26 WDT_ENABLE WDT Enable at power-on 0x0 WDT.CTRLA 27 WDT_ALWAYSON WDT Always-On at power-on 0x0 WDT.CTRLA 31:28 WDT_PER WDT Period at power-on 0xB WDT.CONFIG 35:32 WDT_WINDOW WDT Window mode time-out at power-on 0xB WDT.CONFIG 39:36 WDT_EWOFFSET WDT Early Warning Interrupt Time Offset at power-on 0xB WDT.EWCTRL 40 WDT_WEN WDT Timer Window Mode Enable at power-on 0x0 WDT.CTRLA 41 BOD33_HYST BOD33 Hysteresis configuration at power-on 0x0 SUPC.BOD33 255:42 Reserved Reserved Reserved Reserved CAUTION 1. BOD12 is calibrated in production and its calibration parameters must not be changed to ensure the correct device behavior. Table 10-9. SAM L10 UROW Mapping Offset Bit Pos. Name 0x00 7:0 BOD33 Level - NSULCK Reserved 0x01 15:8 BOD33 Action BOD33 Disable BOD33 Level 0x02 23:16 BOD12 Calibration Parameters 0x03 31:24 WDT_PER WDT_ALWAYS ON WDT_ENABLE WDT_RUNSTD BY BOD12 Calibration Parameters 0x04 39:32 WDT_EWOFFSET WDT_WINDOW 0x05 47:40 Reserved BOD33_HYST WDT_WEN 0x06-0x1F 255:48 Reserved 10.2.1.2 SAM L11 User Row Table 10-10. SAM L11 UROW Bitfields Definition Bit Pos. Name Usage Factory Setting Related Peripheral Register 2:0 SULCK NVM Secure Region UnLock Bits 0x7 NVMCTRL.SULCK 5:3 NSULCK NVM Non-Secure Region UnLock Bits 0x7 NVMCTRL.NSULCK 6 Reserved Reserved Reserved Reserved 12:7 BOD33 Level BOD33 threshold level at power-on. 0x6 SUPC.BOD33 13 BOD33 Disable BOD33 Disable at power-on 0x0 SUPC.BOD33 15:14 BOD33 Action BOD33 Action at power-on 0x1 SUPC.BOD33 24:16 BOD12 Calibration Parameters Do not change(See Note 1 under Caution) 0x08F Reserved SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 39 Bit Pos. Name Usage Factory Setting Related Peripheral Register 25 WDT_RUNSTDBY WDT Runstdby at power-on 0x0 WDT.CTRLA 26 WDT_ENABLE WDT Enable at power-on 0x0 WDT.CTRLA 27 WDT_ALWAYSON WDT Always-On at power-on 0x0 WDT.CTRLA 31:28 WDT_PER WDT Period at power-on 0xB WDT.CONFIG 35:32 WDT_WINDOW WDT Window mode time-out at power-on 0xB WDT.CONFIG 39:36 WDT_EWOFFSET WDT Early Warning Interrupt Time Offset at power-on 0xB WDT.EWCTRL 40 WDT_WEN WDT Timer Window Mode Enable at power-on 0x0 WDT.CTRLA 41 BOD33_HYST BOD33 Hysteresis configuration at power-on 0x0 SUPC.BOD33 42 Reserved Reserved Reserved Reserved 43 RXN RAM is eXecute Never 0x1 IDAU.SECCTRL 44 DXN Data Flash is eXecute Never 0x1 NVMCTRL.SECCTRL 63:45 Reserved Reserved Reserved Reserved 71:64 AS Flash Application Secure Size = AS*0x100 0xFF IDAU.SCFGA 77:72 ANSC Flash Application Non-Secure Callable Size = ANSC*0x20 0x0 IDAU.SCFGA 79:78 Reserved Reserved Reserved Reserved 83:80 DS Data Flash Secure Size = DS*0x100 0x8 IDAU.SCFGA 87:84 Reserved Reserved Reserved Reserved 94:88 RS RAM Secure Size = RS*0x80 0x7F IDAU.SCFGR 95 Reserved Reserved Reserved Reserved 96 URWEN User Row Write Enable 0x1 NVMCTRL.SCFGAD 127:97 Reserved Reserved Reserved Reserved 159:128 NONSECA(1) Peripherals Non-Secure Status Fuses for Bridge A 0x0000_0000 PAC.NONSECA 191:160 NONSECB(2, 3) Peripherals Non-Secure Status Fuses for Bridge B 0x0000_0000 PAC.NONSECB 223:192 NONSECC Peripherals Non-Secure Status Fuses for Bridge C 0x0000_0000 PAC.NONSECC 255:224 USERCRC CRC of NVM User Row bits 223:64 0x8433651E Boot ROM Note:  1. The PAC Peripheral is always secured regardless of its bit value 2. The IDAU and NVMCTRL peripherals are always secured regardless of their bit values. 3. The DSU peripheral is always non-secured regardless of its bit value. CAUTION 1. BOD12 is calibrated in production and its calibration parameters must not be changed to ensure the correct device behavior. Table 10-11. SAM L11 UROW Mapping Offset Bit Pos. Name 0x00 7:0 BOD33 Level - NSULCK SULCK 0x01 15:8 BOD33 Action BOD33 Disable BOD33 Level 0x02 23:16 BOD12 Calibration Parameters SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 40 Offset Bit Pos. Name 0x03 31:24 WDT_PER WDT_ALWAYS ON WDT_ENABLE WDT_RUNSTD BY BOD12 Calibration Parameters 0x04 39:32 WDT_EWOFFSET WDT_WINDOW 0x05 47:40 Reserved DXN RXN Reserved BOD33_HYST WDT_WEN 0x06 55:48 Reserved 0x07 63:56 Reserved 0x08 71:64 AS 0x09 79:72 Reserved ANSC 0x0A 87:80 Reserved DS 0x0B 95:88 Reserved RS 0x0C 103:96 Reserved URWEN 0x0D-0xF 127:104 Reserved 0x10-0x13 159:128 NONSECA 0x14-0x17 191:160 NONSECB 0x18-0x1B 223:192 NONSECC 0x1C-0x1F 255:224 USERCRC 10.2.2 NVM Software Calibration Area The NVM Software Calibration Area contains calibration data that can be used by some peripherals, such as the ADC. Note:  Calibration data are determined and written during production test and cannot be written. The NVM Software Calibration Area can be read at address 0x00806020. Table 10-12. NVM Software Calibration Bitfields Definition Bit Position Name Description 2:0 ADC LINEARITY ADC Linearity Calibration. Should be written to CALIB register. 5:3 ADC BIASCAL ADC Bias Calibration. Should be written to CALIB register. 8:6 DFLLULP Division Factor in PL0 DFLLULP Division Factor in PL0. Should be written to DFLLULPCTRL register. 11:9 DFLLULP Division Factor in PL2 DFLLULP Division Factor in PL2. Should be written to DFLLULPCTRL register. 127:12 Reserved Reserved Table 10-13. NVM Software Calibration Row Mapping Offset Bit Pos. Name 0x00 7:0 DFLLULP Division Factor in PL0 ADC BIASCAL ADC LINEARITY 0x01 15:8 Reserved DFLLULP Division Factor in PL2 DFLLULP Division Factor in PL0 0x02-0xF 127:16 Reserved 10.2.3 NVM Temperature Log Row The NVM Temperature Log Row contains calibration data that are determined and written during production test and cannot be written. These calibration values are required for calculating the temperature from measuring the temperature sensor in the Supply Controller (SUPC) by the ADC. SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 41 The NVM Temperature Log Row can be read at address 0x00806038. Table 10-14. Temperature Log Row Bitfields Definition Bit Position Name Description 7:0 ROOM_TEMP_VAL_INT Integer part of room temperature in °C 11:8 ROOM_TEMP_VAL_DEC Decimal part of room temperature 19:12 HOT_TEMP_VAL_INT Integer part of hot temperature in °C 23:20 HOT_TEMP_VAL_DEC Decimal part of hot temperature 31:24 ROOM_INT1V_VAL 2’s complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) 39:32 HOT_INT1V_VAL 2’s complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) 51:40 ROOM_ADC_VAL Temperature sensor 12bit ADC conversion at room temperature 63:52 HOT_ADC_VAL Temperature sensor 12bit ADC conversion at hot temperature Important:  Hot temperature corresponds to the max operating temperature +/- 5%, so 85°C +/- 5% (package grade 'U') or 125°C +/- 5% (package grade 'F'). Table 10-15. Temperature Log Row Mapping Offset Bit Pos. Name 0x00 7:0 ROOM_TEMP_VAL_INT 0x01 15:8 HOT_TEMP_VAL_INT ROOM_TEMP_VAL_DEC 0x02 23:16 HOT_TEMP_VAL_DEC HOT_TEMP_VAL_INT 0x03 31:24 ROOM_INT1V_VAL 0x04 39:32 HOT_INT1V_VAL 0x05 47:40 ROOM_ADC_VAL 0x06 55:48 HOT_ADC_VAL ROOM_ADC_VAL 0x07 63:56 HOT_ADC_VAL 10.2.4 NVM Boot Configuration Row (BOCOR) The Non-Volatile Memory Boot Configuration Row (BOCOR) contains device configuration data that are automatically read by the Boot ROM program at device startup. This row can be updated using the NVMCTRL peripheral. When writing to the NVM Boot Configuration Row, the new values are not loaded by the other peripherals on the device until a device reset occurs. The NVM Boot Configuration Row can be read at address 0x0080C000. SAM L10 and SAM L11 have different NVM Boot Configuration Row mappings. 10.2.4.1 SAM L10 Boot Configuration Row Table 10-16. SAM L10 BOCOR Bitfields Definition Bit Pos. Name Usage Factory Setting Related Peripheral Register 31:0 Reserved Reserved Reserved Reserved 39:32 BOOTPROT Boot Protection size = BOOTPROT*0x100 0x00 Boot ROM SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 42 Bit Pos. Name Usage Factory Setting Related Peripheral Register 95:40 Reserved Reserved Reserved Reserved 127:96 ROMVERSION ROM Code Version Device Dependent Boot ROM 511:128 Reserved Reserved Reserved Reserved 639:512 CRCKEY CRC Key All '1's Boot ROM 2047:640 Reserved Reserved Reserved Reserved Table 10-17. SAM L10 BOCOR Mapping Offset Bit Pos. Name 0x00-0x03 31:0 Reserved 0x04 39:32 BOOTPROT 0x05-0x0B 95:40 Reserved 0x0C-0x0F 127:96 ROMVERSION 0x10-0x3F 511:128 Reserved 0x40-0x4F 639:512 CRCKEY 0x50-0xFF 2047:640 Reserved 10.2.4.2 SAM L11 Boot Configuration Row Table 10-18. SAM L11 BOCOR Bitfields Definition Bit Pos. Name Usage Factory Setting Related Peripheral Register 7:0 Reserved Reserved Reserved Reserved 15:8 BS Boot Flash Secure Size = BS*0x100 0x00 IDAU.SCFGB 21:16 BNSC Boot Flash Non-Secure Callable Size = BNSC*0x20 0x00 IDAU.SCFGB 23:22 Reserved Reserved Reserved Reserved 31:24 BOOTOPT Boot Option 0xA0 Boot ROM 39:32 BOOTPROT Boot Protection size = BOOTPROT*0x100 0x00 IDAU.SCFGB 47:40 Reserved Reserved Reserved Reserved 48 BCWEN Boot Configuration Write Enable 0x1 NVMCTRL.SCFGB 49 BCREN Boot Configuration Read Enable 0x1 NVMCTRL.SCFGB 63:50 Reserved Reserved Reserved Reserved 95:64 BOCORCRC Boot Configuration CRC for bit 63:0 0xC1D7ECC3 Boot ROM 127:96 ROMVERSION ROM Code Version 0x0000003A Boot ROM 255:128 CEKEY0 Chip Erase Key 0 All 1s Boot ROM 383:256 CEKEY1 Chip Erase Key 1 All 1s Boot ROM 511:384 CEKEY2 Chip Erase Key 2 All 1s Boot ROM 639:512 CRCKEY CRC Key All 1s Boot ROM 895:640 BOOTKEY Secure Boot Key All 1s Boot ROM 1791:896 Reserved Reserved Reserved Reserved 2047:1792 BOCORHASH Boot Configuration Row Hash All 1s Boot ROM SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 43 Table 10-19. SAM L11 BOCOR Mapping Offset Bit Pos. Name 0x00 7:0 Reserved 0x01 15:8 BS 0x02 23:16 Reserved BNSC 0x03 31:24 BOOTOPT 0x04 39:32 BOOTPROT 0x05 47:40 Reserved 0x06 55:48 Reserved BCREN BCWEN 0x07 63:56 Reserved 0x08-0x0B 95:64 BOCORCRC 0x0C-0x0F 127:96 ROMVERSION 0x10-0x1F 255:128 CEKEY0 0x20-0x2F 383:256 CEKEY1 0x30-0x3F 511:384 CEKEY2 0x40-0x4F 639:512 CRCKEY 0x50-0x6F 895:640 BOOTKEY 0x70-0xDF 1791:896 Reserved 0xE0-0xFF 2047:1792 BOCORHASH 10.3 Serial Number Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following addresses of the NVM Rows memory space: • Word 0: 0x0080A00C • Word 1: 0x0080A040 • Word 2: 0x0080A044 • Word 3: 0x0080A048 Note:  The uniqueness of the serial number is only guaranteed when considering all 128 bits. SAM L10/L11 Family Memories © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 44 11. Processor and Architecture 11.1 Cortex-M23 Processor The SAM L10/L11 implement the ARM® Cortex®-M23 processor, based on the ARMv8-M Baseline Architecture, which is the smallest and most energy efficient ARM processor with ARM TrustZone® security technology. TrustZone® for ARMv8-M provides hardware-enforced security isolation between trusted and the untrusted resources on a Cortex™-M23 based device, while maintaining the efficient exception handling. The implemented ARM Cortex-M23 is revision r1p0. The ARM Cortex-M23 core has two bus interfaces: • Single 32-bit AMBA®-5 AHB-Lite system interface that provides connections to peripherals and memories. • Single 32-bit I/O port bus interfacing to the PORT and Crypto Accelerator peripherals with 1-cycle load and store. Note:  For more information refer to http://www.arm.com 11.1.1 Cortex-M23 Configuration This table gives the configuration for the ARM Cortex-M23 processor. Table 11-1. SAM L10/L11 Cortex-M23 Configuration Features Cortex-M23 Configurable Options SAM L10 Implementation SAM L11 Implementation Memory Protection Unit (MPU) Not present, 4, 8, 12, or 16 regions One MPU with 4 regions Two MPUs with 4 regions each (one Secure / one Non-Secure) Security Attribute Unit (SAU) Absent, 4-region, or 8-region Absent Absent Implementation Defined Attribution Unit (IDAU) Present or Absent Absent Present SysTick timer(s) Absent, 1 timer or 2 timers (one Secure and one Non-Secure) One SysTick timer Two timers (One Secure / One Non-Secure) Vector Table Offset Register Present or absent Present (one Vector table) Present (two Vector tables) Reset all registers Present or absent Absent Absent Multiplier Fast (one cycle) or slow (32 cycles) Fast (one cycle) Fast (one cycle) Divider Fast (17 cycles) or slow (34 cycles) Fast (17 cycles) Fast (17 cycles) Interrupts External interrupts 0-240 43(1) 45(1) Instruction fetch width 16-bit only or 32-bit 32-bit 32-bit Single-cycle I/O port Present or absent Present Present Architectural clock gating present Present or absent Present Present Data endianness Little-endian or big-endian Little-endian Little-endian Halt debug support Present or absent Absent Absent Wake-up interrupt controller (WIC) Present or absent Absent Absent Number of breakpoint comparators 0, 1, 2, 3, 4 4 4 Number of watchpoint comparators 0, 1, 2, 3, 4 2 2 SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 45 Features Cortex-M23 Configurable Options SAM L10 Implementation SAM L11 Implementation Cross Trigger Interface (CTI) Present or absent Absent Absent Micro Trace Buffer (MTB) Present or absent Absent Absent Embedded Trace Macrocell (ETM) Present or absent Absent Absent JTAGnSW debug protocol Selects between JTAG or SerialWire interfaces for the DAP Serial-Wire Serial-Wire Multi-drop for Serial Wire Present or absent Absent Absent Note:  1. Refer to Table 11-3 for more information. For more details, refer to the ARM Cortex-M23 Processor Technical Reference Manual (http:// www.arm.com). 11.1.2 Cortex-M23 Core Peripherals The processor has the following core peripheral: • System Timer (SysTick) – The System Timer is a 24-bit timer clocked by the core frequency. Important:  On SAM L11 devices, there are two System timers, one for Secure state and one for Non-secure state. • Nested Vectored Interrupt Controller (NVIC) – The NVIC is an embedded interrupt controller that supports low latency interrupt processing. Important:  On SAM L11 devices, there are two Vector tables: the Secure Vector table and the Non-Secure Vector table. • System Control Block (SCB) – The System Control Block (SCB) provides system implementation information and system control that includes configuration, control, and reporting of system exceptions • Memory Protection Unit (MPU) – The MPU improves system reliability by defining the memory attributes for different memory regions. Important:  On SAM L11 devices, there are two MPUs: one for the Secure state and one for the Non-secure state. Each MPU can define memory access permissions and attributes independently. • Security Attribution Unit (SAU) – The SAU improves system security by defining security attributes for different regions. SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 46 Important:  The SAU is absent from SAM L10 and SAM L11 devices. For more details, refer to the ARM Cortex-M23 Processor Technical Reference Manual (http:// www.arm.com). Table 11-2. Cortex-M23 Core Peripherals Address Map Core Peripherals Base Address (SAM L10 and SAM L11) (Non-Secure) Alias Base Address (SAM L11 only) System Timer (SysTick) 0xE000E010 0xE002E010 Nested Vectored Interrupt Controller (NVIC) 0xE000E100 0xE002E100 System Control Block (SCB) 0xE000ED00 0xE002ED00 Memory Protection Unit (MPU) 0xE000ED90 0xE002ED90 11.1.3 Single Cycle I/O Port The device allows direct access to PORT registers. Accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, so the Cortex-M23 processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O access to be sustained for as long as necessary. Note:  The Crypto Accelerator peripheral also benefits from this port. Refer to the 13.3 Crypto Acceleration section for more information. 11.2 Nested Vector Interrupt Controller 11.2.1 Overview The Nested Vectored Interrupt Controller (NVIC) in the SAM L10/L11 supports up to 45 interrupt lines with four different priority levels + 1 Non Maskable Interrupt (NMI) line. For more details, refer to the Cortex-M23 Technical Reference Manual (http://www.arm.com). 11.2.2 Interrupt Line Mapping Each interrupt line is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a 1 to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing 1 to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/ CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt. SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 47 Table 11-3. Interrupt Line Mapping Module Source NVIC line EIC NMI – External Interrupt Controller NMI NMI PM – Power Manager PLRDY 0 MCLK - Main Clock CKRDY OSCCTRL - Oscillators Controller XOSCRDY XOSCFAIL OSC16MRDY DFLLULPRDY DFLLULPLOCK DFLLULPNOLOCK DPLLLCKR DPLLLCKF DPLLLTO DPLLLDRTO OSC32KCTRL - 32KHz Oscillators Controller XOSC32KRDY CLKFAIL SUPC - Supply Controller BOD33RDY BOD33DET B33SRDY VREGRDY VCORERDY ULPVREFRDY WDT – Watchdog Timer EW 1 RTC – Real Time Counter CMP0 2 CMP1 OVF PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 TAMPER EIC – External Interrupt Controller EXTINT 0 3 EXTINT 1 4 EXTINT 2 5 EXTINT 3 6 EXTINT 4..7 7 NSCHK(1) FREQM - Frequency Meter DONE 8 NVMCTRL – Non-Volatile Memory Controller DONE 9 PROGE SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 48 Module Source NVIC line LOCKE NVME KEYE NSCHK(1) PORT - I/O Pin Controller NSCHK(1) 10 DMAC - Direct Memory Access Controller SUSP 0 11 TERR 0 TCMPL 0 SUSP 1 12 TERR 1 TCMPL 1 SUSP 2 13 TERR 2 TCMPL 2 SUSP 3 14 TERR 3 TCMPL 3 SUSP 4..7 15 TERR 4..7 TCMPL 4..7 EVSYS – Event System EVD 0 16 OVR 0 EVD 1 17 OVR 1 EVD 2 18 OVR 2 EVD 3 19 OVR 3 NSCHK(1) 20 PAC - Peripheral Access Controller ERR 21 SERCOM0 – Serial Communication Interface 0 (Interrupt Sources vary depending on SERCOM mode) Interrupt Bit 0 22 Interrupt Bit 1 23 Interrupt Bit 2 24 Interrupt Bits 3..6 25 SERCOM1 – Serial Communication Interface 1 (Interrupt Sources vary depending on SERCOM mode) Interrupt Bit 0 26 Interrupt Bit 1 27 Interrupt Bit 2 28 Interrupt Bit 3..6 29 SERCOM2 – Serial Communication Interface 2 (Interrupt Sources vary depending on SERCOM mode) Interrupt Bit 0 30 Interrupt Bit 1 31 Interrupt Bit 2 32 Interrupt Bits 3..6 33 TC0 – Timer Counter 0 ERR A 34 MC 0 SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 49 Module Source NVIC line MC 1 OVF TC1 – Timer Counter 1 ERR A 35 MC 0 MC 1 OVF TC2 – Timer Counter 2 ERR A 36 MC 0 MC 1 OVF ADC – Analog-to-Digital Converter OVERRUN 37 WINMON RESRDY 38 AC – Analog Comparator COMP 0 39 COMP 1 WIN 0 DAC – Digital-to-Analog Converter UNDERRUN 40 EMPTY 41 PTC – Peripheral Touch Controller EOC 42 WCOMP TRNG - True Random Number Generator DATARDY 43 TRAM - Trust RAM DRP 44 ERR Note:  1. NSCHK interrupt sources will not generate any interrupts for SAM L10 devices. 11.3 High-Speed Bus System 11.3.1 Features The High-Speed Bus Matrix has the following features: • 32-bit data bus • Allows concurrent accesses from different masters to different slaves • Operation at a one-to-one clock frequency with the bus masters 11.3.2 Configuration There are two master-to-slave connections to optimize system bandwidth: • Multi-Slave Masters which are connected through the AHB bus matrix Table 11-4. AHB Multi-Slave Masters AHB Multi-Slave Masters Cortex-M23 Processor DSU - Device Service Unit DMAC - Direct Memory Access Controller / Data Access SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 50 Table 11-5. AHB Slaves AHB Slaves Flash Memory AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C SRAM Port 0 - Cortex-M23 Access SRAM Port 1 - DMAC Access SRAM Port 2 - DSU Access Boot ROM • Privileged SRAM-access Masters which have a direct access to some dedicated SRAM ports Table 11-6. Privileged SRAM-access Masters Privileged SRAM-access Masters DMAC - Fetch 0 Access DMAC - Fetch 1 Access DMAC - Write Back 0 Access DMAC - Write Back 1 Access Note:  Privileged SRAM-access Masters rely on SRAM quality of service to define priority levels (SRAM Port ID). Refer to 11.4 SRAM Quality of Service for more information. SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 51 Figure 11-1. Master-to-Slave Access Cortex-M23 0 DSU 1 High-Speed Bus SLAVES Flash AHB-APB Bridge A AHB-APB Bridge B AHB-APB Bridge C Multi-Slave MASTERS CM23 DSU SRAM DSU 1 DSU 0 1 2 3 4 5 6 SRAM PORT ID DMAC Data 2 DMAC Data DMAC Fetch 0 DMAC Fetch 1 DMAC WB 0 DMAC WB 1 DMAC Fetch 0 DSU Privileged SRAM-access MASTERS DMAC Fetch 1 DMAC WB 0 DSU DMAC WB 1 Boot ROM 11.4 SRAM Quality of Service To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority levels can be assigned to the masters for different types of access. The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the RAM, the RAM also receives a QoS level. The QoS levels and their corresponding bit values are shown in the following table. Table 11-7. Quality of Service Value Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Note:  If a master is configured with QoS level DISABLE (0x0) or LOW (0x1), there will be a minimum latency of one cycle to get RAM access. SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 52 The priority order for concurrent accesses are decided by two factors: • As first priority, the QoS level for the master. • As a second priority, a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for more details. Table 11-8. HS SRAM Port Connections QoS HS SRAM Port Connection Port ID Connection Type QoS default QoS DMAC - Direct Memory Access Controller - Write-Back 1 Access 6 Direct DMAC QOSCTRL.WRBQOS 0x2 DMAC - Direct Memory Access Controller - Write-Back 0 Access 5 Direct DMAC QOSCTRL.WRBQOS 0x2 DMAC - Direct Memory Access Controller - Fetch 1 Access 4 Direct DMAC QOSCTRL.FQOS 0x2 DMAC - Direct Memory Access Controller - Fetch 0 Access 3 Direct DMAC QOSCTRL.FQOS 0x2 DMAC - Direct Memory Access Controller - Data Access 2 Bus Matrix DMAC QOSCTRL.DQOS 0x2 DSU - Device Service Unit 1 Bus Matrix DSU CFG.LQOS 0x2 CM23 - Cortex M23 Processor 0 Bus Matrix 0x41008114, bits[1:0](1) 0x3 Note:  1. The CPU QoS level can be written/read, using 32-bit access only. SAM L10/L11 Family Processor and Architecture © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 53 12. Peripherals Configuration Summary Table 12-1. Peripherals Configuration Summary Peripheral name Base address IRQ line AHB clock APB clock Generic Clock PAC Events DMA Power domain Index Enabled at Reset Index Enabled at Reset Index Index Write Protection at Reset User Generator Sleep Walking Index Name AHB-APB Bridge A 0x40000000 — 0 Y — — — — — — — N/A — PDSW PAC 0x40000000 21: ERR 6 Y 0 Y — 0 N — 49: ERR Y — PDSW PM 0x40000400 0: PLRDY — — 1 Y — 1 N — — N/A — PDAO MCLK 0x40000800 0: CKRDY — — 2 Y — 2 N — — N/A — PDSW RSTC 0x40000C00 — — — 3 Y — 3 N — — N/A — PDAO OSCCTRL 0x40001000 0: XOSCRDY, XOSCFAIL, OSC16MR DY, DFLLULPR DY, DFLLULPL OCK, DFLLULPN OLOCK, DPLLLCKR, DPLLLCKF, DPLLLTO, DPLLLDRT O — — 4 Y 0: FDPLL96M clk source 1: FDPLL96M 32 kHz 2: DFLLULP reference 4 N 0: TUNE 1: CFD Y — PDSW OSC32KCT RL 0x40001400 0: XOSC32KR DY, CLKFAIL — — 5 Y — 5 N — 2: CFD Y — PDAO SUPC 0x40001800 0: BOD33RDY ,BOD33DE T, B33SRDY, VREGRDY, VCORERD Y, ULPVREFR DY — — 6 Y — 6 N — 3: BOD33DET Y — PDAO GCLK 0x40001C00 — — — 7 Y — 7 N — — N/A — PDSW WDT 0x40002000 1: EW — — 8 Y — 8 N — — N/A — PDSW RTC 0x40002400 2: CMP0-1, TAMPER, OVF, PER0-7 — — 9 Y — 9 N 1: TAMPER 4-11 : PER0-7 12-13 : CMP0-1 14 : TAMPER 15 : OVF 16 : PERD Y 1: TIMESTAM P PDAO EIC 0x40002800 3: EXTINT0 4: EXTINT1 5: EXTINT2 6: EXTINT3 7: EXTINT4-7, NSCHK NMI — — 10 Y 3 10 N — 17-24: EXTINT0-7 Y — PDAO FREQM 0x40002C00 8: DONE — — 11 Y 4: FREQM_M SR 5: FREQM_R EF 11 N — — N/A — PDSW PORT 0x40003000 10: NSCHK — — 12 Y — 12 N 3-6 : EV0-3 — Y — PDAO AC 0x40003400 39: COMP0-1, WIN0 — — 13 Y 17 13 N 16-17: SOC0-1 40-41: COMP0-1 42: WIN0 Y — PDAO SAM L10/L11 Family Peripherals Configuration Summary © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 54 Peripheral name Base address IRQ line AHB clock APB clock Generic Clock PAC Events DMA Power domain Index Enabled at Reset Index Enabled at Reset Index Index Write Protection at Reset User Generator Sleep Walking Index Name AHB-APB Bridge B 0x41000000 — 1 Y — — — — — — — N/A — PDSW DSU 0x41002000 — 4 Y 1 Y — 1 Y — — N/A 2-3: DCC0-1 PDSW NVMCTRL 0x41004000 9: DONE, PROGE, LOCKE, NVME, KEYE, NSCHK 7 Y 2 Y — 2 N 2: AUTOW — Y — PDSW DMAC 0x41006000 11: SUSP0, TERR0, TCMPL0 12: SUSP1, TERR1, TCMPL1 13: SUSP2, TERR2, TCMPL2 14: SUSP3, TERR3, TCMPL3 15: SUSP4-7, TERR4-7, TCMPL4-7 3 Y — — — 3 — 7-10: CH0-3 25-28: CH0-3 Y — PDSW HMATRIXH S 0x41008000 — 5 Y — — — 4 N — — N/A — PDSW AHB-APB Bridge C 0x42000000 — 2 Y — — — — — — — N/A — PDSW EVSYS 0x42000000 16: EVD0, OVR0 17: EVD1, OVR1 18: EVD2, OVR2 19: EVD3, OVR3 20: NSCHK — — 0 Y 6: CH0 7: CH1 8: CH2 9: CH3 0 N — — N/A — PDSW SERCOM0 0x42000400 22: bit 0 23: bit 1 24: bit 2 25: bit 3-6 — — 1 Y 11: CORE 10: SLOW 1 N — — N/A 4: RX 5: TX PDSW SERCOM1 0x42000800 26: bit 0 27: bit 1 28: bit 2 29: bit 3-6 — — 2 Y 12: CORE 10: SLOW 2 N — — N/A 6: RX 7: TX PDSW SERCOM2 0x42000C00 30: bit 0 31: bit 1 32: bit 2 33: bit 3-6 — — 3 Y 13: CORE 10: SLOW 3 N — — N/A 8: RX 9: TX PDSW TC0 0x42001000 34: ERR, MC0, MC1, OVF — — 4 Y 14 4 N 11: EVU 29: OVF 30-31: MC0-1 Y 10: OVF 11-12: MC0-1 PDSW TC1 0x42001400 35: ERR, MC0, MC1, OVF — — 5 Y 14 5 N 12: EVU 32: OVF 33-34: MC0-1 Y 13: OVF 14-15: MC0-1 PDSW TC2 0x42001800 36: ERR, MC0, MC1, OVF — — 6 Y 15 6 N 13: EVU 35: OVF 36-37: MC0-1 Y 16: OVF 17-18: MC0-1 PDSW ADC 0x42001C00 37: OVERRUN, WINMON 38:RESRD Y — — 7 Y 16 7 N 14: START 15 : SYNC 38: RESRDY 39: WINMON Y 19: RESRDY PDSW DAC 0x42002000 40: UNDERRU — — 8 Y 18 8 N 18: START 43: EMPTY Y 20: EMPTY PDSW SAM L10/L11 Family Peripherals Configuration Summary © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 55 Peripheral name Base address IRQ line AHB clock APB clock Generic Clock PAC Events DMA Power domain Index Enabled at Reset Index Enabled at Reset Index Index Write Protection at Reset User Generator Sleep Walking Index Name N 41: EMPTY PTC 0x42002400 42: EOC, WCOMP — — 9 Y 19 9 N 19 : STCONV 20 : DSEQR 44: EOC 45: WCOMP Y 21 : EOC 22 : SEQ 23 : WCOMP PDSW TRNG 0x42002800 43: DATARDY — — 10 Y — 10 N — 46 : READY Y — PDSW CCL 0x42002C00 — — — 11 Y 20 11 N 21 : LUTIN0 22 : LUTIN1 47 : LUTOUT0 48 : LUTOUT1 Y — PDSW OPAMP 0x42003000 — — — 12 Y — 12 N — — N/A — PDSW TRAM 0x42003400 44: DRP, ERR 12 Y — — — 13 — — — N/A — PDSW SAM L10/L11 Family Peripherals Configuration Summary © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 56 13. SAM L11 Security Features This chapter provides an overview of the SAM L11 security features. 13.1 Features Security features can be split in two main categories. The first category relates to the ARM TrustZone for Cortex-M technology features: • Flexible hardware isolation of memories and peripherals: – Up to six regions for the Flash – Up to two regions for the Data Flash – Up to two regions for the SRAM – Individual security attribution (secure or non-secure) for each peripheral using the Peripheral Access Controller (PAC) – Mix-secure peripherals which support both secure and non-secure security attributions • Three debug access levels allowing: – The highest debug level with no restrictions in term of memory and peripheral accesses – A restricted debug level with non-secure memory regions access only – The lowest debug level where no access is authorized except with a debugger using a Boot ROM-specific mode • Different chip erase support according to security settings • Security configuration is fully stored in Flash and safely auto-loaded at startup during Boot ROM execution using CRC checks Important:  Debug access levels, such as Chip Erase support are described in the Boot ROM chapter. The second category relates to the extra security features which are not related to ARM TrustZone for Cortex-M technology support: • Built-in cryptographic accelerator accessible through cryptographic libraries stored in ROM – Supporting AES-128 encryption/decryption, SHA-256 authentication, GCM encryption and authentication – Cryptographic libraries are especially designed for side channel and fault injection attacks prevention • One True Random Generator (TRNG) • Secure Boot, which performs integrity check on a configurable portion of the Flash (BS memory area) • Secure Pin Multiplexing to isolate on dedicated SERCOM I/O pins a secured communication with external devices from the non secure application • Data Flash – Optimized for secrets storage – Data Scrambling with user-defined key (optional) SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 57 – Rapid Tamper erase on scrambling key and on one user-defined row – Silent access for side channel attack resistance • TrustRAM – Address and Data scrambling with user-defined key – Chip-level tamper detection on physical RAM to resist microprobing attacks – Rapid Tamper Erase on scrambling key and RAM data – Silent access for side channel attack resistance – Data remanence prevention • Unique 128-bit serial number 13.2 ARM TrustZone Technology for ARMv8-M ARM TrustZone for Cortex-M technology is an optional core extension, which enables the system and the software to be partitioned into Secure and Non-secure domains. Secure software can access both Secure and Non-secure memories and resources, while Non-Secure software can only access Non-secure memories and resources. Figure 13-1. TrustZone for ARMv8-M Non-Secure states Secure Application/Library Secure OS Non-Secure Application Non-Secure OS Secure states If the TrustZone is implemented (SAM L11 devices), the system starts up in Secure state by default. The security state of the processor can be either Secure or Non-secure. Important:  For more details, please refer to TrustZone Technology for ARMv8-M Architecture, which is available on the ARM web site (www.arm.com). 13.2.1 Memory System and Memory Partitioning The memory space is partitioned into Non-Secure and Secure memory regions: • Non-Secure (NS): Non-Secure addresses are used for memory and peripherals accessible by all software, that is, running on the device. • Secure (S): Secure addresses are used for memory and peripherals accessible only by Secure software or masters. SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 58 • Non-Secure Callable (NSC): NSC is a special type of Secure memory location. It allows software to transition from Non-Secure to Secure state. The Cortex-M23 provides two ways for managing the security configurations of the device. The first solution consists in using the Cortex-M23 SAU (Security Attribution Unit), which is a Memory Protection Unit (MPU) like hardware embedded in the core. The role of the SAU is to manage all the Secure and Non-Secure transactions coming from the core. However, using the SAU implies that the security configuration must be propagated somewhere else in the MCU architecture for security awareness. The second approach, which is the one used for SAM L11 devices, is articulated around a centralized Implementation Defined Attribution Unit (IDAU), which is a hardware unit external to the core. For SAM L11 devices, the IDAU is coupled to the Cortex-M23 and manages all the security configurations related to the core. In addition, the IDAU propagates all the security configurations to the memory controllers. The IDAU, Flash, Data Flash and SRAM embedded memories can be split in sub-regions, which are reserved either for the Secure or for the Non-Secure application. Therefore, the SAU is not required and is absent from SAM L10/L11 devices. The peripherals security attribution is managed by the Peripherals Access Controller (PAC). The PAC and each peripheral can be allocated either to the Secure or to the Non-Secure application, with the exception of the PAC, NVMCTRL, and DSU. Note:  1. The PAC and NVMCTRL peripherals are always secured. 2. The DSU peripheral is always non-secured. Both IDAU and PAC security configurations are stored in NVM fuses, which are read after each reset during Boot ROM execution and are loaded after Boot ROM verifications into their respective registers. The peripherals security attribution (using PAC) is locked before exiting the Boot ROM execution sequence, that is, it is not possible to change a peripheral's configuration (Secure or Non-Secure) during application execution. However, the security attribution of each peripheral, excluding the PAC, NVMCTRL, and DSU, can be modified using the NONSECx NVM fused from the User Row (UROW) during application execution, hence it can be considered after any reset. 13.2.2 Memories Security Attribution The IDAU is used to indicate the processor if a particular memory region is Secure (S), Non-secure Callable (NSC), or Non-secure (NS). It can also mark a memory region to be exempted from security checking. Table 13-1. IDAU Memory Attribution Definition Attribute Description Non-Secure Memory can be accessed in Secure or Non-Secure state. Secure Memory can only be accessed in Secure state. It cannot be called from Non-Secure state. Non-Secure callable Memory can only be accessed in Secure state, but can be called from Non-Secure state. Exempt No attribution check will be done, and the operation will take place on the bus Note:  Refer to " SAM L11 Security Attribution" chapter for the detailed SAM L11 memories and peripherals security attribution description. SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 59 The Cortex-M23 will search each access (fetch or data) in the IDAU, which returns the privilege information about that specific address. If the access is not permitted, the CPU enters a HardFault exception. The IDAU memory region's attributes are partly hardwired and partly set by NVM configuration fuses, and are loaded into the IDAU by the Boot ROM before application execution. The IDAU memory region's attributes are blocked for further writes from the application, but their current state can still be read through dedicated IDAU registers. Note:  Refer to the "SAM L11 IDAU Memory Mapping Registers". 13.2.2.1 Flash The SAM L11 Flash can be split in up to six regions: • The first three regions are called BOOT regions and can be configured to support a first-level bootloader for the application. • The other regions are called APPLICATION regions and relate to the application itself. The total size of the BOOT regions is defined by the BOOTPROT fuses from the NVM Boot Configuration Row (BOCOR), the APPLICATION regions total size being the remaining available size of the Flash. Each of these BOOT / APPLICATION global regions can be split in up to three sub-regions: • The Secure sub-region • The Non-Secure Callable (NSC) sub-region • The Non-Secure (NS) sub-region Each sub-region size can be configured using dedicated fuses from the NVM Boot Configuration Row (BOCOR): • BS fuse corresponds to the size of the Secure + NSC sub-regions of the BOOT region • BNSC fuse corresponds to the NSC sub-region size of the BOOT region • AS fuse corresponds to the size of the Secure + NSC sub-regions of the APPLICATION region • ANSC fuse corresponds to the NSC sub-region size of the APPLICATION region SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 60 Figure 13-2. SAM L11 Flash Memory Mapping BS BOOTPROT BNSC AS ANSC Non-Secure Boot Secure Boot Non-Secure Application Non-Secure Callable Boot Secure Application Non-Secure Callable Application Flash 13.2.2.2 Data Flash The SAM L11 Data Flash can be split in up to two regions: • The Secure Data Flash region, with a size defined by the DS fuse from the NVM Boot Configuration Row (BOCOR) • The Non-Secure (NS) Data Flash region Figure 13-3. SAM L11 Data Flash Memory Mapping DS Secure Non-Secure Data Flash 13.2.2.3 SRAM The SAM L11 SRAM can be split in up to two regions: SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 61 • The Secure SRAM region, with a size defined by the RS fuse from the NVM Boot Configuration Row (BOCOR) • The Non-Secure (NS) SRAM region Figure 13-4. SAM L11 SRAM Memory Mapping RS Secure Non-Secure SRAM 13.2.3 SAM L11 Memory Mapping Configuration Summary The table below summarizes the mapping of the SAM L11 memory regions. Table 13-2. SAM L11 Memory Regions Mapping Memory region Base address Size Flash Boot area 0x00000000 BOOTPROT * 256Bytes Flash Secure Boot 0x00000000 BS*256Bytes - BNSC*32Bytes Flash Non-Secure Callable Boot Contiguous to Flash Secure Boot BNSC * 32Bytes Flash Non-Secure Boot (1) BS * 256Bytes Flash Boot remaining size (BOOTPROT * 256Bytes - BS*256Bytes) Flash Appliation area BOOTPROT * 256Bytes Flash size - BOOTPROT * 256Bytes (Flash Boot area) Flash Secure Application BOOTPROT * 256Bytes AS*256Bytes-ANSC*32Bytes Flash Non-Secure Callable Application Contiguous to Flash Secure APPLICATION ANSC * 32Bytes Flash Non-Secure Application (BOOTPROT+AS) * 256Bytes Flash remaining size (Flash size - BOOTPROT*256Bytes - AS*256Bytes) Secure Data Flash 0x00400000 DS * 256Bytes Non-Secure Data Flash Contiguous to Secure Data Flash 2KB - Secure Data Flash size Secure SRAM 0x20000000 RS * 128Bytes Non-Secure SRAM Contiguous to Secure SRAM SRAM size - Secure SRAM size Note:  1. Flash Secure Boot size cannot be null if a Flash Non-Secure Boot size is defined. Here is a typical configuration for a 64KB of Flash, 2KB of Data Flash and 16KB of SRAM: • Flash boot area: – Total Boot area size = 8KB => BOOTPROT = 8192 / 256 = 0x20 – Flash Secure + Non-Secure Callable Boot size = 1KB => BS = 1024 / 256 = 0x4 – Flash Non-Secure Callable Boot size = 32Bytes => BNSC = 32 / 32 = 0x1 – Flash Non-Secure Boot size = 8KB - 1KB = 7KB • Flash Application area: – Total Application area size = 64 KB - 8KB = 56KB SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 62 – Flash Secure + Non-Secure Callable Application size = 16KB => AS = 16 * 1024 / 256 = 0x40 – Flash Non-Secure Callable Application size = 32Bytes => ANSC = 32 / 32 = 0x1 – Flash Non-Secure Application size = 56KB - 16KB = 40KB • Data Flash area: – Data Flash Secure size = 2KB => DS = 2048 / 256 = 0x8 – Data Flash Non-Secure size = 2 KB - 2 KB = 0KB • SRAM Flash area – SRAM Secure size = 4KB => RS = 4096 / 128 = 0x20 – SRAM Non-Secure size = 16KB - 4KB = 12KB 13.2.4 SAM L11 IDAU Memory Mapping Registers The tables below summarizes the mapping of the SAM L11 IDAU memory regions. Table 13-3. SAM L11 IDAU Memory Register Address Registers Address SECCTRL 0x41000001 SCFGB 0x41000004 SCFGA 0x41000008 SCFGR 0x4100000C Table 13-4. SAM L11 IDAU SECCTRL Register (8-bit) Bit Position Name 7:0 Reserved RXN (Bit 2) Reserved Table 13-5. SAM L11 IDAU SCFGB Register (32-bit) Bit Position Name 7:0 BS 15:8 Reserved BNSC (bit 8-13) 23:16 BOOTPROT 31:24 Reserved Table 13-6. SAM L11 IDAU SCFGA Register (32-bit) Bit Position Name 7:0 AS 15:8 Reserved ANSC (bit 8-13) 23:16 Reserved DS (bit 16-19) 31:24 Reserved Table 13-7. SAM L11IDAU SCFGR Register (8-bit) Bit Position Name 7:0 Reserved RS (bit 0-6) 13.2.5 Peripherals Security Attribution In addition to generic protection features, the Peripheral Access Controller (PAC) configures the security privileges for each individual peripheral in the system. SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 63 Each peripheral can only be configured either in Secure or in Non-Secure mode. The PAC NONSECx registers (Read Only) contain one bit per peripheral for that purpose, which is the image of the NONSECx fuses from the NVM User row (UROW). During Boot ROM execution, the NONSECx fuses from the NVM User row are copied in the PAC peripheral NONSECx registers so that they can be read by the application. All peripherals are marked as "exempt" in the memory map, meaning that all bus transactions are propagated. As a consequence, any illegal accesses are reported back to the PAC and trigger an interrupt if enabled. The security configuration (Secure or Non-Secure) is propagated to each individual peripheral, thus it is the responsibility of the peripheral to grant or not the access with the following rules: • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0), a PAC error is triggered Important:  These rules do not apply to the specific peripherals called Mix-Secure peripherals. Note:  The Secure application will usually provide an API for the Non-Secure application using the NonSecure Callable region (NSC) to allow the Non-Secure application to request specific resources. Table 13-8. Peripheral PAC Security Attribution (Excluding Mix-Secure Peripherals) Mode Secure Master Access Non-Secure Master Access Non-Secure Read / Write Read / Write Secure Read / Write Discarded (Write ignored / Read 0x0) PAC Error is generated 13.2.5.1 SAM L11 Peripherals Configuration Example Below is a typical configuration examples where all peripherals except the ADC, TC0, and Event System (EVSYS) are reserved to the Secure application: • Secure/Non-Secure Peripherals PAC configuration: – PAC.NONSECA=PAC.NONSECB=0x0000_0000 – PAC.NONSECC=0x0000_00091 (ADC, TC0 and EVSYS available for the Non-Secure application) 13.2.6 SAM L11 Memory Space Security Attribution This table provides the security attributions of the SAM L11 memory space: SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 64 Table 13-9. SAM L11 Memory Space Security Attributions Memory region Attribute Flash Secure Boot Secure Flash Non-Secure Callable Boot Non-secure callable Flash Non-Secure Boot Non-secure Flash Secure Application Secure Flash Non-Secure Callable Application Non-secure callable Flash Non-Secure Application Non-secure Secure Data Flash Secure Non-Secure Data Flash Non-secure NVM User Rows Secure (R/W access) Non-Secure (Discarded for BOCOR, Read-only for the others) Boot ROM Secure Execute-only for CRYA functions Hardfault generated if not Secure SRAM Secure Non-Secure SRAM Non-secure Peripherals Exempt IOBUS Exempt Others (Reserved, Undefined...) Secure 13.2.7 Cortex-M23 Test Target Instructions Software may check the privilege state of a memory location by using the Cortex-M23 Test Target instructions: TT, TTT, TTA, and TTAT. The memory location is referenced using the Cortex-M23 IREGION bitfield, which specifies the IDAU region number (see the ARMv8-M Architecture Reference Manual for more information). Table 13-10. SAM L11 IDAU Region Number for TT, TTT, TTA and TTAT Cortex-M23 Instructions Memory Region IDAU Region Number for TTx Instructions (IREGION bits) Flash Secure BOOT 0x01 Flash Non-Secure Callable BOOT 0x02 Flash Non-Secure BOOT 0x03 Flash Secure APPLICATION 0x04 Flash Non-Secure Callable APPLICATION 0x05 Flash Non-Secure APPLICATION 0x06 Secure Data Flash 0x07 Non-Secure Data Flash 0x08 NVM User Rows 0x00 (invalid) Boot ROM 0x09 Secure SRAM 0x0A Non-Secure SRAM 0x0B Peripherals 0x00 (invalid) SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 65 Memory Region IDAU Region Number for TTx Instructions (IREGION bits) IOBUS 0x00 (invalid) Others (Reserved, Undefined...) 0x00 (invalid) 13.2.8 Mix-Secure Peripherals There are five Mix-Secure peripherals that allow internal resources to be shared between the Secure and Non-Secure applications: • The PAC controller which manages peripherals security attribution (Secure or Non-Secure). • The Flash memory controller (NVMCTRL) which supports Secure and Non-Secure Flash regions programming. • The I/O controller (PORT) which allows to individually allocate each I/O to the Secure or NonSecure applications. • The External Interrupt Controller (EIC) which allows to individually assign each external interrupt to the Secure or Non-Secure applications. • The Event System (EVSYS) allows to individually assign each event channel to the Secure or NonSecure applications. When a Mix-Secure peripheral is configured as Secure in the PAC, its register map is automatically duplicated in a Secure and Non-Secure alias: • The Non-Secure alias is at the peripheral base address. • The Secure alias is located at the peripheral base address: – + 0x200 offset for the PAC, EIC, PORT and EVSYS peripherals Non-Secure Alias Secure Alias Registers Table Mix-Secure Peripheral (Not PAC Secured) Base Address Base Address Base Address + 0x200 Mix-Secure Peripheral (PAC Secured) PAC, PORT, EIC and EVSYS Cases – + 0x1000 offset for the NVMCTRL peripheral. SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 66 Non-Secure Alias Secure Alias Registers Table Mix-Secure Peripheral (PAC Secured) Mix-Secure Peripheral (Not PAC Secured) Base Address Base Address Base Address + 0x1000 NVMCTRL Case The Secure alias has the following characteristics: • All of the peripheral registers are available for the Secure application through the Secure alias • When an internal resource becomes available to the Non-Secure application, the corresponding registers (called Mix-Secure registers) or bitfields in registers are still accessible through this Secure alias by the Secure application • Non-Secure accesses to this Secure alias are discarded (Write is ignored, Read is 0x0) and a PAC error is triggered The Non-Secure alias has the following characteristics: • Only a restricted set of registers are available for the Non-Secure application through the NonSecure alias • It is the responsibility of the Secure application to assign some resources to the Non-Secure application. This is done by setting the corresponding bits in the NONSECx registers of the MixSecure peripheral. – When an internal resource becomes available for the Non-Secure application, the corresponding registers (called Mix-Secure and Write-Mix-Secure registers) or bitfields in the registers are accessible through the Non-Secure alias by the Non-Secure application – Non-Secure accesses to Secure resources (registers, bitfields) are silently discarded (Write is ignored, Read is 0x0) and no error is generated • Secure accesses to the Non-Secure alias are silently discarded (Write is ignored, Read is 0x0) and no error is generated SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 67 Registers Table Non-Secure OS Base Address Base Address + 0x200 or 0x1000 Non-Secure Alias Base Address Base Address + 0x200 or 0x1000 Secure Alias Secure Alias Non-Secure registers Non-Secure registers Secure registers Write-Secure registers Mix-Secure registers Write-Mix-Secure registers Non-Secure registers Secure registers Write-Secure registers Mix-Secure registers Write-Mix-Secure registers Non-Secure registers Mix-Secure registers Write-Mix-Secure registers + Some registers/bitfields assigned to Non-Secure Accesses No registers/bitfields assigned to Non-Secure Accesses Mix-Secure Peripheral Write-Secure registers + Non-Secure Alias + Write-Secure registers Mix-Secure peripherals have always the following registers: • NONSEC register is a generic register that tells the Non-Secure application which resources inside a Mix-Secure peripheral can be used • NSCHK register is a register allowing the Non-Secure application to be notified when the security configuration of a Mix-Secure peripheral is being modified during application execution Important:  It is recommended that the Non-Secure application first copy the content of NONSEC register inside NSCHK register, and then enable the NSCHK interrupt flags. Once done, any changes to the NONSEC register by the Secure application will trigger an interrupt so that Non-Secure application can take appropriate actions. This mechanism allows the Secure application to dynamically change the security attribution of a Mix-Secure peripheral and avoid illegal accesses from the Non-Secure application. The interrupt handler should always copy the NONSEC register to NSCHK register before exiting it. Mix-Secure peripherals can have five type of registers: • Non-Secure: these registers will always be available in both the Secure and Non-Secure aliases • Secure: these registers will never be available in the Non-Secure alias and always available in the Secure alias • Write-Secure: these are registers than can: – Be written or read by the Secure application only in the Secure alias – Only read by the Non-Secure application in Non-Secure alias. Write is forbidden. • Mix-Secure registers : these ones are used when a resource can be allocated to either the Secure and Non-Secure alias – Note that, in some cases, the Mix-Secure properties apply to a bitfield only (like one I/O bit in the PORT peripheral register) • Write-Mix-Secure registers (NVMCTRL peripheral only): these are Mix-Secure registers, which: – can be written or read by the Secure application only in the Secure alias – can only be read by the Non-Secure application in Non-Secure alias except if Non-Secure writes are authorized in NVMCTRL.NONSEC register SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 68 Table 13-11. SAM L11 Mix-Secure Peripheral Registers Access Mix-Secure Peripheral Register Secure Master Access Non-Secure Master Access Secure Alias Non-Secure Alias Secure Alias Non-Secure Alias Non-Secure Read / Write Discarded (Write ignored / Read 0x0) No Error is generated Discarded (Write ignored / Read 0x0) PAC Error is generated Read / Write Secure Discarded (Write ignored / Read 0x0) No Error is generated Write-Secure Read-only (Write ignored) No Error is generated Mix-Secure Read/Write if the resource is available for the NonSecure Application Discarded if not (Write ignored / Read 0x0) and no error is generated Write-Mix-Secure Read /Write if the resource is available for the NonSecure Application Read-only if not (Write ignored) and no error is generated 13.3 Crypto Acceleration 13.3.1 Overview The SAM L11 product embeds a hardware/software cryptographic accelerator (CRYA) which supports Advanced Encryption Standard (AES) encryption and decryption, Secure Hash Algorithm 2 (SHA-256) authentication, and Galois Counter Mode (GCM) encryption and authentication through a set of APIs, which are only accessible once the Boot ROM has completed. Note:  The CRYA cryptographic accelerator is mapped as a slave on the IOBUS port and is driven by the CPU using assembly code (located in ROM). The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES operates on a 128-bit block of input data. The key size used for an AES cipher specifies the number of repetitions of transformation rounds that convert the input plaintext, into the final output, called the ciphertext. The AES works on a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. The SHA-256 is a cryptographic hash function that creates a 256-bit hash of a data block. The data block is processed in chunks of 512 bits. The GCM is a mode of operation for AES that combines the CTR (Counter) mode of operation with an authentication hash function. For detail algorithm specification, refer to following standards and specification: • AES: FIPS Publication 197, Advanced Encryption Standard (AES) • SHA: FIPS Pub 180-4, The Secure Hash Standard • GCM: NIST Special Publication 800-38D Recommendation 13.3.2 Features • Advanced Encryption Standard (AES), compliant with FIPS Publication 197 – Encryption with 128-bit cryptographic key – Decryption with 128-bit cryptographic key SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 69 – Countermeasures against side-channel attacks for AES • Secure Hash Algorithm 2 (SHA-256), compliant with FIPS Pub 180-4 – Accelerates message schedule and inner compression loop • Galois Counter Mode (GCM) encryption using AES engine and authentication – Accelerates the GF(2128) multiplication for AES-GCM hash function 13.3.3 CRYA APIs The CRYA APIs which are located in a dedicated Boot ROM area are only accessible from the user application after the Boot ROM has completed. This area is an execute-only area, meaning the CPU cannot do any loads, but can call the APIs. The Boot ROM memory space is a secure area, only the secure application can directly call these APIs. Table 13-12. CRYA APIs Addresses CRYA API Address AES Encryption 0x02001904 AES Decryption 0x02001908 SHA Process 0x02001900 GCM Process 0x0200190C 13.3.3.1 AES API The AES software has two function routines to do encryption and decryption on a 128 bit block of input data. The AES encryption function entry point is located at the Boot ROM address 0x02001904 and the encryption function parameters are: • Src[in] : a pointer to a 128-bit data block to be encrypted • Dst[out]: a pointer to 128 bit encrypted data • Keys[in]: a pointer to 128 bit key • Length[in]: Number of 32-bit words comprising the Key, 4 for 128 bits key The AES decryption function entry point is located at the Boot ROM address 0x02001908 and the decryption function parameters are: • Src[in] : a pointer to a 128-bit data block to be decrypted • Dst[out]: a pointer to 128 bit decrypted data • Keys[in]: a pointer to 128 bit key • Length[in]: Number of 32-bit words comprising the Key, 4 for 128 bits key The APIs are: /* Type definition for CRYA AES functions. */ typedef void (*crya_aes_encrypt_t) (const uint8_t *keys, uint32_t key_len, const uint8_t *src, uint8_t *dst); typedef void (*crya_aes_decrypt_t) (const uint8_t *keys, uint32_t key_len, const uint8_t *src, uint8_t *dst); /* AES encrypt function * \param keys[in]: A pointer to 128-bit key * \param key_len[in]: Number of 32-bit words comprising the key, 4 for 128-bit key * \param src[in]: A pointer to a 128-bit data block to be encrypted SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 70 * \param dst[out]: A pointer to a 128-bit encrypted data */ #define secure_crya_aes_encrypt ((crya_aes_encrypt_t ) (0x02001904 | 0x1)) /* AES decrypt function * \param keys[in]: A pointer to 128-bit key * \param key_len[in]: Number of 32-bit words comprising the key, 4 for 128-bit key * \param src[in]: A pointer to a 128-bit data block to be decrypted * \param dst[out]: A pointer to a 128-bit decrypted data */ #define secure_crya_aes_decrypt ((crya_aes_decrypt_t ) (0x02001908 | 0x1)) 13.3.3.2 SHA API The SHA software function can update the hash value based on the 512-bit data. It is assumed that the message is already preprocessed properly for the SHA algorithm, so that the SHA software can work directly on 512-bit portions. The SHA function entry point is located at the Boot ROM address 0x02001900 and has three parameters: • [In/out]: A pointer to a hash location (hash input and output) • [In]: A pointer to a 512-bit data block • [In]: A pointer to a RAM buffer (256B needed for internal algorithm) The updated hash value is put at first parameter after the function exit. The API is: /* Type definition for CRYA SHA function. */ typedef void (*crya_sha_process_t) (uint32_t hash_in_out[8], const uint8_t data[64], uint32_t ram_buf[64]); /* CRYA SHA function * \param hash_in_out[In/out]: A pointer to a hash location (hash input and output) * \param data[In]: A pointer to a 512 bit data block * \param ram_buf[In]: A pointer to a RAM buffer (256B needed for internal algorithm) */ #define crya_sha_process ((crya_sha_process_t ) (0x02001900 | 0x1)) Code example of using CRYA SHA software: void sha256_process(uint32_t hash[8], const uint8_t data[64]) { uint32_t ram_buf[64]; /* 256 bytes needed for message schedule table */ /* Pointer to CRYA SHA function in ROM */ static void (*crya_sha_process)(uint32_t hash_in_out[8], const uint8_t data[64], uint32_t ram_buf[64]); crya_sha_process = (void (*)(uint32_t *, const uint8_t *, uint32_t *)) *((uint32_t*)0x02001900); crya_sha_process (hash, data, ram_buf); } 13.3.3.3 GCM API The GCM function entry point is is located at the Boot ROM address 0x0200190C and the function parameters are: • Block1[in]: a pointer to 128-bit data blocks that are to be multiplied • Block2[in]: a pointer to 128-bit data blocks that are to be multiplied • dst[out]: a pointer to a location for storing the result SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 71 The API is: /* Type definition for GF(2^128) multiplication */ typedef void (*crya_gf_mult128_t) (const uint32_t *block1, const uint32_t *block2, uint32_t *dst); /* GF(2^128) multiplication. * * \param block1[In]: A pointer to 128-bit data blocks that are to be multiplied * \param block2[In]: A pointer to 128-bit data blocks that are to be multiplied * \param dst[out]: A pointer to a location for storing the result */ #define secure_crya_gf_mult128 ((crya_gf_mult128_t ) (0x0200190C | 0x1)) 13.4 True Random Number Generator (TRNG) Refer to TRNG - True Random Number Generator for more information. 13.5 Secure Boot A Secure Boot with SHA-based authentication on a configurable portion on the Flash (BS memory area) is available with verification mechanisms allowing to reset and restart the authentication process in case of a failure. Refer to 14. Boot ROM for more information. 13.6 Secure Pin Multiplexing on SERCOM The Secure Pin Multiplexing feature can be used on dedicated SERCOM I/O pins to isolate a secured communication with external devices from the non-secure application. To benefit from this feature, the security attribution of the SERCOM must be set as secured using the PAC peripheral. When this operation occurs: • The secured SERCOM instances becomes mapped only on a specific set of I/Os • All of the alternate I/O pins of the secured SERCOM instance are kept in a Hi-Z configuration • The PTC cannot enable PTC lines mapped to any of the secured SERCOM instance I/O pins • The CCL I/Os mapped to the secured SERCOM instance I/O pins are set to '0' Refer to 4.4.2 Secure Pin Multiplexing (on SERCOM) Pins to obtain the list of pins supporting that feature. 13.7 Data Flash Refer to 30. NVMCTRL – Nonvolatile Memory Controller to get all security features related to the Data Flash. 13.8 TrustRAM (TRAM) Refer to TRAM - TrustRAM to get all security features related to the TrustRAM. SAM L10/L11 Family SAM L11 Security Features © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 72 14. Boot ROM The Boot ROM allows to ensure the integrity of the device at boot. The Boot ROM features Boot Interactive mode, which allows the user to perform several actions on the device, such as NVM areas integrity check and chip erase via a debugger connection. Unless a debugger is connected and places the Boot ROM in Boot Interactive mode, the CPU will jump to the Flash memory, loading the Program Counter (PC) and Stack Pointer (SP) values, and will start fetching Flash user code. Note:  Before jumping to the Flash, the Boot ROM resets the two first 2kB of SRAM. The Clocks remain unchanged. In addition, the SAM L11 Boot ROM has extra security features, such as device integrity checks, memories/peripherals security attributions, and secure boot, which can be executed before jumping to the Flash in Secure state. For security reasons, while the Boot ROM is executing, no debug is possible except when entering a specific Boot ROM mode called CPU Park mode. Related Links 13.1 Features 14.1 Features • Command interface for the host debugger supporting: – Chip erase commands to provide secure transitions between the different Debug Access Levels (DAL) – Device integrity check of the NVM memory regions – Debugger read access of the NVM rows • CPU Park mode to get access for a debugger to the resources of the device depending on Debug Access Level (DAL) • SAM L11 Added features: – Device integrity checks – Memory and peripheral security attributions from user configuration stored in NVM rows – Secure Boot on Flash BS Memory Area Related Links 13.1 Features SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 73 14.2 Block Diagram Figure 14-1. Boot ROM Block Diagram Boot ROM DSU Device Service Unit Host Debugger SWD Serial Wire Debug BCC Boot Communication Channels NVMCTRL IDAU (SAM L11) CRYA PAC TRNG Related Links 13.1 Features 14.3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. Related Links 13.1 Features 14.3.1 Clocks The device selects the OSC16M oscillator which is enabled by default after reset and configured at 4 MHz. 14.3.2 NVM User (UROW) and Boot Configuration (BOCOR) rows The Boot ROM reads the different NVM rows during its execution. The relevant fuses must be set appropriately by any configuration tools supported the device in order to operate correctly. Refer to the 10.2 NVM Rows section for additional information. 14.3.3 Debug Operations For security reasons, no debug is possible during the Boot ROM execution except when entering the Boot ROM CPU Park mode. 14.4 Functional Description Related Links 13.1 Features 14.4.1 SAM L10 Boot ROM Flow The SAM L10 Boot ROM checks firstly if a debugger is present to enter the Boot Interactive mode which allows the user to perform specific tasks via a debugger connection. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 74 Before jumping to the application, the Boot ROM can also enter in a specific mode called CPU Park to allow the debugger to get access to the resources of the device depending on Debug Access Level (DAL). Note:  Boot Interactive and CPU Park modes are described later on. Figure 14-2. SAM L10 Boot ROM Flow Wait for Debugger Command Start Application CPU Park Mode System RESET Is Debugger Connected ? Interactive Boot Mode RESET Is Debugger Connected AND BREXT ==1 ? BREXT == 1 BREXT == 0 Yes "Init" Command If no debugger is connected: automatic exit from Boot interactive mode No "Exit" command No Yes 14.4.1.1 Typical Boot Timings The delay is given from the release of the CPU reset to the execution of the first instruction of the user code: Table 14-1. SAM L10 Typical Boot Timing Time to reach User Code 1.33 ms 14.4.2 SAM L11 Boot ROM Flow The SAM L11 Boot ROM sequence consists in performing several security tasks (integrity checks, memories and peripherals security attribution, secure boot...) before starting the application. The Boot ROM checks firstly if a debugger is present to enter the Boot Interactive mode which allows the user to perform specific tasks via a debugger connection. Before jumping to the application in Secure state, the Boot ROM can also enter in a specific mode called CPU Park to allow the debugger to get access to the resources of the device depending on Debug Access Level (DAL). Note:  Boot Interactive and CPU Park modes are described later on. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 75 Figure 14-3. SAM L11 Boot ROM Flow Device Integrity Checks Wait for Debugger Command Apply Memories & Peripherals Security Settings Start Application IS Debugger Connected AND BREXT == 1? CPU Park Mode System RESET Is Debugger Connected ? Boot Interactive Mode BS and BOCOR Verifications Bootloader Authentication BOOTOPT>0 ? RESET No BREXT == 1 Yes BREXT == 0 Yes OK "Init" Command Not OK OK No "Exit" Command No Yes If no debugger is connected: automatic exit from Boot interactive mode OK 14.4.2.1 Device Integrity Checks For SAM L11 devices, the Boot ROM performs security checks on two CRCs: • The User Row CRC (USERCRC) which is located in the NVM User Row (UROW) at: [0x80401C: 0x80401F]: UROW Offset Bit Position Name 0x1C-0x1F 255:224 USERCRC • The Boot Configuration Row CRC (BOCORCRC) which is located in the NVM Boot Configuration Row (BOCOR) at: [0x80C008:0x80C00B]: BCOR Offset Bit Position Name 0x08-0x0B 95:64 BOCORCRC 14.4.2.1.1 User Row CRC (USER CRC) USERCRC allows to check the following fuses parameters integrity: • AS, ANSC, DS, RS SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 76 • URWEN • NONSECA, NONSECB, NONSECC USERCRC is the CRC of the NVM User row area which starts from 0x00804008 and finish at 0x0080401B (bit 64 to bit 223): Table 14-2. SAM L11 UROW Area Computed in USERCRC Offset Bit Pos. Name 0x08 71:64 AS 0x09 79:72 Reserved ANSC 0x0A 87:80 Reserved DS 0x0B 95:88 Reserved RS 0x0C 103:96 Reserved URWEN 0x0D-0xF 127:104 Reserved 0x10-0x13 159:128 NONSECA 0x14-0x17 191:160 NONSECB 0x18-0x1B 223:192 NONSECC 14.4.2.1.2 Boot Configuration Row CRC (BOCORCRC) BOCORCRC allows to check the following fuses parameters integrity: • BS, BNSC • BOOTOPT • BOOTPROT, BCWEN, BCREN BOCORCRC is the CRC of the NVM Boot Configuration row area, which starts from 0x0080C000 and finish at 0x00800C007 (bit 0 to bit 63). Table 14-3. SAM L11 BOCOR Area Computed in BOCORCRC Offset Bit Pos. Name 0x00 7:0 Reserved 0x01 15:8 BS 0x02 23:16 Reserved BNSC 0x03 31:24 BOOTOPT 0x04 39:32 BOOTPROT 0x05 47:40 Reserved 0x06 55:48 Reserved BCREN BCWEN 0x07 63:56 Reserved If one of the checks fails, the Boot ROM will report the error to the DSU peripheral and will enter the Boot Interactive mode: • This will allow, if a debugger is connected, to put the device in the highest debug access level mode (DAL = 2) by issuing a Chip Erase command . Once in that mode, it is possible for a programming tool to reprogram the NVM Rows. • When the check fails and no debugger is connected, the part will reset and restart the check sequence again. Note:  Boot Interactive mode is described later in this chapter. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 77 14.4.2.1.3 CRC Computation and Programming The CRCs needs to be recalculated and updated in their respective NVM row as soon as a data from any of the checked regions is changed. Important:  USERCRC and BOCORCRC CRCs programming must be done by any programming tool supporting the SAM L11 devices. The algorithm is a CRC-32 module embedded in the DSU peripheral and that uses for both CRC calculation with the following parameters: • Width = 32 bits • Polynomial = 0x04C11DB7 (Poly) • Initial Value = 0xFFFFFFFF (Init) • Input Data is reflected (RefIn) • Output Data is reflected (RefOut) • No XOR is performed on the output CRC (XorOut) Example: the DSU CRC of 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39 is 0x340BC6D9 14.4.2.2 Memories and Peripherals Configurations Initialization For SAM L11 devices, memories and peripherals security attributions are done by reading the different fuses values from the NVM User (UROW) and Boot Configuration (BOCOR) rows. The Boot ROM is responsible for setting these attributions on the different concerned memory and peripheral controllers: • Set memory security attribution according to AS, ANSC, DS, RS, BS, BSNC and BOOTPROT fuses • Set peripherals security attribution according to NONSECA, NONSECB and NONSECC fuses Important:  The Boot ROM does not perform any consistency checks on the configured memory attributions (e.g setting BS>BOOTPROT will not trigger any errors during Boot ROM execution). 14.4.2.3 Secure Boot Depending on the BOOTOPT fuse value (from BOCOR NVM row), the following secure boot integrity checks will be performed on: • The Flash BS memory area which is composed by: – The Flash Secure BOOT memory region – The Flash Non-Secure Callable BOOT memory region • And the NVM Boot Configuration row (BOCOR) Table 14-4. Secure Boot Options BOOTOPT Verified Areas Verification Method 0 None - 1 Flash BS Memory Region + NVM BOCOR row SHA-256 SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 78 BOOTOPT Verified Areas Verification Method 2 or 3 Flash BS Memory Region + NVM BOCOR row SHA-256 with BOOTKEY (defined in BOCOR) Other Values None - If the verification fails, the Boot ROM will report the error to the DSU peripheral and will enter the Boot Interactive mode. This will allow, if a debugger is connected, to put the device in the highest debug level access mode (DAL = 2) by issuing a Chip Erase command. Once in that mode, it is possible for a programming tool to reprogram the different memory regions and/or NVM rows. When verification fails and no debugger is connected, the part will reset and restart the integrity checks sequences again. 14.4.2.3.1 Hash algorithm (SHA-256) Verification Method The verifications are done using the standard SHA256 hash algorithm. Both Flash BS region and NVM BOCOR row hashes are computed on the defined memory/row area and compared to their expected reference hash value. Note:  The hash consists of 256 bits, i.e. 32 bytes. SHA256 with BOOTKEY Variant To prevent unauthorized change of the bootloader code, the hash computation can be slightly modified to require a key to produce a valid hash. When SHA with BOOTKEY is selected (BOOTOPT=2 or =3), the hash computation (for both Flash BS region and NVM BOCOR row) starts by processing the secure boot key (BOOTKEY) data twice, then proceeds with the rest of data. This secure boot key (BOOTKEY) is located in the NVM Boot Configuration row (BOCOR) at [0x80C0050:0x80C006F]: BOCOR Offset Bit Position Name 0x50-0x6F 895:640 BOOTKEY 14.4.2.3.2 BS Verification When BOOTOPT>0, the bootloader authentication starts allowing a secure bootloader code to be protected against inadvertent or malicious changes. The hash is computed on the Flash Secure BOOT and Flash Non-Secure Callable BOOT (BNSC) regions. The hash reference value for this area is stored at the end of the Secure BOOT area, just before the NonSecure Callable BOOT (BNSC) one. Note:  The last 256 bits where the hash is stored are not included in the hash computation. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 79 Figure 14-4. BS Hash location in BS memory area Flash Secure BOOT 0x00000000 Flash Non-Secure Callable BOOT BS Reference Hash : 256bits (32 bytes) BNSC BS * Granularity BS Important:  The Non-Secure BOOT region as well as Secure or Non-Secure APPLICATION regions are not part of the Secure Boot verification. So if an authentication of one of these memory regions is required, it must be handled by the user code itself. 14.4.2.3.3 BOCOR Verification When BOOTOPT>0, the hash for the NVM BOCOR row is computed on the whole NVM BOCOR row excluding BOCORHASH fuse value which is the fuse where to store the hash reference value [0x80C00E0:0x80C00FF]: BOCOR Offset Bit Position Name 0xE0-0xFF 2047:1792 BOCORHASH 14.4.2.4 Typical Boot Timings Depending on the boot authentication options, the Boot ROM will require a certain time to complete its different tasks. The delay is given from the release of the CPU reset to the execution of the first instruction of the user code. Table 14-5. SAM L11 Typical Boot Timings Boot options Time to reach User Code BOOTOPT=0 2.30 ms BOOTOPT=1, BS=0x40 207 ms BOOTOPT=1, BS=0x80 409 ms BOOTOPT=2, BS=0x40 209 ms BOOTOPT=2, BS=0x80 411 ms 14.4.3 Debug Access Levels The SAM L10 has only two debug access levels (DAL): • DAL2: Highest debug level access with no restrictions in term of memory and peripheral accesses. • DAL0: No access is authorized except with a debugger using the Boot ROM Interactive mode. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 80 The possible transitions between each debug access level are described below: Figure 14-5. SAM L10 Debug Access Levels Transitions DAL0 1) Program NVM regions 2) Send SDAL0 command (NVMCTRL) Delivered parts DAL2 ChipErase No key required After Reset The SAM L11 has three possible debug access levels (DAL): • DAL2: Highest debug level access with no restrictions in term of memory and peripheral accesses. • DAL1: Access is limited to the Non-Secure memory regions. Secure memory regions accesses are forbidden. • DAL0: No access is authorized except with a debugger using the Boot ROM Interactive mode. The possible transitions between each debug access level are described below: Figure 14-6. SAM L11 Debug Access Levels Transitions DAL0 1) Program NVM regions 2) Send SDAL0 command (NVMCTRL) DAL2 DAL1 Delivered parts 1) Program NVM regions 2) Send SDAL1 command (NVMCTRL) ChipErase_ALL with CEKEY2 key ChipErase_NS with CEKEY0 key ChipErase_S with CEKEY1 key After Reset After Reset Decreasing the Debug Level Access is done using the NVMCTRL peripheral command from the debugger or the CPU. Note:  Refer to 30. NVMCTRL – Nonvolatile Memory Controller for more information. For security reasons, increasing the Debug Level Access is only possible during Boot ROM execution and will be always preceded by a specific chip erase depending on the Debug Access Level. 14.4.4 Chip Erase The chip erase commands allow to erase memories of the device and provide secure transitions between the different Debug Access Levels. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 81 Important:  Chip Erase commands are only issued using the Boot ROM Interactive mode (CMD_CE0, CMD_CE1, CMD_CE2 and CMD_CHIPERASE commands). For SAM L10, the chip erase command does not require a key. For SAM L11, the chip erase commands are protected with keys (CEKEYx) defined in the NVM BOCOR row. Note:  The chip erase keys can only be read if BOCOR.BCREN=1. By default, the devices are delivered with these keys set at “All 1s”. Important:  If the key is set at “All 0s”, the corresponding chip erase command is disabled and it will be impossible for the debugger to use it. The following table gives the effect of the Chip Erase commands on the different memories: Table 14-6. Chip Erase Commands Effects SAM L11 SAM L10 Boot ROM Command ChipErase_NS (CE0) ChipErase_S (CE1) ChipErase_ALL (CE2) ChipErase (CHIPERASE) Key Requirement Yes (CEKEY0) Yes (CEKEY1) Yes (CEKEY2) No Flash BOOT area BOOTPROT (BS+BNSC+BNS) No No Yes No Flash Secure APPLICATION (AS) No Yes Yes Yes Flash Non-secure APPLICATION Yes Yes Yes - Secure Data Flash (DS) No Yes Yes Yes Non-Secure Data Flash Yes Yes Yes - NVM User Row (UROW) No No Yes No NVM Boot Configuration Row (BOCOR) No No Yes No Volatile Memories Yes Yes Yes Yes Debugger Access Level after reset 2 (if DAL was 2) else 1 2 (if DAL was 2 or BS==0) else 1 2 2 Note:  Only the ChipErase_ALL (CE2) command affects rows belonging to the BOOT area (BOOTPROT fuse bits) 14.4.5 Boot ROM Interactive Mode The interactive mode allows the user to perform several actions on the device during the Boot ROM execution via a debugger connection. The debugger communicates with the device using the DSU Boot Communication Channels (BCC). This communication is bi-directional and allows the debugger to post commands and receive status from the Boot ROM. Note:  Refer to Device Service Unit for more information on BCC. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 82 14.4.5.1 Enter Interactive Mode (CMD_INIT) This command allows launching the Boot Interactive command mode of the Boot ROM. To reach interactive mode, the debugger will trigger a “cold plugging” sequence as described in DSU chapter. Important:  Debugger must not clear DSU.STATUSA.BREXT bit before clearing DSU.STATUSA.CRSTEXT bit. When CRSTEXT is cleared, CPU starts Boot ROM Interactive mode execution. After a small delay (5ms advised), the debugger must check if the Boot ROM has not flagged any errors by checking the BCC1D bit in DSU.STATUSB register. If no error is reported, the debugger writes the CMD_INIT command to DSU.BCC0 register to request Boot ROM Interactive mode entry. When command is successful, Boot ROM will place the “SIG_COMM” status in DSU.BCC1 register. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 83 14.4.5.1.1 CMD_INIT Figure 14-7. CMD_INIT Flow diagram Boot ROM in interactive mode Debugger idle CPU in reset Debugger triggers interactive mode entry CPU executes Boot ROM BCC1 Dev to Dbg BCC0 Dbg to Dev Boot Communication Channels Error code Sanity checks Wait for command CMD_INIT Signal command mode entry SIG_COMM Boot ROM Debugger Cold Plugging Sequence Check if error flagged after (DSU CPU (DSU CPU reset extension) 5 ms from CPU release Check status after command Debugger clears CRSTEXT If error Get command code 14.4.5.2 Exit Interactive Mode (CMD_EXIT) This command allows exiting the Boot Interactive mode. Exiting the Boot Interactive mode allows to jump to one of the following: • The Application • The CPU Park Mode SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 84 14.4.5.2.1 CMD_EXIT Figure 14-8. CMD_EXIT to APP flow diagram CPU executes application Debugger idle CPU in reset Debugger triggers exit to app CPU executes Boot ROM BCC1 Device to Dbg BCC0 Dbg to Device Boot Communication Channels Error code Sanity checks Wait for command CMD_EXIT Signal command mode entry SIG_BOOTOK Boot ROM Debugger Cold Plugging Sequence Check if error flagged after 5 ms from CPU release (DSU CPU reset extension) Check status after command Debugger clears CRSTEXT If error Debugger clears BREXT Get command code SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 85 Figure 14-9. CMD_EXIT to Park mode flow diagram CPU parked in a while loop waits for BREXT cleared Debugger idle CPU in reset Debugger triggers interactive mode entry CPU executes Boot ROM BCC1 Device to Dbg BCC0 Dbg to Device Boot Communication Channels Error code Sanity checks Wait for command CMD_EXIT Signal command mode entry SIG_BOOTOK Boot ROM Debugger NOTE : debugger does not clear BREXT before CRSTEXT Cold Plugging Sequence Check if error flagged after 5 ms from CPU release (DSU CPU reset extension Check status after command Debugger clears CRSTEXT If error Get command code 14.4.5.3 System Reset Request (CMD_RESET) This command allows resetting the system using a system reset request. Since the reset is executed immediately after receiving the command, no reply is sent to the debugger. After reset, the CPU executes the Boot ROM code from the beginning 14.4.5.4 Chip Erase (CMD_CHIPERASE) - SAM L10 only CMD_CHIPERASE command erases the entire device except BOOT area, and reverts to Debug Access Level 2. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 86 14.4.5.4.1 CMD_CHIPERASE (SAM L10 only) Figure 14-10. CMD_CHIPERASE Flow diagram Debugger idle Debugger requests Chip Erase BCC1 Dev to Dbg BCC0 Dbg to Dev Boot Communication Channels Wait for command CMD_CHIPERASE Boot ROM Debugger Boot ROM in interactive mode SAM L10 ? Boot ROM in interactive mode SIG_CMD_VALID Erase targeted memories SIG_CMD_SUCCESS On error, one of SIG_CE_x is reported Debugger polls for status update on BCC1 Get data Get command code 14.4.5.5 Chip Erase (CMD_CEx) - SAM L11 only CMD_CEx commands are used to erase specific part of the device and to increase the Debug Access Level. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 87 14.4.5.5.1 CMD_CEx (SAM L11 only) Figure 14-11. CMD_CEx Flow diagram Debugger idle Debugger requests Chip Erase 0 / 1 / 2 BCC1 Dev to Dbg BCC0 Dbg to Dev Boot Communication Channels Wait for command CMD_CEx Get 128 bits key as 4x32bits words CEx_Keyword0 Boot ROM Debugger Boot ROM in interactive mode SAML11 ? CEx_Keyword1 CEx_Keyword2 CEx_Keyword3 Boot ROM in interactive mode Verify key SIG_CMD_VALID NOTE : debugger polls the BCC0D bit to know when bootrom has read the word before sending the next ChipErase_x disabled? SIG_CMD_INVALID Key matches BOCOR key? SIG_CMD_BADKEY NOTE : a 100us delay is inserted before sending BADKEY status Erase targeted memories SIG_CMD_SUCCESS On error, one of SIG_CE_x is reported Debugger polls for status update on BCC1 Get data Get command code Get keyword 0 Get keyword 3 Get keyword 1 Get keyword 2 Ce disabled Ce not disabled keys don't match Keys match 14.4.5.6 NVM Memory Regions Integrity Checks (CMD_CRC) The Boot ROM provides a way to check the integrity of the embedded non-volatile memories which may be of interest in case of a failure analysis. This requires the user to place tables describing the memory area to be checked with their expected CRC values. Note:  During this integrity check process, the debugger sends the CRC table address to the device. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 88 Important:  The table(s) must be programmed by the programming tool in addition to the application binaries. 14.4.5.6.1 CRC Table format Table 14-7. CRC Table Fields Description Description Header Start Address (1) Size in bytes (2) Expected value (3) Field HDR ADDR SIZE REFVAL Offset 0x0 0x4 0x8 0xC Value 0x43524349 0x00000000 0x100 0xAABBCCDD Note 1: ADDR must be a multiple of 4 (Only ADDR[31:2] are used). Note 2: SIZE must be a multiple of 4 (Only SIZE[31:2] are used). Note 3: The expected value is the computed CRC32 value of the memory target. 14.4.5.6.2 Requirements • Each table occupies 16 bytes in memory. • The table must start at a 16byte aligned address. (i.e. 0xXXXXXXX0) • The table must be placed in the same memory region as its target memory range. (i.e. a table placed in the Secure APPLICATION region can only target Secure APPLICATION memory addresses). Note: There are two exceptions to this rule: • For SAM L10: all non-volatile memories are considered as a single region (e.g. a table located in Data Flash can target main array) • For SAM L11: ANSC and BNSC regions are considered to belong to the same region as their “parent” region: AS for ANSC and BS for BNSC. 14.4.5.6.3 CRC Command Key The CRC command (CMD_ CRC) requires an access key (CRCKEY) which is in the NVM BOCOR row at: [0x80C040:0x80C04F]: BOCOR Offset Bit Position Name 0x40-0x4F 639:512 CRCKEY Just like the ChipErase keys, the key can be set to all 0s to prevent any access to the command. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 89 14.4.5.6.4 CMD_CRC Figure 14-12. CMD_CRC Flow diagram Debugger idle Debugger requests CRC of a table BCC1 Dev to Dbg BCC0 Dbg to Dev Boot Communication Channels Wait for command CMD_CRC Get 128 bits key as 4x32bits words CRC_Keyword0 Boot ROM Debugger Boot ROM in interactive mode Internal checks CRC_Keyword1 CRC_Keyword2 CRC_Keyword3 Boot ROM in interactive mode Verify key SIG_CMD_VALID NOTE : debugger polls the BCC0D bit to know when Boot ROM has read the word before sending the next CRC command disabled? SIG_CMD_INVALID Key matches BOCOR key? SIG_CMD_BADKEY NOTE : a 100us delay is inserted before sending BADKEY status Signal crc start SIG_CMD_VALID Debugger polls for status update on BCC1 Process CRC table SIG_CMD_BADTBL Check CRC of target area SIG_CMD_SUCCESS SIG_CMD_FAIL Debugger polls for status update on BCC1 Wait for table address CRC Table Address Send CRC table address Get data Get command code Get keyword 0 Get keyword 3 Get keyword 1 Get keyword 2 Crc disabled Crc not disabled keys don't match Keys match Read Status Table incorrect Crc ok Crc fail Read Status Get table address SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 90 14.4.5.7 Random Session Key Generation (CMD_DCEK) - SAM L11 only This command allows using a challenge-response scheme to prevent exposure of the keys in clear text on the debugger communication lines. The different keys sent by the debugger during the Boot ROM for Chip Erase (CMD_CEx) and CRC (CMD_CRC) commands execution are: • CRCKEY for CMD_CRC command • CEKEYx for CMD_CEx commands Note:  The CMD_DCEK command has no effect on the SAM L10, the key derivation will not be enabled. The random challenge value is generated using the TRNG of the device. It is generated once the CMD_DCEK is received and communicated to the debugger. The next CMD_CEx or CMD_CRC commands will expect the key value to be replaced by the computed response corresponding to the challenge. The challenge value is valid only for the next CMD_CEx/ CMD_CRC command. Before sending a new CMD_CEx/ CMD_CRC command, a CMD_DCEK shall be used to re-enable the challenge-response scheme a get a new challenge value. On the debugger side, the response shall be computed using the following algorithm: Figure 14-13. Debugger Algorithm Where KeyIndex is: • 0 for ChipErase_NS • 1 for ChipErase_S • 2 for ChipErase_ALL • 3 for CRC Command Note:  SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 91 • HMAC is described in FIPS PUB 198-1. • The hash used for HMAC is SHA256. • The output of the HMAC-SHA256 is truncated to obtain an HMAC-SHA256-128 as explained in RFC4868. 14.4.5.7.1 CMD_DCEK (SAM L11 only) Figure 14-14. CMD_DCEK Flow diagram Debugger idle Debugger requests key derivation BCC1 Dev to Dbg BCC0 Dbg to Dev Boot Communication Channels Wait for command CMD_DCEK Send 128 bits random number as 4x32bits words RandomDat0 Boot ROM Debugger Boot ROM in interactive mode Generate random data RandomDat1 RandomDat2 RandomDat3 Boot ROM in interactive mode Set key derivation on Set key derivation on Get data Get data Get data Get data Get command code 14.4.5.8 NVM Rows Content Checks (CMD_RAUX) The Boot ROM provides a way to check the content of the NVM rows. When device is secured (DAL0), the fuse configuration can still be read by the debugger using the Read Auxiliary command (CMD_RAUX). SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 92 The following areas are accessible: Table 14-8. Accessible Memory Range by Read Auxiliary Row Command Area Start address End address User row (UROW) 0x00804000 0x0080401F Software Calibration row 0x00806020 0x0080602F Temperature Log row 0x00806038 0x0080603F Boot Configuration row (BOCOR) 0x0080C000 0x0080C0FF 14.4.5.8.1 CMD_RAUX Figure 14-15. CMD_RAUX Flow diagram Debugger idle Debugger requests a word in AUX address space BCC1 Dev to Dbg BCC0 Dbg to Dev Boot Communication Channels Wait for command CMD_RAUX Boot ROM Debugger Boot ROM in interactive mode Address in allowed range ? Boot ROM in interactive mode Send value DATA_VALUE Debugger polls for status update on BCC1 SIG_ARG_VALID Wait for address Target Address Wait for address Debugger exits read loop out of range Address (eg 0x0) Address in allowed range ? SIG_ARG_INVALID Debugger polls for status update on BCC1 Get status Get command code Get Value Yes Get address No Get status Note: After the CMD_RAUX is sent, the debugger can read multiple data, the read loop is exit when an out of range address is sent. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 93 14.4.5.9 Boot Interactive Mode Commands Table 14-9. Boot Interactive Mode Commands Command Name Description Command prefix Command CMD_INIT Entering Interactive Mode 0x444247 55 CMD_EXIT Exit Interactive Mode 0x444247 AA CMD_RESET System Reset Request 0x444247 52 CMD_CE0 ChipErase_NS for SAM L11 0x444247 E0 CMD_CE1 ChipErase_S for SAM L11 0x444247 E1 CMD_CE2 ChipErase_ALL for SAM L11 0x444247 E2 CMD_CHIPERASE ChipErase for SAM L10 0x444247 E3 CMD_CRC NVM Memory Regions Integrity Checks 0x444247 C0 CMD_DCEK Random Session Key Generation for SAM L11 0x444247 44 CMD_RAUX NVM Rows Integrity Checks 0x444247 4C 14.4.5.10 Boot Interactive Mode Status Table 14-10. Boot Interactive Mode Status Status Name Description Status prefix Status coding SIG_NO No Error 0xEC0000 00 SIG_SAN_FFF Fresh from factory error 0xEC0000 10 SIG_SAN_UROW UROW checksum error 0xEC0000 11 SIG_SAN_SECEN SECEN parameter error 0xEC0000 12 SIG_SAN_BOCOR BOCOR checksum error 0xEC0000 13 SIG_SAN_BOOTPROT BOOTPROT parameter error 0xEC0000 14 SIG_SAN_NOSECREG No secure register parameter error 0xEC0000 15 SIG_COMM Debugger start communication command 0xEC0000 20 SIG_CMD_SUCCESS Debugger command success 0xEC0000 21 SIG_CMD_FAIL Debugger command fail 0xEC0000 22 SIG_CMD_BADKEY Debugger bad key 0xEC0000 23 SIG_CMD_VALID Valid command 0xEC0000 24 SIG_CMD_INVALID Invalid command 0xEC0000 25 SIG_ARG_VALID Valid argument 0xEC0000 26 SIG_ARG_INVALID Invalid argument 0xEC0000 27 SIG_CE_CVM Chip erase error: CVM 0xEC0000 30 SIG_CE_ARRAY_ERASEFAIL Chip erase error: array erase fail 0xEC0000 31 SIG_CE_ARRAY_NVME Chip erase error: array NVME 0xEC0000 32 SIG_CE_DATA_ERASEFAIL Chip erase error: data erase fail 0xEC0000 33 SIG_CE_DATA_NVME Chip erase error: data NVME 0xEC0000 34 SIG_CE_BCUR Chip erase error: BOCOR, UROW 0xEC0000 35 SIG_CE_BC Chip erase error: BC check 0xEC0000 36 SIG_BOOT_OPT BOOTOPT parameter error 0xEC0000 40 SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 94 Status Name Description Status prefix Status coding SIG_BOOT_ERR Boot image hash verify fail 0xEC0000 41 SIG_BOCOR_HASH BOCOR hash error 0xEC0000 42 SIG_CRC_BADTBL Bad CRC table 0xEC0000 50 SIG_SECEN0_ERR PAC or IDAU cfg check failure 0xEC0000 60 SIG_SECEN1_ERR PAC or IDAU cfg check failure 0xEC0000 61 SIG_EXIT_ERR Exit: BC or check error 0xEC0000 70 SIG_HARDFAULT Hardfault error 0xEC0000 F0 SIG_BOOTOK Boot ROM ok to exit 0xEC0000 39 14.4.6 CPU Park mode This mode allows the debugger to get access to the resources of the device during Boot ROM execution while the CPU is trapped in a while loop. The debug access level when entering that mode corresponds to the DAL value which is programmed in the device. Important:  This mode is the recommended way to enter a debugging session in a safe way even if it is also possible to launch a debug session when the application is running. This mode is reached by sending the Exit command (CMD_EXIT) without clearing the DSU.STATUSA.BREXT bit to the Boot ROM. As soon as the BREXT bit is cleared, the device exits this state and performs a system reset. At this point, the MPU is still enabled and prevents software execution elsewhere than in Boot ROM region. If the host needs to run software on the device, MPU shall be disabled by accessing the Cortex-M23 MPU CTRL register with the debugger. SAM L10/L11 Family Boot ROM © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 95 15. PAC - Peripheral Access Controller 15.1 Overview The Peripheral Access Controller provides an interface for the locking and unlocking and for managing security attribution of peripheral registers within the device. It reports all violations that could happen when accessing a peripheral: write protected access, illegal access, enable protected access, access when clock synchronization or software reset is on-going. These errors are reported in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the slave bus level, when an access to a non-existing address is detected. 15.2 Features • Manages write protection access and reports access errors for the peripheral modules or bridges. • Manages security attribution for the peripheral modules (SAM L11) 15.3 Block Diagram Figure 15-1. PAC Block Diagram INTFLAG PERIPHERAL m PERIPHERAL 0 BUSn BUS0 Peripheral ERROR Peripheral ERROR WRITE CONTROL WRITE CONTROL PAC CONTROL PERIPHERAL m PERIPHERAL 0 SLAVEs PAC IRQ APB Slave ERROR 15.4 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 15.4.1 IO Lines Not applicable. 15.4.2 Power Management The PAC can continue to operate in any Sleep mode where the selected source clock is running. The PAC interrupts can be used to wake up the device from Sleep modes. The events can trigger other operations in the system without exiting sleep modes. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 96 Related Links 22. PM – Power Manager 15.4.3 Clocks The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default state of CLK_PAC_APB can be found in the related links. Related Links 19. MCLK – Main Clock 19.6.2.6 Peripheral Clock Masking 15.4.4 DMA Not applicable. 15.4.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the PAC interrupt requires the Interrupt Controller to be configured first. Table 15-1. Interrupt Lines Instances NVIC Line PAC ERR 15.4.6 Events The events are connected to the Event System, which may need configuration. Related Links 33. EVSYS – Event System 15.4.7 Debug Operation When the CPU is halted in Debug mode, write protection of all peripherals is disabled and the PAC continues normal operation. 15.4.8 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: • Write Control (WRCTRL) register • AHB Slave Bus Interrupt Flag Status and Clear (INTFLAGAHB) register • Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. 15.4.9 SAM L11 TrustZone Specific Register Access Protection All PAC registers can only be accessed in the secure alias, with the following exceptions: • Write Control (WRCTRL) register is also accessible in the Non-Secure Alias, but only for write protection requests on non-secured peripherals. • Peripheral Write Protection Status (STATUSn) registers are also accessible in the Non-Secure Alias, but they will only report information on non-secured peripherals. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 97 Note:  Refer to the Mix-Secure Peripherals section in the SAM L11 Security Features chapter for more information. 15.5 Functional Description 15.5.1 Principle of Operation The Peripheral Access Control module allows the user to set a write protection or security attribution on peripheral modules and generate an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, cleared or locked at the user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the peripherals. In addition, slaves bus errors can be also reported in the cases where reserved area is accessed by the application. 15.5.2 Basic Operation 15.5.2.1 Initialization After reset, the PAC is enabled. 15.5.2.2 Initialization, Enabling and Resetting The PAC is always enabled after reset. Only a hardware reset will reset the PAC module. 15.5.2.3 Operations The PAC module allows the user to set, clear or lock the write protection status and security attribution of all peripherals on all Peripheral Bridges. If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all peripherals connected to the corresponding Peripheral Bridge n. The corresponding Peripheral Non-Secure Status n register (NONSECn) gives the state of the security attribution for all peripherals connected to the corresponding Peripheral Bridge n. Refer to 15.5.2.4 Peripheral Access Errors for details. The PAC module also report the errors occurring at slave bus level when an access to reserved area is detected. AHB Slave Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the corresponding slave. Refer to the 15.5.2.9 AHB Slave Bus Errors for details. 15.5.2.4 Peripheral Access Errors The following events will generate a Peripheral Access Error: • Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write protected. Only the registers denoted as “PAC Write-Protection” in the module’s datasheet can be protected. If a peripheral is not write protected, write data accesses are performed normally. If a peripheral is write protected and if a write access is attempted, data will not be written and peripheral returns an access error. The corresponding interrupt flag bit in the INTFLAGn register will be set. • Illegal access: Access to an unimplemented register within the module. • Synchronized write error: For write-synchronized registers an error will be reported if the register is written while a synchronization is ongoing. When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable bit is set. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 98 15.5.2.5 Write Access Protection Management Peripheral access control can be enabled or disabled by writing to the WRCTRL register. The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY. The WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key value that defines the operation to be done on the control access bit. These operations can be “clear protection”, “set protection” and “set and lock protection bit”. The “clear protection” operation will remove the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral. The “set protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID. Write accesses are not allowed for the registers with write protection property in this peripheral. The “set and lock protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID and locks the access rights of the selected peripheral registers. The write access protection will only be cleared by a hardware reset. The peripheral access control status can be read from the corresponding STATUSn register. 15.5.2.6 Write Access Protection Management Errors Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of accesses will have no effect and will cause a PAC write access error. This error is reported in the INTFLAGn.PAC bit corresponding to the PAC module. PAC also offers an additional safety feature for correct program execution with an interrupt generated on double write clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection operation is detected then the PAC returns an error, and similarly for a double clear protection operation. In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral or when a write access is done to a locked set protection. This can be used to ensure that the application follows the intended program flow by always following a write protect with an unprotect and conversely. However in applications where a write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt can not happen while the main application or other interrupt levels manipulates the write protection status or when the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS register. The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will set the INTFLAGn.PAC flag. 15.5.2.7 SAM L11 Security Attribution Management The peripheral security attribution status can be read from the corresponding NONSECn register. 15.5.2.8 SAM L11 Security Attribution Management Errors The errors generated while accessing the PAC module registers (e.g., key error, double protect error...) will set the INTFLAGn.PAC flag. 15.5.2.9 AHB Slave Bus Errors The PAC module reports errors occurring at the AHB Slave bus level. These errors are generated when an access is performed at an address where no slave (bridge or peripheral) is mapped or where nonsecure accesses are prohibited. These errors are reported in the corresponding bits of the INTFLAGAHB register. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 99 15.5.2.10 Generating Events The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To enable the PAC event generation, the control bit EVCTRL.ERREO must be set a '1'. 15.5.3 DMA Operation Not applicable. 15.5.4 Interrupts The PAC has the following interrupt source: • Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC module, or a bridge error occurred in one of the bridges reported by the PAC – This interrupt is a synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present. Note that interrupts must be globally enabled for interrupt requests to be generated. Related Links 22.6.3.3 Sleep Mode Controller 15.5.5 Events The PAC can generate the following output event: • Error (ERR): Generated when one of the interrupt flag registers bits is set Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding output event. Writing a '0' to this bit disables the corresponding output event. 15.5.6 Sleep Mode Operation In Sleep mode, the PAC is kept enabled if an available bus master (CPU, DMA) is running. The PAC will continue to catch access errors from the module and generate interrupts or events. 15.5.7 SAM L11 Secure and Non-Secure Read/Write Accesses Non-Secure write to EVCTRL, INTENCLR, INTENSET, INTFLAGAHB, INTFLAGx, and NONSECx registers is prohibited. Non-Secure read to EVCTRL, INTENCLR, INTENSET, INTFLAGAHB, and INTFLAGx registers will return zero with no error resulting. Non-secure write to a bit of STATUSx registers (by writing to the WRCTRL register) is prohibited if the corresponding bit in NONSECx is zero. STATUSx bits relating to secure peripherals (i.e., the corresponding bits in NONSECx are zero), read as zero in Non-Secure mode, with no error resulting. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 100 15.5.8 Synchronization Not applicable. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 101 15.6 Register Summary Important:  For SAM L11, the PAC register map is automatically duplicated in a Secure and Non-Secure alias: • The Non-Secure alias is at the peripheral base address • The Secure alias is located at the peripheral base address + 0x200 Refer to Mix-Secure Peripherals for more information on register access rights Offset Name Bit Pos. 0x00 WRCTRL 7:0 PERID[7:0] 15:8 PERID[15:8] 23:16 KEY[7:0] 31:24 0x04 EVCTRL 7:0 ERREO 0x05 ... 0x07 Reserved 0x08 INTENCLR 7:0 ERR 0x09 INTENSET 7:0 ERR 0x0A ... 0x0F Reserved 0x10 INTFLAGAHB 7:0 BROM HSRAMDSU HSRAMDMA C HSRAMCPU HPB2 HPB1 HPB0 FLASH 15:8 23:16 31:24 0x14 INTFLAGA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 AC PORT FREQM EIC RTC WDT 23:16 31:24 0x18 INTFLAGB 7:0 Reserved DMAC NVMCTRL DSU IDAU 15:8 23:16 31:24 0x1C INTFLAGC 7:0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 TRAM OPAMP CCL TRNG PTC DAC 23:16 31:24 0x20 ... 0x33 Reserved SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 102 Offset Name Bit Pos. 0x34 STATUSA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 AC PORT FREQM EIC RTC WDT 23:16 31:24 0x38 STATUSB 7:0 Reserved DMAC NVMCTRL DSU IDAU 15:8 23:16 31:24 0x3C STATUSC 7:0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 TRAM OPAMP CCL TRNG PTC DAC 23:16 31:24 0x40 ... 0x53 Reserved 0x54 NONSECA 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 AC PORT FREQM EIC RTC WDT 23:16 31:24 0x58 NONSECB 7:0 HMATRIXHS DMAC NVMCTRL DSU IDAU 15:8 23:16 31:24 0x5C NONSECC 7:0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 TRAM OPAMP CCL TRNG PTC DAC 23:16 31:24 15.7 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to the related links. On SAM L11 devices, the Mix-Secure peripheral has different types of registers (Non-Secure, Secure, Write-Secure, Mix-Secure, and Write-Mix-Secure) with different access permissions for each bitfield. Refer to Mix-Secure Peripherals for more details. In the following register descriptions, the access permissions are specified as shown in the following figure. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 103 Bit 7 6 5 4 3 2 1 0 CMD[7:0] Access R/-/RW R/-/RW R/-/RW R/-/RW R/-/RW R/-/RW R/-/RW R/-/RW TrustZone Non-Protected Devices Access TrustZone Protected Devices Non-Secure Access TrustZone Protected Devices Secure Access SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 104 15.7.1 Write Control Name:  WRCTRL Offset:  0x00 Reset:  0x00000000 Property:  – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 KEY[7:0] Access RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 PERID[15:8] Access RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PERID[7:0] Access RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW RW/RW/RW Reset 0 0 0 0 0 0 0 0 Bits 23:16 – KEY[7:0] Peripheral Access Control Key These bits define the peripheral access control key: Value Name Description 0x0 OFF No action 0x1 CLEAR Clear the peripheral write control 0x2 SET Set the peripheral write control 0x3 LOCK Set and lock the peripheral write control until the next hardware reset Bits 15:0 – PERID[15:0] Peripheral Identifier The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral Identifier is calculated by the following formula: ܲܧܴܦܫ = 32* BridgeNumber + N Where BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for Peripheral Bridge B, etc.). N represents the peripheral index from the respective Peripheral Bridge Number, which can be retrieved in the Peripherals Configuration Summary table: SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 105 Table 15-2. PERID Values Peripheral Bridge Name BridgeNumber PERID Values A 0 0+N B 1 32+N C 2 64+N SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 106 15.7.2 Event Control Name:  EVCTRL Offset:  0x04 Reset:  0x00 Property:  Secure Bit 7 6 5 4 3 2 1 0 ERREO Access RW/-/RW Reset 0 Bit 0 – ERREO Peripheral Access Error Event Output This bit indicates if the Peripheral Access Error Event Output is enabled or disabled. When enabled, an event will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Value Description 0 Peripheral Access Error Event Output is disabled. 1 Peripheral Access Error Event Output is enabled. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 107 15.7.3 Interrupt Enable Clear Name:  INTENCLR Offset:  0x08 Reset:  0x00 Property:  PAC Write-Protection, Secure This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 7 6 5 4 3 2 1 0 ERR Access RW/-/RW Reset 0 Bit 0 – ERR Peripheral Access Error Interrupt Disable This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding interrupt request. Value Description 0 Peripheral Access Error interrupt is disabled. 1 Peripheral Access Error interrupt is enabled. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 108 15.7.4 Interrupt Enable Set Name:  INTENSET Offset:  0x09 Reset:  0x00 Property:  PAC Write-Protection, Secure This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENCLR). Bit 7 6 5 4 3 2 1 0 ERR Access RW/-/RW Reset 0 Bit 0 – ERR Peripheral Access Error Interrupt Enable This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set: Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt request. Value Description 0 Peripheral Access Error interrupt is disabled. 1 Peripheral Access Error interrupt is enabled. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 109 15.7.5 AHB Slave Bus Interrupt Flag Status and Clear Name:  INTFLAGAHB Offset:  0x10 Reset:  0x000000 Property:  Secure This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BROM HSRAMDSU HSRAMDMAC HSRAMCPU HPB2 HPB1 HPB0 FLASH Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bit 7 – BROM Interrupt Flag for Boot ROM Bit 6 – HSRAMDSU Interrupt Flag for SLAVE HS SRAM Port 2 - DSU Access Bit 5 – HSRAMDMAC Interrupt Flag for SLAVE HS SRAM Port 1 - DMAC Access Bit 4 – HSRAMCPU Interrupt Flag for SLAVE HS SRAM Port 0 - CPU Access Bit 3 – HPB2 Interrupt Flag for SLAVE AHB-APB Bridge C Bit 2 – HPB1 Interrupt Flag for SLAVE AHB-APB Bridge B Bit 1 – HPB0 Interrupt Flag for SLAVE AHB-APB Bridge A Bit 0 – FLASH Interrupt Flag for SLAVE FLASH SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 110 15.7.6 Peripheral Interrupt Flag Status and Clear A Name:  INTFLAGA Offset:  0x14 Reset:  0x000000 Property:  Secure This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGA bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGA interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 AC PORT FREQM EIC RTC WDT Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bit 13 – AC Interrupt Flag for AC Bit 12 – PORT Interrupt Flag for PORT Bit 11 – FREQM Interrupt Flag for FREQM Bit 10 – EIC Interrupt Flag for EIC Bit 9 – RTC Interrupt Flag for RTC Bit 8 – WDT Interrupt Flag for WDT Bit 7 – GCLK Interrupt Flag for GCLK Bit 6 – SUPC Interrupt Flag for SUPC SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 111 Bit 5 – OSC32KCTRL Interrupt Flag for OSC32KCTRL Bit 4 – OSCCTRL Interrupt Flag for OSCCTRL Bit 3 – RSTC Interrupt Flag for RSTC Bit 2 – MCLK Interrupt Flag for MCLK Bit 1 – PM Interrupt Flag for PM Bit 0 – PAC Interrupt Flag for PAC SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 112 15.7.7 Peripheral Interrupt Flag Status and Clear B Name:  INTFLAGB Offset:  0x18 Reset:  0x000000 Property:  Secure This flag is cleared by writing a '1' to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGB bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Reserved DMAC NVMCTRL DSU IDAU Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 Bit 4 – Reserved Reserved Bit 3 – DMAC Interrupt Flag for DMAC Bit 2 – NVMCTRL Interrupt Flag for NVMCTRL Bit 1 – DSU Interrupt Flag for DSU Bit 0 – IDAU Interrupt Flag for IDAU SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 113 15.7.8 Peripheral Interrupt Flag Status and Clear C Name:  INTFLAGC Offset:  0x1C Reset:  0x000000 Property:  Secure This flag is cleared by writing a one to the flag. This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective INTFLAGC bit, and will generate an interrupt request if INTENCLR/SET.ERR is one. Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TRAM OPAMP CCL TRNG PTC DAC Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS Access RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW RW/-/RW Reset 0 0 0 0 0 0 0 0 Bit 13 – TRAM Interrupt Flag for TRAM Bit 12 – OPAMP Interrupt Flag for OPAMP Bit 11 – CCL Interrupt Flag for CCL Bit 10 – TRNG Interrupt Flag for TRNG Bit 9 – PTC Interrupt Flag for PTC Bit 8 – DAC Interrupt Flag for DAC Bit 7 – ADC Interrupt Flag for ADC Bits 4, 5, 6 – TC Interrupt Flag for TCn [n = 2..0] SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 114 Bits 1, 2, 3 – SERCOM Interrupt Flag for SERCOMn [n = 2..0] Bit 0 – EVSYS Interrupt Flag for EVSYS SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 115 15.7.9 Peripheral Write Protection Status A Name:  STATUSA Offset:  0x34 Reset:  0x000000 Property:  Mix-Secure Reading STATUSA register returns peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Important:  For SAM L11 Non-Secure accesses, read accesses (R*) are allowed only if the peripheral security attribution for the corresponding peripheral is set as Non-Secured in the NONSECx register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 AC PORT FREQM EIC RTC WDT Access R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R Reset 0 0 0 0 0 0 0 0 Bit 13 – AC Peripheral AC Write Protection Status Bit 12 – PORT Peripheral PORT Write Protection Status Bit 11 – FREQM Peripheral FREQM Write Protection Status Bit 10 – EIC Peripheral EIC Write Protection Status Bit 9 – RTC Peripheral RTC Write Protection Status SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 116 Bit 8 – WDT Peripheral WDT Write Protection Status Bit 7 – GCLK Peripheral GCLK Write Protection Status Bit 6 – SUPC Peripheral SUPC Write Protection Status Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Write Protection Status Bit 4 – OSCCTRL Peripheral OSCCTRL Write Protection Status Bit 3 – RSTC Peripheral RSTC Write Protection Status Bit 2 – MCLK Peripheral MCLK Write Protection Status Bit 1 – PM Peripheral PM Write Protection Status Bit 0 – PAC Peripheral PAC Write Protection Status SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 117 15.7.10 Peripheral Write Protection Status B Name:  STATUSB Offset:  0x38 Reset:  0x000000 Property:  Mix-Secure Reading the STATUSB register returns the peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Important:  For SAM L11 Non-Secure accesses, read accesses (R*) are allowed only if the peripheral security attribution for the corresponding peripheral is set as Non-Secured in the NONSECx register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 Reserved DMAC NVMCTRL DSU IDAU Access R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R Reset 0 0 0 0 0 Bit 4 – Reserved Reserved Bit 3 – DMAC Peripheral DMAC Write Protection Status Bit 2 – NVMCTRL Peripheral NVMCTRL Write Protection Status Bit 1 – DSU Peripheral DSU Write Protection Status Bit 0 – IDAU Peripheral IDAU Write Protection Status SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 118 15.7.11 Peripheral Write Protection Status C Name:  STATUSC Offset:  0x3C Reset:  0x000000 Property:  Mix-Secure Reading the STATUSC register returns the peripheral write protection status: Value Description 0 Peripheral is not write protected. 1 Peripheral is write protected. Important:  For SAM L11 Non-Secure accesses, read accesses (R*) are allowed only if the peripheral security attribution for the corresponding peripheral is set as Non-Secured in the NONSECx register. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TRAM OPAMP CCL TRNG PTC DAC Access R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R R/R*/R Reset 0 0 0 0 0 0 0 0 Bit 13 – TRAM Peripheral TRAM Write Protection Status Bit 12 – OPAMP Peripheral OPAMP Write Protection Status Bit 11 – CCL Peripheral CCL Write Protection Status Bit 10 – TRNG Peripheral TRNG Write Protection Status Bit 9 – PTC Peripheral PTC Write Protection Status SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 119 Bit 8 – DAC Peripheral DAC Write Protection Status Bit 7 – ADC Peripheral ADC Write Protection Status Bits 4, 5, 6 – TC Peripheral TCn Write Protection Status [n = 2..0] Bits 1, 2, 3 – SERCOM Peripheral SERCOMn Write Protection Status [n = 2..0] Bit 0 – EVSYS Peripheral EVSYS Write Protection Status SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 120 15.7.12 Peripheral Non-Secure Status - Bridge A Name:  NONSECA Offset:  0x54 Reset:  x initially determined from NVM User Row after reset Property:  Write-Secure Important:  This register is only available for SAM L11 and has no effect for SAM L10. Reading NONSEC register returns peripheral security attribution status: Value Description 0 Peripheral is secured. 1 Peripheral is non-secured. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 AC PORT FREQM EIC RTC WDT Access R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R Reset x x x x x x Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R Reset x x x x x x x 0 Bit 13 – AC Peripheral AC Non-Secure Bit 12 – PORT Peripheral PORT Non-Secure Bit 11 – FREQM Peripheral FREQM Non-Secure Bit 10 – EIC Peripheral EIC Non-Secure Bit 9 – RTC Peripheral RTC Non-Secure SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 121 Bit 8 – WDT Peripheral WDT Non-Secure Bit 7 – GCLK Peripheral GCLK Non-Secure Bit 6 – SUPC Peripheral SUPC Non-Secure Bit 5 – OSC32KCTRL Peripheral OSC32KCTRL Non-Secure Bit 4 – OSCCTRL Peripheral OSCCTRL Non-Secure Bit 3 – RSTC Peripheral RSTC Non-Secure Bit 2 – MCLK Peripheral MCLK Non-Secure Bit 1 – PM Peripheral PM Non-Secure Bit 0 – PAC Peripheral PAC Non-Secure The PAC Peripheral is always secured. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 122 15.7.13 Peripheral Non-Secure Status - Bridge B Name:  NONSECB Offset:  0x58 Reset:  x initially determined from NVM User Row after reset Property:  Write-Secure Important:  This register is only available for SAM L11 and has no effect for SAM L10. Reading NONSEC register returns peripheral security attribution status: Value Description 0 Peripheral is secured. 1 Peripheral is non-secured. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HMATRIXHS DMAC NVMCTRL DSU IDAU Access R/R/R R/R/R R/R/R R/R/R R/R/R Reset x x 0 1 0 Bit 4 – HMATRIXHS Peripheral HMATRIXHS Non-Secure Bit 3 – DMAC Peripheral DMAC Non-Secure Bit 2 – NVMCTRL Peripheral NVMCTRL Non-Secure The NVMCTRL Peripheral is always secured. Bit 1 – DSU Peripheral DSU Non-Secure The DSU Peripheral is always non-secured. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 123 Bit 0 – IDAU Peripheral IDAU Non-Secure The IDAU Peripheral is always secured. SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 124 15.7.14 Peripheral Non-Secure Status - Bridge C Name:  NONSECC Offset:  0x5C Reset:  x initially determined from NVM User Row after reset Property:  Write-Secure Important:  This register is only available for SAM L11 and has no effect for SAM L10. Reading NONSEC register returns peripheral Security Attribution status: Value Description 0 Peripheral is secured. 1 Peripheral is non-secured. Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TRAM OPAMP CCL TRNG PTC DAC Access R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R Reset x x x x x x Bit 7 6 5 4 3 2 1 0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R R/R/R Reset x x x x x x x x Bit 13 – TRAM Peripheral TRAM Non-Secure Bit 12 – OPAMP Peripheral OPAMP Non-Secure Bit 11 – CCL Peripheral CCL Non-Secure Bit 10 – TRNG Peripheral TRNG Non-Secure Bit 9 – PTC Peripheral PTC Non-Secure SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 125 Bit 8 – DAC Peripheral DAC Non-Secure Bit 7 – ADC Peripheral ADC Non-Secure Bits 4, 5, 6 – TC Peripheral TCn Non-Secure [n = 2..0] Bits 1, 2, 3 – SERCOM Peripheral SERCOMn Non-Secure [n = 2..0] Bit 0 – EVSYS Peripheral EVSYS Non-Secure SAM L10/L11 Family PAC - Peripheral Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 126 16. DSU - Device Service Unit 16.1 Overview The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM Debug Access Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as well as identification of other debug components within the system. Hence, it complies with the ARM Peripheral Identification specification. The DSU also provides system services to applications that need memory testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as it is connected on the High-Speed Bus Matrix. It implements communication channels between the device and external tools which can be used at boot time to make use of Boot ROM services. For security reasons, some of the DSU features will be limited or unavailable when the Debug Access Level (DAL) is less than 0x2. Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.2 Features • CPU reset extension • Debugger probe detection (Cold- and Hot-Plugging) • 32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix • ARM® CoreSight™ compliant device identification • Two debug communications channels • Two Boot communications channels • Debug access port security filter • Onboard memory built-in self-test (MBIST) SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 127 16.3 Block Diagram Figure 16-1. DSU Block Diagram DSU SWCLK CORESIGHT ROM DAP SECURITY FILTER CRC-32 MBIST RESET CPU DAP SWDIO NVMCTRL DBG HIGH-SPEED BUS MATRIX debugger_present D GG R RO INTERFACE AHB-AP cpu_reset_extension AHB-APB BRIDGE B PORT 16.4 Signal Description The DSU uses three signals to function. Signal Name Type Description RESET Digital Input External reset SWCLK Digital Input SW clock SWDIO Digital I/O SW bidirectional data pin 16.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 16.5.1 I/O Lines The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU reset phase. For more information, refer to 16.6.3 Debugger Probe Detection. The HotPlugging feature depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the Hot-Plugging feature is disabled until a power-reset or an external reset is performed. 16.5.2 Power Management The DSU will continue to operate in Idle mode. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 128 Related Links 22. PM – Power Manager 16.5.3 Clocks The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main Clock Controller. Related Links 22. PM – Power Manager 19. MCLK – Main Clock 19.6.2.6 Peripheral Clock Masking 16.5.4 DMA The DMA request lines are connected to the DMA Controller (DMAC). To use DMA requests with this peripheral, the DMAC must be configured first. Refer to 28. DMAC – Direct Memory Access Controller for details. The CFG.DCCDMALEVEL bitfield must be configured depending on the DMA channels access modes (read or write for DCC0 and DCC1). 16.5.5 Interrupts Not applicable. 16.5.6 Events Not applicable. 16.5.7 Register Access Protection Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for the following: • Debug Communication Channel 0 register (DCC0) • Debug Communication Channel 1 register (DCC1) • Boot Communication Channel 0 register (BCC0) • Boot Communication Channel 1 register (BCC1) Note:  Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. Related Links 15. PAC - Peripheral Access Controller 16.5.8 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 129 Refer to Peripherals Security Attribution for more information. 16.5.9 Analog Connections Not applicable. 16.6 Debug Operation 16.6.1 Principle of Operation The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor debug resources: • CPU reset extension • Debugger probe detection • Boot Communication Channels For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification. 16.6.2 CPU Reset Extension “CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This ensures that the CPU is not executing code at startup while a debugger connects to the system. It is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a debugger if SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a '0' to STATUSA.CRSTEXT has no effect. Releasing the "CPU reset extension" is possible for all DAL levels. The CPU then executes the Boot ROM that offers basic failure analysis services and security checks. It is not possible to access the bus system until the Boot ROM has performed these security checks. Note:  Refer to 14. Boot ROM for more information. Figure 16-2. Typical CPU Reset Extension Set and Clear Timing Diagram DSU CRSTEXT Clear SWCLK CPU reset extension CPU_STATE reset running RESET SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 130 16.6.3 Debugger Probe Detection 16.6.3.1 Cold Plugging Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset extension is requested, as described above. 16.6.3.2 Hot Plugging Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the Status B register (STATUSB.HPE). Figure 16-3. Hot-Plugging Detection Timing Diagram SWCLK Hot-Plugging CPU_STATE reset running RESET The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not available when DAL equals to 0x0. This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is released. If DAL equals 0x0, Cold-Plugging is the only way to detect a debugger probe, and so the external reset timing must be longer than the POR timing. If external reset is de-asserted before POR release, the user must retry the procedure above until it gets connected to the device. Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.6.4 Boot Communication Channels Boot Communication Channels allow communication between a debug adapter and the CPU executing the Boot ROM at startup. The Boot ROM implements system level commands. Refer to 14. Boot ROM for more information. 16.7 Programming Programming the Flash or RAM memories is only possible when the debugger access level is sufficient to access the desired resource: If DAL is equal to: • 0x2: debugger can access secured and non-secure areas • 0x1 (SAM L11 only): debugger can access only non-secure areas, refer to Table 16-4. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 131 • 0x0: debugger can only access the DSU external address space making it possible to communicate with the Boot ROM after reset. A typical programming procedure when DAL=0x2 is as follows: 1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until the internally regulated supplies have reached a safe operating state. 2. The Power Manager (PM) starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset. 3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger ColdPlugging procedure. 4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock. 5. The CPU executes the Boot ROM. 6. It is recommended to issue a Chip-Erase (supported by the Boot ROM) to ensure that the Flash is fully erased prior to programming. 7. If the operation issued above was accepted and has completed successfully then DAL equals 0x2 thus programming is available through the AHB-AP. 8. After the operation is completed, the chip can be restarted either by asserting RESET, toggling power, or sending a command to the Boot ROM to jump to the NVM code. Make sure that the SWCLK pin is high when releasing RESET to prevent entering again the cold-plugging procedure with the Boot ROM stalling the CPU. Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.8 Security Enforcement Security enforcement aims at protecting intellectual property, which includes: • Restricts access to internal memories from external tools depending on the debugger access level. • Restricts access to a portion of the DSU address space from non-secure AHB masters depending on the debugger access level. The DAL setting can be locked or reverted using Boot ROM commands depending on the Boot ROM user configuration. When DAL is equal to 0x0, read/write accesses using the AHB-AP are limited to the DSU external address range and DSU commands are restricted. When issuing a Boot ROM Chip-Erase, sensitive information is erased from volatile memory and Flash. Refer to 14. Boot ROM more information about the Boot ROM features. The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP. If DAL=0x0, then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response that sets the ARM AHB-AP sticky error bits (refer to the "ARM Debug Interface v5 Architecture Specification", which is available for download at http://www.arm.com). For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses from internal ones, the first 0x100 bytes of the DSU register map have been replicated at offset 0x100: • The first 0x100 bytes form the internal address range • The next 0x1F00 bytes form the external address range SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 132 When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range limited to the 0x100- 0x2000 offset range. The DSU operating registers are located in the 0x00-0xFF area and mirrored to 0x100-0x1FF to differentiate accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x100-0x1FF, it is subject to security restrictions. For more information, refer to the Table 16-2. Figure 16-4. APB Memory Mapping 0x0000 0x00FF 0x0100 0x01FF 0x1000 0x1FFF DSU operating registers Mirrored DSU operating registers DSU CoreSight ROM Empty Internal address range (cannot be accessed from debug tools when STATUSB.DAL<0x2 and cannot be accessed by a non-secure AHB master) External address range (can be accessed from debug tools with some restrictions, can be accessed by a non-secure AHB master) The DSU filters-out DAP transactions depending on the DAL setting and routes DAP transactions: • In the PPB or IOBUS space to the CPU debug port • Outside the PPB space and outside the IOBUS space to the DSU master port Table 16-1. DAP access rights depending on DAL: DAP access to SAM L11 SAM L10 DAL=0 DAL=1 DAL=2 DAL=0 DAL=2 PPB or IOBUS No Yes (see Note 1) Yes No Yes DSU internal address space No No (see Note 2) Yes No Yes DSU external address space Yes Yes Yes Yes Yes Other secure areas No No Yes No Yes Other non-secure areas No Yes Yes No Yes Note:  1. Refer to ARMv8-M debug documentation for detailed information on PPB and IOBUS access restrictions. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 133 2. When DAL=1 DAP transfers are always non-secure. The DSU internal address space can only be accessed by secure masters. Some features not activated by APB transactions are not available when the device is protected: Table 16-2. Feature Availability Under Protection Features Availability when DAL equals to 0x0 0x1 (SAM L11 only) 0x2 CPU Reset Extension Yes Yes Yes Clear CPU Reset extension Yes Yes Yes Debugger Cold-Plugging Yes Yes Yes Debugger Hot-Plugging No Yes Yes 16.9 Device Identification Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device. 16.9.1 CoreSight Identification A system-level ARM® CoreSight™ ROM table is present in the device to identify the vendor and the chip identification method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers: Figure 16-5. Conceptual 64-bit Peripheral ID Table 16-3. Conceptual 64-Bit Peripheral ID Bit Descriptions Field Size Description Location JEP-106 CC code 4 Continuation code: 0x0 PID4 JEP-106 ID code 7 Device ID: 0x1F PID1+PID2 4KB count 4 Indicates that the CoreSight component is a ROM: 0x0 PID4 RevAnd 4 Not used; read as 0 PID3 CUSMOD 4 Not used; read as 0 PID3 SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 134 Field Size Description Location PARTNUM 12 Contains 0xCD0 to indicate that DSU is present PID0+PID1 REVISION 4 DSU revision (starts at 0x0 and increments by 1 at both major and minor revisions). Identifies DSU identification method variants. If 0x0, this indicates that device identification can be completed by reading the Device Identification register (DID) PID2 For more information, refer to the ARM Debug Interface Version 5 Architecture Specification. 16.9.2 Chip Identification Method The DSU DID register identifies the device by implementing the following information: • Processor identification • Product family identification • Product series identification • Device select 16.10 Functional Description 16.10.1 Principle of Operation The DSU provides memory services, such as CRC32 or MBIST that require almost the same interface. Hence, the Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured first; then a command can be issued by writing the Control register. When a command is ongoing, other commands are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one. 16.10.2 Basic Operation 16.10.2.1 Initialization The module is enabled by enabling its clocks. For more details, refer to 16.5.3 Clocks. The DSU registers can be PAC write-protected. Related Links 15. PAC - Peripheral Access Controller 16.10.2.2 Operation From a Debug Adapter Debug adapters should access the DSU registers in the external address range [0x100 – 0x1FFF]. If STATUSB.DAL is equal to 0x0, accessing the first 0x100 bytes causes the DSU security filter to return an error to the DAP. (SAM L11 only): If STATUSB.DAL is equal to 0x1, debug accesses will go through the DSU security filter but will be forced as non-secure, therefore the DSU internal address space will not be accessible and any access in this case is discarded (writes are ignored, reads return 0) and raise STATUSA.PERR. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 135 Table 16-4. DAP transaction authorizations and error response types DAL Debugger Access Type DAP transaction allowed? DSU internal address space DSU external address space Other than PPB PPB 0 Secure No (Bus Error) Yes No (Bus Error) No (Bus Error) 0 Non-Secure No (Bus Error) Yes No (Bus Error) No (Bus Error) 1 (SAM L11 only) Secure No (PERR) Yes Yes (NS,PERR) Yes (ARMv8M) 1 (SAM L11 only) Non-Secure No (PERR) Yes Yes (NS,PERR) Yes (ARMv8M) 2 Secure Yes Yes Yes Yes 2 Non-Secure No (PERR) Yes Yes Yes Bus Error: A Bus Error is sent back to the DAP setting its sticky bit error. PERR: No bus error, STATUSA.PERR rises, writes are discarded, reads always return 0 NS, PERR: Access forced to non-secure, secure violations are reported in STATUSA.PERR. Note:  Refer to the ARM Debug Interface Architecture Specification for details. Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.10.2.3 Operation From the CPU Only secure masters can access the DSU internal address space. Attempting to access the internal address space from a non-secure AHB master will report a PAC error, such accesses are discarded. The external address space can be accessed by either secure or non-secure AHB masters. The user should access DSU registers in the internal address range (0x0 – 0xFF) to avoid external security restrictions. Refer to 16.8 Security Enforcement. 16.10.3 32-bit Cyclic Redundancy Check CRC32 The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including Flash and AHB RAM). When the CRC32 command is issued from: • The internal range from a secure AHB master, the CRC32 can be operated at any memory location • The external range, the CRC32 operation is not available The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320 (reversed representation). 16.10.3.1 Starting CRC32 Calculation CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the size of the memory range into the Length register (LENGTH). Both must be wordaligned. The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be 0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of separate memory blocks. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 136 Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent CRC32 calculations. The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST). Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.10.3.2 Interpreting the Results The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred. 16.10.4 Debug Communication Channels The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger with no security restriction. The registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and DCC1 registers are always accessible from the external address space. When the device starts with the cold-plugging procedure, a specific Boot ROM command is needed to exit the Boot ROM main routine. Important:  This command is allowed only when DAL=0x2, otherwise the device must be reset to leave the cold plugging state to let the CPU exit the Boot ROM routine and execute the user code. Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on read. Note:  The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly, DCC0 and DCC1 must not be used while performing MBIST operations. Note:  The DCC0 and DCC1 registers are shared with the BCC0 and BCC1 registers therefore mixing DCC and BCC communication is not recommended. Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.10.5 Boot Communication Channels The Boot Communication Channels (BCC0 and BCC1) consist of a pair of registers with associated handshake logic, accessible by both CPU and debugger with no security restriction. The registers are intended to communicate with the CPU while executing the Boot ROM which implements security and failure analysis commands and therefore must not be used for another purpose. Note:  The BCC0 and BCC registers values are not reset except in case of POR or BOD resets. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 137 Two Boot Communication Channel status bits in the Status B registers (STATUS.BCCDx) indicate whether a new value has been written in BCC0 or BCC1. These bits, BCC0D and BCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on read. Note:  The DCC0 and DCC1 registers are shared with the BCC0 and BCC1 registers therefore using DCC is not recommended while the Boot ROM is being executed. 16.10.6 Testing of On-Board Memories MBIST The DSU implements a feature for automatic testing of memory also known as MBIST (memory built-in self test). This is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address range when DAL<0x2. If an MBIST command is issued when the device is protected, it is filtered-out, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR) and STATUSA.DONE don't rise. 1. Algorithm The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a wide range of memory defects, while still keeping a linear run time. The algorithm is: 1.1. Write entire memory to '0', in any order. 1.2. Bit for bit read '0', write '1', in descending order. 1.3. Bit for bit read '1', write '0', read '0', write '1', in ascending order. 1.4. Bit for bit read '1', write '0', in ascending order. 1.5. Bit for bit read '0', write '1', read '1', write '0', in ascending order. 1.6. Read '0' from entire memory, in ascending order. The specific implementation used has a run time which depends on the CPU clock frequency and the number of bytes tested in the RAM. The detected faults are: – Address decoder faults – Stuck-at faults – Transition faults – Coupling faults – Linked Coupling faults 2. Starting MBIST To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size of the memory into the Length register. For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower. The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by writing a '1' to CTRL.SWRST. 3. Interpreting the Results The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set. There are two different modes: – ADDR.AMOD=0: exit-on-error (default) In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and ADDR registers to locate the fault. – ADDR.AMOD=1: pause-on-error SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 138 In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the fault. 4. Locating Faults If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error. The position of the failing bit can be found by reading the following registers: – ADDR: Address of the word containing the failing bit – DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA register will in this case contains the following bit groups: Figure 16-6. DATA bits Description When MBIST Operation Returns an Error Bit Bit Bit Bit phase bit_index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 • bit_index: contains the bit number of the failing bit • phase: indicates which phase of the test failed and the cause of the error, as listed in the following table. Table 16-5. MBIST Operation Phases Phase Test actions 0 Write all bits to zero. This phase cannot fail. 1 Read '0', write '1', increment address 2 Read '1', write '0' 3 Read '0', write '1', decrement address 4 Read '1', write '0', decrement address 5 Read '0', write '1' 6 Read '1', write '0', decrement address 7 Read all zeros. bit_index is not used SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 139 Table 16-6. AMOD Bit Descriptions for MBIST AMOD[1:0] Description 0x0 Exit on Error 0x1 Pause on Error 0x2, 0x3 Reserved Related Links 30. NVMCTRL – Nonvolatile Memory Controller 16.10.7 System Services Availability when Accessed Externally External access: Access performed in the DSU address offset 0x100-0x1FFF range. Internal access: Access performed in the DSU address offset 0x0-0xFF range. Table 16-7. Available Features when Operated From The External Address Range and Device is Protected Features Availability From The External Address Range when DAL<2 CRC32 No CoreSight Compliant Device identification Yes Debug communication channels Yes Boot communication channels Yes Testing of onboard memories (MBIST) No SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 140 16.11 Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 MBIST CRC SWRST 0x01 STATUSA 7:0 BREXT PERR FAIL BERR CRSTEXT DONE 0x02 STATUSB 7:0 BCCDx BCCDx DCCDx DCCDx HPE DBGPRES DAL[1:0] 0x03 Reserved 0x04 ADDR 7:0 ADDR[5:0] AMOD[1:0] 15:8 ADDR[13:6] 23:16 ADDR[21:14] 31:24 ADDR[29:22] 0x08 LENGTH 7:0 LENGTH[5:0] 15:8 LENGTH[13:6] 23:16 LENGTH[21:14] 31:24 LENGTH[29:22] 0x0C DATA 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x10 DCC0 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x14 DCC1 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x18 DID 7:0 DEVSEL[7:0] 15:8 DIE[3:0] REVISION[3:0] 23:16 FAMILY[0:0] SERIES[5:0] 31:24 PROCESSOR[3:0] FAMILY[4:1] 0x1C CFG 7:0 DCCDMALEVEL[1:0] LQOS[1:0] 15:8 23:16 31:24 0x20 BCC0 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x24 BCC1 7:0 DATA[7:0] 15:8 DATA[15:8] 23:16 DATA[23:16] 31:24 DATA[31:24] 0x28 ... 0x0FFF Reserved SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 141 Offset Name Bit Pos. 0x1000 ENTRY0 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1004 ENTRY1 7:0 FMT EPRES 15:8 ADDOFF[3:0] 23:16 ADDOFF[11:4] 31:24 ADDOFF[19:12] 0x1008 END 7:0 END[7:0] 15:8 END[15:8] 23:16 END[23:16] 31:24 END[31:24] 0x100C ... 0x1FCB Reserved 0x1FCC MEMTYPE 7:0 SMEMP 15:8 23:16 31:24 0x1FD0 PID4 7:0 FKBC[3:0] JEPCC[3:0] 15:8 23:16 31:24 0x1FD4 ... 0x1FDF Reserved 0x1FE0 PID0 7:0 PARTNBL[7:0] 15:8 23:16 31:24 0x1FE4 PID1 7:0 JEPIDCL[3:0] PARTNBH[3:0] 15:8 23:16 31:24 0x1FE8 PID2 7:0 REVISION[3:0] JEPU JEPIDCH[2:0] 15:8 23:16 31:24 0x1FEC PID3 7:0 REVAND[3:0] CUSMOD[3:0] 15:8 23:16 31:24 0x1FF0 CID0 7:0 PREAMBLEB0[7:0] 15:8 23:16 31:24 SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 142 Offset Name Bit Pos. 0x1FF4 CID1 7:0 CCLASS[3:0] PREAMBLE[3:0] 15:8 23:16 31:24 0x1FF8 CID2 7:0 PREAMBLEB2[7:0] 15:8 23:16 31:24 0x1FFC CID3 7:0 PREAMBLEB3[7:0] 15:8 23:16 31:24 16.12 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 16.5.7 Register Access Protection. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 143 16.12.1 Control Name:  CTRL Offset:  0x0000 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 MBIST CRC SWRST Access W W W Reset 0 0 0 Bit 3 – MBIST Memory Built-In Self-Test Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the memory BIST algorithm. Bit 2 – CRC 32-bit Cyclic Redundancy Check Writing a '0' to this bit has no effect. Writing a '1' to this bit starts the cyclic redundancy check algorithm. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets the module. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 144 16.12.2 Status A Name:  STATUSA Offset:  0x0001 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 BREXT PERR FAIL BERR CRSTEXT DONE Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 5 – BREXT Boot ROM Phase Extension Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Boot ROM Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the Boot ROM phase. Bit 4 – PERR Protection Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Protection Error bit. This bit is set upon access to: • A reserved address • CTRL, ADDR, LENGTH, DATA, CFG from the external address space when DAL<2 • The internal address space with a Non-Secure access (security violation) (SAM L11 only) Bit 3 – FAIL Failure Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Failure bit. This bit is set when a DSU operation failure is detected. Bit 2 – BERR Bus Error Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Bus Error bit. This bit is set when a bus error is detected. Bit 1 – CRSTEXT CPU Reset Phase Extension Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the CPU Reset Phase Extension bit. This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase. Bit 0 – DONE Done Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Done bit. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 145 This bit is set when a DSU operation is completed. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 146 16.12.3 Status B Name:  STATUSB Offset:  0x0002 Reset:  0xX Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 BCCDx BCCDx DCCDx DCCDx HPE DBGPRES DAL[1:0] Access R R R R R R R R Reset 0 0 0 0 1 0 0 x Bits 7,6 – BCCDx BOOT Communication Channel x Dirty [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when BCCx is written. This bit is cleared when BCCx is read. Bits 5,4 – DCCDx Debug Communication Channel x Dirty [x=1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when DCCx is written. This bit is cleared when DCCx is read. Bit 3 – HPE Hot-Plugging Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when Hot-Plugging is enabled. This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a power-reset or a external reset can set it again. Bit 2 – DBGPRES Debugger Present Writing a '0' to this bit has no effect. Writing a '1' to this bit has no effect. This bit is set when a debugger probe is detected. This bit is never cleared. Bits 1:0 – DAL[1:0] Debugger Access Level Indicates the debugger access level: • 0x0: Debugger can only access the DSU external address space. • 0x1: Debugger can access only Non-Secure regions (SAM L11 only). • 0x2: Debugger can access secure and Non-Secure regions. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 147 Writing in this bitfield has no effect. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 148 16.12.4 Address Name:  ADDR Offset:  0x0004 Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDR[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 ADDR[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 ADDR[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ADDR[5:0] AMOD[1:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:2 – ADDR[29:0] Address Initial word start address needed for memory operations. Bits 1:0 – AMOD[1:0] Address Mode The functionality of these bits is dependent on the operation mode. Bit description when testing on-16.10.6 Testing of On-Board Memories MBISTboard memories (MBIST): refer to SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 149 16.12.5 Length Name:  LENGTH Offset:  0x0008 Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 LENGTH[29:22] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 LENGTH[21:14] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LENGTH[13:6] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LENGTH[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 31:2 – LENGTH[29:0] Length Length in words needed for memory operations. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 150 16.12.6 Data Name:  DATA Offset:  0x000C Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Memory operation initial value or result value. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 151 16.12.7 Debug Communication Channel 0 Name:  DCC0 Offset:  0x0010 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 152 16.12.8 Debug Communication Channel 1 Name:  DCC1 Offset:  0x0014 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 153 16.12.9 Device Identification Name:  DID Offset:  0x0018 Reset:  see related links Property:  PAC Write-Protection The information in this register is related to the 2. Ordering Information. Bit 31 30 29 28 27 26 25 24 PROCESSOR[3:0] FAMILY[4:1] Access R R R R R R R R Reset p p p p f f f f Bit 23 22 21 20 19 18 17 16 FAMILY[0:0] SERIES[5:0] Access R R R R R R R Reset f s s s s s s Bit 15 14 13 12 11 10 9 8 DIE[3:0] REVISION[3:0] Access R R R R R R R R Reset d d d d r r r r Bit 7 6 5 4 3 2 1 0 DEVSEL[7:0] Access R R R R R R R R Reset x x x x x x x x Bits 31:28 – PROCESSOR[3:0] Processor The value of this field defines the processor used on the device. Bits 27:23 – FAMILY[4:0] Product Family The value of this field corresponds to the Product Family part of the ordering code. Bits 21:16 – SERIES[5:0] Product Series The value of this field corresponds to the Product Series part of the ordering code. Bits 15:12 – DIE[3:0] Die Number Identifies the die family. Bits 11:8 – REVISION[3:0] Revision Number Identifies the die revision number. 0x0=rev.A, 0x1=rev.B etc. Note:  The device variant (last letter of the ordering number) is independent of the die revision (DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of the die. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 154 Bits 7:0 – DEVSEL[7:0] Device Selection This bit field identifies a device within a product family and product series. Refer to 2. Ordering Information for device configurations and corresponding values for Flash memory density, pin count, and device variant. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 155 16.12.10 Configuration Name:  CFG Offset:  0x001C Reset:  0x0000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 DCCDMALEVEL[1:0] LQOS[1:0] Access RW RW RW RW Reset 0 0 0 2 Bits 3:2 – DCCDMALEVEL[1:0] DMA TriggerLevel 0x0X: DCC1 trigger is the image of STATUSB.DCC1D, this signals to the DMA that a data is available for read, this is the correct configuration for a channel that reads DCC1. 0x1X: DCC1 trigger is the image of STATUSB.DCC1D inverted, this signals to the DMA that DCC1 is ready for write, this is the correct configuration for a channel that writes DCC1 0xX0: DCC0 trigger is the image of STATUSB.DCC0D, this signals to the DMA that a data is available for read, this is the correct configuration for a channel that reads DCC0. 0xX1: DCC0 trigger is the image of STATUSB.DCC0D inverted, this signals to the DMA that DCC0 is ready for write, this is the correct configuration for a channel that writes DCC0 Bits 1:0 – LQOS[1:0] Latency Quality Of Service Defines the latency quality of service required when accessing the RAM: 0: Background Transfers 1: Bandwidth Sensitive 2: Latency sensitive 3: Latency critical SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 156 16.12.11 Boot Communication Channel 0 Name:  BCC0 Offset:  0x0020 Reset:  N/A Property:  - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 157 16.12.12 Boot Communication Channel 1 Name:  BCC1 Offset:  0x0024 Reset:  N/A Property:  - Bit 31 30 29 28 27 26 25 24 DATA[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DATA[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DATA[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DATA[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – DATA[31:0] Data Data register. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 158 16.12.13 CoreSight ROM Table Entry 0 Name:  ENTRY0 Offset:  0x1000 Reset:  0xXXXXX00X Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always reads as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 159 16.12.14 CoreSight ROM Table Entry 1 Name:  ENTRY1 Offset:  0x1004 Reset:  0xXXXXX00X Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 ADDOFF[19:12] Access R R R R R R R R Reset x x x x x x x x Bit 23 22 21 20 19 18 17 16 ADDOFF[11:4] Access R R R R R R R R Reset x x x x x x x x Bit 15 14 13 12 11 10 9 8 ADDOFF[3:0] Access R R R R Reset x x x x Bit 7 6 5 4 3 2 1 0 FMT EPRES Access R R Reset 1 x Bits 31:12 – ADDOFF[19:0] Address Offset The base address of the component, relative to the base address of this ROM table. Bit 1 – FMT Format Always read as '1', indicating a 32-bit ROM table. Bit 0 – EPRES Entry Present This bit indicates whether an entry is present at this location in the ROM table. This bit is set at power-up if the device is not protected indicating that the entry is not present. This bit is cleared at power-up if the device is not protected indicating that the entry is present. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 160 16.12.15 CoreSight ROM Table End Name:  END Offset:  0x1008 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 END[31:24] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 END[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 END[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 END[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:0 – END[31:0] End Marker Indicates the end of the CoreSight ROM table entries. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 161 16.12.16 CoreSight ROM Table Memory Type Name:  MEMTYPE Offset:  0x1FCC Reset:  0x0000000x Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SMEMP Access R Reset x Bit 0 – SMEMP System Memory Present This bit indicates whether system memory is present on the bus that connects to the ROM table. This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a debug adapter. This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a debug adapter. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 162 16.12.17 Peripheral Identification 4 Name:  PID4 Offset:  0x1FD0 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 FKBC[3:0] JEPCC[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – FKBC[3:0] 4KB Count These bits will always return zero when read, indicating that this debug component occupies one 4KB block. Bits 3:0 – JEPCC[3:0] JEP-106 Continuation Code These bits will always return zero when read. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 163 16.12.18 Peripheral Identification 0 Name:  PID0 Offset:  0x1FE0 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PARTNBL[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:0 – PARTNBL[7:0] Part Number Low These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 164 16.12.19 Peripheral Identification 1 Name:  PID1 Offset:  0x1FE4 Reset:  0x000000FC Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 JEPIDCL[3:0] PARTNBH[3:0] Access R R R R R R R R Reset 1 1 1 1 1 1 0 0 Bits 7:4 – JEPIDCL[3:0] Low part of the JEP-106 Identity Code These bits will always return 0xF when read (JEP-106 identity code is 0x1F). Bits 3:0 – PARTNBH[3:0] Part Number High These bits will always return 0xC when read, indicating that this device implements a DSU module instance. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 165 16.12.20 Peripheral Identification 2 Name:  PID2 Offset:  0x1FE8 Reset:  0x00000019 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVISION[3:0] JEPU JEPIDCH[2:0] Access R R R R R R R R Reset 0 0 0 1 1 0 0 1 Bits 7:4 – REVISION[3:0] Revision Number Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions. Bit 3 – JEPU JEP-106 Identity Code is used This bit will always return one when read, indicating that JEP-106 code is used. Bits 2:0 – JEPIDCH[2:0] JEP-106 Identity Code High These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is 0x1F). SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 166 16.12.21 Peripheral Identification 3 Name:  PID3 Offset:  0x1FEC Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 REVAND[3:0] CUSMOD[3:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 7:4 – REVAND[3:0] Revision Number These bits will always return 0x0 when read. Bits 3:0 – CUSMOD[3:0] ARM CUSMOD These bits will always return 0x0 when read. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 167 16.12.22 Component Identification 0 Name:  CID0 Offset:  0x1FF0 Reset:  0x0000000D Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB0[7:0] Access R R R R R R R R Reset 0 0 0 0 1 1 0 1 Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0 These bits will always return 0x0000000D when read. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 168 16.12.23 Component Identification 1 Name:  CID1 Offset:  0x1FF4 Reset:  0x00000010 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CCLASS[3:0] PREAMBLE[3:0] Access R R R R R R R R Reset 0 0 0 1 0 0 0 0 Bits 7:4 – CCLASS[3:0] Component Class These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the ARM Debug Interface v5 Architecture Specification at http://www.arm.com). Bits 3:0 – PREAMBLE[3:0] Preamble These bits will always return 0x00 when read. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 169 16.12.24 Component Identification 2 Name:  CID2 Offset:  0x1FF8 Reset:  0x00000005 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB2[7:0] Access R R R R R R R R Reset 0 0 0 0 0 1 0 1 Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2 These bits will always return 0x00000005 when read. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 170 16.12.25 Component Identification 3 Name:  CID3 Offset:  0x1FFC Reset:  0x000000B1 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 PREAMBLEB3[7:0] Access R R R R R R R R Reset 1 0 1 1 0 0 0 1 Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3 These bits will always return 0x000000B1 when read. SAM L10/L11 Family DSU - Device Service Unit © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 171 17. Clock System This chapter summarizes the clock distribution and terminology in the SAM L10/L11 device. This document will not explain every detail of its configuration, hence for in-depth details, refer to the respective peripherals descriptions and the Generic Clock documentation. 17.1 Clock Distribution Figure 17-1. Clock Distribution GCLK Generator 0 OSCCTRL GCLK GCLK Generator 1 GCLK Generator x Peripheral Channel 0 (FDPLL96M Ref) Peripheral Channel 1 (FDPLL96M 32k Ref) Peripheral z Peripheral 0 Syncronous Clock Controller MCLK AHB/APB System Clocks GCLK_MAIN OSC16M DFLLULP XOSC Generic Clocks OSCK32CTRL OSCULP32K XOSC32K FDPLL96M Peripheral Channel 3 GCLK_DPLL Peripheral Channel y GCLK_DPLL_32K GCLK_DPLL GCLK_DPLL_32K RTC CLK_RTC_OSC CLK_WDT_OSC Peripheral Channel 2 (DFLLULP Ref) WDT 32kHz 32kHz CLK_ULP32K EIC OPAMP GCLK_DFLLULP GCLK_DFLLULP CLK_ULP32K CLK_DFLLULP CLK_MAIN The SAM L10/L11 clock system consists of these features: • Clock sources, that is oscillators controlled by OSCCTRL and OSC32KCTRL – A clock source provides a time base that is used by other components, such as Generic Clock Generators. Example clock sources are the internal 16MHz oscillator (OSC16M), external crystal oscillator (XOSC) and the Fractional Digital Phase Locked Loop (FDPLL96M). • Generic Clock Controller (GCLK), which generates, controls and distributes the asynchronous clock consisting of: – Generic Clock Generators: These are programmable prescalers that can use any of the system clock sources as a time base. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is used by the Power Manager and the Main Clock (MCLK) module, which in turn generates synchronous clocks. – Generic Clocks: These are clock signals generated by Generic Clock Generators and output by the Peripheral Channels, and serve as clocks for the peripherals of the system. Multiple instances of a peripheral will typically have a separate Generic Clock for each instance. SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 172 Generic Clock 0 serves as the clock source for the FDPLL96M clock input (when multiplying another clock source). • Main Clock Controller (MCLK) – The MCLK generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks. The figure below illustrates an example, where SERCOM0 is clocked by the FDPLL96M in Open Loop mode. The FDPLL96M is enabled, the Generic Clock Generator 1 uses the FDPLL96M as its clock source and feeds into Peripheral Channel 11. The Generic Clock 10, also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK. Figure 17-2. Example of SERCOM Clock OSCCTRL FDPLL96M Generic Clock Generator 1 Peripheral Channel 11 SERCOM 0 Syncronous Clock Controller MCLK CLK_SERCOM0_APB GCLK_SERCOM0_CORE GCLK To customize the clock distribution, refer to these registers and bit fields: • The source oscillator for a generic clock generator 'n' is selected by writing to the Source bit field in the Generator Control n register (GCLK.GENCTRLn.SRC). • A Peripheral Channel m can be configured to use a specific Generic Clock Generator by writing to the Generic Clock Generator bit field in the respective Peripheral Channel m register (GCLK.PCHCTRLm.GEN) • The Peripheral Channel number, m, is fixed for a given peripheral. See the Mapping table in the description of GCLK.PCHCTRLm. • The AHB clocks are enabled and disabled by writing to the respective bit in the AHB Mask register (MCLK.AHBMASK). • The APB clocks are enabled and disabled by writing to the respective bit in the APB x Mask registers (MCLK.APBxMASK). 17.2 Synchronous and Asynchronous Clocks As the CPU and the peripherals can be in different clock domains, that is, they are clocked from different clock sources and with different clock speeds, some peripheral accesses by the CPU need to be synchronized. In this case the peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a sync operation is in progress. For a general description, see 17.3 Register Synchronization. Some peripherals have specific properties described in their individual “Synchronization” sub-sections. SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 173 In the data sheet, references to Synchronous Clocks are referring to the CPU and bus clocks (MCLK), while asynchronous clocks are generated by the Generic Clock Controller (GCLK). 17.3 Register Synchronization 17.3.1 Overview All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK). Communication between these clock domains must be synchronized. This mechanism is implemented in hardware, so the synchronization process takes place even if the peripheral generic clock is running from the same clock source and on the same frequency as the bus interface. All registers in the bus interface are accessible without synchronization. All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are synchronized when read. Each individual register description will have the properties "Read-Synchronized" and/or "WriteSynchronized" if a register is synchronized. As shown in the figure below, each register that requires synchronization has its individual synchronizer and its individual synchronization status bit in the Synchronization Busy register (SYNCBUSY). Note:  For registers requiring both read- and write-synchronization, the corresponding bit in SYNCBUSY is shared. SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 174 Figure 17-3. Register Synchronization Overview Synchronous Domain (CLK_APB) Asynchronous Domain (GCLK ) Non Sync’d reg Periperal Bus Write-Sync’d reg SYNCBUSY R/W-Sync’d reg Sync Sync Read-Sync’d reg Sync Write-only register Read-only register R/W register Write-Sync’d reg Sync R/W register Non Sync’d reg Read-only register Sync INTFLAG 17.3.2 General Write Synchronization Write-Synchronization is triggered by writing to a register in the peripheral clock domain (GCLK). The respective bit in the Synchronization Busy register (SYNCBUSY) will be set when the writesynchronization starts and cleared when the write-synchronization is complete. Refer also to17.3.7 Synchronization Delay. When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded, and an error will be reported though the Peripheral Access Controller (PAC). Example: REGA, REGB are 8-bit core registers. REGC is a 16-bit core register. Offset Register 0x00 REGA 0x01 REGB 0x02 REGC 0x03 Synchronization is per register, so multiple registers can be synchronized in parallel. Consequently, after REGA (8-bit access) was written, REGB (8-bit access) can be written immediately without error. SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 175 REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two consecutive 8-bit accesses without waiting for synchronization, the second write attempt will be discarded and an error is generated through the PAC. A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be updated at different times because of independent write synchronization. 17.3.3 General Read Synchronization Read-synchronized registers are synchronized each time the register value is updated but the corresponding SYNCBUSY bits are not set. Reading a read-synchronized register does not start a new synchronization, it returns the last synchronized value. Note:  The corresponding bits in SYNCBUSY will automatically be set when the device wakes up from sleep because read-synchronized registers need to be synchronized. Therefore reading a readsynchronized register before its corresponding SYNCBUSY bit is cleared will return the last synchronized value before sleep mode. Moreover, if a register is also write-synchronized, any write access while the SYNCBUSY bit is set will be discarded and generate an error. 17.3.4 Completion of Synchronization In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY or use the Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be set when all ongoing synchronizations are complete, i.e. when all bits in SYNCBUSY are '0'. 17.3.5 Write Synchronization for CTRLA.ENABLE Setting the Enable bit in a module's Control A register (CTRLA.ENABLE) will trigger write-synchronization and set SYNCBUSY.ENABLE. CTRLA.ENABLE will read its new value immediately after being written. SYNCBUSY.ENABLE will be cleared by hardware when the operation is complete. The Synchronization Ready interrupt (if available) cannot be used to enable write-synchronization. 17.3.6 Write-Synchronization for Software Reset Bit Setting the Software Reset bit in CTRLA (CTRLA.SWRST=1) will trigger write-synchronization and set SYNCBUSY.SWRST. When writing a ‘1’ to the CTRLA.SWRST bit it will immediately read as ‘1’. CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a '0' to the CTRL.SWRST bit has no effect. The Ready interrupt (if available) cannot be used for Software Reset write-synchronization. Note:  Not all peripherals have the SWRST bit in the respective CTRLA register. 17.3.7 Synchronization Delay The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of: 5×PGCLK + 2×PAPB < D < 6×PGCLK + 3×PAPB Where PGCLK is the period of the generic clock and PAPB is the period of the peripheral bus clock. A normal peripheral bus register access duration is 2×PAPB. SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 176 17.4 Enabling a Peripheral In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs to be configured: • A running Clock Source • A clock from the Generic Clock Generator must be configured to use one of the running Clock Sources, and the Generator must be enabled. • The Peripheral Channel that provides the Generic Clock signal to the peripheral must be configured to use a running Generic Clock Generator, and the Generic Clock must be enabled. • The user interface of the peripheral needs to be unmasked in the Main Clock Controller (MCLK). If this is not done the peripheral registers will read all '0's and any writing attempts to the peripheral will be discarded. 17.5 On Demand Clock Requests Figure 17-4. Clock Request Routing FDPLL96M Generic Clock Generator Clock request Generic Clock Periph. Channel Clock request Peripheral Clock request ENABLE RUNSTDBY ONDEMAND CLKEN RUNSTDBY ENABLE RUNSTDBY GENEN All clock sources in the system can be run in an on-demand mode: the clock source is in a stopped state unless a peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the clock source is no longer needed and no peripheral has an active request, the clock source will be stopped until requested again. The clock request can reach the clock source only if the peripheral, the generic clock and the clock from the Generic Clock Generator in-between are enabled. The time taken from a clock request being asserted to the clock source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the Generic Clock Generator. The total startup time Tstart from a clock request until the clock is available for the peripheral is between: Tstart_max = Clock source startup time + 2 × clock source periods + 2 × divided clock source periods Tstart_min = Clock source startup time + 1 × clock source period + 1 × divided clock source period The time between the last active clock request stopped and the clock is shut down, Tstop, is between: Tstop_min = 1 × divided clock source period + 1 × clock source period Tstop_max = 2 × divided clock source periods + 2 × clock source periods The On-Demand function can be disabled individually for each clock source by clearing the ONDEMAND bit located in each clock source controller. Consequently, the clock will always run whatever the clock request status is. This has the effect of removing the clock source startup time at the cost of power consumption. The clock request mechanism can be configured to work in standby mode by setting the RUNSDTBY bits of the modules (see Figure 17-4). SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 177 17.6 Power Consumption vs. Speed When targeting for either a low-power or a fast acting system, some considerations have to be taken into account due to the nature of the asynchronous clocking of the peripherals: If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed, and will take longer with a slower peripheral clock. This will cause worse response times and longer synchronization delays. 17.7 Clocks after Reset On any Reset the synchronous clocks start to their initial state: • OSC16M is enabled and configured to run at 4MHz • Generic Clock Generator 0 uses OSC16M as source and generates GCLK_MAIN and CLK_MAIN • CPU and BUS clocks are undivided On a Power-on Reset, the 32KHz clock sources are reset and the GCLK module starts to its initial state: • All Generic Clock Generators are disabled except Generator 0 • All Peripheral Channels in GCLK are disabled. On a User Reset the GCLK module starts to its initial state, except for: • Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset SAM L10/L11 Family Clock System © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 178 18. GCLK - Generic Clock Controller 18.1 Overview Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic Clock controller (GCLK) features 5 Generic Clock Generators 0..4 that can provide a wide range of clock frequencies. Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be divided. The outputs from the Generators are used as sources for the Peripheral Channels, which provide the Generic Clock (GCLK_PERIPH) to the peripheral modules, as shown in Figure 18-2. The number of Peripheral Clocks depends on how many peripherals the device has. Note:  The Generator 0 is always the direct source of the GCLK_MAIN signal. 18.2 Features • Provides a device-defined, configurable number of Peripheral Channel clocks • Wide frequency range: – Various clock sources – Embedded dividers 18.3 Block Diagram The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in Device Clocking Diagram. Figure 18-1. Device Clocking Diagram GCLK_IO Generic Clock Generator OSC16M OSCCTRL Clock Divider & Masker Clock Gate Peripheral Channel GCLK_PERIPH PERIPHERAL GENERIC CLOCK CONTROLLER MCLK GCLK_MAIN DFLLULP XOSC OSC32CTRL OSCULP32K XOSC32K FDPLL96M CLK_DFLLULP CLK_MAIN The GCLK block diagram is shown below: SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 179 Figure 18-2. Generic Clock Controller Block Diagram Generic Clock Generator 0 GCLK_IO[0] (I/O input) Clock Divider & Masker Clock Sources GCLKGEN[0] GCLK_IO[1] (I/O input) GCLKGEN[1] GCLK_IO[n] (I/O input) GCLKGEN[n] Clock Gate Peripheral Channel 0 GCLK_PERIPH[0] Clock Gate Peripheral Channel 1 Clock Gate Peripheral Channel n GCLKGEN[n:0] GCLK_MAIN GCLK_IO[1] (I/O output) GCLK_IO[0] (I/O output) GCLK_IO[n] (I/O output) Generic Clock Generator 1 Clock Divider & Masker Generic Clock Generator n Clock Divider & Masker GCLK_PERIPH[1] GCLK_PERIPH[n] 18.4 Signal Description Table 18-1. GCLK Signal Description Signal Name Type Description GCLK_IO[4:0] Digital I/O Clock source for Generators when input Generic Clock signal when output Note:  One signal can be mapped on several pins. 18.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 18.5.1 I/O Lines Using the GCLK I/O lines requires the I/O pins to be configured. Related Links 32. PORT - I/O Pin Controller 18.5.2 Power Management The GCLK can operate in sleep modes, if required. Refer to the sleep mode description in the Power Manager (PM) section. Related Links 22. PM – Power Manager 18.5.3 Clocks The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 180 Related Links 19.6.2.6 Peripheral Clock Masking 24. OSC32KCTRL – 32KHz Oscillators Controller 18.5.4 DMA Not applicable. 18.5.5 Interrupts Not applicable. 18.5.6 Events Not applicable. 18.5.7 Debug Operation When the CPU is halted in debug mode the GCLK continues normal operation. If the GCLK is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 18.5.8 Register Access Protection All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC). Note:  Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. Related Links 15. PAC - Peripheral Access Controller 18.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 18.5.10 Analog Connections Not applicable. 18.6 Functional Description 18.6.1 Principle of Operation The GCLK module is comprised of five Generic Clock Generators (Generators) sourcing up to 64 Peripheral Channels and the Main Clock signal CLK_MAIN. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 181 A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator. A generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal (GCLK_PERIPH) to the peripherals. 18.6.2 Basic Operation 18.6.2.1 Initialization Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be configured as outlined by the following steps: 1. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set (GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register (GENCTRLn). 2. The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control register (PCHCTRLm). The Generator used as the source for the Peripheral Clock must be written to the GEN bit field in the Peripheral Channel Control register (PCHCTRLm.GEN). Note:  Each Generator n is configured by one dedicated register GENCTRLn. Note:  Each Peripheral Channel m is configured by one dedicated register PCHCTRLm. 18.6.2.2 Enabling, Disabling, and Resetting The GCLK module has no enable/disable bit to enable or disable the whole module. The GCLK is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST) to 1. All registers in the GCLK will be reset to their initial state, except for Peripheral Channels and associated Generators that have their Write Lock bit set to 1 (PCHCTRLm.WRTLOCK). For further details, refer to 18.6.3.4 Configuration Lock. 18.6.2.3 Generic Clock Generator Each Generator (GCLK_GEN) can be set to run from one of eight different clock sources except GCLK_GEN[1], which can be set to run from one of seven sources. GCLK_GEN[1] is the only Generator that can be selected as source to others Generators. Each generator GCLK_GEN[x] can be connected to one specific pin GCLK_IO[x]. A pin GCLK_IO[x] can be set either to act as source to GCLK_GEN[x] or to output the clock signal generated by GCLK_GEN[x]. The selected source can be divided. Each Generator can be enabled or disabled independently. Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each Generator output is allocated to one or several Peripherals. GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the Main Clock Controller. Refer to the Main Clock Controller description for details on the synchronous clock generation. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 182 Figure 18-3. Generic Clock Generator Related Links 19. MCLK – Main Clock 18.6.2.4 Enabling a Generator A Generator is enabled by writing a '1' to the Generator Enable bit in the Generator Control register (GENCTRLn.GENEN=1). 18.6.2.5 Disabling a Generator A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN=0, the GCLK_GEN[n] clock is disabled and gated. 18.6.2.6 Selecting a Clock Source for the Generator Each Generator can individually select a clock source by setting the Source Select bit group in the Generator Control register (GENCTRLn.SRC). Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source B is not ready, the Generator will continue using clock source A. As soon as source B is ready, the Generator will switch to it. During the switching operation, the Generator maintains clock requests to both clock sources A and B, and will release source A as soon as the switch is done. The according bit in SYNCBUSY register (SYNCBUSY.GENCTRLn) will remain '1' until the switch operation is completed. The available clock sources are device dependent (usually the oscillators, RC oscillators, DPLL, and DFLLULP). Only Generator 1 can be used as a common source for all other generators. 18.6.2.7 Changing the Clock Frequency The selected source for a Generator can be divided by writing a division value in the Division Factor bit field of the Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is depending on the Divide Selection bit (GENCTRLn.DIVSEL). If GENCTRLn.DIVSEL=0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided. Note:  The number of available DIV bits may vary from Generator to Generator. 18.6.2.8 Duty Cycle When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Setting the Improve Duty Cycle bit of the Generator Control register (GENCTRLn.IDC) will result in a 50/50 duty cycle. 18.6.2.9 External Clock The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO). SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 183 If the Output Enable bit in the Generator Control register is set (GENCTRLn.OE = 1) and the generator is enabled (GENCTRLn.GENEN=1), the Generator requests its clock source and the GCLK_GEN clock is output to an I/O pin. Note:  The I/O pin (GCLK/IO[n]) must first be configured as output by writing the corresponding PORT registers. If GENCTRLn.OE is 0, the according I/O pin is set to an Output Off Value, which is selected by GENCTRLn.OOV: If GENCTRLn.OOV is '0', the output clock will be low. If this bit is '1', the output clock will be high. In Standby mode, if the clock is output (GENCTRLn.OE=1), the clock on the I/O pin is frozen to the OOV value if the Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero. Note:  With GENCTRLn.OE=1 and RUNSTDBY=0, entering the Standby mode can take longer due to a clock source dependent delay between turning off Power Domain PDSW. The maximum delay can be equal to the clock source period multiplied by the division factor. If GENCTRLn.RUNSTDBY is '1', the GCLKGEN clock is kept running and output to the I/O pin. Related Links 22.6.3.5 Power Domain Controller 18.6.3 Peripheral Clock Figure 18-4. Peripheral Clock 18.6.3.1 Enabling a Peripheral Clock Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register (PCHCTRL.GEN). Any available Generator can be selected as clock source for each Peripheral Channel. When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is complete. 18.6.3.2 Disabling a Peripheral Clock A Peripheral Clock is disabled by writing PCHCTRLm.CHEN=0. The PCHCTRLm.CHEN bit must be synchronized to the Generic Clock domain. PCHCTRLm.CHEN will stay in its previous state until the synchronization is complete. The Peripheral Clock is gated when disabled. Related Links 18.8.4 PCHCTRLm SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 184 18.6.3.3 Selecting the Clock Source for a Peripheral When changing a peripheral clock source by writing to PCHCTRLm.GEN, the peripheral clock must be disabled before re-enabling it with the new clock source setting. This prevents glitches during the transition: 1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN=0 2. Assert that PCHCTRLm.CHEN reads '0' 3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN 4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN=1 Related Links 18.8.4 PCHCTRLm 18.6.3.4 Configuration Lock The peripheral clock configuration can be locked for further write accesses by setting the Write Lock bit in the Peripheral Channel Control register PCHCTRLm.WRTLOCK=1). All writing to the PCHCTRLm register will be ignored. It can only be unlocked by a Power Reset. The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn register is locked, and can be unlocked only by a Power Reset. There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It is reset by any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can not unlock the registers. In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to '1' the peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is enabled again. Then, the PCHCTRLm.CHEN are set to '1' again. Related Links 18.8.1 CTRLA 18.6.4 Additional Features 18.6.4.1 Peripheral Clock Enable after Reset The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a Reset. That means that the configuration of the Generators and Peripheral Channels after Reset is device-dependent. Refer to GENCTRLn.SRC for details on GENCTRLn reset. Refer to PCHCTRLm.SRC for details on PCHCTRLm reset. 18.6.5 Sleep Mode Operation 18.6.5.1 SleepWalking The GCLK module supports the SleepWalking feature. If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to execute a process must request it from the Generic Clock Controller. The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and Peripheral Channel stages successively, and delivers the clock to the peripheral. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 185 The RUNSTDBY bit in the Generator Control register controls clock output to pin during standby sleep mode. If the bit is cleared, the Generator output is not available on pin. When set, the GCLK can continuously output the generator output to GCLK_IO. Refer to 18.6.2.9 External Clock for details. Related Links 22. PM – Power Manager 18.6.5.2 Minimize Power Consumption in Standby The following table identifies when a Clock Generator is off in Standby Mode, minimizing the power consumption: Table 18-2. Clock Generator n Activity in Standby Mode Request for Clock n present GENCTRLn.RUNSTDBY GENCTRLn.OE Clock Generator n yes - - active no 1 1 active no 1 0 OFF no 0 1 OFF no 0 0 OFF 18.6.5.3 Entering Standby Mode There may occur a delay when the device is put into Standby, until the power is turned off. This delay is caused by running Clock Generators: if the Run in Standby bit in the Generator Control register (GENCTRLn.RUNSTDBY) is '0', GCLK must verify that the clock is turned of properly. The duration of this verification is frequency-dependent. Related Links 22. PM – Power Manager 18.6.6 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free internal operation. Note that changing the bit value under ongoing synchronization will not generate an error. The following registers are synchronized when written: • Generic Clock Generator Control register (GENCTRLn) • Control A register (CTRLA) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Related Links 18.8.1 CTRLA 18.8.4 PCHCTRLm SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 186 18.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 SWRST 0x01 ... 0x03 Reserved 0x04 SYNCBUSY 7:0 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST 15:8 23:16 31:24 0x08 ... 0x1F Reserved 0x20 GENCTRL0 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x24 GENCTRL1 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x28 GENCTRL2 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x2C GENCTRL3 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x30 GENCTRL4 7:0 SRC[4:0] 15:8 RUNSTDBY DIVSEL OE OOV IDC GENEN 23:16 DIV[7:0] 31:24 DIV[15:8] 0x34 ... 0x7F Reserved 0x80 PCHCTRL0 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0x84 PCHCTRL1 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0x88 PCHCTRL2 7:0 WRTLOCK CHEN GEN[2:0] SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 187 Offset Name Bit Pos. 15:8 23:16 31:24 0x8C PCHCTRL3 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0x90 PCHCTRL4 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0x94 PCHCTRL5 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0x98 PCHCTRL6 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0x9C PCHCTRL7 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xA0 PCHCTRL8 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xA4 PCHCTRL9 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xA8 PCHCTRL10 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xAC PCHCTRL11 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xB0 PCHCTRL12 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xB4 PCHCTRL13 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 188 Offset Name Bit Pos. 31:24 0xB8 PCHCTRL14 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xBC PCHCTRL15 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xC0 PCHCTRL16 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xC4 PCHCTRL17 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xC8 PCHCTRL18 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xCC PCHCTRL19 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 0xD0 PCHCTRL20 7:0 WRTLOCK CHEN GEN[2:0] 15:8 23:16 31:24 18.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 18.5.8 Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 18.6.6 Synchronization. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 189 • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 190 18.8.1 Control A Name:  CTRLA Offset:  0x00 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SWRST Access R/W Reset 0 Bit 0 – SWRST Software Reset Writing a zero to this bit has no effect. Setting this bit to 1 will reset all registers in the GCLK to their initial state after a Power Reset, except for generic clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to 1. Refer to GENCTRL Reset Value for details on GENCTRL register reset. Refer to PCHCTRL Reset Value for details on PCHCTRL register reset. Due to synchronization, there is a waiting period between setting CTRLA.SWRST and a completed Reset. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete. Value Description 0 There is no Reset operation ongoing. 1 A Reset operation is ongoing. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 191 18.8.2 Synchronization Busy Name:  SYNCBUSY Offset:  0x04 Reset:  0x00000000 Property:  – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 GENCTRL4 GENCTRL3 GENCTRL2 GENCTRL1 GENCTRL0 SWRST Access R R R R R R Reset 0 0 0 0 0 0 Bits 2, 3, 4, 5, 6 – GENCTRL Generator Control n Synchronization Busy This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is complete, or when clock switching operation is complete. This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is started. Bit 0 – SWRST Software Reset Synchronization Busy This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete. This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 192 18.8.3 Generator Control Name:  GENCTRLn Offset:  0x20 + n*0x04 [n=0..4] Reset:  0x00000105 Property:  PAC Write-Protection, Write-Synchronized GENCTRLn controls the settings of Generic Generator n (n=0..4). The reset value is 0x00000105 for Generator n=0, else 0x00000000 Bit 31 30 29 28 27 26 25 24 DIV[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RUNSTDBY DIVSEL OE OOV IDC GENEN Access Reset 0 0 0 0 0 1 Bit 7 6 5 4 3 2 1 0 SRC[4:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bits 31:16 – DIV[15:0] Division Factor These bits represent a division value for the corresponding Generator. The actual division factor is dependent on the state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in this table. Written bits outside of the specified range will be ignored. Table 18-3. Division Factor Bits Generic Clock Generator Division Factor Bits Generator 0 8 division factor bits - DIV[7:0] Generator 1 16 division factor bits - DIV[15:0] Generator 2 - 4 8 division factor bits - DIV[7:0] Bit 13 – RUNSTDBY Run in Standby This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral requires the clock. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 193 Value Description 0 The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be dependent on the setting in GENCTRL.OOV. 1 The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode. Bit 12 – DIVSEL Divide Selection This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1. Value Description 0 The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV. 1 The Generator clock frequency equals the clock source frequency divided by 2^(N+1), where N is the Division Factor Bits for the selected generator (refer to GENCTRLn.DIV). Bit 11 – OE Output Enable This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. Value Description 0 No Generator clock signal on pin GCLK_IO. 1 The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is selected as a generator source in the GENCTRLn.SRC bit field. Bit 10 – OOV Output Off Value This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field. Value Description 0 The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero. 1 The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero. Bit 9 – IDC Improve Duty Cycle This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors. Value Description 0 Generator output clock duty cycle is not balanced to 50/50 for odd division factors. 1 Generator output clock duty cycle is 50/50. Bit 8 – GENEN Generator Enable This bit is used to enable and disable the Generator. Value Description 0 Generator is disabled. 1 Generator is enabled. Bits 4:0 – SRC[4:0] Generator Clock Source Selection These bits select the Generator clock source, as shown in this table. SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 194 Table 18-4. Generator Clock Source Selection Value Name Description 0x00 XOSC XOSC oscillator output 0x01 GCLK_IN Generator input pad (GCLK_IO) 0x02 GCLK_GEN1 Generic clock generator 1 output 0x03 OSCULP32K OSCULP32K oscillator output 0x04 XOSC32K XOSC32K oscillator output 0x05 OSC16M OSC16M oscillator output 0x06 DFLLULP DFLLULP ultra low power output 0x07 FDPLL96M FDPLL96M output 0x08-0x1F Reserved Reserved for future use A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table below. Table 18-5. GENCTRLn Reset Value after a Power Reset GCLK Generator Reset Value after a Power Reset 0 0x00000105 others 0x00000000 A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below. Table 18-6. GENCTRLn Reset Value after a User Reset GCLK Generator Reset Value after a User Reset 0 0x00000105 others No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK=1 else 0x00000000 Related Links 18.8.4 PCHCTRLm SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 195 18.8.4 Peripheral Channel Control Name:  PCHCTRLm Offset:  0x80 + m*0x04 [m=0..20] Reset:  0x00000000 Property:  PAC Write-Protection PCHTRLm controls the settings of Peripheral Channel number m (m=0..20). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 WRTLOCK CHEN GEN[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 – WRTLOCK Write Lock After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be unlocked by a Power Reset. Note that Generator 0 cannot be locked. Value Description 0 The Peripheral Channel register and the associated Generator register are not locked 1 The Peripheral Channel register and the associated Generator register are locked Bit 6 – CHEN Channel Enable This bit is used to enable and disable a Peripheral Channel. Value Description 0 The Peripheral Channel is disabled 1 The Peripheral Channel is enabled Bits 2:0 – GEN[2:0] Generator Selection This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below: SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 196 Table 18-7. Generator Selection Value Description 0x0 Generic Clock Generator 0 0x1 Generic Clock Generator 1 0x2 Generic Clock Generator 2 0x3 Generic Clock Generator 3 0x4 Generic Clock Generator 4 0x5 Generic Clock Generator 5 0x6 Generic Clock Generator 6 0x7 Generic Clock Generator 7 0xA Generic Clock Generator 10 0xB Generic Clock Generator 11 Table 18-8. Reset Value after a User Reset or a Power Reset Reset PCHCTRLm.GEN PCHCTRLm.CHEN PCHCTRLm.WRTLOCK Power Reset 0x0 0x0 0x0 User Reset If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change If WRTLOCK = 0 : 0x0 If WRTLOCK = 1: no change No change A Power Reset will reset all the PCHCTRLm registers. A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged. The PCHCTRL register Reset values are shown in the table below, PCHCTRLm Mapping. Table 18-9. PCHCTRLm Mapping index(m) Name Description 0 GCLK_DPLL FDPLL96M input clock source for reference 1 GCLK_DPLL_32K FDPLL96M 32 kHz clock for FDPLL96M internal clock timer 2 GCLK_DFLLULP DFLLULP clock for DFLLULP 3 GCLK_EIC EIC 4 GCLK_FREQM_MSR FREQM Measure 5 GCLK_FREQM_REF FREQM Reference 6 GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0 7 GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1 8 GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2 SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 197 index(m) Name Description 9 GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3 10 GCLK_SERCOM[0,1,2]_SLOW SERCOM[0,1,2]_SLOW 11 GCLK_SERCOM0_CORE SERCOM0_CORE 12 GCLK_SERCOM1_CORE SERCOM1_CORE 13 GCLK_SERCOM2_CORE SERCOM2_CORE 14 GCLK_TC0, GCLK_TC1 TC0,TC1 15 GCLK_TC2 TC2 16 GCLK_ADC ADC 17 GCLK_AC AC 18 GCLK_DAC DAC 19 GCLK_PTC PTC 20 GCLK_CCL CCL SAM L10/L11 Family GCLK - Generic Clock Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 198 19. MCLK – Main Clock 19.1 Overview The Main Clock (MCLK) controls the synchronous clock generation of the device. Using a clock provided by the Generic Clock Module (GCLK_MAIN) or the DFLLULP (CLK_DFLLULP), the Main Clock Controller provides synchronous system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The synchronous system clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU performance or vice versa. In addition, the clock can be masked for individual modules, enabling the user to minimize power consumption. 19.2 Features • Generates CPU, AHB, and APB system clocks – Clock source and division factor from GCLK – Clock prescaler with 1x to 128x division • Safe run-time clock switching from GCLK • Module-level clock gating through maskable peripheral clocks 19.3 Block Diagram Figure 19-1. MCLK Block Diagram MAIN CLOCK CONTROLLER CPU GCLK GCLK_MAIN PERIPHERALS CLK_APBx CLK_AHBx CLK_CPU DFLLULP CLK_DFLLULP CLK_MAIN CKSEL 19.4 Signal Description Not applicable. 19.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 19.5.1 I/O Lines Not applicable. 19.5.2 Power Management The MCLK will operate in all sleep modes if a synchronous clock is required in these modes. Related Links SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 199 22. PM – Power Manager 19.5.3 Clocks The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is disabled, it can only be re-enabled by a reset. The Generic Clock GCLK_MAIN or the DFLLULP Clock CLK_DFLLULP is required to generate the Main Clocks. GCLK_MAIN is configured in the Generic Clock Controller, and can be re-configured by the user if needed. CLK_DFLLULP is configured in the Oscillators Controller (OSCCTRL). Related Links 18. GCLK - Generic Clock Controller 19.6.2.6 Peripheral Clock Masking 19.5.3.1 Main Clock The main clock CLK_MAIN is the common source for the synchronous clocks. This is fed into the common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHBx, and APBx modules. 19.5.3.2 CPU Clock The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions. 19.5.3.3 APBx and AHBx Clock The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock source used by modules requiring a clock on the APBx and the AHBx bus. These clocks are always synchronous to the CPU clock, and can run even when the CPU clock is turned off in sleep mode. A clock gater is inserted after the common APB clock to gate any APBx clock of a module on APBx bus, as well as the AHBx clock. 19.5.3.4 Clock Domains The device has these synchronous clock domains: • CPU synchronous clock domain (CPU Clock Domain). Frequency is fCPU. See also the related links for the clock domain partitioning. Related Links 19.6.2.6 Peripheral Clock Masking 19.5.4 DMA Not applicable. 19.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the MCLK interrupt requires the Interrupt Controller to be configured first. 19.5.6 Events Not applicable. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 200 19.5.7 Debug Operation When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the clocks generated from the MCLK are kept running to allow the debugger accessing any module. As a consequence, power measurements are incorrect in debug mode. 19.5.8 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: • Interrupt Flag register (INTFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 15. PAC - Peripheral Access Controller 19.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 19.5.10 Analog Connections Not applicable. 19.6 Functional Description 19.6.1 Principle of Operation The CLK_MAIN clock signal from the GCLK module or the DFLLULP is the source for the main clock, which in turn is the common root for the synchronous clocks for the CPU, APBx, and AHBx modules. The CLK_MAIN is divided by an 8-bit prescaler. Each of the derived clocks can run from any divided or undivided main clock, ensuring synchronous clock sources for each clock domain. The clock domain (CPU) can be changed on the fly to respond to variable load in the application. The clocks for each module in a clock domain can be masked individually to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can be turned off. 19.6.2 Basic Operation 19.6.2.1 Initialization After a Reset, the default clock source of the CLK_MAIN clock (GCLK_MAIN) is started and calibrated before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any prescaler division. By default, only the necessary clocks are enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 201 Related Links 19.6.2.6 Peripheral Clock Masking 19.6.2.2 Enabling, Disabling, and Resetting The MCLK module is always enabled and cannot be reset. 19.6.2.3 Selecting the Main Clock Source Refer to the Generic Clock Controller description for details on how to configure the clock source of the GCLK_MAIN clock. Refer to the Oscillators Controller (OSCCTRL) description for details on how to configure the clock source of the CLK_DFLLULP clock. Related Links 18. GCLK - Generic Clock Controller 19.6.2.4 Selecting the Synchronous Clock Division Ratio The main clock CLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock domain by writing the Division (DIV) bits in the CPU Clock Division register CPUDIV, resulting in a CPU clock domain frequency determined by this equation: = ܷܲܥ݂ ݂݉ܽ݅݊ ܸܫܦܷܲܥ If the application attempts to write forbidden values in CPUDIV register, registers are written but these bad values are not used and a violation is reported to the PAC module. Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a new clock setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 202 Figure 19-2. Synchronous Clock Selection and Prescaler Prescaler Sleep Controller Sleep mode CLK_AHBx Clock gate CLK_APBx Clock gate APBxDIV AHBxDIV clk_ahb_ip0 clk_ahb_ip1 clk_ahb_ipn clk_apb_ip0 clk_apb_ip1 clk_apb_ipn APBxMASK AHBMASK CPUDIV CLK_CPU GCLK Clock gate Clock gate Clock gate Clock gate Clock gate CLK_MAIN DFLLULP CKSEL Related Links 15. PAC - Peripheral Access Controller 19.6.2.5 Clock Ready Flag There is a slight delay between writing to CPUDIV until the new clock settings become effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will return zero when read. If CKRDY in the INTENSET register is set to '1', the Clock Ready interrupt will be triggered when the new clock setting is effective. The clock settings (CLKCFG) must not be re-written while INTFLAG. CKRDY reads '0'. The system may become unstable or hang, and a violation is reported to the PAC module. Related Links 15. PAC - Peripheral Access Controller 19.6.2.6 Peripheral Clock Masking It is possible to disable/enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock Mask registers (APBxMASK) to '0'/'1'. The default state of the peripheral clocks is shown here. Table 19-1. Peripheral Clock Default State CPU Clock Domain Peripheral Clock Default State CLK_AC_APB Enabled CLK_ADC_APB Enabled SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 203 CPU Clock Domain Peripheral Clock Default State CLK_BRIDGE_A_AHB Enabled CLK_BRIDGE_B_AHB Enabled CLK_BRIDGE_C_AHB Enabled CLK_CCL_APB Enabled CLK_DAC_APB Enabled CLK_DMAC_AHB Enabled CLK_DSU_AHB Enabled CLK_DSU_APB Enabled CLK_EIC_APB Enabled CLK_EVSYS_APB Enabled CLK_FREQM_APB Enabled CLK_GCLK_APB Enabled CLK_HMATRIXHS_AHB Enabled CLK_MCLK_APB Enabled CLK_NVMCTRL_AHB Enabled CLK_NVMCTRL_APB Enabled CLK_OPAMP_APB Enabled CLK_OSCCTRL_APB Enabled CLK_OSC32CTRL_APB Enabled CLK_PAC_AHB Enabled CLK_PAC_APB Enabled CLK_PORT_APB Enabled CLK_PM_APB Enabled CLK_PTC_APB Enabled CLK_RSTC_APB Enabled CLK_RTC_APB Enabled CLK_SERCOM0_APB Enabled CLK_SERCOM1_APB Enabled CLK_SERCOM2_APB(1) Enabled CLK_SUPC_APB Enabled CLK_TC0_APB Enabled CLK_TC1_APB Enabled CLK_TC2_APB Enabled CLK_TRAM_AHB Enabled CLK_WDT_APB Enabled When the APB clock is not provided to a module, its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to '1'. A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several mask bits. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 204 Note that clocks should only be switched off if it is certain that the module will not be used: Switching off the clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash Memory. Switching off the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 19.6.3 DMA Operation Not applicable. 19.6.4 Interrupts The peripheral has the following interrupt sources: • Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wakeup source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled individually by writing a '1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding clearing bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources.If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. Related Links 22. PM – Power Manager 22.6.3.3 Sleep Mode Controller 19.6.5 Events Not applicable. 19.6.6 Sleep Mode Operation In all IDLE sleep modes, the MCLK is still running on the selected main clock. In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 205 19.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 CKSEL 0x01 INTENCLR 7:0 CKRDY 0x02 INTENSET 7:0 CKRDY 0x03 INTFLAG 7:0 CKRDY 0x04 Reserved 0x05 CPUDIV 7:0 CPUDIV[7:0] 0x06 ... 0x0F Reserved 0x10 AHBMASK 7:0 NVMCTRL PAC Reserved DSU DMAC APBC APBB APBA 15:8 TRAM Reserved Reserved Reserved Reserved 23:16 31:24 0x14 APBAMASK 7:0 GCLK SUPC OSC32KCTR L OSCCTRL RSTC MCLK PM PAC 15:8 Reserved AC PORT FREQM EIC RTC WDT 23:16 31:24 0x18 APBBMASK 7:0 HMATRIXHS NVMCTRL DSU IDAU 15:8 23:16 31:24 0x1C APBCMASK 7:0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS 15:8 OPAMP CCL TRNG PTC DAC 23:16 31:24 19.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers can be write-protected optionally by the Peripheral Access Controller (PAC). This is denoted by the property "PAC Write-Protection" in each individual register description. Refer to the 19.5.8 Register Access Protection for details. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 206 Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 207 19.8.1 Control A Name:  CTRLA Offset:  0x00 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CKSEL Access R/W Reset 0 Bit 2 – CKSEL Main Clock Select Value Description 0 The GCLKMAIN clock is selected for the main clock. 1 The DFLLULP clock is selected for the main clock. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 208 19.8.2 Interrupt Enable Clear Name:  INTENCLR Offset:  0x01 Reset:  0x00 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request. Value Description 0 The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt Flag is set. 1 The Clock Ready interrupt is disabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 209 19.8.3 Interrupt Enable Set Name:  INTENSET Offset:  0x02 Reset:  0x00 Property:  PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 0 Bit 0 – CKRDY Clock Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt. Value Description 0 The Clock Ready interrupt is disabled. 1 The Clock Ready interrupt is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 210 19.8.4 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x03 Reset:  0x01 Property:  – Bit 7 6 5 4 3 2 1 0 CKRDY Access R/W Reset 1 Bit 0 – CKRDY Clock Ready This flag is cleared by writing a '1' to the flag. This flag is set when the synchronous CPU, APBx, and AHBx clocks have frequencies as indicated in the CLKCFG registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Clock Ready interrupt flag. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 211 19.8.5 CPU Clock Division Name:  CPUDIV Offset:  0x05 Reset:  0x01 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CPUDIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 1 Bits 7:0 – CPUDIV[7:0] CPU Clock Division Factor These bits define the division ratio of the main clock prescaler related to the CPU clock domain. Frequencies must never exceed the specified maximum frequency for each clock domain. Value Name Description 0x01 DIV1 Divide by 1 0x02 DIV2 Divide by 2 0x04 DIV4 Divide by 4 0x08 DIV8 Divide by 8 0x10 DIV16 Divide by 16 0x20 DIV32 Divide by 32 0x40 DIV64 Divide by 64 0x80 DIV128 Divide by 128 others - Reserved SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 212 19.8.6 AHB Mask Name:  AHBMASK Offset:  0x10 Reset:  0x000001FFF Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 TRAM Reserved Reserved Reserved Reserved Access R/W R/W R/W R/W R/W Reset 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 NVMCTRL PAC Reserved DSU DMAC APBC APBB APBA Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 12 – TRAM TRAM AHB Clock Enable Value Description 0 The AHB clock for the TRAM is stopped 1 The AHB clock for the TRAM is enabled Bit 11 – Reserved Must Be Set to 1 Bit 11 must always be set to ‘1’ when programming the AHBMASK register. Bit 10 – Reserved Must Be Set to 1 Bit 10 must always be set to ‘1’ when programming the AHBMASK register. Bit 9 – Reserved Must Be Set to 1 Bit 9 must always be set to ‘1’ when programming the AHBMASK register. Bit 8 – Reserved Must Be Set to 1 Bit 8 must always be set to ‘1’ when programming the AHBMASK register. Bit 7 – NVMCTRL NVMCTRL AHB Clock Enable SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 213 Value Description 0 The AHB clock for the NVMCTRL is stopped 1 The AHB clock for the NVMCTRL is enabled Bit 6 – PAC PAC AHB Clock Enable Value Description 0 The AHB clock for the PAC is stopped. 1 The AHB clock for the PAC is enabled. Bit 5 – Reserved Must Be Set to 1 Bit 5 must always be set to ‘1’ when programming the AHBMASK register. Bit 4 – DSU DSU AHB Clock Enable Value Description 0 The AHB clock for the DSU is stopped. 1 The AHB clock for the DSU is enabled. Bit 3 – DMAC DMAC AHB Clock Enable Value Description 0 The AHB clock for the DMAC is stopped. 1 The AHB clock for the DMAC is enabled. Bit 2 – APBC APBC AHB Clock Enable Value Description 0 The AHB clock for the APBC is stopped. 1 The AHB clock for the APBC is enabled Bit 1 – APBB APBB AHB Clock Enable Value Description 0 The AHB clock for the APBB is stopped. 1 The AHB clock for the APBB is enabled. Bit 0 – APBA APBA AHB Clock Enable Value Description 0 The AHB clock for the APBA is stopped. 1 The AHB clock for the APBA is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 214 19.8.7 APBA Mask Name:  APBAMASK Offset:  0x14 Reset:  0x000007FFF Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Reserved AC PORT FREQM EIC RTC WDT Access R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 GCLK SUPC OSC32KCTRL OSCCTRL RSTC MCLK PM PAC Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 14 – Reserved For future use Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0. Bit 13 – AC AC APBA Clock Enable Value Description 0 The APBA clock for the AC is stopped. 1 The APBA clock for the AC is enabled. Bit 12 – PORT PORT APBA Clock Enable Value Description 0 The APBA clock for the PORT is stopped. 1 The APBA clock for the PORT is enabled. Bit 11 – FREQM FREQM APBA Clock Enable Value Description 0 The APBA clock for the FREQM is stopped. 1 The APBA clock for the FREQM is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 215 Bit 10 – EIC EIC APBA Clock Enable Value Description 0 The APBA clock for the EIC is stopped. 1 The APBA clock for the EIC is enabled. Bit 9 – RTC RTC APBA Clock Enable Value Description 0 The APBA clock for the RTC is stopped. 1 The APBA clock for the RTC is enabled. Bit 8 – WDT WDT APBA Clock Enable Value Description 0 The APBA clock for the WDT is stopped. 1 The APBA clock for the WDT is enabled. Bit 7 – GCLK GCLK APBA Clock Enable Value Description 0 The APBA clock for the GCLK is stopped. 1 The APBA clock for the GCLK is enabled. Bit 6 – SUPC SUPC APBA Clock Enable Value Description 0 The APBA clock for the SUPC is stopped. 1 The APBA clock for the SUPC is enabled. Bit 5 – OSC32KCTRL OSC32KCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSC32KCTRL is stopped. 1 The APBA clock for the OSC32KCTRL is enabled. Bit 4 – OSCCTRL OSCCTRL APBA Clock Enable Value Description 0 The APBA clock for the OSCCTRL is stopped. 1 The APBA clock for the OSCCTRL is enabled. Bit 3 – RSTC RSTC APBA Clock Enable Value Description 0 The APBA clock for the RSTC is stopped. 1 The APBA clock for the RSTC is enabled. Bit 2 – MCLK MCLK APBA Clock Enable Value Description 0 The APBA clock for the MCLK is stopped. 1 The APBA clock for the MCLK is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 216 Bit 1 – PM PM APBA Clock Enable Value Description 0 The APBA clock for the PM is stopped. 1 The APBA clock for the PM is enabled. Bit 0 – PAC PAC APBA Clock Enable Value Description 0 The APBA clock for the PAC is stopped. 1 The APBA clock for the PAC is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 217 19.8.8 APBB Mask Name:  APBBMASK Offset:  0x18 Reset:  0x00000017 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 HMATRIXHS NVMCTRL DSU IDAU Access R/W R/W R/W R/W Reset 1 1 1 1 Bit 4 – HMATRIXHS HMATRIXHS APBB Clock Enable Value Description 0 The APBB clock for the HMATRIXHS is stopped 1 The APBB clock for the HMATRIXHS is enabled Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable Value Description 0 The APBB clock for the NVMCTRL is stopped 1 The APBB clock for the NVMCTRL is enabled Bit 1 – DSU DSU APBB Clock Enable Value Description 0 The APBB clock for the DSU is stopped 1 The APBB clock for the DSU is enabled Bit 0 – IDAU IDAU APBB Clock Enable Value Description 0 The APBB clock for the IDAU is stopped 1 The APBB clock for the IDAU is enabled SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 218 19.8.9 APBC Mask Name:  APBCMASK Offset:  0x1C Reset:  0x00001FFF for 32-pin packages / 0x00001FF7 for 24-pin packages Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 OPAMP CCL TRNG PTC DAC Access R/W R R R R Reset 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 ADC TC2 TC1 TC0 SERCOM2 SERCOM1 SERCOM0 EVSYS Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 12 – OPAMP OPAMP APBC Clock Enable Value Description 0 The APBC clock for the OPAMP is stopped. 1 The APBC clock for the OPAMP is enabled. Bit 11 – CCL CCL APBC Mask Clock Enable Value Description 0 The APBC clock for the CCL is stopped. 1 The APBC clock for the CCL is enabled. Bit 10 – TRNG TRNG APBC Mask Clock Enable Value Description 0 The APBC clock for the TRNG is stopped. 1 The APBC clock for the TRNG is enabled. Bit 9 – PTC PTC APBC Mask Clock Enable Value Description 0 The APBC clock for the PTC is stopped. 1 The APBC clock for the PTC is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 219 Bit 8 – DAC DAC APBC Mask Clock Enable Value Description 0 The APBC clock for the DAC is stopped. 1 The APBC clock for the DAC is enabled. Bit 7 – ADC ADC APBC Mask Clock Enable Value Description 0 The APBC clock for the ADC is stopped. 1 The APBC clock for the ADC is enabled. Bit 6 – TC2 TC2 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC2 is stopped. 1 The APBC clock for the TC2 is enabled. Bit 5 – TC1 TC1 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC1 is stopped. 1 The APBC clock for the TC1 is enabled. Bit 4 – TC0 TC0 APBC Mask Clock Enable Value Description 0 The APBC clock for the TC0 is stopped. 1 The APBC clock for the TC0 is enabled. Bit 3 – SERCOM2 SERCOM2 APBC Mask Clock Enable SERCOM2 Peripheral Clock is disabled for all 24-pin packages as SERCOM2 is not present. Value Description 0 The APBC clock for the SERCOM2 is stopped. 1 The APBC clock for the SERCOM2 is enabled. Bit 2 – SERCOM1 SERCOM1 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM1 is stopped. 1 The APBC clock for the SERCOM1 is enabled. Bit 1 – SERCOM0 SERCOM0 APBC Mask Clock Enable Value Description 0 The APBC clock for the SERCOM0 is stopped. 1 The APBC clock for the SERCOM0 is enabled. Bit 0 – EVSYS EVSYS APBC Clock Enable SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 220 Value Description 0 The APBC clock for the EVSYS is stopped. 1 The APBC clock for the EVSYS is enabled. SAM L10/L11 Family MCLK – Main Clock © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 221 20. FREQM – Frequency Meter 20.1 Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 20.2 Features • Ratio can be measured with 24-bit accuracy • Accurately measures the frequency of an input clock with respect to a reference clock • Reference clock can be selected from the available GCLK_FREQM_REF sources • Measured clock can be selected from the available GCLK_FREQM_MSR sources 20.3 Block Diagram Figure 20-1. FREQM Block Diagram ENABLE VALUE REFNUM INTFLAG GCLK_FREQM_REF GCLK_FREQM_MSR DONE START COUNTER TIMER CLK_MSR CLK_REF_MUX EN EN DIVREF DIV8 20.4 Signal Description Not applicable. 20.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 20.5.1 I/O Lines The GCLK I/O lines (GCLK_IO[7:0]) can be used as measurement or reference clock sources. This requires the I/O pins to be configured. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 222 20.5.2 Power Management The FREQM will continue to operate in idle sleep mode where the selected source clock is running. The FREQM’s interrupts can be used to wake up the device from idle sleep mode. Refer to the Power Manager chapter for details on the different sleep modes. Related Links 22. PM – Power Manager 20.5.3 Clocks The clock for the FREQM bus interface (CLK_APB_FREQM) is enabled and disabled by the Main Clock Controller, the default state of CLK_APB_FREQM can be found in Peripheral Clock Masking. Two generic clocks are used by the FREQM: Reference Clock (GCLK_FREQM_REF) and Measurement Clock (GCLK_FREQM_MSR). GCLK_FREQM_REF is required to clock the internal reference timer, which acts as the frequency reference. GCLK_FREQM_MSR is required to clock a ripple counter for frequency measurement. These clocks must be configured and enabled in the generic clock controller before using the FREQM. Related Links 19. MCLK – Main Clock 19.6.2.6 Peripheral Clock Masking 18. GCLK - Generic Clock Controller 20.5.4 DMA Not applicable. 20.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using FREQM interrupt requires the interrupt controller to be configured first. 20.5.6 Events Not applicable 20.5.7 Debug Operation When the CPU is halted in debug mode the FREQM continues its normal operation. The FREQM cannot be halted when the CPU is halted in debug mode. If the FREQM is configured in a way that requires it to be periodically serviced by the CPU, improper operation or data loss may result during debugging. 20.5.8 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except the following registers: • Control B register (CTRLB) • Interrupt Flag Status and Clear register (INTFLAG) • Status register (STATUS) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 223 Related Links 15. PAC - Peripheral Access Controller 20.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 20.6 Functional Description 20.6.1 Principle of Operation FREQM counts the number of periods of the measured clock (GCLK_FREQM_MSR) with respect to the reference clock (GCLK_FREQM_REF). The measurement is done for a period of REFNUM/fCLK_REF and stored in the Value register (VALUE.VALUE). REFNUM is the number of Reference clock cycles selected in the Configuration A register (CFGA.REFNUM). The frequency of the measured clock, ݂CLK_MSR, is calculated by ݂CLK_MSR = VALUE REFNUM ݂CLK_REF 20.6.2 Basic Operation 20.6.2.1 Initialization Before enabling FREQM, the device and peripheral must be configured: • Each of the generic clocks (GCLK_FREQM_REF and GCLK_FREQM_MSR) must be configured and enabled. • Important:  The reference clock must be slower than the measurement clock. • Write the number of Reference clock cycles for which the measurement is to be done in the Configuration A register (CFGA.REFNUM). This must be a non-zero number. The following register is enable-protected, meaning that it can only be written when the FREQM is disabled (CTRLA.ENABLE=0): • Configuration A register (CFGA) Enable-protection is denoted by the "Enable-Protected" property in the register description. Related Links 18. GCLK - Generic Clock Controller SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 224 20.6.2.2 Enabling, Disabling and Resetting The FREQM is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The peripheral is disabled by writing CTRLA.ENABLE=0. The FREQM is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). On software reset, all registers in the FREQM will be reset to their initial state, and the FREQM will be disabled. Then ENABLE and SWRST bits are write-synchronized. Related Links 20.6.7 Synchronization 20.6.2.3 Measurement In the Configuration A register, the Number of Reference Clock Cycles field (CFGA.REFNUM) selects the duration of the measurement. The measurement is given in number of GCLK_FREQM_REF periods. Note:  The REFNUM field must be written before the FREQM is enabled. After the FREQM is enabled, writing a '1' to the START bit in the Control B register (CTRLB.START) starts the measurement. The BUSY bit in Status register (STATUS.BUSY) is set when the measurement starts, and cleared when the measurement is complete. There is also an interrupt request for Measurement Done: When the Measurement Done bit in Interrupt Enable Set register (INTENSET.DONE) is '1' and a measurement is finished, the Measurement Done bit in the Interrupt Flag Status and Clear register (INTFLAG.DONE) will be set and an interrupt request is generated. The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured clock GCLK_FREQM_MSR is then: ݂CLK_MSR = VALUE REFNUM ݂CLK_REF Note:  In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status (STATUS.OVF) should be checked. In case an overflow condition occurred, indicated by the Overflow bit in the STATUS register (STATUS.OVF), either the number of reference clock cycles must be reduced (CFGA.REFNUM), or a faster reference clock must be configured. Once the configuration is adjusted, clear the overflow status by writing a '1' to STATUS.OVF. Then another measurement can be started by writing a '1' to CTRLB.START. 20.6.3 DMA Operation Not applicable. 20.6.4 Interrupts The FREQM has one interrupt source: • DONE: A frequency measurement is done. The interrupt flag in the Interrupt Flag Status and Clear (20.8.6 INTFLAG) register is set when the interrupt condition occurs. The interrupt can be enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (20.8.5 INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (20.8.4 INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 225 FREQM is reset. See 20.8.6 INTFLAG for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the 20.8.6 INTFLAG register to determine which interrupt condition is present. This interrupt is a synchronous wake-up source. Note that interrupts must be globally enabled for interrupt requests to be generated. 20.6.5 Events Not applicable. 20.6.6 Sleep Mode Operation The FREQM will continue to operate in idle sleep mode where the selected source clock is running. The FREQM’s interrupts can be used to wake up the device from idle sleep mode. For lowest chip power consumption in sleep modes, FREQM should be disabled before entering a sleep mode. Related Links 22. PM – Power Manager 20.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits and registers are write-synchronized: • Software Reset bit in Control A register (CTRLA.SWRST) • Enable bit in Control A register (CTRLA.ENABLE) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 226 20.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 ENABLE SWRST 0x01 CTRLB 7:0 START 0x02 CFGA 7:0 REFNUM[7:0] 15:8 DIVREF 0x04 ... 0x07 Reserved 0x08 INTENCLR 7:0 DONE 0x09 INTENSET 7:0 DONE 0x0A INTFLAG 7:0 DONE 0x0B STATUS 7:0 OVF BUSY 0x0C SYNCBUSY 7:0 ENABLE SWRST 15:8 23:16 31:24 0x10 VALUE 7:0 VALUE[7:0] 15:8 VALUE[15:8] 23:16 VALUE[23:16] 31:24 20.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 227 20.8.1 Control A Name:  CTRLA Offset:  0x00 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R/W R/W Reset 0 0 Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not enable-protected. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the FREQM to their initial state, and the FREQM will be disabled. Writing a '1' to this bit will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete. This bit is not enable-protected. Value Description 0 There is no ongoing Reset operation. 1 The Reset operation is ongoing. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 228 20.8.2 Control B Name:  CTRLB Offset:  0x01 Reset:  0x00 Property:  – Bit 7 6 5 4 3 2 1 0 START Access W Reset 0 Bit 0 – START Start Measurement Value Description 0 Writing a '0' has no effect. 1 Writing a '1' starts a measurement. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 229 20.8.3 Configuration A Name:  CFGA Offset:  0x02 Reset:  0x0000 Property:  PAC Write-Protection, Enable-protected Bit 15 14 13 12 11 10 9 8 DIVREF Access R/W Reset 0 Bit 7 6 5 4 3 2 1 0 REFNUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – DIVREF Divide Reference Clock Divides the reference clock by 8 Value Description 0 The reference clock is divided by 1. 1 The reference clock is divided by 8. Bits 7:0 – REFNUM[7:0] Number of Reference Clock Cycles Selects the duration of a measurement in number of CLK_FREQM_REF cycles. This must be a non-zero value, i.e. 0x01 (one cycle) to 0xFF (255 cycles). SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 230 20.8.4 Interrupt Enable Clear Name:  INTENCLR Offset:  0x08 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Measurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Measurement Done Interrupt Enable bit, which disables the Measurement Done interrupt. Value Description 0 The Measurement Done interrupt is disabled. 1 The Measurement Done interrupt is enabled. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 231 20.8.5 Interrupt Enable Set Name:  INTENSET Offset:  0x09 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Measurement Done Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Measurement Done Interrupt Enable bit, which enables the Measurement Done interrupt. Value Description 0 The Measurement Done interrupt is disabled. 1 The Measurement Done interrupt is enabled. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 232 20.8.6 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x0A Reset:  0x00 Property:  – Bit 7 6 5 4 3 2 1 0 DONE Access R/W Reset 0 Bit 0 – DONE Mesurement Done This flag is cleared by writing a '1' to it. This flag is set when the STATUS.BUSY bit has a one-to-zero transition. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the DONE interrupt flag. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 233 20.8.7 Status Name:  STATUS Offset:  0x0B Reset:  0x00 Property:  – Bit 7 6 5 4 3 2 1 0 OVF BUSY Access R/W R Reset 0 0 Bit 1 – OVF Sticky Count Value Overflow This bit is cleared by writing a '1' to it. This bit is set when an overflow condition occurs to the value counter. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the OVF status. Bit 0 – BUSY FREQM Status Value Description 0 No ongoing frequency measurement. 1 Frequency measurement is ongoing. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 234 20.8.8 Synchronization Busy Name:  SYNCBUSY Offset:  0x0C Reset:  0x00000000 Property:  – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ENABLE SWRST Access R R Reset 0 0 Bit 1 – ENABLE Enable This bit is cleared when the synchronization of CTRLA.ENABLE is complete. This bit is set when the synchronization of CTRLA.ENABLE is started. Bit 0 – SWRST Synchronization Busy This bit is cleared when the synchronization of CTRLA.SWRST is complete. This bit is set when the synchronization of CTRLA.SWRST is started. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 235 20.8.9 Value Name:  VALUE Offset:  0x10 Reset:  0x00000000 Property:  – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 VALUE[23:16] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 VALUE[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 VALUE[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 23:0 – VALUE[23:0] Measurement Value Result from measurement. SAM L10/L11 Family FREQM – Frequency Meter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 236 21. RSTC – Reset Controller 21.1 Overview The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the device to its initial state and allows the reset source to be identified by software. 21.2 Features • Reset the microcontroller and set it to an initial state according to the reset source • Reset cause register for reading the reset source from the application code • Multiple reset sources – Power supply reset sources: POR, BOD12, BOD33 – User reset sources: External reset (RESET), Watchdog reset, and System Reset Request 21.3 Block Diagram Figure 21-1. Reset System RESET CONTROLLER BODCORE BODVDD POR WDT RESET RESET SOURCES RTC 32kHz clock sources WDT with ALWAYSON GCLK with WRTLOCK Debug Logic CPU Other Modules RCAUSE 21.4 Signal Description Signal Name Type Description RESET Digital input External reset One signal can be mapped on several pins. 21.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. SAM L10/L11 Family RSTC – Reset Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 237 21.5.1 I/O Lines Not applicable. 21.5.2 Power Management The Reset Controller module is always on. 21.5.3 Clocks The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller. Related Links 19. MCLK – Main Clock 19.6.2.6 Peripheral Clock Masking 21.5.4 DMA Not applicable. 21.5.5 Interrupts Not applicable. 21.5.6 Events Not applicable. 21.5.7 Debug Operation When the CPU is halted in debug mode, the RSTC continues normal operation. 21.5.8 Register Access Protection All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC). Note:  Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. 21.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 21.5.10 Analog Connections Not applicable. SAM L10/L11 Family RSTC – Reset Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 238 21.6 Functional Description 21.6.1 Principle of Operation The Reset Controller collects the various Reset sources and generates Reset for the device. 21.6.2 Basic Operation 21.6.2.1 Initialization After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source. 21.6.2.2 Enabling, Disabling, and Resetting The RSTC module is always enabled. 21.6.2.3 Reset Causes and Effects The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence in order to determine proper action. These are the groups of Reset sources: • Power supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets • User Reset: Resets caused by the application. It covers external Resets, system Reset requests and watchdog Resets The following table lists the parts of the device that are reset, depending on the Reset type. Table 21-1. Effects of the Different Reset Causes Power Supply Reset User Reset POR, BOD33, BOD12 External Reset WDT Reset, System Reset Request RTC, OSC32KCTRL, RSTC Y N N GCLK with WRTLOCK Y N N Debug logic Y Y N Others Y Y Y The external Reset is generated when pulling the RESET pin low. The POR, BOD12, and BOD33 Reset sources are generated by their corresponding module in the Supply Controller Interface (SUPC). The WDT Reset is generated by the Watchdog Timer. The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details refer to the ARM® Cortex™ Technical Reference Manual on http://www.arm.com). Note:  Refer to the Timing Characteristics section of the Electrical Characteristics chapter. Related Links 26. WDT – Watchdog Timer 25. SUPC – Supply Controller SAM L10/L11 Family RSTC – Reset Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 239 46.14.1 External Reset Pin 21.6.3 Additional Features Not applicable. 21.6.4 DMA Operation Not applicable. 21.6.5 Interrupts Not applicable. 21.6.6 Events Not applicable. 21.6.7 Sleep Mode Operation The RSTC module is active in all sleep modes. SAM L10/L11 Family RSTC – Reset Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 240 21.7 Register Summary Offset Name Bit Pos. 0x00 RCAUSE 7:0 SYST WDT EXT BOD33 BOD12 POR 21.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 21.5.8 Register Access Protection. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family RSTC – Reset Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 241 21.8.1 Reset Cause Name:  RCAUSE Offset:  0x00 Property:  – When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'. Bit 7 6 5 4 3 2 1 0 SYST WDT EXT BOD33 BOD12 POR Access R R R R R R Reset x x x x x x Bit 6 – SYST System Reset Request This bit is set if a System Reset Request has occurred. Refer to the Cortex processor documentation for more details. Bit 5 – WDT Watchdog Reset This bit is set if a Watchdog Timer Reset has occurred. Bit 4 – EXT External Reset This bit is set if an external Reset has occurred. Bit 2 – BOD33  Brown Out 33 Detector Reset This bit is set if a BOD33 Reset has occurred. Bit 1 – BOD12  Brown Out 12 Detector Reset This bit is set if a BOD12 Reset has occurred. Bit 0 – POR Power On Reset This bit is set if a POR has occurred. SAM L10/L11 Family RSTC – Reset Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 242 22. PM – Power Manager 22.1 Overview The Power Manager (PM) controls the sleep modes and the power domain gating of the device. Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In active mode, the CPU is executing application code. When the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a sleep mode to active mode. Performance level technique consists of adjusting the regulator output voltage to reduce power consumption. The user can select on the fly the performance level configuration which best suits the application. The power domain gating technique enables the PM to turn off unused power domain supplies individually, while keeping others powered up. Based on activity monitoring, power domain gating is managed automatically by hardware without software intervention. This technique is transparent for the application while minimizing the static consumption. The user can also manually control which power domains will be turned on and off in standby sleep mode. The internal state of the logic is retained (retention state) allowing the application context to be kept in non-active states. 22.2 Features • Power management control – Sleep modes: Idle, Standby, and Off – Performance levels: PL0 and PL2 – SleepWalking available in Standby mode. – Full retention state in Standby mode • Power Domain Control – Standby Sleep Mode with static power gating – SleepWalking extension to power gating – SRAM sub-blocks retention in Standby mode SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 243 22.3 Block Diagram Figure 22-1. PM Block Diagram SLEEP MODE CONTROLLER PERFORMANCE LEVEL CONTROLLER SUPPLY CONTROLLER MAIN CLOCK CONTROLLER SLEEPCFG PLCF POWER DOMAIN CONTROLLER POWER MANAGER STDBYCFG POWER LEVEL SWITCHES FOR POWER DOMAINS 22.4 Signal Description Not applicable. 22.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 22.5.1 I/O Lines Not applicable. 22.5.2 Clocks The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is disabled, it can only be re-enabled by a system reset. 22.5.3 DMA Not applicable. 22.5.4 Interrupts The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the interrupt controller to be configured first. 22.5.5 Events Not applicable. 22.5.6 Debug Operation When the CPU is halted in debug mode, the PM continues normal operation. If standby sleep mode is requested by the system while in debug mode, the power domains are not turned off. As a consequence, power measurements while in debug mode are not relevant. If OFF sleep mode is requested by the system while in debug mode, the core domains are kept on, and the debug modules are kept running to allow the debugger to access internal registers. When exiting the OFF mode upon a reset condition, the core domains are reset except the debug logic, allowing users to keep using their current debug session. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 244 Hot plugging in standby mode is supported except if the power domain PDSW is in retention state. Cold plugging in OFF mode is supported as long as the reset duration is superior to (Tmin). 22.5.7 Register Access Protection Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). PAC Write-Protection is not available for the following registers: • Interrupt Flag register (INTFLAG). Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Write-protection does not apply to accesses through an external debugger. Related Links 15. PAC - Peripheral Access Controller 22.5.8 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 22.5.9 Analog Connections Not applicable. 22.6 Functional Description 22.6.1 Terminology The following is a list of terms used to describe the Power Managemement features of this microcontroller. 22.6.1.1 Performance Levels To help balance between performance and power consumption, the device has two performance levels. Each of the performance levels has a maximum operating frequency and a corresponding maximum consumption in µA/MHz. It is the application's responsibility to configure the appropriate PL depending on the application activity level. When the application selects a new PL, the voltage applied on the full logic area moves from one value to another. This voltage scaling technique allows to reduce the active power consumption while decreasing the maximum frequency of the device. 22.6.1.1.1 PL0 Performance Level 0 (PL0) provides the maximum energy efficiency configuration. Refer to the Electrical Characteristics chapters for details on energy consumption and maximum operating frequency. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 245 22.6.1.1.2 PL2 Performance Level 2 (PL2) provides the maximum operating frequency. Refer to the Electrical Characteristics chapters for details on energy consumption and maximum operating frequency. 22.6.1.2 Power Domains In addition to the supply domains, such as VDDIO and VDDANA, the device provides these power domains: • PDSW • PDAO The PDSW is a "switchable power domain". In standby sleep mode, it can be turned off to save leakage consumption according to user configuration. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 246 Figure 22-2. Power Domain Partitioning PDAO (Power Domain Always On) PDSW (Power Domain Switchable) 6 x SERCOM 8 x Timer Counter AHB-APB BRIDGE C M M High-Speed Bus Matrix PORT PORT SERIAL SWDIO WIRE S Cortex-M23 PROCESSOR Fmax 32 MHz SWCLK DEVICE SERVICE UNIT AHB-APB BRIDGE A 10-CHANNEL 12-bit ADC 1MSPS AIN[9..0] VREFA AIN[3..0] S SRAM CONTROLLER 16/8/8 KB RAM (SAM L11) - 16/8/4 KB RAM (SAM L10) M 3x TIMER / COUNTER EVENT SYSTEM S 3x SERCOM 2x ANALOG COMPARATORS PERIPHERAL TOUCH CONTROLLER AHB-APB BRIDGE B S PAD[0] WO[1] PAD[1] PAD[2] PAD[3] WO[0] VREFB 2KB Data Flash NVM CONTROLLER M DMA IOBUS DMA DMA DMA S REAL-TIME COUNTER WATCHDOG TIMER RESET OSCILLATORS CONTROLLER XOUT XIN XOUT32 XIN32 OSCULP32K OSC16M XOSC32K XOSC EXTERNAL INTERRUPT CONTROLLER MAIN CLOCKS CONTROLLER EXTINT[7..0] NMI GCLK_IO[4..0] FDPLL96M GENERIC CLOCK CONTROLLER POWER MANAGER RESET CONTROLLER OSC32K CONTROLLER SUPPLY CONTROLLER VREF BOD33 TRNG IN[5..0] CCL OUT[1..0] FREQUENCY METER DMA IN[3:0] VOUT 10-bit DAC 350kSPS DMA 256 Bytes TrustRAM PERIPHERAL ACCESS CONTROLLER DFLLULP OUT[3:0] CMP[1..0] VREFA 8 KB ROM S IDAU TrustZone for ARMv8-M Crypto Accelerators (AES128, SHA256, GCM) Bootloader Authentication 64/32/16 KB Flash with Cache Data Scrambling EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT EVENT CRC-32 3x OPAMP OA[0..2]POS OA[0..2]NEG SAM L11 Added Features MPU Voltage Regulators BOD12 XY[19..0] OA0OUT / OA2OUT SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 247 22.6.1.2.1 PDSW - Power Domain Switchable PDSW is the switchable power domain. It contains the Event System, Generic Clock Controller, Main Clock Controller, Oscillator Controller, Non-Volatile Memory Controller, DMA Controller, the Device Service Unit, and the ARM core. PDSW also contains a number of peripherals that allow the device to wake up from an interrupt: SERCOM, Timer, ADC, DAC, OPAMP, CCL, PTC. 22.6.1.2.2 PDAO - Power Domain Always On PDAO contains all controllers located in the always-on domain. It is powered when in Active, Idle, or Standby mode. 22.6.1.3 Sleep Modes The device can be set in a sleep mode. In sleep mode, the CPU is stopped and the peripherals are either active or idle, according to the sleep mode depth: • Idle sleep mode: The CPU is stopped. Synchronous clocks are stopped except when requested. The logic is retained. • Standby sleep mode: The CPU is stopped as well as the peripherals. The logic is retained, and power domain gating can be used to reduce power consumption further. • Off sleep mode: The entire device is powered off. 22.6.1.4 Power Domain States and Gating In Standby sleep mode, the Power Domain Gating technique allows for selecting the state of PDSW power domain automatically (e.g. for executing sleepwalking tasks) or manually: Active State The power domain is powered according to the performance level Retention State The main voltage supply for the power domain is switched off, while maintaining a secondary low-power supply for sequential cells. The logic context is restored when waking up. 22.6.2 Principle of Operation In active mode, all clock domains and power domains are active, allowing software execution and peripheral operation. The PM Sleep Mode Controller allows to save power by choosing between different sleep modes depending on application requirements, see 22.6.3.3 Sleep Mode Controller. The PM Performance Level Controller allows to optimize either for low power consumption or high performance. The PM Power Domain Controller allows to reduce the power consumption in standby mode even further. 22.6.3 Basic Operation 22.6.3.1 Initialization After a Power-on Reset (POR), the PM is enabled, the device is in Active mode, the performance level is PL0 (the lowest power consumption) and all the power domains are in active state. 22.6.3.2 Enabling, Disabling and Resetting The PM is always enabled and can not be reset. 22.6.3.3 Sleep Mode Controller Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode. Note:  A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 248 Note:  After power-up, the MAINVREG low power mode takes some time to stabilize. Once stabilized, the SUPC->STATUS.ULPVREFRDY bit is set. Before entering Standby, software must ensure that the SUPC->STATUS.ULPVREFRDY bit is set. Table 22-1. Sleep Mode Entry and Exit Table Mode Mode Entry Wake-Up Sources IDLE SLEEPCFG.SLEEPMODE = IDLE _n Synchronous (2) (APB, AHB), asynchronous (1) STANDBY SLEEPCFG.SLEEPMODE = STANDBY Synchronous(3), Asynchronous OFF SLEEPCFG.SLEEPMODE = OFF External Reset Note:  1. Asynchronous: interrupt generated on generic clock, external clock, or external event. 2. Synchronous: interrupt generated on the APB clock. 3. Synchronous interrupt only for peripherals configured to run in standby. Note:  The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section. The sleep modes (idle, standby, and off) and their effect on the clocks activity, the regulator and the NVM state are described in the table and the sections below. Refer to Power Domain Controller for the power domain gating effect. Table 22-2. Sleep Mode Overview Mode Main clock CPU AHBx and APBx clock GCLK clocks Oscillators Regulator NVM ONDEMAND = 0 ONDEMAND = 1 Active Run Run Run Run(3) Run Run if requested MAINVREG active IDLE Run Stop Stop(1) Run(3) Run Run if requested MAINVREG active STANDBY Stop(1) Stop Stop(1) Stop(1) Run if requested or RUNSTDBY=1 Run if requested MAINVREG in low power mode Ultra Low- power OFF Stop Stop Stop OFF OFF OFF OFF OFF Note:  1. Running if requested by peripheral during SleepWalking. 2. Running during SleepWalking. 3. Following On-Demand Clock Request principle. 22.6.3.3.1 IDLE Mode IDLE mode allows power optimization with the fastest wake-up time. The CPU is stopped, and peripherals are still working. As in Active mode, the AHBx and APBx clocks for peripheral are still provided if requested. As the main clock source is still running, wake-up time is very fast. • Entering Idle mode: The Idle mode is entered by executing the WFI instruction. Additionally, if the SLEEPONEXIT bit in the Cortex System Control register (SCR) is set, the Idle mode will be entered when the CPU exits the lowest priority ISR (Interrupt Service Routine, refer to the ARM Cortex SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 249 documentation for details). This mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Before entering the Idle mode, the user must select the Idle Sleep mode in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=IDLE). • Exiting Idle mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry. The system goes back to the Active mode. The CPU and affected modules are restarted. GCLK clocks, regulators and RAM are not affected by the Idle Sleep mode and operate in normal mode. 22.6.3.3.2 STANDBY Mode The Standby mode is the lowest power configuration while keeping the state of the logic and the content of the RAM. In this mode, all clocks are stopped except those configured to be running sleepwalking tasks. The clocks can also be active on request or at all times, depending on their on-demand and run-in-standby settings. Either synchronous (CLK_APBx or CLK_AHBx) or generic (GCLK_x) clocks or both can be involved in sleepwalking tasks. This is the case when for example the SERCOM RUNSTDBY bit is written to '1'. • Entering Standby mode: This mode is entered by executing the WFI instruction after writing the Sleep Mode bit in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=STANDBY). The SLEEPONEXIT feature is also available as in Idle mode. • Exiting Standby mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU. Refer to 22.6.3.5 Power Domain Controller for the RAM state. The regulator operates in Low-Power mode by default and switches automatically to the normal mode in case of a sleepwalking task requiring more power. It returns automatically to low power mode when the sleepwalking task is completed. 22.6.3.3.3 OFF Mode In Off mode, the device is entirely powered-off. • Entering Off mode: This mode is entered by selecting the Off mode in the Sleep Configuration register by writing the Sleep Mode bits (SLEEPCFG.SLEEPMODE=OFF), and subsequent execution of the WFI instruction. • Exiting Off mode: This mode is left by pulling the RESET pin low, or when a power Reset is done. 22.6.3.4 Performance Level The application can change the performance level on the fly writing to the by Performance Level Select bit in the Performance Level Configuration register (PLCFG.PLSEL). When changing to a lower performance level, the bus frequency must be reduced before writing PLCFG.PLSEL in order to avoid exceeding the limit of the target performance level. When changing to a higher performance level, the bus frequency can be increased only after the Performance Level Ready flag in the Interrupt Flag Status and Clear (INTFLAG.PLRDY) bit set to '1', indicating that the performance level transition is complete. After a reset, the device starts in the lowest PL (lowest power consumption and lowest max frequency). The application can then switch to another PL at anytime without any stop in the code execution. As shown in Figure 22-3, performance level transition is possible only when the device is in active mode. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 250 The Performance Level Disable bit in the Performance Level Configuration register (PLCFG.PLDIS) can be used to freeze the performance level to PL0. This disables the performance level hardware mechanism in order to reduce both the power consumption and the wake-up startup time from standby sleep mode. Note:  This bit PLCFG.PLDIS must be changed only when the current performance level is PL0. Any attempt to modify this bit while the performance level is not PL0 is discarded and a violation is reported to the PAC module. Any attempt to change the performance level to PLn (with n>0) while PLCFG.PLDIS=1 is discarded and a violation is reported to the PAC module. Figure 22-3. Sleep Modes and Performance Level Transitions ACTIVE PLn IDLE PLn SLEEPCFG. IDLE IRQ SLEEPCFG. STANDBY IRQ OFF ACTIVE PL0 RESET PLCFG.PLSEL STANDBY ext reset SLEEPCFG. OFF 22.6.3.5 Power Domain Controller The Power Domain Controller provides several ways of how power domains are handled while the device is in Standby mode or entering Standby mode: • Default operation - all peripherals idle When entering Standby mode, the power domain PDSW is set in retention state. This allows for very low power consumption while retaining all the logic content of these power domains. When exiting Standby mode, all power domains are set back to active state. • Default operation - Standby Sleep Mode with static power gating SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 251 Static Power Domain Gating is a technique that allows to automatically turn off the PDSW power domain supply when not used while keeping PDAO powered up. • SleepWalking extension to power gating (SleepWalking with dynamic power gating) SleepWalking is the capability for a device in Standby Sleep mode, to temporarily wake-up clocks for a peripheral to perform a task without waking-up the CPU. The SleepWalking feature has been expanded to control power gating in addition to clock gating. The power domain PDSW can be automatically controlled (active or retention state) depending on peripheral requirements (PDCFG bit from the STDBYCFG register). The static and dynamic power gating features are fully transparent for the user. Table 22-3. Sleep Modes versus Power Domain States Overview Power Domain State Sleep Mode PDSW PDAO Active active active Idle active active Standby - At least one peripheral from PDSW with RUNSTDBY = 1 OR PDCFG = 1 active (1) active Standby - No peripheral from PDSW with RUNSTDBY = 1 retention active Off off off Note:  1. PDSW can be switched automatically in retention mode if the dynamic power gating feature is enabled. 22.6.3.6 Regulators, RAMs, and NVM State in Sleep Mode By default, in Standby Sleep mode, the RAMs, NVM, and regulators are automatically set in Low-Power mode to reduce power consumption: • The RAM is in Low-Power mode if its power domain is in retention or off state. • Non-Volatile Memory - the NVM is located in the power domain PDSW. By default, the NVM is automatically set in low power mode in these conditions: – When the power domain PDSW is in retention or off state. – When the device is in Standby Sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral. – When the device is in Idle Sleep mode and the NVM is not accessed. This behavior can be changed by software by configuring the SLEEPPRM bit group of the CTRLB register in the NVMCTRL peripheral. • Regulators: by default, in Standby Sleep mode, the PM analyzes the device activity to use either the main or the low-power voltage regulator to supply the VDDCORE. GCLK clocks, regulators and RAM are not affected in Idle Sleep mode and will operate as normal. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 252 Table 22-4. Regulators, RAMs, and NVM state in Sleep Mode Sleep Mode PDSW SRAM Mode(1) NVM Regulators VDDCORE main ULP Active active normal normal on on Idle active auto(2) on on on Standby - PDSW in Active mode active normal(6) auto(2) auto(3) on(5) Standby - PDSW in Retention mode retention low power(6) low power auto(4) on(5) OFF off off off off off Note:  1. RAMs mode by default: STDBYCFG.BBIAS bits are set to their default value. 2. auto: by default, NVM is in low-power mode if not accessed. 3. auto: by default, the main voltage regulator is on if GCLK, APBx, or AHBx clock is running during SleepWalking. 4. auto: by default ULP regulator is selected in retention, but main regulator will be selected if VREG RUNSTDBY register bit in Supply Controller is set to 1. 5. on: low power voltage reference must be ready, and this is confirmed if STATUS.ULPVREFRDY register bit in SUPC equals to 1 6. SRAM can be partially retained in STANDBY using SRAM Power Switch Related Links 22.6.4.4 Regulator Automatic Low Power Mode 22.6.4 Advanced Features 22.6.4.1 Power Domain Configuration When entering Standby Sleep mode, a power domain is set automatically to retention state if no activity is required in it, refer to 22.6.3.5 Power Domain Controller for details. This behavior can be changed by writing the Power Domain Configuration bit group in the Standby Configuration register (STDBYCFG.PDCFG). For example, all power domains can be forced to remain in active state during Standby Sleep mode, this will accelerate wake-up time. 22.6.4.2 RAM Automatic Low Power Mode The RAM is by default put in Low-Power mode (back-biased) if its power domain is in retention state and the device is in Standby Sleep mode. This behavior can be changed by configuring BBIASxx bit groups in the Standby Configuration register (STDBYCFG.BBIASxx), refer to the table below for details. Note:  in Standby Sleep mode, the DMAC can access the SRAM in Standby Sleep mode only when the power domain PDSW is not in retention and PM.STDBYCFG.BBIASxx=0x0. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 253 Table 22-5. RAM Back-Biasing Mode STBYCDFG.BBIASxx config RAM 0x0 Retention Back Biasing mode RAM is back-biased if its power domain is in retention state 0x1 Standby Back Biasing mode RAM is back-biased if the device is in Standby Sleep mode 22.6.4.3 SRAM Power Switch Configuration The SRAM is divided in sub-blocks which can be retained or not in STANDBY low power mode to optimize power consumption. By default, all sub-blocks are retained but it is possible to switch them off depending on SRAM memory size. This behavior can be changed by configuring RAMPSWC bit groups in the Power Configuration register (PWCFG). This configuration takes effect immediately. So, this is the responsibility of the user to ensure that no access is performed on OFF RAM. When a SRAM sub-block is switched ON, the user has to wait 1 us before accessing it. The first sub-block to be switched off is always at the top of the SRAM block memory and this is the same for the next ones. 22.6.4.4 Regulator Automatic Low Power Mode In standby mode, the PM selects either the main or the low power voltage regulator to supply the VDDCORE. If switchable power domain is in retention state, the low power voltage regulator is used. If a sleepwalking task is working on either asynchronous clocks (generic clocks) or synchronous clock (APB/AHB clocks), the main voltage regulator is used. This behavior can be changed by writing the Voltage Regulator Standby Mode bits in the Standby Configuration register (STDBYCFG.VREGSMOD). Refer to the following table for details. Table 22-6. Regulator State in Sleep Mode Sleep Modes STDBYCFG. VREGSMOD SleepWalking(1) Regulator state for VDDCORE Active - - main voltage regulator Idle - - main voltage regulator Standby (active) 0x0: AUTO NO low power regulator YES main voltage regulator 0x1: PERFORMANCE - main voltage regulator 0x2: LP(2) - (2) low power regulator Standby (retention) - - low power regulator Note:  1. SleepWalking is running on GCLK clock or synchronous clock. This is not related to XOSC32K or OSCULP32K clocks. 2. Must only be used when SleepWalking is running on GCLK with 32KHz source. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 254 22.6.4.5 SleepWalking and Performance Level SleepWalking is the capability for a device to temporarily wake up clocks for a peripheral to perform a task without waking up the CPU from STANDBY sleep mode. At the end of the sleepwalking task, the device can either be woken up by an interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode. In this device, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of the clock sources. In standby mode, when SleepWalking is ongoing, the performance level used to execute the sleepwalking task is the current configured performance level (used in active mode), and the main voltage regulator used to execute the SleepWalking task is the selected regulator used in active mode (LDO or Buck converter). These are illustrated in the figure below. Figure 22-4. Operating Conditions and SleepWalking ACTIVE ACTIVE RESET IDLE ACTIVE IDLE STANDBY PL0 PL2 SLEEP PL2 WALKING STANDBY PL0 WALKING IDLE LDO BUCK RESET VREG.SEL LDO BUCK Regulator modes LP VREG SLEEP Sleep Mode Performance Level SUPC 22.6.4.6 Wake-Up Time The total wake-up time depends on the following: • Latency due to Power Domain Gating: Usually, wake-up time is measured with the assumption that the power domain is already in active state. When using Power Domain Gating, changing a power domain from retention to active state will take a certain time, refer to Electrical Characteristics. If power domain was already in active state in standby sleep mode, this latency is zero. If wake-up time is critical for the application, power domain can be forced to active state in Standby Sleep mode, refer to 22.6.4.1 Power Domain Configuration for details. • Latency due to Performance Level and Regulator effect: Performance Level has to be taken into account for the global wake-up time. As example, if PL2 is selected and the device is in Standby Sleep mode, the voltage level supplied by the ULP voltage regulator is lower than the one used in Active mode. When the device wakes up, it takes a certain SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 255 amount of time for the main regulator to transition to the voltage level corresponding to PL2, causing additional wake-up time. • Latency due to the CPU clock source wake-up time. • Latency due to the NVM memory access. • Latency due to Switchable Power Domain back-bias wake-up time: If back-bias is enabled, and the device wakes up from retention, it takes a certain amount of time for the regulator to settle. Figure 22-5. Total Wake-up Time from Standby Sleep Mode Low Power mode PDSW active retention active IRQ from module WFI instruction CPU state run standby sleep mode run interrupt handler VDDCORE Main regulator Main regulator 1 CLK_CPU ON OFF ON 2 3 4 Normal mode 1: latency due to power domain gating 2: latency due to regulator wakeup time 3: latency due to clock source wakeup time 4: latency due to flash memory code access Main regulator Normal mode 22.6.5 Standby with Static Power Domain Gating in Details In Standby Sleep mode, the switchable power domain (PDSW) of a peripheral can remain in active state to perform the peripheral's tasks. This Static Power Domain Gating feature is supported by all peripherals. For some peripherals it must be enabled by writing a Run in Standby bit in the respective Control A register (CTRLA.RUNSTDBY) to '1'. Refer to each peripheral chapter for details. The following examples illustrate Standby with static Power Domain Gating: TC0 Standby with Static Power Domain Gating TC0 peripheral is used in counter operation mode. An interrupt is generated to wake-up the device based on the TC0 peripheral configuration. To make the TC0 peripheral continue to run in Standby Sleep mode, the RUNSTDBY bit is written to '1'. • Entering Standby mode: As shown in Figure 22-6, PDSW remains active. Refer to 22.6.3.5 Power Domain Controller for details. • Exiting Standby mode: When conditions are met, the TC0 peripheral generates an interrupt to wake-up the device, and the CPU is able to operate normally and execute the TC0 interrupt handler accordingly. • Wake-up time: – The required time to set PDSW to active state has to be considered for the global wake-up time, refer to 22.6.4.6 Wake-Up Time for details. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 256 – In this case, the VDDCORE voltage is still supplied by the main voltage regulator, refer to 22.6.4.4 Regulator Automatic Low Power Mode for details. Thus, global wake-up time is not affected by the regulator. Figure 22-6. TC0 in Standby with Static Power Domain Gating PDSW TC0 PM PDAO Main Supply active state active state RUNSTDBY active PDAO PDSW active IRQ IRQ from TC0 WFI instruction CPU state run standby sleep mode run interrupt handler CPU GCLK GCLK_TC0 EIC in Standby with Static Power Domain Gating In this example, EIC peripheral is used to detect an edge condition to generate interrupt to the CPU. An External interrupt pin is filtered by the CLK_ULP32K clock, GCLK peripheral is not used. Refer to Chapter 29. EIC – External Interrupt Controller for details. The EIC peripheral is located in the power domain PDAO (which is not switchable), and there is no RUNSTDBY bit in the EIC peripheral. • Entering Standby mode: As shown in Figure 22-7, the switchable power domain is set in retention state by the Power Manager peripheral. The low power regulator supplies the VDDCORE voltage level. • Exiting Standby mode: When conditions are met, the EIC peripheral generates an interrupt to wake the device up. Successively, the PM peripheral sets PDSW to active state, and the main voltage regulator restarts. Once PDSW is in active state and the main voltage regulator is ready, the CPU is able to operate normally and execute the EIC interrupt handler accordingly. • Wake-up time: – The required time to set the switchable power domains to active state has to be considered for the global wake-up time, refer to 22.6.4.6 Wake-Up Time for details. – When in standby Sleep mode, the GCLK peripheral is not used, allowing the VDDCORE to be supplied by the low power regulator to reduce consumption, see 22.6.4.4 Regulator Automatic Low Power Mode. Consequently, main voltage regulator wake-up time has to be considered for the global wake-up time as shown in Figure 22-7. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 257 Figure 22-7. EIC in Standby with Static Power Domain Gating CPU PDSW EIC PM PDAO Main Supply retention state active state PDSW active active IRQ retention WFI instruction OSCULP32K PDAO active IRQ from EIC VDDCORE WFI instruction CPU state run standby sleep mode run interrupt handler CLK_CPU ON OFF ON clock startup Low Power regulator Main regulator PL2 Main regulator PL2 22.6.6 Sleepwalking with Dynamic Power Domain Gating in Details To reduce power consumption even further, Sleepwalking with dynamic Power Domain Gating (also referred to as "Dynamic Sleepwalking") is used to turn power domain state from retention to active and vice-versa, based on event or DMA trigger. 22.6.6.1 Dynamic SleepWalking based on Event To enable SleepWalking with dynamic power domain gating, the Dynamic Power Gating for Power Domain SW bit in the Standby Configuration register (STDBYCFG.DPGPDSW) has to be written to '1'. When in retention state, a power domain can be automatically set to active state by the PM if an event is directed to this power domain. In this device, this concerns the event users located in power domain PDSW. • When PDSW is in retention state, dynamic SleepWalking can be triggered by: – AC output event – RTC output event – EIC output event (if using the CLK_ULP32K clock and debouncing is enabled) Refer also to 22.6.1.2 Power Domains. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 258 Dynamic SleepWalking based on event is illustrated in the following example: Figure 22-8. Dynamic SleepWalking based on Event: AC Periodic Comparison PDSW active retention active IRQ from AC WFI instruction CPU state run standby sleep mode run interrupt handler AC conversion NO YES NO YES dynamic power sleepwalking CPU PDSW PM PDAO Main Supply active state IRQ DPGPDSW OSCULP32K RTC EVSYS AC_COMPX RTC_PERX RTC_perx dynamic power sleepwalking active PDAO active AC RUNSTDBY The Analog Comparator (AC) peripheral is used in single shot mode to monitor voltage levels on input pins. A comparator interrupt, based on the AC peripheral configuration, is generated to wake up the device. In the GCLK module, the AC generic clock (GCLK_AC) source is routed a 32.768kHz oscillator (for low power applications, OSC32KULP is recommended). RTC and EVSYS modules are configured to generate periodic events to the AC. To make the comparator continue to run in standby sleep mode, the RUNSTDBY bit is written to '1'. To enable the dynamic SleepWalking for PDSW power domain, STDBYCFG.PDSW must be written to '1'. Entering standby mode: The Power Manager sets the PDSW power domain in retention state. The AC comparators, COMPx, are OFF. The GCLK_AC clock is stopped. The VDDCORE is supplied by the low power regulator. Dynamic SleepWalking: The RTC event (RTC_PERX) is routed by the Event System to the Analog Comparator to trigger a single-shot measurement. This event is detected by the Power Manager, which sets the PDSW power domain to active state and starts the main voltage regulator. After enabling the AC comparator and starting the GCLK_AC, the single-shot measurement can be performed during Sleep mode (sleepwalking task), refer to 42.6.14.2 Single-Shot Measurement during Sleep for details. At the end of the conversion, if conditions to generate an interrupt are not met, the GCLK_AC clock is stopped again, as well as the AC comparator. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 259 The low-power regulator starts again and the PDSW power domain is set back to retention state by the PM. During this dynamic SleepWalking period, the CPU is still sleeping. Exiting standby mode: during the dynamic SleepWalking sequence, if conditions are met, the AC module generates an interrupt to wake up the device. Related Links 27. RTC – Real-Time Counter 33. EVSYS – Event System 22.6.6.2 Dynamic SleepWalking Based on Peripheral DMA Trigger To enable this advanced feature, the Dynamic Power Gating for Power Domain SW bit in the Standby Configuration register (STDBYCFG.DPGPDSW) have to be written to '1'. When in retention state, the power domain PDSW (containing the DMAC) can be automatically set to active state if the PM detects a valid DMA trigger that is coming from a peripheral located in PDAO. A peripheral DMA trigger is valid if the corresponding DMA channel is enabled and its Run in Standby bit (RUNSTDBY) is written to '1'. This is illustrated in the following example: Figure 22-9. Dynamic Sleepwalking based on Peripheral DMA Trigger PM PDAO Main Supply active state DPGPDSW OSCULP32K RTC dma_dreq_timestamp PDSW active retention active IRQ from DMAC WFI instruction CPU state run standby sleep mode run interrupt handler RTC_perx dynamic power sleepwalking active DMA_REQ DMA transfer NO YES NO YES dynamic power sleepwalking active DMA_REQ PDAO active CPU PDSW DMAC IRQ RAM DMA destination RUNSTDBY SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 260 The DMAC is configured to operate in standby sleep mode by using its respective RUNSTDBY bit. A DMAC channel is configured to set the DMA destination. The Run in Standby bit of this DMAC channel is written to '1' to allow it running in Standby Sleep mode. Entering Standby mode: The Power Manager peripheral sets PDSW to retention state. The VDDCORE is supplied by the low-power regulator. Dynamic SleepWalking: based on RTC conditions, an RTC output signal (DMA request for timestamp) triggers DMAC to put timestamp value at configured DMA destination. This event is detected by the Power Manager which sets the PDSW power domain to active state and starts the main voltage regulator. This DMA transfer request is detected by the PM, which sets PDSW (containing the DMAC) to active state. The DMAC requests the CLK_DMAC_AHB clock and transfer the timestamp value to the memory. When the DMA beat transfer is completed, the CLK_DMAC_AHB clock is stopped again. The low-power regulator starts again and the PDSW power domain is set back to retention state by the PM. Note that during this dynamic SleepWalking period, the CPU is still sleeping. Exiting Standby mode: during SleepWalking with Dynamic Power Gating sequence, if conditions are met, the DMAC generates an interrupt to wake up the device. Related Links 27. RTC – Real-Time Counter 33. EVSYS – Event System 22.6.7 DMA Operation Not applicable. 22.6.8 Interrupts The peripheral has the following interrupt sources: • Performance Level Ready (PLRDY) This interrupt is a synchronous wake-up source. See Table 22-1 for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. Refer to the Nested Vector Interrupt Controller (NVIC) for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is present. 22.6.9 Events Not applicable. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 261 22.6.10 Sleep Mode Operation The Power Manager is always active. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 262 22.7 Register Summary Offset Name Bit Pos. 0x01 SLEEPCFG 7:0 SLEEPMODE[2:0] 0x02 PLCFG 7:0 PLDIS PLSEL[1:0] 0x03 PWCFG 7:0 RAMPSWC[1:0] 0x04 INTENCLR 7:0 PLRDY 0x05 INTENSET 7:0 PLRDY 0x06 INTFLAG 7:0 PLRDY 0x07 Reserved 0x08 STDBYCFG 7:0 VREGSMOD[1:0] DPGPDSW PDCFG 15:8 BBIASTR BBIASHS 22.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 22.5.7 Register Access Protection. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 263 22.8.1 Sleep Configuration Name:  SLEEPCFG Offset:  0x01 Reset:  0x2 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 SLEEPMODE[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SLEEPMODE[2:0] Sleep Mode Note:  A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software has to make sure the SLEEPCFG register reads the wanted value before issuing WFI instruction. Value Name Definition 0x0 Reserved Reserved 0x1 Reserved Reserved 0x2 IDLE CPU, AHBx, and APBx clocks are OFF 0x3 Reserved Reserved 0x4 STANDBY ALL clocks are OFF, unless requested by sleepwalking peripheral 0x5 Reserved Reserved 0x6 OFF All power domains are powered OFF 0x7 Reserved Reserved SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 264 22.8.2 Performance Level Configuration Name:  PLCFG Offset:  0x02 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 PLDIS PLSEL[1:0] Access R/W R/W R/W Reset 0 0 0 Bit 7 – PLDIS Performance Level Disable Disabling the automatic PL selection forces the device to run in PL0 , reducing the power consumption and the wake-up time from standby sleep mode. Changing this bit when the current performance level is not PL0 is discarded and a violation is reported to the PAC module. Value Description 0 The Performance Level mechanism is enabled. 1 The Performance Level mechanism is disabled. Bits 1:0 – PLSEL[1:0] Performance Level Select Value Name Definition 0x0 PL0 Performance Level 0 0x1 Reserved Reserved 0x2 PL2 Performance Level 2 0x3 Reserved Reserved SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 265 22.8.3 Power Configuration Name:  PWCFG Offset:  0x03 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 RAMPSWC[1:0] Access R/W R/W Reset 0 0 Bits 1:0 – RAMPSWC[1:0] RAM Power Switch Configuration Value Name Definition 0x0 16KB 16KB Available 0x1 12KB 12KB Available 0x2 8KB 8KB Available 0x3 4KB 4KB Available SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 266 22.8.4 Interrupt Enable Clear Name:  INTENCLR Offset:  0x04 Reset:  0x00 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 PLRDY Access R/W Reset 0 Bit 0 – PLRDY Performance Level Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Performance Ready Interrupt Enable bit and the corresponding interrupt request. Value Description 0 The Performance Ready interrupt is disabled. 1 The Performance Ready interrupt is enabled and will generate an interrupt request when the Performance Ready Interrupt Flag is set. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 267 22.8.5 Interrupt Enable Set Name:  INTENSET Offset:  0x05 Reset:  0x00 Property:  PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 PLRDY Access R/W Reset 0 Bit 0 – PLRDY Performance Level Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Performance Ready Interrupt Enable bit and enable the Performance Ready interrupt. Value Description 0 The Performance Ready interrupt is disabled. 1 The Performance Ready interrupt is enabled. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 268 22.8.6 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x06 Reset:  0x00 Property:  – Bit 7 6 5 4 3 2 1 0 PLRDY Access R/W Reset 0 Bit 0 – PLRDY Performance Level Ready This flag is set when the performance level is ready and will generate an interrupt if INTENCLR/ SET.PLRDY is '1'. Writing a '1' to this bit has no effect. Writing a '1' to this bit clears the Performance Ready interrupt flag. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 269 22.8.7 Standby Configuration Name:  STDBYCFG Offset:  0x08 Reset:  0x0000 Property:  PAC Write-Protection Bit 15 14 13 12 11 10 9 8 BBIASTR BBIASHS Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 VREGSMOD[1:0] DPGPDSW PDCFG Access R R R/W R/W Reset 0 0 0 0 Bit 12 – BBIASTR Back Bias for Trust RAM Refer to 22.6.4.2 RAM Automatic Low Power Mode for details. Value Description 0 Retention Back Biasing mode 1 Standby Back Biasing mode Bit 10 – BBIASHS Back Bias for HMCRAMCHS Refer to 22.6.4.2 RAM Automatic Low Power Mode for details. Value Description 0 Retention Back Biasing mode 1 Standby Back Biasing mode Bits 7:6 – VREGSMOD[1:0] VREG Switching Mode Refer to 22.6.4.4 Regulator Automatic Low Power Mode for details. Value Name Description 0x0 AUTO Automatic Mode 0x1 PERFORMANCE Performance oriented 0x2 LP Low Power consumption oriented Bit 4 – DPGPDSW Dynamic Power Gating for Switchable Power Domain Value Description 0 Dynamic SleepWalking for switchable power domain is disabled 1 Dynamic SleepWalking for switchable power domain PDSW is enabled Bit 0 – PDCFG Power Domain Configuration Value Name Description 0x0 DEFAULT In standby mode, all power domain switching are handled by hardware. 0x1 PDSW In standby mode, PDSW is forced ACTIVE. SAM L10/L11 Family PM – Power Manager © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 270 23. OSCCTRL – Oscillators Controller 23.1 Overview The Oscillators Controller (OSCCTRL) provides a user interface to the XOSC, OSC16M, DFLLULP and FDPLL96M. Through the interface registers, it is possible to enable, disable, calibrate, and monitor the OSCCTRL oscillators. All oscillators statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers. 23.2 Features • 0.4-32MHz Crystal Oscillator (XOSC) – Tunable gain control – Programmable start-up time – Crystal or external input clock on XIN I/O – Clock failure detection with safe clock switch – Clock failure event output • 16MHz Internal Oscillator (OSC16M) – Fast startup – 4/8/12/16MHz output frequencies available • Ultra Low-Power Digital Frequency Locked Loop (DFLLULP) – Operates as a frequency multiplier against a known frequency in closed loop mode – Optional frequency dithering • Fractional Digital Phase Locked Loop (FDPLL96M) – 32 MHz to 96 MHz output frequency – 32 kHz to 2MHz reference clock – A selection of sources for the reference clock – Adjustable proportional integral controller – Fractional part used to achieve 1/16th of reference clock step SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 271 23.3 Block Diagram Figure 23-1. OSCCTRL Block Diagram OSCILLATORS CONTROL STATUS INTERRUPTS GENERATOR Interrupts OSCCTRL XINXOUT XOSC OSC16M FDPLL96M CLK_XOSC CLK_OSC16M CLK_DPLL CFD CFD Event register DFLLULP CLK_DFLLULP 23.4 Signal Description Signal Description Type XIN Multipurpose Crystal Oscillator or external clock generator input Analog input XOUT Multipurpose Crystal Oscillator output Analog output The I/O lines are automatically selected when XOSC is enabled. 23.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 23.5.1 I/O Lines I/O lines are configured by OSCCTRL when XOSC is enabled, and need no user configuration. 23.5.2 Power Management The OSCCTRL can continue to operate in any sleep mode where the selected source clock is running. The OSCCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Related Links 22. PM – Power Manager 23.5.3 Clocks The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller (GCLK). The available clock sources are XOSC, OSC16M, DFLLULP and FDPLL96M. The OSCCTRL bus clock (CLK_OSCCTRL_APB) can be enabled and disabled in the Main Clock module (MCLK). SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 272 The control logic uses the oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to 23.6.11 Synchronization for further details. A generic clock (GCLK_DFLLULP) is required to clock the DFLLULP tuner in closed-loop operation. This clock must be configured and enabled in the generic clock controller before using the DFLLULP tuner. Refer to the Generic Clock Controller (GCLK) chapter for details. Related Links 19. MCLK – Main Clock 19.6.2.6 Peripheral Clock Masking 23.5.4 DMA Not applicable. 23.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the OSCCTRL interrupts requires the interrupt controller to be configured first. 23.5.6 Events The events of this peripheral are connected to the Event System. Related Links 33. EVSYS – Event System 23.5.7 Debug Operation When the CPU is halted in debug mode the OSCCTRL continues normal operation. If the OSCCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 23.5.8 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: • Interrupt Flag Status and Clear register (INTFLAG) Note:  Optional write-protection is indicated by the "PAC Write-Protection" property in the register description. Write-protection does not apply for accesses through an external debugger. 23.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 273 23.5.10 Analog Connections The 0.4-32MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors. 23.6 Functional Description 23.6.1 Principle of Operation XOSC, OSC16M, and FDPLL96M. are configured via OSCCTRL control registers. Through this interface, the oscillators are enabled, disabled, or have their calibration values updated. The Status register gathers different status signals coming from the oscillators controlled by the OSCCTRL. The status signals can be used to generate system interrupts, and in some cases wake the system from Sleep mode, provided the corresponding interrupt is enabled. 23.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation The XOSC can operate in two different modes: • External clock, with an external clock signal connected to the XIN pin • Crystal oscillator, with an external 0.4-32MHz crystal The XOSC can be used as a clock source for generic clock generators. This is configured by the Generic Clock Controller. At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the OSCCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN pin will be overridden and controlled by the OSCCTRL, while the XOUT pin can still be used as a GPIO pin. The XOSC is enabled by writing a '1' to the Enable bit in the External Multipurpose Crystal Oscillator Control register (XOSCCTRL.ENABLE). To enable XOSC as an external crystal oscillator, the XTAL Enable bit (XOSCCTRL.XTALEN) must be written to '1'. If XOSCCTRL.XTALEN is zero, the external clock input on XIN will be enabled. When in crystal oscillator mode (XOSCCTRL.XTALEN=1), the External Multipurpose Crystal Oscillator Gain (XOSCCTRL.GAIN) must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic Amplitude Gain Control (XOSCCTRL.AMPGC) is '1', the oscillator amplitude will be automatically adjusted, and in most cases result in a lower power consumption. The XOSC will behave differently in different sleep modes, based on the settings of XOSCCTRL.RUNSTDBY, XOSCCTRL.ONDEMAND, and XOSCCTRL.ENABLE. If XOSCCTRL.ENABLE=0, the XOSC will be always stopped. For XOSCCTRL.ENABLE=1, this table is valid: Table 23-1. XOSC Sleep Behavior CPU Mode XOSCCTRL.RUNST DBY XOSCCTRL.ONDEM AND Sleep Behavior Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 274 CPU Mode XOSCCTRL.RUNST DBY XOSCCTRL.ONDEM AND Sleep Behavior Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSCCTRL.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set once the external clock or crystal oscillator is stable and ready to be used as a clock source. An interrupt is generated on a zero-to-one transition on STATUS.XOSCRDY if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. Related Links 18. GCLK - Generic Clock Controller 23.6.3 Clock Failure Detection Operation The Clock Failure Detector (CFD) enables the user to monitor the external clock or crystal oscillator signal provided by the external oscillator (XOSC). The CFD detects failing operation of the XOSC clock with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also switch from the safe clock back to XOSC in case of recovery. The safe clock is derived from the OSC16M oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller. In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a peripheral. See the Sleep Behavior table above when this is the case. The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is detected. Clock Failure Detection The CFD is disabled at reset. The CFD does not monitor the XOSC clock when the oscillator is disabled (XOSCCTRL.ENABLE=0). Before starting CFD operation, the user must start and enable the safe clock source (OSC16M oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (XOCCTRL.CFDEN). After starting or restarting the XOSC, the CFD does not detect failure until the startup time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal Oscillator Control register (XOSCCTRL.STARTUP). Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored. During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC. There must be at least one rising and one falling XOSC clock edge during 4 safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 275 interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated, too. After a clock failure was issued the monitoring of the XOSC clock is continued, and the Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC activity. Clock Switch When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active clock during the XOSC clock failure. The safe clock source is the OSC16M oscillator clock. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC clock is switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set. When the CFD has switched to the safe clock, the XOSC is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. If the application can recover the XOSC, the application can switch back to the XOSC clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register (XOSCCTRL.SWBACK). Once the XOSC clock is switched back, the Switch Back bit (XOSCCTRL.SWBACK) is cleared by hardware. Prescaler The CFD has an internal configurable prescaler to generate the safe clock from the OSC16M oscillator. The prescaler size allows to scale down the OSC16M oscillator so the safe clock frequency is not higher than the XOSC clock frequency monitored by the CFD. The division factor is 2^P, with P being the value of the CFD Prescaler bits in the CFD Prescaler Register (CFDPRESC.CFDPRESC). Example 23-1.  For an external crystal oscillator at 0.4 MHz and the OSC16M frequency at 16 MHz, the CFDPRESC.CFDPRESC value should be set scale down by more than factor 16/0.4=80, for example 128, for a safe clock of adequate frequency. Event If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC and the peripheral clock request. For further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes. 23.6.4 16MHz Internal Oscillator (OSC16M) Operation The OSC16M is an internal oscillator operating in open-loop mode and generating 4, 8, 12, or 16MHz frequency. The OSC16M frequency is selected by writing to the Frequency Select field in the OSC16M register (OSC16MCTRL.FSEL). OSC16M is enabled by writing '1' to the Oscillator Enable bit in the OSC16M Control register (OSC16MCTRL.ENABLE), and disabled by writing a '0' to this bit. Frequency selection must be done when OSC16M is disabled. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 276 After enabling OSC16M, the OSC16M clock is output as soon as the oscillator is ready (STATUS.OSC16MRDY=1). User must ensure that the OSC16M is fully disabled before enabling it by reading STATUS.OSC16MRDY=0. After reset, OSC16M is enabled and serves as the default clock source at 4MHz. OSC16M will behave differently in different sleep modes based on the settings of OSC16MCTRL.RUNSTDBY, OSC16MCTRL.ONDEMAND, and OSC16MCTRL.ENABLE. If OSC16MCTRL.ENABLE=0, the OSC16M will be always stopped. For OSC16MCTRL.ENABLE=1, this table is valid: Table 23-2. OSC16M Sleep Behavior CPU Mode OSC16MCTRL.RUN STDBY OSC16MCTRL.OND EMAND Sleep Behavior Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral OSC16M is used as a clock source for the generic clock generators. This is configured by the Generic Clock Generator Controller. Related Links 18. GCLK - Generic Clock Controller 23.6.5 Ultra Low-Power Digital Frequency Locked Loop (DFLLULP) Operation The Ultra Low-Power Digital Frequency Locked Loop (DFLLULP) is an internal oscillator that can output a selectable frequency based on user inputs. The frequency is a multiplication ratio relative to a given reference clock using the tuning feature. The oscillator has to be enabled for the tuner to work. Figure 23-2. Block Diagram 23.6.5.1 Basic Operation 23.6.5.1.1 Initialization The following bits are enable-protected, meaning that they can only be written when the DFLLULP is disabled (DFLLULPCTRL.ENABLE is zero): • Binary Search Enable bit in Control register (DFLLULPCTRL.BINSE) • Safe Mode bit in Control register (DFLLULPCTRL.SAFE) • Dither Mode bit in Control register (DFLLULPCTRL.DITHER) • Division Factor bits in Control register (DFLLULPCTRL.DIV) The following registers are enable-protected: • Dither Control register (DFLLULPDITHER) • Target Ratio register (DFLLULPRATIO) Enable-protected bits in the DFLLULPCTRL register can be written at the same time as DFLLULPCTRL.ENABLE is written to one, but not at the same time as DFLLULPCTRL.ENABLE is written to zero. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 277 Enable-protection is denoted by the Enable-Protected property in the register description. 23.6.5.1.2 Enabling and Disabling The DFLLULP is enabled by writing a one to the Enable bit in the Control register (DFLLULPCTRL.ENABLE). The DFLLULP is disabled by writing a zero to DFLLULPCTRL.ENABLE. 23.6.5.1.3 Closed Loop Mode In closed loop mode the frequency is controlled by a tuner which measures the ratio between the DFLLULP output frequency and reference clock frequency. The reference clock is provided by a generic clock. The target ratio is written to the RATIO field in the Target Ratio Register (DFLLULPRATIO). When the oscillator is enabled, the output frequency will be tuned to the target frequency. When the tuning is finished, the Lock bit in the OSCCTRL Status Register will be set (STATUS.DFLLULPLOCK). The No Lock bit in the Status register (STATUS.DFLLULPNOLOCK) will be set to indicate whether a frequency lock is achieved or not. The No Lock bit should be checked after the Lock bit has been set. Lock status is cleared only if the tuner is disabled or a new value is written to DFLLULPDLY. The DFLLULP will attempt to track any variation in the internal oscillator or reference clock, and will not release the lock. No Lock may be set after lock is achieved if the tuner ever reaches the minimum or maximum delay value. Tuning starts from the delay value in DFLLULPDLY.DELAY. A write to DFLLULPDLY.DELAY while tuning is in progress will restart tuning from the newly written value. The tuned delay value can be read back from DFLLULPDLY.DELAY after requesting a synchronization via the Read Request bit in the DFLLULPRREQ register. The accuracy of the tuner frequency comparison is limited by the inverse of the target ratio (1/RATIO). Larger ratios, i.e. much slower reference clocks will give better results. 23.6.5.1.4 Binary Search By default, the tuner starts from the current value of the DFLLULPDLY register and increments or decrements every reference clock period. This linear search can take up to a maximum of 256 reference clock cycles before lock. To speed up the time to lock, binary search can be enabled by writing one to the Binary Search Enable bit in the Control register (DFLLULPCTRL.BINSE). Binary search takes a maximum of 8 reference clock cycles to lock. After 8 reference clock cycles the tuner will operate in normal linear mode to track any changes in the frequency. Note that neither search algorithm is guaranteed to lock if the target ratio is outside of the oscillator tunable range. Binary search will induce large swings in the oscillator frequency. If this is not desirable, an optional safe mode can be used to mask the output clock until the search is complete. Safe mode is enabled by writing a one to the Safe Mode bit in the Control register (DFLLULPCTRL.SAFE). The binary search is re-triggered if there is a write to DFLLULPDLY, or if the tuner is disabled and re-enabled. Ondemand or sleep modes will not retrigger the binary search. If binary search will be used with ondemand behavior, it is recommended to first enable the tuner with DFLLULPCTRL.ONDEMAND=0 and then set DFLLULPCTRL.ONDEMAND=1 after the tuner has locked. This will ensure that each request will start from the locked state. 23.6.5.1.5 Dithering Dithering operation can improve the precision of the closed-loop tuner. Dithering works on two aspects: the delay step size and the comparator resolution. Normally the delay can only be changed in steps of one unit of the 8-bit delay field every reference clock period, for a total of 256 steps. Dithering allows for 8-bits of fractional delay value by automatically changing between DELAY and DELAY+1 values with a weight determined by the tuner. This also has the effect of smoothing the frequency over time. Dithering is therefore equivalent to 16-bits of delay value. If this full range is not needed, the step size can be increased by writing the Step Size field in the Dithering register (DFLLULPDITHER.STEP). By default the frequency comparator resolution is limited to 1/RATIO over a single reference clock period. In dithering operation, the comparator resolution can be made finer by comparing over multiple reference clock SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 278 periods. This behavior is controlled by the Period field in the Dithering register (DFLLULPDITHER.PER). The fine control offered by dithering means that the tuner will take longer to adjust to coarse changes in the frequency. When dithering mode is active, the tuner will attempt to get close to the final locked value before starting the dithering engine. Dithering mode can be restarted if there is a write to DFLLULPDLY, or if the tuner is disabled and re-enabled. 23.6.6 Event Triggered Tuning The EVCTRL.TUNEEI and EVCTRL.TUNEINV control bits allow to start a tuning sequence on an incoming event or inverted event. On an incoming rising or falling edge of the event input, the DFLLULP close loop tuner unlock and start over a frequency tuning, depending on the configuration of the DFLLULP registers, until the tuner achieves a new lock. 23.6.7 Digital Phase Locked Loop (DPLL) Operation The task of the DPLL is to maintain coherence between the input (reference) signal and the respective output frequency, CLK_DPLL, via phase comparison. The DPLL controller supports three independent sources of reference clocks: • XOSC32K: this clock is provided by the 32K External Crystal Oscillator (XOSC32K). • XOSC: this clock is provided by the External Multipurpose Crystal Oscillator (XOSC). • GCLK: this clock is provided by the Generic Clock Controller. When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is: ݂CK = ݂CKR × LDR + 1 + LDRFRAC 16 × 1 2 PRESC Where fCK is the frequency of the DPLL output clock, LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fCKR is the frequency of the selected reference clock, and PRESC is the output prescaler value. Figure 23-3. DPLL Block Diagram XIN XOUT XOSC XIN32 XOUT32 XOSC32K GCLK_DPLL DIVIDER DPLLCTRLB.DIV DPLLCTRLB.REFCLK TDC DIGITAL FILTER DPLLCTRLB.FILTER DCO CKDIV4 CKDIV2 CKDIV1 DPLLPRESC CLK_DPLL RATIO DPLLRATIO CK CKR CG When the controller is disabled, the output clock is low. If the Loop Divider Ratio Fractional part bit field in the DPLL Ratio register (DPLLRATIO.LDRFRAC) is zero, the DPLL works in integer mode. Otherwise, the fractional mode is activated. Note that the fractional part has a negative impact on the jitter of the DPLL. Example (integer mode only): assuming FCKR = 32kHz and FCK = 48MHz, the multiplication ratio is 1500. It means that LDR shall be set to 1499. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 279 Example (fractional mode): assuming FCKR = 32kHz and FCK = 48.006MHz, the multiplication ratio is 1500.1875 (1500 + 3/16). Thus LDR is set to 1499 and LDRFRAC to 3. Related Links 18. GCLK - Generic Clock Controller 24. OSC32KCTRL – 32KHz Oscillators Controller 23.6.7.1 Basic Operation 23.6.7.1.1 Initialization, Enabling, Disabling, and Resetting The DPLLC is enabled by writing a '1' to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The DPLLC is disabled by writing a zero to this bit. The DPLLSYNCBUSY.ENABLE is set when the DPLLCTRLA.ENABLE bit is modified. It is cleared when the DPLL output clock CK has sampled the bit at the high level after enabling the DPLL. When disabling the DPLL, DPLLSYNCBUSY.ENABLE is cleared when the output clock is no longer running. Figure 23-4. Enable Synchronization Busy Operation ENABLE CK SYNCBUSY.ENABLE CLK_APB_OSCCTRL The frequency of the DPLL output clock CK is stable when the module is enabled and when the Lock bit in the DPLL Status register is set (DPLLSTATUS.LOCK). When the Lock Time bit field in the DPLL Control B register (DPLLCTRLB.LTIME) is non-zero, a user defined lock time is used to validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME=0, the lock signal is linked with the status bit of the DPLL, and the lock time varies depending on the filter selection and the final target frequency. Note:  GCLK_DPLL_32K is responsible for counting the user defined lock time (LTIME different from 0x0), hence must be enabled. When the Wake Up Fast bit (DPLLCTRLB.WUF) is set, the wake up fast mode is activated. In this mode the clock gating cell is enabled at the end of the startup time. At this time the final frequency is not stable, as it is still during the acquisition period, but it allows to save several milliseconds. After first acquisition, the Lock Bypass bit (DPLLCTRLB.LBYPASS) indicates if the lock signal is discarded from the control of the clock gater (CG) generating the output clock CLK_DPLL. Table 23-3. CLK_DPLL Behavior from Startup to First Edge Detection WUF LTIME CLK_DPLL Behavior 0 0 Normal Mode: First Edge when lock is asserted 0 Not Equal To Zero Lock Timer Timeout mode: First Edge when the timer down-counts to 0. 1 X Wake Up Fast Mode: First Edge when CK is active (startup time) SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 280 Table 23-4. CLK_DPLL Behavior after First Edge Detection LBYPASS CLK_DPLL Behavior 0 Normal Mode: the CLK_DPLL is turned off when lock signal is low. 1 Lock Bypass Mode: the CLK_DPLL is always running, lock is irrelevant. Figure 23-5. CK and CLK_DPLL Output from DPLL Off Mode to Running Mode CKR ENABLE CK LOCK tstartup_time tlock_time CK STABLE CLK_DPLL 23.6.7.1.2 Reference Clock Switching When a software operation requires reference clock switching, the recommended procedure is to turn the DPLL into the standby mode, modify the DPLLCTRLB.REFCLK to select the desired reference source, and activate the DPLL again. 23.6.7.1.3 Output Clock Prescaler The DPLL controller includes an output prescaler. This prescaler provides three selectable output clocks CK, CKDIV2 and CKDIV4. The Prescaler bit field in the DPLL Prescaler register (DPLLPRESC.PRESC) is used to select a new output clock prescaler. When the prescaler field is modified, the DPLLSYNCBUSY.DPLLPRESC bit is set. It will be cleared by hardware when the synchronization is over. Figure 23-6. Output Clock Switching Operation CKR PRESC CLK_DPLL DPLL_LOCK 0 1 CK STABLE CK SWITCHING CK STABLE SYNCBUSY.PRESC CK CKDIV2 23.6.7.1.4 Loop Divider Ratio Updates The DPLL Controller supports on-the-fly update of the DPLL Ratio Control (DPLLRATIO) register, allowing to modify the loop divider ratio and the loop divider ratio fractional part when the DPLL is enabled. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 281 STATUS.DPLLLDRTO is set when the DPLLRATIO register has been modified and the DPLL analog cell has successfully sampled the updated value. At that time the DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a stable state. Figure 23-7. RATIOCTRL register update operation CKR LDR LDRFRAC CK CLK_DPLL mult0 mult1 LOCK LOCKL 23.6.7.1.5 Digital Filter Selection The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and jitter. Nevertheless a software operation can override the filter setting using the Filter bit field in the DPLL Control B register (DPLLCTRLB.FILTER). The Low Power Enable bit (DPLLCTRLB.LPEN) can be use to bypass the Time to Digital Converter (TDC) module. 23.6.8 DMA Operation Not applicable. 23.6.9 Interrupts The OSCCTRL has the following interrupt sources: • XOSCRDY - Multipurpose Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSCRDY bit is detected • CLKFAIL - Clock Failure. A 0-to-1 transition on the STATUS.CLKFAIL bit is detected • OSC16MRDY - 16MHz Internal Oscillator Ready: A 0-to-1 transition on the STATUS.OSC16MRDY bit is detected • DFLLULP-related: – DFLLULPRDY - DFLLULP Ready: A 0-to1 transition of the STATUS.DFLLULPRDY bit is detected. – DFLLULPLOCK - DFLLULP Lock: A 0-to-1 transition of the STATUS.DFLLULPLOCK bit is detected. – DFLLULPNOLOCK - DFLLULP No Lock: A 0-to-1 transition of the STATUS.DFLLULPNOLOCK bit is detected. • DPLL-related: – DPLLLOCKR - DPLL Lock Rise: A 0-to-1 transition of the STATUS.DPLLLOCKR bit is detected – DPLLLOCKF - DPLL Lock Fall: A 0-to-1 transition of the STATUS.DPLLLOCKF bit is detected – DPLLLTTO - DPLL Lock Timer Time-out: A 0-to-1 transition of the STATUS.DPLLLTTO bit is detected – DPLLLDRTO - DPLL Loop Divider Ratio Update Complete. A 0-to-1 transition of the STATUS.DPLLLDRTO bit is detected SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 282 All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the OSCCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags. The OSCCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details. Note:  The interrupts must be globally enabled for interrupt requests to be generated. 23.6.10 Events The CFD can generate the following output event: • Clock Failure (CLKFAIL): Generated when the Clock Failure status bit is set in the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.CLKSW) in the Status register is set. Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system. The DFLLULP can take the following actions on an input event: • Unlock the DFLLULP close loop tuner and start over a frequency tuning, depending on the settings of the DFLLULP registers, until the tuner achieves a new lock. Writing a '1' to the Event Input Enable bit in the Event Control register (EVCTRL.TUNEEI) enables the corresponding action on input event. Writing a '0' to this bit disables the corresponding action on input event. Refer to the Event System chapter for details on configuring the event system. 23.6.11 Synchronization DFLLULP Due to the asynchronicity between the main clock domain (CLK_OSCCTRL_APB) and the internal clock domain, some registers are synchronized when written. When a write-synchronized register is written, the corresponding bit in the Synchronization Busy register (DFLLULPSYNCBUSY) is set immediately. When the write-synchronization is complete, this bit is cleared. Reading a write-synchronized register while the synchronization is ongoing will return the value written, and not the current value in the peripheral clock domain. To read the current value in the peripheral clock domain after writing a register, the user must wait for the corresponding DFLLULPSYNCBUSY bit to be cleared before reading the value. If a register is written while the corresponding bit in DFLLULPSYNCBUSY is one, the write is discarded and an error is generated. The following bits and registers are write-synchronized: • Delay Value register (DFLLULPDLY) Write-synchronization is denoted by the Write-Synchronized property in the register description. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 283 FDPLL96M Due to the multiple clock domains, some registers in the FDPLL96M must be synchronized when accessed. When executing an operation that requires synchronization, the relevant synchronization bit in the Synchronization Busy register (DPLLSYNCBUSY) will be set immediately, and cleared when synchronization is complete. The following bits need synchronization when written: • Enable bit in control register A (DPLLCTRLA.ENABLE) • DPLL Ratio register (DPLLRATIO) • DPLL Prescaler register (DPLLPRESC) SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 284 23.7 Register Summary Offset Name Bit Pos. 0x00 EVCTRL 7:0 TUNEINV TUNEEI CFDEO 0x01 ... 0x03 Reserved 0x04 INTENCLR 7:0 OSC16MRDY CLKFAIL XOSCRDY 15:8 DFLLULPNOL OCK DFLLULPLOC K DFLLULPRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x08 INTENSET 7:0 OSC16MRDY CLKFAIL XOSCRDY 15:8 DFLLULPNOL OCK DFLLULPLOC K DFLLULPRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x0C INTFLAG 7:0 OSC16MRDY CLKFAIL XOSCRDY 15:8 DFLLULPNOL OCK DFLLULPLOC K DFLLULPRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x10 STATUS 7:0 OSC16MRDY CLKSW CLKFAIL XOSCRDY 15:8 DFLLULPNOL OCK DFLLULPLOC K DFLLULPRDY 23:16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR 31:24 0x14 XOSCCTRL 7:0 ONDEMAND RUNSTDBY SWBACK CFDEN XTALEN ENABLE 15:8 STARTUP[3:0] AMPGC GAIN[2:0] 0x16 CFDPRESC 7:0 CFDPRESC[2:0] 0x17 Reserved 0x18 OSC16MCTRL 7:0 ONDEMAND RUNSTDBY FSEL[1:0] ENABLE 0x19 ... 0x1B Reserved 0x1C DFLLULPCTRL 7:0 ONDEMAND RUNSTDBY DITHER SAFE BINSE ENABLE 15:8 DIV[2:0] 0x1E DFLLULPDITHER 7:0 PER[2:0] STEP[2:0] 0x1F DFLLULPRREQ 7:0 RREQ 0x20 DFLLULPDLY 7:0 DELAY[7:0] 15:8 23:16 31:24 0x24 DFLLULPRATIO 7:0 RATIO[7:0] 15:8 RATIO[10:8] 23:16 31:24 SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 285 Offset Name Bit Pos. 0x28 DFLLULPSYNCBU SY 7:0 DELAY ENABLE 15:8 23:16 31:24 0x2C DPLLCTRLA 7:0 ONDEMAND RUNSTDBY ENABLE 0x2D ... 0x2F Reserved 0x30 DPLLRATIO 7:0 LDR[7:0] 15:8 LDR[11:8] 23:16 LDRFRAC[3:0] 31:24 0x34 DPLLCTRLB 7:0 REFCLK[1:0] WUF LPEN FILTER[1:0] 15:8 LBYPASS LTIME[2:0] 23:16 DIV[7:0] 31:24 DIV[10:8] 0x38 DPLLPRESC 7:0 PRESC[1:0] 0x39 ... 0x3B Reserved 0x3C DPLLSYNCBUSY 7:0 DPLLPRESC DPLLRATIO ENABLE 0x3D ... 0x3F Reserved 0x40 DPLLSTATUS 7:0 CLKRDY LOCK 23.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by the "PAC Write-Protection" property in each individual register description. Refer to the 23.5.8 Register Access Protection section and the PAC - Peripheral Access Controller chapter for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" or "Write-Synchronized" property in each individual register description. Refer to the section on Synchronization for details. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 286 23.8.1 Event Control Name:  EVCTRL Offset:  0x00 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 TUNEINV TUNEEI CFDEO Access R/W R/W R/W Reset 0 0 0 Bit 2 – TUNEINV Tune Event Input Invert This bit is used to invert the input event of the DFLLULP tuner. Value Description 0 Tune event input source is not inverted. 1 Tune event input source is inverted. Bit 1 – TUNEEI Tune Event Input Enable This bit is used to enable the input event of the DFLLULP tuner. Value Description 0 A new closed loop tuning will not be triggered on any incoming event. 1 A new closed loop tuning will be triggered on any incoming event. Bit 0 – CFDEO Clock Failure Detector Event Output Enable This bit indicates whether the Clock Failure detector event output is enabled or not and an output event will be generated when the Clock Failure detector detects a clock failure Value Description 0 Clock Failure detector event output is disabled and no event will be generated. 1 Clock Failure detector event output is enabled and an event will be generated. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 287 23.8.2 Interrupt Enable Clear Name:  INTENCLR Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DFLLULPNOLO CK DFLLULPLOCK DFLLULPRDY Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 OSC16MRDY CLKFAIL XOSCRDY Access R/W R/W R/W Reset 0 0 0 Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Loop Divider Ratio Update Complete Interrupt Enable bit, which disables the DPLL Loop Divider Ratio Update Complete interrupt. Value Description 0 The DPLL Loop Divider Ratio Update Complete interrupt is disabled. 1 The DPLL Loop Divider Ratio Update Complete interrupt is enabled, and an interrupt request will be generated when the DPLL Loop Divider Ratio Update Complete Interrupt flag is set. Bit 18 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 288 Value Description 0 The DPLL Lock Timeout interrupt is disabled. 1 The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Timeout Interrupt flag is set. Bit 17 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled. 1 The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall Interrupt flag is set. Bit 16 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled. 1 The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set. Bit 10 – DFLLULPNOLOCK DFLLULP No Lock Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLLULP No Lock interrupt Enable bit, which disables the DFLLULP No Lock interrupt. Value Description 0 The DFLLULP No Lock is disabled. 1 The DFLLULP No Lock interrupt is enabled, and an interrupt request will be generated when the DFLLULP No Lock Interrupt flag is set. Bit 9 – DFLLULPLOCK DFLLULP Lock Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLLULP Lock Interrupt Enable bit, which disables the DFLLULP Lock interrupt. Value Description 0 The DFLLULP Lock interrupt is disabled. 1 The DFLLULP Lock interrupt is enabled, and an interrupt request will be generated when the DFLLULP Lock Interrupt flag is set. Bit 8 – DFLLULPRDY DFLLULP Ready interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the DFLLULP Ready Interrupt Enable bit, which disables the DFLLULP Ready interrupt. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 289 Value Description 0 The DFLLULP Ready interrupt is disabled. 1 The DFLLULP Ready interrupt is enabled, and an interrupt request will be generated when the DFLLULP Ready Interrupt flag is set. Bit 4 – OSC16MRDY OSC16M Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the OSC16M Ready Interrupt Enable bit, which disables the OSC16M Ready interrupt. Value Description 0 The OSC16M Ready interrupt is disabled. 1 The OSC16M Ready interrupt is enabled, and an interrupt request will be generated when the OSC16M Ready Interrupt flag is set. Bit 1 – CLKFAIL Clock Failure Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Clock Failure Interrupt Enable bit, which disables the XOSC Clock Failure interrupt. Value Description 0 The XOSC Clock Failure interrupt is disabled. 1 The XOSC Clock Failure interrupt is enabled, and an interrupt request will be generated when the XOSC Clock Failure Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled. 1 The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 290 23.8.3 Interrupt Enable Set Name:  INTENSET Offset:  0x08 Reset:  0x00000000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DFLLULPNOLO CK DFLLULPLOCK DFLLULPRDY Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 OSC16MRDY CLKFAIL XOSCRDY Access R/W R/W R/W Reset 0 0 0 Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Loop Ratio Update Complete Interrupt Enable bit, which enables the DPLL Loop Ratio Update Complete interrupt. Value Description 0 The DPLL Loop Divider Ratio Update Complete interrupt is disabled. 1 The DPLL Loop Ratio Update Complete interrupt is enabled, and an interrupt request will be generated when the DPLL Loop Ratio Update Complete Interrupt flag is set. Bit 18 – DPLLLTO DPLL Lock Timeout Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout interrupt. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 291 Value Description 0 The DPLL Lock Timeout interrupt is disabled. 1 The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Timeout Interrupt flag is set. Bit 17 – DPLLLCKF DPLL Lock Fall Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt. Value Description 0 The DPLL Lock Fall interrupt is disabled. 1 The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall Interrupt flag is set. Bit 16 – DPLLLCKR DPLL Lock Rise Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise interrupt. Value Description 0 The DPLL Lock Rise interrupt is disabled. 1 The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise Interrupt flag is set. Bit 10 – DFLLULPNOLOCK DFLLULP No Lock Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLLULP No Lock interrupt Enable bit, which enables the DFLLULP No Lock interrupt. Value Description 0 The DFLLULP No Lock is disabled. 1 The DFLL No Lock interrupt is enabled, and an interrupt request will be generated when the DFLL No Lock Interrupt flag is set. Bit 9 – DFLLULPLOCK DFLLULP Lock Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLLULP Lock Interrupt Enable bit, which enables the DFLLULP Lock interrupt. Value Description 0 The DFLLULP Lock interrupt is disabled. 1 The DFLLULP Lock interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Interrupt flag is set. Bit 8 – DFLLULPRDY DFLLULP Ready interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the DFLLULP Ready Interrupt Enable bit, which enables the DFLLULP Ready interrupt. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 292 Value Description 0 The DFLLULP Ready interrupt is disabled. 1 The DFLLULP Ready interrupt is enabled, and an interrupt request will be generated when the DFLLULP Ready Interrupt flag is set. Bit 4 – OSC16MRDY OSC16M Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the OSC16M Ready Interrupt Enable bit, which enables the OSC16M Ready interrupt. Value Description 0 The OSC16M Ready interrupt is disabled. 1 The OSC16M Ready interrupt is enabled, and an interrupt request will be generated when the OSC16M Ready Interrupt flag is set. Bit 1 – CLKFAIL XOSC Clock Failure Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Clock Failure Interrupt Enable bit, which enables the XOSC Clock Failure Interrupt. Value Description 0 The XOSC Clock Failure Interrupt is disabled. 1 The XOSC Clock Failure Interrupt is enabled, and an interrupt request will be generated when the XOSC Clock Failure Interrupt flag is set. Bit 0 – XOSCRDY XOSC Ready Interrupt Enable Writing '0' to this bit has no effect. Writing '1' to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt. Value Description 0 The XOSC Ready interrupt is disabled. 1 The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 293 23.8.4 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x0C Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DFLLULPNOLO CK DFLLULPLOCK DFLLULPRDY Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 OSC16MRDY CLKFAIL XOSCRDY Access R/W R/W R/W Reset 0 0 0 Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete This flag is cleared by writing '1' to it. This flag is set on a high to low transition of the DPLL Loop Divider Ratio Update Complete bit in the Status register (STATUS.DPLLLDRTO) and will generate an interrupt request if INTENSET.DPLLLDRTO is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Loop Divider Ratio Update Complete interrupt flag. Bit 18 – DPLLLTO DPLL Lock Timeout This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Timeout bit in the Status register (STATUS.DPLLLTO) and will generate an interrupt request if INTENSET.DPLLLTO is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Timeout interrupt flag. Bit 17 – DPLLLCKF DPLL Lock Fall This flag is cleared by writing '1' to it. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 294 This flag is set on 0-to-1 transition of the DPLL Lock Fall bit in the Status register (STATUS.DPLLLCKF) and will generate an interrupt request if INTENSET.DPLLLCKF is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Fall interrupt flag. Bit 16 – DPLLLCKR DPLL Lock Rise This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DPLL Lock Rise bit in the Status register (STATUS.DPLLLCKR) and will generate an interrupt request if INTENSET.DPLLLCKR is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DPLL Lock Rise interrupt flag. Bit 10 – DFLLULPNOLOCK DFLLULP No Lock This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLLULP No Lock bit in the Status register (STATUS.DFLLULPNOLOCK) and will generate an interrupt request if INTENSET.DFLLULPNOLOCK is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLLULP No Lock interrupt flag. Bit 9 – DFLLULPLOCK DFLLULP Lock This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLLULP Lock bit in the Status register (STATUS.DFLLULPLOCK) and will generate an interrupt request if INTENSET.DFLLULPLOCK is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLLULP Lock interrupt flag. Bit 8 – DFLLULPRDY DFLLULP Ready This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the DFLLULP Ready bit in the Status register (STATUS.DFLLULPREADY) and will generate an interrupt request if INTENSET.DFLLULPREADY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the DFLLULP Ready interrupt flag. Bit 4 – OSC16MRDY OSC16M Ready This flag is cleared by writing '1' to it. This flag is set on 0-to-1 transition of the OSC16M Ready bit in the Status register (STATUS.OSC16MRDY) and will generate an interrupt request if INTENSET.OSC16MRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the OSC16M Ready interrupt flag. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 295 Bit 1 – CLKFAIL XOSC Failure Detection This flag is cleared by writing '1' to it. This flag is set on a 0-to-1 transition of the XOSC Clock Failure bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Clock Fail interrupt flag. Bit 0 – XOSCRDY XOSC Ready This flag is cleared by writing '1' to it. This flag is set on a 0-to-1 transition of the XOSC Ready bit in the Status register (STATUS.XOSCRDY) and will generate an interrupt request if INTENSET.XOSCRDY is '1'. Writing '0' to this bit has no effect. Writing '1' to this bit clears the XOSC Ready interrupt flag. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 296 23.8.5 Status Name:  STATUS Offset:  0x10 Reset:  0x00000100 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 DPLLLDRTO DPLLLTO DPLLLCKF DPLLLCKR Access R R R R Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 DFLLULPNOLO CK DFLLULPLOCK DFLLULPRDY Access R R R Reset 0 0 1 Bit 7 6 5 4 3 2 1 0 OSC16MRDY CLKSW CLKFAIL XOSCRDY Access R R R R Reset 0 0 0 0 Bit 19 – DPLLLDRTO DPLL Loop Divider Ratio Update Complete Value Description 0 DPLL Loop Divider Ratio Update Complete not detected. 1 DPLL Loop Divider Ratio Update Complete detected. Bit 18 – DPLLLTO DPLL Lock Timeout Value Description 0 DPLL Lock time-out not detected. 1 DPLL Lock time-out detected. Bit 17 – DPLLLCKF DPLL Lock Fall Value Description 0 DPLL Lock fall edge not detected. 1 DPLL Lock fall edge detected. Bit 16 – DPLLLCKR DPLL Lock Rise SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 297 Value Description 0 DPLL Lock rise edge not detected. 1 DPLL Lock rise edge detected. Bit 10 – DFLLULPNOLOCK DFLLULP No Lock Value Description 0 DFLLULP Tuner no lock state is not detected. 1 DFLLULP Tuner no lock state is detected. Bit 9 – DFLLULPLOCK DFLLULP Lock Value Description 0 DFLLULP Tuner lock state is not detected. 1 DFLLULP Tuner lock state is detected. Bit 8 – DFLLULPRDY DFLLULP Ready Value Description 0 DFLLULP is not ready. 1 DFLLULP is stable and ready to be used as a clock source. Bit 4 – OSC16MRDY OSC16M Ready Value Description 0 OSC16M is not ready. 1 OSC16M is stable and ready to be used as a clock source. Bit 2 – CLKSW XOSC Clock Switch Value Description 0 XOSC is not switched and provides the external clock or crystal oscillator clock. 1 XOSC is switched and provides the safe clock. Bit 1 – CLKFAIL XOSC Clock Failure Value Description 0 No XOSC failure detected. 1 A XOSC failure was detected. Bit 0 – XOSCRDY XOSC Ready Value Description 0 XOSC is not ready. 1 XOSC is stable and ready to be used as a clock source. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 298 23.8.6 External Multipurpose Crystal Oscillator (XOSC) Control Name:  XOSCCTRL Offset:  0x14 Reset:  0x0080 Property:  PAC Write-Protection Bit 15 14 13 12 11 10 9 8 STARTUP[3:0] AMPGC GAIN[2:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY SWBACK CFDEN XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bits 15:12 – STARTUP[3:0] Start-Up Time These bits select start-up time for the oscillator. The OSCULP32K oscillator is used to clock the start-up counter. Table 23-5. Start-Up Time for External Multipurpose Crystal Oscillator STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time [µs] 0x0 1 3 31 0x1 2 3 61 0x2 4 3 122 0x3 8 3 244 0x4 16 3 488 0x5 32 3 977 0x6 64 3 1953 0x7 128 3 3906 0x8 256 3 7813 0x9 512 3 15625 0xA 1024 3 31250 0xB 2048 3 62500µs 0xC 4096 3 125000 0xD 8192 3 250000 SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 299 STARTUP[3:0] Number of OSCULP32K Clock Cycles Number of XOSC Clock Cycles Approximate Equivalent Time [µs] 0xE 16384 3 500000 0xF 32768 3 1000000 Note:  1. Actual startup time is 1 OSCULP32K cycle + 3 XOSC cycles. 2. The given time neglects the three XOSC cycles before OSCULP32K cycle. Bit 11 – AMPGC Automatic Amplitude Gain Control Note:  This bit must be set only after the XOSC has settled, indicated by the XOSC Ready flag in the Status register (STATUS.XOSCRDY). Value Description 0 The automatic amplitude gain control is disabled. 1 The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal Oscillator operation. Bits 10:8 – GAIN[2:0] Oscillator Gain These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary based on capacitive load and crystal characteristics. Those bits must be properly configured even when the Automatic Amplitude Gain Control is active. Value Recommended Max Frequency [MHz] 0x0 2 0x1 4 0x2 8 0x3 16 0x4 30 0x5-0x7 Reserved Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled, the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 300 Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC behaves during Standby Sleep mode, together with the ONDEMAND bit: Value Description 0 The XOSC is not running in Standby sleep mode if no peripheral requests the clock. 1 The XOSC is running in Standby sleep mode. If ONDEMAND=1, the XOSC will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in Standby sleep mode. Bit 4 – SWBACK Clock Switch Back This bit controls the XOSC output switch back to the external clock or crystal oscillator in case of clock recovery: Value Description 0 The clock switch back is disabled. 1 The clock switch back is enabled. This bit is reset once the XOSC output clock is switched back to the external clock or crystal oscillator. Bit 3 – CFDEN Clock Failure Detector Enable This bit controls the clock failure detector: Value Description 0 The Clock Failure Detector is disabled. 1 the Clock Failure Detector is enabled. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator: Value Description 0 External clock connected on XIN. XOUT can be used as general-purpose I/O. 1 Crystal connected to XIN/XOUT. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 301 23.8.7 Clock Failure Detector Prescaler Name:  CFDPRESC Offset:  0x16 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDPRESC[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – CFDPRESC[2:0] Clock Failure Detector Prescaler These bits select the prescaler for the clock failure detector. The OSC16M oscillator is used to clock the CFD prescaler. The CFD safe clock frequency is the OSC16M frequency divided by 2^CFDPRESC. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 302 23.8.8 16MHz Internal Oscillator (OSC16M) Control Name:  OSC16MCTRL Offset:  0x18 Reset:  0x82 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY FSEL[1:0] ENABLE Access R/W R/W R/W R/W R/W Reset 1 0 0 0 1 Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows the oscillator to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will only be running when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The oscillator is always on, if enabled. 1 The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the OSC16M behaves during standby sleep mode. Value Description 0 The OSC16M is disabled in standby sleep mode if no peripheral requests the clock. 1 The OSC16M is not stopped in standby sleep mode. If ONDEMAND=1, the OSC16M will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in standby sleep mode. Bits 3:2 – FSEL[1:0] Oscillator Frequency Selection These bits control the oscillator frequency range. Value Description 0x00 4MHz 0x01 8MHz 0x10 12MHz 0x11 16MHz Bit 1 – ENABLE Oscillator Enable SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 303 Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 304 23.8.9 DFLLULP Control Name:  DFLLULPCTRL Offset:  0x1C Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected, Write-synchronized Bit 15 14 13 12 11 10 9 8 DIV[2:0] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY DITHER SAFE BINSE ENABLE Access R/W R/W R/W R/W R/W R/W R Reset 0 0 0 0 0 0 0 Bits 10:8 – DIV[2:0] Division Factor This field defines the division factor for the output frequency of the DFLLULP. This value from production test, which depends on PL0 or PL2 mode, must be copied from the NVM software calibration row into the DFLLULPCTRL register by software. The value must be changed before switching on a new Performance Level mode (PL0 or PL2). These bits are not synchronized. Value Name Description 0x0 DIV1 Frequency divided by 1 0x1 DIV2 Frequency divided by 2 0x2 DIV4 Frequency divided by 4 0x3 DIV8 Frequency divided by 8 0x4 DIV16 Frequency divided by 16 0x5 DIV32 Frequency divided by 32 0x6 - 0x7 - Reserved Bit 7 – ONDEMAND On Demand The On Demand operation mode allows the oscillator to be enabled or disabled, depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the oscillator will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator’s clock source, the oscillator will be in a disabled state. If On Demand is disabled, the oscillator will always be running when enabled. In standby sleep mode, the On Demand operation is still active. This bit is not enabled-protected. This bit is not synchronized. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 305 Bit 6 – RUNSTDBY Run in Standby This bit controls how the DFLLULP behaves during standby sleep mode, together with the ONDEMAND bit. This bit is not enabled-protected. This bit is not synchronized Bit 5 – DITHER Tuner Dither Mode This bit is not synchronized. Value Description 0 The dither mode is disabled. 1 The dither mode is enabled if tuning is enabled (DFLLULPCTRL.TUNE = 1). Bit 4 – SAFE Tuner Safe Mode This bit is not synchronized. Value Description 0 The clock output is not masked while binary search tuning is ongoing. 1 The clock output is masked while binary search tuning is ongoing (DFLLULPCTRL.BINSE = 1). Bit 3 – BINSE Binary Search Enable This bit is not synchronized. Value Description 0 Binary search tuning is disabled. Maximum number of reference clock cycles to acquire lock is 256. 1 Binary search tuning is enabled. Maximum number of reference clock cycles to acquire lock is 8. Bit 1 – ENABLE Enable This bit is not enable-protected. Value Description 0 The DFLLULP is disabled. 1 The DFLLULP is enabled. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 306 23.8.10 DFLLULP Dither Control Name:  DFLLULPDITHER Offset:  0x1E Reset:  0x00 Property:  PAC Write-Protection, Enable-Protected Bit 7 6 5 4 3 2 1 0 PER[2:0] STEP[2:0] Access R R/W R/W R/W R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 6:4 – PER[2:0] Dither Period These bits define the number of reference clock periods over which dithering is applied. Value Name Description 0x0 PER1 Dither over 1 reference clock period 0x1 PER2 Dither over 2 reference clock periods 0x2 PER4 Dither over 4 reference clock periods 0x3 PER8 Dither over 8 reference clock periods 0x4 PER16 Dither over 16 reference clock periods 0x5 PER32 Dither over 32 reference clock periods 0x6 - 0x7 - Reserved Bits 2:0 – STEP[2:0] Dither Step This field defines the dithering step size. Value Name Description 0x0 STEP1 Dither step = 1 0x1 STEP2 Dither step = 2 0x2 STEP4 Dither step = 4 0x3 STEP8 Dither step = 8 0x4 - 0x7 - Reserved SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 307 23.8.11 DFLLULP Read Request Name:  DFLLULPRREQ Offset:  0x1F Reset:  0x00 Property:  - Bit 7 6 5 4 3 2 1 0 RREQ Access R/W R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 – RREQ Read Request Writing a zero to this bit has no effect. Writing a one to this bit requests synchronization of the DFLLULPDLY register with the current oscillator delay value and sets the Delay Busy bit in the Synchronization Busy register (DFLLULPSYNCBUSY.DELAY). This bit is cleared automatically when synchronization is complete. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 308 23.8.12 DFLLULP Delay Value Name:  DFLLULPDLY Offset:  0x20 Reset:  0x00000080 Property:  PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DELAY[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 0 Bits 7:0 – DELAY[7:0] Delay Value Writing a value to this field sets the oscillator delay. A small value will produce a fast clock and a large value will produce a slow clock. If the tuner is enabled, writing to this field will cause the tuner to start tuning from the written value. Reading this value will return the last written delay or the oscillator delay when a synchronization was requested from the DFLLULPRREQ register. Writing a value to this register while a write synchronization or a read request synchronization is on-going will have no effect and produce a PAC error. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 309 23.8.13 DFLLULP Target Ratio Name:  DFLLULPRATIO Offset:  0x24 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RATIO[10:8] Access R R R R R R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RATIO[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 0 0 Bits 10:0 – RATIO[10:0] Target Tuner Ratio Writing a value to this field sets the target ratio between the DFLLULP output clock and the reference clock. The DFLLULPDLY.DELAY value will be updated in such a way that the target ratio and the actual ratio are as close as possible. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 310 23.8.14 DFLLULP Synchronization Busy Name:  DFLLULPSYNCBUSY Offset:  0x28 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DELAY ENABLE Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 3 – DELAY Delay Register Synchronization Busy This bit is cleared when the synchronization of DFLLULPDLY is complete. This bit is set when the synchronization of DFLLULPDLY is started. Writing this bit has no effect. Bit 1 – ENABLE Enable Bit Synchronization Busy This bit is cleared when the synchronization of DFLLULPCTRL.ENABLE is complete. This bit is set when the synchronization of DFLLULPCTRL.ENABLE is started. Writing this bit has no effect. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 311 23.8.15 DPLL Control A Name:  DPLLCTRLA Offset:  0x2C Reset:  0x80 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY ENABLE Access R/W R/W R/W Reset 1 0 0 Bit 7 – ONDEMAND On Demand Clock Activation The On Demand operation mode allows the DPLL to be enabled or disabled depending on peripheral clock requests. If the ONDEMAND bit has been previously written to '1', the DPLL will only be running when requested by a peripheral. If there is no peripheral requesting the DPLL’s clock source, the DPLL will be in a disabled state. If On Demand is disabled the DPLL will always be running when enabled. In standby sleep mode, the On Demand operation is still active. Value Description 0 The DPLL is always on, if enabled. 1 The DPLL is enabled when a peripheral is requesting the DPLL to be used as a clock source. The DPLL is disabled if no peripheral is requesting the clock source. Bit 6 – RUNSTDBY Run in Standby This bit controls how the DPLL behaves during standby sleep mode: Value Description 0 The DPLL is disabled in standby sleep mode if no peripheral requests the clock. 1 The DPLL is not stopped in standby sleep mode. If ONDEMAND=1, the DPLL will be running when a peripheral is requesting the clock. If ONDEMAND=0, the clock source will always be running in standby sleep mode. Bit 1 – ENABLE DPLL Enable, Write-Synchronized (ENABLE) The software operation of enabling or disabling the DPLL takes a few clock cycles, so the DPLLSYNCBUSY.ENABLE status bit indicates when the DPLL is successfully enabled or disabled. Value Description 0 The DPLL is disabled. 1 The DPLL is enabled. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 312 23.8.16 DPLL Ratio Control Name:  DPLLRATIO Offset:  0x30 Reset:  0x00000000 Property:  PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LDRFRAC[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LDR[11:8] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 LDR[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 19:16 – LDRFRAC[3:0] Loop Divider Ratio Fractional Part Writing these bits selects the fractional part of the frequency multiplier. Due to synchronization there is a delay between writing these bits and the effect on the DPLL output clock. The value written will read back immediately and the DPLLRATIO bit in the DPLL Synchronization Busy register (DPLLSYNCBUSY.DPLLRATIO) will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. Bits 11:0 – LDR[11:0] Loop Divider Ratio Writing these bits selects the integer part of the frequency multiplier. The value written to these bits will read back immediately, and the DPLLRATIO bit in the DPLL Synchronization busy register (DPLLSYNCBUSY.DPLLRATIO), will be set. DPLLSYNCBUSY.DPLLRATIO will be cleared when the operation is completed. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 313 23.8.17 DPLL Control B Name:  DPLLCTRLB Offset:  0x34 Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 DIV[10:8] Access R/W R/W R/W Reset 0 0 0 Bit 23 22 21 20 19 18 17 16 DIV[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 LBYPASS LTIME[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 REFCLK[1:0] WUF LPEN FILTER[1:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bits 26:16 – DIV[10:0] Clock Divider These bits set the XOSC clock division factor and can be calculated with following formula: = ܸܫܦf ܥܱ݂ܵܺ 1ܸ + ܫܦ ݔ2 Bit 12 – LBYPASS Lock Bypass Value Description 0 DPLL Lock signal drives the DPLL controller internal logic. 1 DPLL Lock signal is always asserted. Bits 10:8 – LTIME[2:0] Lock Time These bits select the lock time-out value: Note:  GCLK_DPLL_32K is responsible for counting the user defined lock time (LTIME different from 0x0), hence must be enabled. Value Name Description 0x0 Default No time-out. Automatic lock. 0x1 Reserved 0x2 Reserved 0x3 Reserved SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 314 Value Name Description 0x4 8MS Time-out if no lock within 8ms 0x5 9MS Time-out if no lock within 9ms 0x6 10MS Time-out if no lock within 10ms 0x7 11MS Time-out if no lock within 11ms Bits 5:4 – REFCLK[1:0] Reference Clock Selection Write these bits to select the DPLL clock reference: Value Name Description 0x0 XOSC32K XOSC32K clock reference 0x1 XOSC XOSC clock reference 0x2 GCLK GCLK_DPLL clock reference 0x3 Reserved - Bit 3 – WUF Wake Up Fast Value Description 0 DPLL clock is output after startup and lock time. 1 DPLL clock is output after startup time. Bit 2 – LPEN Low-Power Enable Value Description 0 The low-power mode is disabled. Time to Digital Converter is enabled. 1 The low-power mode is enabled. Time to Digital Converter is disabled. This will improve power consumption but increase the output jitter. Bits 1:0 – FILTER[1:0] Proportional Integral Filter Selection These bits select the DPLL filter type: Value Name Description 0x0 DEFAULT Default filter mode 0x1 LBFILT Low bandwidth filter 0x2 HBFILT High bandwidth filter 0x3 HDFILT High damping filter SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 315 23.8.18 DPLL Prescaler Name:  DPLLPRESC Offset:  0x38 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 PRESC[1:0] Access R/W R/W Reset 0 0 Bits 1:0 – PRESC[1:0] Output Clock Prescaler These bits define the output clock prescaler setting. Value Name Description 0x0 DIV1 DPLL output is divided by 1 0x1 DIV2 DPLL output is divided by 2 0x2 DIV4 DPLL output is divided by 4 0x3 Reserved SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 316 23.8.19 DPLL Synchronization Busy Name:  DPLLSYNCBUSY Offset:  0x3C Reset:  0x00 Property:  – Bit 7 6 5 4 3 2 1 0 DPLLPRESC DPLLRATIO ENABLE Access R R R Reset 0 0 0 Bit 3 – DPLLPRESC DPLL Prescaler Synchronization Status Value Description 0 The DPLLRESC register has been synchronized. 1 The DPLLRESC register value has changed and its synchronization is in progress. Bit 2 – DPLLRATIO DPLL Loop Divider Ratio Synchronization Status Value Description 0 The DPLLRATIO register has been synchronized. 1 The DPLLRATIO register value has changed and its synchronization is in progress. Bit 1 – ENABLE DPLL Enable Synchronization Status Value Description 0 The DPLLCTRLA.ENABLE bit has been synchronized. 1 The DPLLCTRLA.ENABLE bit value has changed and its synchronization is in progress. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 317 23.8.20 DPLL Status Name:  DPLLSTATUS Offset:  0x40 Reset:  0x00 Property:  – Bit 7 6 5 4 3 2 1 0 CLKRDY LOCK Access R R Reset 0 0 Bit 1 – CLKRDY DPLL Clock Ready Value Description 0 The DPLL output clock is off. 1 The DPLL output clock in on. Bit 0 – LOCK DPLL Lock Value Description 0 The DPLL Lock signal is cleared, when the DPLL is disabled or when the DPLL is trying to reach the target frequency. 1 The DPLL Lock signal is asserted when the desired frequency is reached. SAM L10/L11 Family OSCCTRL – Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 318 24. OSC32KCTRL – 32KHz Oscillators Controller 24.1 Overview The 32KHz Oscillators Controller (OSC32KCTRL) provides a user interface to the 32.768kHz oscillators: XOSC32K and OSCULP32K. The OSC32KCTRL sub-peripherals can be enabled, disabled, calibrated, and monitored through interface registers. All sub-peripheral statuses are collected in the Status register (STATUS). They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers. 24.2 Features • 32.768 kHz Crystal Oscillator (XOSC32K) – Programmable start-up time – Crystal or external input clock on XIN32 I/O – Clock failure detection with safe clock switch – Clock failure event output • 32.768 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) – Ultra low-power, always-on oscillator – Frequency fine tuning • Calibration value loaded from Flash factory calibration at reset • 1.024 kHz clock outputs available SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 319 24.3 Block Diagram Figure 24-1. OSC32KCTRL Block Diagram STATUS register INTERRUPTS GENERATOR Interrupts OSC32KCTRL 32K OSCILLATORS CONTROL XOUT32 XIN32 CLK_XOSC32K CLK_OSCULP32K CFD Event XOSC32K OSCULP32K CFD ULP32KSW 24.4 Signal Description Signal Description Type XIN32 Analog Input 32.768 kHz Crystal Oscillator or external clock input XOUT32 Analog Output 32.768 kHz Crystal Oscillator output The I/O lines are automatically selected when XOSC32K is enabled. Note:  The signal of the external crystal oscillator may affect the jitter of neighboring pads. 24.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 24.5.1 I/O Lines I/O lines are configured by OSC32KCTRL when XOSC32K is enabled, and need no user configuration. 24.5.2 Power Management The OSC32KCTRL will continue to operate in any sleep mode where a 32KHz oscillator is running as source clock. The OSC32KCTRL interrupts can be used to wake up the device from sleep modes. Related Links 22. PM – Power Manager SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 320 24.5.3 Clocks The OSC32KCTRL gathers controls for all 32KHz oscillators and provides clock sources to the Generic Clock Controller (GCLK), Real-Time Counter (RTC), and Watchdog Timer (WDT). The available clock sources are: XOSC32K and OSCULP32K. The OSC32KCTRL bus clock (CLK_OSC32KCTRL_APB) can be enabled and disabled in the Main Clock module (MCLK). Related Links 19.6.2.6 Peripheral Clock Masking 24.5.4 Interrupts The interrupt request lines are connected to the interrupt controller. Using the OSC32KCTRL interrupts requires the interrupt controller to be configured first. 24.5.5 Events The events of this peripheral are connected to the Event System. Related Links 33. EVSYS – Event System 24.5.6 Debug Operation When the CPU is halted in debug mode, OSC32KCTRL will continue normal operation. If OSC32KCTRL is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 24.5.7 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: • Interrupt Flag Status and Clear (INTFLAG) register Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 15. PAC - Peripheral Access Controller 24.5.8 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 321 24.5.9 Analog Connections The external 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, along with any required load capacitors. For details on recommended oscillator characteristics and capacitor load, refer to the related links. 24.6 Functional Description 24.6.1 Principle of Operation XOSC32K and OSCULP32K are configured via OSC32KCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled, or have their calibration values updated. The STATUS register gathers different status signals coming from the sub-peripherals of OSC32KCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from standby mode, provided the corresponding interrupt is enabled. 24.6.2 32KHz External Crystal Oscillator (XOSC32K) Operation The XOSC32K can operate in two different modes: • External clock, with an external clock signal connected to XIN32 • Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32 At reset, the XOSC32K is disabled, and the XIN32/XOUT32 pins can either be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN32 and XOUT32 pins are controlled by the OSC32KCTRL, and GPIO functions are overridden on both pins. When in external clock mode, the only XIN32 pin will be overridden and controlled by the OSC32KCTRL, while the XOUT32 pin can still be used as a GPIO pin. The XOSC32K is enabled by writing a '1' to the Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.ENABLE=1). The XOSC32K is disabled by writing a '0' to the Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.ENABLE=0). To enable the XOSC32K as a crystal oscillator, the XTALEN bit in the 32KHz External Crystal Oscillator Control register must be set (XOSC32K.XTALEN=1). If XOSC32K.XTALEN is '0', the external clock input will be enabled. The XOSC32K 32.768kHz output is enabled by setting the 32KHz Output Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.EN32K=1). The XOSC32K also has a 1.024kHz clock output, which can only be used by the RTC. This clock output is enabled by setting the 1KHz Output Enable bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.EN1K=1). It is also possible to lock the XOSC32K configuration by setting the Write Lock bit in the 32KHz External Crystal Oscillator Control register (XOSC32K.WRTLOCK=1). If set, the XOSC32K configuration is locked until a Power-On Reset (POR) is detected. The XOSC32K will behave differently in different sleep modes based on the settings of XOSC32K.RUNSTDBY, XOSC32K.ONDEMAND, and XOSC32K.ENABLE. If XOSC32KCTRL.ENABLE=0, the XOSC32K will be always stopped. For XOS32KCTRL.ENABLE=1, this table is valid: SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 322 Table 24-1. XOSC32K Sleep Behavior CPU Mode XOSC32K. RUNSTDBY XOSC32K. ONDEMAND Sleep Behavior of XOSC32K and CFD Active or Idle - 0 Always run Active or Idle - 1 Run if requested by peripheral Standby 1 0 Always run Standby 1 1 Run if requested by peripheral Standby 0 - Run if requested by peripheral As a crystal oscillator usually requires a very long start-up time, the 32KHz External Crystal Oscillator will keep running across resets when XOSC32K.ONDEMAND=0, except for power-on reset (POR). After a reset or when waking up from a sleep mode where the XOSC32K was disabled, the XOSC32K will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSC32K.STARTUP) in the 32KHz External Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. Once the external clock or crystal oscillator is stable and ready to be used as a clock source, the XOSC32K Ready bit in the Status register is set (STATUS.XOSC32KRDY=1). The transition of STATUS.XOSC32KRDY from '0' to '1' generates an interrupt if the XOSC32K Ready bit in the Interrupt Enable Set register is set (INTENSET.XOSC32KRDY=1). The XOSC32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). Before enabling the GCLK or the RTC module, the corresponding oscillator output must be enabled (XOSC32K.EN32K or XOSC32K.EN1K) in order to ensure proper operation. In the same way, the GCLK or RTC modules must be disabled before the clock selection is changed. For details on RTC clock configuration, refer also to 24.6.6 Real-Time Counter Clock Selection. Related Links 18. GCLK - Generic Clock Controller 27. RTC – Real-Time Counter 24.6.3 Clock Failure Detection Operation The Clock Failure Detector (CFD) allows the user to monitor the external clock or crystal oscillator signal provided by the external oscillator (XOSC32K). The CFD detects failing operation of the XOSC32K clock with reduced latency, and allows to switch to a safe clock source in case of clock failure. The user can also switch from the safe clock back to XOSC32K in case of recovery. The safe clock is derived from the OSCULP32K oscillator with a configurable prescaler. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller. In sleep modes, CFD operation is automatically disabled when the external oscillator is not requested to run by a peripheral. See the Sleep Behavior table above when this is the case. The user interface registers allow to enable, disable, and configure the CFD. The Status register provides status flags on failure and clock switch conditions. The CFD can optionally trigger an interrupt or an event when a failure is detected. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 323 Clock Failure Detection The CFD is reset only at power-on (POR). The CFD does not monitor the XOSC32K clock when the oscillator is disabled (XOSC32K.ENABLE=0). Before starting CFD operation, the user must start and enable the safe clock source (OSCULP32K oscillator). CFD operation is started by writing a '1' to the CFD Enable bit in the External Oscillator Control register (CFDCTRL.CFDEN). After starting or restarting the XOSC32K, the CFD does not detect failure until the start-up time has elapsed. The start-up time is configured by the Oscillator Start-Up Time in the External Multipurpose Crystal Oscillator Control register (XOSC32K.STARTUP). Once the XOSC32K Start-Up Time is elapsed, the XOSC32K clock is constantly monitored. During a period of 4 safe clocks (monitor period), the CFD watches for a clock activity from the XOSC32K. There must be at least one rising and one falling XOSC32K clock edge during 4 safe clock periods to meet non-failure conditions. If no or insufficient activity is detected, the failure status is asserted: The Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) and the Clock Failure Detector interrupt flag bit in the Interrupt Flag register (INTFLAG.CLKFAIL) are set. If the CLKFAIL bit in the Interrupt Enable Set register (INTENSET.CLKFAIL) is set, an interrupt is generated as well. If the Event Output enable bit in the Event Control register (EVCTRL.CFDEO) is set, an output event is generated, too. After a clock failure was issued the monitoring of the XOSC32K clock is continued, and the Clock Failure Detector status bit in the Status register (STATUS.CLKFAIL) reflects the current XOSC32K activity. Clock Switch When a clock failure is detected, the XOSC32K clock is replaced by the safe clock in order to maintain an active clock during the XOSC32K clock failure. The safe clock source is the OSCULP32K oscillator clock. Both 32KHz and 1KHz outputs of the XOSC32K are replaced by the respective OSCULP32K 32KHz and 1KHz outputs. The safe clock source can be scaled down by a configurable prescaler to ensure that the safe clock frequency does not exceed the operating conditions selected by the application. When the XOSC32K clock is switched to the safe clock, the Clock Switch bit in the Status register (STATUS.CLKSW) is set. When the CFD has switched to the safe clock, the XOSC32K is not disabled. If desired, the application must take the necessary actions to disable the oscillator. The application must also take the necessary actions to configure the system clocks to continue normal operations. In the case the application can recover the XOSC32K, the application can switch back to the XOSC32K clock by writing a '1' to Switch Back Enable bit in the Clock Failure Control register (CFDCTRL.SWBACK). Once the XOSC32K clock is switched back, the Switch Back bit (CFDCTRL.SWBACK) is cleared by hardware. Prescaler The CFD has an internal configurable prescaler to generate the safe clock from the OSCULP32K oscillator. The prescaler size allows to scale down the OSCULP32K oscillator so the safe clock frequency is not higher than the XOSC32K clock frequency monitored by the CFD. The maximum division factor is 2. The prescaler is applied on both outputs (32KHz and 1KHz) of the safe clock. Example 24-1.  For an external crystal oscillator at 32KHz and the OSCULP32K frequency is 32KHz, the XOSC32K.CFDPRESC should be set to 0 for a safe clock of equal frequency. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 324 Event If the Event Output Enable bit in the Event Control register (EVCTRL.CFDEO) is set, the CFD clock failure will be output on the Event Output. When the CFD is switched to the safe clock, the CFD clock failure will not be output on the Event Output. Sleep Mode The CFD is halted depending on configuration of the XOSC32K and the peripheral clock request. For further details, refer to the Sleep Behavior table above. The CFD interrupt can be used to wake up the device from sleep modes. 24.6.4 32 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation The OSCULP32K provides a tunable, low-speed, and ultra low-power clock source. The OSCULP32K is factory-calibrated under typical voltage and temperature conditions. The OSCULP32K is enabled by default after a Power-on Reset (POR), and will always run except during POR. The frequency of the OSCULP32K Oscillator is controlled by the value in the Calibration bits in the 32 kHz Ultra Low-Power Internal Oscillator Control register (OSCULP32K.CALIB). This data is used to compensate for process variations. OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during start-up. The calibration value can be overridden by the user by writing to OSCULP32K.CALIB. Users can lock the OSCULP32K configuration by setting the Write Lock bit in the 32 kHz Ultra Low-Power Internal Oscillator Control register (OSCULP32K.WRTLOCK = 1). If set, the OSCULP32K configuration is locked until POR is detected. The OSCULP32K can be used as a source for Generic Clock Generators (GCLK) or for the Real-Time Counter (RTC). To ensure proper operation, the GCLK or RTC modules must be disabled before the clock selection is changed. OSCULP32K Clock Switch The Clock switch operation requires the XOSC32K to be enabled (XOSC32K.ENABLE=1 and STATUS.XOSC32KRDY = 1). When the OSCULP32K Clock Switch Enable bit (OSCULP32K.ULP32KSW) is set, the CLK_OSCULP32K clock is switched to the XOSC32K Clock Oscillator. When the clock switch process is complete, the OSCULP32K Clock Switch bit in Status register (STATUS.ULP32KSW) is set. The OSCULP32K oscillator is shut off, and the XOSC32K oscillator becomes always running. The CFD feature is also disabled by hardware. When set, the OSCULP32K.ULP32KSW can be reset only by POR operation. Related Links 27. RTC – Real-Time Counter 24.6.6 Real-Time Counter Clock Selection 18. GCLK - Generic Clock Controller 24.6.5 Watchdog Timer Clock Selection The Watchdog Timer (WDT) uses the internal 1.024kHz OSCULP32K output clock. This clock is running all the time and internally enabled when requested by the WDT module. Related Links 26. WDT – Watchdog Timer SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 325 24.6.6 Real-Time Counter Clock Selection Before enabling the RTC module, the RTC clock must be selected first. All oscillator outputs are valid as RTC clock. The selection is done in the RTC Control register (RTCCTRL). To ensure a proper operation, it is highly recommended to disable the RTC module first, before the RTC clock source selection is changed. Related Links 27. RTC – Real-Time Counter 24.6.7 Interrupts The OSC32KCTRL has the following interrupt sources: • XOSC32KRDY - 32KHz Crystal Oscillator Ready: A 0-to-1 transition on the STATUS.XOSC32KRDY bit is detected • CLKFAIL - Clock Failure Detector: A 0-to-1 transition on the STATUS.CLKFAIL bit is detected All these interrupts are synchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be enabled individually by setting the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the OSC32KCTRL is reset. See the INTFLAG register for details on how to clear interrupt flags. The OSC32KCTRL has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Refer to the INTFLAG register for details. Note:  Interrupts must be globally enabled for interrupt requests to be generated. Related Links 22. PM – Power Manager 24.6.8 Events The CFD can generate the following output event: • Clock Failure Detector (CLKFAIL): Generated when the Clock Failure Detector status bit is set in the Status register (STATUS.CLKFAIL). The CFD event is not generated when the Clock Switch bit (STATUS.SWBACK) in the Status register is set. Writing a '1' to an Event Output bit in the Event Control register (EVCTRL.CFDEO) enables the CFD output event. Writing a '0' to this bit disables the CFD output event. Refer to the Event System chapter for details on configuring the event system. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 326 24.7 Register Summary Offset Name Bit Pos. 0x00 INTENCLR 7:0 CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x04 INTENSET 7:0 CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x08 INTFLAG 7:0 CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x0C STATUS 7:0 ULP32KSW CLKSW CLKFAIL XOSC32KRD Y 15:8 23:16 31:24 0x10 RTCCTRL 7:0 RTCSEL[2:0] 0x11 ... 0x13 Reserved 0x14 XOSC32K 7:0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE 15:8 WRTLOCK STARTUP[2:0] 0x16 CFDCTRL 7:0 CFDPRESC SWBACK CFDEN 0x17 EVCTRL 7:0 CFDEO 0x18 ... 0x1B Reserved 0x1C OSCULP32K 7:0 ULP32KSW 15:8 WRTLOCK CALIB[4:0] 23:16 31:24 24.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly. All registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Optional Write-Protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write- SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 327 Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. Related Links 15. PAC - Peripheral Access Controller SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 328 24.8.1 Interrupt Enable Clear Name:  INTENCLR Offset:  0x00 Reset:  0x00000000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL XOSC32KRDY Access R/W R/W Reset 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Clock Failure Interrupt Enable bit, which disables the XOSC32K Clock Failure interrupt. Value Description 0 The XOSC32K Clock Failure Detection is disabled. 1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set. Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. 1 The XOSC32K Ready interrupt is enabled. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 329 24.8.2 Interrupt Enable Set Name:  INTENSET Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL XOSC32KRDY Access R/W R/W Reset 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the XOSC32K Clock Failure Interrupt Enable bit, which enables the XOSC32K Clock Failure interrupt. Value Description 0 The XOSC32K Clock Failure Detection is disabled. 1 The XOSC32K Clock Failure Detection is enabled. An interrupt request will be generated when the XOSC32K Clock Failure Detection interrupt flag is set. Bit 0 – XOSC32KRDY XOSC32K Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready interrupt. Value Description 0 The XOSC32K Ready interrupt is disabled. 1 The XOSC32K Ready interrupt is enabled. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 330 24.8.3 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x08 Reset:  0x00000000 Property:  – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLKFAIL XOSC32KRDY Access R/W R/W Reset 0 0 Bit 2 – CLKFAIL XOSC32K Clock Failure Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the XOSC32K Clock Failure Detection bit in the Status register (STATUS.CLKFAIL) and will generate an interrupt request if INTENSET.CLKFAIL is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the XOSC32K Clock Failure Detection flag. Bit 0 – XOSC32KRDY XOSC32K Ready This flag is cleared by writing a '1' to it. This flag is set by a zero-to-one transition of the XOSC32K Ready bit in the Status register (STATUS.XOSC32KRDY), and will generate an interrupt request if INTENSET.XOSC32KRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the XOSC32K Ready interrupt flag. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 331 24.8.4 Status Name:  STATUS Offset:  0x0C Reset:  0x00000000 Property:  – Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ULP32KSW CLKSW CLKFAIL XOSC32KRDY Access R R R R Reset 0 0 0 0 Bit 4 – ULP32KSW OSCULP32K Clock Switch Value Description 0 OSCULP32K is not switched and provided by the ULP32K oscillator. 1 OSCULP32K is switched to be provided by the XOSC32K clock. Bit 3 – CLKSW XOSC32K Clock Switch Value Description 0 XOSC32K is not switched and provided the crystal oscillator. 1 XOSC32K is switched to be provided by the safe clock. Bit 2 – CLKFAIL XOSC32K Clock Failure Detector Value Description 0 XOSC32K is passing failure detection. 1 XOSC32K is not passing failure detection. Bit 0 – XOSC32KRDY XOSC32K Ready Value Description 0 XOSC32K is not ready. 1 XOSC32K is stable and ready to be used as a clock source. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 332 24.8.5 RTC Clock Selection Control Name:  RTCCTRL Offset:  0x10 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 RTCSEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – RTCSEL[2:0] RTC Clock Selection These bits select the source for the RTC. Value Name Description 0x0 ULP1K 1.024kHz from 32KHz internal ULP oscillator 0x1 ULP32K 32.768kHz from 32KHz internal ULP oscillator 0x2, 0x3 Reserved - 0x4 XOSC1K 1.024kHz from 32KHz external oscillator 0x5 XOSC32K 32.768kHz from 32KHz external crystal oscillator 0x6 Reserved 0x7 Reserved SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 333 24.8.6 32KHz External Crystal Oscillator (XOSC32K) Control Name:  XOSC32K Offset:  0x14 Reset:  0x00000080 Property:  PAC Write-Protection Bit 15 14 13 12 11 10 9 8 WRTLOCK STARTUP[2:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY EN1K EN32K XTALEN ENABLE Access R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 0 0 Bit 12 – WRTLOCK Write Lock This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. Value Description 0 The XOSC32K configuration is not locked. 1 The XOSC32K configuration is locked. Bits 10:8 – STARTUP[2:0] Oscillator Start-Up Time These bits select the start-up time for the oscillator. The OSCULP32K oscillator is used to clock the start-up counter. Table 24-2. Start-Up Time for 32KHz External Crystal Oscillator STARTUP[2:0] Number of OSCULP32K Clock Cycles Number of XOSC32K Clock Cycles Approximate Equivalent Time [s] 0x0 2048 3 0.06 0x1 4096 3 0.13 0x2 16384 3 0.5 0x3 32768 3 1 0x4 65536 3 2 0x5 131072 3 4 0x6 262144 3 8 0x7 - - Reserved Note:  1. Actual Start-Up time is 1 OSCULP32K cycle + 3 XOSC32K cycles. 2. The given time assumes an XTAL frequency of 32.768kHz. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 334 Bit 7 – ONDEMAND On Demand Control This bit controls how the XOSC32K behaves when a peripheral clock request is detected. For details, refer to XOSC32K Sleep Behavior. Bit 6 – RUNSTDBY Run in Standby This bit controls how the XOSC32K behaves during standby sleep mode. For details, refer to XOSC32K Sleep Behavior. Bit 4 – EN1K 1KHz Output Enable Value Description 0 The 1KHz output is disabled. 1 The 1KHz output is enabled. Bit 3 – EN32K 32KHz Output Enable Value Description 0 The 32KHz output is disabled. 1 The 32KHz output is enabled. Bit 2 – XTALEN Crystal Oscillator Enable This bit controls the connections between the I/O pads and the external clock or crystal oscillator. Value Description 0 External clock connected on XIN32. XOUT32 can be used as general-purpose I/O. 1 Crystal connected to XIN32/XOUT32. Bit 1 – ENABLE Oscillator Enable Value Description 0 The oscillator is disabled. 1 The oscillator is enabled. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 335 24.8.7 Clock Failure Detector Control Name:  CFDCTRL Offset:  0x16 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDPRESC SWBACK CFDEN Access R/W R/W R/W Reset 0 0 0 Bit 2 – CFDPRESC Clock Failure Detector Prescaler This bit selects the prescaler for the Clock Failure Detector. Value Description 0 The CFD safe clock frequency is the OSCULP32K frequency 1 The CFD safe clock frequency is the OSCULP32K frequency divided by 2 Bit 1 – SWBACK Clock Switch Back This bit clontrols the XOSC32K output switch back to the external clock or crystal scillator in case of clock recovery. Value Description 0 The clock switch is disabled. 1 The clock switch is enabled. This bit is reset when the XOSC32K output is switched back to the external clock or crystal oscillator. Bit 0 – CFDEN Clock Failure Detector Enable This bit selects the Clock Failure Detector state. Value Description 0 The CFD is disabled. 1 The CFD is enabled. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 336 24.8.8 Event Control Name:  EVCTRL Offset:  0x17 Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CFDEO Access R/W Reset 0 Bit 0 – CFDEO Clock Failure Detector Event Out Enable This bit controls whether the Clock Failure Detector event output is enabled and an event will be generated when the CFD detects a clock failure. Value Description 0 Clock Failure Detector Event output is disabled, no event will be generated. 1 Clock Failure Detector Event output is enabled, an event will be generated. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 337 24.8.9 32KHz Ultra Low-Power Internal Oscillator (OSCULP32K) Control Name:  OSCULP32K Offset:  0x1C Reset:  0x0000XX06 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 WRTLOCK CALIB[4:0] Access R/W R/W R/W R/W R/W R/W Reset 0 x x x x x Bit 7 6 5 4 3 2 1 0 ULP32KSW Access R/W Reset 0 Bit 15 – WRTLOCK Write Lock This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration. Value Description 0 The OSCULP32K configuration is not locked. 1 The OSCULP32K configuration is locked. Bits 12:8 – CALIB[4:0] Oscillator Calibration These bits control the oscillator calibration. These bits are loaded from Flash Calibration at startup. Bit 5 – ULP32KSW OSCULP32K Clock Switch Enable Value Description 0 OSCULP32K is not switched and provided by the ULP32K oscillator. 1 OSCULP32K is switched to be provided by the XOSC32K oscillator. SAM L10/L11 Family OSC32KCTRL – 32KHz Oscillators Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 338 25. SUPC – Supply Controller 25.1 Overview The Supply Controller (SUPC) manages the voltage reference and power supply of the device. The SUPC controls the voltage regulators for the core (VDDCORE) domain. It sets the voltage regulators according to the sleep modes, or the user configuration. In active mode, the voltage regulators can be selected on the fly between LDO (low-dropout) type regulator or Buck converter. The SUPC embeds two Brown-Out Detectors. BOD33 monitors the voltage applied to the device (VDD) and BOD12 monitors the internal voltage to the core (VDDCORE). The BOD can monitor the supply voltage continuously (continuous mode) or periodically (sampling mode). The SUPC generates also a selectable reference voltage and a voltage dependent on the temperature which can be used by analog modules like the ADC or DAC. 25.2 Features • Voltage Regulator System – Main voltage regulator: LDO or Buck Converter in active mode (MAINVREG) – Low-Power voltage regulator in Standby mode (LPVREG) – Adjustable VDDCORE to the Sleep mode or the performance level – Controlled VDDCORE voltage slope when changing VDDCORE • Voltage Reference System – Reference voltage for ADC and DAC – Temperature sensor • 3.3V Brown-Out Detector (BOD33) – Programmable threshold – Threshold value loaded from NVM User Row at startup – Triggers resets or interrupts or event. Action loaded from NVM User Row – Operating modes: • Continuous mode • Sampled mode for low power applications with programmable sample frequency – Hysteresis value from Flash User Calibration • 1.2V Brown-Out Detector (BOD12) – Internal non-configurable Brown-Out Detector SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 339 25.3 Block Diagram Figure 25-1. SUPC Block Diagram LDO Buck Converter LP VREG VDDCORE BOD12 VDD BOD33 BOD33 BOD12 VREG Core domain PM performance level sleep mode VREF VREF temperature sensor reference voltage Main VREG 25.4 Signal Description Not appclicable. 25.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 25.5.1 I/O Lines Not applicable. 25.5.2 Power Management The SUPC can operate in all sleep modes. Related Links 22. PM – Power Manager 25.5.3 Clocks The SUPC bus clock (CLK_SUPC_APB) can be enabled and disabled in the Main Clock module. A 32KHz clock, asynchronous to the user interface clock (CLK_SUPC_APB), is required to run BOD33 and BOD12 in sampled mode. Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 25.6.6 Synchronization for further details. Related Links 24. OSC32KCTRL – 32KHz Oscillators Controller 19.6.2.6 Peripheral Clock Masking 25.5.4 DMA Not applicable. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 340 25.5.5 Interrupts The interrupt request lines are connected to the interrupt controller. Using the SUPC interrupts requires the interrupt controller to be configured first. 25.5.6 Events The events are connected to the Event System. Refer to the Event System section for details on how to configure the Event System. 25.5.7 Debug Operation When the CPU is halted in debug mode, the SUPC continues normal operation. If the SUPC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. If debugger cold-plugging is detected by the system, BOD33 and BOD12 resets will be masked. The BOD resets keep running under hot-plugging. This allows to correct a BOD33 user level too high for the available supply. 25.5.8 Register Access Protection Registers with write-access can be write-protected optionally by the peripheral access controller (PAC). Note:  Not all registers with write-access can be write-protected. PAC Write-Protection is not available for the following registers: • Interrupt Flag Status and Clear register (INTFLAG) Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register description. Related Links 15. PAC - Peripheral Access Controller 25.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 25.5.10 Analog Connections Not applicable. 25.6 Functional Description 25.6.1 Voltage Regulator System Operation 25.6.1.1 Enabling, Disabling, and Resetting The LDO main voltage regulator is enabled after any Reset. The main voltage regulator (MAINVREG) can be disabled by writing the Enable bit in the VREG register (VREG.ENABLE) to zero. The main SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 341 voltage regulator output supply level is automatically defined by the performance level or the sleep mode selected in the Power Manager module. Related Links 22. PM – Power Manager 25.6.1.2 Initialization After a Reset, the LDO voltage regulator supplying VDDCORE is enabled. 25.6.1.3 Selecting a Voltage Regulator In Active mode, the type of the main voltage regulator supplying VDDCORE can be switched on the fly. The two alternatives are a LDO regulator and a Buck converter. The main voltage regulator switching sequences are as follows: • The user changes the value of the Voltage Regulator Selection bit in the Voltage Regulator System Control register (VREG.SEL) • The start of the switching sequence is indicated by clearing the Voltage Regulator Ready bit in the STATUS register (STATUS.VREGRDY=0) • Once the switching sequence is completed, STATUS.VREGRDY will read '1' The Voltage Regulator Ready (VREGRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.VREGRDY bit. 25.6.1.4 Voltage Scaling Control The VDDCORE supply will change under certain circumstances: • When a new performance level (PL) is set • When the Standby Sleep mode is entered or left • When a sleepwalking task is requested in Standby Sleep mode To prevent high peak current on the main power supply and to have a smooth transition of VDDCORE, both the voltage scaling step size and the voltage scaling frequency can be controlled: VDDCORE is changed by the selected step size of the selected period until the target voltage is reached. The Voltage Scaling Voltage Step field is in the VREG register, VREG.VSVSTEP. The Voltage Scaling Period field is VREG.VSPER. The following waveform shows an example of changing performance level from PL0 to PL2. VDDCORE time V(PL0) V(PL2) VSVSTEP VSPER Setting VREG.VSVSTEP to the maximum value allows to transition in one voltage step. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 342 The STATUS.VCORERDY bit is set to '1' as soon as the VDDCORE voltage has reached the target voltage. During voltage transition, STATUS.VCORERDY will read '0'. The Voltage Ready interrupt (VCORERDY) can be used to detect a 0-to-1 transition of STATUS.VCORERDY, see also 25.6.4 Interrupts. When entering the Standby Sleep mode and when no sleepwalking task is requested, the VDDCORE Voltage scaling control is not used. 25.6.1.5 Sleep Mode Operation In Standby mode, the low-power voltage regulator (LPVREG) is used to supply VDDCORE. When the Run in Standby bit in the VREG register (VREG.RUNSTDBY) is written to '1', VDDCORE is supplied by the main voltage regulator. Depending on the Standby in PL0 bit in the Voltage Regulator register (VREG.STDBYPL0), the VDDCORE level is either set to the PL0 voltage level, or remains in the current performance level. Table 25-1. VDDCORE Level in Standby Mode VREG.RUNSTDBY VREG.STDBYPL0 VDDCORE Supply in Standby Mode 0 - LPVREG 1 0 MAINVREG in current performance level(1) 1 1 MAINVREG in PL0 Note:  1. When the device is in PL0 but VREG.STDBYPL0=0, the MAINVREG is operating in normal power mode. To minimize power consumption, operate MAINVREG in PL0 mode by selecting VREG.STDBYPL0=1. By writing the Low-Power mode Efficiency bit in the VREG register (VREG.LPEFF) to '1', the efficiency of the regulator in LPVREG can be improved when the application uses a limited VDD range (2.5 to 3.63V). It is also possible to use the BOD33 in order to monitor the VDD and change this LPEFF value on the fly according to VDD level. Related Links 22.6.3.3 Sleep Mode Controller 25.6.2 Voltage Reference System Operation The reference voltages are generated by a functional block DETREF inside of the SUPC. DETREF is providing a fixed-voltage source, BANDGAP=1.1V, and a variable voltage, INTREF. 25.6.2.1 Initialization The voltage reference output and the temperature sensor are disabled after any Reset. 25.6.2.2 Enabling, Disabling, and Resetting The voltage reference output is enabled/disabled by setting/clearing the Voltage Reference Output Enable bit in the Voltage Reference register (VREF.VREFOE). The temperature sensor is enabled/disabled by setting/clearing the Temperature Sensor Enable bit in the Voltage Reference register (VREF.TSEN). Note:  When VREF.ONDEMAND=0, it is not recommended to enable both voltage reference output and temperature sensor at the same time - only the voltage reference output will be present at both ADC inputs. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 343 25.6.2.3 Selecting a Voltage Reference The Voltage Reference Selection bit field in the VREF register (VREF.SEL) selects the voltage of INTREF to be applied to analog modules, e.g. the ADC. 25.6.2.4 Sleep Mode Operation The Voltage Reference output and the Temperature Sensor output behavior during sleep mode can be configured using the Run in Standby bit and the On Demand bit in the Voltage Reference register (VREF.RUNSTDBY, VREF.ONDEMAND), see the following table: Table 25-2. VREF Sleep Mode Operation VREF.ONDEMAND VREF.RUNSTDBY Voltage Reference Sleep behavior - - Disable 0 0 Always run in all sleep modes except standby sleep mode 0 1 Always run in all sleep modes including standby sleep mode 1 0 Only run if requested by the ADC, in all sleep modes except standby sleep mode 1 1 Only run if requested by the ADC, in all sleep modes including standby sleep mode 25.6.3 Brown-Out Detectors 25.6.3.1 Initialization Before a Brown-Out Detector (BOD33) is enabled, it must be configured, as outlined by the following: • Set the BOD threshold level (BOD33.LEVEL) • Set the configuration in Active, Standby (BOD33.ACTION, BOD33.STDBYCFG) • Set the prescaling value if the BOD will run in sampling mode (BOD33.PSEL) • Set the action and hysteresis (BOD33.ACTION and BOD33.HYST) The BOD33 register is Enable-Protected, meaning that they can only be written when the BOD is disabled (BOD33.ENABLE=0 and STATUS.B33SRDY=0). As long as the Enable bit is '1', any writes to Enable-Protected registers will be discarded, and an APB error will be generated. The Enable bits are not Enable-Protected. 25.6.3.2 Enabling, Disabling, and Resetting After power or user reset, the BOD33 and BOD12 register values are loaded from the NVM User Page. The BOD33 is enabled by writing a '1' to the Enable bit in the BOD control register (BOD33.ENABLE). The BOD33 is disabled by writing a '0' to the BOD33.ENABLE. 25.6.3.3 3.3V Brown-Out Detector (BOD33) The 3.3V Brown-Out Detector (BOD33) is able to monitor the VDD supply and compares the voltage with the brown-out threshold level set in the BOD33 Level field (BOD33.LEVEL) in the BOD33 register. When VDD crosses below the brown-out threshold level, the BOD33 can generate either an interrupt or a Reset, depending on the BOD33 Action bit field (BOD33.ACTION). The BOD33 detection status can be read from the BOD33 Detection bit in the Status register (STATUS.BOD33DET). At start-up or at Power-On Reset (POR), the BOD33 register values are loaded from the NVM User Row. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 344 25.6.3.4 1.2V Brown-Out Detector (BOD12) The BOD12 is calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be changed to assure the correct behavior of the BOD12. The BOD12 generates a reset when 1.2V crosses below the preset brown-out level. The BOD12 is always disabled in Standby Sleep mode. 25.6.3.5 Continuous Mode Continuous mode is the default mode for BOD33. The BOD33 is continuously monitoring the VDD supply voltage if it is enabled (BOD33.ENABLE=1) and if the BOD33 Configuration bit in the BOD33 register is cleared (BOD33.ACTCFG=0 for active mode, BOD33.STDBYCFG=0 for standby mode). 25.6.3.6 Sampling Mode The Sampling Mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The BOD33 will monitor the supply voltage for a short period of time and then go to a lowpower disabled state until the next sampling clock tick. Sampling mode is enabled in Active mode for BOD33 by writing the ACTCFG bit (BOD33.ACTCFG=1). Sampling mode is enabled in Standby mode by writing to the STDBYCFG bit (BOD33.STBYCFG=1). The frequency of the clock ticks (Fclksampling) is controlled by the Prescaler Select bit groups in the BOD33 register (BOD33.PSEL). = ݈݃݊݅݌݉ܽݏ݈݇ܿܨ ݎ݈݁ܽܿݏ݁ݎ݌݈݇ܿܨ 2 PSEL + 1 The prescaler signal (Fclkprescaler) is a 1KHz clock, output by the 32KHz Ultra Low Power Oscillator OSCULP32K. As the sampling clock is different from the APB clock domain, synchronization among the clocks is necessary. See also 25.6.6 Synchronization. 25.6.3.7 Hysteresis A hysteresis on the trigger threshold of a BOD will reduce the sensitivity to ripples on the monitored voltage: instead of switching RESET at each crossing of VBOD, the thresholds for switching RESET on and off are separated (VBOD- and VBOD+, respectively). Figure 25-2. BOD Hysteresis Principle Hysteresis OFF: VCC RESET VBOD Hysteresis ON: VCC RESET VBODVBOD+ Enabling the BOD33 hysteresis by writing the Hysteresis bit in the BOD33 register (BOD33.HYST) to '1' will add hysteresis to the BOD33 threshold level. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 345 The hysteresis functionality can be used in both Continuous and Sampling Mode. 25.6.3.8 Sleep Mode Operation 25.6.3.8.1 Standby Mode The BOD33 can be used in standby mode if the BOD is enabled and the corresponding Run in Standby bit is written to '1' (BOD33.RUNSTDBY). The BOD33 can be configured to work in either Continuous or Sampling Mode by writing a '1' to the Configuration in Standby Sleep Mode bit (BOD33.STDBYCFG). 25.6.4 Interrupts The SUPC has the following interrupt sources, which are either synchronous or asynchronous wake-up sources: • VDDCORE Voltage Ready (VCORERDY), asynchronous • Voltage Regulator Ready (VREGRDY) asynchronous • BOD33 Ready (BOD33RDY), synchronous • BOD33 Detection (BOD33DET), asynchronous • BOD33 Synchronization Ready (B33SRDY), synchronous Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled, or the SUPC is reset. See the INTFLAG register for details on how to clear interrupt flags. The SUPC has one common interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine which interrupt condition is present. Note:  Interrupts must be globally enabled for interrupt requests to be generated. Related Links 22.6.3.3 Sleep Mode Controller 25.6.5 Events The SUPC can gemerate the following output event: • BOD12 Detection (BOD12DET): Generated when the VDDCORE crosses below the brown-out threshold level. • BOD33 Detection (BOD33DET): Generated when the VDD crosses below the brown-out threshold level. Writing a one to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to the Event System chapter for details on configuring the event system. 25.6.6 Synchronization The prescaler counters that are used to trigger brown-out detections operate asynchronously from the peripheral bus. As a consequence, the BOD33 Enable bit (BOD33.ENABLE) need synchronization when written. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 346 The Write-Synchronization of the Enable bit is triggered by writing a '1' to the Enable bit of the BOD33 Control register. The Synchronization Ready bit (STATUS.B33SRDY) in the STATUS register will be cleared when the Write-Synchronization starts, and set again when the Write-Synchronization is complete. Writing to the same register while the Write-Synchronization is ongoing (STATUS.B33SRDY is '0') will generate a PAC error without stalling the APB bus. 25.6.7 Low Power VREF in Active Mode During active functional mode, the brownout detector BOD33 and the main voltage regulator (VREG) can reduce their power consumption by using the low power voltage reference (ULPVREF). The low power voltage reference is ready and can be selected when ULPVREFRDY bit in STATUS register is high. The ULPVREF Ready (ULPVREFRDY) interrupt can also be used to detect a zero-to-one transition of the STATUS.ULPVREFRDY bit. Writing the VREF bit in the BOD33 register to '1' selects ULPVREF as voltage reference for the BOD33. If the chip operated in PL0 ((PM->PLCFG.PLSEL=0) or Performance Level is disabled (PM- >PLCFG.PLDIS=1), writing the VREFSEL bit in the VREG register to '1' selects ULPVREF as voltage reference for the main voltage regulator. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 347 25.7 Register Summary Offset Name Bit Pos. 0x00 INTENCLR 7:0 B33SRDY BOD33DET BOD33RDY 15:8 ULPVREFRD Y VCORERDY VREGRDY 23:16 31:24 0x04 INTENSET 7:0 B33SRDY BOD33DET BOD33RDY 15:8 ULPVREFRD Y VCORERDY VREGRDY 23:16 31:24 0x08 INTFLAG 7:0 B33SRDY BOD33DET BOD33RDY 15:8 ULPVREFRD Y VCORERDY VREGRDY 23:16 31:24 0x0C STATUS 7:0 B33SRDY BOD33DET BOD33RDY 15:8 ULPVREFRD Y VCORERDY VREGRDY 23:16 31:24 0x10 BOD33 7:0 RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE 15:8 PSEL[3:0] VREFSEL ACTCFG 23:16 LEVEL[5:0] 31:24 0x14 ... 0x17 Reserved 0x18 VREG 7:0 RUNSTDBY STDBYPL0 SEL ENABLE 15:8 VREFSEL LPEFF 23:16 VSVSTEP[3:0] 31:24 VSPER[7:0] 0x1C VREF 7:0 ONDEMAND RUNSTDBY VREFOE TSEN 15:8 23:16 SEL[3:0] 31:24 0x20 ... 0x2B Reserved 0x2C EVCTRL 7:0 BOD33DETE O 15:8 23:16 31:24 SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 348 25.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). PAC Writeprotection is denoted by the "PAC Write-Protection" property in each individual register description. Refer to 25.5.8 Register Access Protection for details. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Write-Synchronized" or the "Read-Synchronized" property in each individual register description. Refer to 25.6.6 Synchronization for details. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 349 25.8.1 Interrupt Enable Clear Name:  INTENCLR Offset:  0x00 Reset:  0x00000000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set register (INTENSET). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ULPVREFRDY VCORERDY VREGRDY Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R/W R/W R/W Reset 0 0 0 Bit 11 – ULPVREFRDY Low Power Voltage Reference Ready Interrupt Enable Writing a '0' to this bit has no effect. The ULPVREFRDY bit will clear on a zero-to-one transition of the Low Power Voltage Reference Ready bit in the Status register (STATUS.ULPVREFRDY). Value Description 0 The Low Power Ready interrupt is disabled. 1 The Low Power Ready interrupt is enabled and an interrupt request will be generated when the ULPVREFRDY Interrupt Flag is set. Bit 10 – VCORERDY VDDCORE Voltage Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the VDDCORE Ready Interrupt Enable bit, which disables the VDDCORE Ready interrupt. Value Description 0 The VDDCORE Ready interrupt is disabled. 1 The VDDCORE Ready interrupt is enabled and an interrupt request will be generated when the VCORERDY Interrupt Flag is set. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 350 Bit 8 – VREGRDY Voltage Regulator Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Voltage Regulator Ready Interrupt Enable bit, which disables the Voltage Regulator Ready interrupt. Value Description 0 The Voltage Regulator Ready interrupt is disabled. 1 The Voltage Regulator Ready interrupt is enabled and an interrupt request will be generated when the Voltage Regulator Ready Interrupt Flag is set. Bit 2 – B33SRDY  BOD33 Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled. 1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set. Bit 1 – BOD33DET  BOD33 Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection interrupt. Value Description 0 The BOD33 Detection interrupt is disabled. 1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. Bit 0 – BOD33RDY  BOD33 Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready interrupt. Value Description 0 The BOD33 Ready interrupt is disabled. 1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 351 25.8.2 Interrupt Enable Set Name:  INTENSET Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ULPVREFRDY VCORERDY VREGRDY Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R/W R/W R/W Reset 0 0 0 Bit 11 – ULPVREFRDY Low Power Voltage Reference Ready Interrupt Enable Writing a '0' to this bit has no effect. The ULPVREFRDY bit is set on a zero-to-one transition of the Low Power Voltage Reference Ready bit in the Status register (STATUS.ULPVREFRDY). Value Description 0 The Low Power Ready interrupt is disabled. 1 The Low Power Ready interrupt is enabled and an interrupt request will be generated when the ULPVREFRDY Interrupt Flag is set. Bit 10 – VCORERDY VDDCORE Voltage Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the VDDCORE Ready Interrupt Enable bit, which enables the VDDCORE Ready interrupt. Value Description 0 The VDDCORE Ready interrupt is disabled. 1 The VDDCORE Ready interrupt is enabled and an interrupt request will be generated when the VCORERDY Interrupt Flag is set. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 352 Bit 8 – VREGRDY Voltage Regulator Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Voltage Regulator Ready Interrupt Enable bit, which enables the Voltage Regulator Ready interrupt. Value Description 0 The Voltage Regulator Ready interrupt is disabled. 1 The Voltage Regulator Ready interrupt is enabled and an interrupt request will be generated when the Voltage Regulator Ready Interrupt Flag is set. Bit 2 – B33SRDY  BOD33 Synchronization Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33 Synchronization Ready interrupt. Value Description 0 The BOD33 Synchronization Ready interrupt is disabled. 1 The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Synchronization Ready Interrupt flag is set. Bit 1 – BOD33DET  BOD33 Detection Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection interrupt. Value Description 0 The BOD33 Detection interrupt is disabled. 1 The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set. Bit 0 – BOD33RDY  BOD33 Ready Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt. Value Description 0 The BOD33 Ready interrupt is disabled. 1 The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready Interrupt flag is set. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 353 25.8.3 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x08 Reset:  x initially determined from NVM User Row after reset Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ULPVREFRDY VCORERDY VREGRDY Access R/W R/W R/W Reset 0 0 1 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R/W R/W R/W Reset 0 0 x Bit 11 – ULPVREFRDY Low Power Voltage Reference Ready Interrupt Enable Writing a '0' to this bit has no effect. The ULPVREFRDY bit will clear on a zero-to-one transition of the Low Power Voltage Reference Ready bit in the Status register (STATUS.ULPVREFRDY) and will generate an interrupt request if INTENSET.ULPVREFRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the ULPVREFRDY interrupt flag. Bit 10 – VCORERDY VDDCORE Voltage Ready This flag is cleared by writing a '1 to it. This flag is set on a zero-to-one transition of the VDDCORE Ready bit in the Status register (STATUS.VCORERDY) and will generate an interrupt request if INTENSET.VCORERDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the VCORERDY interrupt flag. Bit 8 – VREGRDY Voltage Regulator Ready This flag is cleared by writing a '1' to it. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 354 This flag is set on a zero-to-one transition of the Voltage Regulator Ready bit in the Status register (STATUS.VREGRDY) and will generate an interrupt request if INTENSET.VREGRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the VREGRDY interrupt flag. Bit 2 – B33SRDY  BOD33 Synchronization Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register (STATUS.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Synchronization Ready interrupt flag. Bit 1 – BOD33DET  BOD33 Detection This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (STATUS.BOD33DET) and will generate an interrupt request if INTENSET.BOD33DET=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Detection interrupt flag. Bit 0 – BOD33RDY  BOD33 Ready This flag is cleared by writing a '1' to it. This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (STATUS.BOD33RDY) and will generate an interrupt request if INTENSET.BOD33RDY=1. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the BOD33 Ready interrupt flag. The BOD33 can be enabled. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 355 25.8.4 Status Name:  STATUS Offset:  0x0C Reset:  x,y initially determined from NVM User Row after reset Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 ULPVREFRDY VCORERDY VREGRDY Access R R R Reset x 1 1 Bit 7 6 5 4 3 2 1 0 B33SRDY BOD33DET BOD33RDY Access R R R Reset 0 0 y Bit 12 – ULPVREFRDY Low Power Voltage Reference Ready Value Description 0 The ULPVREF voltage is not as expected. 1 The ULPVREF voltage is the target voltage. Bit 10 – VCORERDY VDDCORE Voltage Ready Value Description 0 The VDDCORE voltage is not as expected. 1 The VDDCORE voltage is the target voltage. Bit 8 – VREGRDY Voltage Regulator Ready Value Description 0 The selected voltage regulator in VREG.SEL is not ready. 1 The voltage regulator selected in VREG.SEL is ready and the core domain is supplied by this voltage regulator. Bit 2 – B33SRDY  BOD33 Synchronization Ready SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 356 Value Description 0 BOD33 synchronization is ongoing. 1 BOD33 synchronization is complete. Bit 1 – BOD33DET  BOD33 Detection Value Description 0 No BOD33 detection. 1 BOD33 has detected that the I/O power supply is going below the BOD33 reference value. Bit 0 – BOD33RDY  BOD33 Ready The BOD33 can be enabled at start-up from NVM User Row. Value Description 0 BOD33 is not ready. 1 BOD33 is ready. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 357 25.8.5 3.3V Brown-Out Detector (BOD33) Control Name:  BOD33 Offset:  0x10 Reset:  x initially determined from NVM User Row after reset Property:  Write-Synchronized, Enable-Protected, PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 LEVEL[5:0] Access R/W R/W R/W R/W R/W R/W Reset x x x x x x Bit 15 14 13 12 11 10 9 8 PSEL[3:0] VREFSEL ACTCFG Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY STDBYCFG ACTION[1:0] HYST ENABLE Access R/W R/W R/W R/W R/W R/W Reset 0 0 x x x x Bits 21:16 – LEVEL[5:0]  BOD33 Threshold Level on VDD These bits set the triggering voltage threshold for the BOD33 when the BOD33 monitors the VDD. These bits are loaded from NVM User Row at start-up. This bit field is not synchronized. Bits 15:12 – PSEL[3:0] Prescaler Select Selects the prescaler divide-by output for the BOD33 sampling mode. The input clock comes from the OSCULP32K 1KHz output. Value Name Description 0x0 DIV2 Divide clock by 2 0x1 DIV4 Divide clock by 4 0x2 DIV8 Divide clock by 8 0x3 DIV16 Divide clock by 16 0x4 DIV32 Divide clock by 32 0x5 DIV64 Divide clock by 64 0x6 DIV128 Divide clock by 128 0x7 DIV256 Divide clock by 256 0x8 DIV512 Divide clock by 512 0x9 DIV1024 Divide clock by 1024 SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 358 Value Name Description 0xA DIV2048 Divide clock by 2048 0xB DIV4096 Divide clock by 4096 0xC DIV8192 Divide clock by 8192 0xD DIV16384 Divide clock by 16384 0xE DIV32768 Divide clock by 32768 0xF DIV65536 Divide clock by 65536 Bit 11 – VREFSEL  BOD33 Voltage Reference Selection This bit is not synchronized. Value Description 0 Selects VREF for the BOD33. 1 Selects ULPVREF for the BOD33. Bit 8 – ACTCFG  BOD33 Configuration in Active Sleep Mode This bit is not synchronized. Value Description 0 In active mode, the BOD33 operates in continuous mode. 1 In active mode, the BOD33 operates in sampling mode. Bit 6 – RUNSTDBY Run in Standby This bit is not synchronized. Value Description 0 In standby sleep mode, the BOD33 is disabled. 1 In standby sleep mode, the BOD33 is enabled. Bit 5 – STDBYCFG  BOD33 Configuration in Standby Sleep Mode If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BOD33 configuration in standby sleep mode. This bit is not synchronized. Value Description 0 In standby sleep mode, the BOD33 is enabled and configured in continuous mode. 1 In standby sleep mode, the BOD33 is enabled and configured in sampling mode. Bits 4:3 – ACTION[1:0]  BOD33 Action These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold. These bits are loaded from NVM User Row at start-up. This bit field is not synchronized. Value Name Description 0x0 NONE No action 0x1 RESET The BOD33 generates a reset SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 359 Value Name Description 0x2 INT The BOD33 generates an interrupt 0x3 - Reserved Bit 2 – HYST Hysteresis This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage. This bit is loaded from NVM User Row at start-up. This bit is not synchronized. Value Description 0 No hysteresis. 1 Hysteresis enabled. Bit 1 – ENABLE Enable This bit is loaded from NVM User Row at start-up. This bit is not enable-protected. Value Description 0 BOD33 is disabled. 1 BOD33 is enabled. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 360 25.8.6 Voltage Regulator System (VREG) Control Name:  VREG Offset:  0x18 Reset:  0x00000002 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 VSPER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 VSVSTEP[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 VREFSEL LPEFF Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 RUNSTDBY STDBYPL0 SEL ENABLE Access R/W R/W R/W R/W Reset 0 1 0 1 Bits 31:24 – VSPER[7:0] Voltage Scaling Period This bitfield sets the period between the voltage steps when the VDDCORE voltage is changing in µs. If VSPER=0, the period between two voltage steps is 1µs. Bits 19:16 – VSVSTEP[3:0] Voltage Scaling Voltage Step This field sets the voltage step height when the VDDCORE voltage is changing to reach the target VDDCORE voltage. The voltage step is equal to 2VSVSTEP* min_step. See the Electrical Characteristics chapters for the min_step voltage level. Bit 9 – VREFSEL Voltage Regulator Voltage Reference Selection This bit provides support of using ULPVREF during active function mode. Value Description 0 Selects VREF for the voltage regulator. 1 Selects ULPVREF for the voltage regulator. Bit 8 – LPEFF Low power Mode Efficiency SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 361 Value Description 0 The voltage regulator in Low power mode has the default efficiency and supports the whole VDD range (1.62V to 3.63V). 1 The voltage regulator in Low power mode has the highest efficiency and supports a limited VDD range (2.5V to 3.63V). Bit 6 – RUNSTDBY Run in Standby Value Description 0 The voltage regulator is in low power mode in Standby sleep mode. 1 The voltage regulator is in normal mode in Standby sleep mode. Bit 5 – STDBYPL0 Standby in PL0 This bit selects the performance level (PL) of the main voltage regulator for the Standby sleep mode. This bit is only considered when RUNSTDBY=1. Value Description 0 In Standby sleep mode, the voltage regulator remains in the current performance level. 1 In Standby sleep mode, the voltage regulator is used in PL0. Bit 2 – SEL Voltage Regulator Selection Value Description 0 The voltage regulator in active mode is a LDO voltage regulator. 1 The voltage regulator in active mode is a buck converter. Bit 1 – ENABLE Enable Value Description 0 The voltage regulator is disabled. 1 The voltage regulator is enabled. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 362 25.8.7 Voltage References System (VREF) Control Name:  VREF Offset:  0x1C Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 SEL[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ONDEMAND RUNSTDBY VREFOE TSEN Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 19:16 – SEL[3:0] Voltage Reference Selection These bits select the Voltage Reference for the ADC/DAC. Value Name Description 0x0 1V0 1.0V voltage reference typical value 0x1 1V1 1.1V voltage reference typical valueThe 1.1V voltage reference typical value must be selected for DAC use. Other values are not permitted. 0x2 1V2 1.2V voltage reference typical value 0x3 1V25 1.25V voltage reference typical value 0x4 2V0 2.0V voltage reference typical value 0x5 2V2 2.2V voltage reference typical value 0x6 2V4 2.4V voltage reference typical value 0x7 2V5 2.5V voltage reference typical value Others Reserved Bit 7 – ONDEMAND On Demand Control The On Demand operation mode allows to enable or disable the voltage reference depending on peripheral requests. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 363 Value Description 0 The voltage reference is always on, if enabled. 1 The voltage reference is enabled when a peripheral is requesting it. The voltage reference is disabled if no peripheral is requesting it. Bit 6 – RUNSTDBY Run In Standby The bit controls how the voltage reference behaves during standby sleep mode. Value Description 0 The voltage reference is halted during standby sleep mode. 1 The voltage reference is not stopped in standby sleep mode. If VREF.ONDEMAND=1, the voltage reference will be running when a peripheral is requesting it. If VREF.ONDEMAND=0, the voltage reference will always be running in standby sleep mode. Bit 2 – VREFOE Voltage Reference Output Enable Value Description 0 The Voltage Reference output (INTREF) is not available as an ADC input channel. 1 The Voltage Reference output (INTREF) is routed to an ADC input channel. Bit 1 – TSEN Temperature Sensor Enable Value Description 0 Temperature Sensor is disabled. 1 Temperature Sensor is enabled and routed to an ADC input channel. SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 364 25.8.8 Event Control Name:  EVCTRL Offset:  0x2C Reset:  0x0000000 Property:  Enable-Protected, PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 BOD33DETEO Access R/W Reset 0 Bit 1 – BOD33DETEO BOD33 Detection Event Output Enable Value Description 0 BOD33 detection event output is disabled and event will not be generated 1 BOD33 detection event output is enabled and event will be generated SAM L10/L11 Family SUPC – Supply Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 365 26. WDT – Watchdog Timer 26.1 Overview The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An early-warning interrupt is available to indicate an upcoming watchdog time-out condition. The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared frequently. When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPU-independent clock source. The WDT will continue operation and issue a system reset or interrupt even if the main clocks fail. 26.2 Features • Issues a system reset if the Watchdog Timer is not cleared before its time-out period • Early Warning interrupt generation • Asynchronous operation from dedicated oscillator • Two types of operation – Normal – Window mode • Selectable time-out periods – From 8 cycles to 16,384 cycles in Normal mode – From 16 cycles to 32,768 cycles in Window mode • Always-On capability SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 366 26.3 Block Diagram Figure 26-1. WDT Block Diagram 0xA5 CLEAR COUNT 0 CLK_WDT_OSC OSC32KCTRL PER/WINDOWS/EWOFFSET Early Warning Interrupt Reset 26.4 Signal Description Not applicable. 26.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 26.5.1 I/O Lines Not applicable. 26.5.2 Power Management The WDT can continue to operate in any sleep modes where the selected source clock is running. The WDT interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep modes. Related Links 22. PM – Power Manager 26.5.3 Clocks The WDT bus clock (CLK_WDT_APB) can be enabled and disabled (masked) in the Main Clock module (MCLK). A 1.024 kHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter. The CLK_WDT_OSC CLOCK is sourced from the clock of the internal Ultra Low-Power Oscillator (OSCULP32K). Due to ultra low-power design, the oscillator is not accurate, hence the exact time-out period may vary from device-to-device. This variation must be considered when designing software that uses the WDT to ensure that the time-out periods used are valid for all devices. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 367 The counter clock CLK_WDT_OSC is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 26.6.7 Synchronization for further details. Related Links 19.6.2.6 Peripheral Clock Masking 24. OSC32KCTRL – 32KHz Oscillators Controller 26.5.4 DMA Not applicable. 26.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the WDT interrupt(s) requires the interrupt controller to be configured first. 26.5.6 Events Not applicable. 26.5.7 Debug Operation When the CPU is halted in debug mode the WDT will halt normal operation. 26.5.8 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: • Interrupt Flag Status and Clear (INTFLAG) register Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. 26.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 26.5.10 Analog Connections Not applicable. 26.6 Functional Description 26.6.1 Principle of Operation The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from error situations such as runaway code, by issuing a Reset. When enabled, the WDT is a SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 368 constantly running timer that is configured to a predefined time-out period. Before the end of the time-out period, the WDT should be set back, or else, a system Reset is issued. The WDT has two modes of operation, Normal mode and Window mode. Both modes offer the option of Early Warning interrupt generation. The description for each of the basic modes is given below. The settings in the Control A register (CTRLA) and the Interrupt Enable register (handled by INTENCLR/ INTENSET) determine the mode of operation: Table 26-1. WDT Operating Modes CTRLA.ENABLE CTRLA.WEN Interrupt Enable Mode 0 x x Stopped 1 0 0 Normal mode 1 0 1 Normal mode with Early Warning interrupt 1 1 0 Window mode 1 1 1 Window mode with Early Warning interrupt 26.6.2 Basic Operation 26.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the WDT is disabled (CTRLA.ENABLE=0): • Control A register (CTRLA), except the Enable bit (CTRLA.ENABLE) • Configuration register (CONFIG) • Early Warning Interrupt Control register (EWCTRL) Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. The WDT can be configured only while the WDT is disabled. The WDT is configured by defining the required Time-Out Period bits in the Configuration register (CONFIG.PER). If Window mode operation is desired, the Window Enable bit in the Control A register must be set (CTRLA.WEN=1) and the Window Period bits in the Configuration register (CONFIG.WINDOW) must be defined. Enable-protection is denoted by the "Enable-Protected" property in the register description. 26.6.2.2 Configurable Reset Values After a Power-on Reset, some registers will be loaded with initial values from the NVM User Row. This includes the following bits and bit groups: • Enable bit in the Control A register, CTRLA.ENABLE • Always-On bit in the Control A register, CTRLA.ALWAYSON • Run In Standby Enable bit in the Control A register (CTRLA.RUNSTDBY) • Watchdog Timer Windows Mode Enable bit in the Control A register, CTRLA.WEN • Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register, CONFIG.WINDOW • Time-Out Period bits in the Configuration register, CONFIG.PER • Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 369 26.6.2.3 Enabling, Disabling, and Resetting The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The WDT is disabled by writing a '0' to CTRLA.ENABLE. The WDT can be disabled only if the Always-On bit in the Control A register (CTRLA.ALWAYSON) is '0'. 26.6.2.4 Normal Mode In Normal mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). Once enabled, the WDT will issue a system reset if a time-out occurs. This can be prevented by clearing the WDT at any time during the time-out period. The WDT is cleared and a new WDT time-out period is started by writing 0xA5 to the Clear register (CLEAR). Writing any other value than 0xA5 to CLEAR will issue an immediate system reset. There are 12 possible WDT time-out (TOWDT) periods, selectable from 8ms to 16s. By default, the early warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW). If the Early Warning Interrupt is enabled, an interrupt is generated prior to a WDT time-out condition. In Normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register, EWCTRL.EWOFFSET, define the time when the early warning interrupt occurs. The Normal mode operation is illustrated in the figure Normal-Mode Operation. Figure 26-2. Normal-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 1 EWOFFSET[3:0] = 0 26.6.2.5 Window Mode In Window mode operation, the WDT uses two different time specifications: the WDT can only be cleared by writing 0xA5 to the CLEAR register after the closed window time-out period (TOWDTW), during the subsequent Normal time-out period (TOWDT). If the WDT is cleared before the time window opens (before TOWDTW is over), the WDT will issue a system reset. Both parameters TOWDTW and TOWDT are periods in a range from 8ms to 16s, so the total duration of the WDT time-out period is the sum of the two parameters. The closed window period is defined by the Window Period bits in the Configuration register (CONFIG.WINDOW), and the open window period is defined by the Period bits in the Configuration register (CONFIG.PER). By default, the Early Warning interrupt is disabled. If it is desired, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be written to '1'. The Early Warning Interrupt is SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 370 disabled again by writing a '1' to the Early Warning Interrupt bit in the Interrupt Enable Clear (INTENCLR.EW) register. If the Early Warning interrupt is enabled in Window mode, the interrupt is generated at the start of the open window period, i.e. after TOWDTW. The Window mode operation is illustrated in figure Window-Mode Operation. Figure 26-3. Window-Mode Operation 5 10 15 20 25 30 35 WDT Timeout Early Warning Interrupt Timely WDT Clear t[ms] TOWDT System Reset WDT Count PER[3:0] = 0 WINDOW[3:0] = 0 TOWDTW Early WDT Clear Closed Open 26.6.3 DMA Operation Not applicable. 26.6.4 Interrupts The WDT has the following interrupt source: • Early Warning (EW): Indicates that the counter is approaching the time-out condition. – This interrupt is an asynchronous wake-up source. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the WDT is reset. See the 26.8.6 INTFLAG register description for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the INTFLAG register to determine which interrupt condition is present. Note:  Interrupts must be globally enabled for interrupt requests to be generated. Related Links 22. PM – Power Manager 22.6.3.3 Sleep Mode Controller 26.6.5 Events Not applicable. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 371 26.6.6 Sleep Mode Operation The Run-In-Standby bit in Control A (CTRLA.RUNSTDBY) control the behavior of the WDT during standby sleep mode. When the bit is zero, the watchdog is disabled during sleep, but maintains its current configuration. When CTRLA.RUNSTDBY is '1', the WDT continues to operate during sleep. Related Links 26.8.1 CTRLA 26.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following registers are synchronized when written: • Enable bit in Control A register (CTRLA.ENABLE) • Window Enable bit in Control A register (CTRLA.WEN) • Run-In-Standby bit in Control A register (CTRLA.RUNSTDBY) • Always-On bit in control Control A (CTRLA.ALWAYSON) • Watchdog Clear register (CLEAR) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. 26.6.8 Additional Features 26.6.8.1 Always-On Mode The Always-On mode is enabled by setting the Always-On bit in the Control A register (CTRLA.ALWAYSON=1). When the Always-On mode is enabled, the WDT runs continuously, regardless of the state of CTRLA.ENABLE. Once written, the Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control (EWCTRL) registers are read-only registers while the CTRLA.ALWAYSON bit is set. Thus, the time period configuration bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed. Enabling or disabling Window mode operation by writing the Window Enable bit (CTRLA.WEN) is allowed while in Always-On mode, but note that CONFIG.PER cannot be changed. The Interrupt Clear and Interrupt Set registers are accessible in the Always-On mode. The Early Warning interrupt can still be enabled or disabled while in the Always-On mode, but note that EWCTRL.EWOFFSET cannot be changed. Table WDT Operating Modes With Always-On shows the operation of the WDT for CTRLA.ALWAYSON=1. Table 26-2. WDT Operating Modes With Always-On WEN Interrupt Enable Mode 0 0 Always-on and normal mode 0 1 Always-on and normal mode with Early Warning interrupt SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 372 WEN Interrupt Enable Mode 1 0 Always-on and window mode 1 1 Always-on and window mode with Early Warning interrupt 26.6.8.2 Early Warning The Early Warning interrupt notifies that the WDT is approaching its time-out condition. The Early Warning interrupt behaves differently in Normal mode and in Window mode. In Normal mode, the Early Warning interrupt generation is defined by the Early Warning Offset in the Early Warning Control register (EWCTRL.EWOFFSET). The Early Warning Offset bits define the number of CLK_WDT_OSC clocks before the interrupt is generated, relative to the start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog time-out system reset is generated prior to the Early Warning interrupt. Consequently, the Early Warning interrupt will never be generated. In window mode, the Early Warning interrupt is generated at the start of the open window period. In a typical application where the system is in sleep mode, the Early Warning interrupt can be used to wake up and clear the Watchdog Timer, after which the system can perform other tasks or return to sleep mode. If the WDT is operating in Normal mode with CONFIG.PER = 0x2 and EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 CLK_WDT_OSC clock cycles after the start of the time-out period. The time-out system reset is generated 32 CLK_WDT_OSC clock cycles after the start of the watchdog timeout period. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 373 26.7 Register Summary Offset Name Bit Pos. 0x00 CTRLA 7:0 ALWAYSON RUNSTDBY WEN ENABLE 0x01 CONFIG 7:0 WINDOW[3:0] PER[3:0] 0x02 EWCTRL 7:0 EWOFFSET[3:0] 0x03 Reserved 0x04 INTENCLR 7:0 EW 0x05 INTENSET 7:0 EW 0x06 INTFLAG 7:0 EW 0x07 Reserved 0x08 SYNCBUSY 7:0 CLEAR ALWAYSON RUNSTDBY WEN ENABLE 15:8 23:16 31:24 0x0C CLEAR 7:0 CLEAR[7:0] 26.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 26.5.8 Register Access Protection. Some registers are synchronized when read and/or written. Synchronization is denoted by the "WriteSynchronized" or the "Read-Synchronized" property in each individual register description. For details, refer to 26.6.7 Synchronization. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 374 26.8.1 Control A Name:  CTRLA Offset:  0x00 Reset:  x initially determined from NVM User Row after reset Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 ALWAYSON RUNSTDBY WEN ENABLE Access R/W R/W R/W R/W Reset x x x x Bit 7 – ALWAYSON Always-On This bit allows the WDT to run continuously. After being set, this bit cannot be written to '0', and the WDT will remain enabled until a power-on Reset is received. When this bit is '1', the Control A register (CTRLA), the Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any writes to these registers are not allowed. Writing a '0' to this bit has no effect. This bit is not Enable-Protected. This bit is loaded from NVM User Row at start-up. Value Description 0 The WDT is enabled and disabled through the ENABLE bit. 1 The WDT is enabled and can only be disabled by a power-on reset (POR). Bit 6 – RUNSTDBY Run in Standby This bit controls the behavior of the watchdog during standby sleep mode. This bit can only be written when CTRLA.ENABLE is zero or CTRLA.ALWAYSON is one: • When CTRLA.ALWAYSON=0, this bit is enable-protected by CTRLA.ENABLE. • When CTRLA.ALWAYSON=1, this bit is not enable-protected by CTRLA.ENABLE. These bits are loaded from NVM User Row at startup. Value Description 0 The WDT is disabled during standby sleep. 1 The WDT is enabled continues to operate during standby sleep. Bit 2 – WEN Watchdog Timer Window Mode Enable This bit enables Window mode. It can only be written if the peripheral is disabled unless CTRLA.ALWAYSON=1. The initial value of this bit is loaded from Flash Calibration. This bit is loaded from NVM User Row at startup. Value Description 0 Window mode is disabled (normal operation). 1 Window mode is enabled. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 375 Bit 1 – ENABLE Enable This bit enables or disables the WDT. It can only be written if CTRLA.ALWAYSON=0. Due to synchronization, there is delay between writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately, and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. This bit is not Enable-Protected. This bit is loaded from NVM User Row at startup. Value Description 0 The WDT is disabled. 1 The WDT is enabled. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 376 26.8.2 Configuration Name:  CONFIG Offset:  0x01 Reset:  x initially determined from NVM User Row after reset Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 WINDOW[3:0] PER[3:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1.024kHz CLK_WDT_OSC clock. These bits are loaded from NVM User Row at start-up. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC-0xF Reserved Reserved Bits 3:0 – PER[3:0]  Time-Out Period These bits determine the watchdog time-out period as a number of 1.024kHz CLK_WDTOSC clock cycles. In Window mode operation, these bits define the open window period. These bits are loaded from NVM User Row at startup. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 377 Value Name Description 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB CYC16384 16384 clock cycles 0xC - 0xF - Reserved SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 378 26.8.3 Early Warning Control Name:  EWCTRL Offset:  0x02 Reset:  x initially determined from NVM User Row after reset Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 EWOFFSET[3:0] Access R/W R/W R/W R/W Reset x x x x Bits 3:0 – EWOFFSET[3:0] Early Warning Interrupt Time Offset These bits determine the number of GCLK_WDT clock cycles between the start of the watchdog time-out period and the generation of the Early Warning interrupt. These bits are loaded from NVM User Row at start-up. Value Name Description 0x0 CYC8 8 clock cycles 0x1 CYC16 16 clock cycles 0x2 CYC32 32 clock cycles 0x3 CYC64 64 clock cycles 0x4 CYC128 128 clock cycles 0x5 CYC256 256 clock cycles 0x6 CYC512 512 clock cycles 0x7 CYC1024 1024 clock cycles 0x8 CYC2048 2048 clock cycles 0x9 CYC4096 4096 clock cycles 0xA CYC8192 8192 clock cycles 0xB - 0xF Reserved Reserved SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 379 26.8.4 Interrupt Enable Clear Name:  INTENCLR Offset:  0x04 Reset:  0x00 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning Interrupt Enable bit, which disables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 380 26.8.5 Interrupt Enable Set Name:  INTENSET Offset:  0x05 Reset:  0x00 Property:  PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit sets the Early Warning Interrupt Enable bit, which enables the Early Warning interrupt. Value Description 0 The Early Warning interrupt is disabled. 1 The Early Warning interrupt is enabled. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 381 26.8.6 Interrupt Flag Status and Clear Name:  INTFLAG Offset:  0x06 Reset:  0x00 Property:  N/A Bit 7 6 5 4 3 2 1 0 EW Access R/W Reset 0 Bit 0 – EW Early Warning This flag is cleared by writing a '1' to it. This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Early Warning interrupt flag. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 382 26.8.7 Synchronization Busy Name:  SYNCBUSY Offset:  0x08 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 CLEAR ALWAYSON RUNSTDBY WEN ENABLE Access R R R R R Reset 0 0 0 0 0 Bit 5 – CLEAR Clear Synchronization Busy Value Description 0 Write synchronization of the CLEAR register is complete. 1 Write synchronization of the CLEAR register is ongoing. Bit 4 – ALWAYSON Always-On Synchronization Busy Value Description 0 Write synchronization of the CTRLA.ALWAYSON bit is complete. 1 Write synchronization of the CTRLA.ALWAYSON bit is ongoing. Bit 3 – RUNSTDBY Run-In-Standby Synchronization Busy Value Description 0 Write synchronization of the CTRLA.RUNSTDBY bit is complete. 1 Write synchronization of the CTRLA.RUNSTDBY bit is ongoing. Bit 2 – WEN Window Enable Synchronization Busy Value Description 0 Write synchronization of the CTRLA.WEN bit is complete. 1 Write synchronization of the CTRLA.WEN bit is ongoing. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 383 Bit 1 – ENABLE Enable Synchronization Busy Value Description 0 Write synchronization of the CTRLA.ENABLE bit is complete. 1 Write synchronization of the CTRLA.ENABLE bit is ongoing. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 384 26.8.8 Clear Name:  CLEAR Offset:  0x0C Reset:  0x00 Property:  Write-Synchronized Bit 7 6 5 4 3 2 1 0 CLEAR[7:0] Access W W W W W W W W Reset 0 0 0 0 0 0 0 0 Bits 7:0 – CLEAR[7:0] Watchdog Clear In Normal mode, writing 0xA5 to this register during the watchdog time-out period will clear the Watchdog Timer and the watchdog time-out period is restarted. In Window mode, any writing attempt to this register before the time-out period started (i.e., during TOWDTW) will issue an immediate system Reset. Writing 0xA5 during the time-out period TOWDT will clear the Watchdog Timer and the complete time-out sequence (first TOWDTW then TOWDT) is restarted. In both modes, writing any other value than 0xA5 will issue an immediate system Reset. SAM L10/L11 Family WDT – Watchdog Timer © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 385 27. RTC – Real-Time Counter 27.1 Overview The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to keep track of time. The RTC can wake up the device from sleep modes using the alarm/ compare wake up, periodic wake up, or overflow wake up mechanisms, or from the wake inputs. The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event, and can be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and peripheral events at very long and accurate intervals. The 10-bit programmable prescaler can scale down the clock source. By this, a wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5µs, and time-out periods can range up to 36 hours. For a counter tick interval of 1s, the maximum time-out period is more than 136 years. 27.2 Features • 32-bit counter with 10-bit prescaler • Multiple clock sources • 32-bit or 16-bit counter mode • One 32-bit or two 16-bit compare values • Clock/Calendar mode – Time in seconds, minutes, and hours (12/24) – Date in day of month, month, and year – Leap year correction • Digital prescaler correction/tuning for increased accuracy • Overflow, alarm/compare match and prescaler interrupts and events – Optional clear on alarm/compare match • 2 general purpose registers • Tamper Detection – Timestamp on event or up to 5 inputs with debouncing – Active layer protection SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 386 27.3 Block Diagram Figure 27-1. RTC Block Diagram (Mode 0 — 32-Bit Counter) OVF MATCHCLR CMPn OSC32KCTRL CLK_RTC_OSC PRESCALER CLK_RTC_CNT Periodic Events COUNT COMPn = 0x00000000 Figure 27-2. RTC Block Diagram (Mode 1 — 16-Bit Counter) CLK_RTC_OSC CLK_RTC_CNT OSC32KCTRL PRESCALER COMPn PER COUNT 0x0000 Periodic Events CMPn OVF Figure 27-3. RTC Block Diagram (Mode 2 — Clock/Calendar) CLK_RTC_OSC CLK_RTC_CNT OSC32KCTRL PRESCALER Periodic Events MASKn CLOCK ALARMn 0x00000000 OVF MATCHCLR ALARMn SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 387 Figure 27-4. RTC Block Diagram (Tamper Detection Use Case) PRESCALER TIMESTAMP CAPTURE IN2 IN1 IN0 OUT0 Tamper Input [0..n] PCB Active Layer Protection TAMPEVT TAMPER OUT1 OUT2 ALARM Pseudo-Random Bitstream DEBOUNCE DEBOUNCE DEBOUNCE FREQCORR CLOCK TrustRAM shield OUT3 SEPTO SEPTO SEPTO Related Links 27.6.2.3 32-Bit Counter (Mode 0) 27.6.2.4 16-Bit Counter (Mode 1) 27.6.2.5 Clock/Calendar (Mode 2) 27.6.8.4 Tamper Detection 27.4 Signal Description Table 27-1. Signal Description Signal Description Type INn [n=0..4] Tamper Detection Input Digital input OUT Tamper Detection Output Digital output One signal can be mapped to one of several pins. Related Links 4.1 Multiplexed Signals 27.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 27.5.1 I/O Lines For more information on I/O configurations, refer to the "RTC Pinout" section. Related Links: I/O Multiplexing and Considerations 27.5.2 Power Management The RTC will continue to operate in any sleep mode where the selected source clock is running. The RTC interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. Refer to the Power Manager for details on the different sleep modes. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 388 The RTC will be reset only at power-on (POR) or by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). Related Links 22. PM – Power Manager 27.5.3 Clocks The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Main Clock module MCLK, and the default state of CLK_RTC_APB can be found in Peripheral Clock Masking section. A 32KHz or 1KHz oscillator clock (CLK_RTC_OSC) is required to clock the RTC. This clock must be configured and enabled in the 32KHz oscillator controller (OSC32KCTRL) before using the RTC. This oscillator clock is asynchronous to the bus clock (CLK_RTC_APB). Due to this asynchronicity, writing to certain registers will require synchronization between the clock domains. Refer to 27.6.7 Synchronization for further details. Related Links 24. OSC32KCTRL – 32KHz Oscillators Controller 19.6.2.6 Peripheral Clock Masking 27.5.4 DMA The DMA request lines (or line if only one request) are connected to the DMA Controller (DMAC). Using the RTC DMA requests requires the DMA Controller to be configured first. Related Links 28. DMAC – Direct Memory Access Controller 27.5.5 Interrupts The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupt requires the Interrupt Controller to be configured first. 27.5.6 Events The events are connected to the Event System. Related Links 33. EVSYS – Event System 27.5.7 Debug Operation When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation during debugging. Refer to 27.8.7 DBGCTRL for details. 27.5.8 Register Access Protection All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the following registers: • Interrupt Flag Status and Clear (INTFLAG) register Write-protection is denoted by the "PAC Write-Protection" property in the register description. Write-protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral Access Controller for details. Related Links SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 389 15. PAC - Peripheral Access Controller 27.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 27.5.10 Analog Connections A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. See the Electrical Characteristics Chapters for details on recommended crystal characteristics and load capacitors. 27.6 Functional Description 27.6.1 Principle of Operation The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends on the RTC operating mode. The RTC can function in one of these modes: • Mode 0 - COUNT32: RTC serves as 32-bit counter • Mode 1 - COUNT16: RTC serves as 16-bit counter • Mode 2 - CLOCK: RTC serves as clock/calendar with alarm functionality 27.6.2 Basic Operation 27.6.2.1 Initialization The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRLA.ENABLE=0): • Operating Mode bits in the Control A register (CTRLA.MODE) • Prescaler bits in the Control A register (CTRLA.PRESCALER) • Clear on Match bit in the Control A register (CTRLA.MATCHCLR) • Clock Representation bit in the Control A register (CTRLA.CLKREP) The following registers are enable-protected: • Control B register (CTRLB) • Event Control register (EVCTRL) • Tamper Control register (TAMPCTRL) • Tamper Control B register (TAMPCTRLB) Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE=0). If the RTC is enabled (CTRLA.ENABLE=1), these operations are necessary: first write SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 390 CTRLA.ENABLE=0 and check whether the write synchronization has finished, then change the desired bit field value. Enable-protected bits in CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the "Enable-Protected" property in the register description. The RTC prescaler divides the source clock for the RTC counter. Note:  In Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct operation. The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula: ݂CLK_RTC_CNT = ݂CLK_RTC_OSC 2 PRESCALER The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT. 27.6.2.2 Enabling, Disabling, and Resetting The RTC is enabled by setting the Enable bit in the Control A register (CTRLA.ENABLE=1). The RTC is disabled by writing CTRLA.ENABLE=0. The RTC is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST=1). All registers in the RTC, except DEBUG, will be reset to their initial state, and the RTC will be disabled. The RTC must be disabled before resetting it. 27.6.2.3 32-Bit Counter (Mode 0) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x0, the counter operates in 32-bit Counter mode. The block diagram of this mode is shown in Figure 27-1. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format. The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs, the Compare 0 Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1 transition of CLK_RTC_CNT. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is '1', the counter is cleared on the next counter cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than the prescaler events. Note that when CTRLA.MATCHCLR is '1', INTFLAG.CMP0 and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0. 27.6.2.4 16-Bit Counter (Mode 1) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x1, the counter operates in 16-bit Counter mode as shown in Figure 27-2. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value, and then wrap to 0x0000. This sets the Overflow Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.OVF). The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 391 The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0..1). When a compare match occurs, the Compare n Interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0..1) is set on the next 0-to-1 transition of CLK_RTC_CNT. 27.6.2.5 Clock/Calendar (Mode 2) When the RTC Operating Mode bits in the Control A register (CTRLA.MODE) are written to 0x2, the counter operates in Clock/Calendar mode, as shown in Figure 27-3. When the RTC is enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode. The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is represented as: • Seconds • Minutes • Hours Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control A register (CTRLA.CLKREP). This bit can be changed only while the RTC is disabled. The date is represented in this form: • Day as the numeric day of the month (starting at 1) • Month as the numeric month of the year (1 = January, 2 = February, etc.) • Year as a value from 0x00 to 0x3F. This value must be added to a user-defined reference year. The reference year must be a leap year (2016, 2020 etc). Example: the year value 0x2D, added to a reference year 2016, represents the year 2061. The RTC will increment until it reaches the top value of 23:59:59 December 31 of year value 0x3F, and then wrap to 00:00:00 January 1 of year value 0x00. This will set the Overflow Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.OVF). The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARM0) is set on the next 0-to-1 transition of CLK_RTC_CNT. E.g. For a 1Hz clock counter, it means the Alarm 0 Interrupt flag is set with a delay of 1s after the occurrence of alarm match. A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL). These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are ignored. If the Clear on Match bit in the Control A register (CTRLA.MATCHCLR) is set, the counter is cleared on the next counter cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events with longer periods than it would be possible with the prescaler events only (see 27.6.8.1 Periodic Intervals). Note:  When CTRLA.MATCHCLR is 1, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match with ALARM0. 27.6.3 DMA Operation The RTC generates the following DMA request: • Tamper (TAMPER): The request is set on capture of the timestamp. The request is cleared when the Timestamp register is read. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 392 If the CPU accesses the registers which are source for DMA request set/clear condition, the DMA request can be lost or the DMA transfer can be corrupted, if enabled. 27.6.4 Interrupts The RTC has the following interrupt sources: • Overflow (OVF): Indicates that the counter has reached its top value and wrapped to zero. • Tamper (TAMPER): Indicates detection of valid signal on a tamper input pin or tamper event input. • Compare (CMPn): Indicates a match between the counter value and the compare register. • Alarm (ALARMn): Indicates a match between the clock value and the alarm register. • Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to 27.6.8.1 Periodic Intervals for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Interrupt Enable Set register (INTENSET=1), and disabled by setting the corresponding bit in the Interrupt Enable Clear register (INTENCLR=1). An interrupt request is generated when the interrupt flag is raised and the corresponding interrupt is enabled. The interrupt request remains active until either the interrupt flag is cleared, the interrupt is disabled or the RTC is reset. See the description of the INTFLAG registers for details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. Refer to the Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to determine which interrupt condition is present. Note:  Interrupts must be globally enabled for interrupt requests to be generated. Refer to the Nested Vector Interrupt Controller for details. 27.6.5 Events The RTC can generate the following output events: • Overflow (OVF): Generated when the counter has reached its top value and wrapped to zero. • Tamper (TAMPER): Generated on detection of valid signal on a tamper input pin or tamper event input. • Compare (CMPn): Indicates a match between the counter value and the compare register. • Alarm (ALARM): Indicates a match between the clock value and the alarm register. • Period n (PERn): The corresponding bit in the prescaler has toggled. Refer to 27.6.8.1 Periodic Intervals for details. • Periodic Daily (PERD): Generated when the COUNT/CLOCK has incremented at a fixed period of time. Setting the Event Output bit in the Event Control Register (EVCTRL.xxxEO=1) enables the corresponding output event. Writing a zero to this bit disables the corresponding output event. Refer to the EVSYS - Event System for details on configuring the event system. The RTC can take the following actions on an input event: • Tamper (TAMPEVT): Capture the RTC counter to the timestamp register. See Tamper Detection. Writing a one to an Event Input bit into the Event Control register (EVCTRL.xxxEI) enables the corresponding action on input event. Writing a zero to this bit disables the corresponding action on input event. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 393 Related Links 33. EVSYS – Event System 27.6.6 Sleep Mode Operation The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to wake up the device from a sleep mode. RTC events can trigger other operations in the system without exiting the sleep mode. An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise the CPU will wake up directly, without triggering any interrupt. In this case, the CPU will continue executing right from the first instruction that followed the entry into sleep. The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event must be enabled and connected to an event channel with its interrupt enabled. See Event System for more information. 27.6.7 Synchronization Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. The following bits are synchronized when written: • Software Reset bit in Control A register, CTRLA.SWRST • Enable bit in Control A register, CTRLA.ENABLE • Count Read Synchronization bit in Control A register (CTRLA.COUNTSYNC) • Clock Read Synchronization bit in Control A register (CTRLA.COUNTSYNC) The following registers are synchronized when written: • Counter Value register, COUNT • Clock Value register, CLOCK • Counter Period register, PER • Compare n Value registers, COMPn • Alarm n Value registers, ALARMn • Frequency Correction register, FREQCORR • Alarm n Mask register, MASKn • The General Purpose n registers (GPn) The following registers are synchronized when read: • The Counter Value register, COUNT, if the Counter Read Sync Enable bit in CTRLA (CTRLA.COUNTSYNC) is '1' • The Clock Value register, CLOCK, if the Clock Read Sync Enable bit in CTRLA (CTRLA.CLOCKSYNC) is '1' • The Timestamp Value register (TIMESTAMP) Required write-synchronization is denoted by the "Write-Synchronized" property in the register description. Required read-synchronization is denoted by the "Read-Synchronized" property in the register description. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 394 27.6.8 Additional Features 27.6.8.1 Periodic Intervals The RTC prescaler can generate interrupts and events at periodic intervals, allowing flexible system tick creation. Any of the upper eight bits of the prescaler (bits 2 to 9) can be the source of an interrupt/event. When one of the eight Periodic Event Output bits in the Event Control register (EVCTRL.PEREO[n=0..7]) is '1', an event is generated on the 0-to-1 transition of the related bit in the prescaler, resulting in a periodic event frequency of: ݂PERIODIC(n) = ݂CLK_RTC_OSC 2 n+3 fCLK_RTC_OSC is the frequency of the internal prescaler clock CLK_RTC_OSC, and n is the position of the EVCTRL.PEREOn bit. For example, PER0 will generate an event every eight CLK_RTC_OSC cycles, PER1 every 16 cycles, etc. This is shown in the figure below. Periodic events are independent of the prescaler setting used by the RTC counter, except if CTRLA.PRESCALER is zero. Then, no periodic events will be generated. Figure 27-5. Example Periodic Events CLK_RTC_OSC PER0 PER1 PER2 PER3 27.6.8.2 Frequency Correction The RTC Frequency Correction module employs periodic counter corrections to compensate for a tooslow or too-fast oscillator. Frequency correction requires that CTRLA.PRESCALER is greater than 1. The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1ppm steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 8192 CLK_RTC_OSC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 128 of these periods. The resulting correction is as follows: Correction in ppm = FREQCORR.VALUE 8192 ڄ 128 ڄ 106 ppm This results in a resolution of 0.95367ppm. The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will add counts and increase the period (reducing the frequency), and a negative value will reduce counts per period (speeding up the frequency). Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened depending on the correction value. 27.6.8.3 General Purpose Registers The RTC includes four General Purpose registers (GPn). These registers are reset only when the RTC is reset or when tamper detection occurs while CTRLA.GPTRST=1, and remain powered while the RTC is powered. They can be used to store user-defined values while other parts of the system are powered off. The general purpose registers 2*n and 2*n+1 are enabled by writing a '1' to the General Purpose Enable bit n in the Control B register (CTRLB.GPnEN). SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 395 The GP registers share internal resources with the COMPARE/ALARM features. Each COMPARE/ ALARM register have a separate read buffer and write buffer. When the general purpose feature is enabled the even GP uses the read buffer while the odd GP uses the write buffer. When the COMPARE/ALARM register is written, the write buffer hold temporarily the COMPARE/ALARM value until the synchronisation is complete (bit SYNCBUSY.COMPn going to 0). After the write is completed the write buffer can be used as a odd general purpose register whithout affecting the COMPARE/ALARM function. If the COMPARE/ALARM function is not used, the read buffer can be used as an even general purpose register. In this case writing the even GP will temporarirely use the write buffer until the synchronisation is complete (bit SYNCBUSY.GPn going to 0). Thus an even GP must be written before writing the odd GP. Changing or writing an even GP needs to temporarily save the value of the odd GP. Before using an even GP, the associated COMPARE/ALARM feature must be disabled by writing a '1' to the General Purpose Enable bit in the Control B register (CTRLB.GPnEN). To re-enable the compare/ alarm, CTRLB.GPnEN must be written to zero and the associated COMPn/ALARMn must be written with the correct value. An example procedure to write the general purpose registers GP0 and GP1 is: 1. Wait for any ongoing write to COMP0 to complete (SYNCBUSY.COMP0 = 0). If the RTC is operating in Mode 1, wait for any ongoing write to COMP1 to complete as well (SYNCBUSY.COMP1 = 0). 2. Write CTRLB.GP0EN = 1 if GP0 is needed. 3. Write GP0 if needed. 4. Wait for any ongoing write to GP0 to complete (SYNCBUSY.GP0 = 0). Note that GP1 will also show as busy when GP0 is busy. 5. Write GP1 if needed. The following table provides the correspondence of General Purpose Registers and the COMPARE/ ALARM read or write buffer in all RTC modes. Table 27-2. General Purpose Registers Versus Compare/Alarm Registers: n in 0, 2, 4, 6... Register Mode 0 Mode 1 Mode 2 Write Before GPn COMPn/2 write buffer (COMPn , COMPn +1) write buffer ALARMn/2 write buffer GPn+1 GPn+1 COMPn/2 read buffer (COMPn , COMPn +1) read buffer ALARMn/2 read buffer - 27.6.8.4 Tamper Detection The RTC provides four tamper channels that can be used for tamper detection. The action of each tamper channel is configured using the Input n Action bits in the Tamper Control register (TAMPCTRL.INnACT): • Off: Detection for tamper channel n is disabled. • Wake: A transition on INn input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will not be captured in the TIMESTAMP register. • Capture: A transition on INn input (tamper channel n) matching TAMPCTRL.TAMPLVLn will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be captured in the TIMESTAMP register. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 396 • Active Layer Protection: A mismatch of an internal RTC signal routed between INn and OUTn pins will be detected and the tamper interrupt flag (INTFLAG.TAMPER) will be set. The RTC value will be captured in the TIMESTAMP register. In order to determine which tamper source caused a tamper event, the Tamper ID register (TAMPID) provides the detection status of each tamper channel. These bits remain active until cleared by software. A single interrupt request (TAMPER) is available for all tamper channels. The RTC also supports an input event (TAMPEVT) for generating a tamper condition within the Event System. The tamper input event is enabled by the Tamper Input Event Enable bit in the Event Control register (EVCTRL.TAMPEVEI). Up to four polarity external inputs (INn) can be used for tamper detection. The polarity for each input is selected with the Tamper Level bits in the Tamper Control register (TAMPCTRL.TAMPLVLn). Separate debouncers are embedded for each external input. The debouncer for each input is enabled/ disabled with the Debounce Enable bits in the Tamper Control register (TAMPCTRL.DEBNCn). The debouncer configuration is fixed for all inputs as set by the Control B register (CTRLB). The debouncing period duration is configurable using the Debounce Frequency field in the Control B register (CTRLB.DEBF). The period is set for all debouncers (i.e., the duration cannot be adjusted separately for each debouncer). When TAMPCTRL.DEBNCn = 0, INn is detected asynchronously. See Figure 27-6 for an example. When TAMPCTRL.DEBNCn = 1, the detection time depends on whether the debouncer operates synchronously or asynchronously, and whether majority detection is enabled or not. Refer to the table below for more details. Synchronous versus asynchronous stability debouncing is configured by the Debounce Asynchronous Enable bit in the Control B register (CTRLB.DEBASYNC): • Synchronous (CTRLB.DEBASYNC = 0): INn is synchronized in two CLK_RTC periods and then must remain stable for four CLK_RTC_DEB periods before a valid detection occurs. See Figure 27-7 for an example. • Asynchronous (CTRLB.DEBASYNC = 1): The first edge on INn is detected. Further detection is blanked until INn remains stable for four CLK_RTC_DEB periods. See Figure 27-8 for an example. Majority debouncing is configured by the Debounce Majority Enable bit in the Control B register (CTRLB.DEBMAJ). INn must be valid for two out of three CLK_RTC_DEB periods. See Figure 27-9 for an example. Table 27-3. Debouncer Configuration TAMPCTRL. DEBNCn CTRLB. DEBMAJ CTRLB. DEBASYNC Description 0 X X Detect edge on INn with no debouncing. Every edge detected is immediately triggered. 1 0 0 Detect edge on INn with synchronous stability debouncing. Edge detected is only triggered when INn is stable for 4 consecutive CLK_RTC_DEB periods. 1 0 1 Detect edge on INn with asynchronous stability debouncing. First detected edge is triggered immediately. All subsequent detected edges are SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 397 TAMPCTRL. DEBNCn CTRLB. DEBMAJ CTRLB. DEBASYNC Description ignored until INn is stable for 4 consecutive CLK_RTC_DEB periods. 1 1 X Detect edge on INn with majority debouncing. Pin INn is sampled for 3 consecutive CLK_RTC_DEB periods. Signal level is determined by majority-rule (LLL, LLH, LHL, HLL = '0' and LHH, HLH, HHL, HHH = '1'). Figure 27-6. Edge Detection with Debouncer Disabled CLK_RTC CLK_RTC_DEB IN OUT NE NE PE TAMLVL=0 CLK_RTC CLK_RTC_DEB IN OUT NE NE PE TAMLVL=1 PE NE PE PE NE PE Figure 27-7. Edge Detection with Synchronous Stability Debouncing OUT TAMLVL=0 CLK_RTC CLK_RTC_DEB IN OUT NE NE PE TAMLVL=1 PE NE PE Whenever an edge is detected, input must be stable for 4 consecutive CLK_RTC_DEB in order for edge to be considered valid CLK_RTC CLK_RTC_DEB IN NE NE PEPE NE PE Whenever an edge is detected, input must be stable for 4 consecutive CLK_RTC_DEB in order for edge to be considered valid SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 398 Figure 27-8. Edge Detection with Asynchronous Stability Debouncing CLK_RTC CLK_RTC_DEB IN OUT Once a new edge is detected, ignore subsequent edges until input is stable for 4 consecutive CLK_RTC_DEB NE NE PE TAMLVL=0 CLK_RTC CLK_RTC_DEB IN OUT Once a new edge is detected, ignore subsequent edges until input is stable for 4 consecutive CLK_RTC_DEB NE NE PE TAMLVL=1 PE NE PE PE NE PE Figure 27-9. Edge Detection with Majority Debouncing CLK_RTC CLK_RTC_DEB IN IN shift 0 IN shift 1 IN shift 2 MAJORITY3 OUT CLK_RTC CLK_RTC_DEB IN IN shift 0 IN shift 1 IN shift 2 MAJORITY3 OUT 11 1 0 0 0 TAMLVL=1 TAMLVL=0 0-to-1 transition 1-to-0 transition NE NE PEPE NE PE 0 0 0 11 1 11 1 11 1 0 0 0 NE NE PEPE NE PE 0 0 0 11 1 11 1 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 399 Related Links 27.3 Block Diagram 27.6.8.4.1 Timestamp 27.6.8.4.2 Active Layer Protection 27.6.8.4.1 Timestamp As part of tamper detection the RTC can capture the counter value (COUNT/CLOCK) into the TIMESTAMP register. Three CLK_RTC periods are required to detect the tampering condition and capture the value. The TIMESTAMP value can be read once the Tamper flag in the Interrupt Flag register (INTFLAG.TAMPER) is set. If the DMA Enable bit in the Control B register (CTRLB.DMAEN) is ‘1’, a DMA request will be triggered by the timestamp. In order to determine which tamper source caused a capture, the Tamper ID register (TAMPID) provides the detection status of each tamper channel and the tamper input event. A DMA transfer can then read both TIMESTAMP and TAMPID in succession. A new timestamp value cannot be captured until the Tamper flag is cleared, either by reading the timestamp or by writing a ‘1’ to INTFLAG.TAMPER. If several tamper conditions occur in a short window before the flag is cleared, only the first timestamp may be logged. However, the detection of each tamper will still be recorded in TAMPID. The Tamper Input Event (TAMPEVT) will always perform a timestamp capture. To capture on the external inputs (INn), the corresponding Input Action field in the Tamper Control register (TAMPCTRL.INnACT) must be written to ‘1’. If an input is set for wake functionality it does not capture the timestamp; however the Tamper flag and TAMPID will still be updated. Related Links 27.6.8.4 Tamper Detection 27.6.8.4.2 Active Layer Protection The RTC provides a mean of detecting broken traces on the PCB , also known as Active layer Protection. In this mode, a generated internal RTC signal can be directly routed over critical components on the board using RTC OUT output pin to one RTC INn input pin. A tamper condition is detected if there is a mismatch on the generated RTC signal. The Active Layer Protection mode and the generation of the RTC signal is enabled by setting the RTCOUT bit in the Control B register (CTRLB.RTCOUT). Enabling active layer protection requires the following steps: • Enable the RTC prescaler output by writing a one to the RTC Out bit in the Control B register (CTRLB.RTCOUT). The I/O pins must also be configured to correctly route the signal to the external pins. • Select the frequency of the output signal by configuring the RTC Active Layer Frequency field in the Control B register (CTRLB.ACTF). GCLK_RTC_OUT = CLK_RTC 2 CTRLB.ACTF +1 • Enable the tamper input n (INn) in active layer mode by writing 3 to the corresponding Input Action field in the Tamper Control register (TAMPCTRL.INnACT). When active layer protection is enabled and INn and OUTn pin are used, the value of INn is sampled on the falling edge of CLK_RTC and compared to the expected value of OUTn. Therefore up to one half of a CLK_RTC period is available for propagation delay through the trace. • Enable Acitive Layer Protection by setting CTRLB.RTCOUT bit. Related Links SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 400 27.6.8.4 Tamper Detection SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 401 27.7 Register Summary - Mode 0 - 32-Bit Counter Offset Name Bit Pos. 0x00 CTRLA 7:0 MATCHCLR MODE[1:0] ENABLE SWRST 15:8 COUNTSYNC GPTRST PRESCALER[3:0] 0x02 CTRLB 7:0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN 15:8 SEPTO ACTF[2:0] DEBF[2:0] 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO TAMPEREO CMPEO0 23:16 TAMPEVEI 31:24 PERDEO 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER CMP0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 COMP0 COUNT FREQCORR ENABLE SWRST 15:8 COUNTSYNC 23:16 GPn[1:0] 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 0x1C ... 0x1F Reserved 0x20 COMP 7:0 COMP[7:0] 15:8 COMP[15:8] 23:16 COMP[23:16] 31:24 COMP[31:24] 0x24 ... 0x3F Reserved 0x40 GP0 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x44 GP1 7:0 GP[7:0] SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 402 Offset Name Bit Pos. 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x48 ... 0x5F Reserved 0x60 TAMPCTRL 7:0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] 15:8 23:16 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 31:24 DEBNC3 DEBNC2 DEBNC1 DEBNC0 0x64 TIMESTAMP 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 COUNT[23:16] 31:24 COUNT[31:24] 0x68 TAMPID 7:0 TAMPID3 TAMPID2 TAMPID1 TAMPID0 15:8 23:16 31:24 TAMPEVT 0x6C TAMPCTRLB 7:0 ALSI3 ALSI2 ALSI1 ALSI0 15:8 23:16 31:24 27.8 Register Description - Mode 0 - 32-Bit Counter This Register Description section is valid if the RTC is in COUNT32 mode (CTRLA.MODE=0). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 403 27.8.1 Control A in COUNT32 mode (CTRLA.MODE=0) Name:  CTRLA Offset:  0x00 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNTSYNC GPTRST PRESCALER[3:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – COUNTSYNC COUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value Description 0 COUNT read synchronization is disabled 1 COUNT read synchronization is enabled Bit 14 – GPTRST GP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 404 Value Name Description 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bit 7 – MATCHCLR Clear on Match This bit defines if the counter is cleared or not on a match. This bit is not synchronized. Value Description 0 The counter is not cleared on a Compare/Alarm 0 match 1 The counter is cleared on a Compare/Alarm 0 match Bits 3:2 – MODE[1:0] Operating Mode This bit group defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is a delay between writing CTRLA.ENABLE and until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description 0 The peripheral is disabled 1 The peripheral is enabled Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description 0 There is not reset operation ongoing 1 The reset operation is ongoing SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 405 27.8.2 Control B in COUNT32 mode (CTRLA.MODE=0) Name:  CTRLB Offset:  0x02 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 SEPTO ACTF[2:0] DEBF[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – SEPTO Separate Tamper Outputs Value Description 0 IN[n] is compared to OUT[0]. 1 IN[n] is compared to OUT[n]. Bits 14:12 – ACTF[2:0] Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_OUT = CLK_RTC / 2 0x1 DIV4 CLK_RTC_OUT = CLK_RTC / 4 0x2 DIV8 CLK_RTC_OUT = CLK_RTC / 8 0x3 DIV16 CLK_RTC_OUT = CLK_RTC / 16 0x4 DIV32 CLK_RTC_OUT = CLK_RTC / 32 0x5 DIV64 CLK_RTC_OUT = CLK_RTC / 64 0x6 DIV128 CLK_RTC_OUT = CLK_RTC / 128 0x7 DIV256 CLK_RTC_OUT = CLK_RTC / 256 Bits 10:8 – DEBF[2:0] Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_DEB = CLK_RTC / 2 0x1 DIV4 CLK_RTC_DEB = CLK_RTC / 4 0x2 DIV8 CLK_RTC_DEB = CLK_RTC / 8 0x3 DIV16 CLK_RTC_DEB = CLK_RTC / 16 0x4 DIV32 CLK_RTC_DEB = CLK_RTC / 32 0x5 DIV64 CLK_RTC_DEB = CLK_RTC / 64 0x6 DIV128 CLK_RTC_DEB = CLK_RTC / 128 0x7 DIV256 CLK_RTC_DEB = CLK_RTC / 256 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 406 Bit 7 – DMAEN DMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value Description 0 Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. 1 Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 – RTCOUT RTC Output Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values. 1 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN General Purpose 0 Enable Value Description 0 COMP0 compare function enabled. GP0/GP1 disabled. 1 COMP0 compare function disabled. GP0/GP1 enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 407 27.8.3 Event Control in COUNT32 mode (CTRLA.MODE=0) Name:  EVCTRL Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 PERDEO Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 TAMPEVEI Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 OVFEO TAMPEREO CMPEO0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 24 – PERDEO Periodic Interval Daily Event Output Enable Value Description 0 Periodic Daily event is disabled and will not be generated. 1 Periodic Daily event is enabled and will be generated. The event occurs at the overflow of the RTC counter (i.e., when the RTC counter goes from 0xFFFF to 0x0000). Bit 16 – TAMPEVEI Tamper Event Input Enable Value Description 0 Tamper event input is disabled and incoming events will be ignored. 1 Tamper event input is enabled and incoming events will capture the COUNT value. Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 14 – TAMPEREO Tamper Event Output Enable SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 408 Value Description 0 Tamper event output is disabled and will not be generated. 1 Tamper event output is enabled and will be generated for every tamper input. Bit 8 – CMPEO0 Compare 0 Event Output Enable Value Description 0 Compare 0 event is disabled and will not be generated. 1 Compare 0 event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 7..0] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 409 27.8.4 Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0) Name:  INTENCLR Offset:  0x08 Reset:  0x0000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this but will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bit 8 – CMP0 Compare 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare 0 Interrupt Enable bit, which disables the Compare 0 interrupt. Value Description 0 The Compare 0 interrupt is disabled. 1 The Compare 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 410 Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 411 27.8.5 Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0) Name:  INTENSET Offset:  0x0A Reset:  0x0000 Property:  PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bit 8 – CMP0 Compare 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare 0 Interrupt Enable bit, which enables the Compare 0 interrupt. Value Description 0 The Compare 0 interrupt is disabled. 1 The Compare 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 412 Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 413 27.8.6 Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0) Name:  INTFLAG Offset:  0x0C Reset:  0x0000 Property:  - Bit 15 14 13 12 11 10 9 8 OVF TAMPER CMP0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 – TAMPER Tamper event This flag is set after a damper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/INTENSET.TAMPER is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Tamper interrupt flag. Bit 8 – CMP0 Compare 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMP0 is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare 0 interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 414 27.8.7 Debug Control Name:  DBGCTRL Offset:  0x0E Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger. 1 The RTC continues normal operation when the CPU is halted by an external debugger. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 415 27.8.8 Synchronization Busy in COUNT32 mode (CTRLA.MODE=0) Name:  SYNCBUSY Offset:  0x10 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 GPn[1:0] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 COUNTSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 COMP0 COUNT FREQCORR ENABLE SWRST Access R R R R R Reset 0 0 0 0 0 Bits 17:16 – GPn[1:0] General Purpose n Synchronization Busy Status Value Description 0 Write synchronization for GPn register is complete. 1 Write synchronization for GPn register is ongoing. Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.COUNTSYNC bit is complete. 1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bit 5 – COMP0 Compare 0 Synchronization Busy Status Value Description 0 Write synchronization for COMP0 register is complete. 1 Write synchronization for COMP0 register is ongoing. Bit 3 – COUNT Count Value Synchronization Busy Status Value Description 0 Read/write synchronization for COUNT register is complete. 1 Read/write synchronization for COUNT register is ongoing. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 416 Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 417 27.8.9 Frequency Correction Name:  FREQCORR Offset:  0x14 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SIGN VALUE[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased. Bits 6:0 – VALUE[6:0] Correction Value These bits define the amount of correction applied to the RTC prescaler. Value Description 0 Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 418 27.8.10 Counter Value in COUNT32 mode (CTRLA.MODE=0) Name:  COUNT Offset:  0x18 Reset:  0x00000000 Property:  PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COUNT[31:0] Counter Value These bits define the value of the 32-bit RTC counter in mode 0. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 419 27.8.11 Compare 0 Value in COUNT32 mode (CTRLA.MODE=0) Name:  COMP Offset:  0x20 Reset:  0x00000000 Property:  PAC Write-Protection, Write-Synchronized Bit 31 30 29 28 27 26 25 24 COMP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COMP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COMP[31:0] Compare Value The 32-bit value of COMP0 is continuously compared with the 32-bit COUNT value. When a match occurs, the Compare 0 interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next counter cycle, and the counter value is cleared if CTRLA.MATCHCLR is '1'. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 420 27.8.12 General Purpose n Name:  GP Offset:  0x40 + n*0x04 [n=0..1] Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 GP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – GP[31:0] General Purpose These bits are for user-defined general purpose use, see 27.6.8.3 General Purpose Registers. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 421 27.8.13 Tamper Control Name:  TAMPCTRL Offset:  0x60 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DEBNC3 DEBNC2 DEBNC1 DEBNC0 Access Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 Access Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] Access Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27 – DEBNC Debounce Enable of Tamper Input INn Value Description 0 Debouncing is disabled for Tamper input INn 1 Debouncing is enabled for Tamper input INn Bits 16, 17, 18, 19 – TAMLVL Tamper Level Select of Tamper Input INn Value Description 0 A falling edge condition will be detected on Tamper input INn. 1 A rising edge condition will be detected on Tamper input INn. Bits 0:1, 2:3, 4:5, 6:7 – INACT Tamper Channel n Action These bits determine the action taken by Tamper Channel n. Value Name Description 0x0 OFF Off (Disabled) 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 422 27.8.14 Timestamp Name:  TIMESTAMP Offset:  0x64 Reset:  0x0 Property:  Read-Only Bit 31 30 29 28 27 26 25 24 COUNT[31:24] Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 COUNT[23:16] Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 Bits 31:0 – COUNT[31:0] Count Timestamp Value The 32-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 423 27.8.15 Tamper ID Name:  TAMPID Offset:  0x68 Reset:  0x00000000 Bit 31 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TAMPID3 TAMPID2 TAMPID1 TAMPID0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description 0 A tamper input event has not been detected 1 A tamper input event has been detected Bits 0, 1, 2, 3 – TAMPID Tamper on Channel n Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description 0 A tamper condition has not been detected on Channel n 1 A tamper condition has been detected on Channel n SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 424 27.8.16 Tamper Control B Name:  TAMPCTRLB Offset:  0x6C Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ALSI3 ALSI2 ALSI1 ALSI0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 0, 1, 2, 3 – ALSI Active Layer Internal Select n Value Description 0 Active layer Protection is monitoring the RTC signal using INn and OUTn tamper pins 1 Active layer Protection is monitoring the RTC signal on the TrustRAM shield SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 425 27.9 Register Summary - Mode 1 - 16-Bit Counter Offset Name Bit Pos. 0x00 CTRLA 7:0 MODE[1:0] ENABLE SWRST 15:8 COUNTSYNC GPTRST PRESCALER[3:0] 0x02 CTRLB 7:0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN 15:8 SEPTO ACTF[2:0] DEBF[2:0] 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO TAMPEREO CMPEO1 CMPEO0 23:16 TAMPEVEI 31:24 PERDEO 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 15:8 OVF TAMPER 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 15:8 OVF TAMPER 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 15:8 OVF TAMPER 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST 15:8 COUNTSYNC 23:16 GPn[1:0] 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 COUNT 7:0 COUNT[7:0] 15:8 COUNT[15:8] 0x1A ... 0x1B Reserved 0x1C PER 7:0 PER[7:0] 15:8 PER[15:8] 0x1E ... 0x1F Reserved 0x20 COMP0 7:0 COMP[7:0] 15:8 COMP[15:8] 0x22 COMP1 7:0 COMP[7:0] 15:8 COMP[15:8] 0x24 ... 0x3F Reserved 0x40 GP0 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 426 Offset Name Bit Pos. 31:24 GP[31:24] 0x44 GP1 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x48 ... 0x5F Reserved 0x60 TAMPCTRL 7:0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] 15:8 23:16 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 31:24 DEBNC3 DEBNC2 DEBNC1 DEBNC0 0x64 TIMESTAMP 7:0 COUNT[7:0] 15:8 COUNT[15:8] 23:16 31:24 0x68 TAMPID 7:0 TAMPID3 TAMPID2 TAMPID1 TAMPID0 15:8 23:16 31:24 TAMPEVT 0x6C TAMPCTRLB 7:0 ALSI3 ALSI2 ALSI1 ALSI0 15:8 23:16 31:24 27.10 Register Description - Mode 1 - 16-Bit Counter This Register Description section is valid if the RTC is in COUNT16 mode (CTRLA.MODE=1). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 427 Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 428 27.10.1 Control A in COUNT16 mode (CTRLA.MODE=1) Name:  CTRLA Offset:  0x00 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COUNTSYNC GPTRST PRESCALER[3:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – COUNTSYNC COUNT Read Synchronization Enable The COUNT register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the COUNT register. This bit is not enable-protected. Value Description 0 COUNT read synchronization is disabled 1 COUNT read synchronization is enabled Bit 14 – GPTRST GP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 GPn registers will not reset when a tamper condition occurs. 1 GPn registers will reset when a tamper condition occurs. Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 429 Value Name Description 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description 0 The peripheral is disabled 1 The peripheral is enabled Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. Value Description 0 There is not reset operation ongoing 1 The reset operation is ongoing SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 430 27.10.2 Control B in COUNT16 mode (CTRLA.MODE=1) Name:  CTRLB Offset:  0x02 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 SEPTO ACTF[2:0] DEBF[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – SEPTO Separate Tamper Outputs Value Description 0 IN[n] is compared to OUT[0] (backward-compatible). 1 IN[n] is compared to OUT[n]. Bits 14:12 – ACTF[2:0] Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_OUT = CLK_RTC / 2 0x1 DIV4 CLK_RTC_OUT = CLK_RTC / 4 0x2 DIV8 CLK_RTC_OUT = CLK_RTC / 8 0x3 DIV16 CLK_RTC_OUT = CLK_RTC / 16 0x4 DIV32 CLK_RTC_OUT = CLK_RTC / 32 0x5 DIV64 CLK_RTC_OUT = CLK_RTC / 64 0x6 DIV128 CLK_RTC_OUT = CLK_RTC / 128 0x7 DIV256 CLK_RTC_OUT = CLK_RTC / 256 Bits 10:8 – DEBF[2:0] Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_DEB = CLK_RTC / 2 0x1 DIV4 CLK_RTC_DEB = CLK_RTC / 4 0x2 DIV8 CLK_RTC_DEB = CLK_RTC / 8 0x3 DIV16 CLK_RTC_DEB = CLK_RTC / 16 0x4 DIV32 CLK_RTC_DEB = CLK_RTC / 32 0x5 DIV64 CLK_RTC_DEB = CLK_RTC / 64 0x6 DIV128 CLK_RTC_DEB = CLK_RTC / 128 0x7 DIV256 CLK_RTC_DEB = CLK_RTC / 256 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 431 Bit 7 – DMAEN DMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value Description 0 Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. 1 Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 – RTCOUT RTC Output Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values. 1 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN General Purpose 0 Enable Value Description 0 COMP0 compare function enabled. GP0/GP1 disabled. 1 COMP0 compare function disabled. GP0/GP1 enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 432 27.10.3 Event Control in COUNT16 mode (CTRLA.MODE=1) Name:  EVCTRL Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 PERDEO Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 TAMPEVEI Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 OVFEO TAMPEREO CMPEO1 CMPEO0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 24 – PERDEO Periodic Interval Daily Event Output Enable Value Description 0 Periodic Daily event is disabled and will not be generated. 1 Periodic Daily event is enabled and will be generated. The event occurs at the overflow of the RTC counter (i.e., when the RTC counter goes from 0xFFFF to 0x0000). Bit 16 – TAMPEVEI Tamper Event Input Enable Value Description 0 Tamper event input is disabled, and incoming events will be ignored 1 Tamper event input is enabled, and incoming events will capture the COUNT value Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. Bit 14 – TAMPEREO Tamper Event Output Enable SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 433 Value Description 0 Tamper event output is disabled, and will not be generated. 1 Tamper event output is enabled, and will be generated for every tamper input. Bits 8, 9 – CMPEOn Compare n Event Output Enable [n = 1..0] Value Description 0 Compare n event is disabled and will not be generated. 1 Compare n event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 7..0] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 434 27.10.4 Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1) Name:  INTENCLR Offset:  0x08 Reset:  0x0000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Tamper Interrupt Enable bit, which disables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bits 0, 1 – CMPn Compare n Interrupt Enable [n = 1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Compare n Interrupt Enable bit, which disables the Compare n interrupt. Value Description 0 The Compare n interrupt is disabled. 1 The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 435 27.10.5 Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1) Name:  INTENSET Offset:  0x0A Reset:  0x0000 Property:  PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value Description 0 The Tamper interrupt is disabled. 1 The Tamper interrupt is enabled. Bits 0, 1 – CMPn Compare n Interrupt Enable [n = 1..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Compare n Interrupt Enable bit, which and enables the Compare n interrupt. Value Description 0 The Compare n interrupt is disabled. 1 The Compare n interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 436 27.10.6 Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1) Name:  INTFLAG Offset:  0x0C Reset:  0x0000 Property:  - Bit 15 14 13 12 11 10 9 8 OVF TAMPER Access R/W R/W Reset 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 CMP1 CMP0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 – TAMPER Tamper This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/ INTENSET.TAMPER is one. Writing a '0' to this bit has no effect. Writing a one to this bit clears the Tamper interrupt flag. Bits 0, 1 – CMPn Compare n [n = 1..0] This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.COMPn is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Compare n interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 437 27.10.7 Debug Control Name:  DBGCTRL Offset:  0x0E Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger. 1 The RTC continues normal operation when the CPU is halted by an external debugger. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 438 27.10.8 Synchronization Busy in COUNT16 mode (CTRLA.MODE=1) Name:  SYNCBUSY Offset:  0x10 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 GPn[1:0] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 COUNTSYNC Access R Reset 0 Bit 7 6 5 4 3 2 1 0 COMP1 COMP0 PER COUNT FREQCORR ENABLE SWRST Access R/W R/W R R R R R Reset 0 0 0 0 0 0 0 Bits 17:16 – GPn[1:0] General Purpose n Synchronization Busy Status Value Description 0 Write synchronization for GPn register is complete. 1 Write synchronization for GPn register is ongoing. Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.COUNTSYNC bit is complete. 1 Write synchronization for CTRLA.COUNTSYNC bit is ongoing. Bits 5, 6 – COMPn Compare n Synchronization Busy Status [n = 1..0] Value Description 0 Write synchronization for COMPn register is complete. 1 Write synchronization for COMPn register is ongoing. Bit 4 – PER Period Synchronization Busy Status Value Description 0 Write synchronization for PER register is complete. 1 Write synchronization for PER register is ongoing. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 439 Bit 3 – COUNT Count Value Synchronization Busy Status Value Description 0 Read/write synchronization for COUNT register is complete. 1 Read/write synchronization for COUNT register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 440 27.10.9 Frequency Correction Name:  FREQCORR Offset:  0x14 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SIGN VALUE[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased. Bits 6:0 – VALUE[6:0] Correction Value These bits define the amount of correction applied to the RTC prescaler. Value Description 0 Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 441 27.10.10 Counter Value in COUNT16 mode (CTRLA.MODE=1) Name:  COUNT Offset:  0x18 Reset:  0x0000 Property:  PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Counter Value These bits define the value of the 16-bit RTC counter in COUNT16 mode (CTRLA.MODE=1). SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 442 27.10.11 Counter Period in COUNT16 mode (CTRLA.MODE=1) Name:  PER Offset:  0x1C Reset:  0x0000 Property:  PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 PER[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PER[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – PER[15:0] Counter Period These bits define the value of the 16-bit RTC period in COUNT16 mode (CTRLA.MODE=1). SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 443 27.10.12 Compare n Value in COUNT16 mode (CTRLA.MODE=1) Name:  COMP Offset:  0x20 + n*0x02 [n=0..1] Reset:  0x0000 Property:  PAC Write-Protection, Write-Synchronized Bit 15 14 13 12 11 10 9 8 COMP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COMP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COMP[15:0] Compare Value The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter cycle. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 444 27.10.13 General Purpose n Name:  GP Offset:  0x40 + n*0x04 [n=0..1] Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 GP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – GP[31:0] General Purpose These bits are for user-defined general purpose use, see 27.6.8.3 General Purpose Registers. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 445 27.10.14 Tamper Control Name:  TAMPCTRL Offset:  0x60 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DEBNC3 DEBNC2 DEBNC1 DEBNC0 Access Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 Access Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] Access Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27 – DEBNC Debounce Enable of Tamper Input INn Value Description 0 Debouncing is disabled for Tamper input INn 1 Debouncing is enabled for Tamper input INn Bits 16, 17, 18, 19 – TAMLVL Tamper Level Select of Tamper Input INn Value Description 0 A falling edge condition will be detected on Tamper input INn. 1 A rising edge condition will be detected on Tamper input INn. Bits 0:1, 2:3, 4:5, 6:7 – INACT Tamper Channel n Action These bits determine the action taken by Tamper Channel n. Value Name Description 0x0 OFF Off (Disabled) 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 446 27.10.15 Timestamp Name:  TIMESTAMP Offset:  0x64 Reset:  0x0000 Property:  Read-Only Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 COUNT[15:8] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COUNT[7:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 15:0 – COUNT[15:0] Count Timestamp Value The 16-bit value of COUNT is captured by the TIMESTAMP when a tamper condition occurs. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 447 27.10.16 Tamper ID Name:  TAMPID Offset:  0x68 Reset:  0x00000000 Bit 31 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TAMPID3 TAMPID2 TAMPID1 TAMPID0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description 0 A tamper input event has not been detected 1 A tamper input event has been detected Bits 0, 1, 2, 3 – TAMPID Tamper on Channel n Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description 0 A tamper condition has not been detected on Channel n 1 A tamper condition has been detected on Channel n SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 448 27.10.17 Tamper Control B Name:  TAMPCTRLB Offset:  0x6C Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ALSI3 ALSI2 ALSI1 ALSI0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 0, 1, 2, 3 – ALSI Active Layer Internal Select n Value Description 0 Active layer Protection is monitoring the RTC signal using INn and OUTn tamper pins 1 Active layer Protection is monitoring the RTC signal on the TrustRAM shield SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 449 27.11 Register Summary - Mode 2 - Clock/Calendar Offset Name Bit Pos. 0x00 CTRLA 7:0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST 15:8 CLOCKSYNC GPTRST PRESCALER[3:0] 0x02 CTRLB 7:0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN 15:8 SEPTO ACTF[2:0] DEBF[2:0] 0x04 EVCTRL 7:0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 15:8 OVFEO TAMPEREO ALARMEO 23:16 TAMPEVEI 31:24 PERDEO 0x08 INTENCLR 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER ALARM0 0x0A INTENSET 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER ALARM0 0x0C INTFLAG 7:0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 15:8 OVF TAMPER ALARM0 0x0E DBGCTRL 7:0 DBGRUN 0x0F Reserved 0x10 SYNCBUSY 7:0 ALARM0 CLOCK FREQCORR ENABLE SWRST 15:8 CLOCKSYNC MASK0 23:16 GPn[1:0] 31:24 0x14 FREQCORR 7:0 SIGN VALUE[6:0] 0x15 ... 0x17 Reserved 0x18 CLOCK 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4:4] 31:24 YEAR[5:0] MONTH[3:2] 0x1C ... 0x1F Reserved 0x20 ALARM 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4:4] 31:24 YEAR[5:0] MONTH[3:2] 0x24 MASK 7:0 SEL[2:0] 0x25 ... 0x3F Reserved 0x40 GP0 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 450 Offset Name Bit Pos. 0x44 GP1 7:0 GP[7:0] 15:8 GP[15:8] 23:16 GP[23:16] 31:24 GP[31:24] 0x48 ... 0x5F Reserved 0x60 TAMPCTRL 7:0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] 15:8 23:16 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 31:24 DEBNC3 DEBNC2 DEBNC1 DEBNC0 0x64 TIMESTAMP 7:0 MINUTE[1:0] SECOND[5:0] 15:8 HOUR[3:0] MINUTE[5:2] 23:16 MONTH[1:0] DAY[4:0] HOUR[4:4] 31:24 YEAR[5:0] MONTH[3:2] 0x68 TAMPID 7:0 TAMPID3 TAMPID2 TAMPID1 TAMPID0 15:8 23:16 31:24 TAMPEVT 0x6C TAMPCTRLB 7:0 ALSI3 ALSI2 ALSI1 ALSI0 15:8 23:16 31:24 27.12 Register Description - Mode 2 - Clock/Calendar This Register Description section is valid if the RTC is in Clock/Calendar mode (CTRLA.MODE=2). Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers require synchronization when read and/or written. Synchronization is denoted by the "Read-Synchronized" and/or "Write-Synchronized" property in each individual register description. Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. Some registers are enable-protected, meaning they can only be written when the module is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 451 Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 452 27.12.1 Control A in Clock/Calendar mode (CTRLA.MODE=2) Name:  CTRLA Offset:  0x00 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected, Write-Synchronized Bit 15 14 13 12 11 10 9 8 CLOCKSYNC GPTRST PRESCALER[3:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MATCHCLR CLKREP MODE[1:0] ENABLE SWRST Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 15 – CLOCKSYNC CLOCK Read Synchronization Enable The CLOCK register requires synchronization when reading. Disabling the synchronization will prevent reading valid values from the CLOCK register. This bit is not enable-protected. Value Description 0 CLOCK read synchronization is disabled 1 CLOCK read synchronization is enabled Bit 14 – GPTRST GP Registers Reset On Tamper Enable Only GP registers enabled by the CTRLB.GPnEN bits are affected. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Bits 11:8 – PRESCALER[3:0] Prescaler These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock (CLK_RTC_CNT). Periodic events and interrupts are not available when the prescaler is off. These bits are not synchronized. Value Name Description 0x0 OFF CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x2 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x3 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x4 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x5 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x6 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x7 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x8 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x9 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0xA DIV512 CLK_RTC_CNT = GCLK_RTC/512 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 453 Value Name Description 0xB DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xC-0xF - Reserved Bit 7 – MATCHCLR Clear on Match This bit is valid only in Mode 0 (COUNT32) and Mode 2 (CLOCK). This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 The counter is not cleared on a Compare/Alarm 0 match 1 The counter is cleared on a Compare/Alarm 0 match Bit 6 – CLKREP Clock Representation This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled. This bit is not synchronized. Value Description 0 24 Hour 1 12 Hour (AM/PM) Bits 3:2 – MODE[1:0] Operating Mode This field defines the operating mode of the RTC. This bit is not synchronized. Value Name Description 0x0 COUNT32 Mode 0: 32-bit counter 0x1 COUNT16 Mode 1: 16-bit counter 0x2 CLOCK Mode 2: Clock/calendar 0x3 - Reserved Bit 1 – ENABLE Enable Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/ disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete. Value Description 0 The peripheral is disabled 1 The peripheral is enabled Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be disabled. Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 454 Value Description 0 There is not reset operation ongoing 1 The reset operation is ongoing SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 455 27.12.2 Control B in Clock/Calendar mode (CTRLA.MODE=2) Name:  CTRLB Offset:  0x2 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 SEPTO ACTF[2:0] DEBF[2:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DMAEN RTCOUT DEBASYNC DEBMAJ GP0EN Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 – SEPTO Separate Tamper Outputs Value Description 0 IN[n] is compared tp OUT[0] (backward-compatible). 1 IN[n] is compared tp OUT[n]. Bits 14:12 – ACTF[2:0] Active Layer Frequency These bits define the prescaling factor for the RTC clock output (OUT) used during active layer protection in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_OUT = CLK_RTC / 2 0x1 DIV4 CLK_RTC_OUT = CLK_RTC / 4 0x2 DIV8 CLK_RTC_OUT = CLK_RTC / 8 0x3 DIV16 CLK_RTC_OUT = CLK_RTC / 16 0x4 DIV32 CLK_RTC_OUT = CLK_RTC / 32 0x5 DIV64 CLK_RTC_OUT = CLK_RTC / 64 0x6 DIV128 CLK_RTC_OUT = CLK_RTC / 128 0x7 DIV256 CLK_RTC_OUT = CLK_RTC / 256 Bits 10:8 – DEBF[2:0] Debounce Frequency These bits define the prescaling factor for the input debouncers in terms of the CLK_RTC. Value Name Description 0x0 DIV2 CLK_RTC_DEB = CLK_RTC / 2 0x1 DIV4 CLK_RTC_DEB = CLK_RTC / 4 0x2 DIV8 CLK_RTC_DEB = CLK_RTC / 8 0x3 DIV16 CLK_RTC_DEB = CLK_RTC / 16 0x4 DIV32 CLK_RTC_DEB = CLK_RTC / 32 0x5 DIV64 CLK_RTC_DEB = CLK_RTC / 64 0x6 DIV128 CLK_RTC_DEB = CLK_RTC / 128 0x7 DIV256 CLK_RTC_DEB = CLK_RTC / 256 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 456 Bit 7 – DMAEN DMA Enable The RTC can trigger a DMA request when the timestamp is ready in the TIMESTAMP register. Value Description 0 Tamper DMA request is disabled. Reading TIMESTAMP has no effect on INTFLAG.TAMPER. 1 Tamper DMA request is enabled. Reading TIMESTAMP will clear INTFLAG.TAMPER. Bit 6 – RTCOUT RTC Out Enable Value Description 0 The RTC active layer output is disabled. 1 The RTC active layer output is enabled. Bit 5 – DEBASYNC Debouncer Asynchronous Enable Value Description 0 The tamper input debouncers operate synchronously. 1 The tamper input debouncers operate asynchronously. Bit 4 – DEBMAJ Debouncer Majority Enable Value Description 0 The tamper input debouncers match three equal values. 1 The tamper input debouncers match majority two of three values. Bit 0 – GP0EN General Purpose 0 Enable Value Description 0 COMP0 compare function enabled. GP0 disabled. 1 COMP0 compare function disabled. GP0 enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 457 27.12.3 Event Control in Clock/Calendar mode (CTRLA.MODE=2) Name:  EVCTRL Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 PERDEO Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 TAMPEVEI Access R/W Reset 0 Bit 15 14 13 12 11 10 9 8 OVFEO TAMPEREO ALARMEO Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PEREO7 PEREO6 PEREO5 PEREO4 PEREO3 PEREO2 PEREO1 PEREO0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 24 – PERDEO Periodic Interval Daily Event Output Enable Value Description 0 Periodic Daily event is disabled and will not be generated. 1 Periodic Daily event is enabled and will be generated. The event occurs at the last second of each day depending on the CTRLA.CLKREP bit: • If CLKREP = 0, the event will occur at 23:59:59 • If CLKREP = 1, the event will occur at 11:59:59, PM = 1 Bit 16 – TAMPEVEI Tamper Event Input Enable Value Description 0 Tamper event input is disabled, and incoming events will be ignored. 1 Tamper event input is enabled, and all incoming events will capture the CLOCK value. Bit 15 – OVFEO Overflow Event Output Enable Value Description 0 Overflow event is disabled and will not be generated. 1 Overflow event is enabled and will be generated for every overflow. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 458 Bit 14 – TAMPEREO Tamper Event Output Enable Value Description 0 Tamper event output is disabled, and will not be generated 1 Tamper event output is enabled, and will be generated for every tamper input. Bit 8 – ALARMEO Alarm 0 Event Output Enable Value Description 0 Alarm 0 event is disabled and will not be generated. 1 Alarm 0 event is enabled and will be generated for every compare match. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PEREOn Periodic Interval n Event Output Enable [n = 7..0] Value Description 0 Periodic Interval n event is disabled and will not be generated. 1 Periodic Interval n event is enabled and will be generated. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 459 27.12.4 Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2) Name:  INTENCLR Offset:  0x08 Reset:  0x0000 Property:  PAC Write-Protection This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Overflow Interrupt Enable bit, which disables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Bit 8 – ALARM0 Alarm 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Alarm 0 Interrupt Enable bit, which disables the Alarm interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Periodic Interval n Interrupt Enable bit, which disables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 460 27.12.5 Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2) Name:  INTENSET Offset:  0x0A Reset:  0x0000 Property:  PAC Write-Protection This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register. Bit 15 14 13 12 11 10 9 8 OVF TAMPER ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Overflow Interrupt Enable bit, which enables the Overflow interrupt. Value Description 0 The Overflow interrupt is disabled. 1 The Overflow interrupt is enabled. Bit 14 – TAMPER Tamper Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Tamper Interrupt Enable bit, which enables the Tamper interrupt. Value Description 0 The Tamper interrupt it disabled. 1 The Tamper interrupt is enabled. Bit 8 – ALARM0 Alarm 0 Interrupt Enable Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Alarm 0 Interrupt Enable bit, which enables the Alarm 0 interrupt. Value Description 0 The Alarm 0 interrupt is disabled. 1 The Alarm 0 interrupt is enabled. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n Interrupt Enable [n = 7..0] Writing a '0' to this bit has no effect. Writing a '1' to this bit will set the Periodic Interval n Interrupt Enable bit, which enables the Periodic Interval n interrupt. Value Description 0 Periodic Interval n interrupt is disabled. 1 Periodic Interval n interrupt is enabled. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 461 27.12.6 Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2) Name:  INTFLAG Offset:  0x0C Reset:  0x0000 Property:  - Bit 15 14 13 12 11 10 9 8 OVF TAMPER ALARM0 Access R/W R/W R/W Reset 0 0 0 Bit 7 6 5 4 3 2 1 0 PER7 PER6 PER5 PER4 PER3 PER2 PER1 PER0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 – OVF Overflow This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will be generated if INTENCLR/SET.OVF is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Overflow interrupt flag. Bit 14 – TAMPER Tamper This flag is set after a tamper condition occurs, and an interrupt request will be generated if INTENCLR.TAMPER/INTENSET.TAMPER is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Tamper interrupt flag. Bit 8 – ALARM0 Alarm 0 This flag is cleared by writing a '1' to the flag. This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt request will be generated if INTENCLR/SET.ALARM0 is one. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Alarm 0 interrupt flag. Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0] This flag is cleared by writing a '1' to the flag. This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request will be generated if INTENCLR/SET.PERx is '1'. Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the Periodic Interval n interrupt flag. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 462 27.12.7 Debug Control Name:  DBGCTRL Offset:  0x0E Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The RTC is halted when the CPU is halted by an external debugger. 1 The RTC continues normal operation when the CPU is halted by an external debugger. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 463 27.12.8 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2) Name:  SYNCBUSY Offset:  0x10 Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 GPn[1:0] Access R R Reset 0 0 Bit 15 14 13 12 11 10 9 8 CLOCKSYNC MASK0 Access R R Reset 0 0 Bit 7 6 5 4 3 2 1 0 ALARM0 CLOCK FREQCORR ENABLE SWRST Access R R R R R Reset 0 0 0 0 0 Bits 17:16 – GPn[1:0] General Purpose n Synchronization Busy Status Value Description 0 Write synchronization for GPn register is complete. 1 Write synchronization for GPn register is ongoing. Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.CLOCKSYNC bit is complete. 1 Write synchronization for CTRLA.CLOCKSYNC bit is ongoing. Bit 11 – MASK0 Mask 0 Synchronization Busy Status Value Description 0 Write synchronization for MASK0 register is complete. 1 Write synchronization for MASK0 register is ongoing. Bit 5 – ALARM0 Alarm 0 Synchronization Busy Status Value Description 0 Write synchronization for ALARM0 register is complete. 1 Write synchronization for ALARM0 register is ongoing. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 464 Bit 3 – CLOCK Clock Register Synchronization Busy Status Value Description 0 Read/write synchronization for CLOCK register is complete. 1 Read/write synchronization for CLOCK register is ongoing. Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status Value Description 0 Write synchronization for FREQCORR register is complete. 1 Write synchronization for FREQCORR register is ongoing. Bit 1 – ENABLE Enable Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.ENABLE bit is complete. 1 Write synchronization for CTRLA.ENABLE bit is ongoing. Bit 0 – SWRST Software Reset Synchronization Busy Status Value Description 0 Write synchronization for CTRLA.SWRST bit is complete. 1 Write synchronization for CTRLA.SWRST bit is ongoing. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 465 27.12.9 Frequency Correction Name:  FREQCORR Offset:  0x14 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SIGN VALUE[6:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 – SIGN Correction Sign Value Description 0 The correction value is positive, i.e., frequency will be decreased. 1 The correction value is negative, i.e., frequency will be increased. Bits 6:0 – VALUE[6:0] Correction Value These bits define the amount of correction applied to the RTC prescaler. Value Description 0 Correction is disabled and the RTC frequency is unchanged. 1 - 127 The RTC frequency is adjusted according to the value. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 466 27.12.10 Clock Value in Clock/Calendar mode (CTRLA.MODE=2) Name:  CLOCK Offset:  0x18 Reset:  0x00000000 Property:  PAC Write-Protection, Write-Synchronized, Read-Synchronized Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The year offset with respect to the reference year (defined in software). The year is considered a leap year if YEAR[1:0] is zero. Bits 25:22 – MONTH[3:0] Month 1 – January 2 – February ... 12 – December Bits 21:17 – DAY[4:0] Day Day starts at 1 and ends at 28, 29, 30, or 31, depending on the month and year. Bits 16:12 – HOUR[4:0] Hour When CTRLA.CLKREP=0, the Hour bit group is in 24-hour format, with values 0-23. When CTRLA.CLKREP=1, HOUR[3:0] has values 1-12, and HOUR[4] represents AM (0) or PM (1). Bits 11:6 – MINUTE[5:0] Minute 0 – 59 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 467 Bits 5:0 – SECOND[5:0] Second 0 – 59 SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 468 27.12.11 Alarm Value in Clock/Calendar mode (CTRLA.MODE=2) Name:  ALARM Offset:  0x20 Reset:  0x00000000 Property:  PAC Write-Protection, Write-Synchronized The 32-bit value of ALARM is continuously compared with the 32-bit CLOCK value, based on the masking set by MASK.SEL. When a match occurs, the Alarm n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.ALARM) is set on the next counter cycle, and the counter is cleared if CTRLA.MATCHCLR is '1'. Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4:4] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The alarm year. Years are only matched if MASK.SEL is 6 Bits 25:22 – MONTH[3:0] Month The alarm month. Months are matched only if MASK.SEL is greater than 4. Bits 21:17 – DAY[4:0] Day The alarm day. Days are matched only if MASK.SEL is greater than 3. Bits 16:12 – HOUR[4:0] Hour The alarm hour. Hours are matched only if MASK.SEL is greater than 2. Bits 11:6 – MINUTE[5:0] Minute The alarm minute. Minutes are matched only if MASK.SEL is greater than 1. Bits 5:0 – SECOND[5:0] Second The alarm second. Seconds are matched only if MASK.SEL is greater than 0. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 469 27.12.12 Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2) Name:  MASK Offset:  0x24 Reset:  0x00 Property:  PAC Write-Protection, Write-Synchronized Bit 7 6 5 4 3 2 1 0 SEL[2:0] Access R/W R/W R/W Reset 0 0 0 Bits 2:0 – SEL[2:0] Alarm Mask Selection These bits define which bit groups of ALARM are valid. Value Name Description 0x0 OFF Alarm Disabled 0x1 SS Match seconds only 0x2 MMSS Match seconds and minutes only 0x3 HHMMSS Match seconds, minutes, and hours only 0x4 DDHHMMSS Match seconds, minutes, hours, and days only 0x5 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x6 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x7 - Reserved SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 470 27.12.13 General Purpose n Name:  GP Offset:  0x40 + n*0x04 [n=0..1] Reset:  0x00000000 Property:  - Bit 31 30 29 28 27 26 25 24 GP[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 GP[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 GP[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 GP[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – GP[31:0] General Purpose These bits are for user-defined general purpose use, see 27.6.8.3 General Purpose Registers. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 471 27.12.14 Tamper Control Name:  TAMPCTRL Offset:  0x60 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 DEBNC3 DEBNC2 DEBNC1 DEBNC0 Access Reset 0 0 0 0 Bit 23 22 21 20 19 18 17 16 TAMLVL3 TAMLVL2 TAMLVL1 TAMLVL0 Access Reset 0 0 0 0 Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 IN3ACT[1:0] IN2ACT[1:0] IN1ACT[1:0] IN0ACT[1:0] Access Reset 0 0 0 0 0 0 0 0 Bits 24, 25, 26, 27 – DEBNC Debounce Enable of Tamper Input INn Value Description 0 Debouncing is disabled for Tamper input INn 1 Debouncing is enabled for Tamper input INn Bits 16, 17, 18, 19 – TAMLVL Tamper Level Select of Tamper Input INn Value Description 0 A falling edge condition will be detected on Tamper input INn. 1 A rising edge condition will be detected on Tamper input INn. Bits 0:1, 2:3, 4:5, 6:7 – INACT Tamper Channel n Action These bits determine the action taken by Tamper Channel n. Value Name Description 0x0 OFF Off (Disabled) 0x1 WAKE Wake and set Tamper flag 0x2 CAPTURE Capture timestamp and set Tamper flag 0x3 ACTL Compare RTC signal routed between INn and OUT pins . When a mismatch occurs, capture timestamp and set Tamper flag SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 472 27.12.15 Timestamp Value Name:  TIMESTAMP Offset:  0x64 Reset:  0 Property:  R Bit 31 30 29 28 27 26 25 24 YEAR[5:0] MONTH[3:2] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 MONTH[1:0] DAY[4:0] HOUR[4:4] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 HOUR[3:0] MINUTE[5:2] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 MINUTE[1:0] SECOND[5:0] Access R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bits 31:26 – YEAR[5:0] Year The year value is captured by the TIMESTAMP when a tamper condition occurs. Bits 25:22 – MONTH[3:0] Month The month value is captured by the TIMESTAMP when a tamper condition occurs. Bits 21:17 – DAY[4:0] Day The day value is captured by the TIMESTAMP when a tamper condition occurs. Bits 16:12 – HOUR[4:0] Hour The hour value is captured by the TIMESTAMP when a tamper condition occurs. Bits 11:6 – MINUTE[5:0] Minute The minute value is captured by the TIMESTAMP when a tamper condition occurs. Bits 5:0 – SECOND[5:0] Second The second value is captured by the TIMESTAMP when a tamper condition occurs. SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 473 27.12.16 Tamper ID Name:  TAMPID Offset:  0x68 Reset:  0x00000000 Bit 31 30 29 28 27 26 25 24 TAMPEVT Access R/W Reset 0 Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 TAMPID3 TAMPID2 TAMPID1 TAMPID0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 31 – TAMPEVT Tamper Event Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description 0 A tamper input event has not been detected 1 A tamper input event has been detected Bits 0, 1, 2, 3 – TAMPID Tamper on Channel n Detected Writing a '0' to this bit has no effect. Writing a '1' to this bit clears the tamper detection bit. Value Description 0 A tamper condition has not been detected on Channel n 1 A tamper condition has been detected on Channel n SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 474 27.12.17 Tamper Control B Name:  TAMPCTRLB Offset:  0x6C Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 ALSI3 ALSI2 ALSI1 ALSI0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 0, 1, 2, 3 – ALSI Active Layer Internal Select n Value Description 0 Active layer Protection is monitoring the RTC signal using INn and OUTn tamper pins 1 Active layer Protection is monitoring the RTC signal on the TrustRAM shield SAM L10/L11 Family RTC – Real-Time Counter © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 475 28. DMAC – Direct Memory Access Controller 28.1 Overview The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to all peripherals, the DMAC can handle automatic transfer of data between communication modules. The DMA part of the DMAC has several DMA channels which all can receive different types of transfer triggers to generate transfer requests from the DMA channels to the arbiter, see also the Block Diagram. The arbiter will grant one DMA channel at a time to act as the active channel. When an active channel has been granted, the fetch engine of the DMAC will fetch a transfer descriptor from the SRAM and store it in the internal memory of the active channel, which will execute the data transmission. An ongoing data transfer of an active channel can be interrupted by a higher prioritized DMA channel. The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM, and grant the higher prioritized channel to start transfer as the new active channel. Once a DMA channel is done with its transfer, interrupts and events can be generated optionally. The DMAC has four bus interfaces: • The data transfer bus is used for performing the actual DMA transfer. • The AHB/APB Bridge bus is used when writing and reading the I/O registers of the DMAC. • The descriptor fetch bus is used by the fetch engine to fetch transfer descriptors before data transfer can be started or continued. • The write-back bus is used to write the transfer descriptor back to SRAM. All buses are AHB master interfaces but the AHB/APB Bridge bus, which is an APB slave interface. The CRC engine can be used by software to detect an accidental error in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the incorrect data. 28.2 Features • Data transfer from: – Peripheral to peripheral – Peripheral to memory – Memory to peripheral – Memory to memory • Transfer trigger sources – Software – Events from Event System – Dedicated requests from peripherals • SRAM based transfer descriptors – Single transfer using one descriptor – Multi-buffer or circular buffer modes by linking multiple descriptors SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 476 • Up to 8 channels – Enable 8 independent transfers – Automatic descriptor fetch for each channel – Suspend/resume operation support for each channel • Flexible arbitration scheme – 4 configurable priority levels for each channel – Fixed or round-robin priority scheme within each priority level • From 1 to 256KB data transfer in a single block transfer • Multiple addressing modes – Static – Configurable increment scheme • Optional interrupt generation – On block transfer complete – On error detection – On channel suspend • 4 event inputs – One event input for each of the 4 least significant DMA channels – Can be selected to trigger normal transfers, periodic transfers or conditional transfers – Can be selected to suspend or resume channel operation • 4 event outputs – One output event for each of the 4 least significant DMA channels – Selectable generation on AHB, block, or transaction transfer complete • Error management supported by write-back function – Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer • CRC polynomial software selectable to – CRC-16 (CRC-CCITT) – CRC-32 (IEEE® 802.3) SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 477 28.3 Block Diagram Figure 28-1. DMAC Block Diagram HIGH SPEED BUS MATRIX AHB/APB Bridge CPU SRAM S S M M Events Channel 0 Channel 1 Channel n Arbiter DMA Channels MASTER Active Channel CRC Engine n Fetch Engine Interrupt / Events DMAC Interrupts Transfer Triggers n Data Transfer Write-back Descriptor Fetch 28.4 Signal Description Not applicable. 28.5 Product Dependencies In order to use this peripheral, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines Not applicable. 28.5.2 Power Management The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations in the system without exiting sleep modes. On hardware or software reset, all registers are set to their reset value. Related Links 22. PM – Power Manager 28.5.3 Clocks The DMAC bus clock (CLK_DMAC_APB) must be configured and enabled in the Main Clock module before using the DMAC. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 478 This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by a prescaler and may run even when the module clock is turned off. Related Links 19.6.2.6 Peripheral Clock Masking 28.5.4 DMA Not applicable. 28.5.5 Interrupts The interrupt request line is connected to the interrupt controller. Using the DMAC interrupt requires the interrupt controller to be configured first. 28.5.6 Events The events are connected to the event system. Related Links 33. EVSYS – Event System 28.5.7 Debug Operation When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue operation during debugging. Refer to 28.8.6 DBGCTRL for details. 28.5.8 Register Access Protection All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers: • Interrupt Pending register (INTPEND) • Channel ID register (CHID) • Channel Interrupt Flag Status and Clear register (CHINTFLAG) Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description. PAC write-protection does not apply to accesses through an external debugger. Related Links 15. PAC - Peripheral Access Controller 28.5.9 SAM L11 TrustZone Specific Register Access Protection On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. 28.5.10 Analog Connections Not applicable. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 479 28.6 Functional Description 28.6.1 Principle of Operation The DMAC consists of a DMA module and a CRC module. 28.6.1.1 DMA The DMAC can transfer data between memories and peripherals without interaction from the CPU. The data transferred by the DMAC are called transactions, and these transactions can be split into smaller data transfers. The following figure shows the relationship between the different transfer sizes: Figure 28-2. DMA Transfer Sizes DMA transaction Block transfer Link Enabled Burst transfer Link Enabled Link Enabled Beat transfer • Beat transfer: The size of one data transfer bus access, and the size is selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) • Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k beats. A block transfer can be interrupted. • Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second and so forth, as shown in the figure above. A DMA transaction is the complete transfer of all blocks within a linked list. A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For further details on the transfer descriptor refer to 28.6.2.3 Transfer Descriptors. The figure above shows several block transfers linked together, which are called linked descriptors. For further information about linked descriptors, refer to 28.6.3.1 Linked Descriptors. A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to be either a software trigger, an event trigger, or one of the dedicated peripheral triggers. The transfer trigger will result in a DMA transfer request from the specific channel to the arbiter. If there are several DMA channels with pending transfer requests, the arbiter chooses which channel is granted access to become the active channel. The DMA channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. A current transaction can be interrupted by a higher prioritized channel, but will resume the block transfer when the according DMA channel is granted access as the active channel again. For each beat transfer, an optional output event can be generated. For each block transfer, optional interrupts and an optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA channel will either be suspended or disabled. 28.6.1.2 CRC The internal CRC engine supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It can be used on a selectable DMA channel, or on the I/O interface. Refer to 28.6.3.7 CRC Operation for details. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 480 28.6.2 Basic Operation 28.6.2.1 Initialization The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled (CTRL.DMAENABLE=0): • Descriptor Base Memory Address register (BASEADDR) • Write-Back Memory Base Address register (WRBADDR) The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are disabled (CTRL.DMAENABLE=0 and CTRL.CRCENABLE=0): • Software Reset bit in Control register (CTRL.SWRST) The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled (CHCTRLA.ENABLE=0): • Channel Control B (CHCTRLB) register, except the Command bit (CHCTRLB.CMD) and the Channel Arbitration Level bit (CHCTRLB.LVL) The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA channel is disabled: • Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST) The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled (CTRL.CRCENABLE=0): • CRC Control register (CRCCTRL) • CRC Checksum register (CRCCHKSUM) Enable-protection is denoted by the "Enable-Protected" property in the register description. Before the DMAC is enabled it must be configured, as outlined by the following steps: • The SRAM address of where the descriptor memory section is located must be written to the Description Base Address (BASEADDR) register • The SRAM address of where the write-back section should be located must be written to the WriteBack Memory Base Address (WRBADDR) register • Priority level x of the arbiter can be enabled by setting the Priority Level x Enable bit in the Control register (CTRL.LVLENx=1) Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, as outlined by the following steps: • DMA channel configurations – The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register – Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT) – Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register (CHCTRLB.TRIGSRC) • Transfer Descriptor – The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the Block Transfer Control register (BTCTRL.BEATSIZE) SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 481 – The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control register (BTCTRL.VALID) – Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT) register – Source address for the block transfer must be selected by writing the Block Transfer Source Address (SRCADDR) register – Destination address for the block transfer must be selected by writing the Block Transfer Destination Address (DSTADDR) register If CRC calculation is needed, the CRC engine must be configured before it is enabled, as outlined by the following steps: • The CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register (CRCCTRL.CRCSRC) • The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control register (CRCCTRL.CRCPOLY) • If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC Control register (CRCCTRL.CRCBEATSIZE) 28.6.2.2 Enabling, Disabling, and Resetting The DMAC is enabled by writing the DMA Enable bit in the Control register (CTRL.DMAENABLE) to '1'. The DMAC is disabled by writing a '0' to CTRL.DMAENABLE. A DMA channel is enabled by writing the Enable bit in the Channel Control A register (CHCTRLA.ENABLE) to '1', after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA channel is disabled by writing a '0' to CHCTRLA.ENABLE. The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is disabled by writing a '0' to CTRL.CRCENABLE. The DMAC is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST) while the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial state. A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register (CHCTRLA.SWRST), after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). The channel registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the reset to take effect. 28.6.2.3 Transfer Descriptors Together with the channel configurations the transfer descriptors decides how a block transfer should be executed. Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first transfer descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of a transaction. All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section Base Address (BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tell the DMAC where to find the descriptor memory section and the write-back memory section. The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As BASEADDR points only to the first transfer descriptor of channel 0 (see figure below), all first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their channel number. For further details on linked descriptors, refer to 28.6.3.1 Linked Descriptors. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 482 The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number. The figure below shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to 28.6.3.1 Linked Descriptors. Figure 28-3. Memory Sections Channel 0 – Descriptor n-1 Channel 0 – Last Descriptor DESCADDR DESCADDR Device Memory Space BASEADDR Channel 0 – First Descriptor Channel 1 – First Descriptor Channel 2 – First Descriptor Channel n – First Descriptor Descriptor Section WRBADDR Channel 0 Ongoing Descriptor Channel 1 Ongoing Descriptor Channel 2 Ongoing Descriptor Channel n Ongoing Descriptor Write-Back Section Undefined Undefined Undefined Undefined Undefined SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL DESCADDR BTCNT SRCADDR DSTADDR BTCTRL 0x00000000 BTCNT The size of the descriptor and write-back memory sections is dependent on the number of the most significant enabled DMA channel m, as shown below: 1 ݉ + ڄ 128bits݁ = ݖ݅ܵ For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are required. The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory and write-back memory in the same section is that it requires less SRAM. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 483 28.6.2.4 Arbitration If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers (PENDCH.PENDCHx) will be set. Depending on the arbitration scheme, the arbiter will choose which DMA channel will be the next active channel. The active channel is the DMA channel being granted access to perform its next transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding bit PENDCH.PENDCHx will be cleared. See also the following figure. If the upcoming transfer is the first for the transfer request, the corresponding Busy Channel x bit in the Busy Channels register will be set (BUSYCH.BUSYCHx=1), and it will remain '1' for the subsequent granted transfers. When the channel has performed its granted transfer(s) it will be either fed into the queue of channels with pending transfers, set to be waiting for a new transfer trigger, suspended, or disabled. This depends on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending transfers, the corresponding BUSYCH.BUSYCHx will remain '1'. If the DMA channel is set to wait for a new transfer trigger, suspended, or disabled, the corresponding BUSYCH.BUSYCHx will be cleared. If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to the queue of pending channels again. If a DMA channel gets disabled (CHCTRLA.ENABLE=0) while it has a pending transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be cleared. Figure 28-4. Arbiter Overview Channel 0 Channel N Active Channel Priority decoder Active.LVLEXx PRICTRLx.LVLPRI Arbiter CTRL.LVLENx Burst Done Transfer Request Channel Number Level Enable Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Channel Burst Done Channel Priority Level Channel Pending Channel Suspend Priority Levels When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the Active Channel and Levels register (ACTIVE.LVLEXx). Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the Channel Arbitration Level bit group in the Channel Control B register (CHCTRLB.LVL). As long as all priority levels are enabled, a channel with a higher priority level number will have priority over a channel with a lower priority level number. Each priority level x is enabled by setting the corresponding Priority Level x Enable bit in the Control register (CTRL.LVLENx=1). SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 484 Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically: Static Arbitration within a priority level is selected by writing a '0' to the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 register (PRICTRL0.RRLVLENx). When static arbitration is selected, the arbiter will prioritize a low channel number over a high channel number as shown in the figure below. When using the static arbitration there is a risk of high channel numbers never being granted access as the active channel. This can be avoided using a dynamic arbitration scheme. Figure 28-5. Static Priority Scheduling Highest Channel Lowest Channel Highest Priority Channel N Lowest Priority Channel 0 Channel x+1 Channel x . . . . . . Dynamic Arbitration within a priority level is selected by writing a '1' to PRICTRL0.RRLVLENx. The dynamic arbitration scheme in the DMAC is round-robin. With the round-robin scheme, the channel number of the last channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel within the same priority level, as shown in Figure 28-6. The channel number of the last channel being granted access as the active channel is stored in the Level x Channel Priority Number bit group in the Priority Control 0 register (PRICTRL0.LVLPRIx) for the corresponding priority level. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 485 Figure 28-6. Dynamic (Round-Robin) Priority Scheduling Channel N Channel N Channel 0 Channel x Channel x+1 Channel x last acknowledge request Channel (x+1) last acknowledge request Channel 0 Channel x Channel x+1 Channel x+2 Lowest Priority Highest Priority Highest Priority Lowest Priority . . . . . . 28.6.2.5 Data Transmission Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding transfer descriptor has to be initialized, and the arbiter has to grant the DMA channel access as the active channel. Once the arbiter has granted a DMA channel access as the active channel (refer to DMA Block Diagram section) the transfer descriptor for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active channel. For a new block transfer, the transfer descriptor will be fetched from the descriptor memory section (BASEADDR); For an ongoing block transfer, the descriptor will be fetched from the write-back memory section (WRBADDR). By using the data transfer bus, the DMAC will read the data from the current source address and write it to the current destination address. For further details on how the current source and destination addresses are calculated, refer to the section on Addressing. The arbitration procedure is performed after each transfer. If the current DMA channel is granted access again, the block transfer counter (BTCNT) of the internal transfer descriptor will be decremented by the number of beats in a transfer, the optional output event Beat will be generated if configured and enabled, and the active channel will perform a new transfer. If a different DMA channel than the current active channel is granted access, the block transfer counter value will be written to the write-back section before the transfer descriptor of the newly granted DMA channel is fetched into the internal memory of the active channel. When a block transfer has come to its end (BTCNT is zero), the Valid bit in the Block Transfer Control register will be cleared (BTCTRL.VALID=0) before the entire transfer descriptor is written to the writeback memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the optional output event Block, will be generated if configured and enabled. After the last block transfer in a transaction, the Next Descriptor Address register (DESCADDR) will hold the value 0x00000000, and the DMA channel will either be suspended or disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the next active channel. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 486 28.6.2.6 Transfer Triggers and Actions A DMA transfer through a DMA channel can be started only when a DMA transfer request is detected, and the DMA channel has been granted access to the DMA. A transfer request can be triggered from software, from a peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel Control B (CHCTRLB.TRIGSRC). The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT). By default, a trigger generates a request for a block transfer operation. If a single descriptor is defined for a channel, the channel is automatically disabled when a block transfer has been completed. If a list of linked descriptors is defined for a channel, the channel is automatically disabled when the last descriptor in the list is executed. If the list still has descriptors to execute, the channel will be waiting for the next block transfer trigger. When enabled again, the channel will wait for the next block transfer trigger. The trigger actions can also be configured to generate a request for a beat transfer (CHCTRLB.TRIGACT=0x2) or transaction transfer (CHCTRLB.TRIGACT=0x3) instead of a block transfer (CHCTRLB.TRIGACT=0x0). Figure 28-7 shows an example where triggers are used with two linked block descriptors. Figure 28-7. Trigger Action and Transfers CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer CHENn Trigger PENDCHn BUSYCHn Data Transfer Block Transfer Block Transfer Block Transfer Block Transfer Block Transfer Block Transfer Trigger Lost Trigger Lost Trigger Lost Transaction Trigger Action Block Trigger Action Beat Trigger Action BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT BEAT If the trigger source generates a transfer request for a channel during an ongoing transfer, the new transfer request will be kept pending (CHSTATUS.PEND=1), and the new transfer can start after the SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 487 ongoing one is done. Only one pending transfer can be kept per channel. If the trigger source generates more transfer requests while one is already pending, the additional ones will be lost. All channels pending status flags are also available in the Pending Channels register (PENDCH). When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register (CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channel busy status flags are also available in the Busy Channels register (BUSYCH) in DMAC. 28.6.2.7 Addressing Each block transfer needs to have both a source address and a destination address defined. The source address is set by writing the Transfer Source Address (SRCADDR) register, the destination address is set by writing the Transfer Destination Address (SRCADDR) register. The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or both. Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.SRCINC=1). The step size of the incrementation is configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control register (BTCTRL.STEPSEL=1) and writing the desired step size in the Address Increment Step Size bit group in the Block Transfer Control register (BTCTRL.STEPSIZE). If BTCTRL.STEPSEL=0, the step size for the source incrementation will be the size of one beat. When source address incrementation is configured (BTCTRL.SRCINC=1), SRCADDR is calculated as follows: If BTCTRL.STEPSEL=1: 2 ڄ 1 + ܧܼܫܵܶܣܧܤ ڄ ܶܰܥܶܤ + ܴܶܣܶܵSRCADDR = SRCADDR STEPSIZE If BTCTRL.STEPSEL=0: 1 + ܧܼܫܵܶܣܧܤ ڄ ܶܰܥܶܤ + ܴܶܣܶܵSRCADDR = SRCADDR • SRCADDRSTART is the source address of the first beat transfer in the block transfer • BTCNT is the initial number of beats remaining in the block transfer • BEATSIZE is the configured number of bytes in a beat • STEPSIZE is the configured number of beats for each incrementation The following figure shows an example where DMA channel 0 is configured to increment the source address by one beat after each beat transfer (BTCTRL.SRCINC=1), and DMA channel 1 is configured to increment the source address by two beats (BTCTRL.SRCINC=1, BTCTRL.STEPSEL=1, and BTCTRL.STEPSIZE=0x1). As the destination address for both channels are peripherals, destination incrementation is disabled (BTCTRL.DSTINC=0). SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 488 Figure 28-8. Source Address Increment SRC Data Buffer a b c d e f Incrementation for the destination address of a block transfer is enabled by setting the Destination Address Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC=1). The step size of the incrementation is configurable by clearing BTCTRL.STEPSEL=0 and writing BTCTRL.STEPSIZE to the desired step size. If BTCTRL.STEPSEL=1, the step size for the destination incrementation will be the size of one beat. When the destination address incrementation is configured (BTCTRL.DSTINC=1), DSTADDR must be set and calculated as follows: zero is STEPSEL.BTCTRL where ܧܼܫܵܲܧܶܵ2 • 1 + ܧܼܫܵܶܣܧܤ • ܶܰܥܶܤ + ܴܶܣܴܶܵܦܦܣܶܵܦ = ܴܦܦܣܶܵܦ one is STEPSEL.BTCTRL where 1 + ܧܼܫܵܶܣܧܤ • ܶܰܥܶܤ + ܴܶܣܴܶܵܦܦܣܶܵܦ = ܴܦܦܣܶܵܦ • DSTADDRSTART is the destination address of the first beat transfer in the block transfer • BTCNT is the initial number of beats remaining in the block transfer • BEATSIZE is the configured number of bytes in a beat • STEPSIZE is the configured number of beats for each incrementation The followiong figure shows an example where DMA channel 0 is configured to increment destination address by one beat (BTCTRL.DSTINC=1) and DMA channel 1 is configured to increment destination address by two beats (BTCTRL.DSTINC=1, BTCTRL.STEPSEL=0, and BTCTRL.STEPSIZE=0x1). As the source address for both channels are peripherals, source incrementation is disabled (BTCTRL.SRCINC=0). SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 489 Figure 28-9. Destination Address Increment DST Data Buffer a b c d 28.6.2.8 Error Handling If a bus error is received from an AHB slave during a DMA data transfer, the corresponding active channel is disabled and the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.TERR) is set. If enabled, the optional transfer error interrupt is generated. The transfer counter will not be decremented and its current value is written-back in the writeback memory section before the channel is disabled. When the DMAC fetches an invalid descriptor (BTCTRL.VALID=0) or when the channel is resumed and the DMA fetches the next descriptor with null address (DESCADDR=0x00000000), the corresponding channel operation is suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register (CHINTFLAG.SUSP) is set, and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If enabled, the optional suspend interrupt is generated. 28.6.3 Additional Features 28.6.3.1 Linked Descriptors A transaction can consist of either a single block transfer or of several block transfers. When a transaction consists of several block transfers it is done with the help of linked descriptors. Figure 28-3 illustrates how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC fetches the next transfer descriptor, which is pointed to by the value stored in the Next Descriptor Address (DESCADDR) register of the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000, the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to section 28.6.2.5 Data Transmission. 28.6.3.1.1 Adding Descriptor to the End of a List To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000 indicating that it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the address of the newly created descriptor. 28.6.3.1.2 Modifying a Descriptor in a List In order to add descriptors to a linked list, the following actions must be performed: 1. Enable the Suspend interrupt for the DMA channel. 2. Enable the DMA channel. 3. Reserve memory space in SRAM to configure a new descriptor. 4. Configure the new descriptor: SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 490 – Set the next descriptor address (DESCADDR) – Set the destination address (DSTADDR) – Set the source address (SRCADDR) – Configure the block transfer control (BTCTRL) including • Optionally enable the Suspend block action • Set the descriptor VALID bit 5. Clear the VALID bit for the existing list and for the descriptor which has to be updated. 6. Read DESCADDR from the Write-Back memory. – If the DMA has not already fetched the descriptor which requires changes (i.e., DESCADDR is wrong): • Update the DESCADDR location of the descriptor from the List • Optionally clear the Suspend block action • Set the descriptor VALID bit to '1' • Optionally enable the Resume software command – If the DMA is executing the same descriptor as the one which requires changes: • Set the Channel Suspend software command and wait for the Suspend interrupt • Update the next descriptor address (DESCRADDR) in the write-back memory • Clear the interrupt sources and set the Resume software command • Update the DESCADDR location of the descriptor from the List • Optionally clear the Suspend block action • Set the descriptor VALID bit to '1' 7. Go to step 4 if needed. 28.6.3.1.3 Adding a Descriptor Between Existing Descriptors To insert a new descriptor 'C' between two existing descriptors ('A' and 'B'), the descriptor currently executed by the DMA must be identified. 1. If DMA is executing descriptor B, descriptor C cannot be inserted. 2. If DMA has not started to execute descriptor A, follow the steps: 2.1. Set the descriptor A VALID bit to '0'. 2.2. Set the DESCADDR value of descriptor A to point to descriptor C instead of descriptor B. 2.3. Set the DESCADDR value of descriptor C to point to descriptor B. 2.4. Set the descriptor A VALID bit to '1'. 3. If DMA is executing descriptor A: 3.1. Apply the software suspend command to the channel and 3.2. Perform steps 2.1 through 2.4. 3.3. Apply the software resume command to the channel. 28.6.3.2 Channel Suspend The channel operation can be suspended at any time by software by writing a '1' to the Suspend command in the Command bit field of Channel Control B register (CHCTRLB.CMD). After the ongoing burst transfer is completed, the channel operation is suspended and the suspend command is automatically cleared. When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set (CHINTFLAG.SUSP=1) and the optional suspend interrupt is generated. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 491 By configuring the block action to suspend by writing Block Action bit group in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will be kept enabled and will be able to receive transfer triggers, but it will be removed from the arbitration scheme. If an invalid transfer descriptor (BTCTRL.VALID=0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status register(CHASTATUS.FERR) will be set. Note:  Only enabled DMA channels can be suspended. If a channel is disabled when it is attempted to be suspended, the internal suspend command will be ignored. For more details on transfer descriptors, refer to section 28.6.2.3 Transfer Descriptors. 28.6.3.3 Channel Resume and Next Suspend Skip A channel operation can be resumed by software by setting the Resume command in the Command bit field of the Channel Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it previously stopped when the Resume command is detected. When the Resume command is issued before the channel is suspended, the next suspend action is skipped and the channel continues the normal operation. Figure 28-10. Channel Suspend/Resume Operation CHENn Memory Descriptor Transfer Resume Command Descriptor 0 (suspend disabled) Fetch Block Transfer 0 Descriptor 1 (suspend enabled) Block Transfer 1 Suspend skipped Descriptor 2 (suspend enabled) Block Transfer 2 Channel suspended Descriptor 3 (last) Block Transfer 3 28.6.3.4 Event Input Actions The event input actions are available only on the four least significant DMA channels. For details on channels with event input support, refer to the in the Event system documentation. Before using event input actions, the event controller must be configured first according to the following table, and the Channel Event Input Enable bit in the Channel Control B register (CHCTRLB.EVIE) must be written to '1'. Refer also to 28.6.6 Events. Table 28-1. Event Input Action Action CHCTRLB.EVACT CHCTRLB.TRGSRC None NOACT - Normal Transfer TRIG DISABLE Conditional Transfer on Strobe TRIG any peripheral Conditional Transfer CTRIG Conditional Block Transfer CBLOCK Channel Suspend SUSPEND Channel Resume RESUME Skip Next Block Suspend SSKIP SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 492 Normal Transfer The event input is used to trigger a beat or burst transfer on peripherals. The event is acknowledged as soon as the event is received. When received, both the Channel Pending status bit in the Channel Status register (CHSTATUS.PEND) and the corresponding Channel n bit in the Pending Channels register (28.8.13 PENDCH.PENDCHn) are set. If the event is received while the channel is pending, the event trigger is lost. The figure below shows an example where beat transfers are enabled by internal events. Figure 28-11. Beat Event Trigger Action CHENn Peripheral Trigger Event PENDCHn BUSYCHn Data Transfer Trigger Lost Block Transfer BEAT BEAT BEAT BEAT BEAT BEAT Block Transfer Conditional Transfer on Strobe The event input is used to trigger a transfer on peripherals with pending transfer requests. This event action is intended to be used with peripheral triggers, e.g. for timed communication protocols or periodic transfers between peripherals: only when the peripheral trigger coincides with the occurrence of a (possibly cyclic) event the transfer is issued. The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the previous trigger action is completed (i.e. the channel is not pending) and when an active event is received. If the peripheral trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When both event and peripheral transfer trigger are active, both CHSTATUS.PEND and 28.8.13 PENDCH.PENDCHn are set. A software trigger will now trigger a transfer. The figure below shows an example where the peripheral beat transfer is started by a conditional strobe event action. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 493 Figure 28-12. Periodic Event with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Trigger Lost Trigger Lost Block Transfer BEAT Conditional Transfer The event input is used to trigger a conditional transfer on peripherals with pending transfer requests. As example, this type of event can be used for peripheral-to-peripheral transfers, where one peripheral is the source of event and the second peripheral is the source of the trigger. Each peripheral trigger is stored internally when the event is received. When the peripheral trigger is stored internally, the Channel Pending status bit is set (CHSTATUS.PEND), the respective Pending Channel n Bit in the Pending Channels register is set (28.8.13 PENDCH.PENDCHn), and the event is acknowledged. A software trigger will now trigger a transfer. The figure below shows an example where conditional event is enabled with peripheral beat trigger requests. Figure 28-13. Conditional Event with Beat Peripheral Triggers Event Peripheral Trigger PENDCHn Data Transfer Block Transfer BEAT BEAT Conditional Block Transfer The event input is used to trigger a conditional block transfer on peripherals. Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the block transfer is completed. A software trigger will trigger a transfer. The figure below shows an example where conditional event block transfer is started with peripheral beat trigger requests. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 494 Figure 28-14. Conditional Block Transfer with Beat Peripheral Triggers BEAT BEAT Block Transfer BEAT BEAT Block Transfer Data Transfer Peripheral Trigger Event PENDCHn Channel Suspend The event input is used to suspend an ongoing channel operation. The event is acknowledged when the current AHB access is completed. For further details on Channel Suspend, refer to 28.6.3.2 Channel Suspend. Channel Resume The event input is used to resume a suspended channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag (CHINTFLAG.SUSP) is cleared. For further details refer to 28.6.3.2 Channel Suspend. Skip Next Block Suspend This event can be used to skip the next block suspend action. If the channel is suspended before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is completed, the channel continues the operation (not suspended) and the event is acknowledged. 28.6.3.5 Event Output Selection Event output selection is available only for the four least significant DMA channels. The pulse width of an event output from a channel is one AHB clock cycle. The output of channel events is enabled by writing a '1' to the Channel Event Output Enable bit in the Control B register (CHCTRLB.EVOE). The event output cause is selected by writing to the Event Output Selection bits in the Block Transfer Control register (BTCTRL.EVOSEL). It is possible to generate events after each block transfer (BTCTRL.EVOSEL=0x1) or beat transfer (BTCTRL.EVOSEL=0x3). To enable an event being generated when a transaction is complete, the block event selection must be set in the last transfer descriptor only. The figure Figure 28-15 shows an example where the event output generation is enabled in the first block transfer, and disabled in the second block. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 495 Figure 28-15. Event Output Generation Beat Event Output Data Transfer Event Output Data Transfer Event Output Block Transfer BEAT Block Event Output Block Transfer Block Transfer Block Transfer BEAT BEAT BEAT BEAT BEAT BEAT BEAT 28.6.3.6 Aborting Transfers Transfers on any channel can be aborted gracefully by software by disabling the corresponding DMA channel. It is also possible to abort all ongoing or pending transfers by disabling the DMAC. When a DMA channel disable request or DMAC disable request is detected: • Ongoing transfers of the active channel will be disabled when the ongoing beat transfer is completed and the write-back memory section is updated. This prevents transfer corruption before the channel is disabled. • All other enabled channels will be disabled in the next clock cycle. The corresponding Channel Enable bit in the Channel Control A register is cleared (CHCTRLA.ENABLE=0) when the channel is disabled. The corresponding DMAC Enable bit in the Control register is cleared (CTRL.DMAENABLE=0) when the entire DMAC module is disabled. 28.6.3.7 CRC Operation A cyclic redundancy check (CRC) is an error detection technique used to find errors in data. It is commonly used to determine whether the data during a transmission, or data present in data and program memories has been corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the data is received, the device or application repeats the calculation: If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. The CRC engine in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). Typically, applying CRC-n (CRC-16 or CRC-32) to a data block of arbitrary length will detect any single alteration that is ≤n bits in length, and will detect the fraction 1-2-n of all longer error bursts. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 496 • CRC-16: – Polynomial: x16+ x12+ x5+ 1 – Hex value: 0x1021 • CRC-32: – Polynomial: x32+x26+ x23+ x22+x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x + 1 – Hex value: 0x04C11DB7 The data source for the CRC engine can either be one of the DMA channels or the APB bus interface, and must be selected by writing to the CRC Input Source bits in the CRC Control register (CRCCTRL.CRCSRC). The CRC engine then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented, as shown in Figure 28-16. The CRC polynomial is selected by writing to the CRC Polynomial Type bit in the CRC Control register (CRCCTRL.CRCPOLY), the default is CRC-16. The CRC engine operates on byte only. When the DMA is used as data source for the CRC engine, the DMA channel beat size setting will be used. When used with APB bus interface, the application must select the CRC Beat Size bit field of CRC Control register (CRCCTRL.CRCBEATSIZE). 8-, 16-, or 32-bit bus transfer access type is supported. The corresponding number of bytes will be written in the CRCDATAIN register and the CRC engine will operate on the input data in a byte by byte manner. Figure 28-16. CRC Generator Block Diagram 8 16 8 32 Checksum read crc32 CRCCTRL CHECKSUM bit-reverse + complement CRC-16 CRC-32 DMAC Channels CRCDATAIN SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 497 CRC on DMA data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC engine will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can also be generated on SRAM, Flash, or I/O memory by passing these data through a DMA channel. If the latter is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC engine. CRC using the I/O interface Before using the CRC engine with the I/O interface, the application must set the CRC Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected. CRC can be performed on any data by loading them into the CRC engine using the CPU and writing the data to the CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC engine takes four cycles to calculate the CRC. The CRC complete is signaled by a set CRCBUSY bit in the CRCSTATUS register. New data can be written only when CRCBUSY flag is not set. 28.6.4 DMA Operation Not applicable. 28.6.5 Interrupts The DMAC channels have the following interrupt sources: • Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to 28.6.2.5 Data Transmission for details. • Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor has been fetched. Refer to 28.6.2.8 Error Handling for details. • Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to 28.6.3.2 Channel Suspend and 28.6.2.5 Data Transmission for details. Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by setting the corresponding bit in the Channel Interrupt Enable Set register (CHINTENSET=1), and disabled by setting the corresponding bit in the Channel Interrupt Enable Clear register (CHINTENCLR=1). An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system level to generate one combined interrupt request to the NVIC. The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which provides the lowest channel number with pending interrupt and the respective interrupt flags. Note:  Interrupts must be globally enabled for interrupt requests to be generated. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 498 28.6.6 Events The DMAC can generate the following output events: • Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer within a block transfer for a given channel has been completed. Refer to Event Output Selection for details. Setting the Channel Control B Event Output Enable bit (CHCTRLB.EVOE=1) enables the corresponding output event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL). Clearing CHCTRLB.EVOE=0 disables the corresponding output event. The DMAC can take the following actions on an input event: • Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled • Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled • Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled • Channel Suspend Operation (SUSPEND): suspend a channel operation • Channel Resume Operation (RESUME): resume a suspended channel operation • Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition • Increase Priority (INCPRI): increase channel priority Setting the Channel Control B Event Input Enable bit (CHCTRLB.EVIE=1) enables the corresponding action on input event. Clearing this bit disables the corresponding action on input event. Note that several actions can be enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of the incoming events. For further details on event input actions, refer to Event Input Actions. Note:  Event input and outputs are not available for every channel. Refer to 28.2 Features for more information. Related Links 33. EVSYS – Event System 28.6.7 Sleep Mode Operation Each DMA channel can be configured to operate in any sleep mode. To be able to run in standby, the RUNSTDBY bit in Channel Control A register (CHCTRLA.RUNSTDBY) must be written to '1'. The DMAC can wake up the device using interrupts from any sleep mode or perform actions through the Event System. For channels with CHCTRLA.RUNSTDBY = 0, it is up to software to stop DMA transfers on these channels and wait for completion before going to standby mode using the following sequence: 1. Suspend the DMAC channels for which CHCTRLA.RUNSTDBY = 0. 2. Check the SYNCBUSY bits of registers accessed by the DMAC channels being suspended. 3. Go to sleep. 4. When the device wakes up, resume the suspended channels. 28.6.8 Synchronization Not applicable. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 499 28.7 Register Summary Offset Name Bit Pos. 0x00 CTRL 7:0 CRCENABLE DMAENABLE SWRST 15:8 LVLENx3 LVLENx2 LVLENx1 LVLENx0 0x02 CRCCTRL 7:0 CRCPOLY[1:0] CRCBEATSIZE[1:0] 15:8 CRCSRC[5:0] 0x04 CRCDATAIN 7:0 CRCDATAIN[7:0] 15:8 CRCDATAIN[15:8] 23:16 CRCDATAIN[23:16] 31:24 CRCDATAIN[31:24] 0x08 CRCCHKSUM 7:0 CRCCHKSUM[7:0] 15:8 CRCCHKSUM[15:8] 23:16 CRCCHKSUM[23:16] 31:24 CRCCHKSUM[31:24] 0x0C CRCSTATUS 7:0 CRCZERO CRCBUSY 0x0D DBGCTRL 7:0 DBGRUN 0x0E QOSCTRL 7:0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] 0x0F Reserved 0x10 SWTRIGCTRL 7:0 SWTRIGn[6:0] 15:8 23:16 31:24 0x14 PRICTRL0 7:0 RRLVLEN0 LVLPRI0[3:0] 15:8 RRLVLEN1 LVLPRI1[3:0] 23:16 RRLVLEN2 LVLPRI2[3:0] 31:24 RRLVLEN3 LVLPRI3[3:0] 0x18 ... 0x1F Reserved 0x20 INTPEND 7:0 ID[3:0] 15:8 PEND BUSY FERR SUSP TCMPL TERR 0x22 ... 0x23 Reserved 0x24 INTSTATUS 7:0 CHINTn[6:0] 15:8 23:16 31:24 0x28 BUSYCH 7:0 BUSYCHn[6:0] 15:8 23:16 31:24 0x2C PENDCH 7:0 PENDCH7 PENDCH6 PENDCH5 PENDCH4 PENDCH3 PENDCH2 PENDCH1 PENDCH0 15:8 23:16 SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 500 Offset Name Bit Pos. 31:24 0x30 ACTIVE 7:0 LVLEXx LVLEXx LVLEXx LVLEXx 15:8 ABUSY ID[4:0] 23:16 BTCNT[7:0] 31:24 BTCNT[15:8] 0x34 BASEADDR 7:0 BASEADDR[7:0] 15:8 BASEADDR[13:8] 23:16 31:24 0x38 WRBADDR 7:0 WRBADDR[7:0] 15:8 WRBADDR[13:8] 23:16 31:24 0x3C ... 0x3E Reserved 0x3F CHID 7:0 ID[3:0] 0x40 CHCTRLA 7:0 RUNSTDBY ENABLE SWRST 0x41 ... 0x43 Reserved 0x44 CHCTRLB 7:0 LVL[1:0] EVOE EVIE EVACT[2:0] 15:8 TRIGSRC[4:0] 23:16 TRIGACT[1:0] 31:24 CMD[1:0] 0x48 ... 0x4B Reserved 0x4C CHINTENCLR 7:0 SUSP TCMPL TERR 0x4D CHINTENSET 7:0 SUSP TCMPL TERR 0x4E CHINTFLAG 7:0 SUSP TCMPL TERR 0x4F CHSTATUS 7:0 FERR BUSY PEND 28.8 Register Description Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly. Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC write-protection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer to 28.5.8 Register Access Protection. Some registers are enable-protected, meaning they can only be written when the peripheral is disabled. Enable-protection is denoted by the "Enable-Protected" property in each individual register description. On SAM L11 devices, this peripheral has different access permissions depending on PAC Security Attribution (Secure or Non-Secure): SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 501 • If the peripheral is configured as Non-Secure in the PAC: – Secure access and Non-Secure access are granted • If the peripheral is configured as Secure in the PAC: – Secure access is granted – Non-Secure access is discarded (Write is ignored, read 0x0) and a PAC error is triggered Refer to Peripherals Security Attribution for more information. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 502 28.8.1 Control Name:  CTRL Offset:  0x00 Reset:  0x00X0 Property:  PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 LVLENx3 LVLENx2 LVLENx1 LVLENx0 Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCENABLE DMAENABLE SWRST Access R/W R/W R/W Reset 0 0 0 Bits 8, 9, 10, 11 – LVLENx Priority Level x Enable When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all requests with the corresponding level will be ignored. For details on arbitration schemes, refer to the Arbitration section. These bits are not enable-protected. Value Description 0 Transfer requests for Priority level x will not be handled. 1 Transfer requests for Priority level x will be handled. Bit 2 – CRCENABLE CRC Enable Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared (CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled. Writing a '1' to this bit will enable the CRC calculation. Value Description 0 The CRC calculation is disabled. 1 The CRC calculation is enabled. Bit 1 – DMAENABLE DMA Enable Setting this bit will enable the DMA module. Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst transfer is completed. This bit is not enable-protected. Value Description 0 The peripheral is disabled. 1 The peripheral is enabled. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 503 Bit 0 – SWRST Software Reset Writing a '0' to this bit has no effect. Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access error. Value Description 0 There is no Reset operation ongoing. 1 A Reset operation is ongoing. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 504 28.8.2 CRC Control Name:  CRCCTRL Offset:  0x02 Reset:  0x0000 Property:  PAC Write-Protection, Enable-Protected Bit 15 14 13 12 11 10 9 8 CRCSRC[5:0] Access R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCPOLY[1:0] CRCBEATSIZE[1:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bits 13:8 – CRCSRC[5:0] CRC Input Source These bits select the input source for generating the CRC, as shown in the table below. The selected source is locked until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation complete is generated and signaled from the selected source when used with the DMA channel. Value Name Description 0x00 NOACT No action 0x01 IO I/O interface 0x02-0x 1F - Reserved 0x20 CHN DMA channel 0 0x21 CHN DMA channel 1 0x22 CHN DMA channel 2 0x23 CHN DMA channel 3 0x24 CHN DMA channel 4 0x25 CHN DMA channel 5 0x26 CHN DMA channel 6 0x27 CHN DMA channel 7 0x28 CHN DMA channel 8 0x29 CHN DMA channel 9 0x2A CHN DMA channel 10 0x2B CHN DMA channel 11 0x2C CHN DMA channel 12 0x2D CHN DMA channel 13 0x2E CHN DMA channel 14 0x2F CHN DMA channel 15 0x30 CHN DMA channel 16 0x31 CHN DMA channel 17 0x32 CHN DMA channel 18 SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 505 Value Name Description 0x33 CHN DMA channel 19 0x34 CHN DMA channel 20 0x35 CHN DMA channel 21 0x36 CHN DMA channel 22 0x37 CHN DMA channel 23 0x38 CHN DMA channel 24 0x39 CHN DMA channel 25 0x3A CHN DMA channel 26 0x3B CHN DMA channel 27 0x3C CHN DMA channel 28 0x3D CHN DMA channel 29 0x3E CHN DMA channel 30 0x3F CHN DMA channel 31 Bits 3:2 – CRCPOLY[1:0] CRC Polynomial Type These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as shown in the table below. Value Name Description 0x0 CRC16 CRC-16 (CRC-CCITT) 0x1 CRC32 CRC32 (IEEE 802.3) 0x2-0x3 Reserved Bits 1:0 – CRCBEATSIZE[1:0] CRC Beat Size These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface. Value Name Description 0x0 BYTE 8-bit bus transfer 0x1 HWORD 16-bit bus transfer 0x2 WORD 32-bit bus transfer 0x3 Reserved SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 506 28.8.3 CRC Data Input Name:  CRCDATAIN Offset:  0x04 Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 CRCDATAIN[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCDATAIN[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCDATAIN[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCDATAIN[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCDATAIN[31:0] CRC Data Input These bits store the data for which the CRC checksum is computed. A new CRC Checksum is ready (CRCBEAT+ 1) clock cycles after the CRCDATAIN register is written. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 507 28.8.4 CRC Checksum Name:  CRCCHKSUM Offset:  0x08 Reset:  0x00000000 Property:  PAC Write-Protection, Enable-Protected The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC. The register is reset to zero by default, but it is possible to reset all bits to one by writing the CRCCHKSUM register directly. It is possible to write this register only when the CRC module is disabled. If CRC-32 is selected and the CRC Status Busy flag is cleared (i.e., CRC generation is completed or aborted), the bit reversed (bit 31 is swapped with bit 0, bit 30 with bit 1, etc.) and complemented result will be read from CRCCHKSUM. If CRC-16 is selected or the CRC Status Busy flag is set (i.e., CRC generation is ongoing), CRCCHKSUM will contain the actual content. Bit 31 30 29 28 27 26 25 24 CRCCHKSUM[31:24] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 CRCCHKSUM[23:16] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 CRCCHKSUM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 CRCCHKSUM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bits 31:0 – CRCCHKSUM[31:0] CRC Checksum These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 508 28.8.5 CRC Status Name:  CRCSTATUS Offset:  0x0C Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 CRCZERO CRCBUSY Access R R/W Reset 0 0 Bit 1 – CRCZERO CRC Zero This bit is cleared when a new CRC source is selected. This bit is set when the CRC generation is complete and the CRC Checksum is zero. When running CRC-32 and appending the checksum at the end of the packet (as little endian), the final checksum should be 0x2144df1c, and not zero. However, if the checksum is complemented before it is appended (as little endian) to the data, the final result in the checksum register will be zero. See the description of CRCCHKSUM to read out different versions of the checksum. Bit 0 – CRCBUSY CRC Module Busy This flag is cleared by writing a one to it when used with I/O interface. When used with a DMA channel, the bit is set when the corresponding DMA channel is enabled, and cleared when the corresponding DMA channel is disabled. This register bit cannot be cleared by the application when the CRC is used with a DMA channel. This bit is set when a source configuration is selected and as long as the source is using the CRC module. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 509 28.8.6 Debug Control Name:  DBGCTRL Offset:  0x0D Reset:  0x00 Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DBGRUN Access R/W Reset 0 Bit 0 – DBGRUN Debug Run This bit is not reset by a software reset. This bit controls the functionality when the CPU is halted by an external debugger. Value Description 0 The DMAC is halted when the CPU is halted by an external debugger. 1 The DMAC continues normal operation when the CPU is halted by an external debugger. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 510 28.8.7 Quality of Service Control Name:  QOSCTRL Offset:  0x0E Reset:  0x2A Property:  PAC Write-Protection Bit 7 6 5 4 3 2 1 0 DQOS[1:0] FQOS[1:0] WRBQOS[1:0] Access R/W R/W R/W R/W R/W R/W Reset 1 0 1 0 1 0 Bits 5:4 – DQOS[1:0] Data Transfer Quality of Service These bits define the memory priority access during the data transfer operation. DQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 3:2 – FQOS[1:0] Fetch Quality of Service These bits define the memory priority access during the fetch operation. FQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency Bits 1:0 – WRBQOS[1:0] Write-Back Quality of Service These bits define the memory priority access during the write-back operation. WRBQOS[1:0] Name Description 0x0 DISABLE Background (no sensitive operation) 0x1 LOW Sensitive Bandwidth 0x2 MEDIUM Sensitive Latency 0x3 HIGH Critical Latency SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 511 28.8.8 Software Trigger Control Name:  SWTRIGCTRL Offset:  0x10 Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 Access Reset Bit 23 22 21 20 19 18 17 16 Access Reset Bit 15 14 13 12 11 10 9 8 Access Reset Bit 7 6 5 4 3 2 1 0 SWTRIGn[6:0] Access R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 Bits 6:0 – SWTRIGn[6:0] Channel n Software Trigger [n = 7..0] This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is either set, or by writing a '1' to it. This bit is set if CHSTATUS.PEND is already '1' when writing a '1' to that bit. Writing a '0' to this bit will clear the bit. Writing a '1' to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND=0 for channel x. CHSTATUS.PEND will be set and SWTRIGn will remain cleared. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 512 28.8.9 Priority Control 0 Name:  PRICTRL0 Offset:  0x14 Reset:  0x00000000 Property:  PAC Write-Protection Bit 31 30 29 28 27 26 25 24 RRLVLEN3 LVLPRI3[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 23 22 21 20 19 18 17 16 RRLVLEN2 LVLPRI2[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 RRLVLEN1 LVLPRI1[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 RRLVLEN0 LVLPRI0[3:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0 Bit 31 – RRLVLEN3 Level 3 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 3. For details on arbitration schemes, refer to 28.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 3 priority. 1 Round-robin arbitration scheme for channels with level 3 priority. Bits 27:24 – LVLPRI3[3:0] Level 3 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3=1) for priority level 3, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 3. When static arbitration is enabled (PRICTRL0.RRLVLEN3=0) for priority level 3, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN3 written to '0'). Bit 23 – RRLVLEN2 Level 2 Round-Robin Arbitration Enable This bit controls which arbitration scheme is selected for DMA channels with priority level 2. For details on arbitration schemes, refer to 28.6.2.4 Arbitration. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 513 Value Description 0 Static arbitration scheme for channels with level 2 priority. 1 Round-robin arbitration scheme for channels with level 2 priority. Bits 19:16 – LVLPRI2[3:0] Level 2 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2=1) for priority level 2, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 2. When static arbitration is enabled (PRICTRL0.RRLVLEN2=0) for priority level 2, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN2 written to '0'). Bit 15 – RRLVLEN1 Level 1 Round-Robin Scheduling Enable For details on arbitration schemes, refer to 28.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 1 priority. 1 Round-robin arbitration scheme for channels with level 1 priority. Bits 11:8 – LVLPRI1[3:0] Level 1 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1=1) for priority level 1, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 1. When static arbitration is enabled (PRICTRL0.RRLVLEN1=0) for priority level 1, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN1 written to '0'). Bit 7 – RRLVLEN0 Level 0 Round-Robin Scheduling Enable For details on arbitration schemes, refer to 28.6.2.4 Arbitration. Value Description 0 Static arbitration scheme for channels with level 0 priority. 1 Round-robin arbitration scheme for channels with level 0 priority. Bits 3:0 – LVLPRI0[3:0] Level 0 Channel Priority Number When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0=1) for priority level 0, this register holds the channel number of the last DMA channel being granted access as the active channel with priority level 0. When static arbitration is enabled (PRICTRL0.RRLVLEN0=0) for priority level 0, and the value of this bit group is non-zero, it will not affect the static priority scheme. This bit group is not reset when round-robin arbitration gets disabled (PRICTRL0.RRLVLEN0 written to '0'). SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 514 28.8.10 Interrupt Pending Name:  INTPEND Offset:  0x20 Reset:  0x0000 Property:  - This register allows the user to identify the lowest DMA channel with pending interrupt. Bit 15 14 13 12 11 10 9 8 PEND BUSY FERR SUSP TCMPL TERR Access R R R R/W R/W R/W Reset 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ID[3:0] Access R/W R/W R/W R/W Reset 0 0 0 0 Bit 15 – PEND Pending This bit will read '1' when the channel selected by Channel ID field (ID) is pending. Bit 14 – BUSY Busy This bit will read '1' when the channel selected by Channel ID field (ID) is busy. Bit 13 – FERR Fetch Error This bit will read '1' when the channel selected by Channel ID field (ID) fetched an invalid descriptor. Bit 10 – SUSP Channel Suspend This bit will read '1' when the channel selected by Channel ID field (ID) has pending Suspend interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Suspend interrupt flag. Bit 9 – TCMPL Transfer Complete This bit will read '1' when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag. Bit 8 – TERR Transfer Error This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt. Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Channel ID (ID) Transfer Error interrupt flag. SAM L10/L11 Family DMAC – Direct Memory Access Controller © 2018 Microchip Technology Inc. Datasheet DS60001513B-page 515 Bits 3:0 – ID[3:0] Channel ID These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending ch