ALF2412 24 Volts continu 300 watts - PDF - Farnell Element 14 - Revenir à l'accueil

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Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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Voltage Level Translation

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Documents PDF :

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1 ALIMENTATION FIXE A DÉCOUPAGE ALF2412 24 Volts continu 300 watts 12,5 Ampères                                - Output ripple < 3mV rms. - Built in power corrector (PFC). - Output voltage adjustable from 20 to 30 V. 15 A at 20 V and 10 A at 30 V. - Parallel active mode. - Short circuit protection. - Temperature controlled fan cooling. - Ausgangswelligkeit < 3mV effektiv. - Eingebaute Leistungsfaktorkorrektur (PFC) - Ausgangsspannung verstellbar zwischen 20 und 30 V 15 A von 20 V und 10 A von 30 V. - Paralleler aktiver modus. - Schutz gegen Kurzschlüsse. - Geregelte Lüftung. Autres caractéristiques • Sécurité : Classe II, double isolation, conforme à la norme EN 61010-1. • CEM : Conforme à la norme EN 61326-1 • Indice de protection : IP 30 • Alimentation : Secteur 190 à 253 Volts, 50 / 60 Hz. • Entrée secteur : cordon 2 pôles double isolation. • Consommation : 360 W maxi. • Facteur de puissance : 0,99 (PFC intégré). • Rigidité diélectrique : 3000 V entre entrée et sortie. • Présentation : Boîtier métal avec peinture époxy. Caractéristiques techniques Tension • Sorties flottantes sur douilles de sécurité de 4 mm. • Tension de sortie : ajustable de 20 à 30 V linéairement par réglage fin. • Régulation : < 50 mV pour une variation de charge de 0 à 100 %. < 10 mV pour une variation secteur de 190 V à 253 V. • Ondulation : < 3 mV efficace comprenant : < 5 mV crête à crête du signal à 100 KHz < 5 mV crête à crête du signal à 100 Hz < 40 mV crête à crête des pics de commutations • Résistance interne : 4 mΩ • Temps de maintien : 25 ms à 50 % de charge et 12 ms à 100 % (secteur à 190 V) • Visualisation : Led verte "alimentation en fonctionnement" Led rouge “surchauffe ou surtension en sortie” Intensité • I maxi : 15,5 A au court-circuit 15 A à 20 V, 12,5 A à 24V, 10 A à 30 V Puissance • Puissance constante de sortie : 300 W de 20 à 30 volts. Mise en parallèle • Bus de contrôle (1 conducteur) sur douilles de sécurité de 2 mm. • Nombre d’unité en parallèle : illimité. Protections • Contre les courts-circuits par limitation de courant. • Contre les surintensités sur la source, par fusible interne. • Contre les surtensions en sortie, par limitation de tension à 33 V. • Contre les échauffements par ventilateur contrôlé. - Ondulation de sortie < 3mV efficace. - Correcteur du facteur de puissance (PFC) intégré. - Tension de sortie ajustable de 20 à 30 Volts. - 15 A à 20 V et 10 A à 30 V - Mise en parallèle active - Protection contre les courts-circuits. - Ventilation controlée. Other specifications • Safety : Class II, double insulation, complies with EN 61010-1. • EMC : Complies with EN 61326-1. • Protection level : IP 30. • Input voltage : 190 to 253 Volts, 50 / 60 Hz. • Mains input : double insulation 2 poles cable. • Power consumption : 360 W max. • Power factor : 0.99 (built in PFC). • Dielectric strength : 3000 V between input and output. • Presentation : metal case with epoxy finish. Specifications Voltage • Floating outputs on 4-mm safety sockets. • Output voltage : adjustable from 20 to 30 V linearly with fine adjustment. • Regulation : < 50 mV for a load change from 0 to 100%. < 10 mV for a line change from 190 to 253 V. • Ripple : < 3 mV rms including : < 5 mV peak to peak of the signal at 100 KHz < 5 mV peak to peak of the signal at 100 Hz < 40 mV peak to peak of switching spikes • Internal resistance : 4 mΩ. • Hold-up time : 25 ms at half load and 12 ms at full load (190V line input). • Indicator : green power-on LED indicator. overheat or overvoltage red LED indicator. Current • Max I : 15,5 A in short circuit condition. 15 A at 20 V, 12,5 A at 24 V, 10 A at 30 V. Power • Constant output power : 300 W from 20 to 30 V. Paralleling • Load share controller (1 wire) on 2 mm safety sockets. • Number of units in parallel : unlimited. Protections • Against short circuits, by current regulation. • Against transformer primary overcurrent, by internal fuse. • Against output overload, by voltage limiting to 33 V. • Against overheat by controlled fan. 46 Andere Eigenschaften • Schutz : Klasse II, schutzisoliert, entspricht den Normen EN 61010-1. • EMC : Entspricht den Normen EN 61326-1. • Schutzart : IP 30. • Versorgung : Netzversorgung 190 bis 253 Volt, 50 / 60 Hz. • Netzversorgungseingang : schutzisoliertes 2-Phasen-Netzkabel. • Leistungsaufnahme : max. 360W. • Leistungsfaktor : 0,99 (PFC integriert). • Durchschlagsfestigkeit : 3000 V Zwischen Eingang und Ausgang. • Erscheinungsbild : Metallgehäuse mit Epoxid-Lackierung. Technische Daten Spannung • Ausgänge von Masse getrennt (floating) auf 4-mm-Schutzbuchsen. • Ausgangsspannung : linear verstellbar zwischen 20 und 30 V. • Regelung : < 50 mV bei Laständerungen von 0 bis 100%. < 10 mV bei Schwankungen der Netzversorgung zwischen 190 V und 253 V. • Welligkeit : < 3 mV effektiv mit : < 5 mV Spitze-Spitze des Signals bei 100kHz < 5 mV Spitze-Spitze des Signals bei 100Hz < 40 mV Spitze-Spitze von Schaltspitzen • Innenwiderstand : 4 mΩ • Haltezeit : 25 ms bei 50% der Last und 12 ms bei 100% (Netzversorgung bei 190V). • Anzeige : Grüne LED “Versorgung bei Betrieb”. Rote LED "Status, Fehler auf Ausgang". Stromstärke • I max : 15,5 A bei Kurzschluss 15 A von 20 V, 12,5 A von 24 V, 10 A von 30 V. Liestung • Konstanter Ausgangsleistung : 300 W von 20 bis 30 V. Parallelbetrieb • PV-Knotten (1 leiter) auf 2mm-Schutzbuchsen. • Anzhal der parallelen Eineiht : umbeschränkt. Schutzvorrichtungen • Gegen Kurzschlüsse durch Strombegrenzung. • Gegen Überströme auf dem Primärkreis des Transformators durch internieter Sicherung. • Gegen Überspannungen am Ausgang durch Spannungsbegrenzung auf 33 V. • Gegen übermässige Erwärmung durch gesteuerten Lüfter. Switching fixed power supply ALF2412 Feste Unterbrechungsfreie Versorgung ALF2412 1 ALIMENTATION FIXE A DÉCOUPAGE ALF1225 12 Volts continu 300 watts 25 Ampères                                - Output ripple < 3mV rms. - Built in power corrector (PFC). - Output voltage adjustable from 10 to 15 V. 25 A from 10 at 12 V and 20 A at 15 V. - Parallel active mode. - Short circuit protection. - Temperature controlled fan cooling. - Ausgangswelligkeit < 3mV effektiv. - Eingebaute Leistungsfaktorkorrektur (PFC). - Ausgangsspannung verstellbar zwischen 10 und 15 V. 25 A von 10 bis 12 V und 20 A bis 15 V. - Paralleler aktiver modus. - Schutz gegen Kurzschlüsse. - Geregelte Lüftung. Autres caractéristiques • Sécurité : Classe II, double isolation, conforme à la norme EN 61010-1. • CEM : Conforme à la norme EN 61326-1 • Indice de protection : IP 30 • Alimentation : Secteur 190 à 253 Volts, 50 / 60 Hz. • Entrée secteur : cordon 2 pôles double isolation. • Consommation : 360 W maxi. • Facteur de puissance : 0,99 (PFC intégré). • Rigidité diélectrique : 3000 V entre entrée et sortie. • Présentation : Boîtier métal avec peinture époxy. Caractéristiques techniques Tension • Sorties flottantes sur douilles de sécurité de 4 mm. • Tension de sortie : ajustable de 10 à 15 V linéairement par réglage fin. • Régulation : < 100 mV pour une variation de charge de 0 à 100 %. < 10 mV pour une variation secteur de 190 V à 253 V. • Ondulation : < 3 mV efficace comprenant : < 5 mV crête à crête du signal à 100 KHz < 5 mV crête à crête du signal à 100 Hz < 40 mV crête à crête des pics de commutations • Résistance interne : 4 mΩ • Temps de maintien : 25 ms à 50 % de charge et 12 ms à 100 % (secteur à 190 V) • Visualisation : Led verte "alimentation en fonctionnement" Led rouge “surchauffe ou surtension en sortie” Intensité • I maxi : 25,5 A au court-circuit 25 A de 10 V à 12 V, 20 A à 15 V Puissance • Puissance de sortie : 300 W de 12 à 15 V, 250 W à 10 V. Mise en parallèle • Bus de contrôle (1 conducteur) sur douilles de sécurité de 2 mm • Nombre d’unité en parallèle : illimité. Protections • Contre les courts-circuits par limitation de courant. • Contre les surintensités sur la source, par fusible interne. • Contre les surtensions en sortie, par limitation de tension à 17 V. • Contre les échauffements par ventilateur contrôlé. - Ondulation de sortie < 3mV efficace. - Correcteur du facteur de puissance (PFC) intégré. - Tension de sortie ajustable de 10 à 15 Volts. - 25 A de 10 à 12 V et 20 A à 15 V - Mise en parallèle active - Protection contre les courts-circuits. - Ventilation controlée. Other specifications • Safety : Class II, double insulation, complies with EN 61010-1. • EMC : Complies with EN 61326-1. • Protection level : IP 30. • Input voltage : 190 to 253 Volts, 50 / 60 Hz. • Mains input : double insulation 2 poles cable. • Power consumption : 360 W max. • Power factor : 0.99 (built in PFC). • Dielectric strength : 3000 V between input and output. • Presentation : metal case with epoxy finish. Specifications Voltage • Floating outputs on 4-mm safety sockets. • Output voltage : adjustable from 10 to 15V linearly with fine adjustment. • Regulation : < 100 mV for a load change from 0 to 100%. < 10 mV for a line change from 190 to 253 V. • Ripple : < 3 mV rms including : < 5 mV peak to peak of the signal at 100 KHz < 5 mV peak to peak of the signal at 100 Hz < 40 mV peak to peak of switching spikes • Internal resistance : 4 mΩ. • Hold-up time : 25 ms at half load and 12 ms at full load (190V line input). • Indicator : green power-on LED indicator. overheat or overvoltage red LED indicator. Current • Max I : 25,5 A in short circuit condition. 25 A from 10 to 12 V, 20 A at 15 V. Power • Output power : 300 W from 12 to 15 V, 250 W to 10 V. Paralleling • Load share controller (1 wire) on 2-mm safety sockets. • Number of units in parallel : unlimited. Protections • Against short circuits by current regulation. • Against transformer primary overcurrent, by internal fuse. • Against output overload by voltage limiting to 17 V. • Against overheat by controlled fan. 38 Andere Eigenschaften • Schutz : Klasse II, schutzisoliert, entspricht den Normen EN 61010-1. • EMC : Entspricht den Normen EN 61326-1. • Schutzart : IP 30. • Versorgung : Netzversorgung 190 bis 253 Volt, 50 / 60 Hz. • Netzversorgungseingang : schutzisoliertes 2-Phasen-Netzkabel. • Leistungsaufnahme : max. 360W. • Leistungsfaktor : 0,99 (PFC integriert). • Durchschlagsfestigkeit : 3000 V Zwischen Eingang und Ausgang. • Erscheinungsbild : Metallgehäuse mit Epoxid-Lackierung. Technische Daten Spannung • Ausgänge von Masse getrennt (floating) auf 4-mm-Schutzbuchsen. • Ausgangsspannung : linear verstellbar zwischen 10 und 15 V. • Regelung : < 100 mV bei Laständerungen von 0 bis 100%. < 10 mV bei Schwankungen der Netzversorgung zwischen 190V und 253V. • Welligkeit : < 3 mV effektiv mit : < 5 mV Spitze-Spitze des Signals bei 100kHz < 5 mV Spitze-Spitze des Signals bei 100Hz < 40 mV Spitze-Spitze von Schaltspitzen • Innenwiderstand : 4 mΩ • Haltezeit : 25 ms bei 50% der Last und 12 ms bei 100% (Netzversorgung bei 190V). • Anzeige : Grüne LED “Versorgung bei Betrieb”. Rote LED "Status, Fehler auf Ausgang". Stromstärke • I max : 25,5 A bei Kurzschluss. 25 A von 10 bis 12 V, 20 A von 15 V. Liestung • Ausgangsleistung : 300 W von 12 bis 15 V, 250 W von 10 V. Parallelbetrieb • PV-Knotten (1 leiter) auf 2mm-Schutzbuchsen. • Anzhal der parallelen Eineiht : umbeschränkt. Schutzvorrichtungen • Gegen Kurzschlüsse durch Strombegrenzung. • Gegen Überströme auf dem Primärkreis des Transformators durch internieter Sicherung. • Gegen Überspannungen am Ausgang durch Spannungsbegrenzung auf 17 V. • Gegen übermässige Erwärmung durch gesteuerten Lüfter. Switching fixed power supply ALF1225 Feste Unterbrechungsfreie Versorgung ALF1225 3U 4V 4A L1 L2 L3 N 4 entrées Tension & 4 entrées Courant Mode Inrush Capacité mémoire inégalée Ratios de tension et de courant C.A 8332B C.A 8334B C.A 8335 L’expérience du Qualistar l’assurance de la performance ANALYSEURS DE PUISSANCE ET DE QUALITÉ D’ÉNERGIE Mesure des paramètres de tension, courant et puissances utiles jusqu’au diagnostic complet d’une installation électrique. Capture et enregistrement simultanés de tous les paramètres, transitoires, alarmes et forme d’ondes. Simplicité d’emploi éprouvée. IEC 61010 600 V CAT IV IEC 61010 1000 V CAT III Nouveau( ) 370V 50.01Hz 231.6 v RMS THD CF 231.6 v -370 0 <> 2 < t = 6.8 ms V1 = +278 V2 = 1 Analyseurs de puissance et de qualité d’énergie Destinés aux services de contrôle et de maintenance des bâtiments industriels ou administratifs, les Qualistar permettent d’obtenir une image instantanée des principales caractéristiques de la qualité du réseau électrique. Maniables et précis, ces appareils proposent également de nombreuses valeurs calculées et plusieurs fonctions de traitement. Affichage en temps réel des différentes formes d’onde Liaison avec le PC via une connexion USB Accès direct aux principales mesures (Harmoniques, …) Accès direct aux principales fonctions (configuration, capture d’écran…) Stabilité grâce à la béquille escamotable Entrées Tension/Courant, munis de bagues de repérage couleur Large écran ¼ V GA couleur pour une excellente lisibilité R.Aubin v 234.4 v 15.3 v 09/12/09 14:02 3U 4V 4A L1 L2 L3 N = +21 V3 = -291 VN= +3 > 3 N 2 3 C.A 8335 FONCTIONNALITÉS 3 Affichage en temps réel des formes d’ondes (4 tensions et 4 courants) 3 Mesures des tensions et courants efficaces à la ½ période 3 Utilisation intuitive 3 Reconnaissance automatique des différents types de capteurs de courant 3 Prise en compte de toutes les composantes continues 3 Mesure, calcul et affichage des harmoniques jusqu’au 50ème rang, avec leur information de phase 3 Calcul des Taux de Distorsion Harmoniques (THD) 3 Capture de transitoires à l’échantillon (1/256ème de période) 3 Affichage du diagramme de phase 3 Mesure des puissances VA, W et var totale et par phase 3 Mesure des énergies VAh, Wh et varh totale et par phase 3 Calcul du facteur K 3 Calcul du Facteur de Déplacement de Puissance cos j (DPF) et du Facteur de Puissance (PF) 3 Captures jusqu’à 210 transitoires 3 Calcul du Flicker 3 Calcul du déséquilibre (courant et tension) 3 Surveillance du réseau électrique avec paramétrage des alarmes 3 Sauvegarde et enregistrement des captures d’écran (image et données) 3 Enregistrement et exportation sur PC 3 Logiciel de rapatriement des données, et de communication en temps réel avec un PC. Flicker Alarmes Evènements Puissances réactives Harmoniques et harmoniques de rang H3 Puissances & cos j FONCTIONNALITÉS 370V 50.01Hz 231.6 v RMS THD CF 231.6 v -370 0 <> 2 < t = 6.8 ms V1 = +278 V2 = 1 SETUP Z BRANCHEMENTS Z RATIOS ET CAPTEURS Z AFFICHAGE Z L’utilisateur entre directement les paramètres généraux de l’appareil (date et heure, contraste de l’affichage...). Ensuite, il sélectionne le type de réseau sur lequel le Qualistar est connecté. Les capteurs connectés sont reconnus automatiquement. La vérification est possible via l’écran correspondant. COCNOFINGUFIRGAUTIROANTION TRANSITO IRES ENREGISTREMENTS ALARMES ( ) Nouveauté C.A 8335 Analyseurs de puissance et de qualité d’énergie Nouveauté C.A 8335 Menus disponibles en 25 langues !( ) v 234.4 v 15.3 v 09/12/09 14:02 3U 4V 4A L1 L2 L3 N = +21 V3 = -291 VN= +3 > 3 N 4 5 Les pratiques Aide En cas d’hésitation, la touche Aide vous explique clairement les fonctions se rapportant à l’écran visualisé. Photographie d’écran En appuyant sur cette touche, l’appareil . effectue une copie d’écran. Une mise en . mémoire de l’écran visualisé est automatique avec horadatage. Effacement Afin de ne pas surcharger la mémoire, l’utilisateur peut sélectionner le type de fichier à supprimer. et ne conserver que ce qui est utile. Mode Harmoniques THD global et phase par phase en U, I, V, VA . en %, et valeur RMS, déphasage des harmoniques. Seul les C.A 8334 & C.A 8335 disposent de la fonction harmoniques en VA . et du « mode expert ». . Ces derniers permettent d’analyser l’influence des harmoniques sur l’échauffement du neutre ou sur les machines tournantes. Graphique Z mesure de puissance Z Vectorie lle Z THD phase par phase Z intégration de puissance/ énergie sur une durée ZZ Mode Puissances/Energies Ce mode affiche toutes les valeurs relatives à la puissance et à l’énergie.. Les touches « start » et « stop » permettent, respectivement, de déclencher et d’arrêter le cumul des énergies. Mesures de : W, var, VA Wh, varh, VAh. PF, DPF ou cos j et tan j Accessible en face avant des Qualistar®, la capture d’écrans se fait par simple appui sur une touche. L’accès à l’Aide est disponible à chaque étape de l’utilisation des Qualistar. Tableau Z Nouveauté C.A 8335 Visualiser les 4 entrées simultanément !( ) THD Global ZZ VISVUAISLIUSEAR LINISSTEARNTANÉMENT LES CARACTÉRISTIQUES D’UN RÉSEAU C.A 8335 OBSERVATION DIAGNOSTIC 370V 50.01Hz 231.6 v RMS THD CF 231.6 v -370 0 <> 2 < t = 6.8 ms V1 = +278 V2 = 1 Mode Enregistrement (Min/Max C.A 8335 uniquement) Lors d’un enregistrement, tous les paramètres désirés sont sauvegardés avec une visualisation graphique de ces paramètres. Notons qu’un bargraphe en haut de la fenêtre permet d’apprécier la durée totale d’enregistrement. Période d’enregistrement et cadence de mémorisation programmables. Mode Alarmes Les alarmes sont à définir lors de la configuration de l’appareil. L’utilisateur paramètre directement l’ensemble des dépassements à surveiller pendant la prise de mesure. Pour chaque dépassement de seuil d’alarme, l’appareil effectue un horodatage de l’événement et enregistre sa durée ainsi que ses valeurs Min et Max. Mode Transitoires Le mode transitoires permet la capture d’événements sur la tension et le courant avec déclenchements sur seuils.. La représentation se fait sur 4 périodes de l’événement capturé à 256 points/périodes, avec possibilité de zoom. Toutes les opérations de surveillance s’effectuent sur l’ensemble des caractéristiques en parallèle ! Analyseurs de puissance et de qualité d’énergie SURVEILLANCE v 234.4 v 15.3 v 09/12/09 14:02 3U 4V 4A L1 L2 L3 N = +21 V3 = -291 VN= +3 > 3 N 6 7 L’utilisateur accède directement : 3 aux données enregistrées dans l’appareil 3 à sa configuration 3 aux différentes mesures en temps réel 3 à la gestion de rapports 3 à la gestion de bases de données Ces appareils se connectent au PC. via liaison USB, interface RS232. est compatible avec. d’autres produits Chauvin Arnoux®. Système d’exploitation minimum requis : 3 Windows® 2000 3 Windows® XP 3 Windows® Vista 3 Windows® 7 Simple d’utilisation, le logiciel reconnaît automatiquement l’appareil connecté au PC, et ouvre le menu correspondant. • Configuration de l’appareil : setup, enregistrement, alarmes • Traitement des données enregistrées et des alarmes • Transfert des impressions d’écran et des transitoires • Exportation des données sur tableur Excel • Exportation des données sous formes graphiques . sous WindowsTM C.A 8335 INRUSH LOLGOICGIEILCSIELS ( ) Nouveauté C.A 8335 L’Inrush ou courant d’appel correspond au courant d’entrée maximal appelé par un dispositif électrique lorsqu’il est mis sous tension. Cette mesure permet le dimensionnement correct de l’installation électrique. Dans sa configuration standard, le est fourni en sacoche avec ses cordons . de mesure et pinces crocodiles, son alimentation secteur, le câble de liaison PC. et son logiciel d’exploitation.. Ensuite, l’utilisateur choisit les pinces de courant selon son besoin. Nouveauté C.A 8335 ! Les bagues de couleur sont à positionner à chaque extrémité. des cordons de mesure et facilite ainsi le repérage des branchements. L’exploitation des mesures réalisées avec les s’effectue à partir de 2 logiciels ; d’une part et le plus complet. ACACECSCSEOSIRSEOSIRES Mode Enveloppe Valeurs RMS Forme d’onde FRANCE Chauvin Arnoux 190, rue Championnet 75876 PARIS Cedex 18 Tél : +33 1 44 85 44 85 Fax : +33 1 46 27 73 89 info@chauvin-arnoux.fr www.chauvin-arnoux.fr SUISSE Chauvin Arnoux AG Moosacherstrasse 15 8804 AU / ZH Tél : +41 44 727 75 55 Fax : +41 44 727 75 56 info@chauvin-arnoux.ch www.chauvin-arnoux.ch moyen-orient Chauvin Arnoux Middle East P.O. BOX 60-154 1241 2020 JAL EL DIB (Beyrouth) - LIBAN Tél : +961 1 890 425 Fax : +961 1 890 424 camie@chauvin-arnoux.com www.chauvin-arnoux.com Mesures Nombre de voies 3U / 4I 4U / 4I Tension (TRMS AC+DC) Phase-Phase 6 V à 960 V 10 V à 1000 V Phase-Neutre 6 V à 480 V 10 V à 1000 V Ratio de tension - jusqu’à 500 kV Courant (TRMS AC+DC) De 100 mA à 6500 A Pinces MN MN93 : 2 à 240 Aac ; MN93A : 0,005 Aac à 5 Aac / 0,1 Aac à 120 Aac Pince C193 3 A à 1200 Aac Pinces AmpFLEX ou MA 30 A à 6500 Aac Pince PAC93 10 A à 1000 Aac / 10 A à 1400 Adc Pince E3N 50 mA à 10 Aac/dc 100 mA à 100 Aac/dc Ratio de courant de 10 mA à 50 kA Fréquence 40 Hz à 69 Hz Puissances W, VA, var, PF, DPF, cos j, tan j Energies Wh, varh, VAh Harmoniques oui THD oui, du rang 0 à 50, phase Mode Expert - oui Transitoires - 50 210 Flicker oui Mode Inrush - oui sur 4 périodes oui, > 1 minute Déséquilibre oui Enregistrement Min/Max non oui de tous les paramètres sur échantillonnage max 21 minutes 42 minutes 1 mois d’une sélection de paramètres avec acquisition toutes les 10 min + de 17 jours + de 37 jours plusieurs années Alarmes 4000 de 10 types différents 10000 de 40 types différents Reconnaissance de capteurs de courant 8 9 Peak oui Représentation vectorielle automatique Affichage LCD couleur ¼ VGA 320 x 240 diagonale 148 mm Capture écrans & courbes 8 12 50 Sécurité électrique IEC 61010 1000 V CAT III / 600 V CAT IV Langues 6 25+ Interface communication RS232 optique / USB USB type B Alimentation Batterie rechargeable 9,6 V NiMH ou alimentation secteur Dimensions 240 x 180 x 55 mm Masse 2,1 kg 1,9 kg État de livraison C.A 8332B et C.A 8334B : livrés avec une sacoche n° 22, un cordon RS232 optique, un cordon secteur, 4 cordons tension banane Ø 4 mm de 3 m, 4 pinces crocodiles, une fiche de sécurité, le mode d’emploi, un logiciel PC de rapatriement des données. Plus le jeu de capteur de courant choisi. C.A 8335 : livré avec une sacoche n° 22, un cordon USB, un chargeur alimentation, un cordon secteur, 5 cordons tension banane Ø 4 mm de 3 m, 5 pinces crocodiles, un jeu de repérage 12 couleurs des cordons et entrées, un film de protection écran, une fiche de sécurité, le mode d’emploi multilangue et le logiciel PC de rapatriement des données. C.A 8332B C.A 8334B Qualistar+ C.A 8335 C.A 8335 seul......................................... P01160577 C.A 8332B-F pince MN93A...................... P01160522 C.A 8334B-F pince MN93A...................... P01160552 C.A 8332B-F AmpFLEXTM 450 mm............ P01160523 C.A 8334B-F AmpFLEXTM 450 mm............ P01160553 C.A 8332B-INT pince MN93A.................. P01160525 C.A 8334B-INT pince MN93A.................. P01160555 C.A 8332B-INT AmpFLEXTM 450 mm........ P01160526 C.A 8334B-INT AmpFLEXTM 450 mm........ P01160556 Autres modèles, nous consulter. Pince MN93........................................... P01120425B Pince MN93A........................................ P01120434B Pince C 193............................................. P01120323B Pince PAC93........................................... P01120079B Pince AMP450...................................... P01120526B Pince AMP800...................................... P01120531B Mini-AmpFLEX™ MA193, 200 mm... P01120580 Pince E3N*............................................. P01120043A Adaptateur E3N*................................. P01120081 Bloc secteur E3N*................................. P01120047 Pack batterie ...........................P01296024 Film écran Qualistar ..............P01102059 Jeu pions-bagues*..................P01102060 Sacoche n° 21............................P01298055 Sacoche n° 22............................P01298056 Cordon optique RS232**.......P01295190A Cordon USB-A USB-B*...........P01295291 Boîtier 5 A.................................P01101959 Bloc secteur C .A 8335*...........P01102057 Logiciel Dataview....................P01102095 *C.A 8335 seulement, **C.A 8334B/C.A 8332B 906210171 - 01/2011 - Ed. 4 Pour informations et commandes Caractéristiques techniques C.A 8332B - C.A 8334B - C.A 8335 RÉFÉRENCES POUR COMMANDER ACCESSOIRES Visitez notre site Web http://www.sefram.fr XLN3640/XLN6024/ Sefram XLN8018 / XLN10014 Sefram Alimentations programmables de puissance à découpage Fiabilité, Précision, Excellence • Puissance délivrée de 1440W • Afficheur LCD graphique rétro-éclairé • Clavier en face avant pour une entrée simplifiée des données • Sortie additionnelle 5V / 1A sur tous les modèles • Programmation (SCPI) • Mémoire de configurations (10 configurations mémorisées) • Protection totale: tension, courant, puissance • Mode "list" permettant de créer 10 programmes de 150 pas chacun • Faible poids (9kg) et format très compact (rack 1U) • Système de refroidissement astucieux : circulation forcée avant - arrière • Entrée programmation analogique • Prise de potentiel à distance pour compenser les pertes dans les connexions • Mise en série et parallèle de plusieurs unités (maxi 4) • Serveur Web embarqué pour une programmation aisée • Interface RS-485 (pilotage de plusieurs unités) • Interface USB en standard • Interface IEEE et LAN en option • Drivers Labview™ Toutes les fonctions nécessaires La nouvelle famille d'alimentations programmables XLN est destinée à toutes les applications industrielles pour lesquelles la fiabilité, la précision et la protection sont des critères importants. Toutes les alimentations XLN disposent non seulement des fonctions standards, mais offrent en plus un logiciel de programmation, les drivers Labview™, des commandes simplifiées à partir de la face avant. La conception a été optimisée pour simplifier la mise en oeuvre et garantir la sécurité des dispositifs connectés. Le format rack 19 pouces (hauteur 1U) permet une intégration facile et directe dans vos applications où la compacité est un critère déterminant. Nouvelle famille pour toutes les applications industrielles XLN3640 XLN6024 XLN8018 XLN10014 Tension de sortie 0 - 36V 0 - 60V 0 - 80V 0 - 100V Courant de sortie 0 - 40A 0 - 24A 0 - 18A 0 - 14A Sortie auxiliaire 5V / 1A 5V / 1A 5V / 1A 5V / 1A Interface USB oui oui oui oui Interface RS-485 oui oui oui oui Interface IEEE et LAN XLN3640GL XLN6024GL XLN8018GL XLN10014GL Guide de sélection 1440W dans un encombrement réduit. Format rack 19 pouces 1U USB RS-485 IEEE* LAN/Ethernet* * Option Alimentations programmables XLN2640, XLN6024, XLN8018, XLN10014 Un panneau avant simple et pratique Des accessoires complets Un panneau arrière complet: sorties, interfaces et contrôles Le clavier numérique en face avant associé à la roue codeuse permet une programmation simple et rapide de l'alimentation. Le courant et la tension peuvent être réglés avec une résolution allant jusqu'à 1mV et 1mA. L'afficheur graphique indique en permanence les valeurs de consigne et les valeurs réelles de tension et de courant. Il est possibles de mémoriser 10 configurations complètes et de les rappeler depuis le panneau avant ou en programmation à distance. Equerres et poignées pour mise en rack Sorties (puissance) Interface LAN Interface IEEE Entrée secteur Sortie auxiliaire 5V/1A Contrôle de la sortie Afficheur LCD graphique rétro-éclairé Roue codeuse Dispositif de refroidissement avec flux avant - arrière Clavier numérique pour l'entrée de valeurs Interface RS-485 Entrées contrôles externes (programmation analogique) Prise de Interface USB potentiel à distance Des connecteurs à visser ou à souder (les 2 sont livrés en standard) Alimentations programmables XLN2640, XLN6024, XLN8018, XLN10014 Jusqu'à 4 alimentations peuvent être connectées en série ou en parallèle en mode Maître/esclave. L'interface RS-485 est utilisée pour communiquer entre les alimentations Jusqu'à 31 alimentations peuvent être commandées au travers de l'interface RS-485, à l'aide d'un PC. La prise de potentiel déportée permet de compenser le spectres dans les câbles (jusqu'à 2V) et d'assurer ainsi une régulation parfaite aux bornes de la charge, quel que soit le courant. La programmation analogique est possible à partir d'une tension externe (0-10V) ou d'une résistance variable (0 - 5kohms). Les alimentations peuvent être contrôlées en SCPI au travers de l'interface Ethernet via une connexion TELNET Le logiciel d'application fourni permet la création de séquences de test (mode list), de créer ou sauvegarder des configurations, d'exporter les donner. Il fonctionne avec l'interface USB ou IEEE (option) Fonctionnement Maître / Esclave Interface TELNET Logiciel d'application sur PC Prise de potentiel déportée Pilotage de plusieurs alimentations Programmation analogique Spécifications susceptibles d’être modifiées sans préavis - FTXLNX F00 XLN2640, XLN6024, XLN8018, XLN10014 Alimentations programmables SSeeffrraamm Partenaire Distributeur 32, rue Edouard Martel • B.P. 55 • 42009 - St Etienne cedex 2 Fax. +33 (0).4.77.57.23.23 Web : www.sefram.fr • e-mail : sales@sefram.fr Spécifications de sortie Tension de sortie 0 - 36V 0 - 60V 0 - 80V 0 - 100V Courant de sortie 0 - 40A 0 - 24A 0 - 18A 0 - 14A Protection des sorties Gamme de réglage de la limite de tension 2 - 38V 3 - 64V 4 - 85V 5 - 105V Précision de la limitation de tension 200mV 300mV 400mV 500mV Régulation aux variations de ligne - Tension <4mV <6mV <8mV <10mV - Courant <4mA <4mA <4mA <4mA Régulation aux variations de charge - Tension <8mV <8mV <10mV <12mV - Courant <8mA <7mA <6,5mA <6mA Ondulation et bruit (20Hz - 20MHz) Tension de mode série avec charge >0,5% de la charge max <5mVeff./<60mVc-c <6mVeff./<70mVc-c <7mVeff./<80mVeff. <8mVeff./<80mVc-c Courant de mode série <90mA <70mA <50mA <40mA Résolution en programmation - Tension 1mV 1,5mV 2mV 2,5mV - Courant 1mA 1mA 1mA 1mA Précision en programmation (% de la sortie + offset) : - Tension ±(0,05% +10mV) ±(0,05% +15mV) ±(0,05% +20mV) ±(0,05% +25mV) - Courant ±(0,05% +10mA) ±(0,05% +18mA) ±(0,05% +7mA) ±(0,05% +6mA) Précision de relecture (% de la sortie + offset) : - Tension ±(0,05% +10mV) ±(0,05% +15mV) ±(0,05% +20mV) ±(0,05% +25mV) - Courant ±(0,05% +10mA) ±(0,05% +18mA) ±(0,05% +7mA) ±(0,05% +6mA) Temps de réponse transitoire < 1ms Temps de montée (pleine charge, pas de charge) <15mS <20ms <25ms <30ms Temps de descente (pleine charge/pas de charge) <15ms / <1000ms <20ms / <1000ms <25ms / <1000ms <30ms / <1000ms Facteur de puissance (PFC) >0,99 (à pleine charge) Temps de réponse à une commande de programmation <50ms Compensation max. en mode remote sense 2V Spécifications générales Température d'utilisation 0°C à 40°C (HR<80%) Température de stockage -10°C à 70°C (HR<85%) Sorties En face arrière Affichage LCD graphique rétro-éclairé Interface USB (Ethernet et IEEE en option) Alimentation 100V à 240V 47-63Hz (-15% à +10%, avec limitation à 90% de la puissance si V<95VAC) Puissance consommée 1700VA max. Rendement 80% Dimensions 420 x 46,3 x 432mm Masse 9kg Sécurité (secteur) IEC1010 catégorie II SPECIFICATIONS XLN2640 XLN6024 XLN8018 XLN10014 Livré avec : cordon d'alimentation, connecteurs de sortie (2), kit de montage en rack, manuel d'utilisation. Option : interface LAN (Ethernet) / IEEE - rajouter GL à la référence du produit (XLN3640GL, XLN6024GL, XLN8018GL, XLN10014GL) Des pompes de charge pour réduire la consommation d’énergie d’un systèm Par Dennis Hudgins, Texas Instruments Pour de nombreuses applications portables, la puissance consommée en mode Arrêt est plus critique que la puissance consommée en mode actif. Dans certaines applications, des mesures sont prises, des calculs sont réalisés et le résultat s’affiche sur un écran LCD ou est mémorisé en vue d’une consultation ultérieure. Pour préserver la durée de vie de la batterie, le circuit entre en général en mode veille entre chaque opération de mesure. Du fait qu’un tel appareil peut être activé pendant une infime période de la durée totale, le courant de drain appliqué à la batterie durant le mode veille peut considérablement affecter la durée de vie de celle-ci. En raison de la nature volatile de la RAM interne du microcontrôleur, une source de tension doit être appliquée pour conserver les données stockées en mémoire. Dans certains cas, avec des systèmes utilisant des pompes de charge, un contrôleur de batterie de secours, tel que le TPS3619, permet de désactiver la source d’alimentation. Grâce au TPS3619, la batterie alimente directement le microprocesseur, comme le MSP430, lorsque la source d’alimentation est désactivée, réduisant ainsi la consommation énergétique du système en mode basse puissance. Le circuit en Figure 1 utilise une pompe de charge REG710 pour convertir en alimentation 3,3V la tension fournie par deux piles alcaline/Ni-Cd ou d’autres convertisseurs Boost à deux piles et dotés d’une fonction activation. Dès que le microcontrôleur a terminé de traiter et de stocker des données, le circuit peut désactiver le REG710, laissant la tension de sortie diminuer jusqu’à ce qu’elle descende au-dessous du seuil de déclenchement interne. Le moniteur de secours commute alors la tension de sortie Vout du REG710 vers l’entrée VBAT. Au même moment, la broche Reset passe au niveau bas. Il n’est pas nécessaire d’utiliser le signal reset du TPS3619 pour réinitialiser le microcontrôleur du fait que le MSP430 fonctionne directement sur la batterie. Procéder ainsi peut provoquer le verrouillage du microcontrôleur en mode reset. Si la fonction Reset est nécessaire, le TPS3606 peut être utilisé en remplacement du TPS3619. Le TPS3619 peut aussi fournir une fonction détection de batterie faible grâce à la broche PFI, qui peut être connectée à un comparateur interne offrant un seuil de 1,15V. Lorsque la tension à l’entrée PFI tombe au-dessous de 1,15V, la tension de sortie PFO baisse. Des résistances RA et RB peuvent être utilisées pour fixer un seuil de batterie faible défini par l’utilisateur, et doivent être utilisées pour le MSP430 du fait que la tension opérationnelle de celui-ci est de 1,8V minimum. Celui-ci peut servir d’indicateur de batterie faible ou pour faire basculer le microcontrôleur en mode basse puissance. Le courant d’entrée de la broche PFI pouvant provoquer une erreur de tension directionnelle, l’association en parallèle de RA et RB doit être inférieure à 1MW. La fonction détection de batterie faible est optionnelle et il faudrait tenir compte de l’alimentation en courant continu utilisée par les résistances RA et RB, soit environ 2mA (2V/1MW). Dans de nombreux cas, le MSP430 fournit une fonction détection batterie faible intégrée, qui ne requiert pas de courant continu et offre une option système à faible consommation. En utilisant le TPS3619, la quantité de courant économisée en mode basse puissance est d’environ 65mA. Lorsque le TPS3619 est en mode batterie de secours, le courant de drain appliqué à la batterie diminue de 0.5mA maximum. Visitez notre site Web http://www.sefram.fr BK2650A, BK2652A, SSeeffrraamm BK2658A Analyseurs de spectre portables Une solution portable pour des analyses précises sur le terrain et en laboratoire. La nouvelle génération d'analyseurs de spectre portables est destinée à toutes les mesures sur le terrain et en laboratoire. Les performances offertes sont celles d'instruments haut de gamme, avec une autonomie de 4 heures, un design ultra compact et sans aucun compromis sur les spécifications. L'interface homme machine simple et conviviale permet une prise en main très rapide par les utilisateurs. Ces 3 analyseurs deviennent les nouvelles références pour les mesures de 50kHz à 8.5GHz. • Gamme de fréquence de 50kHz à 3.3GHz (BK1650A - 2652A) et 50kHz à 8.5GHz (BK2658A) • Design très compact et faible poids(1.8kg) • Autonomie de 4 heures avec batterie LiOn extractible • Générateur de poursuite intégré sur BK2652A • Plancher de bruit (DANL) de -127dBm et très faible bruit de phase • Logiciel d'application pour PC fourni (création de rapport,…) • Mémorisation de courbes et résultats sur clef USB • Afficheur LCD TFT couleur (640 x 480) • Nombreuses fonctions de mesure: puissance du canal, puissance canal adjacent bande occupée, mesures de champ électrique et magnétique, etc. • Fonction Auto tune permettant un réglage rapide et auto matique de tous les paramètres • Trigger externe pour mesures "span zéro" • Interface USB • Pilotage à distance possible avec commandes de type SCPI Performances • Mise en oeuvre et maintenance des installations de radio communication de type: Wifi, GSM, WiMax, Wlan, Bluetooth, CDMA, W-CDMA • Radiodiffusion et TV • Alignement d'antennes • Détection et mesures d'interférences • Mesure de la réponse en fréquence de filtres, câbles, com posants, etc. • Mesure de champ électrique avec les antennes optionnel les M401 à M406 • Mesure de champ magnétique avec la sonde de champ magnétique PR-26M Applications BK2650A, BK2652A, BK2658A FACE AVANT BK2650A/2652A/2658A BK2650A, BK2652A, BK2658A Ecran LCD panoramique (640 x 480), avec possibilité de passer en monochrome très haut contraste pour les utilisation en lumière intense Touches de menu Réglage du balayage et de la détection 2, 5 ou 10dB/div Mémorisation des écrans (bitmap) sur clef USB ou impression d'écran Personnalisation des noms de fichiers, réglage date et heure Réglage du niveau de référence de+1dBm à -60dBm (par pas de 1dB) Fonctions de mesure: - puissance du canal - puissance canal adjacent - bande occupée - champ électrique - champ magnétique Fonctions de calcul: - Max et Min - Moyenne - Overwrite (ré-écriture) Sauvegarde/rappel de courbes et configurations sur clef USB ou en mémoire interne. Marqueurs de mesure Roue codeuse pour sélection des paramètres Interface PC USB (esclave) type A Trigger externe (SMA) Interface USB (Host) pour clef USB (flash drives) Indicateur de charge de la batterie Entrée alimentation continue Entrée RF sur connecteur N, pouvant supporter 27dBm (CW) ou 25V DC. INTERFACES Fonction Auto-tune (recherche de la fréquence du siganl de + forte amplitude) Des fonctions de mesure très performantes Permet de mesurer la puissance totale d'un signal ou la puissance de bruit dans une bande passante définie par l'utilisateur. Mesure de puissance d'un canal La mesure est réalisée avec une antenne dipole connectée à l'instrument. L'utilisateur peut choisir parmi 7 antennes optionnelles. Chaque antenne est dédiée à une bande radiofréquence spécifique. - M401: GSM 850-900MHz - M403: GSM et W-CDMA 1800-1900MHz - M404: Wifi, Bluetooth 2.4GHz - M405: LAN 5GHz - AN307: WiMax Europe 3.5GHz Combiné avec la fonction Max hold et un balayage de 10ms, il est possible de mesurer le champ électrique d'émission de type Bluetooth, bien que ces émissions soient du type agilité de fréquence et spectre étalé. Les différentes antennes proposées en option permettent des mesures précises, contrairement à l'utilisation d'antennes très large bande (qui se traduit par une dynamique de mesure très inférieure). De plus les diagrammes de rayonnement sont intégrés dans l'analyseur de spectre (hors AN307) et permettent des mesures immédiates sans apporter de correction. Le champ est directement affiché en dBμV/m. Pour l'utilisation d'antennes d'autres types, l'utilisateur peut rentrer les données du diagramme de rayonnement. Mesure de champ électrique Avec l'antenne optionnelle PR26M, les analyseurs de spectre de la famille 265XA offrent la possibilité de mesurer la distribution du champ magnétique sur les circuits imprimés ou sur des circuits intégrés. La sonde PR26M dispose d'une tête avec boucle magnétique qui ne mesure que la composante magnétique du champ. La sonde permet des mesures de 10MHz à 3GHz. Les données de compensation sont intégrées en mémoire des instruments et le résultat est directement affiché en dBμA/m. Les applications typiques sont: mesures d'efficacité de condensateurs bypass, mesures d'adaptation ou de couplage de microstrips sur circuit imprimé. La résolution spatiale de la sonde est très fine (0.25mm) ce qui rend la sonde insensible aux parasites. Mesure de champ magnétique Cette fonction permet de mesurer la puissance d'un signal qui est perdue dans les canaux adjacents. Les paramètres de fréquence centrale, offset, bande du canal adjacent peuvent être définis. L'utilisateur peut choisir une des 3 mesures prenant en compte la puissance de la porteuse de référence: puissance totale, puissance crête, puissance dans la bande. Mesure de puissance d'un canal adjacent Cette mesure calcule la bande occupée à partir de la puissance totale. 2 mesures possibles: l'utilisateur définie N% de la puissance totale, ou un niveau de XdB en dessous de la crête. Bande occupée Fonctions calculs et marqueurs Max Hold: pour chaque point affiché, l'amplitude est comparée au point mesuré lors du précédant balayage. Si le point est plus élevé, il est affiché, sinon on conserve la valeur précédente. Cette fonction est très utile pour observer les signaux intermittents, les mesures de champs électriques ou les émissions à agilité de fréquence. Min Hold: fonctionne comme le Max hold, mais ne retient que l'amplitude minimale. Dans les 2 cas, le nombre de balayage pris en compte est paramétrable en puissances de 2 (de 1 à 1024) ou sur un nombre infini. Fonction Max et Min Hold L'analyseur balaye en continu mais, pour chaque point il calcule la moyenne avec les valeurs d'amplitude des précédentes acquisitions. Le nombre d'échantillons est paramétrable en puissances de 2 (de 1 à 1024). Cette fonction est intéressante pour mesurer des signaux noyés dans le bruit. Fonction MOYENNE (Average) Le résultat de chaque balayage n'est pas effacé, ce qui permet de visualiser des variations à long terme de signaux. Deux possibilités sont offertes à l'utilisateur pour l'emploi des marqueurs: - mode "normal" pour lequel la fréquence et l'amplitude sont mesurée au marqueur - mode Delta pour lequel la différence entre les 2 marqueurs est mesurée. Fonction overwrite (ré-écriture) Fonction Marqueurs Deux modes sont possibles pour la fonction crête: - Mode "normal" pour lequel on recherche la valeur crête à l'écran. En appuyant sur la touche Next (suivante) on accède aux points suivants. - Mode crête sur une zone définie par une fréquence centrale et une largeur de bande. Fonction Peak (crête) Facilité d'utilisation Un logiciel PC très utile pour vos rapports de test La sauvegarde directe sur clef USB L'interface homme-machine de la famille d'analyseurs de spectre BK265XA a été optimisée pour rendre l'utilisation des produits simple et intuitive. - la fonction "Auto tune" se charge de régler tous les paramètres de l'analyseur: après avoir effectué un balayage complet de la bande, le signal le plus fort est détecté et les paramètres de fréquence centrale, filtres RBW, VBW, vitesse de balayage et niveau de référence sont ajustés de manière optimale. - l'atténuateur d'entrée et le préamplificateur sont commutés automatiquement en fonction du niveau de signal de référence. - le paramétrage de la fréquence, de l'excursion (span) et de l'amplitude sont très simples. - les marqueurs et la détection crête permettent des mesures très rapides. - 200 configurations et 200 spectres peuvent être mémorisés (méoire interne ou clef USB). - les noms de fichiers peuvent être personnalisés et sont horodatés. - l'affichage LCD TFT couleur très lumineux permet une utilisation plein soleil. Il est aussi doté d'une fonction "noir et blanc" pour les cas extrêmes. Une autonomie de 4 heures La nouvelle batterie lithium permet une utilisation de 4 heures (typiques) en totale autonomie. Le remplacement de la batterie pour des utilisations intensives sur le terrain est rendu très simple et ne nécessite aucun outil. Sur la face avant de l'apparil, une LED indique l'état de la charge: en cours de charge, charge terminée, ou absence de batterie. Le logiciel PC livré avec les analyseurs de spectre BK265XA vous permet d'exploiter les données de vos campagnes de mesures. Au travers de l'interface USB, vous pouvez configurer votre appareil, récupérer vos fichiers enregistrés ainsi que les configurations. Le logiciel permet aussi : - une visualisation temps réel sur l'ordinateur de l'écran de votre isntrument - la capture de courbes avec 1001 points (le double de ce qui est affiché sur l'analyseur), la possibilité de sauvegarder et d'exporter les données au format CSV pour une exploitation dans un tableur (Excel TM par exemple). - l'enregistrement d'écrans (format BMP) ou de les utiliser dans le presse papier - de définir tous les paramètres de l'instrument - de charger dans l'instrument des paramètres de correction spécifiques à une antenne. Impression d'écran sur imprimante USB Avec l'imprimante optionnelle PT2650A (USB), vous pouvez réaliser des copies d'écrans sans passer par un ordinateur. Vous pouvez enregistrer directement sur clef USB des fichiers de configuration et des données au format CSV. Les noms de fichiers sont personnalisables et horodatés. Ils peuvent combiner configuration + mesures. Il est aussi possible avec la fonction "Copy" d'enregistrer des copies d'écran au format BMP. Une utilisation simplifiée avec la fonction "Auto tune" qui règle tous les paramètres pour un affichage optimal. ➩ BK2652A : Analyseur de spectre avec générateur de poursuite Le BK2652A bénéficie de toutes les caractéristiques du BK2650A (bande 50kHz - 3.3GHz) et intègre un générateur de poursuite 5MHz - 3.3GHz permettant la mesure des caractéristiques de transfert des dispositifs RF. Les générateurs de poursuite sont indispensables pour le réglage des filtres, des atténuateurs et pour le calage des étages FI de récepteurs. La fréquence de sortie du générateur est synchronisée avec l'analyseur de spectre. Ainsi, la réponse en fréquence du circuit testé est directement affichée. La fonction "normalize" de l'analyseur permet de s'affranchir des effets des câbles coaxiaux utilisés et ainsi de ne prendre en compte que les caractéristiques du circuit en test. Spécifications du générateur de poursuite Gamme de fréquence 5MHz - 3.3 GHz Niveau de sortie (fixe) -10dBm ±1dBm à 1GHz Platitude ±1.5dB Impédance de sortie 50 ohms Connecteur N Entrée analyseur de spectre Caractériser la réponse en fréquence d'un filtre. La mesure est possible sur la bande 5MHz - 3.3GHz Tracer la courbe de gain d'un amplificateur. La caractéristique en fréquence de dispositifs actifs (amplificateurs, etc…) est immédiate. Mesure de l'adaptation A l'aide dun pont SWR, la courbe "return loss" est tracée et permet de valider l'adaptation d'impédance. Applications Sortie du générateur de poursuite Gamme de fréquence 50 kHz à 3.3 GHz 50 kHz à 8.5 GHz Fréquence centrale Résolution 20kHz, ajustable par la roue codeuse ou le clavier Précision mieux que ± (30+20T) kHz ±1 point @ excursion: 200 kHz à 10 MHz, RBW 3 kHz, 23±5 °C mieux que ± (60+300T) kHz ±1dot @ excursion: 20 MHz à Fmax (3.3 GHz ou 8.5 GHz), RBW 100 kHz, 23±5 °C T: temps de balayage (s) Erreur sur fréquence RBW mieux que ±4 kHz @ 3 kHz, 10 kHz, 30 kHz mieux que 20% de RBW @ RBW: 100 kHz, 300 kHz mieux que 10% de RBW @ RBW: 1 MHz, 3 MHz Excursion en fréquence (Span) Gamme 0 Hz (zéro span) 0 Hz (zéro span) 200 kHz à 2 GHz (séquences 1-2-5 ) 201 kHz à 5 GHz (séquences 1-2-5 ) et 3.3 GHz (full span) et 8.5 GHz (Full span) Précision mieux que ±3% ±1point @ balayage de 0.3s, 23±5 °C Résolution d'affichage 501 points sur l'affichage LCD, 1001 points sur le PC Nbr de points par courbe (501 points affichés sur 1001 mesurés qui peuvent être transféré au PC via l'interface USB.) Résolution de bande passante 3 dB Gamme 3 kHz à 3 MHz (en séquence 1-3) et AUTO Précision ±20% Facteur de forme 1:12 (typique 3 dB : 60 dB) Bande passante Vidéo 100 Hz à 1 MHz (en séquences 1-3) et AUTO Bruit de phase SSB -90 dBc/Hz (typique) @100 kHz d'offset, RBW : 3 kHz, VBW : 100 Hz, balayage: 1 s Raies parasites mieux que -60 dBc Harmoniques <-40 dBc @ ≥ 100 MHz Section amplitude Niveau de référence Gamme +10 à -60 dBm (1dB step) Précision mieux que ± 0.8 dB ± 1 point @ fréquence centrale : 100 MHz, RBW : 3 MHz, VBW : 1 MHz, REF : -15 dBm, 23±5 °C Unités dBm, dBV, dBmV, dBμV, dBμV/m, dBμA/m (dBμV/m et dBμA/m sont utilisés pour les fonctions de mesure uniquement) Niveau moyen de bruit -127 dBm (typique) @ CF : 1 GHz, RBW : 3 kHz, VBW : 100 Hz, Niveau de référence < - 40 dBm ( preampli ON - automatique) Réponse en fréquence mieux que ±2.0 dB ± 1 point @50 kHz à 100 MHz mieux que ±1.0 dB ± 1 point @100 MHz à Fmax (3.3 GHz ou 8.5 GHz) Impédance d'entrée 50 ohms TOS d'entrée < 2.0 Atténuateur Gamme d'atténuation 0 à 25 dB (par pas de 1 dB), couplé avec le niveau de référence Erreur de commutation ±0.6 dB @100 MHz Erreur de commutation RBW ±0.6 dB Résolution d'affichage (verticale) 381 points pour 10 divisions Echelles Echelles 10 dB/div, 5 dB/div, 2 dB/div Précision ±(0.2 dB+1point)/2 dB ±(0.4 dB+1point)/5 dB ±(0.8 dB+1point)/10 dB ±(1.8 dB+1point)/83 dB Niveau maximum admissible +27 dBm max. (signal CW - porteuse pure), 25 VDC Section balayage Vitesse de balayage Gamme 10 ms à 30 s et AUTO 10 ms à 30 s et AUTO (en séquences 1-3) @ excursion en fréquence : 0 to 2 GHz @ excursion en fréquence : 0 to 2 GHz 30 ms à 30 s et AUTO 30 ms à 30 s et AUTO @ excursion en fréquence : full span @ excursion en fréquence : 5GHz et full span Précision Mieux que ±0.1% ±1point Mieux que ±0.1% ±1point @ excursion : 0 à 2 GHz @ excursion : 0 à 5 GHz mieux que ±1.5% ±1point @ full span Mieux que ±2.5% ±1point @ full span Spécifications BK2650A - BK2652A BK2658A SSeeffrraamm BK2650A, BK2652A, BK2658A Déclenchement Modes AUTO (uniquement en span zéro) Source de déclenchement Interne et externe Déclenchement externe Niveau 1 à 10 Vc-c Gamme de fréquence DC à 5 MHz Couplage DC Seuil de déclenchement 0.56 V(fixe) Impédance d'entrée environ 10 kΩ // 15 pF (max.) Niveau maximum d'entrée ±50 V(DC+AC peak) Connecteur SMA(J) Détection Peak positif, peak négatif, Echantillon Fonctions Marqueurs - Mesures NORM : affiche la fréquence (8 digits max) et le niveau (4 digits max) du marqueur DELTA : affiche la différence de fréquence et de niveau entre les 2 marqueurs Recherche de Peak NORM : cherche le peak dans les 10div (gamme totale de fréquence). Ce mode est compatible avec la fonction de reherche du peak suivant, jusqu'à 10). ZONE: recherche du peak dans une zone définie par sa fréquence centrale et sa largeur Calculs NORM, MAX HOLD, MIN HOLD, AVERAGE (moyenne), OVER WRITE (ré-écriture) MAX/MIN HOLD: 2 à 1024 AVERAGE (moyenne) 2 à 256 Mesures Puissance d'un canal, puissance perdue dans le canal adjacent, bande occupée, Champ électrique (avec antenne optionnelle), champ magnétique (avec antenne optionnelle). Auto tuning Fait un balayage complet de la bande, détecte le signal d'amplitude maximum et l'affiche au centre de l'écran. Ajuste automatiquement le niveau de référence, les filtres RBW, VBW et la vitesse de balayage. Sauvegarde/Rappel Sauvegarde 200 courbes de spectre et 200 configurations Rappel Rappel des spectres et de configurations mémorisés Spécifications générales Connecteur d'entrée Type N femelle Interfaces USB Protocole USB version 1.1 (qui fonctionne avec les périphériques USB2.0) Type de connecteur type B Vitesse de transfert 12 Mbps Copie d'écran Avec imprimante USB optionnelle connectée au port A (Host) Connecteur USB Host type A Affichage Afficheur LCD couleur, 5.7 pouces, TFT Rétroéclairage à LED Nombre de points 640(H) x 480(V) points Alimentation Adaptateur secteur 100V à 240 VAC / 50-60Hz Entrée DC 9 VDC/2.6 A Batterie Li-Ion, 7.4 V/5000 mAh (référence: MB400) Charge charge appareil arrêté L'état de la charge est indiqué par LED bicolores Indication de charge bargraph 5 niveaux (à l'écran) Conditions d'environnement Température de fonctionnement 0 à +50° C (spécifications données à 23±10 °C, appareil hors sacoche) Humidité < 40 °C/80 %RH (garanti à 33 °C/70 %RH, appareil hors sacoche) Température de stockage -20 à +60 °C, HR<70 % à 60°C Dimensions 162(L) x 71(H) x 265(l) mm (hors protections et béquille) Masse environ 1.8 kg (avec batterie) Accessoires Livrés avec : Manuel d'utilisation, adaptateur secteur MA400, sacoche LC2650A, sacoche pour accessoires logiciel PC et câble USB, batterie Lithium-Ion MB400 En option : Antennes dipoles M401 – M406 et AN307, sonde champ magnétique PR 26M, imprimante USB PT2650A et rouleaux de papier thermique PX2650A (lot de 10) Spécifications BK2650A - BK2652A - BK2658A SSeeffrraamm BK2650A, BK2652A, BK2658A Spécifications susceptibles d’être modifiées sans préavis - FT BK265XA F00 Partenaire Distributeur 32, rue Edouard Martel • B.P. 55 • 42009 - St Etienne cedex 2 Fax. +33 (0).4.77.57.23.23 Web : www.sefram.fr • e-mail : sales@sefram.fr Référence: T005 32 776 70 Apex Tool Group S.N.C. 25 Av. Maurice Chevalier B.P. 46 77832 Ozoir-la-Ferrière Cedex France Téléphone: +33 (0) 1.64.43.22.00 Telefax: +33 (0) 1.64.43.21.62 Email: info@weller-tools.com Web: www.weller-tools.com Haute technologie pour un soudage de qualité De la puissance avec la station de soudage WSD 121 et le fer à souder WP 120 Puissance sur demande. La technologie Weller détecte automatiquement le besoin thermique de chaque joint de soudure et assure une grande précision de température. Pas besoin de réétalonnage (certificat sur demande). Fer à souder Weller WP 120 Outil polyvalent. Il est parfait pour des soudures standard ou des soudures demandant beaucoup plus de puissance comme pour des circuits multi couches ou pour du blindage. Toute la puissance disponible sera alors transférée pour avoir la température exigée. Station de soudage WSD 121 Très bon rapport qualité prix. Le coût de la station et les consommables sont très bas. Très bonne fiabilité Durée de vie très longue. Grâce à sa conception, l’élément chauffant résistera à plusieurs milliers de cycles de chauffe et de refroidissement. Pannes série XT Fourreau avec ressort Fer WP 120 Panne à forte réserve d’énergie Forme pyramidale et très bonne surface de contact Elément chauffant en argent Composition du WSD 121: Bloc d’alimentation, fer à souder WP 120 et support fer. Puissance élevée (>250W) Faible puissance (75 - 250W) Avantages Avantages Montage facile et rapide avec peu de composants et d'espace. Le tableau de contrôle présente : 40% de réduction des coûts 50% de réduction de surface PCB 40% de réduction du nombre de composants La réduction de courant crête (vs DCM) permet 16% de réduction de surface PCB 10% d'augmentation de la densité de puissance 40% de réduction des coûts de filtrage d'EMI (référence adaptateur 120W) Facteur de puissance 0.999 Distorsion harmonique totale de 3% Nombre de composants minimum pour montage rapide Nombre de composants minimum pour montage rapide Espace carte minimum pour haute densité de puissance Espace carte minimum pour haute densité de puissance Conception/conformité EMI facilitée Conception/conformité EMI facilitée De taille 50% inférieure aux circuits PFC CCM Configuration PCB facile Protection contre surtension en sortie dédiée et programmable (Protection Boucle ouverte) rapide transmission courant crête 1.5A Commutation rapide Commutation rapide Heure fin min. 150-350ns sur la gamme de fréquences Grande efficacité Grande efficacité Limite maximale cycle de fonctionnement : 98% Mode veille' de l'alimentation micro initié par utilisateur Conforme basse consommation en mode marche/standby : Conforme basse consommation en mode marche/standby : Mise sous tension Micro (<200μA) 1W, Blue Angel, Energy Star 1W, Blue Angel, Energy Star Un seul transformateur sens de courant requis ( 2 requis pour les designs CCM conventionnels) Peut servir pour des montages haute efficacité Boost sans shuntage Vcc sous arrêt tension blocage interne de la transmission 13V Sécurité verrouillage et protection ESD Protection système Protection système Démarrage 'Soft' Design robuste Design robuste Protection contre court-circuit et surtension en sortie Excellente réaction transitoire sans alimentation tension avant Excellente réaction transitoire sans alimentation tension avant Limite de courant crête cycle par cycle Fréquence de commutation fixe, programmable (50-200kHz) Un seul dispositif adapté à toute une gamme d'applications Un seul dispositif adapté à toute une gamme d'applications Conforme à la législation PFC pour le Japon, l'Europe et la Chine Haute fiabilité, nombre de composants réduit Contrôle du Mode de courant crête Aucun sens de tension ligne AC requis Haute fiabilité, nombre de composants réduit Conforme à la législation PFC pour le Japon, l'Europe et la Chine Boîtier SO8 Caractéristiques μPFC avec système OCC (Contrôle Un Cycle) exclusif à IR Montage facile et rapide avec peu de composants et d'espace Fonctionnement en mode CCM (mode de conduction continu) Puissance élevée, haute performance A Premier Farnell Company 18 Amplificateurs audio Classe D Une révolution silencieuse Classe A Lorsque l’efficacité n’est pas un critère primordial, comme pour la plupart des petits amplificateurs linéaires, la conception utilisée est de type classe A, cela signifie que les étages de sortie sont toujours dans la zone de conduction. Les amplificateurs classe A sont en général plus linéaires et moins complexes que d’autres modèles, mais peu efficaces. Ce type d’amplificateur est le plus souvent utilisé pour les petits signaux ou pour les applications à faible puissance (comme des écouteurs). Classe B En classe B, il existe deux étages de sortie (ou ensembles de circuits de sortie), chacun utilisant une alternance d’une amplitude de 180° ou la moitié du cycle du signal d’entrée. Classe AB Les amplificateurs de classe AB sont un compromis entre classe A et B, améliorant la linéarité en sortie pour les petits signaux, avec une modulation d’amplitude allant de 180° à plus, selon la conception de l’amplificateur. On les trouve généralement dans les amplificateurs basse fréquence (audio et hi-fi) en raison de leur rendement relativement élevé, ou dans d’autres applications exigeant à la fois linéarité et rendement (téléphones mobiles, transmetteurs TV, etc.). Classe C Appréciée pour les amplificateurs RF haute puissance, la classe C se définit par une variation de phase du signal d’entrée inférieure à 180°. La linéarité n’est pas très bonne, mais cela n’a aucune importance pour de simples amplificateurs de puissance. Le signal reprend une forme presque sinusoïdale via un circuit accordé et le rendement est très supérieur à celui des amplificateurs de classes A, AB ou B. Classe D Les amplificateurs de classe D utilisent la commutation pour obtenir un rendement énergétique élevé (plus de 90% dans les modèles récents). En permettant à chaque étages de sortie d’être totalement sous ou hors tension, les pertes sont minimisées. Une méthode simple, comme la modulation de largeur d’impulsion, est parfois encore utilisée. Cependant, les amplificateurs de commutation haute performance utilisent des techniques numériques, comme la modulation sigma-delta, pour obtenir de meilleures performances. D’abord utilisés spécifiquement avec les haut-parleurs de graves, pour leur bande passante limitée et leur distorsion relativement élevée, l’évolution des circuits semiconducteurs a permis le développement d’une gamme complète d’amplificateurs audio HIFI en classe D, avec un rapport signal/bruit et des niveaux de distorsion similaires à leurs homologues linéaires. La classe D offre de gros avantages en termes de gain d’espace, d’efficacité énergétique et de dissipation thermique. Depuis qu’une gamme complète d’amplificateurs classe D, offrant tous les niveaux de puissance, est disponible chez Texas Instruments, la haute fidélité et la fiabilité ne constituent plus un problème comparé aux débuts de cette technologie. Avant, les interférences EMI dans les amplificateurs classe D étaient parfois considérées comme un facteur critique pour certaines applications. Aujourd’hui, on trouve ce type d’amplificateurs dans toutes les applications dites « critiques », comme les combinés portables, les systèmes automobile et les avions. Egalement fondamental à l’évolution commerciale de cette technologie, l’apparition de marchés émergents comme les récepteurs AV multicanaux, les téléviseurs LCD et Plasma, ainsi que tous les équipements portables audio/vidéo fonctionnant sur batterie, les téléphones mobiles, les systèmes de navigation par satellite, les équipements médicaux tel que prothèses auditives et enfin, et non des moindres, les systèmes audio automobile haut de gamme. Tous ces marchés nécessitent un petit facteur de forme pour être adaptés dans des boîtiers miniatures mais élégants. Leur rendement très efficace, permet une bonne gestion thermique, d’avoir une alimentation par batterie et un refroidissement pour les applications où la température ambiante est élevée. Dans tous ces domaines, la classe D bénéficie d’un avantage très évident sur les autres solutions linéaires présentes sur le marché. Cette technologie offre un rendement proche de 100% ce qui constitue un atout de plus en plus recherché pour les prochaines générations d’applications qui souhaite répondre à la tendance mondiale d’économiser l’énergie. Texas Instruments (TI) est reconnu par l’industrie comme un fabricant majeur de chipsets (ensembles de circuits intégrés) classe D, qui propose des circuits avec des niveaux de puissance variés et se spécialise dans le secteur de l’électronique grand public (téléviseurs à écran plat, périphériques informatiques, équipement portable et systèmes audio Automobile et amplificateurs Depuis près d’un siècle, les amplificateurs linéaires dominent le marché. Depuis l’apparition des amplis à tubes, puis l’intégration des premiers transistors à la fin des années 1950, le principe de base de leur conception n’a pas beaucoup changé et même de nos jours certains utilisateurs, essentiellement des musiciens, préfèrent encore la sonorité des bons vieux amplis à tubes en raison de la qualité de leurs harmoniques et des spécificités de saturation douce. Néanmoins, les limites de l’architecture d’un amplificateur linéaire traditionnel et sa technologie de base continuent à contribuer au succès et à l’évolution des amplificateurs. Article présenté par Texas Instruments 19 de puissance externes). Pour répondre à ces marchés, TI a développé plusieurs familles d’amplificateurs classe D avec des entrées analogiques et numériques. Pour le marché des appareils portables, la famille TPA2xxx, propose un amplificateur à entrée analogique qui domine le secteur en termes de performance audio, rendement, taille et coût de la solution. Des versions mono et stéréo sont disponibles, avec des puissances de 1W à 2,75W et une alimentation allant de 1,8V à 5,5V. Au coeur du marché des téléviseurs à écran plat, la famille TPA3xxx supporte tous les niveaux de puissance (de 5W à 40W), options à entrée analogique et numérique, terminaison simple et sortie « à charge montée en pont » (BTL – bridge-tied load). Pour le marché des récepteurs AV, TI offre une technologie d’amplificateur audio à entrée PurePass Digital™ exclusive, d’une puissance de 10 à 300W par voie. Le TAS5261 monopuce offre en classe D le niveau de puissance le plus élevé et délivre 110dB, un rapport Signal/bruit pour une netteté acoustique ultime dans les applications audio domestiques. Il envoie 300W dans une enceinte de 4 Ohms (10% THD+N) et peut restituer 125W en 8 Ohms, à moins de 0,09% THD+N avec 95% de rendement. Membre de la famille des amplificateurs de puissance PurePath Digital™ de TI, il offre une capacité de gestion de puissance et de courant incomparable. Les nouveaux amplificateurs numériques pour l’automobile de TI sont des amplificateurs audio numériques de classe D, à 4 voies, ultra efficaces. Avec des niveaux de puissance modérés, les amplificateurs de classe A/B fournissent, au mieux, un rendement de 40 à 50% (25% dans certains cas). Avec les amplificateurs TAS54x4, TI offre 90% de rendement énergétique à des niveaux d’écoute normaux pour les systèmes audio sur le segment automobile. Comparativement, deux amplificateurs TAS54x4 peuvent fournir huit voies tout en générant moins de chaleur qu’un système basé sur 4 voies en classe A/B, permettant une toute nouvelle catégorie de systèmes audio 8 voies économiques, qui sont plus légers, plus petits et moins gourmands en énergie que les systèmes existants. De plus, les nouveaux amplificateurs numériques de TI peuvent aussi être utilisés avec des enceintes 2 Ohms pour offrir deux fois la puissance de sortie qu’un amplificateur AB dans des enceintes 4 Ohms tout en générant moins de chaleur. Electrometer/High Resistance Meter Simplifies measuring high resistances and the resistivity of insulating materials Simplifies measuring high resistances and the resistivity of insulating materials LOW LEVEL MEASURE & SOURCE A Greater Measure of Confidence www.keithley.com 1.888.KEITHLEY (U.S. only) 6517B Electrometer/High Resistance Meter produces a highly repeatable, accurate measurement of resistance (or resistivity) by the seventh reversal on most materials (i.e., by discarding the first three readings). For example, a 1mm-thick sample of 1014W-cm material can be measured with 0.3% repeatability in the Model 8009 test fixture, provided the background current changes less than 200fA over a 15-second period. Simple DMM-like Operation The Model 6517B is designed for easy, DMM-like operation via the front panel, with single-button control of important functions such as resistance measurement. It can also be controlled via a built-in IEEE-488 interface, which makes it possible to program all functions over the bus through a computer controller. High Accuracy High Resistance Measurements The Model 6517B offers a number of features and capabilities that help ensure the accuracy of high resistance measurement applications. For example, the built-in voltage source simplifies determining the relationship between an insulator’s resistivity and the level of source voltage used. It is well suited for capacitor leakage and insulation resistance measurements, tests of the surface insulation resistance of printed circuit boards, voltage coefficient testing of resistors, and diode leakage characterization. Temperature and Humidity Stamping Humidity and temperature can influence the resistivity values of materials significantly. To help you make accurate comparisons of readings acquired under varying conditions, the Model 6517B offers a built-in type K thermocouple and an optional Model 6517-RH Relative Humidity Probe. A built-in data storage buffer allows recording and recalling readings stamped with the time, temperature, and relative humidity at which they were acquired. Accessories Extend Measurement Capabilities A variety of optional accessories can be used to extend the Model 6517B’s applications and enhance its performance. Scanner Cards. Two scanner cards are available to simplify scanning multiple signals. Either card can be easily inserted in the option slot of the instrument’s back panel. The Model 6521 Scanner Card offers ten channels of low-level current scanning. The Model 6522 Scanner Card provides ten channels of high impedance voltage switching or low current switching. Test Fixture. The Model 8009 Resistivity Chamber is a guarded test fixture for measuring volume and surface resistivities of sample materials. It has stainless- steel electrodes built to ASTM standards. The fixture’s electrode dimensions are pre-programmed into the Model 6517B, so there’s no need to calculate those values then enter them manually. This accessory is designed to protect you from contact with potentially hazardous voltages —opening the lid of the chamber automatically turns off the Model 6517B’s voltage source. Applications The Model 6517B is well suited for low current and high impedance voltage, resistance, and charge measurements in areas of research such as physics, optics, and materials science. Its extremely low voltage burden makes it particularly appropriate for use in solar cell applications, and its built-in voltage source and low current sensitivity make it an excellent solution for high resistance measurements of nanomaterials such as polymer based nanowires. Its high speed and ease of use also make it an excellent choice for quality control, product engineering, and production test applications involving leakage, breakdown, and resistance testing. Volume and surface resistivity measurements on nonconductive materials are particularly enhanced by the Model 6517B’s voltage reversal method. The Model 6517B is also well suited for electrochemistry applications such as ion selective electrode and pH measurements, conductivity cells, and potentiometry. Model 6517B Enhancements The Model 6517B is an updated version, replacing the earlier Model 6517A, which was introduced in 1996. Software applications created for the Model 6517A using SCPI commands can run without modifications on the Model 6517B. However, the Model 6517B does offer some useful enhancements to the earlier design. Its internal battery-backed memory buffer can now store up to 50,000 readings, allowing users to log test results for longer periods and to store more data associated with those readings. The new model also provides faster reading rates to the internal buffer (up to 425 readings/second) and to external memory via the IEEE bus (up to 400 readings/second). Several connector modifications have been incorporated to address modern connectivity and safety requirements. Ordering Information 6517B Electrometer/High Resistance Meter Accessories Supplied 237-AL G-2 Low Noise Triax Cable, 3-slot Triax to Alligator Clips, 2m (6.6 ft) 8607 Safety High Voltage Dual Test Leads 6517-TP Thermocouple Bead Probe CS-1305 Interlock Connector ACCESSOR IES AVAILABL E CABL ES 6517B-ILC-3 Interlock Cable 7007-1 Shielded IEEE-488 Cable, 1m (3.2 ft) 7007-2 Shielded IEEE-488 Cable, 2m (6.5 ft) 7009-5 RS-232 Cable 7078-TRX-3 Low Noise Triax Cable, 3-Slot Triax Connectors, 0.9m (3 ft) 7078-TRX-10 Low Noise Triax Cable, 3-Slot Triax Connectors, 3m (10 ft) 7078-TRX-20 Low Noise Triax Cable, 3-Slot Triax Connectors, 6m (20 ft) 8501-1 Trigger Link Cable, 1m (3.3 ft) 8501-2 Trigger Link Cable, 2m (6.6 ft) 8503 Trigger Link Cable to 2 male BNCs, 1m (3.3 ft) 8607 1kV Source Banana Cables PROBES 6517-RH Humidity Probe with Extension Cable 6517-TP Temperature Bead Probe (included with 6517B) TEST FIXTUR E 8009 Resistivity Test Fixture Othe r CS-1305 Interlock Connector ADAPTERS 237-BNC-TRX Male BNC to 3-Lug Female Triax Adapter 237-TRX-NG Triax Male-Female Adapter with Guard Disconnected 237-TRX-T 3-Slot Male Triax to Dual 3-Lug Female Triax Tee Adapter 237-TRX-TBC 3-Lug Female Triax Bulkhead Connector (1.1kV rated) 7078-TRX-BNC 3-Slot Male Triax to BNC Adapter 7078-TRX-GND 3-Slot Male Triax to BNC Adapter with guard removed 7078-TRX-TBC 3-Lug Female Triax Bulkhead Connector with Cap RA CK MOUNT KITS 4288-1 Single Fixed Rack Mounting Kit 4288-2 Dual Fixed Rack Mounting Kit Sc anne r Cards 6521 Low Current Scanner Card 6522 Voltage/Low Current Scanner Card GPIB Interfaces KPCI-488LPA IEEE-488 Interface/Controller for the PCI Bus KUSB-488B IEEE-488 USB-to-GPIB Interface Adapter Simplifies measuring high resistances and the resistivity of insulating materials LOW LEVEL MEASURE & SOURCE www.keithley.com 1.888.KEITHLEY (U.S. only) A Greater Measure of Confidence 6517B Electrometer/High Resistance Meter VOL TS Acc uracy Tempe rature (1 Year)1 Coefficient 5½-Digit 18°–28°C 0°–18°C & 28°–50°C Range Re soluti on ±(%rdg+counts) ±(%rdg+counts)/°C 2 V 10 μV 0.025 + 4 0.003 + 2 20 V 100 μV 0.025 + 3 0.002 + 1 200 V 1 mV 0.06 + 3 0.002 + 1 NMRR: 2V and 20V ranges >60dB, 200V range >55dB. 50Hz or 60Hz2. CMRR: >120dB at DC, 50Hz or 60Hz. INPUT IMPEDANCE: >200TW in parallel with 20pF, <2pF guarded (1MW with zero check on). SMALL SIGNAL BANDWIDTH AT PREAMP OUTPUT: Typically 100kHz (–3dB). Note s 1. When properly zeroed, 5½-digit, 1 PLC (power line cycle), median filter on, digital filter = 10 readings. 2. Line sync on. AMPS Acc uracy Tempe rature (1 Year)1 Coefficient 5½-Digit 18°–28°C 0°–18°C & 28°–50°C Range Re soluti on ±(%rdg+counts) ±(%rdg+counts)/°C 20 pA 100 aA 2 1 + 30 0.1 + 5 200 pA 1 fA 2 1 + 5 0.1 + 1 2 nA 10 fA 0.2 + 30 0.1 + 2 20 nA 100 fA 0.2 + 5 0.03 + 1 200 nA 1 pA 0.2 + 5 0.03 + 1 2 μA 10 pA 0.1 + 10 0.005 + 2 20 μA 100 pA 0.1 + 5 0.005 + 1 200 μA 1 nA 0.1 + 5 0.005 + 1 2 mA 10 nA 0.1 + 10 0.008 + 2 20 mA 100 nA 0.1 + 5 0.008 + 1 INPUT BIAS CURRENT: <3fA at Tcal . Temperature coefficient = 0.5fA/°C, 20pA range. INPUT BIAS CURRENT NOISE: <750aA p-p (capped input), 0.1Hz to 10Hz bandwidth, damping on. Digital filter = 40 readings, 20pA range. INPUT VOLTAGE BURDEN at Tcal ±1°C: <20μV on 20pA, 2nA, 20nA, 2μA, and 20μA ranges. <100μV on 200pA, 200nA, and 200μA ranges. <2mV on 2mA range. <5mV on 20mA range. TEMPERATURE COEFFICIENT OF INPUT VOLTAGE BURDEN: <10μV/°C on pA, nA, and μA ranges. PREAMP SETTLING TIME (to 10% of final value) Typical: 0.5sec (damping off) 2.0 sec (damping on) on pA ranges. 15msec on nA ranges damping off, 1msec on μA ranges damping off. 500μsec on mA ranges damping off. NMRR: >60dB on all ranges at 50Hz or 60Hz3. Note s 1. When properly zeroed, 5½-digit, 1PLC (power line cycle), median filter on, digital filter = 10 readings. 2. aA = 10–18A, fA = 10–15A. 3. Line sync on. OHMS (Normal Method) Tempe rature Acc uracy 1 Coefficient (10–100% Range) (10–100% Range) 5½-Digit 18°–28°C (1 Year) 0°–18°C & 28°–50°C Auto Amp s Range Re soluti on ±(% rdg+counts) ±(% rdg+counts) V Source R ange 2 MW 10 W 0.125 + 1 0.01 + 1 40 V 200 μA 20 MW 100 W 0.125 + 1 0.01 + 1 40 V 20 μA 200 MW 1 kW 0.15 + 1 0.015 + 1 40 V 2 μA 2 GW 10 kW 0.225 + 1 0.035 + 1 40 V 200 nA 20 GW 100 kW 0.225 + 1 0.035 + 1 40 V 20 nA 200 GW 1 MW 0.35 + 1 0.110 + 1 40 V 2 nA 2 TW 10 MW 0.35 + 1 0.110 + 1 400 V 2 nA 20 TW 100 MW 1.025 + 1 0.105 + 1 400 V 200 pA 200 TW 1 GW 1.15 + 1 0.125 + 1 400 V 20 pA Note s 1. Specifications are for auto V-source ohms, when properly zeroed, 5½-digit, 1PLC, median filter on, digital filter = 10 readings. If user selectable voltage is required, use manual mode. Manual mode displays resistance (up to 1018W) calculated from measured current. Accuracy is equal to accuracy of V-source plus accuracy of selected Amps range. PREAMP SETTLING TIME: Add voltage source settling time to preamp settling time in Amps specification. Ranges over 20GW require additional settling based on the characteristics of the load. OHMS (Alte rnating Polarity Meth od) The alternating polarity sequence compensates for the background (offset) currents of the material or device under test. Maximum tolerable offset up to full scale of the current range used. Using Keithley 8009 fixture repeatabilit y: DIBG × R/VALT + 0.1% (1σ) (instrument temperature constant ±1°C). ACCURACY: (VSRCErr + IMEASErr × R)/VALT where: DIBG is a measured, typical background current noise from the sample and fixture. VALT is the alternating polarity voltage used. VSRCErr is the accuracy (in volts) of the voltage source using VALT as the setting. IMEASErr is the accuracy (in amps) of the ammeter using VALT /R as the reading. VOL TAGE SOUR CE Tempe rature Acc uracy (1 Year) Coefficient 5½-Digit 18°–28°C 0°–18°C & 28°–50°C Range Re soluti on ±(% setting + offset) ±(% setting+offset)/°C 100 V 5 mV 0.15 + 10 mV 0.005 + 1 mV 1000 V 50 mV 0.15 + 100 mV 0.005 + 10 mV MAXIMUM OUTPUT CURRENT: 100V Range: ±10mA, hardware short circuit protection at <14mA. 1000V Range: ±1mA, hardware short circuit protection at <1.4mA. SETTLING TIME: 100V Range: <8ms to rated accuracy. 1000V Range: <50ms to rated accuracy. NOISE (typical): 100V Range: <2.6mV rms. 1000V Range: <2.9mV rms. Model 6517B specifications Model 6517B specifications LOW LEVEL MEASURE & SOURCE A Greater Measure of Confidence www.keithley.com 1.888.KEITHLEY (U.S. only) 6517B Electrometer/High Resistance Meter IEEE-488 BUS IMPLEMENTATION IMPLEMENTATION: SCPI (IEEE-488.2, SCPI-1999.0). TRIGGER TO READING DONE: 150ms typical, with external trigger. RS-232 IMPLEMENTATION: Supports: SCPI 1991.0. Baud Rates: 300, 600, 1200, 2400, 4800, 9600, 19.2k, 38.4k, 57.6k, and 115.2k. Flow Control : None, Xon/Xoff. Connector : DB-9 TXD/RXD/GND. GENERAL Overrange Indication : Display reads “OVERFLOW” for readings >105% of range. The display reads “OUT OF LIMIT” for excesive overrange conditions. RANGING: Automatic or manual. CONVERSION TIME: Selectable 0.01PLC to 10PLC. MAXIMUM INPUT: 250V peak, DC to 60Hz sine wave; 10sec per minute maximum on mA ranges. MAXIMUM COMMON MODE VOLTAGE (DC to 60Hz sine wave): Electrometer, 500V peak; V Source, 750V peak. ISOLATION (Meter COMMON to chassis): >1010W, <500pF. INPUT CONNECTOR: Three lug triaxial on rear panel. 2V ANALOG OUTPUT: 2V for full range input. Non-inverting in Volts mode, inverting when measuring Amps, Ohms, or Coulombs. Output impedance 10kW. PREAMP OUTPUT: Provides a guard output for Volts measurements. Can be used as an inverting output or with external feedback in Amps and Coulombs modes. EXTERNAL TRIGGER: TTL compatible External Trigger and Electrometer Complete. GUARD: Switchable voltage guard available. DIGITAL I/O AND TRIGGER LINE: Available, see manual for usage. EMC: Conforms to European Union Directive 89/336/EEC, EN 61326-1. Safet y: Conforms to European Union Directive 73/23/EEC, EN 61010-1. READING STORAGE: 50,000. READING RATEs: To Internal Buffer: 425 readings/second1. To IEEE-488 Bus: 400 readings/second1, 2. Bus Transfer: 3300 readings/second2. 1. 0.01PLC, digital filters off, front panel off, temperature + RH off, Line Sync off. 2. Binary transfer mode. DIGITAL FILTER: Median and averaging. ENVIRONMENT: Operating: 0°–50°C; relative humidity 70% non-condensing, up to 35°C. Storage: –25° to +65°C. Altitude : Maximum 2000 meters above sea level per EN 61010-1. WARM-UP: 1 hour to rated accuracy (see manual for recommended procedure). POWER: User selectable 100, 120, 220, 240VAC ±10%; 50/60Hz, 100VA max. PHYSICAL: Case Dimensions: 90mm high × 214mm wide × 369mm deep (3½ in. × 8½ in. × 14½ in.). Working Dimensions: From front of case to rear including power cord and IEEE-488 connector: 15.5 inches. Net Weight: 5.4kg (11.8 lbs.). Shipping Weight: 6.9kg (15.11 lbs.). COULO MBS Acc uracy Tempe rature (1 Year)1, 2 Coefficient 5½-Digit 18°–28°C 0°–18°C & 28°–50°C Range Re soluti on ±(%rdg+counts) ±(%rdg+counts)/°C 2 nC 10 fC 0.4 + 5 0.04 + 3 20 nC 100 fC 0.4 + 5 0.04 + 1 200 nC 1 pC 0.4 + 5 0.04 + 1 2 μC 10 pC 0.4 + 5 0.04 + 1 Note s 1. Specifications apply immediately after charge acquisition. Add |QAV| (4fA + _____ ) TA RC where TA = period of time in seconds between the coulombs zero and measurement and QAV = average charge measured over TA, and RC = 300,000 typical. 2. When properly zeroed, 5½-digit, 1PLC (power line cycle), median filter on, digital filter = 10 readings. INPUT BIAS CURRENT: <4fA at Tcal . Temperature coefficient = 0.5fA/°C, 2nC range. TEMPERA TUR E (Thermocouple) Acc uracy (1 Year)1 The rmocouple 18°–28°C Type R ange ±(% rdg + °C) K –25°C to 150°C ±(0.3% + 1.5°C) Note s 1. Excluding probe errors, Tcal ± 5°C, 1 PLC integration time. HUMIDITY Acc uracy (1 Year)1 Range 18°–28°C, ±(% rdg + % RH) 0–100% ±(0.3% +0.5) Note s 1. Humidity probe accuracy must be added. This is ±3% RH for Model 6517-RH, up to 65°C probe environment, not to exceed 85°C. Service s Av ailable 6517B-3Y-EW 1-year factory warranty extended to 3 years from date of shipment C/6517B-3Y-ISO 3 (ISO-17025 accredited) calibrations within 3 years of purchase* *Not available in all countries SMBJ Transil™ Features ■ Peak pulse power: – 600 W (10/1000 μs) – 4 kW (8/20 μs) ■ Stand off voltage range: from 5 V to 188 V ■ Unidirectional and bidirectional types ■ Low leakage current: – 0.2 μA at 25 °C – 1 μA at 85 °C ■ Operating Tj max: 150 °C ■ High power capability at Tj max: – 515 W (10/1000 μs) ■ JEDEC registered package outline Complies with the following standards ■ IEC 61000-4-2 level 4: – 15 kV (air discharge) – 8 kV (contact discharge) ■ IEC 61000-4-5 ■ MIL STD 883G, method 3015-7 Class 3B: – 25 kV HBM (human body model) ■ Resin meets UL 94, V0 ■ MIL-STD-750, method 2026 soldererability ■ EIA STD RS-481 and IEC 60286-3 packing ■ IPC 7531 footprint Description The SMBJ Transil series has been designed to protect sensitive equipment against electrostatic discharges according to IEC 61000-4-2, and MIL STD 883, method 3015, and electrical over stress according to IEC 61000-4-4 and 5. These devices are more generally used against surges below 600 W (10/1000 μs). Planar technology makes these devices suitable for high-end equipment and SMPS where low leakage current and high junction temperature are required to provide reliability and stability over time. SMBJ are packaged in SMB (SMB footprint in accordance with IPC 7531 standard). TM: Transil is a trademark of STMicroelectronics K A Unidirectional Bidirectional SMB (JEDEC DO-214AA) www.st.com Characteristics SMBJ 2/10 Doc ID 5616 Rev 10 1 Characteristics Figure 1. Electrical characteristics - definitions Figure 2. Pulse definition for electrical characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit PPP Peak pulse power dissipation (1) Tj initial = Tamb 600 W Tstg Storage temperature range -65 to +150 °C Tj Operating junction temperature range -55 to +150 °C TL Maximum lead temperature for soldering during 10 s. 260 °C 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Table 2. Thermal resistances Symbol Parameter Value Unit Rth(j-l) Junction to leads 20 °C/W Rth(j-a) Junction to ambient on recommended pad layout 100 °C/W VCLVBR VRM IRM IR IPP V I IRM IR IPP VRMVBR VCL V CLVBR VRM IRM IR IPP V I IF VF Unidirectional Bidirectional Symbol Parameter V Stand-off voltage V Breakdown voltage V Clamping voltage I Leakage current @ V I Peak pulse current T Voltage temperature coefficient V Forward voltage drop R Dynamic resistance RM BR CL RM RM PP F D α Repetitive pulse current tr = rise time (μs) tp = pulse duration time (μs) tp t tr % Ipp 100 50 0 SMBJ Characteristics Doc ID 5616 Rev 10 3/10 Table 3. Electrical characteristics - parameter values (Tamb = 25 °C) Order code IRM max@VRM VBR @IR (1) VCL @IPP 10/1000 μs RD (2) 10/1000 μs VCL @IPP 8/20 μs RD (2) 8/20 μs αT (3) 25 °C 85 °C min typ max max max μA V V mA V A(4) Ω V A(4) Ω 10-4/ °C SMBJ5.0A/CA 20 50 5.0 6.4 6.74 10 9.2 68 0.031 13.4 298 0.021 5.7 SMBJ6.0A/CA 20 50 6.0 6.7 7.05 10 10.3 61 0.048 13.7 290 0.022 5.9 SMBJ6.5A/CA 20 50 6.5 7.2 7.58 10 11.2 56 0.058 14.5 276 0.024 6.1 SMBJ8.5A/CA 20 50 8.5 9.4 9.9 1 14.4 41.7 0.096 19.5 205 0.044 7.3 SMBJ10A/CA 0.2 1 10 11.1 11.7 1 17 37 0.127 21.7 184 0.051 7.8 SMBJ12A/CA 0.2 1 12 13.3 14 1 19.9 31 0.168 25.3 157 0.068 8.3 SMBJ13A/CA 0.2 1 13 14.4 15.2 1 21.5 29 0.191 27.2 147 0.076 8.4 SMBJ15A/CA 0.2 1 15 16.7 17.6 1 24.4 25.1 0.236 32.5 123 0.114 8.8 SMBJ16A/CA 0.2 1 16 17.8 18.7 1 26 23.1 0.276 34.4 116 0.127 8.8 SMBJ18A/CA 0.2 1 18 20.0 21.1 1 29.2 21.5 0.328 39.3 102 0.168 9.2 SMBJ20A/CA 0.2 1 20 22.2 23.4 1 32.4 19.4 0.404 42.8 93 0.196 9.4 SMBJ22A/CA 0.2 1 22 24.4 25.7 1 35.5 17.7 0.481 48.3 83 0.257 9.6 SMBJ24A/CA 0.2 1 24 26.7 28.1 1 38.9 16 0.587 50 80 0.256 9.6 SMBJ26A/CA 0.2 1 26 28.9 30.4 1 42.1 14.9 0.683 53.5 75 0.288 9.7 SMBJ28A/CA 0.2 1 28 31.1 32.7 1 45.4 13.8 0.802 59 68 0.363 9.8 SMBJ30A/CA 0.2 1 30 33.3 35.1 1 48.4 13 0.888 64.3 62 0.443 9.9 SMBJ33A/CA 0.2 1 33 36.7 38.6 1 53.3 11.8 1.08 69.7 57 0.512 10.0 SMBJ36A/CA 0.2 1 36 40.0 42.1 1 58.1 10.3 1.35 76 52 0.611 10.0 SMBJ40A/CA 0.2 1 40 44.4 46.7 1 64.5 9.7 1.59 84 48 0.728 10.1 SMBJ48A/CA 0.2 1 48 53.3 56.1 1 77.4 8.1 2.28 100 40 1.03 10.3 SMBJ58A/CA 0.2 1 58 64.4 67.8 1 93.6 6.7 3.34 121 33 1.51 10.4 SMBJ70A/CA 0.2 1 70 77.8 81.9 1 113 5.5 4.91 146 27 2.22 10.5 SMBJ85A/CA 0.2 1 85 94 99 1 137 4.6 7.18 178 22.5 3.29 10.6 SMBJ100A/CA 0.2 1 100 111 117 1 162 3.8 10.3 212 19 4.69 10.7 SMBJ130A/CA 0.2 1 130 144 152 1 209 3 16.5 265 15 7.03 10.8 SMBJ154A/CA 0.2 1 154 171 180 1 246 2.4 23.8 317 12.6 10.2 10.8 SMBJ170A/CA 0.2 1 170 189 199 1 275 2.2 30.0 353 11.3 12.7 10.8 SMBJ188A/CA 0.2 1 188 209 220 1 328 2 48.5 388 10.3 15.2 10.8 1. Pulse test : tp < 50 ms 2. To calculate maximum clamping voltage at other surge level,use the following formula: VCLmax = VCL - RD x (IPP - IPPappli) where IPPappli is the surge current in the application 3. To calculate VBR or VCL versus junction temperature, use the following formulas: VBR @ TJ = VBR @ 25°C x (1 + αT x (TJ – 25)) VCL @ TJ = VCL @ 25°C x (1 + αT x (TJ – 25)) 4. Surge capability given for both directions for unidirectional and bidirectional types. Characteristics SMBJ 4/10 Doc ID 5616 Rev 10 Figure 5. Clamping voltage versus peak pulse current (exponential waveform, maximum values) Figure 3. Peak pulse power dissipation versus initial junction temperature Figure 4. Peak pulse power versus exponential pulse duration (Tj initial = 25 °C) 0 100 200 300 400 500 600 700 0 25 50 75 100 125 150 175 Ppp (W) Tj(°C) 0.1 1.0 10.0 100.0 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 PPP(kW) Tj initial = 25 °C tP(ms) IPP(A) 0.1 1.0 10.0 100.0 1000.0 1 10 100 1000 10/1000 μs Tj initial=25 °C 8/20 μs 10 ms SMBJ5.0A SMBJ188A SMBJ12A SMBJ24A SMBJ40A SMBJ85A VCL(V) SMBJ Characteristics Doc ID 5616 Rev 10 5/10 Figure 6. Junction capacitance versus reverse applied voltage for unidirectional types (typical values) Figure 7. Junction capacitance versus reverse applied voltage for bidirectional types (typical values) 10 100 1000 10000 1 10 100 1000 C(pF) F=1 MHz Vosc=30 mVRMS Tj=25 °C SMBJ5.0A SMBJ12A SMBJ24A SMBJ40A SMBJ85A VR(V) SMBJ188A 10 100 1000 10000 1 10 100 1000 C(pF) F=1 MHz Vosc=30 mVRMS Tj=25 °C SMBJ5.0CA SMBJ12CA SMBJ24CA SMBJ40CA SMBJ85CA SMBJ188CA VR(V) Figure 8. Peak forward voltage drop versus peak forward current (typical values) Figure 9. Relative variation of thermal impedance, junction to ambient, versus pulse duration Figure 10. Thermal resistance, junction to ambient, versus copper surface under each lead Figure 11. Leakage current versus junction temperature (typical values) IFM(A) 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Tj =25 °C Tj =125 °C VFM(V) 0.01 0.10 1.00 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 Zth(j-a) /Rth(j-a) tP(s) Recommended pad layout PCB FR4, copper thickness = 35 μm 0 10 20 30 40 50 60 70 80 90 100 110 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 R (°C/W) th(J-A) SCU(cm²) PCB FR4, copper thickness = 35 μm 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 25 50 75 100 125 150 VR=VRM VRM ≥ 10 V VR=VRM VRM< 10 V Tj(°C) IR (nA) Ordering information scheme SMBJ 6/10 Doc ID 5616 Rev 10 2 Ordering information scheme Figure 12. Ordering information scheme SM B J 85 CA - TR Surface mount Peak pulse power B = 600 WTransil in SMB Stand off voltage 85 = 85 V Type A = Unidirectional CA = Bidirectional Delivery mode TR = Tape and reel SMBJ Package information Doc ID 5616 Rev 10 7/10 3 Package information ● Case: JEDEC DO-214AA molded plastic over planar junction ● Terminals: solder plated - solderable per MIL-STD-750, Method 2026 ● Polarity: for unidirectional types the band indicates cathode ● Flammability: epoxy is rated UL94V-0 ● RoHS package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 4. SMB dimensions Ref. Dimensions Millimeters Inches Min. Max. Min. Max. A1 1.90 2.45 0.075 0.096 A2 0.05 0.20 0.002 0.008 b 1.95 2.20 0.077 0.087 c 0.15 0.40 0.006 0.016 D 3.30 3.95 0.130 0.156 E 5.10 5.60 0.201 0.220 E1 4.05 4.60 0.159 0.181 L 0.75 1.50 0.030 0.059 Figure 13. Footprint dimensions in mm (inches) Figure 14. Marking layout(1) 1. Marking layout can vary according to assembly location. E C L E1 D A1 A2 b 2.60 5.84 1.62 2.18 1.62 (0.064) (0.102) (0.23) (0.064) (0.086) y w w e z x x x e: ECOPACK compliance XXX: Marking Z: Manufacturing location Y: Year WW: week Cathode bar ( unidirectional devices only ) Package information SMBJ 8/10 Doc ID 5616 Rev 10 Table 5. Marking Order code Marking Order code Marking SMBJ5.0A-TR BUZ SMBJ5.0CA-TR BBZ SMBJ6.0A-TR BUA SMBJ6.0CA-TR BBA SMBJ6.5A-TR BUB SMBJ6.5CA-TR BBB SMBJ8.5A-TR BUC SMBJ8.5CA-TR BBC SMBJ10A-TR BUD SMBJ10CA-TR BBD SMBJ12A-TR BUE SMBJ12CA-TR BBE SMBJ13A-TR BUF SMBJ13CA-TR BBF SMBJ15A-TR BUG SMBJ15CA-TR BBG SMBJ16A-TR CUG SMBJ16CA-TR CBG SMBJ18A-TR BUH SMBJ18CA-TR BBH SMBJ20A-TR BUI SMBJ20CA-TR BBI SMBJ22A-TR BVA SMBJ22CA-TR CBH SMBJ24A-TR BUJ SMBJ24CA-TR BBJ SMBJ26A-TR BUK SMBJ26CA-TR BBK SMBJ28A-TR BUL SMBJ28CA-TR BBL SMBJ30A-TR BUM SMBJ30CA-TR BBM SMBJ33A-TR BUN SMBJ33CA-TR BBN SMBJ36A-TR CUN SMBJ36CA-TR CBN SMBJ40A-TR CUJ SMBJ40CA-TR CBJ SMBJ43A-TR CUW SMBJ43CA-TR CBW SMBJ48A-TR BUW SMBJ48CA-TR BBW SMBJ58A-TR BUO SMBJ58CA-TR BBO SMBJ70A-TR CUM SMBJ70CA-TR CBM SMBJ85A-TR BUQ SMBJ85CA-TR BBQ SMBJ100A-TR CUQ SMBJ100CA-TR CBQ SMBJ130A-TR BUS SMBJ130CA-TR BBS SMBJ154A-TR BUT SMBJ154CA-TR BBT SMBJ170A-TR BUU SMBJ170CA-TR BBU SMBJ188A-TR BUV SMBJ188CA-TR BBV SMBJ Ordering information Doc ID 5616 Rev 10 9/10 4 Ordering information 5 Revision history Table 6. Order codes Order code Marking Package Weight Base qty Delivery mode SMBJxxxA/CA-TR(1) 1. Where xxx is nominal value of VBR and A or CA indicates unidirectional or bidirectional version. See Table 3 for list of available devices and their order codes See Table 5 on page 8 SMB 0.11 g 2500 Tape and reel Table 7. Document revision history Date Revision Changes Oct-2001 4 Previous issue 10-Feb-2005 5 Reformatted to current template. Added directional (uni and bi) indications to graphics. Added ECOPACK statement. 16-Nov-2006 6 Add part numbers SMBJ36A-TR and SMBJ36CA-TR in Table 3. 14-May-2009 7 Reformatted to current standards. Updated ECOPACK statement. Added part number SMBJ43CA/A 17-Sep-2009 8 Document updated for low leakage current. 09-Jul-2010 9 Changed timescale in Figure 9. 20-Oct-2010 10 Updated Figure 13. SMBJ 10/10 Doc ID 5616 Rev 10 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 1 of 211 A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee® Applications • 2.4 GHz IEEE 802.15.4 systems • ZigBee® systems • Home/building automation • Industrial Control and Monitoring • Low power wireless sensor networks • PC peripherals • Set-top boxes and remote controls • Consumer Electronics Product Description The CC2430 comes in three different flash versions: CC2430F32/64/128, with 32/64/128 KB of flash memory respectively. The CC2430 is a true System-on-Chip (SoC) solution specifically tailored for IEEE 802.15.4 and ZigBee® applications. It enables ZigBee® nodes to be built with very low total bill-ofmaterial costs. The CC2430 combines the excellent performance of the leading CC2420 RF transceiver with an industry-standard enhanced 8051 MCU, 32/64/128 KB flash memory, 8 KB RAM and many other powerful features. Combined with the industry leading ZigBee® protocol stack (Z-Stack™) from Texas Instruments, the CC2430 provides the market’s most competitive ZigBee® solution. The CC2430 is highly suited for systems where ultra low power consumption is required. This is ensured by various operating modes. Short transition times between operating modes further ensure low power consumption. Key Features • RF/Layout o 2.4 GHz IEEE 802.15.4 compliant RF transceiver (industry leading CC2420 radio core) o Excellent receiver sensitivity and robustness to interferers o Very few external components o Only a single crystal needed for mesh network systems o RoHS compliant 7x7mm QLP48 package • Low Power o Low current consumption (RX: 27 mA, TX: 27 mA, microcontroller running at 32 MHz) o Only 0.5 μA current consumption in powerdown mode, where external interrupts or the RTC can wake up the system o 0.3 μA current consumption in stand-by mode, where external interrupts can wake up the system o Very fast transition times from low-power modes to active mode enables ultra low average power consumption in low dutycycle systems o Wide supply voltage range (2.0V - 3.6V) • Microcontroller o High performance and low power 8051 microcontroller core o 32, 64 or 128 KB in-system programmable flash o 8 KB RAM, 4 KB with data retention in all power modes o Powerful DMA functionality o Watchdog timer o One IEEE 802.15.4 MAC timer, one general 16-bit timer and two 8-bit timers o Hardware debug support • Peripherals o CSMA/CA hardware support. o Digital RSSI / LQI support o Battery monitor and temperature sensor o 12-bit ADC with up to eight inputs and configurable resolution o AES security coprocessor o Two powerful USARTs with support for several serial protocols o 21 general I/O pins, two with 20mA sink/source capability • Development tools o Powerful and flexible development tools available Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 2 of 211 Table Of Contents 1 ABBREVIATIONS................................................................................................................................ 5 2 REFERENCES....................................................................................................................................... 7 3 REGISTER CONVENTIONS .............................................................................................................. 8 4 FEATURES EMPHASIZED ................................................................................................................ 9 4.1 HIGH-PERFORMANCE AND LOW-POWER 8051-COMPATIBLE MICROCONTROLLER ............................... 9 4.2 UP TO 128 KB NON-VOLATILE PROGRAM MEMORY AND 2 X 4 KB DATA MEMORY ............................ 9 4.3 HARDWARE AES ENCRYPTION/DECRYPTION ....................................................................................... 9 4.4 PERIPHERAL FEATURES......................................................................................................................... 9 4.5 LOW POWER.......................................................................................................................................... 9 4.6 IEEE 802.15.4MAC HARDWARE SUPPORT........................................................................................... 9 4.7 INTEGRATED 2.4GHZ DSSS DIGITAL RADIO ........................................................................................ 9 5 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 10 6 OPERATING CONDITIONS............................................................................................................. 10 7 ELECTRICAL SPECIFICATIONS .................................................................................................. 11 7.1 GENERAL CHARACTERISTICS .............................................................................................................. 12 7.2 RF RECEIVE SECTION ......................................................................................................................... 13 7.3 RF TRANSMIT SECTION....................................................................................................................... 13 7.4 32 MHZ CRYSTAL OSCILLATOR.......................................................................................................... 14 7.5 32.768 KHZ CRYSTAL OSCILLATOR.................................................................................................... 14 7.6 32 KHZ RC OSCILLATOR..................................................................................................................... 15 7.7 16 MHZ RC OSCILLATOR ................................................................................................................... 15 7.8 FREQUENCY SYNTHESIZER CHARACTERISTICS ................................................................................... 16 7.9 ANALOG TEMPERATURE SENSOR........................................................................................................ 16 7.10 ADC ................................................................................................................................................... 16 7.11 CONTROL AC CHARACTERISTICS........................................................................................................ 18 7.12 SPI AC CHARACTERISTICS ................................................................................................................. 19 7.13 DEBUG INTERFACE AC CHARACTERISTICS ......................................................................................... 20 7.14 PORT OUTPUTS AC CHARACTERISTICS............................................................................................... 21 7.15 TIMER INPUTS AC CHARACTERISTICS................................................................................................. 21 7.16 DC CHARACTERISTICS........................................................................................................................ 21 8 PIN AND I/O PORT CONFIGURATION ........................................................................................ 22 9 CIRCUIT DESCRIPTION ................................................................................................................. 24 9.1 CPU AND PERIPHERALS ...................................................................................................................... 25 9.2 RADIO ................................................................................................................................................. 26 10 APPLICATION CIRCUIT ................................................................................................................. 27 10.1 INPUT / OUTPUT MATCHING................................................................................................................. 27 10.2 BIAS RESISTORS .................................................................................................................................. 27 10.3 CRYSTAL............................................................................................................................................. 27 10.4 VOLTAGE REGULATORS ...................................................................................................................... 27 10.5 DEBUG INTERFACE.............................................................................................................................. 27 10.6 POWER SUPPLY DECOUPLING AND FILTERING...................................................................................... 28 11 8051 CPU .............................................................................................................................................. 30 11.1 8051 CPU INTRODUCTION .................................................................................................................. 30 11.2 MEMORY............................................................................................................................................. 30 11.3 CPU REGISTERS.................................................................................................................................. 42 11.4 INSTRUCTION SET SUMMARY.............................................................................................................. 44 11.5 INTERRUPTS ........................................................................................................................................ 49 12 DEBUG INTERFACE......................................................................................................................... 60 12.1 DEBUG MODE ..................................................................................................................................... 60 12.2 DEBUG COMMUNICATION ................................................................................................................... 60 12.3 DEBUG COMMANDS ............................................................................................................................ 60 12.4 DEBUG LOCK BIT................................................................................................................................ 60 12.5 DEBUG INTERFACE AND POWER MODES ............................................................................................. 64 13 PERIPHERALS................................................................................................................................... 65 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 3 of 211 13.1 POWER MANAGEMENT AND CLOCKS................................................................................................... 65 13.2 RESET ................................................................................................................................................. 71 13.3 FLASH CONTROLLER........................................................................................................................... 71 13.4 I/O PORTS............................................................................................................................................ 77 13.5 DMA CONTROLLER ............................................................................................................................ 88 13.6 16-BIT TIMER, TIMER1 ........................................................................................................................ 99 13.7 MAC TIMER (TIMER2)...................................................................................................................... 110 13.8 8-BIT TIMERS, TIMER 3 AND TIMER 4 ................................................................................................ 117 13.9 SLEEP TIMER..................................................................................................................................... 126 13.10 ADC ................................................................................................................................................. 128 13.11 RANDOM NUMBER GENERATOR ....................................................................................................... 134 13.12 AES COPROCESSOR .......................................................................................................................... 136 13.13 WATCHDOG TIMER ........................................................................................................................... 141 13.14 USART............................................................................................................................................. 143 14 RADIO................................................................................................................................................ 153 14.1 IEEE 802.15.4MODULATION FORMAT............................................................................................. 154 14.2 COMMAND STROBES ......................................................................................................................... 155 14.3 RF REGISTERS................................................................................................................................... 155 14.4 INTERRUPTS ...................................................................................................................................... 155 14.5 FIFO ACCESS .................................................................................................................................... 157 14.6 DMA ................................................................................................................................................ 157 14.7 RECEIVE MODE.................................................................................................................................. 158 14.8 RXFIFO OVERFLOW......................................................................................................................... 158 14.9 TRANSMIT MODE............................................................................................................................... 159 14.10 GENERAL CONTROL AND STATUS ...................................................................................................... 160 14.11 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION ..................................................... 160 14.12 FRAME FORMAT................................................................................................................................ 161 14.13 SYNCHRONIZATION HEADER ............................................................................................................. 161 14.14 LENGTH FIELD................................................................................................................................... 162 14.15 MAC PROTOCOL DATA UNIT ............................................................................................................. 162 14.16 FRAME CHECK SEQUENCE ................................................................................................................. 162 14.17 RF DATA BUFFERING........................................................................................................................ 163 14.18 ADDRESS RECOGNITION.................................................................................................................... 164 14.19 ACKNOWLEDGE FRAMES .................................................................................................................. 165 14.20 RADIO CONTROL STATE MACHINE ..................................................................................................... 166 14.21 MAC SECURITY OPERATIONS (ENCRYPTION AND AUTHENTICATION).............................................. 168 14.22 LINEAR IF AND AGC SETTINGS ........................................................................................................ 168 14.23 RSSI / ENERGY DETECTION.............................................................................................................. 168 14.24 LINK QUALITY INDICATION .............................................................................................................. 168 14.25 CLEAR CHANNEL ASSESSMENT......................................................................................................... 169 14.26 FREQUENCY AND CHANNEL PROGRAMMING..................................................................................... 169 14.27 VCO AND PLL SELF-CALIBRATION.................................................................................................. 169 14.28 OUTPUT POWER PROGRAMMING....................................................................................................... 170 14.29 INPUT / OUTPUT MATCHING.............................................................................................................. 170 14.30 TRANSMITTER TEST MODES ............................................................................................................. 171 14.31 SYSTEM CONSIDERATIONS AND GUIDELINES.................................................................................... 173 14.32 PCB LAYOUT RECOMMENDATION .................................................................................................... 175 14.33 ANTENNA CONSIDERATIONS............................................................................................................. 175 14.34 CSMA/CA STROBE PROCESSOR....................................................................................................... 176 14.35 RADIO REGISTERS............................................................................................................................. 183 15 VOLTAGE REGULATORS............................................................................................................. 202 15.1 VOLTAGE REGULATORS POWER-ON.................................................................................................. 202 16 EVALUATION SOFTWARE........................................................................................................... 202 17 REGISTER OVERVIEW................................................................................................................. 203 18 PACKAGE DESCRIPTION (QLP 48) ............................................................................................ 206 18.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 48).................................................................... 207 18.2 PACKAGE THERMAL PROPERTIES....................................................................................................... 207 18.3 SOLDERING INFORMATION ................................................................................................................ 207 18.4 TRAY SPECIFICATION ........................................................................................................................ 207 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 4 of 211 18.5 CARRIER TAPE AND REEL SPECIFICATION.......................................................................................... 207 19 ORDERING INFORMATION......................................................................................................... 209 20 GENERAL INFORMATION........................................................................................................... 210 20.1 DOCUMENT HISTORY........................................................................................................................ 210 21 ADDRESS INFORMATION............................................................................................................ 210 22 TI WORLDWIDE TECHNICAL SUPPORT................................................................................. 210 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 5 of 211 1 Abbreviations ADC Analog to Digital Converter AES Advanced Encryption Standard AGC Automatic Gain Control ARIB Association of Radio Industries and Businesses BCD Binary Coded Decimal BER Bit Error Rate BOD Brown Out Detector BOM Bill of Materials CBC Cipher Block Chaining CBC-MAC Cipher Block Chaining Message Authentication Code CCA Clear Channel Assessment CCM Counter mode + CBC-MAC CFB Cipher Feedback CFR Code of Federal Regulations CMOS Complementary Metal Oxide Semiconductor CMRR Common Mode Ratio Recjection CPU Central Processing Unit CRC Cyclic Redundancy Check CSMA-CA Carrier Sense Multiple Access with Collision Avoidance CSP CSMA/CA Strobe Processor CTR Counter mode (encryption) CW Continuous Wave DAC Digital to Analog Converter DC Direct Current DMA Direct Memory Access DNL Differential Nonlineraity DSM Delta Sigma Modulator DSSS Direct Sequence Spread Spectrum ECB Electronic Code Book (encryption) EM Evaluation Module ENOB Effective Number of bits ESD Electro Static Discharge ESR Equivalent Series Resistance ETSI European Telecommunications Standards Institute EVM Error Vector Magnitude FCC Federal Communications Commission FCF Frame Control Field FCS Frame Check Sequence FFCTRL FIFO and Frame Control FIFO First In First Out HF High Frequency HSSD High Speed Serial Data I/O Input / Output I/Q In-phase / Quadrature-phase IEEE Institute of Electrical and Electronics Engineers IF Intermediate Frequency INL Integral Nonlinearity IOC I/O Controller IRQ Interrupt Request ISM Industrial, Scientific and Medical ITU-T International Telecommunication Union – Telecommunication Standardization Sector IV Initialization Vector JEDEC Joint Electron Device Engineering Council KB 1024 bytes kbps kilo bits per second LC Inductor-capacitor LFSR Linear Feedback Shift Register LNA Low-Noise Amplifier LO Local Oscillator LQI Link Quality Indication LSB Least Significant Bit / Byte LSB Least Significant Byte MAC Medium Access Control MAC Message Authentication Code MCU Microcontroller Unit MFR MAC Footer MHR MAC Header MIC Message Integrity Code MISO Master In Slave Out MOSI Master Out Slave In MPDU MAC Protocol Data Unit MSB Most Significant Byte MSDU MAC Service Data Unit MUX Multiplexer NA Not Available NC Not Connected OFB Output Feedback (encryption) O-QPSK Offset - Quadrature Phase Shift Keying PA Power Amplifier PCB Printed Circuit Board PER Packet Error Rate PHR PHY Header PHY Physical Layer PLL Phase Locked Loop Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 6 of 211 PM{0-3} Power Mode 0-3 PMC Power Management Controller POR Power On Reset PSDU PHY Service Data Unit PWM Pulse Width Modulator QLP Quad Leadless Package RAM Random Access Memory RBW Resolution Bandwidth RC Resistor-Capacitor RCOSC RC Oscillator RF Radio Frequency RoHS Restriction on Hazardous Substances RSSI Receive Signal Strength Indicator RTC Real-Time Clock RX Receive SCK Serial Clock SFD Start of Frame Delimiter SFR Special Function Register SHR Synchronization Header SINAD Signal-to-noise and distortion ratio SPI Serial Peripheral Interface SRAM Static Random Access Memory ST Sleep Timer T/R Tape and reel T/R Transmit / Receive TBD To Be Decided / To Be Defined THD Total Harmonic Distortion TI Texas Instruments TX Transmit UART Universal Asynchronous Receiver/Transmitter USART Universal Synchronous/Asynchronous Receiver/Transmitter VCO Voltage Controlled Oscillator VGA Variable Gain Amplifier WDT Watchdog Timer XOSC Crystal Oscillator Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 7 of 211 2 References [1] IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf [2] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 8 of 211 3 Register conventions Each SFR register is described in a separate table. The table heading is given in the following format: REGISTER NAME (SFR Address) - Register Description. Each RF register is described in a separate table. The table heading is given in the following format: REGISTER NAME (XDATA Address) In the register descriptions, each register bit is shown with a symbol indicating the access mode of the register bit. The register values are always given in binary notation unless prefixed by ‘0x’ which indicates hexadecimal notation. Table 1: Register bit conventions Symbol Access Mode R/W Read/write R Read only R0 Read as 0 R1 Read as 1 W Write only W0 Write as 0 W1 Write as 1 H0 Hardware clear H1 Hardware set Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 9 of 211 4 Features Emphasized 4.1 High-Performance and Low-Power 8051-Compatible Microcontroller • Optimized 8051 core, which typically gives 8x the performance of a standard 8051 • Dual data pointers • In-circuit interactive debugging is supported for the IAR Embedded Workbench through a simple two-wire serial interface 4.2 Up to 128 KB Non-volatile Program Memory and 2 x 4 KB Data Memory • 32/64/128 KB of non-volatile flash memory in-system programmable through a simple two-wire interface or by the 8051 core • Worst-case flash memory endurance: 1000 write/erase cycles • Programmable read and write lock of portions of Flash memory for software security • 4096 bytes of internal SRAM with data retention in all power modes • Additional 4096 bytes of internal SRAM with data retention in power modes 0 and 1 4.3 Hardware AES Encryption/Decryption • AES supported in hardware coprocessor 4.4 Peripheral Features • Powerful DMA Controller • Power On Reset/Brown-Out Detection • Eight channel ADC with configurable resolution • Programmable watchdog timer • Real time clock with 32.768 kHz crystal oscillator • Four timers: one general 16-bit timer, two general 8-bit timers, one MAC timer • Two programmable USARTs for master/slave SPI or UART operation • 21 configurable general-purpose digital I/O-pins • True random number generator 4.5 Low Power • Four flexible power modes for reduced power consumption • System can wake up on external interrupt or real-time counter event • Low-power fully static CMOS design • System clock source can be 16 MHz RC oscillator or 32 MHz crystal oscillator. The 32 MHz oscillator is used when radio is active • Optional clock source for ultra-low power operation can be either low-power RC oscillator or an optional 32.768 kHz crystal oscillator 4.6 IEEE 802.15.4 MAC hardware support • Automatic preamble generator • Synchronization word insertion/detection • CRC-16 computation and checking over the MAC payload • Clear Channel Assessment • Energy detection / digital RSSI • Link Quality Indication • CSMA/CA Coprocessor 4.7 Integrated 2.4GHz DSSS Digital Radio • 2.4 GHz IEEE 802.15.4 compliant RF transceiver (based on industry leading CC2420 radio core). • Excellent receiver sensitivity and robustness to interferers • 250 kbps data rate, 2 MChip/s chip rate • Reference designs comply with worldwide radio frequency regulations covered by ETSI EN 300 328 and EN 300 440 class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan). Transmit on 2480MHz under FCC is supported by duty-cycling, or by reducing output power. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 10 of 211 5 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 2 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Table 2: Absolute Maximum Ratings Parameter Min Max Units Condition Supply voltage –0.3 3.9 V All supply pins must have the same voltage Voltage on any digital pin –0.3 VDD+0.3, max 3.9 V Voltage on the 1.8V pins (pin no. 22, 25-40 and 42) –0.3 2.0 V Input RF level 10 dBm Storage temperature range –50 150 °C Device not programmed Reflow soldering temperature 260 °C According to IPC/JEDEC J-STD-020C <500 V On RF pads (RF_P, RF_N, AVDD_RF1, and AVDD_RF2), according to Human Body Model, JEDEC STD 22, method A114 700 V All other pads, according to Human Body Model, JEDEC STD 22, method A114 ESD 200 V According to Charged Device Model, JEDEC STD 22, method C101 Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. 6 Operating Conditions The operating conditions for CC2430 are listed in Table 3 . Table 3: Operating Conditions Parameter Min Max Unit Condition Operating ambient temperature range, TA -40 85 °C Operating supply voltage 2.0 3.6 V The supply pins to the radio part must be driven by the 1.8 V on-chip regulator Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 11 of 211 7 Electrical Specifications Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 4: Electrical Specifications Parameter Min Typ Max Unit Condition Current Consumption MCU Active Mode, 16 MHz, low MCU activity 4.3 mA Digital regulator on. 16 MHz RCOSC running. No radio, crystals, or peripherals active. Low MCU activity: no flash access (i.e. only cache hit), no RAM access. MCU Active Mode, 16 MHz, medium MCU activity 5.1 mA Digital regulator on. 16 MHz RCOSC running. No radio, crystals, or peripherals active. Medium MCU activity: normal flash access1, minor RAM access. MCU Active Mode, 16 MHz, high MCU activity 5.7 mA Digital regulator on. 16 MHz RCOSC running. No radio, crystals, or peripherals active. High MCU activity: normal flash access1, extensive RAM access and heavy CPU load. MCU Active Mode, 32 MHz, low MCU activity 9.5 mA 32 MHz XOSC running. No radio or peripherals active. Low MCU activity : no flash access (i.e. only cache hit), no RAM access MCU Active Mode, 32 MHz, medium MCU activity 10.5 mA 32 MHz XOSC running. No radio or peripherals active. Medium MCU activity: normal flash access1, minor RAM access. MCU Active Mode, 32 MHz, high MCU activity 12.3 mA 32 MHz XOSC running. No radio or peripherals active. High MCU activity: normal flash access1, extensive RAM access and heavy CPU load. MCU Active and RX Mode 26.7 mA MCU running at full speed (32MHz), 32MHz XOSC running, radio in RX mode, -50 dBm input power. No peripherals active. Low MCU activity. MCU Active and TX Mode, 0dBm 26.9 mA MCU running at full speed (32MHz), 32MHz XOSC running, radio in TX mode, 0dBm output power. No peripherals active. Low MCU activity. Power mode 1 190 μA Digital regulator on, 16 MHz RCOSC and 32 MHz crystal oscillator off. 32.768 kHz XOSC, POR and ST active. RAM retention. Power mode 2 0.5 μA Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator off. 32.768 kHz XOSC, POR and ST active. RAM retention. Power mode 3 0.3 μA No clocks. RAM retention. POR active. Peripheral Current Consumption Adds to the figures above if the peripheral unit is activated Timer 1 150 μA Timer running, 32MHz XOSC used. Timer 2 230 μA Timer running, 32MHz XOSC used. Timer 3 50 μA Timer running, 32MHz XOSC used. Timer 4 50 μA Timer running, 32MHz XOSC used. Sleep Timer 0.2 μA Including 32.753 kHz RCOSC. ADC 1.2 mA When converting. Flash write 3 mA Estimated value Flash erase 3 mA Estimated value 1 Normal Flash access means that the code used exceeds the cache storage (see last paragraph in section 11.2.3 Flash memory) so cache misses will happen frequently. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 12 of 211 7.1 General Characteristics Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 5: General Characteristics Parameter Min Typ Max Unit Condition/Note Wake-Up and Timing Power mode 1 􀃆 power mode 0 4.1 μs Digital regulator on, 16 MHz RCOSC and 32 MHz crystal oscillator off. Start-up of 16 MHz RCOSC. Power mode 2 or 3 􀃆 power mode 0 120 μs Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator off. Start-up of regulator and 16 MHz RCOSC. Active 􀃆 TX or RX 32MHz XOSC initially OFF. Voltage regulator initially OFF 525 μs Time from enabling radio part in power mode 0, until TX or RX starts. Includes start-up of voltage regulator and crystal oscillator in parallel. Crystal ESR=16Ω. Active 􀃆 TX or RX Voltage regulator initially OFF 320 μs Time from enabling radio part in power mode 0, until TX or RX starts. Includes start-up of voltage regulator. Active 􀃆 RX or TX 192 μs Radio part already enabled. Time until RX or TX starts. RX/TX turnaround 192 μs Radio part RF Frequency Range 2400 2483.5 MHz Programmable in 1 MHz steps, 5 MHz between channels for compliance with [1] Radio bit rate 250 kbps As defined by [1] Radio chip rate 2.0 MChip/s As defined by [1] Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 13 of 211 7.2 RF Receive Section Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 6: RF Receive Parameters Parameter Min Typ Max Unit Condition/Note Receiver sensitivity -92 dBm PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun. [1] requires –85 dBm Saturation (maximum input level) 10 dBm PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun. [1] requires –20 dBm Adjacent channel rejection + 5 MHz channel spacing 41 dB Wanted signal -88dBm, adjacent modulated channel at +5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB Adjacent channel rejection - 5 MHz channel spacing 30 dB Wanted signal -88dBm, adjacent modulated channel at -5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB Alternate channel rejection + 10 MHz channel spacing 55 dB Wanted signal -88dBm, adjacent modulated channel at +10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB Alternate channel rejection - 10 MHz channel spacing 53 dB Wanted signal -88dBm, adjacent modulated channel at -10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB Channel rejection ≥ + 15 MHz ≤ - 15 MHz 55 53 dB dB Wanted signal @ -82 dBm. Undesired signal is an 802.15.4 modulated channel, stepped through all channels from 2405 to 2480 MHz. Signal level for PER = 1%. Values are estimated. Co-channel rejection -6 dB Wanted signal @ -82 dBm. Undesired signal is 802.15.4 modulated at the same frequency as the desired signal. Signal level for PER = 1%. Blocking / Desensitization + 5 MHz from band edge + 10 MHz from band edge + 20 MHz from band edge + 50 MHz from band edge - 5 MHz from band edge - 10 MHz from band edge - 20 MHz from band edge - 50 MHz from band edge -42 -45 -26 -22 -31 -36 -24 -25 dBm dBm dBm dBm dBm dBm dBm dBm Wanted signal 3 dB above the sensitivity level, CW jammer, PER = 1%. Measured according to EN 300 440 class 2. Spurious emission 30 – 1000 MHz 1 – 12.75 GHz −64 −75 dBm dBm Conducted measurement in a 50 Ω single ended load. Complies with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66. Frequency error tolerance ±140 ppm Difference between centre frequency of the received RF signal and local oscillator frequency. [1] requires minimum 80 ppm Symbol rate error tolerance ±900 ppm Difference between incoming symbol rate and the internally generated symbol rate [1] requires minimum 80 ppm 7.3 RF Transmit Section Measured on Texas Instruments CC2430 EM reference design with TA=25°C, VDD=3.0V, and nominal output power unless stated otherwise. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 14 of 211 Table 7: RF Transmit Parameters Parameter Min Typ Max Unit Condition/Note Nominal output power 0 dBm Delivered to a single ended 50 Ω load through a balun and output power control set to 0x5F (TXCTRLL). [1] requires minimum –3 dBm Programmable output power range 26 dB The output power is programmable in 16 steps from typically -25.2 to 0.6 dBm (see Table 45). Harmonics 2nd harmonic 3rd harmonic 4th harmonic 5th harmonic -50.7 -55.8 -54.2 -53.4 dBm dBm dBm dBm Measurement conducted with 100 kHz resolution bandwidth on spectrum analyzer and output power control set to 0x5F (TXCTRLL). Output Delivered to a single ended 50 Ω load through a balun. Spurious emission 30 - 1000 MHz 1– 12.75 GHz 1.8 – 1.9 GHz 5.15 – 5.3 GHz -47 -43 -58 -56 dBm dBm dBm dBm Maximum output power. Texas Instruments CC2430 EM reference design complies with EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STDT- 66. Transmit on 2480MHz under FCC is supported by duty-cycling, or by reducing output power The peak conducted spurious emission is -47 dBm @ 192 MHz which is in an EN 300 440 restricted band limited to -54 dBm. All radiated spurious emissions are within the limits of ETSI/FCC/ARIB. Conducted spurious emission (CSE) can be reduced with a simple band pass filter connected between matching network and RF connector (1.8 pF in parallel with 1.6 nH reduces the CSE by 20 dB), this filter must be connected to good RF ground. Error Vector Magnitude (EVM) 11 % Measured as defined by [1] [1] requires max. 35 % Optimum load impedance 60 + j164 Ω Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna2. 7.4 32 MHz Crystal Oscillator Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 8: 32 MHz Crystal Oscillator Parameters Parameter Min Typ Max Unit Condition/Note Crystal frequency 32 MHz Crystal frequency accuracy requirement - 40 40 ppm Including aging and temperature dependency, as specified by [1] ESR 6 16 60 Ω Simulated over operating conditions C0 1 1.9 7 pF Simulated over operating conditions CL 10 13 16 pF Simulated over operating conditions Start-up time 212 μs 7.5 32.768 kHz Crystal Oscillator Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. 2 This is for 2440MHz Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 15 of 211 Table 9: 32.768 kHz Crystal Oscillator Parameters Parameter Min Typ Max Unit Condition/Note Crystal frequency 32.768 kHz Crystal frequency accuracy requirement –40 40 ppm Including aging and temperature dependency, as specified by [1] ESR 40 130 kΩ Simulated over operating conditions C0 0.9 2.0 pF Simulated over operating conditions CL 12 16 pF Simulated over operating conditions Start-up time 400 ms Value is simulated. 7.6 32 kHz RC Oscillator Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 10: 32 kHz RC Oscillator parameters Parameter Min Typ Max Unit Condition/Note Calibrated frequency 32.753 kHz The calibrated 32 kHz RC Oscillator frequency is the 32 MHz XTAL frequency divided by 977 Frequency accuracy after calibration ±0.2 % Value is estimated. Temperature coefficient +0.4 % / °C Frequency drift when temperature changes after calibration. Value is estimated. Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes after calibration. Value is estimated. Initial calibration time 1.7 ms When the 32 kHz RC Oscillator is enabled, calibration is continuously done in the background as long as the 32 MHz crystal oscillator is running and SLEEP.OSC32K_CALDIS bit is cleared. 7.7 16 MHz RC Oscillator Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 11: 16 MHz RC Oscillator parameters Parameter Min Typ Max Unit Condition/Note Frequency 16 MHz The calibrated 16 MHz RC Oscillator frequency is the 32 MHz XTAL frequency divided by 2 Uncalibrated frequency accuracy ±18 % Calibrated frequency accuracy ±0.6 ±1 % Start-up time 10 μs Temperature coefficient -325 ppm / °C Frequency drift when temperature changes after calibration Supply voltage coefficient 28 ppm / mV Frequency drift when supply voltage changes after calibration Initial calibration time 50 μs When the 16 MHz RC Oscillator is enabled it will be calibrated continuously when the 32MHz crystal oscillator is running. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 16 of 211 7.8 Frequency Synthesizer Characteristics Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 12: Frequency Synthesizer Parameters Parameter Min Typ Max Unit Condition/Note Phase noise −116 −117 −118 dBc/Hz dBc/Hz dBc/Hz Unmodulated carrier At ±1.5 MHz offset from carrier At ±3 MHz offset from carrier At ±5 MHz offset from carrier PLL lock time 192 μs The startup time until RX/TX turnaround. The crystal oscillator is running. 7.9 Analog Temperature Sensor Measured on Texas Instruments CC2430 EM reference design with TA=25°C and VDD=3.0V unless stated otherwise. Table 13: Analog Temperature Sensor Parameters Parameter Min Typ Max Unit Condition/Note Output voltage at –40°C 0.648 V Value is estimated Output voltage at 0°C 0.743 V Value is estimated Output voltage at +40°C 0.840 V Value is estimated Output voltage at +80°C 0.939 V Value is estimated Temperature coefficient 2.45 mV/°C Fitted from –20°C to +80°C on estimated values. Absolute error in calculated temperature –8 °C From –20°C to +80°C when assuming best fit for absolute accuracy on estimated values: 0.743V at 0°C and 2.45mV / °C. Error in calculated temperature, calibrated -2 0 2 °C From –20°C to +80°C when using 2.45mV / °C, after 1-point calibration at room temperature. Values are estimated. Indicated min/max with 1- point calibration is based on simulated values for typical process parameters Current consumption increase when enabled 280 μA 7.10 ADC Measured with TA=25°C and VDD=3.0V. Note that other data may result using Texas Instruments CC2430 EM reference design. Table 14: ADC Characteristics Parameter Min Typ Max Unit Condition/Note Input voltage 0 VDD V VDD is voltage on AVDD_SOC pin External reference voltage 0 VDD V VDD is voltage on AVDD_SOC pin External reference voltage differential 0 VDD V VDD is voltage on AVDD_SOC pin Input resistance, signal 197 kΩ Simulated using 4 MHz clock speed (see section 13.10.2.7) Full-Scale Signal3 2.97 V Peak-to-peak, defines 0dBFS 3 Measured with 300 Hz Sine input and VDD as reference. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 17 of 211 Parameter Min Typ Max Unit Condition/Note ENOB3 5.7 bits 7-bits setting. Single ended input 7.5 9-bits setting. 9.3 10-bits setting. 10.8 12-bits setting. ENOB3 6.5 bits 7-bits setting. Differential input 8.3 9-bits setting. 10.0 10-bits setting. 11.5 12-bits setting. Useful Power Bandwidth 0-20 kHz 7-bits setting, both single and differential THD3 -Single ended input -75.2 dB 12-bits setting, -6dBFS -Differential input -86.6 dB 12-bits setting, -6dBFS Signal To Non-Harmonic Ratio3 -Single ended input 70.2 dB 12-bits setting -Differential input 79.3 dB 12-bits setting Spurious Free Dynamic Range3 -Single ended input 78.8 dB 12-bits setting, -6dBFS -Differential input 88.9 dB 12-bits setting, -6dBFS CMRR, differential input <-84 dB 12- bit setting, 1 kHz Sine (0dBFS), limited by ADC resolution Crosstalk, single ended input <-84 dB 12- bit setting, 1 kHz Sine (0dBFS), limited by ADC resolution Offset -3 mV Mid. scale Gain error 0.68 % DNL3 0.05 LSB 12-bits setting, mean 0.9 LSB 12-bits setting, max INL3 4.6 LSB 12-bits setting, mean 13.3 LSB 12-bits setting, max SINAD3 35.4 dB 7-bits setting. Single ended input 46.8 dB 9-bits setting. (-THD+N) 57.5 dB 10-bits setting. 66.6 dB 12-bits setting. SINAD3 40.7 dB 7-bits setting. Differential input 51.6 dB 9-bits setting. (-THD+N) 61.8 dB 10-bits setting. 70.8 dB 12-bits setting. Conversion time 20 μs 7-bits setting. 36 μs 9-bits setting. 68 μs 10-bits setting. 132 μs 12-bits setting. Power Consumption 1.2 mA Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 18 of 211 7.11 Control AC Characteristics TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 15: Control Inputs AC Characteristics Parameter Min Typ Max Unit Condition/Note System clock, fSYSCLK tSYSCLK= 1/ fSYSCLK 16 32 MHz System clock is 32 MHz when crystal oscillator is used. System clock is 16 MHz when calibrated 16 MHz RC oscillator is used. RESET_N low width 250 ns See item 1, Figure 1. This is the shortest pulse that is guaranteed to be recognized as a complete reset pin request. Note that shorter pulses may be recognized but will not lead to complete reset of all modules within the chip. Interrupt pulse width tSYSCLK ns See item 2, Figure 1.This is the shortest pulse that is guaranteed to be recognized as an interrupt request. In PM2/3 the internal synchronizers are bypassed so this requirement does not apply in PM2/3. 1 2 2 RESET_N Px.n Px.n Figure 1: Control Inputs AC Characteristics Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 19 of 211 7.12 SPI AC Characteristics TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 16: SPI AC Characteristics Parameter Min Typ Max Unit Condition/Note SCK period See section 13.14.4 ns Master. See item 1 Figure 2 SCK duty cycle 50% Master. SSN low to SCK 2*tSYSCLK See item 5 Figure 2 SCK to SSN high 30 ns See item 6 Figure 2 MISO setup 10 ns Master. See item 2 Figure 2 MISO hold 10 ns Master. See item 3 Figure 2 SCK to MOSI 25 ns Master. See item 4 Figure 2, load = 10 pF SCK period 100 ns Slave. See item 1 Figure 2 SCK duty cycle 50% Slave. MOSI setup 10 ns Slave. See item 2 Figure 2 MOSI hold 10 ns Slave. See item 3 Figure 2 SCK to MISO 25 ns Slave. See item 4 Figure 2, load = 10 pF Figure 2: SPI AC Characteristics Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 20 of 211 7.13 Debug Interface AC Characteristics TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 17: Debug Interface AC Characteristics Parameter Min Typ Max Unit Condition/Note Debug clock period 128 ns See item 1 Figure 3 Debug data setup 5 ns See item 2 Figure 3 Debug data hold 5 ns See item 3 Figure 3 Clock to data delay 10 ns See item 4 Figure 3, load = 10 pF RESET_N inactive after P2_2 rising 10 ns See item 5 Figure 3 1 3 2 DEBUG CLK P2_2 DEBUG DATA P2_1 DEBUG DATA P2_1 4 RESET_N 5 Figure 3: Debug Interface AC Characteristics Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 21 of 211 7.14 Port Outputs AC Characteristics TA= 25°C, VDD=3.0V if nothing else stated. Table 18: Port Outputs AC Characteristics Parameter Min Typ Max Unit Condition/Note P0_[0:7], P1_[2:7], P2_[0:4] Port output rise time (SC=0/SC=1) 3.15/ 1.34 ns Load = 10 pF Timing is with respect to 10% VDD and 90% VDD levels. Values are estimated fall time (SC=0/SC=1) 3.2/ 1.44 Load = 10 pF Timing is with respect to 90% VDD and 10% VDD. Values are estimated 7.15 Timer Inputs AC Characteristics TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 19: Timer Inputs AC Characteristics Parameter Min Typ Max Unit Condition/Note Input capture pulse width tSYSCLK ns Synchronizers determine the shortest input pulse that can be recognized. The synchronizers operate at the current system clock rate (16 or 32 MHz) 7.16 DC Characteristics The DC Characteristics of CC2430 are listed in Table 20 below. TA=25°C, VDD=3.0V if nothing else stated. Table 20: DC Characteristics Digital Inputs/Outputs Min Typ Max Unit Condition Logic "0" input voltage 0.5 V Logic "1" input voltage VDD-0.5 V Logic "0" input current NA –1 μA Input equals 0V Logic "1" input current NA 1 μA Input equals VDD I/O pin pull-up and pull-down resistor 20 kΩ Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 22 of 211 8 Pin and I/O Port Configuration The CC2430 pinout is shown in Figure 4 and Table 21. See section 13.4 for details on the configuration of digital I/O ports. P2_4/XOSC_Q2 P2_2 P0_7 P0_2 P0_3 P0_4 P0_5 P0_6 XOSC_Q2 DVDD P2_1 P2_3/XOSC_Q1 AVDD_DREG DCOUPL AVDD_SOC XOSC_Q1 RBIAS1 AVDD_RREG RREG_OUT AVDD_DGUARD DVDD_ADC AVDD_ADC AVDD_IF2 P2_0 Figure 4: Pinout top view Note: The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 23 of 211 Table 21: Pinout overview Pin Pin name Pin type Description - GND Ground The exposed die attach pad must be connected to a solid ground plane 1 P1_7 Digital I/O Port 1.7 2 P1_6 Digital I/O Port 1.6 3 P1_5 Digital I/O Port 1.5 4 P1_4 Digital I/O Port 1.4 5 P1_3 Digital I/O Port 1.3 6 P1_2 Digital I/O Port 1.2 7 DVDD Power (Digital) 2.0V-3.6V digital power supply for digital I/O 8 P1_1 Digital I/O Port 1.1 – 20 mA drive capability 9 P1_0 Digital I/O Port 1.0 – 20 mA drive capability 10 RESET_N Digital input Reset, active low 11 P0_0 Digital I/O Port 0.0 12 P0_1 Digital I/O Port 0.1 13 P0_2 Digital I/O Port 0.2 14 P0_3 Digital I/O Port 0.3 15 P0_4 Digital I/O Port 0.4 16 P0_5 Digital I/O Port 0.5 17 P0_6 Digital I/O Port 0.6 18 P0_7 Digital I/O Port 0.7 19 XOSC_Q2 Analog I/O 32 MHz crystal oscillator pin 2 20 AVDD_SOC Power (Analog) 2.0V-3.6V analog power supply connection 21 XOSC_Q1 Analog I/O 32 MHz crystal oscillator pin 1, or external clock input 22 RBIAS1 Analog I/O External precision bias resistor for reference current 23 AVDD_RREG Power (Analog) 2.0V-3.6V analog power supply connection 24 RREG_OUT Power output 1.8V Voltage regulator power supply output. Only intended for supplying the analog 1.8V part (power supply for pins 25, 27-31, 35-40). 25 AVDD_IF1 Power (Analog) 1.8V Power supply for the receiver band pass filter, analog test module, global bias and first part of the VGA 26 RBIAS2 Analog output External precision resistor, 43 kΩ, ±1 % 27 AVDD_CHP Power (Analog) 1.8V Power supply for phase detector, charge pump and first part of loop filter 28 VCO_GUARD Power (Analog) Connection of guard ring for VCO (to AVDD) shielding 29 AVDD_VCO Power (Analog) 1.8V Power supply for VCO and last part of PLL loop filter 30 AVDD_PRE Power (Analog) 1.8V Power supply for Prescaler, Div-2 and LO buffers 31 AVDD_RF1 Power (Analog) 1.8V Power supply for LNA, front-end bias and PA 32 RF_P RF I/O Positive RF input signal to LNA during RX. Positive RF output signal from PA during TX 33 TXRX_SWITCH Power (Analog) Regulated supply voltage for PA 34 RF_N RF I/O Negative RF input signal to LNA during RX Negative RF output signal from PA during TX 35 AVDD_SW Power (Analog) 1.8V Power supply for LNA / PA switch 36 AVDD_RF2 Power (Analog) 1.8V Power supply for receive and transmit mixers 37 AVDD_IF2 Power (Analog) 1.8V Power supply for transmit low pass filter and last stages of VGA 38 AVDD_ADC Power (Analog) 1.8V Power supply for analog parts of ADCs and DACs 39 DVDD_ADC Power (Digital) 1.8V Power supply for digital parts of ADCs 40 AVDD_DGUARD Power (Digital) Power supply connection for digital noise isolation 41 AVDD_DREG Power (Digital) 2.0V-3.6V digital power supply for digital core voltage regulator 42 DCOUPL Power (Digital) 1.8V digital power supply decoupling. Do not use for supplying external circuits. 43 P2_4/XOSC_Q2 Digital I/O Port 2.4/32.768 kHz XOSC 44 P2_3/XOSC_Q1 Digital I/O Port 2.3/32.768 kHz XOSC 45 P2_2 Digital I/O Port 2.2 46 P2_1 Digital I/O Port 2.1 47 DVDD Power (Digital) 2.0V-3.6V digital power supply for digital I/O 48 P2_0 Digital I/O Port 2.0 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 24 of 211 9 Circuit Description Figure 5: CC2430 Block Diagram A block diagram of CC2430 is shown in Figure 5. The modules can be roughly divided into one of three categories: CPU-related modules, modules related to power, test and clock distribution, and radio-related modules. In the following subsections, a short description of each module that appears in Figure 5 is given. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 25 of 211 9.1 CPU and Peripherals The 8051 CPU core is a single-cycle 8051- compatible core. It has three different memory access buses (SFR, DATA and CODE/XDATA), a debug interface and an 18- input extended interrupt unit. See section 11 for details on the CPU. The memory crossbar/arbitrator is at the heart of the system as it connects the CPU and DMA controller with the physical memories and all peripherals through the SFR bus. The memory arbitrator has four memory access points, access at which can map to one of three physical memories: an 8 KB SRAM, flash memory or RF and SFR registers. The memory arbitrator is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory. The SFR bus is drawn conceptually in Figure 5 as a common bus that connects all hardware peripherals to the memory arbitrator. The SFR bus in the block diagram also provides access to the radio registers in the radio register bank even though these are indeed mapped into XDATA memory space. The 8 KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. 4 KB of the 8 KB SRAM is an ultralow- power SRAM that retains its contents even when the digital part is powered off (power modes 2 and 3). The rest of the SRAM loses its contents when the digital part is powered off. The 32/64/128 KB flash block provides incircuit programmable non-volatile program memory for the device and maps into the CODE and XDATA memory spaces. Table 22 shows the available devices in the CC2430 family. The available devices differ only in flash memory size. Writing to the flash block is performed through a flash controller that allows page-wise (2048 byte) erasure and 4 byte-wise programming. See section 13.3 for details on the flash controller. A versatile five-channel DMA controller is available in the system and accesses memory using the XDATA memory space and thus has access to all physical memories. Each channel is configured (trigger, priority, transfer mode, addressing mode, source and destination pointers, and transfer count) with DMA descriptors anywhere in memory. Many of the hardware peripherals rely on the DMA controller for efficient operation (AES core, flash write controller, USARTs, Timers, ADC interface) by performing data transfers between a single SFR address and flash/SRAM. See section 13.5 for details. The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which is associated with one of four interrupt priorities. An interrupt request is serviced even if the device is in a sleep mode (power modes 1-3) by bringing the CC2430 back to active mode (power mode 0). The debug interface implements a proprietary two-wire serial interface that is used for incircuit debugging. Through this debug interface it is possible to perform an erasure of the entire flash memory, control which oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051 core, set code breakpoints, and single step through instructions in the code. Using these techniques it is possible to elegantly perform in-circuit debugging and external flash programming. See section 12 for details. The I/O-controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral modules control certain pins or whether they are under software control, and if so whether each pin is configured as an input or output and if a pullup or pull-down resistor in the pad is connected. Each peripheral that connects to the I/O-pins can choose between two different I/O pin locations to ensure flexibility in various applications. See section 13.4 for details. The sleep timer is an ultra-low power timer that counts 32.768 kHz crystal oscillator or 32 kHz RC oscillator periods. The sleep timer runs continuously in all operating modes except power mode 3. Typical uses for it is as a real-time counter that runs regardless of operating mode (except power mode 3) or as a wakeup timer to get out of power mode 1 or 2. See section 13.9 for details. A built-in watchdog timer allows the CC2430 to reset itself in case the firmware hangs. When enabled by software, the watchdog timer must be cleared periodically, otherwise it will reset the device when it times out. See section 13.13 for details. Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period value and three individually programmable counter/capture channels each with a 16-bit compare value. Each of the counter/capture channels can be used as PWM outputs or to Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 26 of 211 capture the timing of edges on input signals. See section 13.6 for details. MAC timer (Timer 2) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slotted protocols in software. The timer has a configurable timer period and an 8-bit overflow counter that can be used to keep track of the number of periods that have transpired. There is also a 16-bit capture register used to record the exact time at which a start of frame delimiter is received/transmitted or the exact time of which transmission ends, as well as a 16-bit output compare register that can produce various command strobes (start RX, start TX, etc) at specific times to the radio modules. See section 13.7 for details. Timers 3 and 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler, an 8-bit period value and one programmable counter channel with a 8-bit compare value. Each of the counter channels can be used as PWM outputs. See section 13.8 for details. USART 0 and 1 are each configurable as either an SPI master/slave or a UART. They provide double buffering on both RX and TX and hardware flow-control and are thus well suited to high-throughput full-duplex applications. Each has its own high-precision baud-rate generator thus leaving the ordinary timers free for other uses. When configured as an SPI slave they sample the input signal using SCK directly instead of some oversampling scheme and are thus well-suited to high data rates. See section 13.14 for details. The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with 128-bit keys. The core is able to support the AES operations required by IEEE 802.15.4 MAC security, the ZigBee® network layer and the application layer. See section 13.12 for details. The ADC supports 7 to 12 bits of resolution in a 30 kHz to 4 kHz bandwidth respectively. DC and audio conversions with up to 8 input channels (Port 0) are possible. The inputs can be selected as single ended or differential. The reference voltage can be internal, AVDD, or a single ended or differential external signal. The ADC also has a temperature sensor input channel. The ADC can automate the process of periodic sampling or conversion over a sequence of channels. See Section 13.10 for details. 9.2 Radio CC2430 features an IEEE 802.15.4 compliant radio based on the leading CC2420 transceiver. See Section 14 for details. Table 22: CC2430 Flash Memory Options Device Flash CC2430F32 32 KB CC2430F64 64 KB CC2430F128 128 KB Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 27 of 211 10 Application Circuit Few external components are required for the operation of CC2430. A typical application circuit is shown in Figure 6. Typical values and description of external components are shown in Table 23. 10.1 Input / output matching The RF input/output is high impedance and differential. The optimum differential load for the RF port is 60 + j164 Ω4. When using an unbalanced antenna such as a monopole, a balun should be used in order to optimize performance. The balun can be implemented using low-cost discrete inductors and capacitors. The recommended balun shown, consists of C341, L341, L321 and L331 together with a PCB microstrip transmission line (λ/2-dipole), and will match the RF input/output to 50 Ω. An internal T/R switch circuit is used to switch between the 4 This is for 2440MHz. LNA (RX) and the PA (TX). See Input/output matching section on page 170 for more details. If a balanced antenna such as a folded dipole is used, the balun can be omitted. If the antenna also provides a DC path from TXRX_SWITCH pin to the RF pins, inductors are not needed for DC bias. Figure 6 shows a suggested application circuit using a differential antenna. The antenna type is a standard folded dipole. The dipole has a virtual ground point; hence bias is provided without degradation in antenna performance. Also refer to the section Antenna Considerations on page 175. 10.2 Bias resistors The bias resistors are R221 and R261. The bias resistor R221 is used to set an accurate bias current for the 32 MHz crystal oscillator. 10.3 Crystal An external 32 MHz crystal, XTAL1, with two loading capacitors (C191 and C211) is used for the 32 MHz crystal oscillator. See page 14 for details. The load capacitance seen by the 32 MHz crystal is given by: L parasitic C C C C + + = 191 211 1 1 1 XTAL2 is an optional 32.768 kHz crystal, with two loading capacitors (C441 and C431), used for the 32.768 kHz crystal oscillator. The 32.768 kHz crystal oscillator is used in applications where you need both very low sleep current consumption and accurate wake up times. The load capacitance seen by the 32.768 kHz crystal is given by: L parasitic C C C C + + = 441 431 1 1 1 A series resistor may be used to comply with the ESR requirement. 10.4 Voltage regulators The on chip voltage regulators supply all 1.8 V power supply pins and internal power supplies. C241 and C421 are required for stability of the regulators. 10.5 Debug interface The debug interface pin P2_2 is connected through pull-up resistor R451 to the power supply. See section 12 on page 60. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 28 of 211 10.6 Power supply decoupling and filtering Proper power supply decoupling must be used for optimum performance. The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. TI provides a compact reference design that should be followed very closely. Refer to the section PCB Layout Recommendation on page 175. 35 34 33 32 31 30 29 28 27 26 25 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 R261 2.0 - 3.6V Power Supply C341 Antenna (50 Ohm) L331 L321 RESET_N P1_6 P1_5 P1_4 P1_3 DVDD P1_2 P1_1 P1_0 P0_0 P0_1 P1_7 P0_7 P0_2 P0_3 P0_4 P0_5 P0_6 XOSC_Q2 AVDD_SOC XOSC_Q1 RBIAS1 AVDD_RREG RREG_OUT AVDD_PRE RF_P RF_N AVDD_SW AVDD_RF1 TXRX_SWITCH AVDD_RF2 AVDD_IF1 AVDD_CHP VCO_GUARD RBIAS2 AVDD_VCO P2_4 P2_2 DVDD P2_1 P2_3 AVDD_DREG DCOUPL AVDD_DGUARD DVDD_ADC AVDD_ADC AVDD_IF2 P2_0 R221 C241 XTAL2 C441 C431 or L321 Folded Dipole PCB Antenna L331 XTAL1 C191 C211 C421 L341 optional /4 /4 Figure 6: CC2430 Application Circuit. (Digital I/O and ADC interface not connected). Decoupling capacitors not shown. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 29 of 211 Table 23: Overview of external components (excluding supply decoupling capacitors) Component Description Single Ended 50Ω Output Differential Antenna C191 32 MHz crystal load capacitor 33 pF, 5%, NP0, 0402 33 pF, 5%, NP0, 0402 C211 32 MHz crystal load capacitor 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 C241 Load capacitance for analogue power supply voltage regulators 220 nF, 10%, 0402 220 nF, 10%, 0402 C421 Load capacitance for digital power supply voltage regulators 1 μF, 10%, 0402 1 μF, 10%, 0402 C341 DC block to antenna and match 5.6 pF, 5%, NP0, 0402 Not used Note: For RF connector a LP filter can be connected between this C, the antenna and good ground in order to remove conducted spurious emission by using 1.8pF in parallel with 1.6nH 1.8 pF, Murata COG 0402, GRM15 1.6 nH, Murata 0402, LQG15HS1N6S02 C431, C441 32.768 kHz crystal load capacitor (if lowfrequency crystal is needed in application) 15 pF, 5%, NP0, 0402 15 pF, 5%, NP0, 0402 L321 Discrete balun and match 6.8 nH, 5%, Monolithic/multilayer, 0402 12 nH 5%, Monolithic/multilayer, 0402 L331 Discrete balun and match 22 nH, 5%, Monolithic/multilayer, 0402 27 nH, 5%, Monolithic/multilayer, 0402 L341 Discrete balun and match 1.8 nH, +/-0.3 nH, Monolithic/multilayer, 0402 Not used R221 Precision resistor for current reference generator to system-on-chip part 56 kΩ, 1%, 0402 56 kΩ, 1%, 0402 R261 Precision resistor for current reference generator to RF part 43 kΩ, 1%, 0402 43 kΩ, 1%, 0402 XTAL1 32 MHz Crystal 32 MHz crystal, ESR < 60 Ω 32 MHz crystal, ESR < 60 Ω XTAL2 Optional 32.768 kHz watch crystal (if lowfrequency crystal is needed in application) 32.768 kHz crystal, Epson MC 306. 32.768 kHz crystal, Epson MC 306. Not Recommended for New Designs CC2430 8051 CPU : 8051 CPU Introduction CC2430 Data Sheet (rev. 2.1) SWRS036F Page 30 of 211 11 8051 CPU This section describes the 8051 CPU core, with interrupts, memory and instruction set. 11.1 8051 CPU Introduction The CC2430 includes an 8-bit CPU core which is an enhanced version of the industry standard 8051 core. The enhanced 8051 core uses the standard 8051 instruction set. Instructions execute faster than the standard 8051 due to the following: • One clock per instruction cycle is used as opposed to 12 clocks per instruction cycle in the standard 8051. • Wasted bus states are eliminated. Since an instruction cycle is aligned with memory fetch when possible, most of the single byte instructions are performed in a single clock cycle. In addition to the speed improvement, the enhanced 8051 core also includes architectural enhancements: • A second data pointer. • Extended 18-source interrupt unit The 8051 core is object code compatible with the industry standard 8051 microcontroller. That is, object code compiled with an industry standard 8051 compiler or assembler executes on the 8051 core and is functionally equivalent. However, because the 8051 core uses a different instruction timing than many other 8051 variants, existing code with timing loops may require modification. Also because the peripheral units such as timers and serial ports differ from those on a other 8051 cores, code which includes instructions using the peripheral units SFRs will not work correctly. 11.2 Memory The 8051 CPU architecture has four different memory spaces. The 8051 has separate memory spaces for program memory and data memory. The 8051 memory spaces are the following (see section 11.2.1 and 11.2.2 for details): CODE. A read-only memory space for program memory. This memory space addresses 64 KB. DATA. A read/write data memory space, which can be directly or indirectly, accessed by a single cycle CPU instruction, thus allowing fast access. This memory space addresses 256 bytes. The lower 128 bytes of the DATA memory space can be addressed either directly or indirectly, the upper 128 bytes only indirectly. XDATA. A read/write data memory space access to which usually requires 4-5 CPU instruction cycles, thus giving slow access. This memory space addresses 64 KB. Access to XDATA memory is also slower in hardware than DATA access as the CODE and XDATA memory spaces share a common bus on the CPU core and instruction pre-fetch from CODE can thus not be performed in parallel with XDATA accesses. SFR. A read/write register memory space which can be directly accessed by a single CPU instruction. This memory space consists of 128 bytes. For SFR registers whose address is divisible by eight, each bit is also individually addressable. The four different memory spaces are distinct in the 8051 architecture, but are partly overlapping in the CC2430 to ease DMA transfers and hardware debugger operation. How the different memory spaces are mapped onto the three physical memories (flash program memory, 8 KB SRAM and memorymapped registers) is described in sections 11.2.1 and 11.2.2. 11.2.1 Memory Map This section gives an overview of the memory map. The memory map differs from the standard 8051 memory map in two important aspects, as described below. First, in order to allow the DMA controller access to all physical memory and thus allow DMA transfers between the different 8051 memory spaces, parts of SFR and CODE memory space are mapped into the XDATA memory space. Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 31 of 211 Secondly, two alternative schemes for CODE memory space mapping can be used. The first scheme is the standard 8051 mapping where only the program memory i.e. flash memory is mapped to CODE memory space. This mapping is the default used after a device reset. The second scheme is an extension to the standard CODE space mapping in that all physical memory is mapped to the CODE space region. This second scheme is called unified mapping of the CODE memory space. Details about mapping of all 8051 memory spaces are given in the next section. The memory map showing how the different physical memories are mapped into the CPU memory spaces is given in the figures on the following pages for 128 KB flash memory size option only. The other flash options are reduced versions of the F128 with natural limitations. Note that for CODE memory space, the two alternative memory maps are shown; unified and non-unified (standard) mapping. For users familiar with the 8051 architecture, the standard 8051 memory space is shown as “8051 memory spaces” in the figures. Non-volatile program memory 56 KB CC2430-F128 XDATA memory space Physical memory 8 KB SRAM RF registers XDATA memory space DATA memory space SF R memory space 8051 memory spaces 0x0000 Registers Fast access RAM 0xFF00 Slow access RAM / program memory in RAM 0xE000 0xFFFF 0x0000 0xFF 0x80 0xFF 0x00 SFR registers 0xDFFF 0xDF00 0xDF80 0xDFFF 0xDEFF 0xDEFF 0x0000 lower 56 KB 0xFFFF 0xFFFF 0xDF00 128 KB Flash 0xFFFF Figure 7: CC2430-F128 XDATA memory space Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 32 of 211 Code memory space 8051 memory spaces 0xFFFF 0x0000 Physical memory MEMCTR.MUNIF = 0 CODE maps to flash memory only Non-volatile program memory 32 KB bank 0 0x0000 0x7FFF Non-volatile program memory 32 KB bank 0 - bank 3 0x8000 0xFFFF 0x07FFF 0x00000 32 KB bank 0 32 KB bank 1 0x08000 0x1FFFF 32 KB bank 2 32 KB bank 3 0x18000 0x10000 0x17FFF 0x0FFFF CC2430-F128 CODE memory space 128 KB flash Figure 8: CC2430-F128 Non-unified mapping of CODE Space Non-volatile program memory 32 KB bank 0 Non-volatile program memory 24 KB bank 0 - bank 3 Physical memory 8 KB SRAM RF registers 0x0000 Registers Fast access RAM 0xFF00 Slow access RAM / program memory in RAM 0xE000 SFR registers 0xDF00 0xDF80 0xDFFF 0xDEFF 128 KB Flash (0x8000 * (bank +1)) - 0x20FF 0x0000 32 KB bank 0 0xFFFF 0x7FFF MEMCTR.MUNIF = 1 CODE maps to unified memory CC2430-F128 CODE memory space 0x8000 * bank 0x7FFF 0x8000 24 KB bank 0-3 Figure 9: CC2430-F128 Unified mapping of CODE space Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 33 of 211 11.2.2 CPU Memory Space This section describes the details of each CPU memory space. XDATA memory space. The XDATA memory map is given in Figure 7. For devices with flash size above 32 KB only 56 KB of the flash memory is mapped into XDATA, address range 0x0000-0xDEFF. For the 32 KB flash size option, the 32 KB flash memory is mapped to 0x0000-0x7FFF in XDATA. Access to unimplemented areas in the memory map gives an undefined result (applies to F32 only). For all device flash-options, the 8 KB SRAM is mapped into address range 0xE000-0xFFFF. The SFR registers are mapped into address range 0xDF80-0xDFFF, and are also equal on all flash options. Another memory-mapped register area is the RF register area which is mapped into the address range 0xDF00-0xDF7F. These registers are associated with the radio (see sections 14 and 14.35) and are also equal on all flash options. The mapping of flash memory, SRAM and registers to XDATA allows the DMA controller and the CPU access to all the physical memories in a single unified address space (maximum of 56 KB flash, above reserved for CODE). Note that the CODE banking scheme, described in CODE memory space section, will not affect the contents of the 24 KB above the 32KB lowest memory area, thus XDATA mapps into the Flash as shown in Figure 7. One of the ramifications of this mapping is that the first address of usable SRAM starts at address 0xE000 instead of 0x0000, and therefore compilers/assemblers must take this into consideration. In low-power modes PM2-3 the upper 4 KB of SRAM, i.e. the memory locations in XDATA address range 0xF000-0xFFFF, will retain their contents. There are some locations in this area that are excepted from retention and thus does not keep its data in these power modes. Refer to section 13.1 on page 65 for a detailed description of power modes and SRAM data retention. CODE memory space. The CODE memory space uses either a unified or a non-unified memory mapping (see section 11.2.1 on page 30) to the physical memories as shown in Figure 8 and Figure 9. The unified mapping of the CODE memory space is similar to the XDATA mapping. Note that some SFR registers internal to the CPU can not be accessed in the unified CODE memory space (see section 11.2.3, SFR registers, on page 34). With flash memory sizes above 32 KB, only 56 KB of flash memory is mapped to CODE memory space at a time when unified mapping is used. The upper 24 KB follows the banking scheme described below and shown in Figure 9. This is similar to the XDATA memory space exept for the upper 24 KB that can change content. Using unified memory CODE data at address above 0xDEFF will not contain flash data. The 8 KB SRAM is included in the unified CODE address space to allow program execution out of the SRAM. Note: In order to use the unified memory mapping within CODE memory space, the SFR register bit MEMCTR.MUNIF must be 1. For devices with flash memory size of 128 KB (CC2430F128), a flash memory banking scheme is used for the CODE memory space. For the banking scheme the upper 32 KB area of CODE memory space is mapped to one out of the four 32 KB physical blocks (banks) of flash memory. The lower 32 KB of CODE space is always mapped to the lowest 32 KB of the flash memory. The banking is controlled through the flash bank select bit (FMAP.MAP) and shown in the non-unified CODE memory map in Figure 8. The flash bank select bits reside in the SFR register bits FMAP.MAP, and also in the SFR register bits MEMCTR.FMAP, (see section 11.2.5 on page 40). The FMAP.MAP bit and MEMCTR.FMAP bit are transparent and updating one is reflected by the other. When banking and unified CODE memory space are used, only the lower 24 KB in the selected bank is available. This is shown in Figure 9. DATA memory space. The 8-bit address range of DATA memory is mapped into the upper 256 bytes of the 8 KB SRAM. This area is also accessible through the unified CODE and XDATA memory spaces at the address range 0xFF00-0xFFFF. SFR memory space. The 128 entry hardware register area is accessed through this memory space. The SFR registers are also accessible through the XDATA address space at the address range 0xDF80-0xDFFF. Some CPUNot Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 34 of 211 specific SFR registers reside inside the CPU core and can only be accessed using the SFR memory space and not through the duplicate mapping into XDATA memory space. These specific SFR registers are listed in section 11.2.3, SFR registers, on page 34. 11.2.3 Physical memory RAM. The CC2430 contains static RAM. At power-on the contents of RAM is undefined. The RAM size is 8 KB in total. The upper 4 KB of the RAM (XDATA memory locations 0xF000-0xFFFF) retains data in all power modes (see exception below). The remaining lower 4 KB (XDATA memory locations 0xE000-0xEFFF) will loose its contents in PM2 and PM3 and contains undefined data when returning to PM0. The memory locations 0xFD56-0xFEFF (XDATA) consists of 426 bytes in RAM that will not retain data when PM2/3 is entered. Flash Memory. The on-chip flash memory consists of 32768, 655536 or 131072 bytes. The flash memory is primarily intended to hold program code. The flash memory has the following features: • Flash page erase time: 20 ms • Flash chip (mass) erase time: 200 ms • Flash write time (4 bytes): 20 μs • Data retention5:100 years • Program/erase endurance: 1,000 cycles The flash memory consists of the Flash Main Pages (up to 64 times 2 KB) which is where the CPU reads program code and data. The flash memory also contains a Flash Information Page (2 KB) which contains the Flash Lock Bits. The Flash Information Page and hence the Lock Bits is only accessed through the Debug Interface, and must be selected as source prior to access. The Flash 5 At room temperature Controller (see section 13.3) is used to write and erase the contents of the flash main memory. When the CPU reads instructions from flash memory, it fetches the next instruction through a cache. The instruction cache is provided mainly to reduce power consumption by reducing the amount of time the flash memory itself is accessed. The use of the instruction cache may be disabled with the MEMCTR.CACHDIS register bit, but doing so will increase power consuption. SFR Registers. The Special Function Registers (SFRs) control several of the features of the 8051 CPU core and/or peripherals. Many of the 8051 core SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control features that are not available in the standard 8051. The additional SFRs are used to interface with the peripheral units and RF transceiver. Table 24 shows the address to all SFRs in CC2430. The 8051 internal SFRs are shown with grey background, while the other SFRs are the SFRs specific to CC2430. Note: All internal SFRs (shown with grey background in Table 24), can only be accessed through SFR space as these registers are not mapped into XDATA space. Table 25 lists the additional SFRs that are not standard 8051 peripheral SFRs or CPUinternal SFRs. The additional SFRs are described in the relevant sections for each peripheral function. Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 35 of 211 Table 24: SFR address overview 8 bytes 80 P0 SP DPL0 DPH0 DPL1 DPH1 U0CSR PCON 87 88 TCON P0IFG P1IFG P2IFG PICTL P1IEN - P0INP 8F 90 P1 RFIM DPS MPAGE T2CMP ST0 ST1 ST2 97 98 S0CON - IEN2 S1CON T2PEROF0 T2PEROF1 T2PEROF2 FMAP 9F A0 P2 T2OF0 T2OF1 T2OF2 T2CAPLPL T2CAPHPH T2TLD T2THD A7 A8 IEN0 IP0 - FWT FADDRL FADDRH FCTL FWDATA AF B0 - ENCDI ENCDO ENCCS ADCCON1 ADCCON2 ADCCON3 - B7 B8 IEN1 IP1 ADCL ADCH RNDL RNDH SLEEP - BF C0 IRCON U0DBUF U0BAUD T2CNF U0UCR U0GCR CLKCON MEMCTR C7 C8 - WDCTL T3CNT T3CTL T3CCTL0 T3CC0 T3CCTL1 T3CC1 CF D0 PSW DMAIRQ DMA1CFGL DMA1CFGH DMA0CFGL DMA0CFGH DMAARM DMAREQ D7 D8 TIMIF RFD T1CC0L T1CC0H T1CC1L T1CC1H T1CC2L T1CC2H DF E0 ACC RFST T1CNTL T1CNTH T1CTL T1CCTL0 T1CCTL1 T1CCTL2 E7 E8 IRCON2 RFIF T4CNT T4CTL T4CCTL0 T4CC0 T4CCTL1 T4CC1 EF F0 B PERCFG ADCCFG P0SEL P1SEL P2SEL P1INP P2INP F7 F8 U1CSR U1DBUF U1BAUD U1UCR U1GCR P0DIR P1DIR P2DIR FF Table 25: CC2430 specific SFR overview Register name SFR Address Module Description ADCCON1 0xB4 ADC ADC Control 1 ADCCON2 0xB5 ADC ADC Control 2 ADCCON3 0xB6 ADC ADC Control 3 ADCL 0xBA ADC ADC Data Low ADCH 0xBB ADC ADC Data High RNDL 0xBC ADC Random Number Generator Data Low RNDH 0xBD ADC Random Number Generator Data High ENCDI 0xB1 AES Encryption/Decryption Input Data ENCDO 0xB2 AES Encryption/Decryption Output Data ENCCS 0xB3 AES Encryption/Decryption Control and Status DMAIRQ 0xD1 DMA DMA Interrupt Flag DMA1CFGL 0xD2 DMA DMA Channel 1-4 Configuration Address Low DMA1CFGH 0xD3 DMA DMA Channel 1-4 Configuration Address High DMA0CFGL 0xD4 DMA DMA Channel 0 Configuration Address Low DMA0CFGH 0xD5 DMA DMA Channel 0 Configuration Address High DMAARM 0xD6 DMA DMA Channel Armed DMAREQ 0xD7 DMA DMA Channel Start Request and Status FWT 0xAB FLASH Flash Write Timing FADDRL 0xAC FLASH Flash Address Low FADDRH 0xAD FLASH Flash Address High FCTL 0xAE FLASH Flash Control FWDATA 0xAF FLASH Flash Write Data P0IFG 0x89 IOC Port 0 Interrupt Status Flag Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 36 of 211 Register name SFR Address Module Description P1IFG 0x8A IOC Port 1 Interrupt Status Flag P2IFG 0x8B IOC Port 2 Interrupt Status Flag PICTL 0x8C IOC Port Pins Interrupt Mask and Edge P1IEN 0x8D IOC Port 1 Interrupt Mask P0INP 0x8F IOC Port 0 Input Mode PERCFG 0xF1 IOC Peripheral I/O Control ADCCFG 0xF2 IOC ADC Input Configuration P0SEL 0xF3 IOC Port 0 Function Select P1SEL 0xF4 IOC Port 1 Function Select P2SEL 0xF5 IOC Port 2 Function Select P1INP 0xF6 IOC Port 1 Input Mode P2INP 0xF7 IOC Port 2 Input Mode P0DIR 0xFD IOC Port 0 Direction P1DIR 0xFE IOC Port 1 Direction P2DIR 0xFF IOC Port 2 Direction MEMCTR 0xC7 MEMORY Memory System Control FMAP 0x9F MEMORY Flash Memory Bank Mapping RFIM 0x91 RF RF Interrupt Mask RFD 0xD9 RF RF Data RFST 0xE1 RF RF Command Strobe RFIF 0xE9 RF RF Interrupt flags ST0 0x95 ST Sleep Timer 0 ST1 0x96 ST Sleep Timer 1 ST2 0x97 ST Sleep Timer 2 SLEEP 0xBE PMC Sleep Mode Control CLKCON 0xC6 PMC Clock Control T1CC0L 0xDA Timer1 Timer 1 Channel 0 Capture/Compare Value Low T1CC0H 0xDB Timer1 Timer 1 Channel 0 Capture/Compare Value High T1CC1L 0xDC Timer1 Timer 1 Channel 1 Capture/Compare Value Low T1CC1H 0xDD Timer1 Timer 1 Channel 1 Capture/Compare Value High T1CC2L 0xDE Timer1 Timer 1 Channel 2 Capture/Compare Value Low T1CC2H 0xDF Timer1 Timer 1 Channel 2 Capture/Compare Value High T1CNTL 0xE2 Timer1 Timer 1 Counter Low T1CNTH 0xE3 Timer1 Timer 1 Counter High T1CTL 0xE4 Timer1 Timer 1 Control and Status T1CCTL0 0xE5 Timer1 Timer 1 Channel 0 Capture/Compare Control T1CCTL1 0xE6 Timer1 Timer 1 Channel 1 Capture/Compare Control T1CCTL2 0xE7 Timer1 Timer 1 Channel 2 Capture/Compare Control T2CMP 0x94 Timer2 Timer 2 Compare Value T2PEROF0 0x9C Timer2 Timer 2 Overflow Capture/Compare 0 T2PEROF1 0x9D Timer2 Timer 2 Overflow Capture/Compare 1 T2PEROF2 0x9E Timer2 Timer 2 Overflow Capture/Compare 2 Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 37 of 211 Register name SFR Address Module Description T2OF0 0xA1 Timer2 Timer 2 Overflow Count 0 T2OF1 0xA2 Timer2 Timer 2 Overflow Count 1 T2OF2 0xA3 Timer2 Timer 2 Overflow Count 2 T2CAPLPL 0xA4 Timer2 Timer 2 Timer Period Low T2CAPHPH 0xA5 Timer2 Timer 2 Timer Period High T2TLD 0xA6 Timer2 Timer 2 Timer Value Low T2THD 0xA7 Timer2 Timer 2 Timer Value High T2CNF 0xC3 Timer2 Timer 2 Configuration T3CNT 0xCA Timer3 Timer 3 Counter T3CTL 0xCB Timer3 Timer 3 Control T3CCTL0 0xCC Timer3 Timer 3 Channel 0 Compare Control T3CC0 0xCD Timer3 Timer 3 Channel 0 Compare Value T3CCTL1 0xCE Timer3 Timer 3 Channel 1Compare Control T3CC1 0xCF Timer3 Timer 3 Channel 1 Compare Value T4CNT 0xEA Timer4 Timer 4 Counter T4CTL 0xEB Timer4 Timer 4 Control T4CCTL0 0xEC Timer4 Timer 4 Channel 0 Compare Control T4CC0 0xED Timer4 Timer 4 Channel 0 Compare Value T4CCTL1 0xEE Timer4 Timer 4 Channel 1 Compare Control T4CC1 0xEF Timer4 Timer 4 Channel 1 Compare Value TIMIF 0xD8 TMINT Timers 1/3/4 Joint Interrupt Mask/Flags U0CSR 0x86 USART0 USART 0 Control and Status U0DBUF 0xC1 USART0 USART 0 Receive/Transmit Data Buffer U0BAUD 0xC2 USART0 USART 0 Baud Rate Control U0UCR 0xC4 USART0 USART 0 UART Control U0GCR 0xC5 USART0 USART 0 Generic Control U1CSR 0xF8 USART1 USART 1 Control and Status U1DBUF 0xF9 USART1 USART 1 Receive/Transmit Data Buffer U1BAUD 0xFA USART1 USART 1 Baud Rate Control U1UCR 0xFB USART1 USART 1 UART Control U1GCR 0xFC USART1 USART 1 Generic Control WDCTL 0xC9 WDT Watchdog Timer Control RFR Registers. The RFR registers are all related to Radio configuration and control. These registers can only be accessed through the XDATA memory space. A complete description of each register is given in section 14.35 on page 183. Table 26 gives an overview of the register address space while Table 27 gives a more descriptive overview of these registers. Note that shaded areas in Table 26 are registers for test purposes only. Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 38 of 211 Table 26: RFR address overview (XDATA addressable with offset DF00h) DF+ 8 bytes DF+ 00 - - MDMCTRL0H MDMCTRL0L MDMCTRL1H MDMCTRL1L RSSIH RSSIL 07 08 SYNCHWORDH SYNCWORDL TXCTRLH TXCTRLL RXCTRL0H RXCTRL0L RXCTRL1H RXCTRL1L 0F 10 FSCTRLH FSCTRLL CSPX CSPY CSPZ CSPCTRL CSPT RFPWR 17 18 - - - - - - - - 1F 20 FSMTCH FSMTCL MANANDH MANANDL MANORH MANORL AGCCTRLH AGCCTRLL 27 28 AGCTST0H AGCTS0L AGCTST1H AGCTST1L AGCTST2H AGCTST2L FSTST0H FSTST0L 2F 30 FSTST1H FSTST1L FSTST2H FSTST2L FSTST3H FSTST3L - RXBPFTSTH 37 38 RXBPFTSTL FSMSTATE ADCTSTH ADCTSTL DACTSTH DACTSTL - TOPTST 3F 40 RESERVEDH RESERVEDL - IEEE_ADDR0 IEEE_ADDR1 IEEE_ADDR2 IEEE_ADDR3 IEEE_ADDR4 47 48 IEEE_ADDR5 IEEE_ADDR6 IEEE_ADDR7 PANIDH PANIDL SHORTADDRH SHORTADDRL IOCFG0 4F 50 IOCFG1 IOCFG2 IOCFG3 RXFIFOCNT FSMTC1 - - - 57 58 - - - - - - - - 5F 60 CHVER CHIPID RFSTATUS - IRQSRC - - - 67 68 - - - - - - - - 6F 70 - - - - - - - - 77 78 - - - - - - - - 7F Table 27 : Overview of RF registers XDATA Address Register name Description 0xDF00- 0xDF01 - Reserved 0xDF02 MDMCTRL0H Modem Control 0, high 0xDF03 MDMCTRL0L Modem Control 0, low 0xDF04 MDMCTRL1H Modem Control 1, high 0xDF05 MDMCTRL1L Modem Control 1, low 0xDF06 RSSIH RSSI and CCA Status and Control, high 0xDF07 RSSIL RSSI and CCA Status and Control, low 0xDF08 SYNCWORDH Synchronisation Word Control, high 0xDF09 SYNCWORDL Synchronisation Word Control, low 0xDF0A TXCTRLH Transmit Control, high 0xDF0B TXCTRLL Transmit Control, low 0xDF0C RXCTRL0H Receive Control 0, high 0xDF0D RXCTRL0L Receive Control 0, low 0xDF0E RXCTRL1H Receive Control 1, high 0xDF0F RXCTRL1L Receive Control 1, low 0xDF10 FSCTRLH Frequency Synthesizer Control and Status, high 0xDF11 FSCTRLL Frequency Synthesizer Control and Status, low 0xDF12 CSPX CSP X Data 0xDF13 CSPY CSP Y Data 0xDF14 CSPZ CSP Z Data 0xDF15 CSPCTRL CSP Control Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 39 of 211 XDATA Address Register name Description 0xDF16 CSPT CSP T Data 0xDF17 RFPWR RF Power Control 0xDF20 FSMTCH Finite State Machine Time Constants, high 0xDF21 FSMTCL Finite State Machine Time Constants, low 0xDF22 MANANDH Manual AND Override, high 0xDF23 MANANDL Manual AND Override, low 0xDF24 MANORH Manual OR Override, high 0xDF25 MANORL Manual OR Override, low 0xDF26 AGCCTRLH AGC Control, high 0xDF27 AGCCTRLL AGC Control, low 0xDF28- 0xDF38 - Reserved 0xDF39 FSMSTATE Finite State Machine State Status 0xDF3A ADCTSTH ADC Test, high 0xDF3B ADCTSTL ADC Test, low 0xDF3C DACTSTH DAC Test, high 0xDF3D DACTSTL DAC Test, low 0xDF3E- 0xDF41 - Reserved 0xDF43 IEEE_ADDR0 IEEE Address 0 (LSB) 0xDF44 IEEE_ADDR1 IEEE Address 1 0xDF45 IEEE_ADDR2 IEEE Address 2 0xDF46 IEEE_ADDR3 IEEE Address 3 0xDF47 IEEE_ADDR4 IEEE Address 4 0xDF48 IEEE_ADDR5 IEEE Address 5 0xDF49 IEEE_ADDR6 IEEE Address 6 0xDF4A IEEE_ADDR7 IEEE Address 7 (MSB) 0xDF4B PANIDH PAN Identifier, high 0xDF4C PANIDL PAN Identifier, low 0xDF4D SHORTADDRH Short Address, high 0xDF4E SHORTADDRL Short Address, low 0xDF4F IOCFG0 I/O Configuration 0 0xDF50 IOCFG1 I/O Configuration 1 0xDF51 IOCFG2 I/O Configuration 2 0xDF52 IOCFG3 I/O Configuration 3 0xDF53 RXFIFOCNT RX FIFO Count Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 40 of 211 XDATA Address Register name Description 0xDF54 FSMTC1 Finite State Machine Control 0xDF55- 0xDF5F - Reserved 0xDF60 CHVER Chip Version 0xDF61 CHIPID Chip Identification 0xDF62 RFSTATUS RF Status 0xDF63 - Reserved 0xDF64 IRQSRC RF Interrupt Source 0xDF65- 0xDFFF - Reserved 11.2.4 XDATA Memory Access The CC2430 provides an additional SFR register MPAGE. This register is used during instructions MOVX A,@Ri and MOVX @Ri,A. MPAGE gives the 8 most significant address bits, while the register Ri gives the 8 least significant bits. In some 8051 implementations, this type of XDATA access is performed using P2 to give the most significant address bits. Existing software may therefore have to be adapted to make use of MPAGE instead of P2. MPAGE (0x93) – Memory Page Select Bit Name Reset R/W Description 7:0 MPAGE[7:0] 0x00 R/W Memory page, high-order bits of address in MOVX instruction 11.2.5 Memory Arbiter The CC2430 includes a memory arbiter which handles CPU and DMA access to all physical memory. The control registers MEMCTR and FMAP are used to control various aspects of the memory sub-system. The MEMCTR and FMAP registers are described below. MEMCTR.MUNIF controls unified mapping of CODE memory space as shown in Figure 8 and Figure 9 on page 32. Unified mapping is required when the CPU is to execute program stored in RAM (XDATA). For the 128 KB flash version (CC2430-F128), the Flash Bank Map register, FMAP, controls mapping of physical banks of the 128 KB flash to the program address region 0x8000-0xFFFF in CODE memory space as shown in Figure 8 on 32. Please note that the FMAP.MAP[1:0] and MEMCTR.FMAP[1:0] bits are aliased. Writing to FMAP.MAP[1:0] will also change the contents of the MEMCTR.FMAP[1:0] bits, and vice versa. Not Recommended for New Designs CC2430 8051 CPU : Memory CC2430 Data Sheet (rev. 2.1) SWRS036F Page 41 of 211 MEMCTR (0xC7) – Memory Arbiter Control Bit Name Reset R/W Description 7 - 0 R0 Not used Unified memory mapping. When unified mapping is enabled, all physical memories are mapped into the CODE memory space as far as possible, when uniform mapping is disabled only flash memory is mapped to CODE space 0 Disable unified mapping 6 MUNIF 0 R/W 1 Enable unified mapping Flash bank map. These bits are supported by CC2430-F128 only. Controls which of the four 32 KB flash memory banks to map to program address 0x8000 – 0xFFFF in CODE memory space. These bits are aliased to FMAP.MAP[1:0] 00 Map program address 0x8000 – 0xFFFF to physical memory address 0x00000 – 0x07FFF 01 Map program address 0x8000 – 0xFFFF to physical memory address 0x08000– 0x0FFFF 10 Map program address 0x8000 – 0xFFFF to physical memory address 0x10000 – 0x17FFF 5:4 FMAP[1:0] 01 R/W 11 Map program address 0x8000 – 0xFFFF to physical memory address 0x18000 – 0x1FFFF 3:2 - 00 R0 Not used Flash cache disable. Invalidates contents of instruction cache and forces all instruction read accesses to read straight from flash memory. Disabling will increase power consumption and is provided for debug purposes. 0 Cache enabled 1 CACHDIS 0 R/W 1 Cache disabled 0 - 1 R/W Reserved. Always set to 1.6 FMAP (0x9F) – Flash Bank Map Bit Name Reset R/W Description 7:2 - 0x00 R0 Not used Flash bank map. Controls which of the four 32 KB flash memory banks to map to program address 0x8000 – 0xFFFF in CODE memory space. These bits are aliased to MEMCTR.FMAP[5:4] 00 Map program address 0x8000 – 0xFFFF to physical memory address 0x00000 – 0x07FFF 01 Map program address 0x8000 – 0xFFFF to physical memory address 0x08000– 0x0FFFF 10 Map program address 0x8000 – 0xFFFF to physical memory address 0x10000 – 0x17FFF 1:0 MAP[1:0] 01 R/W 11 Map program address 0x8000 – 0xFFFF to physical memory address 0x18000 – 0x1FFFF 6 Reserved bits must always be set to the specified value. Failure to follow this will result in indeterminate behaviour. Not Recommended for New Designs CC2430 8051 CPU : CPU Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 42 of 211 11.3 CPU Registers This section describes the internal registers found in the CPU. 11.3.1 Data Pointers The CC2430 has two data pointers, DPTR0 and DPTR1 to accelerate the movement of data blocks to/from memory. The data pointers are generally used to access CODE or XDATA space e.g. MOVC A,@A+DPTR MOV A,@DPTR. The data pointer select bit, bit 0 in the Data Pointer Select register DPS, chooses which data pointer shall be the active one during execution of an instruction that uses the data pointer, e.g. in one of the above instructions. The data pointers are two bytes wide consisting of the following SFRs: • DPTR0 – DPH0:DPL0 • DPTR1 – DPH1:DPL1 DPH0 (0x83) – Data Pointer 0 High Byte Bit Name Reset R/W Description 7:0 DPH0[7:0] 0 R/W Data pointer 0, high byte DPL0 (0x82) – Data Pointer 0 Low Byte Bit Name Reset R/W Description 7:0 DPL0[7:0] 0 R/W Data pointer 0, low byte DPH1 (0x85) – Data Pointer 1 High Byte Bit Name Reset R/W Description 7:0 DPH1[7:0] 0 R/W Data pointer 1, high byte DPL1 (0x84) – Data Pointer 1 Low Byte Bit Name Reset R/W Description 7:0 DPL1[7:0] 0 R/W Data pointer 1, low byte DPS (0x92) – Data Pointer Select Bit Name Reset R/W Description 7:1 - 0x00 R0 Not used 0 DPS 0 R/W Data pointer select. Selects active data pointer. 0 : DPTR0 1 : DPTR1 11.3.2 Registers R0-R7 The CC2430 provides four register banks (not to be confused with CODE memory space banks that only applies to flash memory organization) of eight registers each. These register banks are mapped in the DATA memory space at addresses 0x00-0x07, 0x08- 0x0F, 0x10-0x17 and 0x18-0x1F (XDATA address range 0xFF00 to 0xFF1F). Each register bank contains the eight 8-bit register R0-R7. The register bank to be used is selected through the Program Status Word PSW.RS[1:0]. Not Recommended for New Designs CC2430 8051 CPU : CPU Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 43 of 211 11.3.3 Program Status Word The Program Status Word (PSW) contains several bits that show the current state of the CPU. The Program Status Word is accessible as an SFR and it is bit-addressable. PSW is shown below and contains the Carry flag, Auxiliary Carry flag for BCD operations, Register Select bits, Overflow flag and Parity flag. Two bits in PSW are uncommitted and can be used as user-defined status flags. PSW (0xD0) – Program Status Word Bit Name Reset R/W Description 7 CY 0 R/W Carry flag. Set to 1 when the last arithmetic operation resulted in a carry (during addition) or borrow (during subtraction), otherwise cleared to 0 by all arithmetic operations. 6 AC 0 R/W Auxiliary carry flag for BCD operations. Set to 1 when the last arithmetic operation resulted in a carry into (during addition) or borrow from (during subtraction) the high order nibble, otherwise cleared to 0 by all arithmetic operations. 5 F0 0 R/W User-defined, bit-addressable Register bank select bits. Selects which set of R7-R0 registers to use from four possible register banks in DATA space. 00 Register Bank 0, 0x00 – 0x07 01 Register Bank 1, 0x08 – 0x0F 10 Register Bank 2, 0x10 – 0x17 4:3 RS[1:0] 00 R/W 11 Register Bank 3, 0x18 – 0x1F 2 OV 0 R/W Overflow flag, set by arithmetic operations. Set to 1 when the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise, the bit is cleared to 0 by all arithmetic operations. 1 F1 0 R/W User-defined, bit-addressable 0 P 0 R/W Parity flag, parity of accumulator set by hardware to 1 if it contains an odd number of 1’s, otherwise it is cleared to 0 11.3.4 Accumulator ACC is the accumulator. This is the source and destination of most arithmetic instructions, data transfers and other instructions. The mnemonic for the accumulator (in instructions involving the accumulator) refers to A instead of ACC. ACC (0xE0) – Accumulator Bit Name Reset R/W Description 7:0 ACC[7:0] 0x00 R/W Accumulator 11.3.5 B Register The B register is used as the second 8-bit argument during execution of multiply and divide instructions. When not used for these purposes it may be used as a scratch-pad register to hold temporary data. B (0xF0) – B Register Bit Name Reset R/W Description 7:0 B[7:0] 0x00 R/W B register. Used in MUL/DIV instructions. Not Recommended for New Designs CC2430 8051 CPU : Instruction Set Summary CC2430 Data Sheet (rev. 2.1) SWRS036F Page 44 of 211 11.3.6 Stack Pointer The stack resides in DATA memory space and grows upwards. The PUSH instruction first increments the Stack Pointer (SP) and then copies the byte into the stack. The Stack Pointer is initialized to 0x07 after a reset and it is incremented once to start from location 0x08 which is the first register (R0) of the second register bank. Thus, in order to use more than one register bank, the SP should be initialized to a different location not used for data storage. SP (0x81) – Stack Pointer Bit Name Reset R/W Description 7:0 SP[7:0] 0x07 R/W Stack Pointer 11.4 Instruction Set Summary The 8051 instruction set is summarized in Table 28. All mnemonics copyrighted © Intel Corporation, 1980. The following conventions are used in the instruction set summary: • Rn – Register R7-R0 of the currently selected register bank. • direct – 8-bit internal data location’s address. This can be DATA area (0x00 – 0x7F) or SFR area (0x80 – 0xFF). • @Ri – 8-bit internal data location, DATA area (0x00 – 0xFF) addressed indirectly through register R1 or R0. • #data – 8-bit constant included in instruction. • #data16 – 16-bit constant included in instruction. • addr16 – 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64 KB CODE memory space. • addr11 – 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 KB page of program memory as the first byte of the following instruction. • rel – Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is –128 to +127 bytes relative to first byte of the following instruction. • bit – direct addressed bit in DATA area or SFR. The instructions that affect CPU flag settings located in PSW are listed in Table 29 on page 49. Note that operations on the PSW register or bits in PSW will also affect the flag settings. Not Recommended for New Designs CC2430 8051 CPU : Instruction Set Summary CC2430 Data Sheet (rev. 2.1) SWRS036F Page 45 of 211 Table 28: Instruction Set Summary Mnemonic Description Hex Opcode Bytes Cycles Arithmetic operations ADD A,Rn Add register to accumulator 28-2F 1 1 ADD A,direct Add direct byte to accumulator 25 2 2 ADD A,@Ri Add indirect RAM to accumulator 26-27 1 2 ADD A,#data Add immediate data to accumulator 24 2 2 ADDC A,Rn Add register to accumulator with carry flag 38-3F 1 1 ADDC A,direct Add direct byte to A with carry flag 35 2 2 ADDC A,@Ri Add indirect RAM to A with carry flag 36-37 1 2 ADDC A,#data Add immediate data to A with carry flag 34 2 2 SUBB A,Rn Subtract register from A with borrow 98-9F 1 1 SUBB A,direct Subtract direct byte from A with borrow 95 2 2 SUBB A,@Ri Subtract indirect RAM from A with borrow 96-97 1 2 SUBB A,#data Subtract immediate data from A with borrow 94 2 2 INC A Increment accumulator 04 1 1 INC Rn Increment register 08-0F 1 2 INC direct Increment direct byte 05 2 3 INC @Ri Increment indirect RAM 06-07 1 3 INC DPTR Increment data pointer A3 1 1 DEC A Decrement accumulator 14 1 1 DEC Rn Decrement register 18-1F 1 2 DEC direct Decrement direct byte 15 2 3 DEC @Ri Decrement indirect RAM 16-17 1 3 MUL AB Multiply A and B A4 1 5 DIV Divide A by B 84 1 5 DA A Decimal adjust accumulator D4 1 1 Not Recommended for New Designs CC2430 8051 CPU : Instruction Set Summary CC2430 Data Sheet (rev. 2.1) SWRS036F Page 46 of 211 Mnemonic Description Hex Opcode Bytes Cycles Logical operations ANL A,Rn AND register to accumulator 58-5F 1 1 ANL A,direct AND direct byte to accumulator 55 2 2 ANL A,@Ri AND indirect RAM to accumulator 56-57 1 2 ANL A,#data AND immediate data to accumulator 54 2 2 ANL direct,A AND accumulator to direct byte 52 2 3 ANL direct,#data AND immediate data to direct byte 53 3 4 ORL A,Rn OR register to accumulator 48-4F 1 1 ORL A,direct OR direct byte to accumulator 45 2 2 ORL A,@Ri OR indirect RAM to accumulator 46-47 1 2 ORL A,#data OR immediate data to accumulator 44 2 2 ORL direct,A OR accumulator to direct byte 42 2 3 ORL direct,#data OR immediate data to direct byte 43 3 4 XRL A,Rn Exclusive OR register to accumulator 68-6F 1 1 XRL A,direct Exclusive OR direct byte to accumulator 65 2 2 XRL A,@Ri Exclusive OR indirect RAM to accumulator 66-67 1 2 XRL A,#data Exclusive OR immediate data to accumulator 64 2 2 XRL direct,A Exclusive OR accumulator to direct byte 62 2 3 XRL direct,#data Exclusive OR immediate data to direct byte 63 3 4 CLR A Clear accumulator E4 1 1 CPL A Complement accumulator F4 1 1 RL A Rotate accumulator left 23 1 1 RLC A Rotate accumulator left through carry 33 1 1 RR A Rotate accumulator right 03 1 1 RRC A Rotate accumulator right through carry 13 1 1 SWAP A Swap nibbles within the accumulator C4 1 1 Not Recommended for New Designs CC2430 8051 CPU : Instruction Set Summary CC2430 Data Sheet (rev. 2.1) SWRS036F Page 47 of 211 Mnemonic Description Hex Opcode Bytes Cycles Data transfers MOV A,Rn Move register to accumulator E8-EF 1 1 MOV A,direct Move direct byte to accumulator E5 2 2 MOV A,@Ri Move indirect RAM to accumulator E6-E7 1 2 MOV A,#data Move immediate data to accumulator 74 2 2 MOV Rn,A Move accumulator to register F8-FF 1 2 MOV Rn,direct Move direct byte to register A8-AF 2 4 MOV Rn,#data Move immediate data to register 78-7F 2 2 MOV direct,A Move accumulator to direct byte F5 2 3 MOV direct,Rn Move register to direct byte 88-8F 2 3 MOV direct1,direct2 Move direct byte to direct byte 85 3 4 MOV direct,@Ri Move indirect RAM to direct byte 86-87 2 4 MOV direct,#data Move immediate data to direct byte 75 3 3 MOV @Ri,A Move accumulator to indirect RAM F6-F7 1 3 MOV @Ri,direct Move direct byte to indirect RAM A6-A7 2 5 MOV @Ri,#data Move immediate data to indirect RAM 76-77 2 3 MOV DPTR,#data16 Load data pointer with a 16-bit constant 90 3 3 MOVC A,@A+DPTR Move code byte relative to DPTR to accumulator 93 1 3 MOVC A,@A+PC Move code byte relative to PC to accumulator 83 1 3 MOVX A,@Ri Move external RAM (8-bit address) to A E2-E3 1 3-10 MOVX A,@DPTR Move external RAM (16-bit address) to A E0 1 3-10 MOVX @Ri,A Move A to external RAM (8-bit address) F2-F3 1 4-11 MOVX @DPTR,A Move A to external RAM (16-bit address) F0 1 4-11 PUSH direct Push direct byte onto stack C0 2 4 POP direct Pop direct byte from stack D0 2 3 XCH A,Rn Exchange register with accumulator C8-CF 1 2 XCH A,direct Exchange direct byte with accumulator C5 2 3 XCH A,@Ri Exchange indirect RAM with accumulator C6-C7 1 3 XCHD A,@Ri Exchange low-order nibble indirect. RAM with A D6-D7 1 3 Not Recommended for New Designs CC2430 8051 CPU : Instruction Set Summary CC2430 Data Sheet (rev. 2.1) SWRS036F Page 48 of 211 Mnemonic Description Hex Opcode Bytes Cycles Program branching ACALL addr11 Absolute subroutine call xxx11 2 6 LCALL addr16 Long subroutine call 12 3 6 RET Return from subroutine 22 1 4 RETI Return from interrupt 32 1 4 AJMP addr11 Absolute jump xxx01 2 3 LJMP addr16 Long jump 02 3 4 SJMP rel Short jump (relative address) 80 2 3 JMP @A+DPTR Jump indirect relative to the DPTR 73 1 2 JZ rel Jump if accumulator is zero 60 2 3 JNZ rel Jump if accumulator is not zero 70 2 3 JC rel Jump if carry flag is set 40 2 3 JNC Jump if carry flag is not set 50 2 3 JB bit,rel Jump if direct bit is set 20 3 4 JNB bit,rel Jump if direct bit is not set 30 3 4 JBC bit,direct rel Jump if direct bit is set and clear bit 10 3 4 CJNE A,direct rel Compare direct byte to A and jump if not equal B5 3 4 CJNE A,#data rel Compare immediate to A and jump if not equal B4 3 4 CJNE Rn,#data rel Compare immediate to reg. and jump if not equal B8-BF 3 4 CJNE @Ri,#data rel Compare immediate to indirect and jump if not equal B6-B7 3 4 DJNZ Rn,rel Decrement register and jump if not zero D8-DF 2 3 DJNZ direct,rel Decrement direct byte and jump if not zero D5 3 4 NOP No operation 00 1 1 Boolean variable operations CLR C Clear carry flag C3 1 1 CLR bit Clear direct bit C2 2 3 SETB C Set carry flag D3 1 1 SETB bit Set direct bit D2 2 3 CPL C Complement carry flag B3 1 1 CPL bit Complement direct bit B2 2 3 ANL C,bit AND direct bit to carry flag 82 2 2 ANL C,/bit AND complement of direct bit to carry B0 2 2 ORL C,bit OR direct bit to carry flag 72 2 2 ORL C,/bit OR complement of direct bit to carry A0 2 2 MOV C,bit Move direct bit to carry flag A2 2 2 MOV bit,C Move carry flag to direct bit 92 2 3 Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 49 of 211 Table 29: Instructions that affect flag settings Instruction CY OV AC ADD x x x ADDC x x x SUBB x x x MUL 0 x - DIV 0 x - DA x - - RRC x - - RLC x - - SETB C 1 - - CLR C x - - CPL C x - - ANL C,bit x - - ANL C,/bit x - - ORL C,bit x - - ORL C,/bit x - - MOV C,bit x - - CJNE x - - “0”=set to 0, “1”=set to 1, “x”=set to 0/1, “-“=not affected 11.5 Interrupts The CPU has 18 interrupt sources. Each source has its own request flag located in a set of Interrupt Flag SFR registers. Each interrupt requested by the corresponding flag can be individually enabled or disabled. The definitions of the interrupt sources and the interrupt vectors are given in Table 30. The interrupts are grouped into a set of priority level groups with selectable priority levels. The interrupt enable registers are described in section 11.5.1 and the interrupt priority settings are described in section 11.5.3 on page 57. 11.5.1 Interrupt Masking Each interrupt can be individually enabled or disabled by the interrupt enable bits in the Interrupt Enable SFRs IEN0, IEN1 and IEN2. The CPU Interrupt Enable SFRs are described below and summarized in Table 30. Note that some peripherals have several events that can generate the interrupt request associated with that peripheral. This applies to Port 0, Port 1, Port 2, Timer 1, Timer2, Timer 3, Timer 4 and Radio. These peripherals have interrupt mask bits for each internal interrupt source in the corresponding SFR registers. In order to enable any of the interrupts in the CC2430, the following steps must be taken: 1. Clear interrupt flags 2. Set individual interrupt enable bit in the peripherals SFR register, if any. 3. Set the corresponding individual, interrupt enable bit in the IEN0, IEN1 or IEN2 registers to 1. 4. Enable global interrupt by setting the EA bit in IEN0 to 1 5. Begin the interrupt service routine at the corresponding vector address of that interrupt. See Table 30 for addresses Figure 10 gives a complete overview of all interrupt sources and associated control and state registers. Shaded boxes are interrupt flags that are automatically cleared by HW when interrupt service routine is called. indicates a one-shot, either due to the level source or due to edge shaping. For the Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 revision E Data Sheet (rev. 2.1) SWRS036F Page 50 of 211 interrupts missing this they are to be treated as level triggered (apply to ports P0, P1 and P2). The switchboxes are shown in default state, and or indicates rising or falling edge detection, i.e. at what time instance the interrupt is generated. As a general rule for pulsed or edge shaped interrupt sources one should clear CPU interrupt flag registers prior to clearing source flag bit, if available, for flags that are not automatically cleared. For level sources one has to clear source prior to clearing CPU flag. Table 30: Interrupts Overview Interrupt number Description Interrupt name Interrupt Vector Interrupt Mask, CPU Interrupt Flag, CPU 0 RF TX FIFO underflow and RX FIFO overflow. RFERR 03h IEN0.RFERRIE TCON.RFERRIF7 1 ADC end of conversion ADC 0Bh IEN0.ADCIE TCON.ADCIF7 2 USART0 RX complete URX0 13h IEN0.URX0IE TCON.URX0IF7 3 USART1 RX complete URX1 1Bh IEN0.URX1IE TCON.URX1IF7 4 AES encryption/decryption complete ENC 23h IEN0.ENCIE S0CON.ENCIF 5 Sleep Timer compare ST 2Bh IEN0.STIE IRCON.STIF 6 Port 2 inputs P2INT 33h IEN2.P2IE IRCON2.P2IF8 7 USART0 TX complete UTX0 3Bh IEN2.UTX0IE IRCON2.UTX0IF 8 DMA transfer complete DMA 43h IEN1.DMAIE IRCON.DMAIF 9 Timer 1 (16-bit) capture/compare/overflow T1 4Bh IEN1.T1IE IRCON.T1IF7,8 10 Timer 2 (MAC Timer) T2 53h IEN1.T2IE IRCON.T2IF7,8 11 Timer 3 (8-bit) compare/overflow T3 5Bh IEN1.T3IE IRCON.T3IF7,8 12 Timer 4 (8-bit) compare/overflow T4 63h IEN1.T4IE IRCON.T4IF7,8 13 Port 0 inputs P0INT 6Bh IEN1.P0IE IRCON.P0IF8 14 USART1 TX complete UTX1 73h IEN2.UTX1IE IRCON2.UTX1IF 15 Port 1 inputs P1INT 7Bh IEN2.P1IE IRCON2.P1IF8 16 RF general interrupts RF 83h IEN2.RFIE S1CON.RFIF8 17 Watchdog overflow in timer mode WDT 8Bh IEN2.WDTIE IRCON2.WDTIF 7 HW cleared when Interrupt Service Routine is called. 8 Additional IRQ mask and IRQ flag bits exists. Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 revision E Data Sheet (rev. 2.1) SWRS036F Page 51 of 211 polling sequence Figure 10: CC2430 interrupt overview Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 revision E Data Sheet (rev. 2.1) SWRS036F Page 52 of 211 IEN0 (0xA8) – Interrupt Enable 0 Bit Name Reset R/W Description Disables all interrupts. 0 No interrupt will be acknowledged 7 EA 0 R/W 1 Each interrupt source is individually enabled or disabled by setting its corresponding enable bit 6 - 0 R0 Not used. Read as 0 STIE – Sleep Timer interrupt enable 0 Interrupt disabled 5 STIE 0 R/W 1 Interrupt enabled ENCIE – AES encryption/decryption interrupt enable 0 Interrupt disabled 4 ENCIE 0 R/W 1 Interrupt enabled URX1IE – USART1 RX interrupt enable 0 Interrupt disabled 3 URX1IE 0 R/W 1 Interrupt enabled URX0IE - USART0 RX interrupt enable 0 Interrupt disabled 2 URX0IE 0 R/W 1 Interrupt enabled ADCIE – ADC interrupt enable 0 Interrupt disabled 1 ADCIE 0 R/W 1 Interrupt enabled RFERRIE – RF TX/RX FIFO interrupt enable 0 Interrupt disabled 0 RFERRIE 0 R/W 1 Interrupt enabled Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 revision E Data Sheet (rev. 2.1) SWRS036F Page 53 of 211 IEN1 (0xB8) – Interrupt Enable 1 Bit Name Reset R/W Description 7:6 - 00 R0 Not used. Read as 0 P0IE – Port 0 interrupt enable 0 Interrupt disabled 5 P0IE 0 R/W 1 Interrupt enabled T4IE - Timer 4 interrupt enable 0 Interrupt disabled 4 T4IE 0 R/W 1 Interrupt enabled T3IE - Timer 3 interrupt enable 0 Interrupt disabled 3 T3IE 0 R/W 1 Interrupt enabled T2IE – Timer 2 interrupt enable 0 Interrupt disabled 2 T2IE 0 R/W 1 Interrupt enabled T1IE – Timer 1 interrupt enable 0 Interrupt disabled 1 T1IE 0 R/W 1 Interrupt enabled DMAIE – DMA transfer interrupt enable 0 Interrupt disabled 0 DMAIE 0 R/W 1 Interrupt enabled IEN2 (0x9A) – Interrupt Enable 2 Bit Name Reset R/W Description 7:6 - 00 R0 Not used. Read as 0 WDTIE – Watchdog timer interrupt enable 0 Interrupt disabled 5 WDTIE 0 R/W 1 Interrupt enabled P1IE– Port 1 interrupt enable 0 Interrupt disabled 4 P1IE 0 R/W 1 Interrupt enabled UTX1IE – USART1 TX interrupt enable 0 Interrupt disabled 3 UTX1IE 0 R/W 1 Interrupt enabled UTX0IE - USART0 TX interrupt enable 0 Interrupt disabled 2 UTX0IE 0 R/W 1 Interrupt enabled P2IE – Port 2 interrupt enable 0 Interrupt disabled 1 P2IE 0 R/W 1 Interrupt enabled RFIE – RF general interrupt enable 0 Interrupt disabled 0 RFIE 0 R/W 1 Interrupt enabled Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 54 of 211 11.5.2 Interrupt Processing When an interrupt occurs, the CPU will vector to the interrupt vector address as shown in Table 30. Once an interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a RETI (return from interrupt instruction). When an RETI is performed, the CPU will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the CPU will also indicate this by setting an interrupt flag bit in the interrupt flag registers. This bit is set regardless of whether the interrupt is enabled or disabled. If the interrupt is enabled when an interrupt flag is set, then on the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector address. Interrupt response will require a varying amount of time depending on the state of the CPU when the interrupt occurs. If the CPU is performing an interrupt service with equal or greater priority, the new interrupt will be pending until it becomes the interrupt with highest priority. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is seven machine cycles. This includes one machine cycle for detecting the interrupt and six cycles to perform the LCALL. TCON (0x88) – Interrupt Flags Bit Name Reset R/W Description URX1IF – USART1 RX interrupt flag. Set to 1 when USART1 RX interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 7 URX1IF 0 R/W H0 1 Interrupt pending 6 - 0 R/W Not used ADCIF – ADC interrupt flag. Set to 1 when ADC interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 5 ADCIF 0 R/W H0 1 Interrupt pending 4 - 0 R/W Not used URX0IF – USART0 RX interrupt flag. Set to 1 when USART0 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 3 URX0IF 0 R/W H0 1 Interrupt pending 2 IT1 1 R/W Reserved. Must always be set to 1. Setting a zero will enable low level interrupt detection, which is almost always the case (one-shot when interrupt request is initiated) RFERRIF – RF TX/RX FIFO interrupt flag. Set to 1 when RFERR interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 1 RFERRIF 0 R/W H0 1 Interrupt pending 0 IT0 1 R/W Reserved. Must always be set to 1. Setting a zero will enable low level interrupt detection, which is almost always the case (one-shot when interrupt request is initiated) Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 55 of 211 S0CON (0x98) – Interrupt Flags 2 Bit Name Reset R/W Description 7:2 - 0x00 R/W Not used ENCIF – AES interrupt. ENC has two interrupt flags, ENCIF_1 and ENCIF_0. Setting one of these flags will request interrupt service. Both flags are set when the AES co-processor requests the interrupt. 0 Interrupt not pending 1 ENCIF_1 0 R/W 1 Interrupt pending ENCIF – AES interrupt. ENC has two interrupt flags, ENCIF_1 and ENCIF_0. Setting one of these flags will request interrupt service. Both flags are set when the AES co-processor requests the interrupt. 0 Interrupt not pending 0 ENCIF_0 0 R/W 1 Interrupt pending S1CON (0x9B) – Interrupt Flags 3 Bit Name Reset R/W Description 7:2 - 0x00 R/W Not used RFIF – RF general interrupt. RF has two interrupt flags, RFIF_1 and RFIF_0. Setting one of these flags will request interrupt service. Both flags are set when the radio requests the interrupt. 0 Interrupt not pending 1 RFIF_1 0 R/W 1 Interrupt pending RFIF – RF general interrupt. RF has two interrupt flags, RFIF_1 and RFIF_0. Setting one of these flags will request interrupt service. Both flags are set when the radio requests the interrupt. 0 Interrupt not pending 0 RFIF_0 0 R/W 1 Interrupt pending Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 56 of 211 IRCON (0xC0) – Interrupt Flags 4 Bit Name Reset R/W Description STIF – Sleep timer interrupt flag 0 Interrupt not pending 7 STIF 0 R/W 1 Interrupt pending 6 - 0 R/W Must be written 0. Writing a 1 will always enable interrupt source. P0IF – Port 0 interrupt flag 0 Interrupt not pending 5 P0IF 0 R/W 1 Interrupt pending T4IF – Timer 4 interrupt flag. Set to 1 when Timer 4 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 4 T4IF 0 R/W H0 1 Interrupt pending T3IF – Timer 3 interrupt flag. Set to 1 when Timer 3 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 3 T3IF 0 R/W H0 1 Interrupt pending T2IF – Timer 2 interrupt flag. Set to 1 when Timer 2 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 2 T2IF 0 R/W H0 1 Interrupt pending T1IF – Timer 1 interrupt flag. Set to 1 when Timer 1 interrupt occurs and cleared when CPU vectors to the interrupt service routine. 0 Interrupt not pending 1 T1IF 0 R/W H0 1 Interrupt pending DMAIF – DMA complete interrupt flag. 0 Interrupt not pending 0 DMAIF 0 R/W 1 Interrupt pending Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 57 of 211 IRCON2 (0xE8) – Interrupt Flags 5 Bit Name Reset R/W Description 7:5 - 00 R/W Not used WDTIF – Watchdog timer interrupt flag. 0 Interrupt not pending 4 WDTIF 0 R/W 1 Interrupt pending P1IF – Port 1 interrupt flag. 0 Interrupt not pending 3 P1IF 0 R/W 1 Interrupt pending UTX1IF – USART1 TX interrupt flag. 0 Interrupt not pending 2 UTX1IF 0 R/W 1 Interrupt pending UTX0IF – USART0 TX interrupt flag. 0 Interrupt not pending 1 UTX0IF 0 R/W 1 Interrupt pending P2IF – Port2 interrupt flag. 0 Interrupt not pending 0 P2IF 0 R/W 1 Interrupt pending 11.5.3 Interrupt Priority The interrupts are grouped into six interrupt priority groups and the priority for each group is set by the registers IP0 and IP1. In order to assign a higher priority to an interrupt, i.e. to its interrupt group, the corresponding bits in IP0 and IP1 must be set as shown in Table 31 on page 58. The interrupt priority groups with assigned interrupt sources are shown in Table 32. Each group is assigned one of four priority levels. While an interrupt service request is in progress, it cannot be interrupted by a lower or same level interrupt. In the case when interrupt requests of the same priority level are received simultaneously, the polling sequence shown in Table 33 is used to resolve the priority of each request. Note that the polling sequence in Figure 10 is the algorithm fond in Table 33, not that polling is among the IP bits as listed in the figure. IP1 (0xB9) – Interrupt Priority 1 Bit Name Reset R/W Description 7:6 - 00 R/W Not used. 5 IP1_IPG5 0 R/W Interrupt group 5, priority control bit 1, refer to Table 32: Interrupt Priority Groups 4 IP1_IPG4 0 R/W Interrupt group 4, priority control bit 1, refer to Table 32: Interrupt Priority Groups 3 IP1_IPG3 0 R/W Interrupt group 3, priority control bit 1, refer to Table 32: Interrupt Priority Groups 2 IP1_IPG2 0 R/W Interrupt group 2, priority control bit 1, refer to Table 32: Interrupt Priority Groups 1 IP1_IPG1 0 R/W Interrupt group 1, priority control bit 1, refer to Table 32: Interrupt Priority Groups 0 IP1_IPG0 0 R/W Interrupt group 0, priority control bit 1, refer to Table 32: Interrupt Priority Groups Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 58 of 211 IP0 (0xA9) – Interrupt Priority 0 Bit Name Reset R/W Description 7:6 - 00 R/W Not used. 5 IP0_IPG5 0 R/W Interrupt group 5, priority control bit 0, refer to Table 32: Interrupt Priority Groups 4 IP0_IPG4 0 R/W Interrupt group 4, priority control bit 0, refer to Table 32: Interrupt Priority Groups 3 IP0_IPG3 0 R/W Interrupt group 3, priority control bit 0, refer to Table 32: Interrupt Priority Groups 2 IP0_IPG2 0 R/W Interrupt group 2, priority control bit 0, refer to Table 32: Interrupt Priority Groups 1 IP0_IPG1 0 R/W Interrupt group 1, priority control bit 0, refer to Table 32: Interrupt Priority Groups 0 IP0_IPG0 0 R/W Interrupt group 0, priority control bit 0, refer to Table 32: Interrupt Priority Groups Table 31: Priority Level Setting IP1_x IP0_x Priority Level 0 0 0 – lowest 0 1 1 1 0 2 1 1 3 – highest Table 32: Interrupt Priority Groups Group Interrupts IPG0 RFERR RF DMA IPG1 ADC T1 P2INT IPG2 URX0 T2 UTX0 IPG3 URX1 T3 UTX1 IPG4 ENC T4 P1INT IPG5 ST P0INT WDT Not Recommended for New Designs CC2430 8051 CPU : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 59 of 211 Table 33: Interrupt Polling Sequence Interrupt number Interrupt name 0 RFERR 16 RF 8 DMA 1 ADC 9 T1 2 URX0 10 T2 3 URX1 11 T3 4 ENC 12 T4 5 ST 13 P0INT 6 P2INT 7 UTX0 14 UTX1 15 P1INT 17 WDT Polling sequence Not Recommended for New Designs CC2430 Debug Interface : Debug Mode CC2430 Data Sheet (rev. 2.1) SWRS036F Page 60 of 211 12 Debug Interface The CC2430 includes a debug interface that provides a two-wire interface to an on-chip debug module. The debug interface allows programming of the on-chip flash and it provides access to memory and registers contents and debug features such as breakpoints, single-stepping and register modification. The debug interface uses the I/O pins P2_1 as Debug Data and P2_2 as Debug Clock during Debug mode. These I/O pins can be used as general purpose I/O only while the device is not in Debug mode. Thus the debug interface does not interfere with any peripheral I/O pins. 12.1 Debug Mode Debug mode is entered by forcing two rising edge transitions on pin P2_2 (Debug Clock) while the RESET_N input is held low. While in Debug mode pin P2_1 is the Debug Data bi-directional pin and P2_2 is the Debug Clock input pin. 12.2 Debug Communication The debug interface uses an SPI-like two-wire interface consisting of the P2_1 (Debug Data) and P2_2 (Debug Clock) pins. Data is driven on the bi-directional Debug Data pin at the positive edge of Debug Clock and data is sampled on the negative edge of this clock. Debug commands are sent by an external host and consist of 1 to 4 output bytes (including command byte) from the host and an optional input byte read by the host. Command and data is transferred with MSB first. Figure 11 shows a timing diagram of data on the debug interface. The first byte of the debug command is a command byte and is encoded as follows: • bits 7 to 3 : instruction code • bits 2 : return input byte to host when high • bits 1 to 0 : number of bytes from host following command byte Figure 11: Debug interface timing diagram 12.3 Debug Commands The debug commands are shown in Table 35. Some of the debug commands are described in further detail in the following sub-sections. 12.4 Debug Lock Bit For software and/or access protection a set of lock bits can be written. This information is contained in the Flash Information page (section 11.2.3 under Flash memory), at location 0x000 and the flash information page can only be accessed through the debug interface. There are three kinds of lock protect bits as described in this section. The LSIZE[2:0] lock protect bits are used to define a section of the flash memory which is write protected. The size of the write protected area can be set by the LSIZE[2:0] lock bits in sizes of eight steps from 0 to 128 KB (all starting from top of flash memory and defining a section below this). The second type of lock protect bits is BBLOCK, which is used to lock the boot sector page (page 0 ranging from address 0 to 0x07FF). When BBLOCK is set to 0, the boot sector page is locked. The third type of lock protect bit is DBGLOCK, which is used to disable hardware debug support through the Debug Interface. When DBGLOCK is set to 0, almost all debug commands are disabled. When the Debug Lock bit, DBGLOCK is set to 0 (see Table 34) all debug commands except CHIP_ERASE, READ_STATUS and GET_CHIP_ID are disabled and will not function. The status of the Debug Lock bit can be read using the READ_STATUS command (see section 12.4.2). Not Recommended for New Designs CC2430 Debug Interface : Debug Lock Bit CC2430 Data Sheet (rev. 2.1) SWRS036F Page 61 of 211 Note that after the Debug Lock bit has changed due to a flash information page write or a flash mass erase, a HALT, RESUME, DEBUG_INSTR or STEP command must be executed so that the Debug Lock value returned by READ_STATUS shows the updated Debug Lock value. For example a dummy NOP DEBUG_INSTR command could be executed. After a device reset, the Debug Lock bit will be updated. Alternatively the chip must be reset and debug mode reentered. The CHIP_ERASE command is used to clear the Debug Lock bit. The lock protect bits are written as a normal flash write to FWDATA (see section 13.3.2), but the Debug Interface needs to select the Flash Information Page first instead of the Flash Main Pages which is the default setting. The Information Page is selected through the Debug Configuration which is written through the Debug Interface only. Refer to section 12.4.1 and Table 36 for details on how the Flash Information Page is selected using the Debug Interface. Table 34 defines the byte containing the flash lock protection bits. Note that this is not an SFR register, but instead the byte stored at location 0x000 in Flash Information Page. Table 34: Flash Lock Protection Bits Definition Bit Name Description 7:5 - Reserved, write as 0 Boot Block Lock 0 Page 0 is write protected 4 BBLOCK 1 Page 0 is writeable, unless LSIZE is 000 Lock Size. Sets the size of the upper Flash area which is writeprotected. Byte sizes and page number are listed below 000 128k bytes (All pages) CC2430-F128 only 001 64k bytes (page 32 - 63) CC2430-F64/128 only 010 32k bytes (page 48 - 63) 011 16k bytes (page 56 - 63) 100 8k bytes (page 60 - 63) 101 4k bytes (page 62 - 63) 110 2k bytes (page 63) 3:1 LSIZE[2:0] 111 0k bytes (no pages) Debug lock bit 0 Disable debug commands 0 DBGLOCK 1 Enable debug commands 12.4.1 Debug Configuration The commands WR_CONFIG and RD_CONFIG are used to access the debug configuration data byte. The format and description of this configuration data is shown in Table 36. 12.4.2 Debug Status A Debug status byte is read using the READ_STATUS command. The format and description of this debug status is shown in Table 37. The READ_STATUS command is used e.g. for polling the status of flash chip erase after a CHIP_ERASE command or oscillator stable status required for debug commands HALT, RESUME, DEBUG_INSTR, STEP_REPLACE and STEP_INSTR. Not Recommended for New Designs CC2430 Debug Interface : Debug Lock Bit CC2430 Data Sheet (rev. 2.1) SWRS036F Page 62 of 211 Table 35: Debug Commands Command Instruction code Description CHIP_ERASE 0001 0000 Perform flash chip erase (mass erase) and clear lock bits. If any other command, except READ_STATUS, is issued, then the use of CHIP_ERASE is disabled. WR_CONFIG 0001 1001 Write configuration data. Refer to Table 36 for details RD_CONFIG 0010 0100 Read configuration data. Returns value set by WR_CONFIG command. GET_PC 0010 1000 Return value of 16-bit program counter. Returns 2 bytes regardless of value of bit 2 in instruction code READ_STATUS 0011 0000 Read status byte. Refer to Table 37 SET_HW_BRKPNT 0011 1111 Set hardware breakpoint HALT 0100 0100 Halt CPU operation RESUME 0100 1100 Resume CPU operation. The CPU must be in halted state for this command to be run. DEBUG_INSTR 0101 01yy Run debug instruction. The supplied instruction will be executed by the CPU without incrementing the program counter. The CPU must be in halted state for this command to be run. Note that yy is number of bytes following the command byte, i.e. how many bytes the CPU instruction has (see Table 28) STEP_INSTR 0101 1100 Step CPU instruction. The CPU will execute the next instruction from program memory and increment the program counter after execution. The CPU must be in halted state for this command to be run. STEP_REPLACE 0110 01yy Step and replace CPU instruction. The supplied instruction will be executed by the CPU instead of the next instruction in program memory. The program counter will be incremented after execution. The CPU must be in halted state for this command to be run. Note that yy is number of bytes following the command byte, i.e. how many bytes the CPU instruction has (see Table 28) GET_CHIP_ID 0110 1000 Return value of 16-bit chip ID and version number. Returns 2 bytes regardless of value of bit 2 of instruction code Not Recommended for New Designs CC2430 Debug Interface : Debug Lock Bit CC2430 Data Sheet (rev. 2.1) SWRS036F Page 63 of 211 Table 36: Debug Configuration Bit Name Description 7-4 - Not used, must be set to zero. Disable timers. Disable timer operation. This overrides the TIMER_SUSPEND bit and its function. 0 Do not disable timers 3 TIMERS_OFF 1 Disable timers DMA pause 0 Enable DMA transfers 2 DMA_PAUSE 1 Pause all DMA transfers Suspend timers. Timer operation is suspended for debug instructions and if a step instruction is a branch. If not suspended these instructions would result an extra timer count during the clock cycle in which the branch is executed 0 Do not suspend timers 1 TIMER_SUSPEND 1 Suspend timers Select flash information page (2KB lowest part of flash) 0 Select flash main page (32, 64, or 128 KB) 0 SEL_FLASH_INFO_PAGE 1 Select flash information page (2KB) Table 37: Debug Status Bit Name Description Flash chip erase done 0 Chip erase in progress 7 CHIP_ERASE_DONE 1 Chip erase done PCON idle 0 CPU is running 6 PCON_IDLE 1 CPU is idle (clock gated) CPU halted 0 CPU running 5 CPU_HALTED 1 CPU halted Power Mode 0 0 Power Mode 1-3 selected 4 POWER_MODE_0 1 Power Mode 0 selected Halt status. Returns cause of last CPU halt 0 CPU was halted by HALT debug command 3 HALT_STATUS 1 CPU was halted by hardware breakpoint Debug locked. Returns value of DBGLOCK bit 0 Debug interface is not locked 2 DEBUG_LOCKED 1 Debug interface is locked Oscillators stable. This bit represents the status of the SLEEP.XSOC_STB and SLEEP.HFRC_STB register bits. 0 Oscillators not stable 1 OSCILLATOR_STABLE 1 Oscillators stable Stack overflow. This bit indicates when the CPU writes to DATA memory space at address 0xFF which is possibly a stack overflow 0 No stack overflow 0 STACK_OVERFLOW 1 Stack overflow 12.4.3 Hardware Breakpoints The debug command SET_HW_BRKPNT is used to set a hardware breakpoint. The CC2430 supports up to four hardware breakpoints. When a hardware breakpoint is enabled it will compare the CPU address bus with the breakpoint. When a match occurs, the CPU is halted. When issuing the SET_HW_BRKPNT, the external host must supply three data bytes that define the hardware breakpoint. The hardware breakpoint itself consists of 18 bits while three bits are used for control purposes. The format of the three data bytes for the SET_HW_BRKPNT command is as follows. Not Recommended for New Designs CC2430 Debug Interface : Debug interface and Power Modes CC2430 Data Sheet (rev. 2.1) SWRS036F Page 64 of 211 The first data byte consists of the following: • bits 7-5 : unused • bits 4-3 : breakpoint number; 0-3 • bit 2 : 1=enable, 0=disable • bits 1-0 : Memory bank bits. Bits 17-16 of hardware breakpoint. The second data byte consists of bits 15-8 of the hardware breakpoint. The third data byte consists of bits 7-0 of the hardware breakpoint. Thus the second and third data byte sets the CPU CODE address to stop execution at. 12.4.4 Flash Programming Programming of the on-chip flash is performed via the debug interface. The external host must initially send instructions using the DEBUG_INSTR debug command to perform the flash programming with the Flash Controller as described in section 13.3 on page 71. 12.5 Debug interface and Power Modes The debug interface can be used in all power modes, but with limitations. When enabling a power mode the system will act as normally with the exeption that the digital voltage regulator is not turned off, thus power consumption when debugging power modes is higher than expected. The limitation when debugging power modes 2 and 3 is that the chip will stop operating when woke up, thus a HALT and a RESUME command is needed to continue the SW execution. Pleas note that PM1 works as expected, also after chip is woke up. Not Recommended for New Designs CC2430 Peripherals : Power Management and clocks CC2430 Data Sheet (rev. 2.1) SWRS036F Page 65 of 211 13 Peripherals In the following sub-sections each CC2430 peripheral is described in detail. 13.1 Power Management and clocks This section describes the Power Management Controller. The Power Management Controller controls the use of power modes and clock control to achieve lowpower operation. 13.1.1 Power Management Introduction The CC2430 uses different operating modes, or power modes, to allow low-power operation. Ultra-low-power operation is obtained by turning off power supply to modules to avoid static (leakage) power consumption and also by using clock gating and turning off oscillators to reduce dynamic power consumption. The various operating modes are enumerated and are to be designated as power modes 0, 1, 2, and 3 (PM0..3). The CC2430 four major power modes are called PM0, PM1, PM2 and PM3. PM0 is the active mode while PM3 has the lowest power consumption. The power modes impact on system operation is shown in Table 38, together with voltage regulator and oscillator options. Table 38: Power Modes Power Mode Highfrequency oscillator Low- frequency oscillator Voltage regulator (digital) Configuration A None B 32 MHz XOSC C 16 MHz RCOSC A None B 32.753 kHz RCOSC C 32.768 kHz XOSC PM0 B, C B or C ON PM1 A B or C ON PM2 A B or C OFF PM3 A A OFF PM0 : The full functional mode. The voltage regulator to the digital core is on and either the 16 MHz RC oscillator or the 32 MHz crystal oscillator or both are running. Either the 32.753 kHz RC oscillator or the 32.768 kHz crystal oscillator is running. PM1 : The voltage regulator to the digital part is on. Neither the 32 MHz crystal oscillator nor the 16 MHz RC oscillator are running. Either the 32.753 kHz RC oscillator or the 32.768 kHz crystal oscillator is running. The system will go to PM0 on reset or an external interrupt or when the sleep timer expires. PM2 : The voltage regulator to the digital core is turned off. Neither the 32 MHz crystal oscillator nor the 16 MHz RC oscillator are running. Either the 32.768 kHz RC oscillator or the 32.753 kHz crystal oscillator is running. The system will go to PM0 on reset or an external interrupt or when the sleep timer expires. PM3 : The voltage regulator to the digital core is turned off. None of the oscillators are running. The system will go to PM0 on reset or an external interrupt. Note:The voltage regulator above refers to the digital regulator. The analog voltage regulator must be disabled separately through the RF register RFPWR. 13.1.1.1 PM0 PM0 is the full functional mode of operation where the CPU, peripherals and RF transceiver are active. The digital voltage regulator is turned on. This is also refered to as active mode. PM0 is used for normal operation. It should be noted that by enabling the PCON.IDLE bit while in PM0 (SLEEP.MODE=0x00) the CPU core stops from operating. All other peripherals will function as normal and CPU core will be waked up by any enabled interrupt. Not Recommended for New Designs CC2430 Peripherals : Power Management and clocks CC2430 Data Sheet (rev. 2.1) SWRS036F Page 66 of 211 13.1.1.2 PM1 In PM1, the high-frequency oscillators are powered down (32MHz XOSC and 16MHz RC OSC). The voltage regulator and the enabled 32 kHz oscillator is on. When PM1 is entered, a power down sequence is run. When the device is taken out of PM1 to PM0, the highfrequency oscillators are started. The device will run on the 16MHz RC oscillator until 32MHz is selected as source by SW. PM1 is used when the expected time until a wakeup event is relatively short (less than 3 ms) since PM1 uses a fast power down/up sequence. 13.1.1.3 PM2 PM2 has the second lowest power consumption. In PM2 the power-on reset, external interrupts, 32.768 kHz oscillator and sleep timer peripherals are active. I/O pins retain the I/O mode and output value set before entering PM2. All other internal circuits are powered down. The voltage regulator is also turned off. When PM2 is entered, a power down sequence is run. PM2 is typically entered when using the sleep timer as the wakeup event, and also combined with external interrupts. PM2 should typically be choosen, compared to PM1, when sleep times exeeds 3 ms. Using less sleep time will not reduce system power consumption compared to using PM1. 13.1.1.4 PM3 PM3 is used to achieve the operating mode with the lowest power consumption. In PM3 all internal circuits that are powered from the voltage regulator are turned off (basically all digital modules, the only exeption are interrupt detection and POR level sensing). The internal voltage regulator and all oscillators are also turned off. Reset (POR or external) and external I/O port interrupts are the only functions that are operating in this mode. I/O pins retain the I/O mode and output value set before entering PM3. A reset condition or an enabled external IO interrupt event will wake the device up and place it into PM0 (an external interrupt will start from where it entered PM3, while a reset returns to start of program execution). The content of RAM and registers is partially preserved in this mode (see section 13.1.6). PM3 uses the same power down/up sequence as PM2. PM3 is used to achieve ultra low power consumption when waiting for an external event. 13.1.2 Power Management Control The required power mode is selected by the MODE bits in the SLEEP control register. Setting the SFR register PCON.IDLE bit after setting the MODE bits, enters the selected sleep mode. An enabled interrupt from port pins or sleep timer or a power-on reset will wake the device from other power modes and bring it into PM0 by resetting the MODE bits. 13.1.3 Power Management Registers This section describes the Power Management registers. All register bits retain their previous values when entering PM2 or PM3 unless otherwise stated. Not Recommended for New Designs CC2430 Peripherals : Power Management and clocks CC2430 Data Sheet (rev. 2.1) SWRS036F Page 67 of 211 PCON (0x87) – Power Mode Control Bit Name Reset R/W Description 7:2 - 0x00 R/W Not used. 1 - 0 R0 Not used, always read as 0. 0 IDLE 0 R0/W H0 Power mode control. Writing a 1 to this bit forces CC2430 to enter the power mode set by SLEEP.MODE (note that MODE = 0x00 will stop CPU core, no peripherals, activity when this bit is enabled). This bit is always read as 0 All enabled interrupts will clear this bit when active and CC2430 will reenter PM0. SLEEP (0xBE) – Sleep Mode Control Bit Name Reset R/W Description 7 OSC32K_CALDIS 0 R/W Disable 32 kHz RC oscillator calibration 0 – 32 kHz RC oscillator calibration is enabled 1 – 32 kHz RC oscillator calibration is disabled. The setting of this bit to 1 does not take effect until high-frequency RC oscillator is chosen as source for system clock, i.e. CLKCON.OSC set to 1. Note: this bit is not retained in PM2 and PM3. After re-entry to PM0 from PM2 or PM3 this bit will be at the reset value 0 6 XOSC_STB 0 R XOSC stable status: 0 – XOSC is not powered up or not yet stable 1 – XOSC is powered up and stable. Note that an additionl wait time of 64 μs is needed after this bit has been set until true stable state is reached. 5 HFRC_STB 0 R High-frequency RC oscillator (HF RCOSC) stable status: 0 – HF RCOSC is not powered up or not yet stable 1 – HF RCOSC is powered up and stable 4:3 RST[1:0] XX R Status bit indicating the cause of the last reset. If there are multiple resets, the register will only contain the last event. 00 – Power-on reset 01 – External reset 10 – Watchdog timer reset 2 OSC_PD 1 R/W H0 High-frequency (32 MHz) crystal oscillator and High-frequency (16 MHz) RC oscillator power down setting. If there is a calibration in progress and the CPU attempts to set this bit, the bit will be updated at the end of calibration: 0 – Both oscillators powered up 1 – Oscillator not selected by CLKCON.OSC bit powered down 1:0 MODE[1:0] 00 R/W Power mode setting: 00 – Power mode 0 01 – Power mode 1 10 – Power mode 2 11 – Power mode 3 Not Recommended for New Designs CC2430 Peripherals : Power Management and clocks CC2430 Data Sheet (rev. 2.1) SWRS036F Page 68 of 211 Figure 12: Clock System Overview 13.1.4 Oscillators and clocks The CC2430 has one internal system clock. The source for the system clock can be either a 16 MHz RC oscillator or a 32 MHz crystal oscillator. Clock control is performed using the CLKCON SFR register. The system clock also feeds all 8051 peripherals (as described in section 6). There is also one 32 kHz clock source that can either be a RC oscillator or a crystal oscillator, also controlled by the CLKCON register. The choice of oscillator allows a trade-off between high-accuracy in the case of the crystal oscillator and low power consumption when the RC oscillator is used. Note that operation of the RF transceiver requires that the 32 MHz crystal oscillator is used. 13.1.4.1 Oscillators Figure 12 gives an overview of the clock system with available clock sources. Two high frequency oscillators are present in the device: Not Recommended for New Designs CC2430 Peripherals : Power Management and clocks CC2430 Data Sheet (rev. 2.1) SWRS036F Page 69 of 211 • 32 MHz crystal oscillator. • 16 MHz RC oscillator. The 32 MHz crystal oscillator startup time may be too long for some applications, therefore the device can run on the 16 MHz RC oscillator until crystal oscillator is stable. The 16 MHz RC oscillator consumes less power than the crystal oscillator, but since it is not as accurate as the crystal oscillator it can not be used for RF transceiver operation. Two low frequency oscillators are present in the device: • 32 kHz crystal oscillator • 32 kHz RC oscillator The 32 kHz crystal oscillator is designed to operate at 32.768 kHz and provide a stable clock signal for systems requiring time accuracy. The 32 kHz RC oscillator run at 32.753 kHz when calibrated. The calibration can only take place when 32 MHz crystal oscillator is enabled, and this calibration can be disabled by enabling the SLEEP.OSC32K_CALDIS bit. The 32 kHz RC oscillator should be used to reduce cost and power consumption compared to the 32 kHz crystal oscillator solution. The two low frequency oscillators can not be operated simultaneously. 13.1.4.2 System clock The system clock is derived from the selected system clock source, which is the 32 MHz crystal oscillator or the 16 MHz RC oscillator. The CLKCON.OSC bit selects the source of the system clock. Note that to use the RF transceiver the 32 MHz crystal oscillator must be selected and stable. Note that changing the CLKCON.OSC bit does not happen instantaneously. This is caused by the requirement to have stable clocks prior to actually changing the clock source. Also note that CLKCON.CLKSPD bit reflect the frequency of the system clock and thus is a mirror of the CLKCON.OSC bit. When the SLEEP.XOSC_STB is 1, the 32 MHz crystal oscillator is reported stable by the system. This may however not be the case and a safety time of additional 64 μs should be used prior to selecting 32 MHz clock as source for the system clock. Failure to do so may lead to system crash. E.g. a loop of CPU NOP instructions should be used to suspend further system operation prior to selecting XOSC as clock source. The oscillator not selected as the system clock source, will be set in power-down mode by setting SLEEP.OSC_PD to 1 (the default state). Thus the 16MHz RC oscillator may be turned off when the 32 MHz crystal oscillator has been selected as system clock source and vice versa. When SLEEP.OSC_PD is 0, both oscillators are powered up and running. When the 32 MHz crystal oscillator is selected as system clock source and the 16 MHz RC oscillator is also powered up, the 16 MHz RC oscillator will be continuously calibrated to ensure clock stability over supply voltage and operating temperature. This calibration is not performed when the 16 MHz RC oscillator itself is chosen as system clock source. 13.1.4.3 32 kHz oscillators Two 32 kHz oscillators are present in the device as clock sources for the 32 kHz clock: • 32.768 kHz crystal oscillator • 32 kHz RC oscillator By default, after a reset, the 32 kHz RC oscillator is enabled and selected as the 32 kHz clock source. The RC oscillator consumes less power, but is less accurate than the 32.768 kHz crystal oscillator. Refer to Table 9 and Table 10 on page 15 for characteristics of these oscillators. The 32 kHz clock runs the Sleep Timer and Watchdog Timer and used as a strobe in Timer2 (MAC timer) for when to calculate Sleep Timer sleep time. Selecting which oscillator source to use as source for the 32 kHz is performed with the CLKCON.OSC32K register bit. The CLKCON.OSC32K register bit must only be changed while using the 16 MHz RC oscillator as the system clock source. When the 32 MHz crystal oscillator is selected and it is stable, i.e. SLEEP.XOSC_STB is 1, calibration of the 32 kHz RC oscillator is continuously performed and 32kHz clock is derived from 32 MHz clock. This calibration is not performed in other power modes than PM0. The result of the calibration is a RC clock running at 32.753 kHz. The 32 kHz RC oscillator calibration may take up to 2 ms to complete. When entering low power modes PM1 or PM2 an ongoing calibration must be completed before the low power mode is entered. In some applications this extra delay may be unacceptable and Not Recommended for New Designs CC2430 Peripherals : Power Management and clocks CC2430 Data Sheet (rev. 2.1) SWRS036F Page 70 of 211 therefore the calibration may be disabled by setting register bit SLEEP.OSC32K_CALDIS to 1. Note that any ongoing calibration will be completed when a 1 is written to SLEEP.OSC32K_CALDIS. 13.1.4.4 Oscillator and Clock Registers This section describes the Oscillator and Clock registers. All register bits retain their previous values when entering PM2 or PM3 unless otherwise stated. CLKCON (0xC6) – Clock Control Bit Name Reset R/W Description 7 OSC32K 1 R/W 32 kHz clock oscillator select. The 16 MHz high frequency RC oscillator must be selected as system clock source when this bit is to be changed. 0 – 32.768 kHz crystal oscillator 1 – 32 kHz RC oscillator Note: this bit is not retained in PM2 and PM3. After re-entry to PM0 from PM2 or PM3 this bit will be at the reset value 1. 6 OSC 1 R/W System clock oscillator select: 0 – 32 MHz crystal oscillator 1 – 16 MHz high frequency RC oscillator This setting will only take effect when the selected oscillator is powered up and stable. If the XOSC oscillator is not powered up, it should be enabled by SLEEP.OSC_PD bit prior to selecting it as souorce. Note that there is an additional wait time (64 μs) from SLEEP.XOSC_STB set until XOSC can be selected as source. If RC osc is to be the source and it is powered down, setting this bit will turn it on. 5:3 TICKSPD[2:0] 001 R/W Timer ticks output setting, can not be higher than system clock setting given by OSC bit setting 000 – 32 MHz 001 – 16 MHz 010 – 8 MHz 011 – 4 MHz 100 – 2 MHz 101 – 1 MHz 110 – 500 kHz 111 – 250 kHz 2:1 - 00 R Reserved. 0 CLKSPD 1 R Clock Speed. Indicates current system clock frequency. The value of this bit is set by the OSC bit setting 0 – 32 MHz 1 – 16 MHz This bit is updated when clock source selected with the OSC is stable 13.1.5 Timer Tick generation The power management controller generates a tick or enable signal for the peripheral timers, thus acting as a prescaler for the timers. This is a global clock division for Timer 1, Timer 3 and Timer 4. The tick speed is programmed from 0.25 MHz to 32 MHz in the CLKCON.TICKSPD register. It should be noted that TICKSPD must not be set to a higher frequency than system clock. 13.1.6 Data Retention In power modes PM2 and PM3, power is removed from most of the internal circuitry. However parts of SRAM will retain its contents. The content of internal registers is also retained in PM2 and PM3. The XDATA memory locations 0xF000- 0xFFFF (4096 bytes) retains data in PM2 and PM3. Please note the exception as given below. The XDATA memory locations 0xE000- 0xEFFF (4096 bytes) and the area 0xFD56- Not Recommended for New Designs CC2430 Peripherals : Reset CC2430 Data Sheet (rev. 2.1) SWRS036F Page 71 of 211 0xFEFF (426 bytes) will lose all data when PM2 or PM3 is entered. These locations will contain undefined data when PM0 is reentered. The registers which retain their contents are the CPU registers, peripheral registers and RF registers, unless otherwise specified for a given register bit field. Switching to the lowpower modes PM2 or PM3 appears transparent to software with the following exceptions: • The RF TXFIFO/RXFIFO contents are not retained when entering PM2 or PM3. • Watchdog timer 15-bit counter is reset to 0x0000 when entering PM2 or PM3. 13.2 Reset The CC2430 has four reset sources. The following events generate a reset: • Forcing RESET_N input pin low • A power-on reset condition • A brown-out reset condition • Watchdog timer reset condition The initial conditions after a reset are as follows: • I/O pins are configured as inputs with pullup • CPU program counter is loaded with 0x0000 and program execution starts at this address • All peripheral registers are initialized to their reset values (refer to register descriptions) • Watchdog timer is disabled 13.2.1 Power On Reset and Brown Out Detector The CC2430 includes a Power On Reset (POR) providing correct initialization during device power-on. Also includes is a Brown Out Detector (BOD) operating on the regulated 1.8V digital power supply only, The BOD will protect the memory contents during supply voltage variations which cause the regulated 1.8V power to drop below the minimum level required by flash memory and SRAM. When power is initially applied to the CC2430 the Power On Reset (POR) and Brown Out Detector (BOD) will hold the device in reset state until the supply voltage reaches above the Power On Reset and Brown Out voltages. Figure 13 shows the POR/BOD operation with the 1.8V (typical) regulated supply voltage together with the active low reset signals BOD_RESET and POR_RESET shown in the bottom of the figure (note that signals are not available, just for ilustaration of events). The cause of the last reset can read from the register bits SLEEP.RST. It should be noted that a BOD reset will be read as a POR reset. 0 1.8V REGULATED UNREGULATED POR RESET ASSERT FALLING VDD BOD RESET ASSERT POR RESET DEASSERT RISING VDD VOLT POR OUTPUT BOD RESET POR RESET X X X X X X Figure 13 : Power On Reset and Brown Out Detector Operation 13.3 Flash Controller The CC2430 contains 32, 64 or 128 KB flash memory for storage of program code. The flash memory is programmable from the user software and through the debug interface. See Table 22 on page 26 for flash memory size options. Not Recommended for New Designs CC2430 Peripherals : Flash Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 72 of 211 The Flash Controller handles writing and erasing the embedded flash memory. The embedded flash memory consists of 64 pages of 2048 bytes each (CC2430F128). The flash controller has the following features: • 32-bit word programmable • Page erase • Lock bits for write-protection and code security • Flash page erase timing 20 ms • Flash chip erase timing 200 ms • Flash write timing (4 bytes) 20 μs • Auto power-down during low-frequency CPU clock read access 13.3.1 Flash Memory Organization The flash memory is divided into 64 flash pages consisting of 2 KB each (all versions have 2 KB pages, but the number of pages differs and here 128 KB is referred). A flash page is the smallest erasable unit in the memory, while a 32 bit word is the smallest writable unit that may be addressed through the flash controller. When performing write operations, the flash memory is word-addressable using a 15-bit address written to the address registers FADDRH:FADDRL. When performing page erase operations, the flash memory page to be erased is addressed through the register bits FADDRH[6:1]. Note the difference in addressing the flash memory; when accessed by the CPU to read code or data, the flash memory is byteaddressable. When accessed by the Flash Controller, the flash memory is wordaddressable, where a word consists of 32 bits. The next sections describe the procedures for flash write and flash page erase in detail. 13.3.2 Flash Write Data is written to the flash memory by using a program command initiated by writing the Flash Control register, FCTL. Flash write operations can program any number of words in the flash memory, single words or block of words in sequence starting at start address (set by FADDRH:FADDRL). Each location may be programmed twice before the next erase must take place, meanaing that a bit in a word can change from 1-1 or 1-0 but not 0-1 (writing a 0 to 1 will be ignored). This can be utilized by writing to different parts of the word with masking without having to do a page erase before writing. After a page erase or chip erase (through debug interface), the erased bits are set to 1. A write operation is performed using one out of two methods; • Through DMA transfer • Through CPU SFR access. The DMA transfer method is the preferred way to write to the flash memory. A write operation is initiated by writing a 1 to FCTL.WRITE. The start address for writing the 32-bit word is given by FADDRH:FADDRL. During each single write operation FCTL.SWBSY is set high. During a write operation, the byte written to the FWDATA register is forwarded to the flash memory. The flash memory is 32-bit word-programmable, meaning data is written as 32-bit words. The first byte written to FWDATA is the LSB of the 32-bit word. The actual writing to flash memory takes place each time four bytes have been written to FWDATA, meaning that all Flash writes must be 4 bytes aligned. The CPU will not be able to access the flash, e.g. to read program code, while a flash write operation is in progress. Therefore the program code executing the flash write must be executed from RAM, meaning that the program code must reside in the area 0xE000 to 0xFEFF in Unified CODE memory space. When a flash write operation is executed from RAM, the CPU continues to execute code from the next instruction after initiation of the flash write operation (FCTL.WRITE=1). The FCTL.SWBSY bit must be 0 before accessing the flash after a flash write, otherwise an access violation occurs. This also means that FCTL.SWBSY must be 0 before program execution can continue from a location in flash memory. Not Recommended for New Designs CC2430 Peripherals : Flash Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 73 of 211 13.3.2.1 DMA Flash Write When using DMA write operations, the data to be written into flash is stored in the XDATA memory space (RAM or FLASH). A DMA channel is configured to read the data to be written from memory, source address, and write this data to the Flash Write Data register, FWDATA, fixed destination address, with the DMA trigger event FLASH (TRIG[4:0]=10010 in DMA configuration) enabled. Thus the Flash Controller will trigger a DMA transfer when the Flash Write Data register, FWDATA, is ready to receive new data. The DMA channel should be configured to perform single mode, byte size transfers with source address set to start of data block and destination address to fixed FWDATA (note that the block size, LEN in configuration data, must be 4 bytes aligned). High priority should also be ensured for the DMA channel so it is not interrupted in the write process. If interrupted for more than 40 μs the write will not take place as write bit, FCTL.WRITE, will be reset. When the DMA channel is armed, starting a flash write by setting FCTL.WRITE to 1 will trigger the first DMA transfer (DMA and Flash controller handles the reset of the transfer). Figure 15 shows an example of how a DMA channel is configured and how a DMA transfer is initiated to write a block of data from a location in XDATA to flash memory, assuming the code is executed from RAM (unified CODE). DMA Flash Write from XDATA memory When performing DMA flash write while executing code from within flash memory, the instruction that triggers the first DMA trigger event FLASH (TRIG[4:0]=10010 DMA in configuration) must be aligned on a 4-byte boundary. Figure 14 shows an example of code that correctly aligns the instruction for triggering DMA (Note that this code is IAR specific). ; Write flash and generate Flash DMA trigger ; Code is executed from flash memory ; #include “ioCC2430.h” MODULE flashDmaTrigger.s51 RSEG RCODE (2) PUBLIC halFlashDmaTrigger FUNCTION halFlashDmaTrigger, 0203H halFlashDmaTrigger: ORL FCTL, #0x02; RET; END; Figure 14: Flash write using DMA from flash Not Recommended for New Designs CC2430 Peripherals : Flash Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 74 of 211 Figure 15: Flash write using DMA 13.3.2.2 CPU Flash Write The CPU can also write directly to the flash when executing program code from RAM using Unified CODE memory space. The CPU writes data to the Flash Write Data register, FWDATA. The flash memory is written each time four bytes have been written to FWDATA, and FCTL.WRITE bit set to 1. The CPU can poll the FCTL.SWBSY status to determine when the flash is ready for four more bytes to be written to FWDATA. Note that all flash writes needs to be four bytes aligned. Also note that there exist a timeout periode for writing to one flash word, thus writing all four bytes to the FWDATA register has to end within 40 μs after FCTL.SWBSY went low in repeated writes, or after FCTL.WRITE set for first time write. The FCTL.BUSY=0 flag will indicate if the time out happened or not. If FCTL.BUSY= 0 the write ended and one have to start over again by enabling the FCTL.WRITE bit. The address is set for word to write to, but FWDATA has to be updated again with the 4 bytes that casuse the time out to happen. Performing CPU flash write The steps required to start a CPU flash write operation are shown in Figure 16 on page 75. Note that code must be run from RAM in unified CODE memory space. Setup DMA channel: SRCADDR= DESTADDRR=FWDATA VLEN=0 LEN= WORDSIZE=byte TMODE=single mode TRIG=FLASH SRCINC=yes DESTINC=no IRQMASK=yes M8=0 PRIORITY=high Arm DMA Channel Start flash write Setup flash address Not Recommended for New Designs CC2430 Peripherals : Flash Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 75 of 211 Figure 16: Performing CPU Flash write 13.3.3 Flash Page Erase After a flash page erase, all bytes in the erased page are set to 1. A page erase is initiated by setting FCTL.ERASE to 1. The page addressed by FADDRH[6:1] is erased when a page erase is initiated. Note that if a page erase is initiated simultaneously with a page write, i.e. FCTL.WRITE is set to 1, the page erase will be performed before the page write operation. The FCTL.BUSY bit can be polled to see when the page erase has completed. Note: If flash page erase operation is performed from within flash memory and the watchdog timer is enabled, a watchdog timer interval must be selected that is longer than 20 ms, the duration of the flash page erase operation, so that the CPU will manage to clear the watchdog timer. Performing flash erase from flash memory The steps required to perform a flash page erase from within flash memory are outlined in Figure 17. Note that, while executing program code from within flash memory, when a flash erase or write operation is initiated, program execution will resume from the next instruction when the flash controller has completed the operation. The flash erase operation requires that the instruction that starts the erase i.e. writing to FCTL.ERASE is followed by a NOP instruction as shown in the example code. Omitting the NOP instruction after the flash erase operation will lead to undefined behavior. ; Erase page in flash memory ; Assumes 32 MHz system clock is used ; CLR EA ;mask interrupts C1: MOV A,FCTL ;wait until flash controller is ready JB ACC.7,C1 MOV FADDRH,#00h ;setup flash address high MOV FWT,#2Ah ;setup flash timing MOV FCTL,#01h ;erase page NOP ;must always execute a NOP after erase RET ;continues here when flash is ready Figure 17: Flash page erase performed from flash memory Not Recommended for New Designs CC2430 Peripherals : Flash Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 76 of 211 13.3.4 Flash Write Timing The Flash Controller contains a timing generator, which controls the timing sequence of flash write and erase operations. The timing generator uses the information set in the Flash Write Timing register, FWT.FWT[5:0], to set the internal timing. FWT.FWT[5:0] must be set to a value according to the currently selected CPU clock frequency. The value set in the FWT.FWT[5:0] shall be set according to the CPU clock frequency. The initial value held in FWT.FWT[5:0] after a reset is 0x2A which corresponds to 32 MHz CPU clock frequency. The FWT values for the 16 MHz and 32 MHz CPU clock frequencies are given in Table 39. Table 39: Flash timing (FWT) values CPU clock frequency (MHz) FWT 16 0x15 32 0x2A 13.3.5 Flash DMA trigger The Flash DMA trigger is activated when flash data written to the FWDATA register has been written to the specified location in the flash memory, thus indicating that the flash controller is ready to accept new data to be written to FWDATA. In order to start first transfer one has to set the FCTL.WRITE bit to 1. The DMA and the flash controller will then handle all transfer automatically for the defined block of data (LEN in DMA configuration). It is further important that the DMA is armed prior to setting the FCTL.WRITE bit and that the trigger source set to FLASH (TRIG[4:0]=10010) and that the DMA has high priority so the transfer in not interrupted. If interrupted for more than 40 μs the write will not complete as write flag is reset (not allowed to access one word for write for more than 40 μs thus protection to turn the write off). 13.3.6 Flash Controller Registers The Flash Controller registers are described in this section. Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 77 of 211 FCTL (0xAE) – Flash Control Bit Name Reset R/W Description 7 BUSY 0 R Indicates that write or erase is in operation 0 No write or erase operation active 1 Write or erase operation activated 6 SWBSY 0 R Indicates that current word write is busy; avoid writing to FWDATA register while this is true 0 Ready to accept data 1 Busy 5 - 0 R/W Not used. 4 CONTRD 0 R/W Continuous read enable mode 0 Avoid wasting power; turn on read enables to flash only when needed 1 Enable continuous read enables to flash when read is to be done. Reduces internal switching of read enables, but greatly increases power consumption. 3:2 0 R/W Not used. 1 WRITE 0 R0/W Write. Start writing word at location given by FADDRH:FADDRL. If ERASE is set to 1, a page erase of the whole page addressed by FADDRH, is performed before the write. 0 ERASE 0 R0/W Page Erase. Erase page that is given by FADDRH[6:1] FWDATA (0xAF) – Flash Write Data Bit Name Reset R/W Description 7:0 FWDATA[7:0] 0x00 R/W Flash write data. Data written to FWDATA is written to flash when FCTL.WRITE is set to 1. FADDRH (0xAD) – Flash Address High Byte Bit Name Reset R/W Description 7 - 0 R/W Not used 6:0 FADDRH[6:0] 0x00 R/W Page address / High byte of flash word address Bits 6:1 will select which page to access. FADDRL (0xAC) – Flash Address Low Byte Bit Name Reset R/W Description 7:0 FADDRL[7:0] 0x00 R/W Low byte of flash word address FWT (0xAB) – Flash Write Timing Bit Name Reset R/W Description 7:6 - 00 R/W Not used 5:0 FWT[5:0] 0x2A R/W Flash Write Timing. Controls flash timing generator. 13.4 I/O ports The CC2430 has 21 digital input/output pins that can be configured as general purpose digital I/O or as peripheral I/O signals connected to the ADC, Timers or USART peripherals. The usage of the I/O ports is fully configurable from user software through a set of configuration registers. The I/O ports have the following key features: Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 78 of 211 • 21 digital input/output pins • General purpose I/O or peripheral I/O • Pull-up or pull-down capability on inputs • External interrupt capability The external interrupt capability is available on all 21 I/O pins. Thus external devices may generate interrupts if required. The external interrupt feature can also be used to wake up from sleep modes. 13.4.1 Unused I/O pins Unused I/O pins should have a defined level and not be left floating. One way to do this is to leave the pin unconnected and configure the pin as a general purpose I/O input with pull-up resistor. This is also the state of all pins after reset (note that only P2[2] has pull-up during reset). Alternatively the pin can be configured as a general purpose I/O output. In both cases the pin should not be connected directly to VDD or GND in order to avoid excessive power consumption. 13.4.2 Low I/O Supply Voltage In applications where the digital I/O power supply voltage pin DVDD is below 2.6 V, the register bit PICTL.PADSC should be set to 1 in order to obtain output DC characteristics specified in section 7.16. 13.4.3 General Purpose I/O When used as general purpose I/O, the pins are organized as three 8-bit ports, ports 0-2, denoted P0, P1 and P2. P0 and P1 are complete 8-bit wide ports while P2 has only five usable bits. All ports are both bit- and byte addressable through the SFR registers P0, P1 and P2. Each port pin can individually be set to operate as a general purpose I/O or as a peripheral I/O. The output drive strength is 4 mA on all outputs, except for the two high-drive outputs, P1_0 and P1_1, which each have 20 mA output drive strength. The registers PxSEL where x is the port number 0-2 are used to configure each pin in a port as either a general purpose I/O pin or as a peripheral I/O signal. By default, after a reset, all digital input/output pins are configured as general-purpose input pins. To change the direction of a port pin, at any time, the registers PxDIR are used to set each port pin to be either an input or an output. Thus by setting the appropriate bit within PxDIR, to 1 the corresponding pin becomes an output. When reading the port registers P0, P1 and P2, the logic values on the input pins are returned regardless of the pin configuration. This does not apply during the execution of read-modify-write instructions. The readmodify- write instructions are: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ and MOV, CLR or SETB. Operating on a port registers the following is true: When the destination is an individual bit in a port register P0, P1 or P2 the value of the register, not the value on the pin, is read, modified, and written back to the port register. When used as an input, the general purpose I/O port pins can be configured to have a pullup, pull-down or tri-state mode of operation. By default, after a reset, inputs are configured as inputs with pull-up. To deselect the pull-up or pull-down function on an input the appropriate bit within the PxINP must be set to 1. The I/O port pins P1_0 and P1_1 do not have pullup/ pull-down capability. In power modes PM2 and PM3 the I/O pins retain the I/O mode and output value (if applicable) that was set when PM2/3 was entered. 13.4.4 General Purpose I/O Interrupts General purpose I/O pins configured as inputs can be used to generate interrupts. The interrupts can be configured to trigger on either a rising or falling edge of the external signal. Each of the P0, P1 and P2 ports have separate interrupt enable bits common for all bits within the port located in the IEN1-2 registers as follows: • IEN1.P0IE : P0 interrupt enable • IEN2.P1IE : P1 interrupt enable • IEN2.P2IE : P2 interrupt enable In addition to these common interrupt enables, the bits within each port have interrupt enables located in I/O port SFR registers. Each bit within P1 has an individual interrupt enable. In P0 the low-order nibble and the high-order Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 79 of 211 nibble have their individual interrupt enables. For the P2_0 – P2_4 inputs there is a common interrupt enable. When an interrupt condition occurs on one of the general purpose I/O pins, the corresponding interrupt status flag in the P0- P2 interrupt flag registers, P0IFG , P1IFG or P2IFG will be set to 1. The interrupt status flag is set regardless of whether the pin has its interrupt enable set. When an interrupt is serviced the interrupt status flag is cleared by writing a 0 to that flag, and this flag must be cleared prior to clearing the CPU port interrupt flag (PxIF). The I/O SFR registers used for interrupts are described in section 13.4.9 on page 82. The registers are summarized below: • P1IEN : P1 interrupt enables • PICTL : P0/P2 interrupt enables and P0-2 edge configuration • P0IFG : P0 interrupt flags • P1IFG : P1 interrupt flags • P2IFG : P2 interrupt flags 13.4.5 General Purpose I/O DMA When used as general purpose I/O pins, the P0 and P1 ports are each associated with one DMA trigger. These DMA triggers are IOC_0 for P0 and IOC_1 for P1 as shown in Table 41 on page 94. The IOC_0 or IOC_1 DMA trigger is activated when an input transition occurs on one of the P0 or P1 pins respectively. Note that input transitions on pins configured as general purpose I/O inputs only will produce the DMA trigger. Note that port registers P0 and P1 are mapped to XDATA memory space (see Table 24 on page 35). Therefore these registers are reachable for DMA transfers. Port register P2 is not reachable for DMA transfers. 13.4.6 Peripheral I/O This section describes how the digital I/O pins are configured as peripheral I/Os. For each peripheral unit that can interface with an external system through the digital input/output pins, a description of how peripheral I/Os are configured is given in the following subsections. In general, setting the appropriate PxSEL bits to 1 is required to select peripheral I/O function on a digital I/O pin. Note that peripheral units have two alternative locations for their I/O pins, refer to Table 40. Also note that as a general rule only two peripherials can be used per IO Port at a time. Priority can be set between these if conflicting settings regarding IO mapping is present. Priority among unlisted peripherial units is undefined and should not be used (P2SEL.PRIxP1 and P2DIR.PRIP0 bits). All combinations not causing conlicts can be combined. Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 80 of 211 Table 40: Peripheral I/O Pin Mapping Periphery / P0 P1 P2 Function 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 ADC A7 A6 A5 A4 A3 A2 A1 A0 T USART0 SPI C SS M0 MI Alt. 2 M0 MI C SS USART0 UART RT CT TX RX Alt. 2 TX RX RT CT USART1 SPI MI M0 C SS Alt. 2 MI M0 C SS USART1 UART RX TX RT CT Alt. 2 RX TX RT CT TIMER1 2 1 0 Alt. 2 0 1 2 TIMER3 1 0 Alt. 2 1 0 TIMER4 1 0 Alt. 2 1 0 32.768 kHz XOSC Q2 Q1 DEBUG D C D D 13.4.6.1 Timer 1 PERCFG.T1CFG selects whether to use alternative 1 or alternative 2 locations. In Table 40, the Timer 1 signals are shown as the following: • 0 : Channel 0 capture/compare pin • 1 : Channel 1 capture/compare pin • 2 : Channel 2 capture/compare pin P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0. When set to 10 or 11 the timer 1 channels have precedence. P2SEL.PRI1P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to port 1. The timer 1 channels have precedence when the former is set low and the latter is set high. 13.4.6.2 Timer 3 PERCFG.T3CFG selects whether to use alternative 1 or alternative 2 locations. In Table 40, the Timer 3 signals are shown as the following: • 0 : Channel 0 compare pin • 1 : Channel 1 compare pin P2SEL.PRI2P1 selects the order of precedence when assigning several peripherals to port 1. The timer 3 channels have precedence when the bit is set. 13.4.6.3 Timer 4 PERCFG.T4CFG selects whether to use alternative 1 or alternative 2 locations. In Table 40, the Timer 4 signals are shown as the following: • 0 : Channel 0 compare pin • 1 : Channel 1 compare pin P2SEL.PRI1P1 selects the order of precedence when assigning several peripherals to port 1. The timer 4 channels have precedence when the bit is set. Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 81 of 211 13.4.6.4 USART0 The SFR register bit PERCFG.U0CFG selects whether to use alternative 1 or alternative 2 locations. In Table 40, the USART0 signals are shown as follows: UART: • RX : RXDATA • TX : TXDATA • RT : RTS • CT : CTS SPI: • MI : MISO • MO : MOSI • C : SCK • SS : SSN P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0. When set to 00, USART0 has precedence. Note that if UART mode is selected and hardware flow control is disabled, USART1 or timer 1 will have precedence to use ports P0_4 and P0_5. P2SEL.PRI3P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals to port 1. USART0 has precedence when both are set to 0. Note that if UART mode is selected and hardware flow control is disabled, timer 1 or timer 3 will have precedence to use ports P1_2 and P1_3. 13.4.6.5 USART1 The SFR register bit PERCFG.U1CFG selects whether to use alternative 1 or alternative 2 locations. In Table 40, the USART1 signals are shown as follows: UART: • RX : RXDATA • TX : TXDATA • RT : RTS • CT : CTS SPI: • MI : MISO • MO : MOSI • C : SCK • SS : SSN P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to port 0. When set to 01, USART1 has precedence. Note that if UART mode is selected and hardware flow control is disabled, USART0 or timer 1 will have precedence to use ports P0_2 and P0_3. P2SEL.PRI3P1 and P2SEL.PRI2P1 select the order of precedence when assigning several peripherals to port 1. USART1 has precedence when the former is set to 1 and the latter is set to 0. Note that if UART mode is selected and hardware flow control is disabled, USART0 or timer 3 will have precedence to use ports P2_4 and P2_5. 13.4.6.6 ADC When using the ADC, Port 0 pins must be configured as ADC inputs. Up to eight ADC inputs can be used. To configure a Port 0 pin to be used as an ADC input the corresponding bit in the ADCCFG register must be set to 1. The default values in this register select the Port 0 pins as non-ADC input i.e. digital input/outputs. The settings in the ADCCFG register override the settings in P0SEL. The ADC can be configured to use the general-purpose I/O pin P2_0 as an external trigger to start conversions. P2_0 must be configured as a general-purpose I/O in input mode, when being used for ADC external trigger. Refer to section 13.9 on page 126 for a detailed description of use of the ADC. 13.4.7 Debug interface Ports P2_1 and P2_2 are used for debug data and clock signals, respectively. These are shown as DD (debug data) and DC (debug clock) in Table 40. When the debug interface is in use, P2DIR should select these pins as inputs. The state of P2SEL is overridden by the debug interface. Also, the direction is overridden when the chip changes the direction to supply the external host with data. Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 82 of 211 13.4.8 32.768 kHz XOSC input Ports P2_3 and P2_4 are used to connect an external 32.768 kHz crystal. These port pins will be used by the 32.768 kHz crystal oscillator when CLKCON.OSC32K is low, regardless of register settings. The port pins will be set in analog mode when CLKCON.OSC32K is low. 13.4.9 Radio Test Output Signals For debug purposes and to some degree CC2420 pin compability, the RFSTATUS.SFD, RFSTATUS.FIFO, RFSTATUS.FIFOP and RFSTATUS.CCA bits can be output onto P1.7 – P1.4 I/O pins to monitor the status of these signals. These test output signals are selected by the IOCFG0, IOCFG1 and IOCFG2 registers. The debug signals are output to the following I/O pins: • P1.4 – FIFO • P1.5 – FIFOP • P1.6 – SFD • P1.7 – CCA Configuring this mode has precedence over other settings in the IOC, and these pins will be assigned the above signals and forced to be outputs. 13.4.10 I/O registers The registers for the I/O ports are described in this section. The registers are: • P0 Port 0 • P1 Port 1 • P2 Port 2 • PERCFG Peripheral control register • ADCCFG ADC input configuration register • P0SEL Port 0 function select register • P1SEL Port 1 function select register • P2SEL Port 2 function select register • P0DIR Port 0 direction register • P1DIR Port 1 direction register • P2DIR Port 2 direction register • P0INP Port 0 input mode register • P1INP Port 1 input mode register • P2INP Port 2 input mode register • P0IFG Port 0 interrupt status flag register • P1IFG Port 1 interrupt status flag register • P2IFG Port 2 interrupt status flag register • PICTL Interrupt mask and edge register • P1IEN Port 1 interrupt mask register P0 (0x80) – Port 0 Bit Name Reset R/W Description 7:0 P0[7:0] 0xFF R/W Port 0. General purpose I/O port. Bit-addressable. P1 (0x90) – Port 1 Bit Name Reset R/W Description 7:0 P1[7:0] 0xFF R/W Port 1. General purpose I/O port. Bit-addressable. Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 83 of 211 P2 (0xA0) – Port 2 Bit Name Reset R/W Description 7:5 - 000 R0 Not used 4:0 P2[4:0] 0x1F R/W Port 2. General purpose I/O port. Bit-addressable. PERCFG (0xF1) – Peripheral Control Bit Name Reset R/W Description 7 - 0 R0 Not used Timer 1 I/O location 0 Alternative 1 location 6 T1CFG 0 R/W 1 Alternative 2 location Timer 3 I/O location 0 Alternative 1 location 5 T3CFG 0 R/W 1 Alternative 2 location Timer 4 I/O location 0 Alternative 1 location 4 T4CFG 0 R/W 1 Alternative 2 location 3:2 - 00 R0 Not used USART1 I/O location 0 Alternative 1 location 1 U1CFG 0 R/W 1 Alternative 2 location USART0 I/O location 0 Alternative 1 location 0 U0CFG 0 R/W 1 Alternative 2 location ADCCFG (0xF2) – ADC Input Configuration Bit Name Reset R/W Description ADC input configuration. ADCCFG[7:0] select P0_7 - P0_0 as ADC inputs AIN7 – AIN0 0 ADC input disabled 7:0 ADCCFG[7:0] 0x00 R/W 1 ADC input enabled P0SEL (0xF3) – Port 0 Function Select Bit Name Reset R/W Description P0_7 to P0_0 function select 0 General purpose I/O 7:0 SELP0_[7:0] 0x00 R/W 1 Peripheral function P1SEL (0xF4) – Port 1 Function Select Bit Name Reset R/W Description P1_7 to P1_0 function select 0 General purpose I/O 7:0 SELP1_[7:0] 0x00 R/W 1 Peripheral function Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 84 of 211 P2SEL (0xF5) – Port 2 Function Select Bit Name Reset R/W Description 7 - 0 R0 Not used Port 1 peripheral priority control. These bits shall determine which module has priority in the case when modules are assigned to the same pins. 0 USART0 has priority 6 PRI3P1 0 R/W 1 USART1 has priority Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns USART1 and timer 3 to the same pins. 0 USART1 has priority 5 PRI2P1 0 R/W 1 Timer 3 has priority Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns timer 1 and timer 4 to the same pins. 0 Timer 1 has priority 4 PRI1P1 0 R/W 1 Timer 4 has priority Port 1 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns USART0 and timer 1 to the same pins. 0 USART0 has priority 3 PRI0P1 0 R/W 1 Timer 1 has priority P2_4 function select 0 General purpose I/O 2 SELP2_4 0 R/W 1 Peripheral function P2_3 function select 0 General purpose I/O 1 SELP2_3 0 R/W 1 Peripheral function P2_0 function select 0 General purpose I/O 0 SELP2_0 0 R/W 1 Peripheral function P0DIR (0xFD) – Port 0 Direction Bit Name Reset R/W Description P0_7 to P0_0 I/O direction 0 Input 7:0 DIRP0_[7:0] 0x00 R/W 1 Output P1DIR (0xFE) – Port 1 Direction Bit Name Reset R/W Description P1_7 to P1_0 I/O direction 0 Input 7:0 DIRP1_[7:0] 0x00 R/W 1 Output Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 85 of 211 P2DIR (0xFF) – Port 2 Direction Bit Name Reset R/W Description Port 0 peripheral priority control. These bits shall determine the order of priority in the case when PERCFG assigns several peripherals to the same pins 00 USART0 has priority over USART1 01 USART1 has priority OVER Timer1 10 Timer 1 channels 0 and 1has priority over USART1 7:6 PRIP0[1:0] 00 R/W 11 Timer 1 channel 2 has priority over USART0 5 - 0 R0 Not used P2_4 to P2_0 I/O direction 0 Input 4:0 DIRP2_[4:0] 00000 R/W 1 Output P0INP (0x8F) – Port 0 Input Mode Bit Name Reset R/W Description P0_7 to P0_0 I/O input mode 0 Pull-up / pull-down (see P2INP (0xF7) – Port 2 Input Mode) 7:0 MDP0_[7:0] 0x00 R/W 1 Tristate P1INP (0xF6) – Port 1 Input Mode Bit Name Reset R/W Description P1_7 to P1_2 I/O input mode 0 Pull-up / pull-down (see P2INP (0xF7) – Port 2 Input Mode) 7:2 MDP1_[7:2] 0x00 R/W 1 Tristate 1:0 - 00 R0 Not used P2INP (0xF7) – Port 2 Input Mode Bit Name Reset R/W Description Port 2 pull-up/down select. Selects function for all Port 2 pins configured as pull-up/pull-down inputs. 0 Pull-up 7 PDUP2 0 R/W 1 Pull-down Port 1 pull-up/down select. Selects function for all Port 1 pins configured as pull-up/pull-down inputs. 0 Pull-up 6 PDUP1 0 R/W 1 Pull-down Port 0 pull-up/down select. Selects function for all Port 0 pins configured as pull-up/pull-down inputs. 0 Pull-up 5 PDUP0 0 R/W 1 Pull-down P2_4 to P2_0 I/O input mode 0 Pull-up / pull-down 4:0 MDP2_[4:0] 00000 R/W 1 Tristate Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 86 of 211 P0IFG (0x89) – Port 0 Interrupt Status Flag Bit Name Reset R/W Description 7:0 P0IF[7:0] 0x00 R/W0 Port 0, inputs 7 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set. P1IFG (0x8A) – Port 1 Interrupt Status Flag Bit Name Reset R/W Description 7:0 P1IF[7:0] 0x00 R/W0 Port 1, inputs 7 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set. P2IFG (0x8B) – Port 2 Interrupt Status Flag Bit Name Reset R/W Description 7:5 - 000 R0 Not used. 4:0 P2IF[4:0] 0x00 R/W0 Port 2, inputs 4 to 0 interrupt status flags. When an input port pin has an interrupt request pending, the corresponding flag bit will be set. Not Recommended for New Designs CC2430 Peripherals : I/O ports CC2430 Data Sheet (rev. 2.1) SWRS036F Page 87 of 211 PICTL (0x8C) – Port Interrupt Control Bit Name Reset R/W Description 7 - 0 R0 Not used 6 PADSC 0 R/W Drive strength control for I/O pins in output mode. Selects output drive capability to account for low I/O supply voltage on pin DVDD (this to ensure same drive strength at lower voltages as is on higher). 0 Minimum drive capability. DVDD equal or greater than 2.6V 1 Maximum drive capability. DVDD less than 2.6V Port 2, inputs 4 to 0 interrupt enable. This bit enables interrupt requests for the port 2 inputs 4 to 0. 0 Interrupts are disabled 5 P2IEN 0 R/W 1 Interrupts are enabled Port 0, inputs 7 to 4 interrupt enable. This bit enables interrupt requests for the port 0 inputs 7 to 4. 0 Interrupts are disabled 4 P0IENH 0 R/W 1 Interrupts are enabled Port 0, inputs 3 to 0 interrupt enable. This bit enables interrupt requests for the port 0 inputs 3 to 0. 0 Interrupts are disabled 3 P0IENL 0 R/W 1 Interrupts are enabled Port 2, inputs 4 to 0 interrupt configuration. This bit selects the interrupt request condition for all port 2 inputs 0 Rising edge on input gives interrupt 2 P2ICON 0 R/W 1 Falling edge on input gives interrupt Port 1, inputs 7 to 0 interrupt configuration. This bit selects the interrupt request condition for all port 1 inputs 0 Rising edge on input gives interrupt 1 P1ICON 0 R/W 1 Falling edge on input gives interrupt Port 0, inputs 7 to 0 interrupt configuration. This bit selects the interrupt request condition for all port 0 inputs 0 Rising edge on input gives interrupt 0 P0ICON 0 R/W 1 Falling edge on input gives interrupt P1IEN (0x8D) – Port 1 Interrupt Mask Bit Name Reset R/W Description Port P1_7 to P1_0 interrupt enable 0 Interrupts are disabled 7:0 P1_[7:0]IEN 0x00 R/W 1 Interrupts are enabled Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 88 of 211 13.5 DMA Controller The CC2430 includes a direct memory access (DMA) controller, which can be used to relieve the 8051 CPU core of handling data movement operations thus achieving high overall performance with good power efficiency. The DMA controller can move data from a peripheral unit such as ADC or RF transceiver to memory with minimum CPU intervention. The DMA controller coordinates all DMA transfers, ensuring that DMA requests are prioritized appropriately relative to each other and CPU memory access. The DMA controller contains a number of programmable DMA channels for memory-memory data movement. The DMA controller controls data transfers over the entire address range in XDATA memory space. Since most of the SFR registers are mapped into the DMA memory space, these flexible DMA channels can be used to unburden the CPU in innovative ways, e.g. feed a USART with data from memory or periodically transfer samples between ADC and memory, etc. Use of the DMA can also reduce system power consumption by keeping the CPU in a low-power mode without having to wake up to move data to or from a peripheral unit (see section 13.1.1.1 for CPU low power mode). Note that section 11.2.3 describes which SFR registers that are not mapped into XDATA memory space. The main features of the DMA controller are as follows: • Five independent DMA channels • Three configurable levels of DMA channel priority • 31 configurable transfer trigger events • Independent control of source and destination address • Single, block and repeated transfer modes • Supports length field in transfer data setting variable transfer length • Can operate in either word-size or bytesize mode 13.5.1 DMA Operation There are five DMA channels available in the DMA controller numbered channel 0 to channel 4. Each DMA channel can move data from one place within the DMA memory space to another i.e. between XDATA locations. In order to use a DMA channel it must first be configured as described in sections 13.5.2 and 13.5.3. Figure 18 shows the DMA state diagram. Once a DMA channel has been configured it must be armed before any transfers are allowed to be initiated. A DMA channel is armed by setting the appropriate bit in the DMA Channel Arm register DMAARM. When a DMA channel is armed a transfer will begin when the configured DMA trigger event occurs. Note that the time to arm one channel (i.e. get configuration data) takes 9 system clocks, thus if DMAARM bit set and a trigger appears within the time it takes to configure the channel the trigger will be lost. If more than one DMA channels are armed simultaneously, the time for all channels to be configured will be longer (sequential read from memory). If all 5 are armed it will take 45 system clocks and channel 1 will first be ready, then channel 2 and lastly channel 0 (all within the last 8 system clocks). There are 31 possible DMA trigger events, e.g. UART transfer, Timer overflow etc. The trigger event to be used by a DMA channel is set by the DMA channel configuration thus no knowledge of this is available until after configuration has been read. The DMA trigger events are listed in Table 41. In addition to starting a DMA transfer through the DMA trigger events, the user software may force a DMA transfer to begin by setting the corresponding DMAREQ bit. Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 89 of 211 Figure 18: DMA Operation 13.5.2 DMA Configuration Parameters Setup and control of the DMA operation is performed by the user software. This section describes the parameters which must be configured before a DMA channel can be used. Section 13.5.3 on page 92 describes how the parameters are set up in software and passed to the DMA controller. The behavior of each of the five DMA channels is configured with the following parameters: Source address: The first address from which the DMA channel should read data. Destination address: The first address to which the DMA channel should write the data Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 90 of 211 read from the source address. The user must ensure that the destination is writable. Transfer count: The number of transfers to perform before rearming or disarming the DMA channel and alerting the CPU with an interrupt request. The length can be defined in the configuration or it can be defined as described next as VLEN setting. VLEN setting: The DMA channel is capable of variable length transfers using the first byte or word to set the transfer length. When doing this, various options regarding how to count number of bytes to transfer are available. Priority: The priority of the DMA transfers for the DMA channel in respect to the CPU and other DMA channels and access ports. Trigger event: All DMA transfers are initiated by so-called DMA trigger events. This trigger either starts a DMA block transfer or a single DMA transfer. In addition to the configured trigger, a DMA channel can always be triggered by setting its designated DMAREQ.DMAREQx flag. The DMA trigger sources are described in Table 41 on page 94. Source and Destination Increment: The source and destination addresses can be controlled to increment or decrement or not change. Transfer mode: The transfer mode determines whether the transfer should be a single transfer or a block transfer, or repeated versions of these. Byte or word transfers: Determines whether each DMA transfer should be 8-bit (byte) or 16-bit (word). Interrupt Mask: An interrupt request is generated upon completion of the DMA transfer. The interrupt mask bit controls if the interrupt generation is enabled or disabled. M8: Decide whether to use seven or eight bits of length byte for transfer length. This is only applicable when doing byte transfers. A detailed description of all configuration parameters are given in the sections 13.5.2.1 to 13.5.2.11. 13.5.2.1 Source Address The address in XDATA memory where the DMA channel shall start to read data. 13.5.2.2 Destination Address The first address to which the DMA channel should write the data read from the source address. The user must ensure that the destination is writable. 13.5.2.3 Transfer Count The number of bytes/words needed to be transferred for the DMA transfer to be complete. When the transfer count is reached, the DMA controller rearms or disarms the DMA channel and alerts the CPU with an interrupt request. The transfer count can be defined in the configuration or it can be defined as a variable length described in the next section. 13.5.2.4 VLEN Setting The DMA channel is capable of using the first byte or word (for word, bits 12:0 are used) in source data as the transfer length. This allows variable length transfers. When using variable length transfer, various options regarding how to count number of bytes to transfer is given. In any case, the transfer count (LEN) setting is used as maximum transfer count. If the transfer length specified by the first byte or word is greater than LEN, then LEN bytes/words will be transferred. When using variable length transfers, then LEN should be set to the largest allowed transfer length plus one. Note that the M8 bit (see page 92) is only used when byte size transfers are chosen. Options which can be set with VLEN are the following: 1. Transfer number of bytes/words commanded by first byte/word + 1 (transfers the length byte/word, and then as many bytes/words as dictated by length byte/word) 2. Transfer number of bytes/words commanded by first byte/word 3. Transfer number of bytes/words commanded by first byte/word + 2 (transfers the length byte/word, and then as many bytes/words as dictated by length byte/word + 1) Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 91 of 211 4. Transfer number of bytes/words commanded by first byte/word + 3 (transfers the length byte/word, and then as many bytes/words as dictated by length byte/word + 2) Figure 19 shows the VLEN options. LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n LENGTH=n byte/word 1 byte/word 2 byte/word 3 byte/word n-1 byte/word n byte/word n+1 byte/word n+1 byte/word n+2 VLEN=001 VLEN=010 VLEN=011 VLEN=100 Figure 19: Variable Length (VLEN) Transfer Options 13.5.2.5 Trigger Event Each DMA channel can be set up to sense on a single trigger. This field determines which trigger the DMA channel shall sense. 13.5.2.6 Source and Destination Increment When the DMA channel is armed or rearmed the source and destination addresses are transferred to internal address pointers. The possibilities for address increment are : • Increment by zero. The address pointer shall remain fixed after each transfer. • Increment by one. The address pointer shall increment one count after each transfer. • Increment by two. The address pointer shall increment two counts after each transfer. • Decrement by one. The address pointer shall decrement one count after each transfer. 13.5.2.7 DMA Transfer Mode The transfer mode determines how the DMA channel behaves when it starts transferring data. There are four transfer modes described below: Single: On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After the number of transfers specified by the transfer count, are completed, the CPU is notified and the DMA channel is disarmed. Block: On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified and the DMA channel is disarmed. Repeated single: On a trigger a single DMA transfer occurs and the DMA channel awaits the next trigger. After the number of transfers specified by the transfer count are completed, the CPU is notified and the DMA channel is rearmed. Repeated block: On a trigger the number of DMA transfers specified by the transfer count is performed as quickly as possible, after which the CPU is notified and the DMA channel is rearmed. Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 92 of 211 13.5.2.8 DMA Priority A DMA priority is configurable for each DMA channel. The DMA priority is used to determine the winner in the case of multiple simultaneous internal memory requests, and whether the DMA memory access should have priority or not over a simultaneous CPU memory access. In case of an internal tie, a round-robin scheme is used to ensure access for all. There are three levels of DMA priority: High: Highest internal priority. DMA access will always prevail over CPU access. Normal: Second highest internal priority. This guarantees that DMA access prevails over CPU on at least every second try. Low: Lowest internal priority. DMA access will always defer to a CPU access. 13.5.2.9 Byte or Word transfers Determines whether 8-bit (byte) or 16-bit (word) are done. 13.5.2.10 Interrupt mask Upon completing a DMA transfer, the channel can generate an interrupt to the processor. This bit will mask the interrupt. 13.5.2.11 Mode 8 setting This field determines whether to use 7 or 8 bits of length byte for transfer length. Only applicable when doing byte transfers. 13.5.3 DMA Configuration Setup The DMA channel parameters such as address mode, transfer mode and priority described in the previous section have to be configured before a DMA channel can be armed and activated. The parameters are not configured directly through SFR registers, but instead they are written in a special DMA configuration data structure in memory. Each DMA channel in use requires its own DMA configuration data structure. The DMA configuration data structure consists of eight bytes and is described in section 13.5.6 on page 93. A DMA configuration data structure may reside at any location decided upon by the user software, and the address location is passed to the DMA controller through a set of SFRs DMAxCFGH:DMAxCFGL, Once a channel has been armed, the DMA controller will read the configuration data structure for that channel, given by the address in DMAxCFGH:DMAxCFGL. It is important to note that the method for specifying the start address for the DMA configuration data structure differs between DMA channel 0 and DMA channels 1-4 as follows: DMA0CFGH:DMA0CFGL gives the start address for DMA channel 0 configuration data structure. DMA1CFGH:DMA1CFGL gives the start address for DMA channel 1 configuration data structure followed by channel 2-4 configuration data structures. Thus the DMA controller expects the DMA configuration data structures for DMA channels 1-4 to lie in a contiguous area in memory starting at the address held in DMA1CFGH:DMA1CFGL and consisting of 32 bytes. 13.5.4 Stopping DMA Transfers Ongoing DMA transfer or armed DMA channels will be aborted using the DMAARM register to disarm the DMA channel. One or more DMA channels are aborted by writing a 1 to DMAARM.ABORT register bit, and at the same time select which DMA channels to abort by setting the corresponding, DMAARM.DMAARMx bits to 1. When setting DMAARM.ABORT to 1, the DMAARM.DMAARMx bits for non-aborted channels must be written as 0. Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 93 of 211 13.5.5 DMA Interrupts Each DMA channel can be configured to generate an interrupt to the CPU upon completing a DMA transfer. This is accomplished with the IRQMASK bit in the channel configuration. The corresponding interrupt flag in the DMAIRQ SFR register will be set when the interrupt is generated. Regardless of the IRQMASK bit in the channel configuration, the interrupt flag will be set upon DMA channel complete. Thus software should always check (and clear) this register when rearming a channel with a changed IRQMASK setting. Failure to do so could generate an interrupt based on the stored interrupt flag. 13.5.6 DMA Configuration Data Structure For each DMA channel, the DMA configuration data structure consists of eight bytes. The configuration data structure is described in Table 42. 13.5.7 DMA memory access The DMA data transfer is affected by endian convention. This as the memory system use Big-Endian in XDATA memory, while Little- Endian is used in SFR memory. This must be accounted for in compilers. Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 94 of 211 Table 41: DMA Trigger Sources DMA Trigger number DMA Trigger name Functional unit Description 0 NONE DMA No trigger, setting DMAREQ.DMAREQx bit starts transfer 1 PREV DMA DMA channel is triggered by completion of previous channel 2 T1_CH0 Timer 1 Timer 1, compare, channel 0 3 T1_CH1 Timer 1 Timer 1, compare, channel 1 4 T1_CH2 Timer 1 Timer 1, compare, channel 2 5 T2_COMP Timer 2 Timer 2, compare 6 T2_OVFL Timer 2 Timer 2, overflow 7 T3_CH0 Timer 3 Timer 3, compare, channel 0 8 T3_CH1 Timer 3 Timer 3, compare, channel 1 9 T4_CH0 Timer 4 Timer 4, compare, channel 0 10 T4_CH1 Timer 4 Timer 4, compare, channel 1 11 ST Sleep Timer Sleep Timer compare 12 IOC_0 IO Controller Port 0 I/O pin input transition9 13 IOC_1 IO Controller Port 1 I/O pin input transition9 14 URX0 USART0 USART0 RX complete 15 UTX0 USART0 USART0 TX complete 16 URX1 USART1 USART1 RX complete 17 UTX1 USART1 USART1 TX complete 18 FLASH Flash controller Flash data write complete 19 RADIO Radio RF packet byte received/transmit 20 ADC_CHALL ADC ADC end of a conversion in a sequence, sample ready 21 ADC_CH11 ADC ADC end of conversion channel 0 in sequence, sample ready 22 ADC_CH21 ADC ADC end of conversion channel 1 in sequence, sample ready 23 ADC_CH32 ADC ADC end of conversion channel 2 in sequence, sample ready 24 ADC_CH42 ADC ADC end of conversion channel 3 in sequence, sample ready 25 ADC_CH53 ADC ADC end of conversion channel 4 in sequence, sample ready 26 ADC_CH63 ADC ADC end of conversion channel 5 in sequence, sample ready 27 ADC_CH74 ADC ADC end of conversion channel 6 in sequence, sample ready 28 ADC_CH84 ADC ADC end of conversion channel 7 in sequence, sample ready 29 ENC_DW AES AES encryption processor requests download input data 30 ENC_UP AES AES encryption processor requests upload output data 9 Using this trigger source must be aligned with port interrupt enable bits, PICTL.P0IENL/H and P1IEN. Note that all interrupt enabled port pins will generate a trigger and the trigger is generated on each level change on the enabled input (0-1 gives a trigger as does 1-0). Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 95 of 211 Table 42: DMA Configuration Data Structure Byte Offset Bit Name Description 0 7:0 SRCADDR[15:8] The DMA channel source address, high 1 7:0 SRCADDR[7:0] The DMA channel source address, low 2 7:0 DESTADDR[15:8] The DMA channel destination address, high. Note that flash memory is not directly writeable. 3 7:0 DESTADDR[7:0] The DMA channel destination address, low. Note that flash memory is not directly writeable. 4 7:5 VLEN[2:0] Variable length transfer mode. In word mode, bits 12:0 of the first word is considered as the transfer length. 000 Use LEN for transfer count 001 Transfer the number of bytes/words specified by first byte/word + 1 (up to a maximum specified by LEN). Thus transfer count excludes length byte/word 010 Transfer the number of bytes/words specified by first byte/word (up to a maximum specified by LEN). Thus transfer count includes length byte/word. 011 Transfer the number of bytes/words specified by first byte/word + 2 (up to a maximum specified by LEN). 100 Transfer the number of bytes/words specified by first byte/word + 3 (up to a maximum specified by LEN). 101 reserved 110 reserved 111 Alternative for using LEN as transfer count 4 4:0 LEN[12:8] The DMA channel transfer count. Used as maximum allowable length when VLEN = 000/111. The DMA channel counts in words when in WORDSIZE mode, and in bytes otherwise. 5 7:0 LEN[7:0] The DMA channel transfer count. Used as maximum allowable length when VLEN = 000/111. The DMA channel counts in words when in WORDSIZE mode, and in bytes otherwise. 6 7 WORDSIZE Selects whether each DMA transfer shall be 8-bit (0) or 16-bit (1). 6 6:5 TMODE[1:0] The DMA channel transfer mode: 00 : Single 01 : Block 10 : Repeated single 11 : Repeated block 6 4:0 TRIG[4:0] Select DMA trigger to use 00000 : No trigger (writing to DMAREQ is only trigger) 00001 : The previous DMA channel finished 00010 – 11110 : Selects one of the triggers shown in Table 41, in that order. 7 7:6 SRCINC[1:0] Source address increment mode (after each transfer): 00 : 0 bytes/words 01 : 1 bytes/words 10 : 2 bytes/words 11 : -1 bytes/words 7 5:4 DESTINC[1:0] Destination address increment mode (after each transfer): 00 : 0 bytes/words 01 : 1 bytes/words 10 : 2 bytes/words 11 : -1 bytes/words 7 3 IRQMASK Interrupt Mask for this channel. 0 : Disable interrupt generation 1 : Enable interrupt generation upon DMA channel done Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 96 of 211 Byte Offset Bit Name Description 7 2 M8 Mode of 8th bit for VLEN transfer length; only applicable when WORDSIZE=0. 0 : Use all 8 bits for transfer count 1 : Use 7 LSB for transfer count 7 1:0 PRIORITY[1:0] The DMA channel priority: 00 : Low, CPU has priority. 01 : Guaranteed, DMA at least every second try. 10 : High, DMA has priority 11 : Highest, DMA has priority. Reserved for DMA port access. 13.5.8 DMA registers This section describes the SFR registers associated with the DMA Controller DMAARM (0xD6) – DMA Channel Arm Bit Name Reset R/W Description 7 ABORT 0 R0/W DMA abort. This bit is used to stop ongoing DMA transfers. Writing a 1 to this bit will abort all channels which are selected by setting the corresponding DMAARM bit to 1 0 : Normal operation 1 : Abort all selected channels 6:5 - 00 R/W Not used 4 DMAARM4 0 R/W1 DMA arm channel 4 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 3 DMAARM3 0 R/W1 DMA arm channel 3 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 2 DMAARM2 0 R/W1 DMA arm channel 2 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 1 DMAARM1 0 R/W1 DMA arm channel 1 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 0 DMAARM0 0 R/W1 DMA arm channel 0 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 97 of 211 DMAREQ (0xD7) – DMA Channel Start Request and Status Bit Name Reset R/W Description 7:5 - 000 R0 Not used 4 DMAREQ4 0 R/W1 H0 DMA transfer request, channel 4 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 3 DMAREQ3 0 R/W1 H0 DMA transfer request, channel 3 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 2 DMAREQ2 0 R/W1 H0 DMA transfer request, channel 2 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 1 DMAREQ1 0 R/W1 H0 DMA transfer request, channel 1 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 0 DMAREQ0 0 R/W1 H0 DMA transfer request, channel 0 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte Bit Name Reset R/W Description 7:0 DMA0CFG[15:8] 0x00 R/W The DMA channel 0 configuration address, high order DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte Bit Name Reset R/W Description 7:0 DMA0CFG[7:0] 0x00 R/W The DMA channel 0 configuration address, low order DMA1CFGH (0xD3) – DMA Channel 1-4 Configuration Address High Byte Bit Name Reset R/W Description 7:0 DMA1CFG[15:8] 0x00 R/W The DMA channel 1-4 configuration address, high order Not Recommended for New Designs CC2430 Peripherals : DMA Controller CC2430 Data Sheet (rev. 2.1) SWRS036F Page 98 of 211 DMA1CFGL (0xD2) – DMA Channel 1-4 Configuration Address Low Byte Bit Name Reset R/W Description 7:0 DMA1CFG[7:0] 0x00 R/W The DMA channel 1-4 configuration address, low order DMAIRQ (0xD1) – DMA Interrupt Flag Bit Name Reset R/W Description 7:5 - 000 R/W0 Not used 4 DMAIF4 0 R/W0 DMA channel 4 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending 3 DMAIF3 0 R/W0 DMA channel 3 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending 2 DMAIF2 0 R/W0 DMA channel 2 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending 1 DMAIF1 0 R/W0 DMA channel 1 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending 0 DMAIF0 0 R/W0 DMA channel 0 interrupt flag. 0 : DMA channel transfer not complete 1 : DMA channel transfer complete/interrupt pending Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 99 of 211 13.6 16-bit timer, Timer1 Timer 1 is an independent 16-bit timer which supports typical timer/counter functions such as input capture, output compare and PWM functions. The timer has three independent capture/compare channels. The timer uses one I/O pin per channel. The timer is used for a wide range of control and measurement applications and the availability of up/down count mode with three channels will for example allow implementation of motor control applications. The features of Timer 1 are as follows: • Three capture/compare channels • Rising, falling or any edge input capture • Set, clear or toggle output compare • Free-running, modulo or up/down counter operation • Clock prescaler for divide by 1, 8, 32 or 128 • Interrupt request generated on each capture/compare and terminal count • DMA trigger function 13.6.1 16-bit Timer Counter The timer consists of a 16-bit counter that increments or decrements at each active clock edge. The period of the active clock edges is defined by the register bits CLKCON.TICKSPD which sets the global division of the system clock giving a variable clock tick frequency from 0.25 MHz to 32 MHz (given the use of the 32 MHz XOSC as clock source). This is further divided in Timer 1 by the prescaler value set by T1CTL.DIV. This prescaler value can be from 1, 8, 32, or 128. Thus the lowest clock frequency used by Timer 1 is 1953.125 Hz and the highest is 32 MHz when the 32 MHz crystal oscillator is used as system clock source. When the 16 MHz RC oscillator is used as system clock source then the highest clock frequency used by Timer 1 is 16 MHz. The counter operates as either a free-running counter, a modulo counter or as an up/down counter for use in centre-aligned PWM. It is possible to read the 16-bit counter value through the two 8-bit SFRs; T1CNTH and T1CNTL, containing the high-order byte and low-order byte respectively. When the T1CNTL is read, the high-order byte of the counter at that instant is buffered in T1CNTH so that the high-order byte can be read from T1CNTH. Thus T1CNTL shall always be read first before reading T1CNTH. All write accesses to the T1CNTL register will reset the 16-bit counter. The counter produces an interrupt request when the terminal count value (overflow) is reached. It is possible to start and halt the counter with T1CTL control register settings. The counter is started when a value other than 00 is written to T1CTL.MODE. If 00 is written to T1CTL.MODE the counter halts at its present value. 13.6.2 Timer 1 Operation In general, the control register T1CTL is used to control the timer operation. The various modes of operation are described below. 13.6.3 Free-running Mode In the free-running mode of operation the counter starts from 0x0000 and increments at each active clock edge. When the counter reaches 0xFFFF (overflow) the counter is loaded with 0x0000 and continues incrementing its value as shown in Figure 20. When the terminal count value 0xFFFF is reached, both the IRCON.T1IF and the T1CTL.OVFIF flag are set. An interrupt request is generated if the corresponding interrupt mask bit TIMIF.OVFIM is set together with IEN1.T1EN. The free-running mode can be used to generate independent time intervals and output signal frequencies. Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 100 of 211 0000h FFFFh OVFL OVFL Figure 20: Free-running mode 13.6.4 Modulo Mode When the timer operates in modulo mode the 16-bit counter starts at 0x0000 and increments at each active clock edge. When the counter reaches the terminal count value T1CC0 (overflow), held in registers T1CC0H:T1CC0L, the counter is reset to 0x0000 and continues to increment. Both the IRCON.T1IF and the flag T1CTL.OVFIF flag are set when the terminal count value is reached. An interrupt request is generated if the corresponding interrupt mask bit TIMIF.OVFIM is set together with IEN1.T1EN. The modulo mode can be used for applications where a period other then 0xFFFF is required. The counter operation is shown in Figure 21. 0000h T1CC0 OVFL OVFL Figure 21: Modulo mode 13.6.5 Up/down Mode In the up/down timer mode, the counter repeatedly starts from 0x0000 and counts up until the value held in T1CC0H:T1CC0L is reached and then the counter counts down until 0x0000 is reached as shown in Figure 22. This timer mode is used when symmetrical output pulses are required with a period other than 0xFFFF, and therefore allows implementation of centre-aligned PWM output applications. Both the IRCON.T1IF and the T1CTL.OVFIF flag are set when the counter value reaches 0x0000 in the up/down mode. An interrupt request is generated if the corresponding interrupt mask bit TIMIF.OVFIM is set together with IEN1.T1EN. Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 101 of 211 0000h T1CC0 OVFL OVFL Figure 22 : Up/down mode 13.6.6 Channel Mode Control The channel mode is set with each channel’s control and status register T1CCTLn. The settings include input capture and output compare modes. 13.6.7 Input Capture Mode When a channel is configured as an input capture channel, the I/O pin associated with that channel, is configured as an input. After the timer has been started, a rising edge, falling edge or any edge on the input pin will trigger a capture of the 16-bit counter contents into the associated capture register. Thus the timer is able to capture the time when an external event takes place. Note: Before an I/O pin can be used by the timer, the required I/O pin must be configured as a Timer 1 peripheral pin as described in section 13.4.5 on page 79 . The channel input pin is synchronized to the internal system clock. Thus pulses on the input pin must have a minimum duration greater than the system clock period. The contents of the 16-bit capture register is read out from registers T1CCnH:T1CCnL. When the capture takes place the IRCON.T1IF flag is set together with the interrupt flag for the channel is set. These bits are T1CTL.CH0IF for channel 0, T1CTL.CH1IF for channel 1, and T1CTL.CH2IF for channel 2. An interrupt request is generated if the corresponding interrupt mask bit on T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM, respectively, is set together with IEN1.T1EN. 13.6.8 Output Compare Mode In output compare mode the I/O pin associated with a channel is set as an output. After the timer has been started, the contents of the counter are compared with the contents of the channel compare register T1CCnH:T1CCnL. If the compare register equals the counter contents, the output pin is set, reset or toggled according to the compare output mode setting of T1CCTLn.CMP. Note that all edges on output pins are glitch-free when operating in a given output compare mode. Writing to the compare register T1CCnL is buffered so that a value written to T1CCnL does not take effect until the corresponding high order register, T1CCnH is written. For output compare modes 1-3, a new value written to the compare register T1CCnH:T1CCnL takes effect after the registers have been written. For other output compare modes the new value written to the compare register takes effect when the timer reaches 0x0000. Note that channel 0 has fewer output compare modes because T1CC0H:T1CC0L has a special function in modes 6 and 7, meaning these modes would not be useful for channel 0. When a compare occurs, the interrupt flag for the channel is set. These bits are T1CTL.CH0IF for channel 0, T1CTL.CH1IF for channel 1, and T1CTL.CH2IF for channel 2, and the common interrupt flag IRCON.T1IF. An interrupt request is generated if the corresponding interrupt mask bit on T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM, respectively, is set together with IRCON.T1IF. When operating in up-down mode, the interrupt flag for channel 0 is set Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 102 of 211 when the counter reaches 0x0000 instead of when a compare occurs. Examples of output compare modes in various timer modes are given in the following figures. Edge-aligned: PWM output signals can be generated using the timer modulo mode and channels 1 and 2 in output compare mode 6 or 7 (defined by T1CCTLn.CMP bits, wher n is 1 or 2) as shown in Figure 23. The period of the PWM signal is determined by the setting in T1CC0 and the duty cycle is determined by T1CCn, where n is the PWM channel 1 or 2. The timer free-running mode may also be used. In this case CLKCON.TICKSPD and the prescaler divider value in T1CTL.DIV bits set the period of the PWM signal. The polarity of the PWM signal is determined by whether output compare mode 6 or 7 is used. PWM output signals can also be generated using output compare modes 4 and 5 as shown in Figure 23, or by using modulo mode as shown in Figure 24. Using output compare mode 4 and 5 is preferred for simple PWM. Centre-aligned: PWM outputs can be generated when the timer up/down mode is selected. The channel output compare mode 4 or 5 (defined by T1CCTLn.CMP bits, wher n is 1 or 2) is selected depending on required polarity of the PWM signal. The period of the PWM signal is determined by T1CC0 and the duty cycle for the channel output is determined by T1CCn, where n is the PWM channel 1 or 2. The centre-aligned PWM mode is required by certain types of motor drive applications and typically less noise is produced than the edgealigned PWM mode because the I/O pin transitions are not lined up on the same clock edge. In some types of applications, a defined delay or dead time is required between outputs. Typically this is required for outputs driving an H-bridge configuration to avoid uncontrolled cross-conduction in one side of the H-bridge. The delay or dead-time can be obtained in the PWM outputs by using T1CCn as shown in the following: Assuming that channel 1 and channel 2 are used to drive the outputs using timer up/down mode and the channels use output compare modes 4 and 5 respectively, then the timer period (in Timer 1 clock periods) is: TP = T1CC0 x 2 and the dead time, i.e. the time when both outputs are low, (in Timer 1 clock periods) is given by: TD = T1CC1 – T1CC2 Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 103 of 211 0000h FFFFh 0 - Set output on compare 1 - Clear output on compare 2 - Toggle output on compare 5 - Clear when T1CC0, set when T1CCn 6 - Set when T1CC0, clear when T1CCn T1CCn T1CC0 T1CCn T1CC0 3 - Set output on compare-up, clear on 0 4 - Clear output on compare-up, set on 0 T1CC0 T1CCn Figure 23: Output compare modes, timer free-running mode Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 104 of 211 0000h T1CC0 0 - Set output on compare 1 - Clear output on compare 2 - Toggle output on compare 5 - Clear when T1CC0, set when T1CCn 6 - Set when T1CC0, clear when T1CCn T1CCn T1CC0 T1CCn T1CC0 3 - Set output on compare-up, clear on 0 4 - Clear output on compare-up, set on 0 Figure 24: Output compare modes, timer modulo mode Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 105 of 211 0000h 0 - Set output on compare 1 - Clear output on compare 2 - Toggle output on compare 5 - Clear when T1CC0, set when T1CCn 6 - Set when T1CC0, clear when T1CCn T1CCn T1CC0 T1CCn T1CC0 T1CC0 T1CCn 3 - Set output on compare-up, clear on compare-down 4 - Clear output on compare-up, set on compare-down T1CCn T1CCn Figure 25: Output modes, timer up/down mode 13.6.9 Timer 1 Interrupts There is one interrupt vector assigned to the timer. An interrupt request is generated when one of the following timer events occur: • Counter reaches terminal count value (overflow, or turns around zero. • Input capture event. • Output compare event The register bits T1CTL.OVFIF, T1CTL.CH0IF, T1CTL.CH1IF, and T1CTL.CH2IF contains the interrupt flags for the terminal count value event, and the three channel compare/capture events, respectively. An interrupt request is only generated when the corresponding interrupt mask bit is set together witjh IEN1.T1EN. The interrupt mask bits are T1CCTL0.IM, T1CCTL1.IM, T1CCTL2.IM and TIMIF.OVFIM. If there are other pending interrupts, the corresponding interrupt flag must be cleared by software before a new interrupt request is generated. Also, enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. 13.6.10 Timer 1 DMA Triggers There are three DMA triggers associated with Timer 1. These are DMA triggers T1_CH0, T1_CH1 and T1_CH2 which are generated on timer compare events as follows: • T1_CH0 – channel 0 compare • T1_CH1 – channel 1 compare • T1_CH2 – channel 2 compare Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 106 of 211 13.6.11 Timer 1 Registers This section describes the Timer 1 registers which consist of the following registers: • T1CNTH – Timer 1 Count High • T1CNTL – Timer 1 Count Low • T1CTL – Timer 1 Control and Status • T1CCTLx – Timer 1 Channel x Capture/Compare Control • T1CCxH – Timer 1 Channel x Capture/Compare Value High • T1CCxL – Timer 1 Channel x Capture/Compare Value Low The TIMIF.OVFIM register bit resides in the TIMIF register, which is described together with Timer 3 and Timer 4 registers on page 118. T1CNTH (0xE3) – Timer 1 Counter High Bit Name Reset R/W Description 7:0 CNT[15:8] 0x00 R Timer count high order byte. Contains the high byte of the 16-bit timer counter buffered at the time T1CNTL is read. T1CNTL (0xE2) – Timer 1 Counter Low Bit Name Reset R/W Description 7:0 CNT[7:0] 0x00 R/W Timer count low order byte. Contains the low byte of the 16-bit timer counter. Writing anything to this register results in the counter being cleared to 0x0000. T1CTL (0xE4) – Timer 1 Control and Status Bit Name Reset R/W Description 7 CH2IF 0 R/W0 Timer 1 channel 2 interrupt flag. Set when the channel 2 interrupt condition occurs. Writing a 1 has no effect. 6 CH1IF 0 R/W0 Timer 1 channel 1 interrupt flag. Set when the channel 1 interrupt condition occurs. Writing a 1 has no effect. 5 CH0IF 0 R/W0 Timer 1 channel 0 interrupt flag. Set when the channel 0 interrupt condition occurs. Writing a 1 has no effect. 4 OVFIF 0 R/W0 Timer 1 counter overflow interrupt flag. Set when the counter reaches the terminal count value in free-running or modulo mode, and when zero is reached counting down in up-down mode. Writing a 1 has no effect. Prescaler divider value. Generates the active clock edge used to update the counter as follows: 00 Tick frequency/1 01 Tick frequency/8 10 Tick frequency/32 3:2 DIV[1:0] 00 R/W 11 Tick frequency/128 Timer 1 mode select. The timer operating mode is selected as follows: 00 Operation is suspended 01 Free-running, repeatedly count from 0x0000 to 0xFFFF 10 Modulo, repeatedly count from 0x0000 to T1CC0 1:0 MODE[1:0] 00 R/W 11 Up/down, repeatedly count from 0x0000 to T1CC0 and from T1CC0 down to 0x0000 Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 107 of 211 T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control Bit Name Reset R/W Description 7 - 0 R/W Reserved. Always set to 0 6 IM 1 R/W Channel 0 interrupt mask. Enables interrupt request when set. Channel 0 compare mode select. Selects action on output when timer value equals compare value in T1CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Not used 110 Not used 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 1 channel 0 capture or compare mode 0 Capture mode 2 MODE 0 R/W 1 Compare mode Channel 0 capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 1:0 CAP[1:0] 00 R/W 11 Capture on all edges T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value High Bit Name Reset R/W Description 7:0 T1CC0[15:8] 0x00 R/W Timer 1 channel 0 capture/compare value, high order byte T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value Low Bit Name Reset R/W Description 7:0 T1CC0[7:0] 0x00 R/W Timer 1 channel 0 capture/compare value, low order byte Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 108 of 211 T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control Bit Name Reset R/W Description 7 - 0 R/W Reserved. Always set to 0. 6 IM 1 R/W Channel 1 interrupt mask. Enables interrupt request when set. Channel 1 compare mode select. Selects action on output when timer value equals compare value in T1CC1 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Clear when equal T1CC0, set when equal T1CC1 110 Set when equal T1CC0, clear when equal T1CC1 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 1 channel 1 capture or compare mode 0 Capture mode 2 MODE 0 R/W 1 Compare mode Channel 1 capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 1:0 CAP[1:0] 00 R/W 11 Capture on all edges T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High Bit Name Reset R/W Description 7:0 T1CC1[15:8] 0x00 R/W Timer 1 channel 1 capture/compare value, high order byte T1CC1L (0xDC) – Timer 1 Channel 1 Capture/Compare Value Low Bit Name Reset R/W Description 7:0 T1CC1[7:0] 0x00 R/W Timer 1 channel 1 capture/compare value, low order byte Not Recommended for New Designs CC2430 Peripherals : 16-bit timer, Timer1 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 109 of 211 T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control Bit Name Reset R/W Description 7 - 0 R/W Reserved. Always set to 0. 6 IM 1 R/W Channel 2 interrupt mask. Enables interrupt request when set. Channel 2 compare mode select. Selects action on output when timer value equals compare value in T1CC2 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Clear when equal T1CC0, set when equal T1CC2 110 Set when equal T1CC0, clear when equal T1CC2 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 1 channel 2 capture or compare mode 0 Capture mode 2 MODE 0 R/W 1 Compare mode Channel 2 capture mode select 00 No capture 01 Capture on rising edge 10 Capture on falling edge 1:0 CAP[1:0] 00 R/W 11 Capture on all edges T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High Bit Name Reset R/W Description 7:0 T1CC2[15:8] 0x00 R/W Timer 1 channel 2 capture/compare value, high order byte T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low Bit Name Reset R/W Description 7:0 T1CC2[7:0] 0x00 R/W Timer 1 channel 2 capture/compare value, low order byte Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 110 of 211 13.7 MAC Timer (Timer2) The MAC Timer is mainly used to provide timing for 802.15.4 CSMA-CA algorithms and for general timekeeping in the 802.15.4 MAC layer. When the MAC Timer is used together with the Sleep Timer described in section 13.9, the timing function is provided even when the system enters low-power modes. The main features of the MAC Timer are the following: • 16-bit timer up-counter providing symbol/frame period: 16μs/320μs • Adjustable period with accuracy 31.25 ns • 8-bit timer compare function • 20-bit overflow count • 20-bit overflow count compare function • Start of Frame Delimiter capture function. • Timer start/stop synchronous with 32.768 kHz clock and timekeeping maintained by Sleep Timer. • Interrupts generated on compare and overflow • DMA trigger capability 13.7.1 Timer Operation This section describes the operation of the timer. 13.7.1.1 General After a reset the timer is in the timer IDLE mode where it is stopped. The timer starts running when T2CNF.RUN is set to 1. The timer will then enter the timer RUN mode. The entry is either immediate or it is performed synchronous with the 32 kHz clock. See section 13.7.4 for a description of the synchronous start and stop mode. Once the timer is running in RUN mode, it can be stopped by writing a 0 to T2CNF.RUN. The timer will then enter the timer IDLE mode. The stopping of the timer is performed either immediately or it is performed synchronous with the 32 kHz clock 13.7.1.2 Up Counter The MAC Timer contains a 16-bit timer, which increments during each clock cycle. 13.7.1.3 Timer overflow When the timer is about to count to a value that is equal to or greater than the timer period set by registers T2CAPHPH:T2CAPLPL, a timer overflow occurs. When the timer overflow occurs, the timer is set to the difference between the value it is about to count to and the timer period, e.g. if the next value of the timer would be 0x00FF and the timer period is 0x00FF then the timer is set to 0x000. If the overflow interrupt mask bit T2PEROF2.PERIM is 1, an interrupt request is generated. The interrupt flag bit T2CNF.PERIF is set to 1 regardless of the interrupt mask value. 13.7.1.4 Timer delta increment The timer period may be adjusted once during a timer period by writing a timer delta value. When a timer delta value is written to the registers T2THD:T2TLD, the 16-bit timer halts at its current value and a delta counter starts counting. The delta counter starts counting from the delta value written, down to zero. Once the delta counter reaches zero, the 16- bit timer starts counting again. The delta counter decrements by the same rate as the timer. When the delta counter has reached zero it will not start counting again until the delta value is written once again. In this way a timer period may be increased by the delta value in order to make adjustments to the timer overflow events over time. 13.7.1.5 Timer Compare A timer compare occurs when the timer is about to count to a value that is equal or greater than the 8-bit compare value held in the T2CMP register. Note that the compare value is only 8 bits so the compare is made between the compare value and either the most significant byte or the least significant byte of the timer. The selection of which part of Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 111 of 211 the timer is to be compared is set by the T2CNF.CMSEL bit. When a timer compare occurs the interrupt flag T2CNF.CMPIF is set to 1. An interrupt request is also generated if the interrupt mask T2PEROF2.CMPIM is set to 1. 13.7.1.6 Capture Input The MAC timer has a timer capture function which captures at the time when the start of frame delimiter (SFD) status in the radio goes high. Refer to sections 14.6 and 14.9 starting on page 157 for a description of the SFD. When the capture event occurs the current timer value will be captured into the capture register. The capture value can be read from the registers T2CAPHPH:T2CAPLPL. The value of the overflow count is also captured (see section 13.7.1.7) at the time of the capture event and can be read from the registers T2PEROF2:T2PEROF1:T2PEROF0. 13.7.1.7 Overflow count At each timer overflow, the 20-bit overflow counter is incremented by 1. The overflow counter value is read through the SFR registers T2OF2:T2OF1:T2OF0. Note that the register contents in T2OF2:T2OF1 is latched when T2OF0 is read, meaning that T2OF0 must always be read first. Overflow count update: The overflow count value may be updated by writing to the registers T2OF2:T2OF1:T2OF0 when the timer is in the IDLE or RUN state. Note that the last data written to registers T2OF1:T2OF0 is latched when T2OF2 is written, meaning that T2OF2 must always be written last. 13.7.1.8 Overflow count compare A compare value may be set for the overflow counter. The compare value is set by writing to T2PEROF2:T2PEROF1:T2PEROF0. When the overflow count value is equal or greater than the set compare value an overflow compare event occurs. If the overflow compare interrupt mask bit T2PEROF2.OFCMPIM is 1, an interrupt request is generated. The interrupt flag bit T2CNF.OFCMPIF is set to 1 regardless of the interrupt mask value. It should be noted that if a capture event occurs when the T2PEROF2 is written to the three most significant bits will not be updated. In order to address this one should either write twice to this register while interrupts are disabled, or read back and verify that written data was set. 13.7.2 Interrupts The Timer has three individually maskable interrupt sources. These are the following: • Timer overflow • Timer compare • Overflow count compare The interrupt flags are given in the T2CNF registers. The interrupt flag bits are set only by hardware and may be cleared only by writing to the SFR register. Each interrupt source may be masked by the mask bits in the T2PEROF2 register. An interrupt is generated when the corresponding mask bit is set, otherwise the interrupt will not be generated. The interrupt flag bit is set, however disregarding the state of the interrupt mask bit. 13.7.3 DMA Triggers Timer 2 can generate two DMA triggers – T2_COMP and T2_OVFL which are activated as follows: • T2_COMP: Timer 2 compare event • T2_OVFL: Timer 2 overflow event 13.7.4 Timer start/stop synchronization This section describes the synchronized timer start and stop. Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 112 of 211 13.7.4.1 General The Timer can be started and stopped synchronously with the 32kHz clock rising edge. Note this event is derived from a 32kHz clock signal, but is synchronous with the 32MHz system clock and thus has a period approximately equal the 32kHz clock period. At the time of a synchronous start the timer is reloaded with new calculated values for the timer and overflow count such that it appears that the timer has not been stopped (e.g. im PM1/2 mode). 13.7.4.2 Timer synchronous stop After the timer has started running, i.e. entered timer RUN mode it is stopped synchronously by writing 0 to T2CNF.RUN when T2CNF.SYNC is 1. After T2CNF.RUN has been set to 0, the timer will continue running until the 32kHz clock rising edge is sampled as 1. When this occurs the timer is stopped and the current Sleep timer value is stored. 13.7.4.3 Timer synchronous start When the timer is in the IDLE mode it is started synchronously by writing 1 to T2CNF.RUN when T2CNF.SYNC is 1. After T2CNF.RUN has been set to 1, the timer will remain in the IDLE mode until the 32kHz clock rising edge is detected. When this occurs the timer will first calculate new values for the 16- bit timer value and for the 20-bit timer overflow count, based on the current and stored Sleep timer values and the current 16-bit timer values. The new MAC Timer and overflow count values are loaded into the timer and the timer enters the RUN mode. This synchronous start process takes 75 clock cycles from the time when the 32kHz clock rising edge is sampled high. The synchronous start and stop function requires that the system clock frequency is selected to be 32MHz. If the 16MHz clock is selected, there will be an offset added to the new calculated value. The method for calculating the new MAC Timer value and overflow count value is given below. Due to the fact that the MAC Timer clock and Sleep timer clocks are asynchronous with a non-integer clock ratio there will be an error of maximum ±1 in calculated timer value compared to the ideal timer value. Calculation of new timer value and overflow count value: N CurrentSleepTimerValue c = N StoredSleepTimerValue s = K = ClockRatio = 976.5625 ck 10 stw = SleepTimerWidth = 24 P = Timer2Period O CurrentOverflowCountValue c = T CurrentTimerValue c = T = Overhead = 75 OH t c s N = N − N t t d t stw t d N ≤ 0⇒N = 2 + N ;N > 0⇒N = N d ck C OH C = N ⋅ K +T +T (Rounded to nearest integer value) T = C mod P ( ) C O P O C T + − = Timer2Value = T Timer2OverflowCount = O 10 Clock ratio of MAC Timer clock frequency (32 MHz - XOSC) and Sleep timer clock frequency (32.768 kHz - XOSC) For a given Timer 2 period value, P, there is a maximum duration between Timer2 synchronous stop and start for which the timer value is correctly updated after starting. The maximum value is given in terms of the number of Sleep Timer clock periods, i.e. 32kHz clock periods, TST(max): ck OH ST K P T T − × + ≤ (220 1) (max) The maximum period controlled by T2CAPHPH and T2CAPHPL is defined when thes registers are 0x0000. When operation in power modes PM1 or PM2 this will always result in an overflow and both overflow and timer counter will be sett to 0xFFFF. The value 0x0000 in Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 113 of 211 T2CAPHPH and T2CAPHPL should be avoided when using Timer2 in PM1 or PM2. 13.7.5 Timer 2 Registers The SFR registers associated with Timer 2 are listed in this section. These registers are the following: • T2CNF – Timer 2 Configuration • T2HD – Timer 2 Count/Delta High • T2LD – Timer 2 Count/Delta Low • T2CMP – Timer 2 Compare • T2OF2 – Timer 2 Overflow Count 2 • T2OF1 – Timer 2 Overflow Count 1 • T2OF0 – Timer 2 Overflow Count 0 • T2CAPHPH – Timer 2 Capture/Period High • T2CAPLPL – Timer 2 Capture/Period Low • T2PEROF2 – Timer 2 Overflow Capture/Compare 2 • T2PEROF1 – Timer 2 Overflow Capture/Compare 1 • T2PEROF0 – Timer 2 Overflow Capture/Compare 0 T2CNF (0xC3) – Timer 2 Configuration Bit Name Reset R/W Description 7 CMPIF 0 R/W0 Timer compare interrupt flag. This bit is set to 1 when a timer compare event occurs. Cleared by software only. Writing a 1 to this bit has no effect. 6 PERIF 0 R/W0 Overflow interrupt flag. This bit is set to 1 when a period event occurs. Cleared by software only. Writing a 1 to this bit has no effect. 5 OFCMPIF 0 R/W0 Overflow compare interrupt flag. This bit is set to 1 when a overflow compare occurs. Cleared by software only. Writing a 1 to this bit has no effect. 4 - 0 R0 Not used. Read as 0 3 CMSEL 0 R/W Timer compare source select. 0 Compare with 16-bit Timer bits [15:8] 1 Compare with 16-bit Timer bits [7:0] 2 - 0 R/W Reserved. Always set to 0 1 SYNC 1 R/W Enable synchronized start and stop. 0 start and stop of timer is immediate 1 start and stop of timer is synchronized with 32.768 kHz edge and new timer values are reloaded. 0 RUN 0 R/W Dual function: timer start / timer status. Writing this bit will start or stop the timer. 0 stop timer 1 start timer Reading this bit the current state of the timer is returned. 0 timer is stopped (IDLE state) 1 timer is running (RUN state) Note when SYNC =1 (the reset condition), the timer status does not change immediately when the timer is started or stopped. Instead the timer status is changed when the actual synchronous start/stop takes place. Prior to the synchronous start/stop event, the read value of RUN will differ from the last value written. Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 114 of 211 T2THD (0xA7) – Timer 2 Timer Value High Byte Bit Name Reset R/W Description 7:0 THD[7:0] 0x00 R/W The value read from this register is the high-order byte of the timer value. The high-order byte read is from timer value at the last instant when T2TLD was read. The value written to this register while the timer is running is the highorder byte of the timer delta counter value. The low-order byte of this value is the value last written to T2TLD. The timer will halt for delta clock cycles. The value written to this register while the timer is idle will be written to the high-order byte of the timer. T2TLD (0xA6) – Timer 2 Timer Value Low Byte Bit Name Reset R/W Description 7:0 TLD[7:0] 0x00 R/W The value read from this register is the low-order byte of the timer value. The value written to this register while the timer is running is the loworder byte of the timer delta counter value. The timer will halt for delta clock cycles. The value written to T2TLD will not take effect until T2THD is written. The value written to this register while the timer is idle will be written to the low-order byte of the timer. T2CMP (0x94) – Timer 2 Compare Value Bit Name Reset R/W Description 7:0 CMP[7:0] 0x00 R/W Timer Compare value. A timer compare occurs when the compare source selected by T2CNF.CMSEL equals the value held in CMP. T2OF2 (0xA3) – Timer 2 Overflow Count 2 Bit Name Reset R/W Description 7:4 - 0000 R0 Not used, read as 0 3:0 OF2[3:0] 0x00 R/W Overflow count. High bits T2OF[19:16]. T2OF is incremented by 1 each time the timer overflows i.e. timer counts to a value greater or equal to period. When reading this register, the value read is the value latched when T2OF0 was read. Writing to this register when the timer is in IDLE or RUN states will force the overflow count to be set to the value written to T2OF2:T2OF1:T2OF0. If the count would otherwise be incremented by 1 when this register is written then 1 is added to the value written. T2OF1 (0xA2) – Timer 2 Overflow Count 1 Bit Name Reset R/W Description 7:0 OF1[7:0] 0x00 R/W Overflow count. Middle bits T2OF[15:8]. T2OF is incremented by 1 each time the timer overflows i.e. timer counts to a value greater or equal to period. When reading this register, the value read is the value latched when T2OF0 was read. Writing to this register when the timer is in IDLE or RUN states will force the overflow count to be set to the value written to T2OF2:T2OF1:T2OF0. If the count would otherwise be incremented by 1 when this register is written then 1 is added to the value written. The value written will not take effect until T2OF2 is written. Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 115 of 211 T2OF0 (0xA1) – Timer 2 Overflow Count 0 Bit Name Reset R/W Description 7:0 OF0[7:0] 0x00 R/W Overflow count. Low bits T2OF[7:0]. T2OF is incremented by 1 each time the timer overflows i.e. timer counts to a value greater or equal to period. Writing to this register when the timer is in IDLE or RUN states will force the overflow count to be set to the value written to T2OF2:T2OF1:T2OF0. If the count would otherwise be incremented by 1 when this register is written then 1 is added to the value written. The value written will not take effect until T2OF2 is written. T2CAPHPH (0xA5) – Timer 2 Period High Byte Bit Name Reset R/W Description 7:0 CAPHPH[7:0] 0xFF R/W Capture value high/timer period high. Writing this register sets the high order bits [15:8] of the timer period. Reading this register gives the high order bits [15:8] of the timer value at the last capture event. T2CAPLPL (0xA4) – Timer 2 Period Low Byte Bit Name Reset R/W Description 7:0 CAPLPL[7:0] 0xFF R/W Capture value low/timer period low. Writing this register sets the low order bits [7:0] of the timer period. Reading this register gives the low order bits [7:0] of the timer value at the last capture event. T2PEROF2 (0x9E) – Timer 2 Overflow Capture/Compare 2 Bit Name Reset R/W Description 7 CMPIM 0 R/W Compare interrupt mask. 0: No interrupt is generated on compare event 1: Interrupt is generated on compare event. 6 PERIM 0 R/W Overflow interrupt mask 0: No interrupt is generated on timer overflow 1: Interrupt is generated on timer overflow 5 OFCMPIM 0 R/W Overflow count compare interrupt mask 0: No interrupt is generated on overflow count compare 1: Interrupt is generated on overflow count compare 4 - 0 R0 Not used, read as 0 3:0 PEROF2[3:0] 0000 R/W Overflow count capture/Overflow count compare value. Writing these bits set the high bits [19:16] of the overflow count compare value. Reading these bits returns the high bits [19:16] of the overflow count value at the time of the last capture event. T2PEROF1 (0x9D) – Timer 2 Overflow Capture/Compare 1 Bit Name Reset R/W Description 7:0 PEROF1[7:0] 0x00 R/W Overflow count capture /Overflow count compare value. Writing these bits set the middle bits [15:8] of the overflow count compare value. Reading these bits returns the middle bits [15:8] of the overflow count value at the time of the last capture event. Not Recommended for New Designs CC2430 Peripherals : MAC Timer (Timer2) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 116 of 211 T2PEROF0 (0x9C) – Timer 2 Overflow Capture/Compare 0 Bit Name Reset R/W Description 7:0 PEROF0[7:0] 0x00 R/W Overflow count capture /Overflow count compare value. Writing these bits set the low bits [7:0] of the overflow count compare value. Reading these bits returns the low bits [7:0] of the overflow count value at the time of the last capture event. Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 117 of 211 13.8 8-bit timers, Timer 3 and Timer 4 Timer 3 and 4 are two 8-bit timers which support typical timer/counter functions souch as output compare and PWM functions. The timers have two independent compare channels each using on IO per channel. Features of Timer 3/4 are as follows: • Two compare channels • Set, clear or toggle output compare • Clock prescaler for divide by 1, 2, 4, 8, 16, 32, 64, 128 • Interrupt request generated on each compare and terminal count event • DMA trigger function 13.8.1 8-bit Timer Counter All timer functions are based on the main 8-bit counter found in Timer 3/4. The counter increments or decrements at each active clock edge. The period of the active clock edges is defined by the register bits CLKCON.TICKSPD which is further divided by the prescaler value set by TxCTL.DIV (where x refers to the timer number, 3 or 4). The counter operates as either a free-running counter, a down counter, a modulo counter or as an up/down counter. It is possible to read the 8-bit counter value through the SFR TxCNT where x refers to the timer number, 3 or 4. The possibility to clear and halt the counter is given with TxCTL control register settings. The counter is started when a 1 is written to TxCTL.START. If a 0 is written to TxCTL.START the counter halts at its present value. 13.8.2 Timer 3/4 Mode Control In general the control register TxCTL is used to control the timer operation. 13.8.2.1 Free-running Mode In the free-running mode of operation the counter starts from 0x00 and increments at each active clock edge. When the counter reaches 0xFF the counter is loaded with 0x00 and continues incrementing its value. When the terminal count value 0xFF is reached (i.e. an overflow occurs), the interrupt flag TIMIF.TxOVFIF is set. If the corresponding interrupt mask bit TxCTL.OVFIM is set, an interrupt request is generated. The freerunning mode can be used to generate independent time intervals and output signal frequencies. 13.8.2.2 Down mode In the down mode, after the timer has been started, the counter is loaded with the contents in TxCC. The counter then counts down to 0x00. The flag TIMIF.TxOVFIF is set when 0x00 is reached. If the corresponding interrupt mask bit TxCTL.OVFIM is set, an interrupt request is generated. The timer down mode can generally be used in applications where an event timeout interval is required. 13.8.2.3 Modulo Mode When the timer operates in modulo mode the 8-bit counter starts at 0x00 and increments at each active clock edge. When the counter reaches the terminal count value held in register TxCC the counter is reset to 0x00 and continues to increment. The flag TIMIF.TxOVFIF is set when on this event. If the corresponding interrupt mask bit TxCTL.OVFIM is set, an interrupt request is generated. The modulo mode can be used for applications where a period other than 0xFF is required. 13.8.2.4 Up/down Mode In the up/down timer mode, the counter repeatedly starts from 0x00 and counts up until the value held in TxCC is reached and then the counter counts down until 0x00 is reached. This timer mode is used when symmetrical output pulses are required with a period other than 0xFF, and therefore allows implementation of centre-aligned PWM output applications. Clearing the counter by writing to TxCTL.CLR will also reset the count direction to the count up from 0x00 mode. Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 118 of 211 13.8.3 Channel Mode Control The channel modes for each channel; 0 and 1, are set by the control and status registers TxCCTLn where n is the channel number, 0 or 1. The settings include output compare modes. 13.8.4 Output Compare Mode In output compare mode the I/O pin associated with a channel shall be set to an output. After the timer has been started, the content of the counter is compared with the contents of the channel compare register TxCC0n. If the compare register equals the counter contents, the output pin is set, reset or toggled according to the compare output mode setting of TxCCTL.CMP1:0. Note that all edges on output pins are glitch-free when operating in a given compare output mode. For simple PWM use, output compare modes 4 and 5 are preferred. Writing to the compare register TxCC0 does not take effect on the output compare value until the counter value is 0x00. Writing to the compare register TxCC1 takes effect immediately. When a compare occurs the interrupt flag corresponding to the actual channel is set. This is TIMIF.TxCHnIF. An interrupt request is generated if the corresponding interrupt mask bit TxCCTLn.IM is set. 13.8.5 Timer 3 and 4 interrupts There is one interrupt vector assigned to each of the timers. These are T3 and T4. An interrupt request is generated when one of the following timer events occur: • Counter reaches terminal count value. • Output compare event The SFR register TIMIF contains all interrupt flags for Timer 3 and Timer 4. The register bits TIMIF.TxOVFIF and TIMIF.TxCHnIF, contains the interrupt flags for the two terminal count value events and the four channel compare events, respectively. An interrupt request is only generated when the corresponding interrupt mask bit is set. If there are other pending interrupts, the corresponding interrupt flag must be cleared by the CPU before a new interrupt request can be generated. Also, enabling an interrupt mask bit will generate a new interrupt request if the corresponding interrupt flag is set. 13.8.6 Timer 3 and Timer 4 DMA triggers There are two DMA triggers associated with Timer 3 and two DMA triggers associated with Timer 4. These are the following: • T3_CH0 : Timer 3 channel 0 compare • T3_CH1 : Timer 3 channel 1 compare • T4_CH0 : Timer 4 channel 0 compare • T4_CH0 : Timer 4 channel 1 compare Refer to section 13.5 on page 88 for a description on use of DMA channels. 13.8.7 Timer 3 and 4 registers T3CNT (0xCA) – Timer 3 Counter Bit Name Reset R/W Description 7:0 CNT[7:0] 0x00 R Timer count byte. Contains the current value of the 8-bit counter. Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 119 of 211 T3CTL (0xCB) – Timer 3 Control Bit Name Reset R/W Description Prescaler divider value. Generates the active clock edge used to clock the timer from CLKCON.TICKSPD as follows: 000 Tick frequency /1 001 Tick frequency /2 010 Tick frequency /4 011 Tick frequency /8 100 Tick frequency /16 101 Tick frequency /32 110 Tick frequency /64 7:5 DIV[2:0] 000 R/W 111 Tick frequency /128 4 START 0 R/W Start timer. Normal operation when set, suspended when cleared 3 OVFIM 1 R/W0 Overflow interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled 2 CLR 0 R0/W1 Clear counter. Writing high resets counter to 0x00 Timer 3 mode. Select the mode as follows: 00 Free running, repeatedly count from 0x00 to 0xFF 01 Down, count from T3CC0 to 0x00 10 Modulo, repeatedly count from 0x00 to T3CC0 1:0 MODE[1:0] 00 R/W 11 Up/down, repeatedly count from 0x00 to T3CC0 and down to 0x00 Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 120 of 211 T3CCTL0 (0xCC) – Timer 3 Channel 0 Compare Control Bit Name Reset R/W Description 7 - 0 R0 Unused 6 IM 1 R/W Channel 0 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T3CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Set output on compare, clear on 0xFF 110 Clear output on compare, set on 0x00 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 3 channel 0 compare mode 0 Compare disabled 2 MODE 0 R/W 1 Compare enable 1:0 - 00 R/W Reserved. Set to 00. T3CC0 (0xCD) – Timer 3 Channel 0 Compare Value Bit Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer compare value channel 0 Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 121 of 211 T3CCTL1 (0xCE) – Timer 3 Channel 1 Compare Control Bit Name Reset R/W Description 7 - 0 R0 Unused 6 IM 1 R/W Channel 1 interrupt mask 0 : interrupt is disabled 1 : interrupt is enabled Channel 1 compare output mode select. Specified action on output when timer value equals compare value in T3CC1 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Set output on compare, clear on T3CC0 110 Clear output on compare, set on T3CC0 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 3 channel 1 compare mode 0 Compare disabled 2 MODE 0 R/W 1 Compare enabled 1:0 - 00 R/W Reserved. Set to 00. T3CC1 (0xCF) – Timer 3 Channel 1 Compare Value Bit Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer compare value channel 1 T4CNT (0xEA) – Timer 4 Counter Bit Name Reset R/W Description 7:0 CNT[7:0] 0x00 R Timer count byte. Contains the current value of the 8-bit counter. Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 122 of 211 T4CTL (0xEB) – Timer 4 Control Bit Name Reset R/W Description Prescaler divider value. Generates the active clock edge used to clock the timer from CLKCON.TICKSPD as follows: 000 Tick frequency /1 001 Tick frequency /2 010 Tick frequency /4 011 Tick frequency /8 100 Tick frequency /16 101 Tick frequency /32 110 Tick frequency /64 7:5 DIV[2:0] 000 R/W 111 Tick frequency /128 4 START 0 R/W Start timer. Normal operation when set, suspended when cleared 3 OVFIM 1 R/W0 Overflow interrupt mask 2 CLR 0 R0/W1 Clear counter. Writing high resets counter to 0x00 Timer 4 mode. Select the mode as follows: 00 Free running, repeatedly count from 0x00 to 0xFF 01 Down, count from T4CC0 to 0x00 10 Modulo, repeatedly count from 0x00 to T4CC0 1:0 MODE[1:0] 00 R/W 11 Up/down, repeatedly count from 0x00 to T4CC0 and down to 0x00 Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 123 of 211 T4CCTL0 (0xEC) – Timer 4 Channel 0 Compare Control Bit Name Reset R/W Description 7 - 0 R0 Unused 6 IM 1 R/W Channel 0 interrupt mask Channel 0 compare output mode select. Specified action on output when timer value equals compare value in T4CC0 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Set output on compare, clear on 0x00 110 Clear output on compare, set on 0x00 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 4 channel 0 compare mode 0 Compare disabled 2 MODE 0 R/W 1 Compare enabled 1:0 - 00 R/W Reserved. Set to oo T4CC0 (0xED) – Timer 4 Channel 0 Compare Value Bit Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer compare value channel 0 Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 124 of 211 T4CCTL1 (0xEE) – Timer 4 Channel 1 Compare Control Bit Name Reset R/W Description 7 - 0 R0 Unused 6 IM 1 R/W Channel 1 interrupt mask Channel 1 compare output mode select. Specified action on output when timer value equals compare value in T4CC1 000 Set output on compare 001 Clear output on compare 010 Toggle output on compare 011 Set output on compare-up, clear on 0 (clear on comparedown in up/down mode) 100 Clear output on compare-up, set on 0 (set on comparedown in up/down mode) 101 Set output on compare, clear on T4CC0 110 Clear output on compare, set on T4CC0 5:3 CMP[2:0] 000 R/W 111 Not used Mode. Select Timer 4 channel 1 compare mode 0 Compare disabled 2 MODE 0 R/W 1 Compare enabled 1:0 - 00 R/W Reserved. Set to 00. T4CC1 (0xEF) – Timer 4 Channel 1 Compare Value Bit Name Reset R/W Description 7:0 VAL[7:0] 0x00 R/W Timer compare value channel 1 Not Recommended for New Designs CC2430 Peripherals : 8-bit timers, Timer 3 and Timer 4 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 125 of 211 TIMIF (0xD8) – Timers 1/3/4 Interrupt Mask/Flag Bit Name Reset R/W Description 7 - 0 R0 Unused 6 OVFIM 1 R/W Timer 1 overflow interrupt mask 5 T4CH1IF 0 R/W0 Timer 4 channel 1 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending 4 T4CH0IF 0 R/W0 Timer 4 channel 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending 3 T4OVFIF 0 R/W0 Timer 4 overflow interrupt flag 0 : no interrupt is pending 1 : interrupt is pending 2 T3CH1IF 0 R/W0 Timer 3 channel 1 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending 1 T3CH0IF 0 R/W0 Timer 3 channel 0 interrupt flag 0 : no interrupt is pending 1 : interrupt is pending 0 T3OVFIF 0 R/W0 Timer 3 overflow interrupt flag 0 : no interrupt is pending 1 : interrupt is pending Not Recommended for New Designs CC2430 Peripherals : Sleep Timer CC2430 Data Sheet (rev. 2.1) SWRS036F Page 126 of 211 13.9 Sleep Timer The Sleep timer is used to set the period between when the system enters and exits low-power sleep modes. The Sleep timer is also used to maintain timing in Timer 2 (MAC Timer) when entering a lowpower sleep mode. The main features of the Sleep timer are the following: • 24-bit timer up-counter operating at 32kHz clock • 24-bit compare • Low-power mode operation in PM2 • Interrupt and DMA trigger 13.9.1 Timer Operation This section describes the operation of the timer. 13.9.1.1 General The Sleep timer is a 24-bit timer running on the 32kHz clock (either RC or XOSC). The timer starts running immediately after a reset and continues to run uninterrupted. The current value of the timer can be read from the SFR registers ST2:ST1:ST0. 13.9.1.2 Timer Compare A timer compare occurs when the timer value is equal to the 24-bit compare value. The compare value is set by writing to the registers ST2:ST1:ST0. When a timer compare occurs the interrupt flag STIF is asserted. The interrupt enable bit for the ST interrupt is IEN0.STIE and the interrupt flag is IRCON.STIF. When operating in all power modes except PM3 the Sleep timer will be running. In PM1 and PM2 the Sleep timer compare event is used to wake up the device and return to active operation in PM0. The default value of the compare value after reset is 0xFFFFFF. Note that before entering PM2 one should wait for ST0 to change after setting new compare value. The Sleep timer compare can also be used as a DMA trigger (DMA trigger 11 in Table 41). Note that if supply voltage drops below 2V while being in PM2, the sleep interval might be affected. 13.9.1.3 Sleep Timer Registers The registers used by the Sleep Timer are: • ST2 – Sleep Timer 2 • ST1 – Sleep Timer 1 • ST0 – Sleep Timer 0 ST2 (0x97) – Sleep Timer 2 Bit Name Reset R/W Description 7:0 ST2[7:0] 0x00 R/W Sleep timer count/compare value. When read, this register returns the high bits [23:16] of the sleep timer count. When writing this register sets the high bits [23:16] of the compare value. The value read is latched at the time of reading register ST0. The value written is latched when ST0 is written. ST1 (0x96) – Sleep Timer 1 Bit Name Reset R/W Description 7:0 ST1[7:0] 0x00 R/W Sleep timer count/compare value. When read, this register returns the middle bits [15:8] of the sleep timer count. When writing this register sets the middle bits [15:8] of the compare value. The value read is latched at the time of reading register ST0. The value written is latched when ST0 is written. Not Recommended for New Designs CC2430 Peripherals : Sleep Timer CC2430 Data Sheet (rev. 2.1) SWRS036F Page 127 of 211 ST0 (0x95) – Sleep Timer 0 Bit Name Reset R/W Description 7:0 ST0[7:0] 0x00 R/W Sleep timer count/compare value. When read, this register returns the low bits [7:0] of the sleep timer count. When writing this register sets the low bits [7:0] of the compare value. Not Recommended for New Designs CC2430 Peripherals : ADC CC2430 Data Sheet (rev. 2.1) SWRS036F Page 128 of 211 13.10 ADC 13.10.1 ADC Introduction The ADC supports up to 12-bit analog-todigital conversion. The ADC includes an analog multiplexer with up to eight individually configurable channels, reference voltage generator and conversion results written to memory through DMA. Several modes of operation are available. The main features of the ADC are as follows: • Selectable decimation rates which also sets the resolution (7 to 12 bits). • Eight individual input channels, singleended or differential • Reference voltage selectable as internal, external single ended, external differential or AVDD_SOC. • Interrupt request generation • DMA triggers at end of conversions • Temperature sensor input • Battery measurement capability input mux Sigma-delta modulator Decimation filter Clock generation and control AIN0 AIN7 . . . ref mux VDD/3 TMP_SENSOR Int 1.25V AIN7 AVDD AIN6-AIN7 Figure 26: ADC block diagram. 13.10.2 ADC Operation This section describes the general setup and operation of the ADC and describes the usage of the ADC control and status registers accessed by the CPU. 13.10.2.1 ADC Core The ADC includes an ADC capable of converting an analog input into a digital representation with up to 12 bits resolution. The ADC uses a selectable positive reference voltage. 13.10.2.2 ADC Inputs The signals on the P0 port pins can be used as ADC inputs. In the following these port pin will be referred to as the AIN0-AIN7 pins. The input pins AIN0-AIN7 are connected to the ADC. The ADC can be set up to automatically perform a sequence of conversions and optionally perform an extra conversion from any channel when the sequence is completed. It is possible to configure the inputs as singleended or differential inputs. In the case where differential inputs are selected, the differential inputs consist of the input pairs AIN0-1, AIN2- 3, AIN4-5 and AIN6-7. Note that no negative supply can be applied to these pins, nor a supply larger than VDD (unregulated power). It is the difference between the pairs that are converted in differential mode. In addition to the input pins AIN0-AIN7, the output of an on-chip temperature sensor can be selected as an input to the ADC for temperature measurements. Not Recommended for New Designs CC2430 Peripherals : ADC CC2430 Data Sheet (rev. 2.1) SWRS036F Page 129 of 211 It is also possible to select a voltage corresponding to AVDD_SOC/3 as an ADC input. This input allows the implementation of e.g. a battery monitor in applications where this feature is required. Alle these input configurations are controlled by the register ADCCON2.SCH 13.10.2.3 ADC conversion sequences The ADC can perform a sequence of conversions, and move the results to memory (through DMA) without any interaction from the CPU. The conversion sequence can be influenced with the ADCCFG register (see section 13.4.6.6 on page 81) in that the eight analog inputs to the ADC comes from IO pins that are not necessarily programmed to be analog inputs. If a channel should normally be part of a sequence, but the corresponding analog input is disabled in the ADCCFG, then that channel will be skipped. For channels 8 to 12, both input pins must be enabled. The ADCCON2.SCH register bits are used to define an ADC conversion sequence, from the ADC inputs. A conversion sequence will contain a conversion from each channel from 0 up to and including the channel number programmed in ADCCON2.SCH when ADCCON2.SCH is set to a value less than 8. The single-ended inputs AIN0 to AIN7 are represented by channel numbers 0 to 7 in ADCCON2.SCH. Channel numbers 8 to 11 represent the differential inputs consisting of AIN0-AIN1, AIN2-AIN3, AIN4-AIN5 and AIN6- AIN7. Channel numbers 12 to 15 represent GND, internal voltage reference, temperature sensor and AVDD_SOC/3, respectively. When ADCCON2.SCH is set to a value between 8 and 12, the sequence will start at channel 8. For even higher settings, only single conversions are performed. In addition to this sequence of conversions, the ADC can be programmed to perform a single conversion from any channel as soon as the sequence has completed. This is called an extra conversion and is controlled with the ADCCON3 register. 13.10.2.4 ADC Operating Modes This section describes the operating modes and initialization of conversions. The ADC has three control registers: ADCCON1, ADCCON2 and ADCCON3. These registers are used to configure the ADC and to report status. The ADCCON1.EOC bit is a status bit that is set high when a conversion ends and cleared when ADCH is read. The ADCCON1.ST bit is used to start a sequence of conversions. A sequence will start when this bit is set high, ADCCON1.STSEL is 11 and no conversion is currently running. When the sequence is completed, this bit is automatically cleared. The ADCCON1.STSEL bits select which event that will start a new sequence of conversions. The options which can be selected are rising edge on external pin P2_0, end of previous sequence, a Timer 1 channel 0 compare event or ADCCON1.ST is 1. The ADCCON2 register controls how the sequence of conversions is performed. ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed when no conversion is running. The ADCCON2.SDIV bits select the decimation rate (and thereby also the resolution and time required to complete a conversion and sample rate). The decimation rate should only be changed when no conversion is running. The last channel of a sequence is selected with the ADCCON2.SCH bits. The ADCCON3 register controls the channel number, reference voltage and decimation rate for the extra conversion. The extra conversion will take place immediately after the ADCCON3 register is updated. The coding of the register bits is exactly as for ADCCON2. 13.10.2.5 ADC Conversion Results The digital conversion result is represented in two's complement form. For single ended configurations the result is always positive. This is because the result is the difference between ground and input signal which is always possivitely signed (Vconv=Vinp-Vinn, Not Recommended for New Designs CC2430 Peripherals : ADC CC2430 Data Sheet (rev. 2.1) SWRS036F Page 130 of 211 where Vinn=0V). The maximum value is reached when the input amplitude is equal VREF, the selected voltage reference. For differential configurations the difference between two pin pairs are converted and this differense can be negatively signed. For 12-bit resolution the digital conversion result is 2047 when the analog input, Vconv, is equal to VREF, and the conversion result is -2048 when the analog input is equal to –VREF. The digital conversion result is available in ADCH and ADCL when ADCCON1.EOC is set to 1. Note that the conversion result always resides in MSB section of combined ADCH and ADCL registers. When the ADCCON2.SCH bits are read, they will indicate the channel above the channel which the conversion result in ADCL and ADCH apply to. E.g. reading the value 0x1 from ADCCON2.SCH, means that the available conversion result is from input AIN0. 13.10.2.6 ADC Reference Voltage The positive reference voltage for analog-todigital conversions is selectable as either an internally generated 1.25V voltage, the AVDD_SOC pin, an external voltage applied to the AIN7 input pin or a differential voltage applied to the AIN6-AIN7 inputs. It is possible to select the reference voltage as the input to the ADC in order to perform a conversion of the reference voltage e.g. for calibration purposes. Similarly, it is possible to select the ground terminal GND as an input. 13.10.2.7 ADC Conversion Timing The ADC should be run when on the 32MHz system clock, which is divided by 8 to give a 4 MHz clock. Both the delta sigma modulator and decimation filter expect 4 MHz clock for their calculations. Using other frequencies will affect the results, and conversion time. All data presented within this data sheet are from 32MHz system clock usage. The time required to perform a conversion depends on the selected decimation rate. When the decimation rate is set to for instance 128, the decimation filter uses exactly 128 of the 4 MHz clock periods to calculate the result. When a conversion is started, the input multiplexer is allowed 16 4 MHz clock cycles to settle in case the channel has been changed since the previous conversion. The 16 clock cycles settling time applies to all decimation rates. Thus in general, the conversion time is given by: Tconv = (decimation rate + 16) x 0.25 μs. 13.10.2.8 ADC Interrupts The ADC will generate an interrupt when an extra conversion has completed. An interrupt is not generated when a conversion from the sequence is completed. 13.10.2.9 ADC DMA Triggers The ADC will generate a DMA trigger every time a conversion from the sequence has completed. When an extra conversion completes, no DMA trigger is generated. There is one DMA trigger for each of the eight channels defined by the first eight possible settings for ADCCON2.SCH . The DMA trigger is active when a new sample is ready from the conversion for the channel. The DMA triggers are named ADC_CHsd in Table 41 on page 94, where s is single ended channel and d is differential channel. In addition there is one DMA trigger, ADC_CHALL, which is active when new data is ready from any of the channels in the ADC conversion sequence. 13.10.2.10 ADC Registers This section describes the ADC registers. ADCL (0xBA) – ADC Data Low Bit Name Reset R/W Description 7:2 ADC[5:0] 0x00 R Least significant part of ADC conversion result. 1:0 - 00 R0 Not used. Always read as 0 Not Recommended for New Designs CC2430 Peripherals : ADC CC2430 Data Sheet (rev. 2.1) SWRS036F Page 131 of 211 ADCH (0xBB) – ADC Data High Bit Name Reset R/W Description 7:0 ADC[13:6] 0x00 R Most significant part of ADC conversion result. ADCCON1 (0xB4) – ADC Control 1 Bit Name Reset R/W Description 7 EOC 0 R H0 End of conversion Cleared when ADCH has been read. If a new conversion is completed before the previous data has been read, the EOC bit will remain high. 0 conversion not complete 1 conversion completed 6 ST 0 R/W1 Start conversion. Read as 1 until conversion has completed 0 no conversion in progress 1 start a conversion sequence if ADCCON1.STSEL = 11 and no sequence is running. 5:4 STSEL[1:0] 11 R/W Start select. Selects which event that will start a new conversion sequence. 00 External trigger on P2_0 pin. 01 Full speed. Do not wait for triggers. 10 Timer 1 channel 0 compare event 11 ADCCON1.ST = 1 3:2 RCTRL[1:0] 00 R/W Controls the 16 bit random number generator. When written 01, the setting will automatically return to 00 when operation has completed. 00 Normal operation. (13x unrolling) 01 Clock the LFSR once (no unrolling). 10 Reserved 11 Stopped. Random number generator is turned off. 1:0 - 11 R/W Reserved. Always set to 11. Not Recommended for New Designs CC2430 Peripherals : ADC CC2430 Data Sheet (rev. 2.1) SWRS036F Page 132 of 211 ADCCON2 (0xB5) – ADC Control 2 Bit Name Reset R/W Description Selects reference voltage used for the sequence of conversions 00 Internal 1.25V reference 01 External reference on AIN7 pin 10 AVDD_SOC pin 7:6 SREF[1:0] 00 R/W 11 External reference on AIN6-AIN7 differential input Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00 64 decimation rate (7 bits resolution) 01 128 decimation rate (9 bits resolution) 10 256 decimation rate (10 bits resolution) 5:4 SDIV[1:0] 01 R/W 11 512 decimation rate (12 bits resolution) Sequence Channel Select. Selects the end of the sequence. A sequence can either be from AIN0 to AIN7 (SCH<=7) or from the differential input AIN0-AIN1 to AIN6-AIN7 (8<=SCH<=11). For other settings, only single conversions are performed. When read, these bits will indicate the channel number plus one of current conversion result. 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 AIN0-AIN1 1001 AIN2-AIN3 1010 AIN4-AIN5 1011 AIN6-AIN7 1100 GND 1101 Positive voltage reference 1110 Temperature sensor 3:0 SCH[3:0] 0000 R/W 1111 VDD/3 Not Recommended for New Designs CC2430 Peripherals : ADC CC2430 Data Sheet (rev. 2.1) SWRS036F Page 133 of 211 ADCCON3 (0xB6) – ADC Control 3 Bit Name Reset R/W Description Selects reference voltage used for the extra conversion 00 Internal 1.25V reference 01 External reference on AIN7 pin 10 AVDD_SOC pin 7:6 EREF[1:0] 00 R/W 11 External reference on AIN6-AIN7 differential input Sets the decimation rate used for the extra conversion. The decimation rate also determines the resolution and time required to complete the conversion. 00 64 dec rate (7 bits resolution) 01 128 dec rate (9 bits resolution) 10 256 dec rate (10 bits resolution) 5:4 EDIV[1:0] 00 R/W 11 512 dec rate (12 bits resolution) Extra channel select. Selects the channel number of the extra conversion that is carried out after a conversion sequence has ended. This bit field must be written for an extra conversion to be performed. If the ADC is not running, writing to these bits will trigger an immediate single conversion from the selected extra channel. The bits are automatically cleared when the extra conversion has finished. 0000 AIN0 0001 AIN1 0010 AIN2 0011 AIN3 0100 AIN4 0101 AIN5 0110 AIN6 0111 AIN7 1000 AIN0-AIN1 1001 AIN2-AIN3 1010 AIN4-AIN5 1011 AIN6-AIN7 1100 GND 1101 Positive voltage reference 1110 Temperature sensor 3:0 ECH[3:0] 0000 R/W 1111 VDD/3 Not Recommended for New Designs CC2430 Peripherals : Random Number Generator CC2430 Data Sheet (rev. 2.1) SWRS036F Page 134 of 211 13.11 Random Number Generator 13.11.1 Introduction The random number generator has the following features. • Generate pseudo-random bytes which can be read by the CPU or used directly by the Command Strobe Processor (see section 14.34). • Calculate CRC16 of bytes that are written to RNDH. • Seeded by value written to RNDL. The random number generator is a 16-bit Linear Feedback Shift Register (LFSR) with polynomial X 16 + X 15 + X 2 +1 (i.e. CRC16). It uses different levels of unrolling depending on the operation it performs. The basic version (no unrolling) is shown in Figure 27. The random number generator is turned off when ADCCON1.RCTRL= 11. 15 + 14 13 12 11 10 9 8 7 6 5 4 3 2 + 1 0 in_bit + Figure 27: Basic structure of the Random Number Generator 13.11.2 Random Number Generator Operation The operation of the random number generator is controlled by the ADCCON1.RCTRL bits. The current value of the 16-bit shift register in the LFSR can be read from the RNDH and RNDL registers. 13.11.2.1 Semi random sequence generation The default operation (ADCCON1.RCTRL is 00) is to clock the LFSR once (13x unrolling) each time the Command Strobe Processor reads the random value. This leads to the availability of a fresh pseudo-random byte from the LSB end of the LFSR. Another way to update the LFSR is to set ADCCON1.RCTRL is 01. This will clock the LFSR once (no unrolling) and the ADCCON1.RCTRL bits will automatically be cleared when the operation has completed. 13.11.2.2 Seeding The LFSR can be seeded by writing to the RNDL register twice. Each time the RNDL register is written, the 8 LSB of the LFSR is copied to the 8 MSB and the 8 LSBs are replaced with the new data byte that was written to RNDL. When a true random value is required, the LFSR should be seeded by writing RNDL with random values from the IF_ADC in the RF receive path. To use this seeding method, the radio must first be powered on by enabling the voltage regulator as described in section 15.1. The radio should be placed in infinite TX state, to avoid possible sync detect in RX state. The random values from the IF_ADC are read from the RF registers ADCTSTH and ADCTSTL (see page 196). The values read are used as the seed values to be written to the RNDL register as described above. Note that this can not be done while radio is in use for normal tasks. 13.11.2.3 CRC16 The LFSR can also be used to calculate the CRC value of a sequence of bytes. Writing to the RNDH register will trigger a CRC calculation. The new byte is processed from the MSB end and an 8x unrolling is used, so that a new byte can be written to RNDH every clock cycle. Note that the LFSR must be properly seeded by writing to RNDL, before the CRC calculations start. Usually the seed value should be 0x0000 or 0xFFFF. Not Recommended for New Designs CC2430 Peripherals : Random Number Generator CC2430 Data Sheet (rev. 2.1) SWRS036F Page 135 of 211 13.11.3 Random Number Generator Registers This section describes the Random Number Generator registers. RNDL (0xBC) – Random Number Generator Data Low Byte Bit Name Reset R/W Description [7:0] RNDL[7:0] 0xFF R/W Random value/seed or CRC result, low byte When used for random number generation writing this register twice will seed the random number generator. Writing to this register copies the 8 LSBs of the LFSR to the 8 MSBs and replaces the 8 LSBs with the data value written. The value returned when reading from this register is the 8 LSBs of the LSFR. When used for random number generation, reading this register returns the 8 LSBs of the random number. When used for CRC calculations, reading this register returns the 8 LSBs of the CRC result. RNDH (0xBD) – Random Number Generator Data High Byte Bit Name Reset R/W Description [7:0] RNDH[7:0] 0xFF R/W Random value or CRC result/input data, high byte When written, a CRC16 calculation will be triggered, and the data value written is processed starting with the MSB bit. The value returned when reading from this register is the 8 MSBs of the LSFR. When used for random number generation, reading this register returns the 8 MSBs of the random number. When used for CRC calculations, reading this register returns the 8 MSBs of the CRC result. Not Recommended for New Designs CC2430 Peripherals : AES Coprocessor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 136 of 211 13.12 AES Coprocessor The CC2430 data encryption is performed using a dedicated coprocessor which supports the Advanced Encryption Standard, AES. The coprocessor allows encryption/decryption to be performed with minimal CPU usage. The coprocessor has the following features: • Supports all security suites in IEEE 802.15.4 • ECB, CBC, CFB, OFB, CTR and CBCMAC modes. • Hardware support for CCM mode • 128-bits key and IV/Nonce • DMA transfer trigger capability 13.12.1 AES Operation To encrypt a message, the following procedure must be followed (ECB, CBC): • Load key • Load initialization vector (IV) • Download and upload data for encryption/decryption. The AES coprocessor works on blocks of 128 bits. A block of data is loaded into the coprocessor, encryption is performed and the result must be read out before the next block can be processed. Before each block load, a dedicated start command must be sent to the coprocessor. 13.12.2 Key and IV Before a key or IV/nonce load starts, an appropriate load key or IV/nonce command must be issued to the coprocessor. When loading the IV it is important to also set the correct mode. A key load or IV load operation aborts any processing that could be running. The key, once loaded, stays valid until a key reload takes place. The IV must be downloaded before the beginning of each message (not block). Both key and IV values are cleared by a reset of the device. 13.12.3 Padding of input data The AES coprocessor works on blocks of 128 bits. If the last block contains less than 128 bits, it must be padded with zeros when written to the coprocessor. 13.12.4 Interface to CPU The CPU communicates with the coprocessor using three SFR registers: • ENCCS, Encryption control and status register • ENCDI, Encryption input register • ENCDO, Encryption output register Read/write to the status register is done directly by the CPU, while access to the input/output registers should be performed using direct memory access (DMA). When using DMA with AES coprosessor, two DMA channels must be used, one for input data and one for output data. The DMA channels must be initialized before a start command is written to the ENCCS. Writing a start command generates a DMA trigger and the transfer is started. After each block is processed, an interrupt is generated. The interrupt is used to issue a new start command to the ENCCS. 13.12.5 Modes of operation When using CFB, OFB and CTR mode, the 128 bits blocks are divided into four 32 bit blocks. 32 bits are loaded into the AES coprocessor and the resulting 32 bits are read out. This continues until all 128 bits have been encrypted. The only time one has to consider this is if data is loaded/read directly using the CPU. When using DMA, this is handled automatically by the DMA triggers generated by the AES coprocessor, thus DMA is preferred. Both encryption and decryption are performed similarly. The CBC-MAC mode is a variant of the CBC mode. When performing CBC-MAC, data is downloaded to the coprocessor one 128 bits block at a time, except for the last block. Before the last block is loaded, the mode must Not Recommended for New Designs CC2430 Peripherals : AES Coprocessor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 137 of 211 be changed to CBC. The last block is then downloaded and the block uploaded will be the MAC value. CCM is a combination of CBC-MAC and CTR. Parts of the CCM must therefore be done in software. The following section gives a short explanation of the necessary steps to be done. 13.12.5.1 CBC-MAC When performing CBC-MAC encryption, data is downloaded to the coprocessor in CBCMAC mode one block at a time, except for the last block. Before the last block is loaded, the mode is changed to CBC. The last block is downloaded and the block uploaded is the message MAC. CBC-MAC decryption is similar to encryption. The message MAC uploaded must be compared with the MAC to be verified. 13.12.5.2 CCM mode To encrypt a message under CCM mode, the following sequence can be conducted (key is already loaded): Message Authentication Phase This phase takes place during steps 1-6 shown in the following. (1) The software loads the IV with zeros. (2) The software creates the block B0. The layout of block B0 is shown in Figure 28. Name B0 Designation First block for authentication in CCM mode Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Flag NONCE L_M Figure 28: Message Authentication Phase Block 0 There is no restriction on the NONCE value. L_M is the message length in bytes. For 802.15.4 the NONCE is 13 bytes and L_M is 2 bytes. The content of the Authentication Flag byte is described in Figure 29. L is set to 6 in this example. So, L-1 is set to 5. M and A_Data can be set to any value. Name FLAG/B0 Designation Authentication Flag Field for CCM mode Bit 7 6 5 4 3 2 1 0 Name Reserved A_Data (M-2)/2 L-1 Value 0 x x x x 1 0 1 Figure 29: Authentication Flag Byte (3) If some Additional Authentication Data (denoted a below) is needed (that is A_Data =1), the software creates the A_Data length field, called L(a) by : • (3a) If l(a)=0, (that is A_Data =0), then L(a) is the empty string. Note that l(a) is the length of a in octets. • (3b) If 0 < l(a) < 216 - 28 , then L(a) is the 2- octets encoding of l(a). The Additional Authentication Data is appended to the A_Data length field L(a). The Additional Authentication Blocks is padded with zeros until the last Additional Authentication Block is full. There is no restriction on the length of a. AUTH-DATA = L(a) + Authentication Data + (zero padding) (4) The last block of the message is padded with zeros until full (that is if its length is not a multiple of 128 bits). (5) The software concatenates the block B0, the Additional Authentication Blocks if any, and the message; Input message = B0 + AUTH-DATA + Message + (zero padding of message) (6) Once the input message authentication by CBC-MAC is finished, the software leaves the uploaded buffer contents unchanged (M=16), or keeps only the buffer’s higher M bytes Not Recommended for New Designs CC2430 Peripherals : AES Coprocessor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 138 of 211 unchanged, while setting the lower bits to 0 (M != 16). The result is called T. Message Encryption (7) The software creates the key stream block A0. Note that L=6, with the current example of the CTR generation. The content is shown in Figure 30. Note that when encrypting authentication data T to generate U in OFB mode, the CTR value must be zero. When encrypting message blocks using CTR mode, CTR value must be any value but zero. The content of the Encryption Flag byte is described in Figure 31. Name A0 Designation First CTR value for CCM mode Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Flag NONCE CTR Figure 30: Message Encryption Phase Block Name FLAG/A0 Designation Encryption Flag Field for CCM mode Bit 7 6 5 4 3 2 1 0 Name Reserved - L-1 Value 0 0 0 0 0 1 0 1 Figure 31: Encryption Flag Byte Message Encryption (cont.) (8) The software loads A0 by selecting a Load IV/Nonce command. To do so, it sets Mode to CFB or OFB at the same time it selects the Load IV/Nonce command. (9) The software calls a CFB or an OFB encryption on the authenticated data T. The uploaded buffer contents stay unchanged (M=16), or only its first M bytes stay unchanged, the others being set to 0 (M-16). The result is U, which will be used later. (10) The software calls a CTR mode encryption right now on the still padded message blocks. It has to reload the IV when CTR value is any value but zero. (11) The encrypted authentication data U is appended to the encrypted message. This gives the final result, c. Result c = encrypted message(m) + U Message Decryption CCM Mode decryption In the coprocessor, the automatic generation of CTR works on 32 bits, therefore the maximum length of a message is 128 x 232 bits, that is 236 bytes, which can be written in a six-bit word. So, the value L is set to 6. To decrypt a CCM mode processed message, the following sequence can be conducted (key is already loaded): Message Parsing Phase (1) The software parses the message by separating the M rightmost octets, namely U, and the other octets, namely string C. (2) C is padded with zeros until it can fill an integer number of 128-bit blocks; (3) U is padded with zeros until it can fill a 128- bit block. (4) The software creates the key stream block A0. It is done the same way as for CCM encryption. (5) The software loads A0 by selecting a Load IV/Nonce command. To do so, it sets Mode to CFB or OFB at the same time as it selects the IV load. (6) The software calls a CFB or an OFB encryption on the encrypted authenticated data U. The uploaded buffer contents stay unchanged (M=16), or only its first M bytes stay unchanged, the others being set to 0 (M!=16). The result is T. Not Recommended for New Designs CC2430 Peripherals : AES Coprocessor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 139 of 211 (7) The software calls a CTR mode decryption right now on the encrypted message blocks C. It does not have to reload the IV/CTR. Reference Authentication tag generation This phase is identical to the Authentication Phase of CCM encryption. The only difference is that the result is named MACTag (instead of T). Message Authentication checking Phase The software compares T with MACTag. 13.12.6 Sharing the AES coprocessor between layers The AES coprocessor is a common resource shared by all layers. The AES coprocessor can only be used by one instance one at a time. It is therefore necessary to implement some kind of software semaphore to allocate and deallocate the resource. 13.12.7 AES Interrupts The AES interrupt, ENC, is produced when encryption or decryption of a block is completed. The interrupt enable bit is IEN0.ENCIE and the interrupt flag is S0CON.ENCIF. 13.12.8 AES DMA Triggers There are two DMA triggers associated with the AES coprocessor. These are ENC_DW which is active when input data needs to be downloaded to the ENCDI register, and ENC_UP which is active when output data needs to be uploaded from the ENCDO register. The ENCDI and ENCDO registers should be set as destination and source locations for DMA channels used to transfer data to or from the AES coprocessor. 13.12.9 AES Registers The AES coprocessor registers have the layout shown in this section. Not Recommended for New Designs CC2430 Peripherals : AES Coprocessor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 140 of 211 ENCCS (0xB3) – Encryption Control and Status Bit Name Reset R/W Description 7 - 0 R0 Not used, always read as 0 Encryption/decryption mode 000 CBC 001 CFB 010 OFB 011 CTR 100 ECB 101 CBC MAC 110 Not used 6:4 MODE[2:0] 000 R/W 111 Not used Encryption/decryption ready status 0 Encryption/decryption in progress 3 RDY 1 R 1 Encryption/decryption is completed Command to be performed when a 1 is written to ST. 00 encrypt block 01 decrypt block 10 load key 2:1 CMD[1:0] 0 R/W 11 load IV/nonce 0 ST 0 R/W1 H0 Start processing command set by CMD. Must be issued for each command or 128 bits block of data. Cleared by hardware ENCDI (0xB1) – Encryption Input Data Bit Name Reset R/W Description 7:0 DIN[7:0] 0x00 R/W Encryption input data ENCDO (0xB2) – Encryption Output Data Bit Name Reset R/W Description 7:0 DOUT[7:0] 0x00 R/W Encryption output data Not Recommended for New Designs CC2430 Peripherals : Watchdog Timer CC2430 Data Sheet (rev. 2.1) SWRS036F Page 141 of 211 13.13 Watchdog Timer The watchdog timer (WDT) is intended as a recovery method in situations where the CPU may be subjected to a software upset. The WDT shall reset the system when software fails to clear the WDT within a selected time interval. The watchdog can be used in applications that are subject to electrical noise, power glitches, electrostatic discharge etc., or where high reliability is required. If the watchdog function is not needed in an application, it is possible to configure the watchdog timer to be used as an interval timer that can be used to generate interrupts at selected time intervals. The features of the watchdog timer are as follows: • Four selectable timer intervals • Watchdog mode • Timer mode • Interrupt request generation in timer mode • Clock independent from system clock The WDT is configured as either a watchdog timer or as a timer for general-purpose use. The operation of the WDT module is controlled by the WDCTL register. The watchdog timer consists of an 15-bit counter clocked by the 32.768 kHz clock. Note that the contents of the 15-bit counter is not user-accessible. The contents of the 15-bit counter is reset to 0x0000 when power modes PM2 or PM3 is entered. 13.13.1 Watchdog mode The watchdog timer is disabled after a system reset. To set the WDT in watchdog mode the WDCTL.MODE bit is set to 0. The watchdog timer counter starts incrementing when the enable bit WDCTL.EN is set to 1. When the timer is enabled in watchdog mode it is not possible to disable the timer. Therefore, writing a 0 to WDCTL.EN has no effect if a 1 was already written to this bit when WDCTL.MODE was 0. The WDT operates with a watchdog timer clock frequency of 32.768 kHz. This clock frequency gives time-out periods equal to 1.9 ms, 15.625 ms, 0.25 s and 1 s corresponding to the count value settings 64, 512, 8192 and 32768 respectively. If the counter reaches the selected timer interval value, the watchdog timer generates a reset signal for the system. If a watchdog clear sequence is performed before the counter reaches the selected timer interval value, the counter is reset to 0x0000 and continues incrementing its value. The watchdog clear sequence consists of writing 0xA to WDCTL.CLR[3:0] followed by writing 0x5 to the same register bits within one half of a watchdog clock period. If this complete sequence is not performed, the watchdog timer generates a reset signal for the system. Note that as long as a correct watchdog clear sequence begins within the selected timer interval, the counter is reset when the complete sequence has been received. When the watchdog timer has been enabled in watchdog mode, it is not possible to change the mode by writing to the WDCTL.MODE bit. The timer interval value can be changed by writing to the WDCTL.INT[1:0] bits. Note that it is recommended that user software clears the watchdog timer at the same time as the timer interval value is changed, in order to avoid an unwanted watchdog reset. In watchdog mode, the WDT does not produce an interrupt request. 13.13.2 Timer mode To set the WDT in normal timer mode, the WDCTL.MODE bit is set to 1. When register bit WDCTL.EN is set to 1, the timer is started and the counter starts incrementing. When the counter reaches the selected interval value, the timer will produce an interrupt request. In timer mode, it is possible to clear the timer contents by writing a 1 to WDCTL.CLR[0]. When the timer is cleared the contents of the counter is set to 0x0000. Writing a 0 to the enable bit WDCTL.EN stops the timer and writing 1 restarts the timer from 0x0000. The timer interval is set by the WDCTL.INT[1:0] bits. In timer mode, a reset will not be produced when the timer interval has been reached. 13.13.3 Watchdog and Power Modes In the two lowest power modes, PM2 and PM3, the watchdog is disabled and reset. After wake up it will still be enabled and configured as it was prior to entering PM2/3 mode, but Not Recommended for New Designs CC2430 Peripherals : Watchdog Timer CC2430 Data Sheet (rev. 2.1) SWRS036F Page 142 of 211 counting will start from zero. In PM1 the watchdog is still running, but it will not reset the chip while in PM1. This will not happen until it is woken up (it will wrap around and start over again when reset condition is reached). Also note that if the chip is woken in the watchdog timeout (reset condition) period the chip will be reset immediately. If woke up just prior to watchdog timeout the chip will be reset unless SW clears the watchdog immediately after waking up from PM1. As the sleep timer and the watchdog run on the same clock the watchdog timeout interval can be aligned with sleep timer interval so SW can be made able to reset the watchdog. For external interrupt wakeups the max watchdog time out period should be used and the sleep timer set so SW can be activated to clear the watchdog periodically while waiting for external interrupt events. 13.13.4 Watchdog Timer Register This section describes the register, WDCTL, for the Watchdog Timer. WDCTL (0xC9) – Watchdog Timer Control Bit Name Reset R/W Description 7:4 CLR[3:0] 0000 R/W Clear timer. When 0xA followed by 0x5 is written to these bits, the timer is loaded with 0x0. Note the timer will only be cleared when 0x5 is written within 0.5 watchdog clock period after 0xA was written. Writing to these bits when EN is 0 have no effect. Enable timer. When a 1 is written to this bit the timer is enabled and starts incrementing. Writing a 0 to this bit in timer mode stops the timer. Writing a 0 to this bit in watchdog mode has no effect. 0 Timer disabled (stop timer) 3 EN 0 R/W 1 Timer enabled Mode select. This bit selects the watchdog timer mode. 0 Watchdog mode 2 MODE 0 R/W 1 Timer mode Timer interval select. These bits select the timer interval defined as a given number of 32.768 kHz oscillator periods. 00 clock period x 32768 (typical 1 s) 01 clock period x 8192 (typical 0.25 s) 10 clock period x 512 (typical 15.625 ms) 1:0 INT[1:0] 00 R/W 11 clock period x 64 (typical 1.9 ms) Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 143 of 211 13.14 USART USART0 and USART1 are serial communications interfaces that can be operated separately in either asynchronous UART mode or in synchronous SPI mode. The two USARTs have identical function, and are assigned to separate I/O pins. Refer to section 13.1 for I/O configuration. 13.14.1 UART mode For asynchronous serial interfaces, the UART mode is provided. In the UART mode the interface uses a two-wire or four-wire interface consisting of the pins RXD, TXD and optionally RTS and CTS. The UART mode of operation includes the following features: • 8 or 9 data bits • Odd, even or no parity • Configurable start and stop bit level • Configurable LSB or MSB first transfer • Independent receive and transmit interrupts • Independent receive and transmit DMA triggers • Parity and framing error status The UART mode provides full duplex asynchronous transfers, and the synchronization of bits in the receiver does not interfere with the transmit function. A UART byte transfer consists of a start bit, eight data bits, an optional ninth data or parity bit, and one or two stop bits. Note that the data transferred is referred to as a byte, although the data can actually consist of eight or nine bits. The UART operation is controlled by the USART Control and Status registers, UxCSR and the UART Control register UxUCR where x is the USART number, 0 or 1. The UART mode is selected when UxCSR.MODE is set to 1. 13.14.1.1 UART Transmit A UART transmission is initiated when the USART Receive/transmit Data Buffer, UxDBUF register is written. The byte is transmitted on TXDx output pin. The UxDBUF register is double-buffered. The UxCSR.ACTIVE bit goes high when the byte transmission starts and low when it ends. When the transmission ends, the UxCSR.TX_BYTE bit is set to 1. An interrupt request is generated when the UxDBUF register is ready to accept new transmit data. This happens immediately after the transmission has been started, hence a new data byte value can be loaded into the data buffer while the byte is being transmitted. 13.14.1.2 UART Receive Data reception on the UART is initiated when a 1 is written to the UxCSR.RE bit. The UART will then search for a valid start bit on the RXDx input pin and set the UxCSR.ACTIVE bit high. When a valid start bit has been detected the received byte is shifted into the receive register. The UxCSR.RX_BYTE bit is set and a receive interrupt is generated when the operation has completed. At the same time UxCSR.ACTIVE will go low. The received data byte is available through the UxDBUF register. When UxDBUF is read, UxCSR.RX_BYTE is cleared by hardware. 13.14.1.3 UART Hardware Flow Control Hardware flow control is enabled when the UxUCR.FLOW bit is set to 1. The RTS output will then be driven low when the receive register is empty and reception is enabled. Transmission of a byte will not occur before the CTS input go low. 13.14.1.4 UART Character Format If the BIT9 and PARITY bits in register UxUCR are set high, parity generation and detection is enabled. The parity is computed and transmitted as the ninth bit, and during reception, the parity is computed and compared to the received ninth bit. If there is a parity error, the UxCSR.ERR bit is set high. This bit is cleared when UxCSR is read. The number of stop bits to be transmitted is set to one or two bits determined by the register bit UxUCR.SPB. The receiver will always check for one stop bit. If the first stop bit received during reception is not at the expected stop bit level, a framing error is signaled by setting register bit UxCSR.FE high. UxCSR.FE is cleared when UxCSR is read. Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 144 of 211 The receiver will check both stop bits when UxUCR.SPB is set. Note that the RX interrupt will be set when first stop bit is checked OK. If second stop bit is not OK there will be a delay in when the framing error bit, UxCSR.FE, is set. This delay is baud rate dependable (bit duration). 13.14.2 SPI Mode This section describes the SPI mode of operation for synchronous communication. In SPI mode, the USART communicates with an external system through a 3-wire or 4-wire interface. The interface consists of the pins MOSI, MISO, SCK and SS_N. Refer to section 13.1 for description of how the USART pins are assigned to the I/O pins. The SPI mode includes the following features: • 3-wire (master) and 4-wire SPI interface • Master and slave modes • Configurable SCK polarity and phase • Configurable LSB or MSB first transfer The SPI mode is selected when UxCSR.MODE is set to 0. In SPI mode, the USART can be configured to operate either as an SPI master or as an SPI slave by writing the UxCSR.SLAVE bit. 13.14.2.1 SPI Master Operation An SPI byte transfer in master mode is initiated when the UxDBUF register is written. The USART generates the SCK serial clock using the baud rate generator (see section 13.14.4) and shifts the provided byte from the transmit register onto the MOSI output. At the same time the receive register shifts in the received byte from the MISO input pin. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. When the transfer ends, the UxCSR.TX_BYTE bit is set to 1. The polarity and clock phase of the serial clock SCK is selected by UxGCR.CPOL and UxGCR.CPHA. The order of the byte transfer is selected by the UxGCR.ORDER bit. At the end of the transfer, the received data byte is available for reading from the UxDBUF. A receive interrupt is generated when this new data is ready in the UxDBUF USART Receive/Transmit Data register. A transmit interrupt is generated when the unit is ready to accept another data byte for transmission. Since UxDBUF is doublebuffered, this happens just after the transmission has been initiated. Note that data should not be written to UxDBUF until UxCSR.TX_BYTE is 1. For DMA transfers this is handled automatically. For back-to-back transmits using DMA the UxGDR.CPHA bit must be set to zero, if not transmitted bytes can become corrupted. For systems requiring setting of UxGDR.CPHA, polling UxCSR.TX_BYTE is needed. Also note the difference between transmit interrupt and receive interrupt as the former arrives approximately 8 bit periodes prior to the latter. SPI master mode operation as described above is a 3-wire interface. No select input is used to enable the master. If the external slave requires a slave select signal this can be implemented through software using a general-purpose I/O pin. 13.14.2.2 SPI Slave Operation An SPI byte transfer in slave mode is controlled by the external system. The data on the MOSI input is shifted into the receive register controlled by the serial clock SCK which is an input in slave mode. At the same time the byte in the transmit register is shifted out onto the MISO output. The UxCSR.ACTIVE bit goes high when the transfer starts and low when the transfer ends. Then the UxCSR.RX_BYTE bit is set and a receive interrupt is generated. The expected polarity and clock phase of SCK is selected by UxGCR.CPOL and UxGCR.CPHA. The expected order of the byte transfer is selected by the UxGCR.ORDER bit. Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 145 of 211 At the end of the transfer, the received data byte is available for reading from UxDBUF The transmit interrupt is generated at the start of the operation. 13.14.3 SSN Slave Select Pin When the USART is operating in SPI mode, configured as an SPI slave, a 4-wire interface is used with the Slave Select (SSN) pin as an input to the SPI (edge controlled). At falling edge of SSN the SPI slave is active and receives data on the MOSI input and outputs data on the MISO output. At rising edge of SSN, the SPI slave is inactive and will not receive data. Note that the MISO output is not tri-stated after rising edge on SSn. Also note that release of SSn (rising edge) must be aligned to end of byte recived or sent. If released in a byte the next received byte will not be received properly as information about previous byte is present in SPI system. A USART flush can be used to remove this information. In SPI master mode, the SSN pin is not used. When the USART operates as an SPI master and a slave select signal is needed by an external SPI slave device, then a general purpose I/O pin should be used to implement the slave select signal function in software. 13.14.4 Baud Rate Generation An internal baud rate generator sets the UART baud rate when operating in UART mode and the SPI master clock frequency when operating in SPI mode. The UxBAUD.BAUD_M[7:0] and UxGCR.BAUD_E[4:0] registers define the baud rate used for UART transfers and the rate of the serial clock for SPI transfers. The baud rate is given by the following equation: Baudrate BAUD M F BAUD E ∗ + ∗ = 28 _ 2 (256 _ ) 2 where F is the system clock frequency, 16 MHz (calibrated RC osc.) or 32 MHz (crystal osc.). The register values required for standard baud rates are shown in Table 43 for a typical system clock set to 32 MHz. The table also gives the difference in actual baud rate to standard baud rate value as a percentage error. The maximum baud rate for UART mode is F/16 when BAUD_E is 16 and BAUD_M is 0, and where F is the system clock frequency. The maximum baud rate for SPI master mode and thus SCK frequency is F/8. This is set when BAUD_E is 17 and BAUD_M is 0. If SPI master mode does not need to receive data the maximum SPI rate is F/2 where BAUD_E is 19 and BAUD_M is 0. Setting higher baud rates than this will give erroneous results. For SPI slave mode the maximum baud rate is always F/8. Note that the baud rate must be set through the UxBAUD and registers UxGCR before any other UART or SPI operations take place. This means that the timer using this information is not updated until it has completed its start conditions, thus changing the baud rate take time. Table 43: Commonly used baud rate settings for 32 MHz system clock Baud rate (bps) UxBAUD.BAUD_M UxGCR.BAUD_E Error (%) 2400 59 6 0.14 4800 59 7 0.14 9600 59 8 0.14 14400 216 8 0.03 19200 59 9 0.14 28800 216 9 0.03 38400 59 10 0.14 57600 216 10 0.03 76800 59 11 0.14 115200 216 11 0.03 230400 216 12 0.03 Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 146 of 211 13.14.5 USART flushing The current operation can be aborted by setting the UxUCR.FLUSH register bit. This event will stop the current operation and clear all data buffers. It should be noted that setting the flush bit in the middle of a TX/RX bit, the flushing will not take place until this bit has ended (buffers will be cleared immediately but timer keeping knowledge of bit duration will not). Thus using the flush bit should either be aligned with USART interrupts or use a wait time of one bit duration at current baud rate before updated data or configuration can be received by the USART. 13.14.6 USART Interrupts Each USART has two interrupts. These are the RX complete interrupt (URXx) and the TX complete interrupt (UTXx). The USART interrupt enable bits are found in the IEN0 and IEN2 registers. The interrupt flags are located in the TCON and IRCON2 registers. Refer to section 11.5 on page 49 for details of these registers. The interrupt enables and flags are summarized below. Interrupt enables: • USART0 RX : IEN0.URX0IE • USART1 RX : IEN0.URX1IE • USART0 TX : IEN2.UTX0IE • USART1 TX : IEN2.UTX1IE Interrupt flags: • USART0 RX : TCON.URX0IF • USART1 RX : TCON.URX1IF • USART0 TX : IRCON2.UTX0IF • USART1 TX : IRCON2.UTX1IF 13.14.7 USART DMA Triggers There are two DMA triggers associated with each USART. The DMA triggers are activated by RX complete and TX complete events i.e. the same events as the USART interrupt requests. A DMA channel can be configured using a USART Receive/transmit buffer, UxDBUF, as source or destination address. Refer to Table 41 on page 94 for an overview of the DMA triggers. 13.14.8 USART Registers The registers for the USART are described in this section. For each USART there are five registers consisting of the following (x refers to USART number i.e. 0 or 1): • UxCSR USART x Control and Status • UxUCR USART x UART Control • UxGCR USART x Generic Control • UxDBUF USART x Receive/Transmit data buffer • UxBAUD USART x Baud Rate Control Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 147 of 211 U0CSR (0x86) – USART 0 Control and Status Bit Name Reset R/W Description USART mode select 0 SPI mode 7 MODE 0 R/W 1 UART mode UART receiver enable 0 Receiver disabled 6 RE 0 R/W 1 Receiver enabled SPI master or slave mode select 0 SPI master 5 SLAVE 0 R/W 1 SPI slave UART framing error status 0 No framing error detected 4 FE 0 R/W0 1 Byte received with incorrect stop bit level UART parity error status 0 No parity error detected 3 ERR 0 R/W0 1 Byte received with parity error Receive byte status. UART mode and SPI slave mode 0 No byte received 2 RX_BYTE 0 R/W0 1 Received byte ready Transmit byte status. UART mode and SPI master mode 0 Byte not transmitted 1 TX_BYTE 0 R/W0 1 Last byte written to Data Buffer register transmitted USART transmit/receive active status 0 USART idle 0 ACTIVE 0 R 1 USART busy in transmit or receive mode Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 148 of 211 U0UCR (0xC4) – USART 0 UART Control Bit Name Reset R/W Description 7 FLUSH 0 R0/W1 Flush unit. When set, this event will stop the current operation and return the unit to idle state. UART hardware flow enable. Selects use of hardware flow control with RTS and CTS pins 0 Flow control disabled 6 FLOW 0 R/W 1 Flow control enabled UART data bit 9 contents. This value is used when 9 bit transfer is enabled. When parity is disabled, the value written to D9 is transmitted as the bit 9 when 9 bit data is enabled. If parity is enabled then this bit sets the parity level as follows. 0 Even parity 5 D9 0 R/W 1 Odd parity UART 9-bit data enable. When this bit is 1, data is 9 bits and the content of data bit 9 is given by D9 and PARITY. 0 8 bits transfer 4 BIT9 0 R/W 1 9 bits transfer UART parity enable. 0 Parity disabled 3 PARITY 0 R/W 1 Parity enabled UART number of stop bits. Selects the number of stop bits to transmit 0 1 stop bit 2 SPB 0 R/W 1 2 stop bits UART stop bit level 0 Low stop bit 1 STOP 1 R/W 1 High stop bit UART start bit level. The polarity of the idle line is assumed the opposite of the selected start bit level. 0 Low start bit 0 START 0 R/W 1 High start bit Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 149 of 211 U0GCR (0xC5) – USART 0 Generic Control Bit Name Reset R/W Description SPI clock polarity 0 Negative clock polarity 7 CPOL 0 R/W 1 Positive clock polarity SPI clock phase 0 Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted. 6 CPHA 0 R/W 1 Data is output on MOSI when SCK goes from CPOL to CPOL inverted, and data input is sampled on MISO when SCK goes from CPOL inverted to CPOL. Bit order for transfers 0 LSB first 5 ORDER 0 R/W 1 MSB first 4:0 BAUD_E[4:0] 0x00 R/W Baud rate exponent value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer Bit Name Reset R/W Description 7:0 DATA[7:0] 0x00 R/W USART receive and transmit data. When writing this register the data written is written to the internal, transmit data register. When reading this register, the data from the internal read data register is read. U0BAUD (0xC2) – USART 0 Baud Rate Control Bit Name Reset R/W Description 7:0 BAUD_M[7:0] 0x00 R/W Baud rate mantissa value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 150 of 211 U1CSR (0xF8) – USART 1 Control and Status Bit Name Reset R/W Description USART mode select 0 SPI mode 7 MODE 0 R/W 1 UART mode UART receiver enable 0 Receiver disabled 6 RE 0 R/W 1 Receiver enabled SPI master or slave mode select 0 SPI master 5 SLAVE 0 R/W 1 SPI slave UART framing error status 0 No framing error detected 4 FE 0 R/W0 1 Byte received with incorrect stop bit level UART parity error status 0 No parity error detected 3 ERR 0 R/W0 1 Byte received with parity error Receive byte status. UART mode and SPI slave mode 0 No byte received 2 RX_BYTE 0 R/W0 1 Received byte ready Transmit byte status. UART mode and SPI master mode 0 Byte not transmitted 1 TX_BYTE 0 R/W0 1 Last byte written to Data Buffer register transmitted USART transmit/receive active status 0 USART idle 0 ACTIVE 0 R 1 USART busy in transmit or receive mode Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 151 of 211 U1UCR (0xFB) – USART 1 UART Control Bit Name Reset R/W Description 7 FLUSH 0 R0/W1 Flush unit. When set, this event will immediately stop the current operation and return the unit to idle state. UART hardware flow enable. Selects use of hardware flow control with RTS and CTS pins 0 Flow control disabled 6 FLOW 0 R/W 1 Flow control enabled UART data bit 9 contents. This value is used 9 bit transfer is enabled. When parity is disabled, the value written to D9 is transmitted as the bit 9 when 9 bit data is enabled. If parity is enabled then this bit sets the parity level as follows. 0 Even parity 5 D9 0 R/W 1 Odd parity UART 9-bit data enable. When this bit is 1, data is 9 bits and the content of data bit 9 is given by D9 and PARITY. 0 8 bits transfer 4 BIT9 0 R/W 1 9 bits transfer UART parity enable. 0 Parity disabled 3 PARITY 0 R/W 1 Parity enabled UART number of stop bits. Selects the number of stop bits to transmit 0 1 stop bit 2 SPB 0 R/W 1 2 stop bits UART stop bit level 0 Low stop bit 1 STOP 1 R/W 1 High stop bit UART start bit level. The polarity of the idle line is assumed the opposite of the selected start bit level. 0 Low start bit 0 START 0 R/W 1 High start bit Not Recommended for New Designs CC2430 Peripherals : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 152 of 211 U1GCR (0xFC) – USART 1 Generic Control Bit Name Reset R/W Description SPI clock polarity 0 Negative clock polarity 7 CPOL 0 R/W 1 Positive clock polarity SPI clock phase 0 Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input is sampled on MISO when SCK goes from CPOL to CPOL inverted. 6 CPHA 0 R/W 1 Data is output on MOSI when SCK goes from CPOL to CPOL inverted, and data input is sampled on MISO when SCK goes from CPOL inverted to CPOL. Bit order for transfers 0 LSB first 5 ORDER 0 R/W 1 MSB first 4:0 BAUD_E[4:0] 0x00 R/W Baud rate exponent value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency U1DBUF (0xF9) – USART 1 Receive/Transmit Data Buffer Bit Name Reset R/W Description 7:0 DATA[7:0] 0x00 R/W USART receive and transmit data. When writing this register the data written is written to the internal, transmit data register. When reading this register, the data from the internal read data register is read. U1BAUD (0xFA) – USART 1 Baud Rate Control Bit Name Reset R/W Description 7:0 BAUD_M[7:0] 0x00 R/W Baud rate mantissa value. BAUD_E along with BAUD_M decides the UART baud rate and the SPI master SCK clock frequency Not Recommended for New Designs CC2430 Radio : USART CC2430 Data Sheet (rev. 2.1) SWRS036F Page 153 of 211 14 Radio LNA DIGITAL DEMODULATOR - Digital RSSI - Gain Control - Image Suppression - Channel Filtering - Demodulation - Frame synchronization DIGITAL MODULATOR - Data spreading - Modulation Σ AUTOMATIC GAIN CONTROL TX POWER CONTROL TXRX SWITCH ADC ADC DAC DAC 0 90 FREQ SYNTH Power Control PA FFCTRL Register bus CSMA/CA STROBE PROCESSOR RADIO REGISTER BANK RADIO DATA INTERFACE CONTROL LOGIC IRQ HANDLING SFR bus Figure 32: CC2430 Radio Module A simplified block diagram of the IEEE 802.15.4 compliant radio inside CC2430 is shown in Figure 32. The radio core is based on the industry leading CC2420 RF transceiver. CC2430 features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF (2 MHz), the complex I/Q signal is filtered and amplified, and then digitized by the RF receiver ADCs. Automatic gain control, final channel filtering, despreading, symbol correlation and byte synchronization are performed digitally. An interrupt indicates that a start of frame delimiter has been detected. CC2430 buffers the received data in a 128 byte receive FIFO. The user may read the FIFO through an SFR interface. It is recommended to use direct memory access (DMA) to move data between memory and the FIFO. CRC is verified in hardware. RSSI and correlation values are appended to the frame. Clear channel assessment, CCA, is available through an interrupt in receive mode. The CC2430 transmitter is based on direct upconversion. The data is buffered in a 128 byte transmit FIFO (separate from the receive FIFO). The preamble and start of frame delimiter are generated in hardware. Each symbol (4 bits) is spread using the IEEE 802.15.4 spreading sequence to 32 chips and output to the digital-to-analog converters (DACs). An analog low pass filter passes the signal to the quadrature (I and Q) up-conversion mixers. The RF signal is amplified in the power amplifier (PA) and fed to the antenna. The internal T/R switch circuitry makes the antenna interface and matching easy. The RF connection is differential. A balun may be used for single-ended antennas. The biasing of the PA and LNA is done by connecting TXRX_SWITCH to RF_P and RF_N through an external DC path. The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the I and Q LO signals to the down-conversion mixers in receive mode and up-conversion mixers in transmit mode. The VCO operates in the frequency range 4800 – 4966 MHz, and the frequency is divided by two when split into I and Q signals. The digital baseband includes support for frame handling, address recognition, data buffering, CSMA-CA strobe processor and MAC security. An on-chip voltage regulator delivers the regulated 1.8 V supply voltage. Not Recommended for New Designs CC2430 Radio : IEEE 802.15.4 Modulation Format CC2430 Data Sheet (rev. 2.1) SWRS036F Page 154 of 211 14.1 IEEE 802.15.4 Modulation Format This section is meant as an introduction to the 2.4 GHz direct sequence spread spectrum (DSSS) RF modulation format defined in IEEE 802.15.4. For a complete description, please refer to [1]. The modulation and spreading functions are illustrated at block level in Figure 33 [1]. Each byte is divided into two symbols, 4 bits each. The least significant symbol is transmitted first. For multi-byte fields, the least significant byte is transmitted first. Each symbol is mapped to one out of 16 pseudo-random sequences, 32 chips each. The symbol to chip mapping is shown in Table 44. The chip sequence is then transmitted at 2 MChips/s, with the least significant chip (C0) transmitted first for each symbol. Bit-to- Symbol Symbolto- Chip O-QPSK Modulator Transmitted bit-stream (LSB first) Modulated Signal Figure 33: Modulation and spreading functions [1] The modulation format is Offset – Quadrature Phase Shift Keying (O-QPSK) with half-sine chip shaping. This is equivalent to MSK modulation. Each chip is shaped as a halfsine, transmitted alternately in the I and Q channels with one half chip period offset. This is illustrated for the zero-symbol in Figure 34. Table 44: IEEE 802.15.4 symbol-to-chip mapping [1] Symbol Chip sequence (C0, C1, C2, … , C31) 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 2 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 3 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 4 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 5 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 6 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 7 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 8 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 9 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 10 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 11 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 12 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 13 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 14 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 15 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 Not Recommended for New Designs CC2430 Radio : Command strobes CC2430 Data Sheet (rev. 2.1) SWRS036F Page 155 of 211 1 0 1 0 1 1 0 1 I-phase Q-phase 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 TC 2TC Figure 34: I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 μs 14.2 Command strobes The CPU uses a set of command strobes to control operation of the radio in CC2430. Command strobes may be viewed as single byte instructions which each control some function of the radio. These command strobes must be used to enable the frequency synthesizer, enable receive mode, enable transmit mode and other functions. A total of nine command strobes are defined for the radio and these can be written individually to the radio or they can be given in a sequence together with a set of dedicated software instructions making up a simple program. All command strobes from the CPU to the radio pass through the CSMACA/ Command Strobe Processor (CSP). Detailed description about the CSP and how command strobes are used is given in section 14.34 on page 176. 14.3 RF Registers The operation of the radio is configured through a set of RF registers. These RF registers are mapped to XDATA memory space as shown in Figure 7 on page 31. The RF registers also provide status information from the radio. The RF registers control/status bits are referred to where appropriate in the following sections while section 14.35 on page 183 gives a full description of all RF registers. 14.4 Interrupts The radio is associated with two interrupt vectors on the CPU. These are the RFERR interrupt (interrupt 0) and the RF interrupt (interrupt 12) with the following functions • RFERR : TXFIFO underflow, RXFIFO overflow • RF : all other RF interrupts given by RFIF interrupt flags The RF interrupt vector combines the interrupts in RFIF shown on page 156. Note that these RF interrupts are rising- edge triggered. Thus an interrupt is generated when e.g. the SFD status flag goes from 0 to 1. The RFIF interrupt flags are described in the next section. 14.4.1 Interrupt registers Two of the main interrupt control SFR registers are used to enable the RF and RFERR interrupts. These are the following: • RFERR : IEN0.RFERRIE • RF : IEN2.RFIE Two main interrupt flag SFR registers hold the RF and RFERR interrupt flags. These are the following: • RFERR : TCON.RFERRIF • RF : S1CON.RFIF Refer to section 11.5 on page 49 for details about the interrupts. The RF interrupt is the combined interrupt from eight different sources in the radio. Two SFR registers are used for setting the eight individual RFIF radio interrupt flags and interrupt enables. These are the RFIF and RFIM registers. Not Recommended for New Designs CC2430 Radio : Interrupts CC2430 Data Sheet (rev. 2.1) SWRS036F Page 156 of 211 The interrupt flags in SFR register RFIF show the status for each interrupt source for the RF interrupt vector. The interrupt enable bits in RFIM are used to disable individual interrupt sources for the RF interrupt vector. Note that masking an interrupt source in RFIM does not affect the update of the status in the RFIF register. Due to the use of the individual interrupt masks in RFIM, and the main interrupt mask for the RF interrupt given by IEN2.RFIE there is two-layered masking of this interrupt. Special attention needs to be taken when processing this type of interrupt as described below. To clear the RF interrupt, S1CON.RFIF and the interrupt flag in RFIF need to be cleared. If more than one interrupt source generates an interrupt the source that was not cleared will generate another interrupt after completing the interrupt service routine (ISR). A RFIF flag that was set and was not cleared during ISR will create another interrupt when ISR completed. If no individual knowlage of which interrupt caused the ISR to be called, all RFIF flags should be cleared. RFIF (0xE9) – RF Interrupt Flags Bit Name Reset R/W Description Voltage regulator for radio has been turned on 0 No interrupt pending 7 IRQ_RREG_ON 0 R/W0 1 Interrupt pending TX completed with packet sent. Also set for acknowledge frames if RF register IRQSRC.TXACK is 1 0 No interrupt pending 6 IRQ_TXDONE 0 R/W0 1 Interrupt pending Number of bytes in RXFIFO is above threshold set by IOCFG0.FIFOP_THR 0 No interrupt pending 5 IRQ_FIFOP 0 R/W0 1 Interrupt pending Start of frame delimiter (SFD) has been detected 0 No interrupt pending 4 IRQ_SFD 0 R/W0 1 Interrupt pending Clear channel assessment (CCA) indicates that channel is clear 0 No interrupt pending 3 IRQ_CCA 0 R/W0 1 Interrupt pending CSMA-CA/strobe processor (CSP) wait condition is true 0 No interrupt pending 2 IRQ_CSP_WT 0 R/W0 1 Interrupt pending CSMA-CA/strobe processor (CSP) program execution stopped 0 No interrupt pending 1 IRQ_CSP_STOP 0 R/W0 1 Interrupt pending CSMA-CA/strobe processor (CSP) INT instruction executed 0 No interrupt pending 0 IRQ_CSP_INT 0 R/W0 1 Interrupt pending Not Recommended for New Designs CC2430 Radio : FIFO access CC2430 Data Sheet (rev. 2.1) SWRS036F Page 157 of 211 RFIM (0x91) – RF Interrupt Mask Bit Name Reset R/W Description Voltage regulator for radio has been turned on 0 Interrupt disabled 7 IM_RREG_PD 0 R/W 1 Interrupt enabled TX completed with packet sent. Also for acknowledge frames if RF register IRQSRC.TXACK is 1 0 Interrupt disabled 6 IM_TXDONE 0 R/W 1 Interrupt enabled Number of bytes in RXFIFO is above threshold set by IOCFG0.FIFOP_THR 0 Interrupt disabled 5 IM_FIFOP 0 R/W 1 Interrupt enabled Start of frame delimiter (SFD) has been detected 0 Interrupt disabled 4 IM_SFD 0 R/W 1 Interrupt enabled Clear channel assessment (CCA) indicates that channel is clear 0 Interrupt disabled 3 IM_CCA 0 R/W 1 Interrupt enabled CSMA-CA/strobe processor (CSP) wait condition is true 0 Interrupt disabled 2 IM_CSP_WT 0 R/W 1 Interrupt enabled CSMA-CA/strobe processor (CSP) program execution stopped 0 Interrupt disabled 1 IM_CSP_STOP 0 R/W 1 Interrupt enabled CSMA-CA/strobe processor (CSP) INT instruction executed 0 Interrupt disabled 0 IM_CSP_INT 0 R/W 1 Interrupt enabled 14.5 FIFO access The TXFIFO and RXFIFO may be accessed through the SFR register RFD (0xD9). Data is written to the TXFIFO when writing to the RFD register. Data is read from the he RXFIFO when the RFD register is read. The RF register bits RFSTATUS.FIFO and RFSTATUS.FIFOP provide information on the data in the receive FIFO, as described in section 14.6 on page 157. Note that the RFSTATUS.FIFO and RFSTATUS.FIFOP only apply to the RXFIFO. The TXFIFO may be flushed by issuing a SFLUSHTX command strobe. Similarly, a SFLUSHRX command strobe will flush the receive FIFO. The FIFO may contain 256 bytes (128 bytes for RX and 128 bytes for TX). RFD (0xD9) – RF Data Bit Name Reset R/W Description 7:0 RFD[7:0] 0x00 R/W Data written to the register is written to the TXFIFO. When reading this register, data from the RXFIFO is read 14.6 DMA It is possible, and in most cases recommended, to use direct memory access (DMA) to move data between memory and the radio. The DMA controller is described in section 13.5. Refer to this section for a detailed description on how to setup and use DMA transfers. To support the DMA controller there is one DMA trigger associated with the radio, this is the RADIO DMA trigger (DMA trigger 19). The RADIO DMA trigger is activated by two events. The first event to cause a RADIO DMA trigger, is when the first data is present in the RXFIFO, i.e. when the RXFIFO goes from the empty state to the non-empty state. The second Not Recommended for New Designs CC2430 Radio : Receive mode CC2430 Data Sheet (rev. 2.1) SWRS036F Page 158 of 211 event that causes a RADIO DMA trigger, is when data is read from the RXFIFO (through RFD SFR register) and there is still more data available in the RXFIFO. 14.7 Receive mode In receive mode, the interrupt flag RFIF.IRQ_SFD goes high and the RF interrupt is requested after the start of frame delimiter (SFD) field has been completely received. If address recognition is disabled or is successful, the RFSTATUS.SFD bit goes low again only after the last byte of the MPDU has been received. If the received frame fails address recognition, the RFSTATUS.SFD bit goes low immediately. This is illustrated in Figure 35. The RFSTATUS.FIFO bit is high when there is one or more data bytes in the RXFIFO. The first byte to be stored in the RXFIFO is the length field of the received frame, i.e. the RFSTATUS.FIFO bit is set high when the length field is written to the RXFIFO. The RFSTATUS.FIFO bit then remains high until the RXFIFO is empty. The RF register RXFIFOCNT contains the number of bytes present in the RXFIFO. The RFSTATUS.FIFOP bit is high when the number of unread bytes in the RXFIFO exceeds the threshold programmed into IOCFG0.FIFOP_THR. When address recognition is enabled the RFSTATUS.FIFOP bit will not go high until the incoming frame passes address recognition, even if the number of bytes in the RXFIFO exceeds the programmed threshold. The RFSTATUS.FIFOP bit will also go high when the last byte of a new packet is received, even if the threshold is not exceeded. If so the RFSTATUS.FIFOP bit will go back to low once one byte has been read out of the RXFIFO. When address recognition is enabled, data should not be read out of the RXFIFO before the address is completely received, since the frame may be automatically flushed by CC2430 if it fails address recognition. This may be handled by using the RFSTATUS.FIFOP bit, since this bit does not go high until the frame passes address recognition. Figure 36 shows an example of status bit activity when reading a packet from the RXFIFO. In this example, the packet size is 8 bytes, IOCFG0.FIFOP_THR = 3 and MDMCTRL0L.AUTOCRC is set. The length will be 8 bytes, RSSI will contain the average RSSI level during receiving of the packet and FCS/corr contains information of FCS check result and the correlation levels. 14.8 RXFIFO overflow The RXFIFO can only contain a maximum of 128 bytes at a given time. This may be divided between multiple frames, as long as the total number of bytes is 128 or less. If an overflow occurs in the RXFIFO, this is signaled to the CPU by asserting the RFERR interrupt when enabled. In addition the radio will set RFSTATUS.FIFO bit low while the RFSTATUS.FIFOP bit is high. Data already in the RXFIFO will not be affected by the overflow, i.e. frames already received may be read out. A SFLUSHRX command strobe is required after a RXFIFO overflow to enable reception of new data. Not Recommended for New Designs CC2430 Radio : Transmit mode CC2430 Data Sheet (rev. 2.1) SWRS036F Page 159 of 211 Data received over RF Preamble SFD Length SFD FIFO FIFOP , if threshold higher than frame length FIFOP , if threshold lower than frame length SFD detected Length byte received Last MPDU byte received Data received over RF Preamble SFD Length SFD FIFO FIFOP Address regocnition completed MAC Protocol Data Unit (MPDU) with correct address MAC Protocol Data Unit (MPDU) with wrong address Address recognition OK Address recognition fails Figure 35: SFD, FIFO and FIFOP activity examples during receive Figure 36: Example of status activity when reading RXFIFO. 14.9 Transmit mode During transmit the RFSTATUS.FIFO and RFSTATUS.FIFOP bits are still only related to the RXFIFO. The RFSTATUS.SFD bit is however active during transmission of a data frame, as shown in Figure 37. The RFIF.IRQ_SFD interrupt flag goes high and the RF interrupt is requested when the SFD field has been completely transmitted. It goes low again when the complete MPDU (as defined by the length field) has been transmitted or if an underflow is detected. The interrupt RFERR is then asserted if enabled. See section 14.17.1 on page 163 for more information on TXFIFO underflow. As can be seen from comparing Figure 35 and Figure 37, the RFSTATUS.SFD bit behaves very similarly during reception and transmission of a data frame. If the RFSTATUS.SFD bits of the transmitter and the receiver are compared during the transmission of a data frame, a small delay between 3.076 μs and 3.284 μs can be seen because of bandwidth limitations in both the transmitter and the receiver. Not Recommended for New Designs CC2430 Radio : General control and status CC2430 Data Sheet (rev. 2.1) SWRS036F Page 160 of 211 Preamble SFD Lengt h Data transmitted over RF SFD SFD transmitted Last MPDU byte transmitted or TX underflow MAC Protocol Data Unit (MPDU) STXON command strobe 12 symbol periods Automatically generated preamble and SFD Data fetched from TXFIFO CRC generated Figure 37: SFD status activity example during transmit 14.10 General control and status In receive mode, the RFIF.IRQ_FIFOP interrupt flag and RF interrupt request can be used to interrupt the CPU when a threshold has been exceeded or a complete frame has been received. In receive mode, the RFSTATUS.FIFO bit can be used to detect if there is data at all in the receive FIFO. The RFIF.IRQ_SFD interrupt flag can be used to extract the timing information of transmitted and received data frames. The RFIF.IRQ_SFD bit will go high when a start of frame delimiter has been completely detected / transmitted. For debug purposes, the RFSTATUS.SFD, RFSTATUS.FIFO, RFSTATUS.FIFOP and RFSTATUS.CCA bits can be output onto P1.7 – P1.4 I/O pins to monitor the status of these signals as selected by the IOCFG0, IOCFG1 and IOCFG2 register. The polarity of these signals given on the debug outputs can also be controlled by the IOCFG0-2 registers, if needed. 14.11 Demodulator, Symbol Synchronizer and Data Decision The block diagram for the CC2430 demodulator is shown in Figure 38. Channel filtering and frequency offset compensation is performed digitally. The signal level in the channel is estimated to generate the RSSI level (see the RSSI / Energy Detection section on page 168 for more information). Data filtering is also included for enhanced performance. With the ±40 ppm frequency accuracy requirement from [1], a compliant receiver must be able to compensate for up to 80 ppm or 200 kHz. The CC2430 demodulator tolerates up to 300 kHz offset without significant degradation of the receiver performance. Soft decision is used at the chip level, i.e. the demodulator does not make a decision for each chip, only for each received symbol. Despreading is performed using over-sampling symbol correlators. Symbol synchronization is achieved by a continuous start of frame delimiter (SFD) search. When an SFD is detected, data is written to the RXFIFO and may be read out by the CPU at a lower bit rate than the 250 kbps generated by the receiver. The CC2430 demodulator also handles symbol rate errors in excess of 120 ppm without performance degradation. Resynchronization is performed continuously to adjust for error in the incoming symbol rate. The RF register MDMCTRL1H.CORR_THR control bits should be written to 0x14 to set the threshold for detecting IEEE 802.15.4 start of frame delimiters. Not Recommended for New Designs CC2430 Radio : Frame Format CC2430 Data Sheet (rev. 2.1) SWRS036F Page 161 of 211 Digital IF Channel Filtering ADC Digital Data Filtering Frequency Offset Compensation Symbol Correlators and Synchronisation RSSI Generator I / Q Analog IF signal Data Symbol Output RSSI Average Correlation Value (may be used for LQI) Figure 38: Demodulator Simplified Block Diagram 14.12 Frame Format CC2430 has hardware support for parts of the IEEE 802.15.4 frame format. This section gives a brief summary to the IEEE 802.15.4 frame format, and describes how CC2430 is set up to comply with this. Figure 39 [1] shows a schematic view of the IEEE 802.15.4 frame format. Similar figures describing specific frame formats (data frames, beacon frames, acknowledgment frames and MAC command frames) are included in [1]. Figure 39: Schematic view of the IEEE 802.15.4 Frame Format [1] 14.13 Synchronization header The synchronization header (SHR) consists of the preamble sequence followed by the start of frame delimiter (SFD). In [1], the preamble sequence is defined to be four bytes of 0x00. The SFD is one byte, set to 0xA7. In CC2430, the preamble length and SFD is configurable. The default values are compliant with [1]. Changing these values will make the system non-compliant to IEEE 802.15.4. A synchronization header is always transmitted first in all transmit modes. The preamble sequence length can be set with RF register bit MDMCTRL0L.PREAMBLE_LENGTH, while the SFD is programmed in the SYNCWORDH:SYNCWORDL registers. SYNCWORDH:SYNCWORDL is two bytes long, which gives the user some extra flexibility as described below. Figure 40 shows how the CC2430 synchronization header relates to the IEEE 802.15.4 specification. The programmable preamble length only applies to transmission, it does not affect receive mode. The preamble length should not be set shorter than the default value. Note that 2 of the 8 zero-symbols in the preamble sequence required by [1] are included in the SYNCWORDH:SYNCWORDL registers so that the CC2430 preamble sequence is only 6 symbols long for compliance with [1]. Two additional zero symbols in SYNCWORDH:SYNCWORDL make CC2430 compliant with [1]. In reception, CC2430 synchronizes to received zero-symbols and searches for the SFD sequence defined by the SYNCWORDH:SYNCWORDL registers. The least significant symbols in SYNCWORDH:SYNCWORDL set to 0xF will be ignored, while symbols different from 0xF will be required for synchronization. The default setting of 0xA70F thereby requires one additional zero-symbol for synchronization. This will reduce the number of false frames detected due to noise. PHY Layer Frame Control Field (FCF) Data Sequence Number Bytes: 2 1 Address Information 0 to 20 Frame payload n Frame Check Sequence (FCS) 2 MAC Header (MHR) MAC Payload MAC Footer (MFR) Frame Length MAC Protocol Data Unit (MPDU) Start of frame Delimiter (SFD) Bytes: 1 1 5 + (0 to 20) + n Preamble Sequence 4 Synchronisation Header (SHR) PHY Header (PHR) PHY Service Data Unit (PSDU) PHY Protocol Data Unit (PPDU) 11 + (0 to 20) + n MAC Layer Not Recommended for New Designs CC2430 Radio : Length field CC2430 Data Sheet (rev. 2.1) SWRS036F Page 162 of 211 In receive mode CC2430 uses the preamble sequence for symbol synchronization and frequency offset adjustments. The SFD is used for byte synchronization, and is not part of the data stored in the receive buffer (RXFIFO). IEEE 802.15.4 0 7 A Preamble SFD 2·(PREAMBLE_LENGTH + 1) zero symbols 0 0 0 0 0 0 0 SW0 SW0 = SYNCWORD[3:0] SW1 = SYNCWORD[7:4] SW2 = SYNCWORD[11:8] SW3 = SYNCWORD[15:12] SW1 SW2 SW3 if different from 'F', else '0' if different from 'F', else '0' if different from 'F', else '0' if different from 'F', else '0' Synchronisation Header Figure 40: Transmitted Synchronization Header 14.14 Length field The frame length field shown in Figure 39 defines the number of bytes in the MPDU. Note that the length field does not include the length field itself. It does however include the FCS (Frame Check Sequence), even if this is inserted automatically by CC2430 hardware. The length field is 7 bits and has a maximum value of 127. The most significant bit in the length field is reserved [1], and should be set to zero. CC2430 uses the length field both for transmission and reception, so this field must always be included. In transmit mode, the length field is used for underflow detection, as described in the FIFO access section on page 157. 14.15 MAC protocol data unit The FCF, data sequence number and address information follows the length field as shown in Figure 39. Together with the MAC data payload and Frame Check Sequence, they form the MAC Protocol Data Unit (MPDU). The format of the FCF is shown in Figure 41. Please refer to [1] for details. There is no hardware support for the data sequence number, this field must be inserted and verified by software. CC2430 includes hardware address recognition, as described in the Address Recognition section on page 164. Bits: 0-2 3 4 5 6 7-9 10-11 12-13 14-15 Frame Type Security Enabled Frame Pending Acknowledge request Intra PAN Reserved Destination addressing mode Reserved Source addressing mode Figure 41: Format of the Frame Control Field (FCF) [1] 14.16 Frame check sequence A 2-byte frame check sequence (FCS) follows the last MAC payload byte as shown in Figure 39. The FCS is calculated over the MPDU, i.e. the length field is not part of the FCS. This field is automatically generated and verified by hardware when the RF register MDMCTRL0L.AUTOCRC control bit is set. It is recommended to always have this enabled, except possibly for debug purposes. If cleared, CRC generation and verification must be performed by software. The FCS polynomial is [1]: x16 + x12 + x5 + 1 Not Recommended for New Designs CC2430 Radio : RF Data Buffering CC2430 Data Sheet (rev. 2.1) SWRS036F Page 163 of 211 The CC2430 hardware implementation is shown in Figure 42. Please refer to [1] for further details. In transmit mode the FCS is appended at the correct position defined by the length field. The FCS is not written to the TXFIFO, but stored in a separate 16-bit register. In receive mode the FCS is verified by hardware. The user is normally only interested in the correctness of the FCS, not the FCS sequence itself. The FCS sequence itself is therefore not written to the RXFIFO during receive. Instead, when MDMCTRL0L.AUTOCRC is set the two FCS bytes are replaced by the RSSI value, average correlation value (used for LQI) and CRC OK/not OK. This is illustrated in Figure 43. The first FCS byte is replaced by the 8-bit RSSI value. See the RSSI section on page 168 for details. The seven least significant bits in the last FCS byte are replaced by the average correlation value of the 8 first symbols of the received PHY header (length field) and PHY Service Data Unit (PSDU). This correlation value may be used as a basis for calculating the LQI. See the Link Quality Indication section on page 168 for details. The most significant bit in the last byte of each frame is set high if the CRC of the received frame is correct and low otherwise. r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 Data input (LSB first) Figure 42: CC2430 Frame Check Sequence (FCS) hardware implementation [1] Length byte MPDU n MPDU1 MPDU2 MPDUn-2 RSSI (signed) CRC / Corr Bit number 7 6 5 4 3 2 1 0 CRC OK Correlation value (unsigned) Data in RXFIFO Figure 43: Data in RXFIFO when MDMCTRL0L.AUTOCRC is set 14.17 RF Data Buffering CC2430 can be configured for different transmit and receive modes, as set in the MDMCTRL1L.TX_MODE and MDMCTRL1L.RX_MODE control bits. Buffered mode (mode 0) will be used for normal operation of CC2430, while other modes are available for test purposes. 14.17.1 Buffered transmit mode In buffered transmit mode (TX_MODE=0), the 128 byte TXFIFO is used to buffer data before transmission. A synchronization header is automatically inserted before the length field during transmission. The length field must always be the first byte written to the transmit buffer for all frames. Writing one or multiple bytes to the TXFIFO is described in the FIFO access section on page 157. A DMA transfer can be configured to write transmit data to the TXFIFO. Transmission is enabled by issuing a STXON or STXONCCA command strobe. See the Radio control state machine section on page 166 for an illustration of how the transmit command strobes affect the state of CC2430. The STXONCCA strobe is ignored if the channel is busy. See section 14.25 on page 169 for details on CCA. The preamble sequence is started 12 symbol periods after the transmit command strobe. After the programmable start of frame delimiter Not Recommended for New Designs CC2430 Radio : Address Recognition CC2430 Data Sheet (rev. 2.1) SWRS036F Page 164 of 211 has been transmitted, data is fetched from the TXFIFO. The TXFIFO can only contain one data frame at a given time. After complete transmission of a data frame, the TXFIFO is automatically refilled with the last transmitted frame. Issuing a new STXON or STXONCCA command strobe will then cause CC2430 to retransmit the last frame. Writing to the TXFIFO after a frame has been transmitted will cause the TXFIFO to be automatically flushed before the new byte is written. The only exception is if a TXFIFO underflow has occurred, when a SFLUSHTX command strobe is required. 14.17.2 Buffered receive mode In buffered receive mode (RX_MODE 0), the 128 byte RXFIFO, located in CC2430 RAM, is used to buffer data received by the demodulator. Accessing data in the RXFIFO is described in the FIFO access section on page 157. The RF interrupt generated by RFSTATUS.FIFOP and also the RFSTATUS.FIFO and RFSTATUS.FIFOP register bits are used to assist the CPU in supervising the RXFIFO. Please note that these status bits are only related to the RXFIFO, even if CC2430 is in transmit mode. A DMA transfer should be used to read data from the RXFIFO. In this case a DMA channel can be setup to use the RADIO DMA trigger (see DMA triggers on page 94) to initiate a DMA transfer using the RFD register as the DMA source. Multiple data frames may be in the RXFIFO simultaneously, as long as the total number of bytes does not exceed 128. See the RXFIFO overflow section on page 158 for details on how a RXFIFO overflow is detected and signaled. 14.18 Address Recognition CC2430 includes hardware support for address recognition, as specified in [1]. Hardware address recognition may be enabled or disabled using the MDMCTRL0H.ADDR_DECODE control bit. Address recognition uses the following RF registers • IEEE_ADDR7-IEEE_ADDR0 • PANIDH:PANIDL • SHORTADDRH:SHORTADDRL. Address recognition is based on the following requirements, listed from section 7.5.6.2 in [1]: • The frame type subfield shall not contain an illegal frame type • If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier. • If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). • If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise if an extended destination address is included in the frame, it shall match aExtendedAddress. • If only source addressing fields are included in a data or MAC command frame, the frame shall only be accepted if the device is a PAN coordinator and the source PAN identifier matches macPANId. If any of the above requirements are not satisfied and address recognition is enabled, CC2430 will disregard the incoming frame and flush the data from the RXFIFO. Only data from the rejected frame is flushed, data from previously accepted frames may still be in the RXFIFO. Incoming frames are first subject to frame type filtering according to the setting of the MDMCTRL0H.FRAMET_FILT register bit. Following the required frame type filtering, incoming frames with reserved frame types (FCF frame type subfield is 4, 5, 6 or 7) are however accepted if the RESERVED_FRAME_MODE control bit in the RF register MDMCTRL0H is set. In this case, no further address recognition is performed on Not Recommended for New Designs CC2430 Radio : Acknowledge Frames CC2430 Data Sheet (rev. 2.1) SWRS036F Page 165 of 211 these frames. This option is included for future expansions of the IEEE 802.15.4 standard. If a frame is rejected, CC2430 will only start searching for a new frame after the rejected frame has been completely received (as defined by the length field) to avoid detecting false SFDs within the frame. The MDMCTRL0.PAN_COORDINATOR control bit must be correctly set, since parts of the address recognition procedure requires knowledge about whether the current device is a PAN coordinator or not. 14.19 Acknowledge Frames CC2430 includes hardware support for transmitting acknowledge frames, as specified in [1]. Figure 44 shows the format of the acknowledge frame. If MDMCTRL0L.AUTOACK is enabled, an acknowledge frame is transmitted for all incoming frames accepted by the address recognition with the acknowledge request flag set and a valid CRC. AUTOACK therefore does not make sense unless also ADDR_DECODE and AUTOCRC are enabled. The sequence number is copied from the incoming frame. Frame Control Field (FCF) Data Sequence Number 2 1 Frame Check Sequence (FCS) 2 MAC Header (MHR) MAC Footer (MFR) Frame Length Start of Frame Delimiter (SFD) Bytes: 1 1 Preamble Sequence 4 Synchronisation Header (SHR) PHY Header (PHR) Figure 44: Acknowledge frame format [1] Two command strobes, SACK and SACKPEND are defined to transmit acknowledge frames with the frame pending field cleared or set, respectively. The acknowledge frame is only transmitted if the CRC is valid. For systems using beacons, there is an additional timing requirement that the acknowledge frame transmission may be started on the first backoff-slot boundary (20 symbol periods) at least 12 symbol periods after the last symbol of the incoming frame. When the RF register control bit MDMCTRL1H.SLOTTED_ACK is set to 1, the acknowledge frame is transmitted between 12 and 30 symbol periods after the incoming frame. The timing is defined such that there is an integer number of 20-symbol period backoff-slots between the incoming packet SFD and the transmitted acknowledge frame SFD. This timing is also illustrated in Figure 45. Using SACKPEND will set the pending data flag for automatically transmitted acknowledge frames using AUTOACK. The pending flag will then be set also for future acknowledge frames, until a SACK command strobe is issued. The pending data flag that is transmitted will be logically OR’ed with the value of FSMTC1.PENDING_OR. Thus the pending flag can be set high using this register control bit. When an acknowledge frame transmission completes, the RF Interrupt flag RFIF.IRQ_TXDONE will be set if this interrupt source is selected by setting RF register bit IRQSRC.TXACK to 1. Acknowledge frames may be manually transmitted using normal data transmission if desired. Not Recommended for New Designs CC2430 Radio : Radio control state machine CC2430 Data Sheet (rev. 2.1) SWRS036F Page 166 of 211 PPDU Acknowledge PPDU Acknowledge tack = 12 symbol periods tack = 12 - 30 symbol periods tbackoffslot = 20 symbol periods Last PPDU symbol Last PPDU symbol SLOTTED_ACK = 0 SLOTTED_ACK = 1 Figure 45: Acknowledge frame timing 14.20 Radio control state machine CC2430 has a built-in state machine that is used to switch between different operation states (modes). The change of state is done either by using command strobes or by internal events such as SFD detected in receive mode. The radio control state machine states are shown in Figure 46. The numbers in brackets refer to the state number readable in the FSMSTATE status register. Reading the FSMSTATE status register is primarily for test / debug purposes. The figure assumes that the device is already placed in the PM0 power mode. Before using the radio in either RX or TX mode, the voltage regulator and crystal oscillator must be turned on and become stable. The voltage regulator and crystal oscillator startup times are given in the section 7.4 on page 14. The voltage regulator for the radio is enabled by setting the RF register bit RFPWR.RREG_RADIO_PD to 0. The interrupt flag RFIF.IRQ_RREG_ON is set to 1 when the voltage regulator has powered-up. The crystal oscillator is controlled through the Power Management Controller. The SLEEP.XOSC_STB bit indicates whether the oscillator is running and stable or not (see page 67). This SFR register can be polled when waiting for the oscillator to start. It should be noted that an additional wait time after this event until selecting XOSC as source is needed. This is described in section 13.1.4.2. For test purposes, the frequency synthesizer (FS) can also be manually calibrated and started by using the STXCALN or ISTXCALN command strobe (see section 14.34 and Table 47). This will not start a transmission before a STXON command strobe is issued. This is not shown in Figure 46. Enabling transmission is done by issuing a STXON or STXONCCA command strobe. Turning off RF can be accomplished by using the SRFOFF command strobe. After bringing the CC2430 up to Power Mode 0 (PM0) from a low-power mode e.g. Power Mode 3 (PM3), all RF registers will retain their values thus placing the chip ready to operate at the correct frequency and mode. Due to the very fast start-up time, CC2430 can remain in a low-power mode until a transmission session is requested. Not Recommended for New Designs CC2430 Radio : Radio control state machine CC2430 Data Sheet (rev. 2.1) SWRS036F Page 167 of 211 Frame received and FSMTC1.RX2RX_TIME_OFF = 0 Figure 46: Radio control states Not Recommended for New Designs CC2430 Radio : MAC Security Operations (Encryption and Authentication) CC2430 Data Sheet (rev. 2.1) SWRS036F Page 168 of 211 14.21 MAC Security Operations (Encryption and Authentication) CC2430 features hardware IEEE 802.15.4 MAC security operations. Refer to section 13.12 on page 136 for a description of the AES encryption unit. 14.22 Linear IF and AGC Settings C2430 is based on a linear IF chain where the signal amplification is done in an analog VGA (variable gain amplifier). The gain of the VGA is digitally controlled. The AGC (Automatic Gain Control) loop ensures that the ADC operates inside its dynamic range by using an analog/digital feedback loop. The AGC characteristics are set through the AGCCTRLL:AGCCTRLH, registers. The reset values should be used for all AGC control registers. 14.23 RSSI / Energy Detection CC2430 has a built-in RSSI (Received Signal Strength Indicator) giving a digital value that can be read from the 8 bit, signed 2’s complement RSSIL.RSSI_VAL register bits. The RSSI value is always averaged over 8 symbol periods (128 μs), in accordance with [1]. The RSSI register value RSSI.RSSI_VAL can be referred to the power P at the RF pins by using the following equations: P = RSSI_VAL + RSSI_OFFSET [dBm] where the RSSI_OFFSET is found empirically during system development from the front end gain. RSSI_OFFSET is approximately –45. E.g. if reading a value of –20 from the RSSI register, the RF input power is approximately – 65 dBm. A typical plot of the RSSI_VAL reading as function of input power is shown in Figure 47. It can be seen from the figure that the RSSI reading from CC2430 is very linear and has a dynamic range of about 100 dB. -60 -40 -20 0 20 40 60 -100 -80 -60 -40 -20 0 RF Level [dBm] RSSI Register Value Figure 47: Typical RSSI value vs. input power 14.24 Link Quality Indication The link quality indication (LQI) measurement is a characterization of the strength and/or quality of a received packet, as defined by [1]. The RSSI value described in the previous section may be used by the MAC software to produce the LQI value. The LQI value is required by [1] to be limited to the range 0 through 255, with at least eight unique values. Software is responsible for generating the appropriate scaling of the LQI value for the given application. Using the RSSI value directly to calculate the LQI value has the disadvantage that e.g. a narrowband interferer inside the channel bandwidth will increase the LQI value although it actually reduces the true link quality. CC2430 Not Recommended for New Designs CC2430 Radio : Clear Channel Assessment CC2430 Data Sheet (rev. 2.1) SWRS036F Page 169 of 211 therefore also provides an average correlation value for each incoming packet, based on the eight first symbols following the SFD. This unsigned 7-bit value, which should be as high as possible, can be looked upon as a indication of the “chip error rate,” although CC2430 does not perform chip decision. As described in the Frame check sequence section on page 162, the average correlation value for the eight first symbols is appended to each received frame together with the RSSI and CRC OK/not OK when MDMCTRL0L.AUTOCRC is set. A correlation value of approx. 110 indicates a maximum quality frame while a value of approx. 50 is typically the lowest quality frames detectable by CC2430. Software must convert the correlation value to the range 0-255 defined by [1], e.g. by calculating: LQI = (CORR – a) · b limited to the range 0-255, where a and b are found empirically based on PER measurements as a function of the correlation value. A combination of RSSI and correlation values may also be used to generate the LQI value. 14.25 Clear Channel Assessment The clear channel assessment signal is based on the measured RSSI value and a programmable threshold. The clear channel assessment function is used to implement the CSMA-CA functionality specified in [1]. CCA is valid when the receiver has been enabled for at least 8 symbol periods. Carrier sense threshold level is programmed by RSSI.CCA_THR. The threshold value can be programmed in steps of 1 dB. A CCA hysteresis can also be programmed in the MDMCTRL0H.CCA_HYST control bits. All three CCA modes specified by [1] are implemented in CC2430. These are set in MDMCTRL0L.CCA_MODE, as can be seen in the register description. The different modes are: 00 Reserved 01 Clear channel when received energy is below threshold. 10 Clear channel when not receiving valid IEEE 802.15.4 data. 11 Clear channel when energy is below threshold and not receiving valid IEEE 802.15.4 data Clear channel assessment is available on the RFSTATUS.CCA RF register bit. RFSTATUS.CCA is active high. This register bit will also set the interrupt flag RFIF.IRQ_CCA. Implementing CSMA-CA may easiest be done by using the STXONCCA command strobe given by the CSMA-CA/strobe processor, as shown in the Radio control state machine section on page 166. Transmission will then only start if the channel is clear. The TX_ACTIVE status bit in the RFSTATUS RF register may be used to detect the result of the CCA. 14.26 Frequency and Channel Programming The operating frequency is set by programming the 10 bit frequency word located in FSCTRLH.FREQ[9:8] and FSCTRLL.FREQ[7:0]. The operating frequency FC in MHz is given by: FC = 2048 + FREQ[9:0] MHz where FREQ[9:0] is the value given by FSCTRLH.FREQ[9:8]:FSCTRLL.FREQ[7:0] In receive mode the actual LO frequency is FC – 2 MHz, since a 2 MHz IF is used. Direct conversion is used for transmission, so here the LO frequency equals FC. The 2 MHz IF is automatically set by CC2430, so the frequency programming is equal for RX and TX. IEEE 802.15.4 specifies 16 channels within the 2.4 GHz band, numbered 11 through 26. The RF frequency of channel k is given by [1] : FC = 2405 + 5 (k-11) MHz, k=11, 12, ..., 26 For operation in channel k, the FSCTRLH.FREQ:FSCTRLL.FREQ register should therefore be set to: FSCTRLH.FREQ:FSCTRLL.FREQ = 357 + 5 (k-11) 14.27 VCO and PLL Self-Calibration Not Recommended for New Designs CC2430 Radio : Output Power Programming CC2430 Data Sheet (rev. 2.1) SWRS036F Page 170 of 211 14.27.1 VCO The VCO is completely integrated and operates at 4800 – 4966 MHz. The VCO frequency is divided by 2 to generate frequencies in the desired band (2400-2483.5 MHz). 14.27.2 PLL self-calibration The VCO's characteristics will vary with temperature, changes in supply voltages, and the desired operating frequency. In order to ensure reliable operation the VCO’s bias current and tuning range are automatically calibrated every time the RX mode or TX mode is enabled, i.e. in the RX_CALIBRATE, TX_CALIBRATE and TX_ACK_CALIBRATE control states in Figure 46 on page 167. 14.28 Output Power Programming The RF output power of the device is programmable and is controlled by the TXCTRLL RF register. Table 45 shows the output power for different settings, including the complete programming of the TXCTRLL register and the current consumption in the whole device. For optimum link quality it is recommended to set TXCTRLL to 0x5F. Table 45: Output power settings Output Power [dBm] TXCTRLL register value Device current consumption [mA] 0.6 0xFF 32.4 0.5 0xDF 31.3 0.3 0xBF 30.3 0.2 0x9F 29.2 -0.1 0x7F 28.1 -0.4 0x5F 26.9 -0.9 0x3F 25.7 -1.5 0x1F 24.5 -2.7 0x1B 23.6 -4.0 0x17 22.8 -5.7 0x13 21.9 -7.9 0x0F 21.0 -10.8 0x0B 20.1 -15.4 0x07 19.2 -18.6 0x06 18.8 -25.2 0x03 18.3 14.29 Input / Output Matching The RF input / output is differential (RF_N and RF_P). In addition there is supply switch output pin (TXRX_SWITCH) that must have an external DC path to RF_N and RF_P. In RX mode the TXRX_SWITCH pin is at ground and will bias the LNA. In TX mode the TXRX_SWITCH pin is at supply rail voltage and will properly bias the internal PA. The RF output and DC bias can be done using different topologies. Some are shown in Figure 6 on page 28. Component values are given in Table 23 on page 29. If a differential antenna is implemented, no balun is required. If a single ended output is required (for a single ended connector or a single ended antenna), a balun should be used for optimum performance. Not Recommended for New Designs CC2430 Radio : Transmitter Test Modes CC2430 Data Sheet (rev. 2.1) SWRS036F Page 171 of 211 14.30 Transmitter Test Modes CC2430 can be set into different transmit test modes for performance evaluation. The test mode descriptions in the following sections requires that the chip is first reset, the crystal oscillator is selected using the CLKCON register and that the crystal oscillator has stabilized. 14.30.1 Unmodulated carrier An unmodulated carrier may be transmitted by setting MDMCTRL1L.TX_MODE to 2, writing 0x1800 to the DACTSTH:DACTSTL registers and issue a STXON command strobe. The transmitter is then enabled while the transmitter I/Q DACs are overridden to static values. An un-modulated carrier will then be available on the RF output pins. A plot of the single carrier output spectrum from CC2430 is shown in Figure 48 below. Figure 48: Single carrier output 14.30.2 Modulated spectrum The CC2430 has a built-in test pattern generator that can generate a pseudo random sequence using the CRC generator. This is enabled by setting MDMCTRL1L.TX_MODE to 3 and issuing a STXON command strobe. The modulated spectrum is then available on the RF pins. The low byte of the CRC word is transmitted and the CRC is updated with 0xFF for each new byte. The length of the transmitted data sequence is 65535 bits. The transmitted data-sequence is then: [synchronization header] [0x00, 0x78, 0xb8, 0x4b, 0x99, 0xc3, 0xe9, …] Since a synchronization header (preamble and SFD) is transmitted in all TX modes, this test mode may also be used to transmit a known Not Recommended for New Designs CC2430 Radio : Transmitter Test Modes CC2430 Data Sheet (rev. 2.1) SWRS036F Page 172 of 211 pseudorandom bit sequence for bit error testing. Please note that CC2430 requires symbol synchronization, not only bit synchronization, for correct reception. Packet error rate is therefore a better measurement for the true RF performance. Another option to generate a modulated spectrum is to fill the TXFIFO with pseudorandom data and set MDMCTRL1L.TX_MODE to 2. CC2430 will then transmit data from the FIFO disregarding a TXFIFO underflow. The length of the transmitted data sequence is then 1024 bits (128 bytes). A plot of the modulated spectrum from CC2430 is shown in Figure 49. Note that to find the output power from the modulated spectrum, the RBW must be set to 3 MHz or higher. Figure 49: Modulated spectrum plot Not Recommended for New Designs CC2430 Radio : System Considerations and Guidelines CC2430 Data Sheet (rev. 2.1) SWRS036F Page 173 of 211 14.31 System Considerations and Guidelines 14.31.1 SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for license free operation are allowed to operate in the 2.4 GHz band worldwide. The most important regulations are ETSI EN 300 328 and EN 300 440 (Europe), FCC CFR-47 part 15.247 and 15.249 (USA), and ARIB STD-T66 (Japan). 14.31.2 Frequency hopping and multi-channel systems The 2.4 GHz band is shared by many systems both in industrial, office and home environments. CC2430 uses direct sequence spread spectrum (DSSS) as defined by [1] to spread the output power, thereby making the communication link more robust even in a noisy environment. With CC2430 it is also possible to combine both DSSS and FHSS (frequency hopping spread spectrum) in a proprietary non-IEEE 802.15.4 system. This is achieved by reprogramming the operating frequency (see the Frequency and Channel Programming section on page 169) before enabling RX or TX. A frequency synchronization scheme must then be implemented within the proprietary MAC layer to make the transmitter and receiver operate on the same RF channel. 14.31.3 Data burst transmissions The data buffering in CC2430 lets the user have a lower data rate link between the CPU and the radio module than the RF bit rate of 250 kbps. This allows the CPU to buffer data at its own speed, reducing the workload and timing requirements. DMA transfers may be used to efficiently move data to and from the radio FIFOs. The relatively high data rate of CC2430 also reduces the average power consumption compared to the 868 / 915 MHz bands defined by [1], where only 20 / 40 kbps are available. CC2430 may be powered up a smaller portion of the time, so that the average power consumption is reduced for a given amount of data to be transferred. 14.31.4 Crystal accuracy and drift A crystal accuracy of ±40 ppm is required for compliance with IEEE 802.15.4 [1]. This accuracy must also take ageing and temperature drift into consideration. A crystal with low temperature drift and low aging could be used without further compensation. A trimmer capacitor in the crystal oscillator circuit (in parallel with C191 in Figure 6) could be used to set the initial frequency accurately. For non-IEEE 802.15.4 systems, the robust demodulator in CC2430 allows up to 140 ppm total frequency offset between the transmitter and receiver. This could e.g. relax the accuracy requirement to 60 ppm for each of the devices. Optionally in a star network topology, the fullfunction device (FFD) could be equipped with a more accurate crystal thereby relaxing the requirement on the reduced-function device (RFD). This can make sense in systems where the reduced-function devices ship in higher volumes than the full-function devices. 14.31.5 Communication robustness CC2430 provides very good adjacent, alternate and co channel rejection, image frequency suppression and blocking properties. The CC2430 performance is significantly better than the requirements imposed by [1]. These are highly important parameters for reliable operation in the 2.4 GHz band, since an increasing number of devices/systems are using this license free frequency band. 14.31.6 Communication security The hardware encryption and authentication operations in CC2430 enable secure communication, which is required for many applications. Security operations require a lot Not Recommended for New Designs CC2430 Radio : System Considerations and Guidelines CC2430 Data Sheet (rev. 2.1) SWRS036F Page 174 of 211 of data processing, which is costly in an 8-bit microcontroller system. The hardware support within CC2430 enables a high level of security with minimum CPU processing requirements. 14.31.7 Low cost systems As the CC2430 provides 250 kbps multichannel performance without any external filters, a very low cost system can be made (e.g. two layer PCB with single-sided component mounting). A differential antenna will eliminate the need for a balun, and the DC biasing can be achieved in the antenna topology. 14.31.8 Battery operated systems In low power applications, the CC2430 should be placed in the low-power modes PM2 or PM3 when not being active. Ultra low power consumption may be achieved since the voltage regulators are turned off. 14.31.9 BER / PER measurements CC2430 includes test modes where data is received infinitely and output to pins. The required test modes are selected with the RF register bits MDMCTRL1L.TX_MODE[1:0] and MDMCTRL1L.RX_MODE[1:0]. These modes may be used for Bit Error Rate (BER) measurements. However, the following precautions must be taken to perform such a measurement: • A preamble and SFD sequence must be used, even if pseudo random data is transmitted, since receiving the DSSS modulated signal requires symbol synchronization, not bit synchronization like e.g. in 2FSK systems. The SYNCWORDH:SYNCWORDL may be set to another value to fit to the measurement setup if necessary. • The data transmitted over air must be spread according to [1] and the description on page 154. This means that the transmitter used during measurements must be able to do spreading of the bit data to chip data. Remember that the chip sequence transmitted by the test setup is not the same as the bit sequence, which is output by CC2430. • When operating at or below the sensitivity limit, CC2430 may lose symbol synchronization in infinite receive mode. A new SFD and restart of the receiver may be required to re-gain synchronization. In an IEEE 802.15.4 system, all communication is based on packets. The sensitivity limit specified by [1] is based on Packet Error Rate (PER) measurements instead of BER. This is a more realistic measurement of the true RF performance since it mirrors the way the actual system operates. It is recommended to perform PER measurements instead of BER measurements to evaluate the performance of IEEE 802.15.4 systems. To do PER measurements, the following may be used as a guideline: • A valid preamble, SFD and length field must be used for each packet. • The PSDU (see Figure 39 on page 161) length should be 20 bytes for sensitivity measurements as specified by [1]. • The sensitivity limit specified by [1] is the RF level resulting in a 1% PER. The packet sample space for a given measurement must then be >> 100 to have a sufficiently large sample space. E.g. at least 1000 packets should be used to measure the sensitivity. • The data transmitted over air must be spread according to [1] and the description on page 154. Pre-generated packets may be used, although [1] requires that the PER is averaged over random PSDU data. • The CC2430 receive FIFO may be used to buffer data received during PER measurements, since it is able to buffer up to 128 bytes. • The MDMCTRL1H.CORR_THR control register should be set to 20, as described in the Demodulator, Symbol Synchronizer and Data Decision section. The simplest way of making a PER measurement will be to use another CC2430 as the reference transmitter. However, this makes it difficult to measure the exact receiver performance. Using a signal generator, this may either be set up as O-QPSK with half-sine shaping or as MSK. If using O-QPSK, the phases must be selected according to [1]. If using MSK, the Not Recommended for New Designs CC2430 Radio : PCB Layout Recommendation CC2430 Data Sheet (rev. 2.1) SWRS036F Page 175 of 211 chip sequence must be modified such that the modulated MSK signal has the same phase shifts as the O-QPSK sequence previously defined. For a desired symbol sequence s0, s1, … , sn-1 of length n symbols, the desired chip sequence c0, c1, c2, …, c32n-1 of length 32n is found using table lookup from Table 44 on page 154. It can be seen from comparing the phase shifts of the O-QPSK signal with the frequency of a MSK signal that the MSK chip sequence is generated as: (c0 xnor c1), (c1 xor c2), (c2 xnor c3), … , (c32n-1 xor c32n) where c32n may be arbitrarily selected. 14.32 PCB Layout Recommendation In the Texas Instruments reference design, the top layer is used for signal routing, and the open areas are filled with metallization connected to ground using several vias. The area under the chip is used for grounding and must be well connected to the ground plane with several vias. The ground pins should be connected to ground as close as possible to the package pin using individual vias. The de-coupling capacitors should also be placed as close as possible to the supply pins and connected to the ground plane by separate vias. Supply power filtering is very important. The external components should be as small as possible (0402 is recommended) and surface mount devices must be used. If using any external high-speed digital devices, caution should be used when placing these in order to avoid interference with the RF circuitry. A Development Kit, CC2430DK, with a fully assembled Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to obtain the best performance. The schematic, BOM and layout Gerber files for the reference designs are all available from the TI website. 14.33 Antenna Considerations CC2430 can be used together with various types of antennas. A differential antenna like a dipole would be the easiest to interface not needing a balun (balanced to un-balanced transformation network). The length of the λ/2-dipole antenna is given by: L = 14250 / f where f is in MHz, giving the length in cm. An antenna for 2450 MHz should be 5.8 cm. Each arm is therefore 2.9 cm. Other commonly used antennas for shortrange communication are monopole, helical and loop antennas. The single-ended monopole and helical would require a balun network between the differential output and the antenna. Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical wavelength (λ/4). They are very easy to design and can be implemented simply as a “piece of wire” or even integrated into the PCB. The length of the λ/4-monopole antenna is given by: L = 7125 / f where f is in MHz, giving the length in cm. An antenna for 2450 MHz should be 2.9 cm. Non-resonant monopole antennas shorter than λ/4 can also be used, but at the expense of range. In size and cost critical applications such an antenna may very well be integrated into the PCB. Enclosing the antenna in high dielectric constant material reduces the overall size of the antenna. Many vendors offer such antennas intended for PCB mounting. Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications. Helical antennas tend to be more difficult to optimize than the simple monopole. Loop antennas are easy to integrate into the PCB, but are less effective due to difficult impedance matching because of their very low radiation resistance. For low power applications the differential antenna is recommended giving the best range and because of its simplicity. Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 176 of 211 The antenna should be connected as close as possible to the IC. If the antenna is located away from the RF pins the antenna should be matched to the feeding transmission line (50Ω). 14.34 CSMA/CA Strobe Processor The Command Strobe/CSMA-CA Processor (CSP) provides the control interface between the CPU and the Radio module in the CC2430. The CSP interfaces with the CPU through the SFR register RFST and the RF registers CSPX, CSPY, CSPZ, CSPT and CSPCTRL. The CSP produces interrupt requests to the CPU. In addition the CSP interfaces with the MAC Timer by observing MAC Timer overflow events. The CSP allows the CPU to issue command strobes to the radio thus controlling the operation of the radio. The CSP has two modes of operation as follows, which are described below. • Immediate Command Strobe execution. • Program execution Immediate Command Strobes are written as an Immediate Command Strobe instruction to the CSP which are issued instantly to the Radio module. The Immediate Command Strobe instruction is also used only to control the CSP. The Immediate Command Strobe instructions are described in section 14.34.7. Program execution mode means that the CSP executes a sequence of instructions, from a program memory or instruction memory, thus constituting a short user-defined program. The available instructions are from a set of 14 instructions. The instruction set is defined in section 14.34.8. The required program is first loaded into the CSP by the CPU, and then the CPU instructs the CSP to start executing the program. The program execution mode together with the MAC Timer allows the CSP to automate CSMA-CA algorithms and thus act as a coprocessor for the CPU. The operation of the CSP is described in detail in the following sections. The command strobes and other instructions supported by the CSP are given in section 14.34.8 on page 179. RFST (0xE1) – RF CSMA-CA/Strobe Processor Bit Name Reset R/W Description 7:0 INSTR[7:0] 0xC0 R/W Data written to this register will be written to the CSP instruction memory. Reading this register will return the CSP instruction currently being executed. 14.34.1 Instruction Memory The CSP executes single byte program instructions which are read from a 24 byte instruction memory. The instruction memory is written to sequentially through the SFR register RFST. An instruction write pointer is maintained within the CSP to hold the location within the instruction memory where the next instruction written to RFST will be stored. Following a reset the write pointer is reset to location 0. During each RFST register write, the write pointer will be incremented by 1 until the end of memory is reached when the write pointer will stop incrementing, thus writing more than 24 bytes only the last byte written will be stored in the last position. The first instruction written to RFST will be stored in location 0, the location where program execution starts. Thus a complete CSP program may contain a maximum of 24 bytes that is written to the instruction memory by writing each instruction in the desired order to the RFST register. Note that the program memory does not need to be filled, thus a CSP program may contain less than 24 bytes. The write pointer may be reset to 0 by writing the immediate command strobe instruction ISSTOP. In addition the write pointer will be reset to 0 when the command strobe SSTOP is executed in a program. Following a reset, the instruction memory is filled with SNOP (No Operation) instructions (opcode value 0xC0). While the CSP is executing a program, there shall be no attempts to write instructions to the instruction memory by writing to RFST. Failure to observe this rule can lead to incorrect program execution and corrupt instruction memory contents. However, Immediate Command Strobe instructions may be written to RFST (see section 14.34.3). Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 177 of 211 14.34.2 Data Registers The CSP has three data registers CSPT, CSPX, CSPY and CSPZ, which are read/write accessible for the CPU as RF registers. These registers are read or modified by some instructions, thus allowing the CPU to set parameters to be used by a CSP program or allowing the CPU to read CSP program status. The CSPT data register is not modified by any instruction. The CSPT data register is used to set a MAC Timer overflow compare value. Once program execution has started on the CSP, the content of this register is decremented by 1 each time the MAC timer overflows. When CSPT reaches zero, program execution is halted and the interrupt IRQ_CSP_STOP is asserted. The CSPT register will not be decremented if the CPU writes 0xFF to this register. Note: If the CSPT register compare function is not used, this register must be set to 0xFF before the program execution is started. 14.34.3 Program Execution After the instruction memory has been filled, program execution is started by writing the immediate command strobe instruction ISSTART to the RFST register. The program execution will continue until either the instruction at last location has been executed, the CSPT data register contents is zero, a SSTOP instruction has been executed, an immediate ISSTOP instruction is written to RFST or until a SKIP instruction returns a location beyond the last location in the instruction memory. The CSP runs at 8 MHz clock frequency. Immediate Command Strobe instructions may be written to RFST while a program is being executed. In this case the Immediate instruction will bypass the instruction in the instruction memory, which will be completed once the Immediate instruction has been completed. During program execution, reading RFST will return the current instruction being executed. An exception to this is the execution of immediate command strobes, during which RFST will return C0h. 14.34.4 Interrupt Requests The CSP has three interrupts flags which can produce the RF interrupt vector. These are the following: • IRQ_CSP_STOP: asserted when the processor has executed the last instruction in memory and when the processor stops due to a SSTOP or ISSTOP instruction or CSPT register equal zero. • IRQ_CSP_WT: asserted when the processor continues executing the next instruction after a WAIT W or WAITX instruction. • IRQ_CSP_INT: asserted when the processor executes an INT instruction. 14.34.5 Random Number Instruction There will be a delay in the update of the random number used by the RANDXY instruction. Therefore if an instruction, RANDXY, that uses this value is issued immediately after a previous RANDXY instruction, the random value read may be the same in both cases. 14.34.6 Running CSP Programs The basic flow for loading and running a program on the CSP is shown in Figure 50. When program execution stops due to end of program the current program remains in program memory. This makes it possible to run the same program again by starting execution with the ISSTART command. However, when program execution is stopped by the SSTOP or ISTOP instruction, the program memory will be cleared. It is also importat to note that a WAIT W or WEVENT instruction can not be executed between X register update and X data read by one of the following instructions: RPT, SKIP or WAITX. If this is done the CSPX register will be decremented on each MAC timer (Timer2) overflow occurrence. Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 178 of 211 Write instruction to RFST All instructions written? Setup CSPT, CSPX, CSPY, CSPZ and CSPCTRL registers Start execution by writing ISSTART to RFST yes no SSTOP instruction, end of program or writing ISTOP to RFST stops program Figure 50: Running a CSP program 14.34.7 Instruction Set Summary This section gives an overview of the instruction set. This is intended as a summary and definition of instruction opcodes. Refer to section 14.34.8 for a description of each instruction. Each instruction consists of one byte which is written to the RFST register to be stored in the instruction memory. The Immediate Strobe instructions (ISxxx) are not used in a program. When these instructions are written to the RFST register, they are executed immediately. If the CSP is already executing a program the current instruction will be delayed until the Immediate Strobe instruction has completed. For undefined opcodes, the behavior of the CSP is defined as a No Operation Strobe Command (SNOP). Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 179 of 211 Table 46: Instruction Set Summary Opcode Bit number Mnemonic 7 6 5 4 3 2 1 0 Description11 SKIP C,S 0 S N C Skip S instructions when condition (C xor N) is true. See Table 48 for C conditional codes WAIT W 1 0 0 W Wait for W number of MAC Timer overflows. If W is zero, wait for 32 MAC Timer overflows WEVENT 1 0 1 1 1 0 0 0 Wait until MAC Timer value is greater than or equal to compare value in T2CMP WAITX 1 0 1 1 1 0 1 1 Wait for CSPX number of backoffs. When CSPX is zero there is no wait. LABEL 1 0 1 1 1 0 1 0 Label next instruction as loop start RPT 1 0 1 0 N C Repeat from start of loop if condition (C xor N) is true. See Table 48 for C conditional codes INT 1 0 1 1 1 0 0 1 Assert interrupt INCY 1 0 1 1 1 1 0 1 Increment CSPY INCMAXY 1 0 1 1 0 M Increment CSPY not greater than M DECY 1 0 1 1 1 1 1 0 Decrement CSPY DECZ 1 0 1 1 1 1 1 1 Decrement CSPZ RANDXY 1 0 1 1 1 1 0 0 Load CSPX with CSPY bit random value. Sxxx 1 1 0 STRB Command strobe instructions ISxxx 1 1 1 STRB Immediate strobe instructions 11 Refer to Table 47 for full description of each instruction 14.34.8 Instruction Set Definition There are 14 basic instruction types. Furthermore the Command Strobe and Immediate Strobe instructions can each be divided into eleven sub-instructions giving an effective number of 34 different instructions. Table 47 describe each instruction. Note: the following definitions are used in this section PC = CSP program counter X = RF register CSPX Y = RF register CSPY Z = RF register CSPZ T = RF register CSPT ! = not > = greater than < = less than | = bit wise or Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 180 of 211 Table 47: CSMA/CA strobe processor instruction details NMONIC OPCODE Function Operation Description DECZ 0xBF Decrement Z Z := Z - 1 The Z register is decremented by 1. Original values of 0x00 will underflow to 0x0FF. DECY 0xBE Decrement Y Y := Y - 1 The Y register is decremented by 1. Original values of 0x00 will underflow to 0x0FF. INCY 0xBD Increment Y Y := Y + 1 The Y register is incremented by 1. An original value of 0x0FF will overflow to 0x00. INCMAXY 0xB0|M12 Increment Y !> M Y := min(Y+1, M) The Y register is incremented by 1 if the result is less than M otherwise Y register is loaded with value M. An original value of Y equal 0x0FF will result in the value M. RANDXY 0xBC Load random data into X X[Y-1:0] := RNG_DOUT[Y-1:0], X[7:Y] := 0 The [Y] LSB bits of X register are loaded with random value. Note that if two RANDXY instructions are issued immediately after each other the same random value will be used in both cases. If Y equals 0 or if Y is greater than 8, then 8 LSB bits are loaded. INT 0xB9 Interrupt IRQ_CSP_INT = 1 The interrupt IRQ_CSP_INT is asserted when this instruction is executed. WAITX 0xBB Wait for X MAC Timer overflows X := X-1 when MAC timer overflow true PC := PC while number of MAC timer compare true < X PC := PC + 1 when number of MAC timer compare true = X Wait until MAC Timer overflows the numbers of times equal to register X. The contents of register X is decremented each time a MAC Timer overflow is detected. Program execution continues with the next instruction and the interrupt flag IRQ_CSP_WT is asserted when the wait condition is true. If register X is zero when this instruction starts executing, there is no wait. WAIT W 0x80|W12 Wait for W MAC Timer overflows PC := PC while number of MAC timer compare true < W PC := PC + 1 when number of MAC timer compare true = W Wait until MAC Timer overflows number of times equal to value W. If W=0 the instruction will wait for 32 overflows. Program execution continues with the next instruction and the interrupt flag IRQ_CSP_WT is asserted when the wait condition is true. WEVENT 0xB8 Wait until MAC Timer compare PC := PC while MAC timer compare false PC := PC + 1 when MAC timer compare true Wait MAC Timer value is greater than or equal to the compare value in T2CMP. Program execution continues with the next instruction when the wait condition is true. LABEL 0xBA Set loop label LABEL:= PC+1 Sets next instruction as start of loop. If the current instruction is the last instruction in the instruction memory then the current PC is set as start of loop. Only one level of loops is supported. RPT C 0xA0|N|C12 Conditional repeat PC := LABEL when (C xor N) true PC := PC + 1 when (C xor N) false or LABEL not set If condition C is true then jump to instruction defined by last LABEL instruction, i.e. jump to start of loop. If the condition is false or if a LABEL instruction has not been executed, then execution will continue from next instruction. The condition C may be negated by setting N=1 and is described in Table 48. SKIP S,C 0x00|S|N|C12 Conditional skip instruction PC := PC + S + 1 when (C xor N) true else PC := PC + 1 If condition C is true then skip S instructions. The condition C may be negated (N=1) and is described in Table 48 (note same conditions as RPT C instruction). Setting S=0, will cause a wait at current instruction until (C xor N) = true 12 Refer to Table 46 for OPCODE Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 181 of 211 NMONIC OPCODE Function Operation Description STOP 0xDF Stop program execution Stop exec, PC:=0, write pointer:=0 The SSTOP instruction stops the CSP program execution. The instruction memory is cleared, any loop start location set by the LABEL instruction is invalidated and the IRQ_CSP_STOP interrupt flag is asserted. SNOP 0xC0 No Operation PC := PC + 1 Operation continues at the next instruction. STXCALN 0xC1 Enable and calibrate freq. synth. for TX STCALN The STXCALN instruction enables and calibrate frequency synthesizer for TX. The instruction waits for the radio to acknowledge the command before executing the next instruction. NOTE: Only for test purposes (see section 14.20). SRXON 0xC2 Enable and calibrate freq. synth. for RX SRXON The SRXON instruction asserts the output FFCTL_SRXON_STRB to enable and calibrate frequency synthesizer for RX. The instruction waits for the radio to acknowledge the command before executing the next instruction. STXON 0xC3 Enable TX after calibration STXON The STXON instruction enables TX after calibration. The instruction waits for the radio to acknowledge the command before executing the next instruction. STXONCCA 0xC4 Enable calibration and TX if CCA indicated a clear channel STXONCCA STXONCCA instruction enables TX after calibration if CCA indicates a clear channel. The instruction waits for the radio to acknowledge the command before executing the next instruction. Note that this strobe should only be used when FSMTC1.RX2RX_TIME_OFF is set to 1, if not time from strobe until transmit may not be 192 μs. SROFF 0xC5 Disable RX/TX and freq. synth. SRFOFF The SRFOFF instruction asserts disables RX/TX and the frequency synthesizer. The instruction waits for the radio to acknowledge the command before executing the next instruction. SFLUSHRX 0xC6 Flush RXFIFO buffer and reset demodulator SFLUSHRX The SFLUSHRX instruction flushes the RXFIFO buffer and resets the demodulator. The instruction waits for the radio to acknowledge the command before executing the next instruction. SFLUSHTX 0xC7 Flush TXFIFO buffer SFLUSHTX The SFLUSHTX instruction flushes the TXFIFO buffer. The instruction waits for the radio to acknowledge the command before executing the next instruction. SACK 0xC8 Send acknowledge frame with pending field cleared SACK The SACK instruction sends an acknowledge frame. The instruction waits for the radio to acknowledge the command before executing the next instruction. SACPEND 0xC9 Send acknowledge frame when pending field set SACKPEND The SACKPEND instruction sends an acknowledge frame with pending field set. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISSTOP 0xFF Stop program execution Stop execution ISSTOP instruction stops the CSP program execution. The instruction memory is cleared, any loop start location set be the LABEL instruction is invalidated and the IRQ_CSP_STOP interrupt flag is asserted. ISSTART 0xFE Start program execution PC := 0, start execution The ISSTART instruction starts the CSP program execution from first instruction written to instruction memory. ISTXCALN 0xE1 Enable and calibrate freq. synth. for TX STXCALN ISTXCALN instruction immediately enables and calibrates frequency synthesizer for TX. The instruction waits for the radio to acknowledge the command before executing the next instruction. Not Recommended for New Designs CC2430 Radio : CSMA/CA Strobe Processor CC2430 Data Sheet (rev. 2.1) SWRS036F Page 182 of 211 NMONIC OPCODE Function Operation Description ISRXON 0xE2 Enable and calibrate freq. synth. for RX SRXON The ISRXON instruction immediately enables and calibrates frequency synthesizer for RX. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISTXON 0xE3 Enable TX after calibration STXON_STRB The ISTXON instruction immediately enables TX after calibration. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISTXONCCA 0xE4 Enable calibration and TX if CCA indicates a clear channel STXONCCA The ISTXONCCA instruction immediately enables TX after calibration if CCA indicates a clear channel. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISRFOFF 0xE5 Disable RX/TX and freq. synth. FFCTL_SRFOFF_STRB = 1 The ISRFOFF instruction immediately disables RX/TX and frequency synthesizer. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISFLUSHRX 0xE6 Flush RXFIFO buffer and reset demodulator SFLUSHRX ISFLUSHRX instruction flushes the RXFIFO buffer and resets the demodulator. The instruction waits for the radio to acknowledge the command before executing the next instruction. Note that for compete flush the command must be run twice. ISFLUSHTX 0xE7 Flush TXFIFO buffer SFLUSHTX ISFLUSHTX instruction immediately flushes the TXFIFO buffer. The instruction waits for the radio to acknowledge the command before executing the next instruction. ISACK 0xE8 Send acknowledge frame with pending field cleared SACK The ISACK instruction immediately sends an acknowledge frame. The instruction waits for the radio to receive and interpret the command before executing the next instruction. ISACKPEND 0xE9 Send acknowledge frame when pending field set SACPEND The ISACKPEND instruction immediately sends an acknowledge frame with pending field set. The instruction waits for the radio to receive and interpret the command before executing the next instruction. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 183 of 211 Table 48: Condition code for C Condition code C Description Function 000 CCA is true CCA = 1 001 Transmiting or Receiving packet SFD = 1 010 CPU control true CSPCTRL.CPU_CTRL=1 011 End of instruction memory PC = 23 100 Register X=0 X = 0 101 Register Y=0 Y = 0 110 Register Z=0 Z = 0 111 Not used - 14.35 Radio Registers This section describes all RF registers used for control and status for the radio. The RF registers reside in XDATA memory space. Table 49 gives an overview of register addresses while the remaining tables in this section describe each register. Refer also to section 3 for Register conventions. Table 49 : Overview of RF registers XDATA Address Register name Description 0xDF00- 0xDF01 - Reserved 0xDF02 MDMCTRL0H Modem Control 0, high 0xDF03 MDMCTRL0L Modem Control 0, low 0xDF04 MDMCTRL1H Modem Control 1, high 0xDF05 MDMCTRL1L Modem Control 1, low 0xDF06 RSSIH RSSI and CCA Status and Control, high 0xDF07 RSSIL RSSI and CCA Status and Control, low 0xDF08 SYNCWORDH Synchronisation Word Control, high 0xDF09 SYNCWORDL Synchronisation Word Control, low 0xDF0A TXCTRLH Transmit Control, high 0xDF0B TXCTRLL Transmit Control, low 0xDF0C RXCTRL0H Receive Control 0, high 0xDF0D RXCTRL0L Receive Control 0, low 0xDF0E RXCTRL1H Receive Control 1, high 0xDF0F RXCTRL1L Receive Control 1, low 0xDF10 FSCTRLH Frequency Synthesizer Control and Status, high 0xDF11 FSCTRLL Frequency Synthesizer Control and Status, low 0xDF12 CSPX CSP X Data 0xDF13 CSPY CSP Y Data 0xDF14 CSPZ CSP Z Data 0xDF15 CSPCTRL CSP Control 0xDF16 CSPT CSP T Data 0xDF17 RFPWR RF Power Control Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 184 of 211 XDATA Address Register name Description 0xDF20 FSMTCH Finite State Machine Time Constants, high 0xDF21 FSMTCL Finite State Machine Time Constants, low 0xDF22 MANANDH Manual AND Override, high 0xDF23 MANANDL Manual AND Override, low 0xDF24 MANORH Manual OR Override, high 0xDF25 MANORL Manual OR Override, low 0xDF26 AGCCTRLH AGC Control, high 0xDF27 AGCCTRLL AGC Control, low 0xDF28- 0xDF38 - Reserved 0xDF39 FSMSTATE Finite State Machine State Status 0xDF3A ADCTSTH ADC Test, high 0xDF3B ADCTSTL ADC Test, low 0xDF3C DACTSTH DAC Test, high 0xDF3D DACTSTL DAC Test, low 0xDF3E - Reserved 0xDF3F - Reserved 0xDF40 - Reserved 0xDF41 - Reserved 0xDF43 IEEE_ADDR0 IEEE Address 0 (LSB) 0xDF44 IEEE_ADDR1 IEEE Address 1 0xDF45 IEEE_ADDR2 IEEE Address 2 0xDF46 IEEE_ADDR3 IEEE Address 3 0xDF47 IEEE_ADDR4 IEEE Address 4 0xDF48 IEEE_ADDR5 IEEE Address 5 0xDF49 IEEE_ADDR6 IEEE Address 6 0xDF4A IEEE_ADDR7 IEEE Address 7 (MSB) 0xDF4B PANIDH PAN Identifier, high 0xDF4C PANIDL PAN Identifier, low 0xDF4D SHORTADDRH Short Address, high 0xDF4E SHORTADDRL Short Address, low 0xDF4F IOCFG0 I/O Configuration 0 0xDF50 IOCFG1 I/O Configuration 1 0xDF51 IOCFG2 I/O Configuration 2 0xDF52 IOCFG3 I/O Configuration 3 0xDF53 RXFIFOCNT RX FIFO Count Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 185 of 211 XDATA Address Register name Description 0xDF54 FSMTC1 Finite State Machine Control 0xDF55- 0xDF5F - Reserved 0xDF60 CHVER Chip Version 0xDF61 CHIPID Chip Identification 0xDF62 RFSTATUS RF Status 0xDF63 - Reserved 0xDF64 IRQSRC RF Interrupt Source The RF registers shown in Table 50 are reserved for test purposes. The values for these registers should be obtained from SmartRF® Studio (see section 16 on page 202) and should not be changed. Table 50 : Overview of RF test registers XDATA Address Register name Reset value 0xDF28 AGCTST0H 0x36 0xDF29 AGCTST0L 0x49 0xDF2A AGCTST1H 0x08 0xDF2B AGCTST1L 0x54 0xDF2C AGCTST2H 0x09 0xDF2D AGCTST2L 0x0A 0xDF2E FSTST0H 0x10 0xDF2F FSTST0L 0x00 0xDF30 FSTST1H 0x40 0xDF31 FSTST1L 0x32 0xDF32 FSTST2H 0x20 0xDF33 FSTST2L 0x00 0xDF34 FSTST3H 0x92 0xDF35 FSTST3L 0xDD 0xDF37 RXBPFTSTH 0x00 0xDF38 RXBPFTSTL 0x00 0xDF3F TOPTST 0x10 0xDF40 RESERVEDH 0x00 0xDF41 RESERVEDL 0x00 Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 186 of 211 MDMCTRL0H (0xDF02) Bit Name Reset R/W Function 7:6 FRAMET_FILT 00 R/W These bits are used to perform special operations on the frame type field of a received packet. These operations do not influence the packet that is written to the RXFIFO. 00 : Leave frame type as it is. 01 : Invert MSB of frame type. 10 : Set MSB of frame type to 0. 11 : Set MSB of frame type to 1. For IEEE 802.15.4 compliant operation these bits should always be set to 00. 5 RESERVED_FRAME_MODE 0 R/W Mode for accepting reserved IEEE 802.15.4 frame types when address recognition is enabled (MDMCTRL0.ADDR_DECODE = 1). 0 : Reserved frame types (100, 101, 110, 111) are rejected by address recognition. 1 : Reserved frame types (100, 101, 110, 111) are always accepted by address recognition. No further address decoding is done. When address recognition is disabled (MDMCTRL0.ADDR_DECODE = 0), all frames are received and RESERVED_FRAME_MODE is don’t care. For IEEE 802.15.4 compliant operation these bits should always be set to 00. 4 PAN_COORDINATOR 0 R/W PAN Coordinator enable. Used for filtering packets with no destination address, as specified in section 7.5.6.2 in 802.15.4 [1] 0 : Device is not a PAN Coordinator 1 : Device is a PAN Coordinator 3 ADDR_DECODE 1 R/W Hardware Address decode enable. 0 : Address decoding is disabled 1 : Address decoding is enabled 2:0 CCA_HYST[2:0] 010 R/W CCA Hysteresis in dB, values 0 through 7 dB Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 187 of 211 MDMCTRL0L (0xDF03) Bit Name Reset R/W Description 7:6 CCA_MODE[1:0] 11 R/W Clear Channel Assessment mode select. 00 : Reserved 01 : CCA=1 when RSSI < CCA_THR-CCA_HYST CCA=0 when RSSI >= CCA_THR 10 : CCA=1 when not receiving a packet 11 : CCA=1 when RSSI < CCA_THR-CCA_HYST and not receiving a packet CCA=0 when RSSI >= CCA_THR or receiving a packet 5 AUTOCRC 1 R/W In packet mode a CRC-16 (ITU-T) is calculated and is transmitted after the last data byte in TX. In RX CRC is calculated and checked for validity. 4 AUTOACK 0 R/W If AUTOACK is enabled, all packets accepted by address recognition with the acknowledge request flag set and a valid CRC are acknowledged 12 symbol periods after being received if MDMCTRL1H.SLOTTED_ACK = 0. Acknowledgment is at the beginning of the first backoff slot more than 12 symbol periods after the end of the received frame if the MDMCTRL1H.SLOTTED_ACK = 1 0 : AUTOACK disabled 1 : AUTOACK enabled 3:0 PREAMBLE_LENGTH[3:0] 0010 R/W The number of preamble bytes (2 zero-symbols) to be sent in TX mode prior to the SYNCWORD. The reset value of 0010 is compliant with IEEE 802.15.4, since the 4th zero byte is included in the SYNCWORD. 0000 : 1 leading zero bytes (not recommended) 0001 : 2 leading zero bytes (not recommended) 0010 : 3 leading zero bytes (IEEE 802.15.4 compliant) 0011 : 4 leading zero bytes … 1111 : 16 leading zero bytes MDMCTRL1H (0xDF04) Bit Name Reset R/W Description 7 SLOTTED_ACK 0 R/W SLOTTED_ACK defines the timing of automatically transmitted acknowledgment frames. 0 : The acknowledgment frame is transmitted 12 symbol periods after the incoming frame. 1 : The acknowledgment frame is transmitted between 12 and 30 symbol periods after the incoming frame. The timing is defined such that there is an integer number of 20-symbol periods between the received and the transmitted SFDs. This may be used to transmit slotted acknowledgment frames in a beacon enabled network. 6 - 0 R/W Reserved 5 CORR_THR_SFD 1 R/W CORR_THR_SFD defines the level at which the CORR_THR correlation threshold is used to filter out received frames. 0 : Same filtering as CC2420, should be combined with a CORR_THR of 0x14 1 : More extensive filtering is performed, which will result in less false frame detections e.g. caused by noise. 4:0 CORR_THR[4:0] 0x10 R/W Demodulator correlator threshold value, required before SFD search. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 188 of 211 MDMCTRL1L (0xDF05) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5 DEMOD_AVG_MODE 0 R/W DC average filter behavior. 0 : Lock DC level to be removed after preamble match 1 : Continuously update DC average level. 4 MODULATION_MODE 0 R/W Set one of two RF modulation modes for RX / TX 0 : IEEE 802.15.4 compliant mode 1 : Reversed phase, non-IEEE compliant (could be used to set up a system which will not receive 802.15.4 packets) 3:2 TX_MODE[1:0] 00 R/W Set test modes for TX 00 : Normal operation, transmit TXFIFO 01 : Serial mode, use transmit data on serial interface, infinite transmission. 10 : TXFIFO looping ignore underflow in TXFIFO and read cyclic, infinite transmission. 11 : Send random data from CRC, infinite transmission. 1:0 RX_MODE[1:0] 00 R/W Set test mode of RX 00 : Normal operation, use RXFIFO 01 : Receive serial mode, output received data on pins. Infinite RX. 10 : RXFIFO looping ignore overflow in RXFIFO and write cyclic, infinite reception. 11 : Reserved RSSIH (0xDF06) Bit Name Reset R/W Description 7:0 CCA_THR[7:0] 0xE0 R/W Clear Channel Assessment threshold value, signed number in 2’s complement for comparison with the RSSI. The unit is 1 dB, offset is TBD [depends on the absolute gain of the RX chain, including external components and should be measured]. The CCA signal goes high when the received signal is below this value. The reset value is in the range of -70 dBm. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 189 of 211 RSSIL (0xDF07) Bit Name Reset R/W Description 7:0 RSSI_VAL[7:0] 0x80 R RSSI estimate on a logarithmic scale, signed number in 2’s complement. Unit is 1 dB, offset is TBD [depends on the absolute gain of the RX chain, including external components, and should be measured]. The RSSI value is averaged over 8 symbol periods. SYNCWORDH (0xDF08) Bit Name Reset R/W Description 7:0 SYNCWORD[15:8] 0xA7 R/W Synchronization word. The SYNCWORD is processed from the least significant nibble (F at reset) to the most significant nibble (A at reset). SYNCWORD is used both during modulation (where 0xF’s are replaced with 0x0’s) and during demodulation (where 0xF’s are not required for frame synchronization). In reception an implicit zero is required before the first symbol required by SYNCWORD. The reset value is compliant with IEEE 802.15.4. SYNCWORDL (0xDF09) Bit Name Reset R/W Description 7:0 SYNCWORD[7:0] 0x0F R/W Synchronization word. The SYNCWORD is processed from the least significant nibble (F at reset) to the most significant nibble (A at reset). SYNCWORD is used both during modulation (where 0xF’s are replaced with 0x0’s) and during demodulation (where 0xF’s are not required for frame synchronization). In reception an implicit zero is required before the first symbol required by SYNCWORD. The reset value is compliant with IEEE 802.15.4. TXCTRLH (0xDF0A) Bit Name Reset R/W Description 7:6 TXMIXBUF_CUR[1:0] 10 R/W TX mixer buffer bias current. 00 : 690 uA 01 : 980 uA 10 : 1.16 mA (nominal) 11 : 1.44 mA 5 TX_TURNAROUND 1 R/W Sets the wait time after STXON before transmission is started. 0 : 8 symbol periods (128 us) 1 : 12 symbol periods (192 us) 4:3 TXMIX_CAP_ARRAY[1:0] 0 R/W Selects varactor array settings in the transmit mixers. 2:1 TXMIX_CURRENT[1:0] 0 R/W Transmit mixers current: 00 : 1.72 mA 01 : 1.88 mA 10 : 2.05 mA 11 : 2.21 mA 0 PA_DIFF 1 R/W Power Amplifier (PA) output select. Selects differential or single-ended PA output. 0 : Single-ended output 1 : Differential output Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 190 of 211 TXCTRLL (0xDF0B) Bit Name Reset R/W Description 7:5 PA_CURRENT[2:0] 011 R/W Current programming of the PA 000 : -3 current adjustment 001 : -2 current adjustment 010 : -1 current adjustment 011 : Nominal setting 100 : +1 current adjustment 101 : +2 current adjustment 110 : +3 current adjustment 111 : +4 current adjustment 4:0 PA_LEVEL[4:0] 0x1F R/W Output PA level. (~0 dBm) RXCTRL0H (0xDF0C) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5:4 RXMIXBUF_CUR[1:0] 01 R/W RX mixer buffer bias current. 00 : 690 uA 01 : 980 uA (nominal) 10 : 1.16 mA 11 : 1.44 mA 3:2 HIGH_LNA_GAIN[1:0] 0 R/W Controls current in the LNA gain compensation branch in AGC High gain mode. 00 : Compensation disabled 01 : 100 μA compensation current 10 : 300 μA compensation current (Nominal) 11 : 1000 μA compensation current 1:0 MED_LNA_GAIN[1:0] 10 R/W Controls current in the LNA gain compensation branch in AGC Med gain mode. RXCTRL0L (0xDF0D) Bit Name Reset R/W Description 7:6 LOW_LNA_GAIN[1:0] 11 R/W Controls current in the LNA gain compensation branch in AGC Low gain mode 5:4 HIGH_LNA_CURRENT[1:0] 10 R/W Controls main current in the LNA in AGC High gain mode 00 : 240 μA LNA current (x2) 01 : 480 μA LNA current (x2) 10 : 640 μA LNA current (x2) 11 : 1280 μA LNA current (x2) 3:2 MED_LNA_CURRENT[1:0] 01 R/W Controls main current in the LNA in AGC Med gain mode 1:0 LOW_LNA_CURRENT[1:0] 01 R/W Controls main current in the LNA in AGC Low gain mode Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 191 of 211 RXCTRL1H (0xDF0E) Bit Name Reset R/W Description 7:6 - 0 R0 Reserved, read as 0. 5 RXBPF_LOCUR 1 R/W Controls reference bias current to RX band-pass filters: 0 : 4 uA 1 : 3 uA (Default) 4 RXBPF_MIDCUR 0 R/W Controls reference bias current to RX band-pass filters: 0 : 4 uA (Default) 1 : 3.5 uA 3 LOW_LOWGAIN 1 R/W LNA low gain mode setting in AGC low gain mode. 2 MED_LOWGAIN 0 R/W LNA low gain mode setting in AGC medium gain mode. 1 HIGH_HGM 1 R/W RX Mixers high gain mode setting in AGC high gain mode. 0 MED_HGM 0 R/W RX Mixers high gain mode setting in AGC medium gain mode. RXCTRL1L (0xDF0F) Bit Name Reset R/W Description 7:6 LNA_CAP_ARRAY[1:0] 01 R/W Selects varactor array setting in the LNA 00 : OFF 01 : 0.1 pF (x2) (Nominal) 10 : 0.2 pF (x2) 11 : 0.3 pF (x2) 5:4 RXMIX_TAIL[1:0] 01 R/W Control of the receiver mixers output current. 00 : 12 μA 01 : 16 μA (Nominal) 10 : 20 μA 11 : 24 μA 3:2 RXMIX_VCM[1:0] 01 R/W Controls VCM level in the mixer feedback loop 00 : 8 μA mixer current 01 : 12 μA mixer current (Nominal) 10 : 16 μA mixer current 11 : 20 μA mixer current 1:0 RXMIX_CURRENT[1:0] 10 R/W Controls current in the mixer 00 : 360 μA mixer current (x2) 01 : 720 μA mixer current (x2) 10 : 900 μA mixer current (x2) (Nominal) 11 : 1260 μA mixer current (x2) Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 192 of 211 FSCTRLH (0xDF10) Bit Name Reset R/W Description 7:6 LOCK_THR[1:0] 01 R/W Number of consecutive reference clock periods with successful sync windows required to indicate lock: 00 : 64 01 : 128 10 : 256 11 : 512 5 CAL_DONE 0 R Frequency synthesizer calibration done. 0 : Calibration not performed since the last time the FS was turned on. 1 : Calibration performed since the last time the FS was turned on. 4 CAL_RUNNING 0 R Calibration status, '1' when calibration in progress. 3 LOCK_LENGTH 0 R/W LOCK_WINDOW pulse width: 0: 2 CLK_PRE periods 1: 4 CLK_PRE periods 2 LOCK_STATUS 0 R PLL lock status 0 : PLL is not in lock 1 : PLL is in lock 1:0 FREQ[9:8] 01 (2405 MHz) R/W Frequency control word. Used directly in TX, in RX the LO frequency is automatically set 2 MHz below the RF frequency. [ ] ( [ ]) (2048 [9 : 0] 2 ) MHz 2048 9 : 0 MHz 4 2048 9 : 0 f FREQ RXEN f FREQ Frequency division FREQ LO RF = + − ⋅ = + ⇔ + = FSCTRLL (0xDF11) Bit Name Reset R/W Description 7:0 FREQ[7:0] 0x65 (2405 MHz) R/W Frequency control word. Used directly in TX, in RX the LO frequency is automatically set 2 MHz below the RF frequency. [ ] ( [ ]) (2048 [9 : 0] 2 ) MHz 2048 9 : 0 MHz 4 2048 9 : 0 f FREQ RXEN f FREQ Frequency division FREQ LO RF = + − ⋅ = + ⇔ + = CSPT (0xDF16) Bit Name Reset R/W Description 7:0 CSPT 0x00 R/W CSP T Data register. Contents is decremented each time MAC Timer overflows while CSP program is running. CSP program stops when is about to count to 0. Setting T=0xFF disables decrement function. CSPX (0xDF12) Bit Name Reset R/W Description 7:0 CSPX 0x00 R/W CSP X Data register. Used by CSP WAITX, RANDXY and conditional instructions Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 193 of 211 CSPY (0xDF13) Bit Name Reset R/W Description 7:0 CSPY 0x00 R/W CSP Y Data register. Used by CSP INCY, DECY, INCMAXY, RANDXY and conditional instructions CSPZ (0xDF14) Bit Name Reset R/W Description 7:0 CSPZ 0x00 R/W CSP Z Data register. Used by CSP DECZ and conditional instructions CSPCTRL (0xDF15) Bit Name Reset R/W Description 7:1 - 0x00 R0 Reserved, read as 0 0 CPU_CTRL 0 R/W CSP CPU control input. Used by CSP conditional instructions. RFPWR (0xDF17) Bit Name Reset R/W Description 7:5 - 0 R0 Reserved, read as 0. 4 ADI_RADIO_PD 1 R ADI_RADIO_PD is a delayed version of RREG_RADIO_PD. The delay is set by RREG_DELAY[2:0]. When ADI_RADIO_PD is 0, all analog modules in the radio are set in power down. ADI_RADIO_PD is read only. 3 RREG_RADIO_PD 1 R/W Power down of the voltage regulator to the analog part of the radio. This signal is used to enable or disable the analog radio. 0 : Power up 1 : Power down 2:0 RREG_DELAY[2:0] 100 R/W Delay value used in power-on for voltage regulator VREG_DELAY[2:0] Delay Units 000 0 μs 001 31 μs 010 63 μs 011 125 μs 100 250 μs 101 500 μs 110 1000 μs 111 2000 μs Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 194 of 211 FSMTCH (0xDF20) Bit Name Reset R/W Description 7:5 TC_RXCHAIN2RX[2:0] 011 R/W The time in 5 us steps between the time the RX chain is enabled and the demodulator and AGC is enabled. The RX chain is started when the band pass filter has been calibrated (after 6.5 symbol periods). 4:2 TC_SWITCH2TX[2:0] 110 R/W The time in advance the RXTX switch is set high, before enabling TX. Unit is μs. 1:0 TC_PAON2TX[3:2] 10 R/W The time in advance the PA is powered up before enabling TX. Unit is μs. FSMTCL (0xDF21) Bit Name Reset R/W Description 7:6 TC_PAON2TX[1:0] 10 R/W The time in advance the PA is powered up before enabling TX. Unit is μs. 5:3 TC_TXEND2SWITCH[2:0] 010 R/W The time after the last chip in the packet is sent, and the rxtx switch is disabled. Unit is μs. 2:0 TC_TXEND2PAOFF[2:0] 100 R/W The time after the last chip in the packet is sent, and the PA is set in power-down. Also the time at which the modulator is disabled. Unit is μs. MANANDH (0xDF22) Bit Name Reset R/W Description 7 VGA_RESET_N 1 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain. 6 BIAS_PD 1 R/W Reserved, read as 0 5 BALUN_CTRL 1 R/W The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch. 4 RXTX 1 R/W RXTX signal: controls whether the LO buffers (0) or PA buffers (1) should be used. 3 PRE_PD 1 R/W Powerdown of prescaler. 2 PA_N_PD 1 R/W Powerdown of PA (negative path). 1 PA_P_PD 1 R/W Powerdown of PA (positive path). When PA_N_PD=1 and PA_P_PD=1 the up conversion mixers are in powerdown. 0 DAC_LPF_PD 1 R/W Powerdown of TX DACs. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 195 of 211 MANANDL (0xDF23) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0 6 RXBPF_CAL_PD 1 R/W Powerdown control of complex band pass receive filter calibration oscillator. 5 CHP_PD 1 R/W Powerdown control of charge pump. 4 FS_PD 1 R/W Powerdown control of VCO, I/Q generator, LO buffers. 3 ADC_PD 1 R/W Powerdown control of the ADCs. 2 VGA_PD 1 R/W Powerdown control of the VGA. 1 RXBPF_PD 1 R/W Powerdown control of complex band pass receive filter. 0 LNAMIX_PD 1 R/W Powerdown control of LNA, down conversion mixers and front-end bias. MANORH (0xDF24) Bit Name Reset R/W Description 7 VGA_RESET_N 0 R/W The VGA_RESET_N signal is used to reset the peak detectors in the VGA in the RX chain. 6 BIAS_PD 0 R/W Global Bias power down (1) 5 BALUN_CTRL 0 R/W The BALUN_CTRL signal controls whether the PA should receive its required external biasing (1) or not (0) by controlling the RX/TX output switch. 4 RXTX 0 R/W RXTX signal: controls whether the LO buffers (0) or PA buffers (1) should be used. 3 PRE_PD 0 R/W Powerdown of prescaler. 2 PA_N_PD 0 R/W Powerdown of PA (negative path). 1 PA_P_PD 0 R/W Powerdown of PA (positive path). When PA_N_PD=1 and PA_P_PD=1 the up conversion mixers are in powerdown. 0 DAC_LPF_PD 0 R/W Powerdown of TX DACs. MANORL (0xDF25) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0 6 RXBPF_CAL_PD 0 R/W Powerdown control of complex band pass receive filter calibration oscillator. 5 CHP_PD 0 R/W Powerdown control of charge pump. 4 FS_PD 0 R/W Powerdown control of VCO, I/Q generator, LO buffers. 3 ADC_PD 0 R/W Powerdown control of the ADCs. 2 VGA_PD 0 R/W Powerdown control of the VGA. 1 RXBPF_PD 0 R/W Powerdown control of complex band pass receive filter. 0 LNAMIX_PD 0 R/W Powerdown control of LNA, down conversion mixers and front-end bias. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 196 of 211 AGCCTRLH (0xDF26) Bit Name Reset R/W Description 7 VGA_GAIN_OE 0 R/W Use the VGA_GAIN value during RX instead of the AGC value. 6:0 VGA_GAIN[6:0] 0x7F R/W When written, VGA manual gain override value; when read, the currently used VGA gain setting. AGCCTRLL (0xDF27) Bit Name Reset R/W Description 7:4 - 0 R0 Reserved, read as 0. 3:2 LNAMIX_GAINMODE_O [1:0] 00 R/W LNA / Mixer Gain mode override setting 00 : Gain mode is set by AGC algorithm 01 : Gain mode is always low-gain 10 : Gain mode is always med-gain 11 : Gain mode is always high-gain 1:0 LNAMIX_GAINMODE[1:0] 00 R Status bit, defining the currently selected gain mode selected by the AGC or overridden by the LNAMIX_GAINMODE_O setting. Note that this value is updated by HW and may have changed between reset and when read. FSMSTATE (0xDF39) Bit Name Reset R/W Description 7:6 - 0 R0 Reserved, read as 0. 5:0 FSM_FFCTRL_STATE[5:0 ] - R Gives the current state of the FIFO and Frame Control (FFCTRL) finite state machine. ADCTSTH (0xDF3A) Bit Name Reset R/W Function 7 ADC_CLOCK_DISABLE 0 R/W ADC Clock Disable 0 : Clock enabled when ADC enabled 1 : Clock disabled, even if ADC is enabled 6:0 ADC_I[6:0] - R Returns the current ADC I-branch value. ADCTSTL (0xDF3B) Bit Name Reset R/W Function 7 - 0 R0 Reserved, read as 0. 6:0 ADC_Q[6:0] - R Returns the current ADC Q-branch value. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 197 of 211 DACTSTH (0xDF3C) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6:4 DAC_SRC[2:0] 000 R/W The TX DACs data source is selected by DAC_SRC according to: 000 : Normal operation (from modulator). 001 : The DAC_I_O and DAC_Q_O override values below.- 010 : From ADC, most significant bits 011 : I/Q after digital down mix and channel filtering. 100 : Full-spectrum White Noise (from CRC) 101 : From ADC, least significant bits 110 : RSSI / Cordic Magnitude Output 111 : HSSD module. This feature will often require the DACs to be manually turned on in MANOVR and PAMTST.ATESTMOD_MODE=4. 3:0 DAC_I_O[5:2] 000 R/W I-branch DAC override value. DACTSTL (0xDF3D) Bit Name Reset R/W Description 7:6 DAC_I_O[1:0] 00 R/W I-branch DAC override value. 5:0 DAC_Q_O[5:0] 0x00 R/W Q-branch DAC override value. IEEE_ADDR0 (0xDF43) Bit Name Reset R/W Description 7:0 IEEE_ADDR0[7:0] 0x00 R/W IEEE ADDR byte 0 (LSB) IEEE_ADDR1 (0xDF44) Bit Name Reset R/W Description 7:0 IEEE_ADDR1[7:0] 0x00 R/W IEEE ADDR byte 1 IEEE_ADDR2 (0xDF45) Bit Name Reset R/W Description 7:0 IEEE_ADDR2[7:0] 0x00 R/W IEEE ADDR byte 2 IEEE_ADDR3 (0xDF46) Bit Name Reset R/W Description 7:0 IEEE_ADDR3[7:0] 0x00 R/W IEEE ADDR byte 3 IEEE_ADDR4 (0xDF47) Bit Name Reset R/W Description 7:0 IEEE_ADDR4[7:0] 0x00 R/W IEEE ADDR byte 4 Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 198 of 211 IEEE_ADDR5 (0xDF48) Bit Name Reset R/W Description 7:0 IEEE_ADDR5[7:0] 0x00 R/W IEEE ADDR byte 5 IEEE_ADDR6 (0xDF49) Bit Name Reset R/W Description 7:0 IEEE_ADDR6[7:0] 0x00 R/W IEEE ADDR byte 6 IEEE_ADDR7 (0xDF4A) Bit Name Reset R/W Description 7:0 IEEE_ADDR7[7:0] 0x00 R/W IEEE ADDR byte 7 (MSB) PANIDH (0xDF4B) Bit Name Reset R/W Description 7:0 PANIDH[7:0] 0x00 R/W PAN identifier high byte PANIDL (0xDF4C) Bit Name Reset R/W Description 7:0 PANIDL[7:0] 0x00 R/W PAN identifier low byte SHORTADDRH (0xDF4D) Bit Name Reset R/W Description 7:0 SHORTADDRH[7:0] 0x00 R/W Short address high byte SHORTADDRL (0xDF4E) Bit Name Reset R/W Description 7:0 SHORTADDRL[7:0] 0x00 R/W Short address low byte IOCFG0 (0xDF4F) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6:0 FIFOP_THR[6:0] 0x40 R/W Sets the number of bytes in RXFIFO that is required for FIFOP to go high. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 199 of 211 IOCFG1 (0xDF50) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6 OE_CCA 0 R/W CCA is output on P1.7 when this bit is 1 5 IO_CCA_POL 0 R/W Polarity of the IO_CCA signal. This bit is xor’ed with the internal CCA signal. 4:0 IO_CCA_SEL 00000 R/W Multiplexer setting for the CCA signal. Must be 0x00 in order to output the CCA status. IOCFG2 (0xDF51) Bit Name Reset R/W Description 7 - 0 R0 Reserved, read as 0. 6 OE_SFD 0 R/W SFD is output on P1.6 when this bit is 1 5 IO_SFD_POL 0 R/W Polarity of the IO_SFD signal. This bit is xor’ed with the internal SFD signal. 4:0 IO_SFD_SEL 00000 R/W Multiplexer setting for the SFD signal. Must be 0x00 in order to output the SFD status IOCFG3 (0xDF52) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5:4 HSSD_SRC 00 R/W Configures the HSSD interface. Only the first 4 settings (compared to CC2420) are used. 00 : Off 01 : Output AGC status (gain setting/peak detector status/accumulator value) 10 : Output ADC I and Q values 11 : Output I/Q after digital down mix and channel filtering 3 OE_FIFOP 0 R/W FIFOP is output on P1.5 when this bit is 1. 2 IO_FIFOP_POL 0 R/W Polarity of the IO_FIFOP signal. This bit is xor’ed with the internal FIFOP signal 1 OE_FIFO 0 R/W FIFO is output on P1.4 when this bit is 1 0 IO_FIFO_POL 0 R/W Polarity of the IO_FIFO signal. This bit is xor’ed with the internal FIFO signal RXFIFOCNT (0xDF53) Bit Name Reset R/W Description 7:0 RXFIFOCNT[7:0] 0x00 R Number of bytes in the RX FIFO Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 200 of 211 FSMTC1 (0xDF54) Bit Name Reset R/W Description 7:6 - 00 R0 Reserved, read as 0. 5 ABORTRX_ON_SRXON 1 R/W Abort RX when SRXON strobe is issued 0 : Packet reception is not aborted when SRXON is issued 1 : Packet reception is aborted when SRXON is issued 4 RX_INTERRUPTED 0 R RX interrupted by strobe command This bit is cleared when the next strobe is detected. 0 : Strobe command detected 1 : Packet reception was interrupted by strobe command 3 AUTO_TX2RX_OFF 0 R/W Automatically go to RX after TX. Applies to both data packets and ACK packets. 0 : Automatic RX after TX 1 : No automatic RX after TX 2 RX2RX_TIME_OFF 0 R/W Turns off the 12 symbol timeout after packet reception has ended. Active high. 1 PENDING_OR 0 R/W This bit is OR’ed with the pending bit from FFCTRL before it goes to the modulator. 0 ACCEPT_ACKPKT 1 R/W Accept ACK packet control. 0 : Reject all ACK packets 1 : ACK packets are received CHVER (0xDF60) Bit Name Reset R/W Description 7:0 VERSION[7:0] 0x03 R Chip revision number. The relationship between the value in VERSION[7:0] and the die revision is as follows: 0x03 : Die revision D The current number in VERSION[7:0] may not be consistent with past or future die revisions of this product CHIPID (0xDF61) Bit Name Reset R/W Description 7:0 CHIPID[7:0] 0x85 R Chip identification number. Always read as 0x85. Not Recommended for New Designs CC2430 Radio : Radio Registers CC2430 Data Sheet (rev. 2.1) SWRS036F Page 201 of 211 RFSTATUS (0xDF62) Bit Name Reset R/W Description 7:5 - 000 R0 Reserved, read as 0. 4 TX_ACTIVE 0 R TX active indicates transmission in progress 0 : TX inactive 1 : TX active 3 FIFO 0 R RXFIFO data available 0 : No data available in RXFIFO 1 : One or more bytes available in RXFIFO 2 FIFOP 0 R RXFIFO threshold flag 0 : Number of bytes in RXFIFO is less or equal threshold set by IOCFG0.FIFOP_THR 1 : Number of bytes in RXFIFO is greater than threshold set by IOCFG0.FIFOP_THR Note that if frame filtering/address recognition is enabled this bit is set only when the frame has passed filtering. This bit is also set when a complete frame has been received. 1 SFD 0 R Start of Frame Delimiter status 0 : SFD inactive 1 : SFD active 0 CCA R Clear Channel Assessment IRQSRC (0xDF64) Bit Name Reset R/W Description 7:1 - 0000000 R0 Reserved, read as 0. 0 TXACK 0 R/W TX Acknowledge interrupt enable. 0 : RFIF interrupt is not set for acknowledge frames 1 : RFIF interrupt is set for acknowledge frames Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 202 of 211 15 Voltage Regulators The CC2430 includes two low drop-out voltage regulators. These are used to provide a 1.8 V power supply to the CC2430 analog and digital power supplies. Note: It is recommended that the voltage regulators are not used to provide power to external circuits. This is because of limited power sourcing capability and due to noise considerations. External circuitry can be powered if they can be used when internal power consumption is low and can be set I PD mode when internal power consumption I high. The analog voltage regulator input pin AVDD_RREG is to be connected to the unregulated 2.0 to 3.6 V power supply. The regulated 1.8 V voltage output to the analog parts, is available on the RREG_OUT pin. The digital regulator input pin AVDD_DREG is also to be connected to the unregulated 2.0 to 3.6 V power supply. The output of the digital regulator is connected internally within the CC2430 to the digital power supply. The voltage regulators require external components as described in section 10 on page 27. 15.1 Voltage Regulators Power-on The analog voltage regulator is disabled by setting the RF register bit RFPWR.RREG_RADIO_PD to 1. When the analog voltage regulator is powered-on by clearing the RFPWR.RREG_RADIO_PD bit, there will be a delay before the regulator is enabled. This delay is programmable through the RFPWR RF register. The interrupt flag RFIF.IRQ_RREG_PD is set when the delay has expired. The delayed power-on can also be observed by polling the RF register bit RFPWR.ADI_RADIO_PD. The digital voltage regulator is disabled when the CC2430 is placed in power modes PM2 or PM3 (see section 13.1). When the voltage regulators are disabled, register and RAM contents will be retained while the unregulated 2.0 to 3.6 power supply is present. 16 Evaluation Software Texas Instruments provides users of CC2430 with a software program, SmartRF® Studio, which may be used for radio performance and functionality evaluation. SmartRF® Studio runs on Microsoft Windows 95/98 and Microsoft Windows NT/2000/XP. SmartRF® Studio can be downloaded from the Texas Instruments web page: http://www.ti.com/lpw Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 203 of 211 17 Register overview ACC (0xE0) – Accumulator...................................................................................................................43 ADCCFG (0xF2) – ADC Input Configuration ........................................................................................83 ADCCON1 (0xB4) – ADC Control 1....................................................................................................131 ADCCON2 (0xB5) – ADC Control 2....................................................................................................132 ADCCON3 (0xB6) – ADC Control 3....................................................................................................133 ADCH (0xBB) – ADC Data High .........................................................................................................131 ADCL (0xBA) – ADC Data Low...........................................................................................................130 ADCTSTH (0xDF3A)...........................................................................................................................196 ADCTSTL (0xDF3B) ...........................................................................................................................196 AGCCTRLH (0xDF26) ........................................................................................................................196 AGCCTRLL (0xDF27).........................................................................................................................196 B (0xF0) – B Register............................................................................................................................43 CHIPID (0xDF61) ................................................................................................................................200 CHVER (0xDF60)................................................................................................................................200 CLKCON (0xC6) – Clock Control..........................................................................................................70 CSPCTRL (0xDF15) ...........................................................................................................................193 CSPT (0xDF16)...................................................................................................................................192 CSPX (0xDF12) ..................................................................................................................................192 CSPY (0xDF13) ..................................................................................................................................193 CSPZ (0xDF14)...................................................................................................................................193 DACTSTH (0xDF3C)...........................................................................................................................197 DACTSTL (0xDF3D) ...........................................................................................................................197 DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte ...........................................97 DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte ............................................97 DMAARM (0xD6) – DMA Channel Arm ................................................................................................96 DMAIRQ (0xD1) – DMA Interrupt Flag .................................................................................................98 DMAREQ (0xD7) – DMA Channel Start Request and Status...............................................................97 DPH0 (0x83) – Data Pointer 0 High Byte..............................................................................................42 DPH1 (0x85) – Data Pointer 1 High Byte..............................................................................................42 DPL0 (0x82) – Data Pointer 0 Low Byte ...............................................................................................42 DPL1 (0x84) – Data Pointer 1 Low Byte ...............................................................................................42 DPS (0x92) – Data Pointer Select ........................................................................................................42 ENCCS (0xB3) – Encryption Control and Status ................................................................................140 ENCDI (0xB1) – Encryption Input Data...............................................................................................140 ENCDO (0xB2) – Encryption Output Data ..........................................................................................140 FADDRH (0xAD) – Flash Address High Byte .......................................................................................77 FADDRL (0xAC) – Flash Address Low Byte.........................................................................................77 FCTL (0xAE) – Flash Control................................................................................................................77 FSCTRLH (0xDF10)............................................................................................................................192 FSCTRLL (0xDF11) ............................................................................................................................192 FSMSTATE (0xDF39) .........................................................................................................................196 FSMTC1 (0xDF54)..............................................................................................................................200 FSMTCH (0xDF20) .............................................................................................................................194 FSMTCL (0xDF21)..............................................................................................................................194 FWDATA (0xAF) – Flash Write Data ....................................................................................................77 FWT (0xAB) – Flash Write Timing ........................................................................................................77 IEEE_ADDR0 (0xDF43)......................................................................................................................197 IEEE_ADDR1 (0xDF44)......................................................................................................................197 IEEE_ADDR2 (0xDF45)......................................................................................................................197 IEEE_ADDR3 (0xDF46)......................................................................................................................197 IEEE_ADDR4 (0xDF47)......................................................................................................................197 IEEE_ADDR5 (0xDF48)......................................................................................................................198 IEEE_ADDR6 (0xDF49)......................................................................................................................198 IEEE_ADDR7 (0xDF4A) .....................................................................................................................198 IEN0 (0xA8) – Interrupt Enable 0..........................................................................................................52 IEN2 (0x9A) – Interrupt Enable 2..........................................................................................................53 IOCFG0 (0xDF4F)...............................................................................................................................198 IOCFG1 (0xDF50)...............................................................................................................................199 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 204 of 211 IOCFG2 (0xDF51)...............................................................................................................................199 IOCFG3 (0xDF52)...............................................................................................................................199 IP0 (0xA9) – Interrupt Priority 0 ............................................................................................................58 IP1 (0xB9) – Interrupt Priority 1 ............................................................................................................57 IRCON (0xC0) – Interrupt Flags 4 ........................................................................................................56 IRCON2 (0xE8) – Interrupt Flags 5.......................................................................................................57 IRQSRC (0xDF64) ..............................................................................................................................201 MANANDH (0xDF22)..........................................................................................................................194 MANANDL (0xDF23)...........................................................................................................................195 MANORH (0xDF24) ............................................................................................................................195 MANORL (0xDF25).............................................................................................................................195 MDMCTRL0H (0xDF02)......................................................................................................................186 MDMCTRL0L (0xDF03) ......................................................................................................................187 MDMCTRL1H (0xDF04)......................................................................................................................187 MDMCTRL1L (0xDF05) ......................................................................................................................188 MEMCTR (0xC7) – Memory Arbiter Control .........................................................................................41 MPAGE (0x93) – Memory Page Select ................................................................................................40 P0 (0x80) – Port 0 .................................................................................................................................82 P0DIR (0xFD) – Port 0 Direction...........................................................................................................84 P0IFG (0x89) – Port 0 Interrupt Status Flag .........................................................................................86 P0INP (0x8F) – Port 0 Input Mode........................................................................................................85 P0SEL (0xF3) – Port 0 Function Select ................................................................................................83 P1 (0x90) – Port 1 .................................................................................................................................82 P1DIR (0xFE) – Port 1 Direction...........................................................................................................84 P1IEN (0x8D) – Port 1 Interrupt Mask ..................................................................................................87 P1IFG (0x8A) – Port 1 Interrupt Status Flag.........................................................................................86 P1INP (0xF6) – Port 1 Input Mode........................................................................................................85 P1SEL (0xF4) – Port 1 Function Select ................................................................................................83 P2 (0xA0) – Port 2.................................................................................................................................83 P2DIR (0xFF) – Port 2 Direction ...........................................................................................................85 P2IFG (0x8B) – Port 2 Interrupt Status Flag.........................................................................................86 P2INP (0xF7) – Port 2 Input Mode........................................................................................................85 P2SEL (0xF5) – Port 2 Function Select ................................................................................................84 PANIDH (0xDF4B) ..............................................................................................................................198 PANIDL (0xDF4C)...............................................................................................................................198 PCON (0x87) – Power Mode Control....................................................................................................67 PERCFG (0xF1) – Peripheral Control...................................................................................................83 PICTL (0x8C) – Port Interrupt Control ..................................................................................................87 PSW (0xD0) – Program Status Word ...................................................................................................43 RFD (0xD9) – RF Data........................................................................................................................157 RFIF (0xE9) – RF Interrupt Flags .......................................................................................................156 RFIM (0x91) – RF Interrupt Mask .......................................................................................................157 RFPWR (0xDF17) ...............................................................................................................................193 RFSTATUS (0xDF62) .........................................................................................................................201 RNDH (0xBD) – Random Number Generator Data High Byte ...........................................................135 RNDL (0xBC) – Random Number Generator Data Low Byte.............................................................135 RSSIH (0xDF06) .................................................................................................................................188 RXCTRL0H (0xDF0C).........................................................................................................................190 RXCTRL0L (0xDF0D) .........................................................................................................................190 RXCTRL1H (0xDF0E).........................................................................................................................191 RXCTRL1L (0xDF0F)..........................................................................................................................191 RXFIFOCNT (0xDF53)........................................................................................................................199 S0CON (0x98) – Interrupt Flags 2 ........................................................................................................55 S1CON (0x9B) – Interrupt Flags 3........................................................................................................55 SHORTADDRH (0xDF4D) ..................................................................................................................198 SHORTADDRL (0xDF4E) ...................................................................................................................198 SLEEP (0xBE) – Sleep Mode Control...................................................................................................67 SP (0x81) – Stack Pointer.....................................................................................................................44 ST0 (0x95) – Sleep Timer 0................................................................................................................127 ST1 (0x96) – Sleep Timer 1................................................................................................................126 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 205 of 211 ST2 (0x97) – Sleep Timer 2................................................................................................................126 SYNCWORDH (0xDF08) ....................................................................................................................189 SYNCWORDL (0xDF09).....................................................................................................................189 T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value High................................................107 T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value Low .................................................107 T1CC1H (0xDD) – Timer 1 Channel 1 Capture/Compare Value High ...............................................108 T1CC1L (0xDC) – Timer 1 Channel 1 Capture/Compare Value Low.................................................108 T1CC2H (0xDF) – Timer 1 Channel 2 Capture/Compare Value High................................................109 T1CC2L (0xDE) – Timer 1 Channel 2 Capture/Compare Value Low .................................................109 T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control.....................................................107 T1CCTL1 (0xE6) – Timer 1 Channel 1 Capture/Compare Control.....................................................108 T1CCTL2 (0xE7) – Timer 1 Channel 2 Capture/Compare Control.....................................................109 T1CNTH (0xE3) – Timer 1 Counter High............................................................................................106 T1CNTL (0xE2) – Timer 1 Counter Low .............................................................................................106 T1CTL (0xE4) – Timer 1 Control and Status ......................................................................................106 T2CAPHPH (0xA5) – Timer 2 Period High Byte.................................................................................115 T2CAPLPL (0xA4) – Timer 2 Period Low Byte...................................................................................115 T2CMP (0x94) – Timer 2 Compare Value ..........................................................................................114 T2CNF (0xC3) – Timer 2 Configuration ..............................................................................................113 T2OF0 (0xA1) – Timer 2 Overflow Count 0 ........................................................................................115 T2OF1 (0xA2) – Timer 2 Overflow Count 1 ........................................................................................114 T2OF2 (0xA3) – Timer 2 Overflow Count 2 ........................................................................................114 T2PEROF0 (0x9C) – Timer 2 Overflow Capture/Compare 0 .............................................................116 T2PEROF1 (0x9D) – Timer 2 Overflow Capture/Compare 1 .............................................................115 T2PEROF2 (0x9E) – Timer 2 Overflow Capture/Compare 2..............................................................115 T2THD (0xA7) – Timer 2 Timer Value High Byte................................................................................114 T2TLD (0xA6) – Timer 2 Timer Value Low Byte.................................................................................114 T3CC0 (0xCD) – Timer 3 Channel 0 Compare Value ........................................................................120 T3CC1 (0xCF) – Timer 3 Channel 1 Compare Value.........................................................................121 T3CCTL0 (0xCC) – Timer 3 Channel 0 Compare Control..................................................................120 T3CCTL1 (0xCE) – Timer 3 Channel 1 Compare Control ..................................................................121 T3CNT (0xCA) – Timer 3 Counter ......................................................................................................118 T3CTL (0xCB) – Timer 3 Control ........................................................................................................119 T4CC0 (0xED) – Timer 4 Channel 0 Compare Value.........................................................................123 T4CC1 (0xEF) – Timer 4 Channel 1 Compare Value .........................................................................124 T4CCTL0 (0xEC) – Timer 4 Channel 0 Compare Control ..................................................................123 T4CCTL1 (0xEE) – Timer 4 Channel 1 Compare Control ..................................................................124 T4CNT (0xEA) – Timer 4 Counter ......................................................................................................121 T4CTL (0xEB) – Timer 4 Control ........................................................................................................122 TCON (0x88) – Interrupt Flags .............................................................................................................54 TIMIF (0xD8) – Timers 1/3/4 Interrupt Mask/Flag...............................................................................125 TXCTRLH (0xDF0A) ...........................................................................................................................189 TXCTRLL (0xDF0B)............................................................................................................................190 U0BAUD (0xC2) – USART 0 Baud Rate Control................................................................................149 U0CSR (0x86) – USART 0 Control and Status...................................................................................147 U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer ..............................................................149 U0GCR (0xC5) – USART 0 Generic Control ......................................................................................149 U0UCR (0xC4) – USART 0 UART Control .........................................................................................148 U1BAUD (0xFA) – USART 1 Baud Rate Control................................................................................152 U1CSR (0xF8) – USART 1 Control and Status ..................................................................................150 U1DBUF (0xF9) – USART 1 Receive/Transmit Data Buffer...............................................................152 U1GCR (0xFC) – USART 1 Generic Control ......................................................................................152 U1UCR (0xFB) – USART 1 UART Control .........................................................................................151 WDCTL (0xC9) – Watchdog Timer Control ........................................................................................142 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 206 of 211 18 Package Description (QLP 48) All dimensions are in millimeters, angles in degrees. NOTE: The CC2430 is available in RoHS leadfree package only. Compliant with JEDEC MS-020. Table 51: Package dimensions Quad Leadless Package (QLP) D D1 E E1 e b L D2 E2 QLP 48 Min Max 6.9 7.0 7.1 6.65 6.75 6.85 6.9 7.0 7.1 6.65 6.75 6.85 0.5 0.18 0.30 0.3 0.4 0.5 5.05 5.10 5.15 5.05 5.10 5.15 The overall package height is 0.85 +/- 0.05 All dimensions in mm Figure 51: Package dimensions drawing Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 207 of 211 18.1 Recommended PCB layout for package (QLP 48) Figure 52: Recommended PCB layout for QLP 48 package Note: The figure is an illustration only and not to scale. There are nine 14 mil diameter via holes distributed symmetrically in the ground pad under the package. See also the CC2430 EM reference design 18.2 Package thermal properties Table 52: Thermal properties of QLP 48 package Thermal resistance Air velocity [m/s] 0 Rth,j-a [K/W] 25.6 18.3 Soldering information The recommendations for lead-free solder reflow in IPC/JEDEC J-STD-020C should be followed. 18.4 Tray specification Table 53: Tray specification Tray Specification Package Tray Width Tray Height Tray Length Units per Tray QLP 48 135.9mm ± 0.25mm 7.62mm ± 0.13mm 322.6mm ± 0.25mm 260 18.5 Carrier tape and reel specification Carrier tape and reel is in accordance with EIA Specification 481. Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 208 of 211 Table 54: Carrier tape and reel specification Tape and Reel Specification Package Tape Width Component Pitch Hole Pitch Reel Diameter Units per Reel QLP 48 16mm 12mm 4mm 13 inches 2500 Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 209 of 211 19 Ordering Information Table 55: Ordering Information Ordering part number Description MOQ CC2430F128RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 260 CC2430F128RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 2,500 CC2430ZF128RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver, including royalty for using TI’s ZigBee® Software Stack, ZStack ™, in an end product 260 CC2430ZF128RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 128 Kbytes in-system programmable flash memory, System-on-chip RF transceiver, including royalty for using TI’s ZigBee® Software Stack, ZStack ™, in an end product 2,500 CC2430F64RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 64 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 260 CC2430F64RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 64 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 2,500 CC2430F32RTC CC2430, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, 32 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 260 CC2430F32RTCR CC2430, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, 32 Kbytes in-system programmable flash memory, System-on-chip RF transceiver. 2,500 CC2430DK CC2430 DK Development kit. 1 CC2430ZDK CC2430 ZigBee® DK Development kit 1 CC2430EMK CC2430 Evaluation Module Kit 1 CC2430DB CC2430 Demonstration Board 1 MOQ = Minimum Order Quantity T&R = tape and reel Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 210 of 211 20 General Information 20.1 Document History Table 56: Document History Revision Date Description/Changes 2.1 2007-05-30 First data sheet for released product. Preliminary data sheets exist for engineering samples and pre-production prototype devices, but these data sheets are not complete and may be incorrect in some aspects compared with the released product. 21 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw 22 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: support.ti.com TI Semiconductor KnowledgeBase Home Page: support.ti.com/sc/knowledgebase Product Information Centers Americas Phone: +1(972) 644-5580 Fax: +1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.htm Europe, Middle East and Africa Phone: Belgium (English) +32 (0) 27 45 54 32 Finland (English) +358 (0) 9 25173948 France +33 (0) 1 30 70 11 64 Germany +49 (0) 8161 80 33 11 Israel (English) 180 949 0107 Italy 800 79 11 37 Netherlands (English) +31 (0) 546 87 95 45 Russia +7 (0) 95 363 4824 Spain +34 902 35 40 28 Sweden (English) +46 (0) 8587 555 22 United Kingdom +44 (0) 1604 66 33 99 Fax: +49 (0) 8161 80 2045 Internet: support.ti.com/sc/pic/euro.htm Not Recommended for New Designs CC2430 CC2430 Data Sheet (rev. 2.1) SWRS036F Page 211 of 211 Japan Fax International +81-3-3344-5317 Domestic 0120-81-0036 Internet/Email International support.ti.com/sc/pic/japan.htm Domestic www.tij.co.jp/pic Asia Phone International +886-2-23786800 Domestic Toll-Free Number Australia 1-800-999-084 China 800-820-8682 Hong Kon 800-96-5941 India +91-80-51381665 (Toll) Indonesia 001-803-8861-1006 Korea 080-551-2804 Malaysia 1-800-80-3973 New Zealand 0800-446-934 Philippines 1-800-765-7404 Singapore 800-886-1028 Taiwan 0800-006800 Thailand 001-800-886-0010 Fax +886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.htm Not Recommended for New Designs TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CC2430F32RTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CC2430F64RTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CC2430ZF128RTCR VQFN RTC 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC2430F32RTCR VQFN RTC 48 2500 378.0 70.0 346.0 CC2430F64RTCR VQFN RTC 48 2500 378.0 70.0 346.0 CC2430ZF128RTCR VQFN RTC 48 2500 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated Overview Freescale Semiconductor proudly introduces an addition to the 68K/ColdFire family of embedded controllers, a complete hardware and software solution for commercial VoIP applications based on the popular MCF532x products. The solution is designed to help embedded developers reduce time-tomarket by providing a complete hardware and software solution that can function as a reference design or a take-to-market product platform. This flexibility gives developers the option to integrate fully developed module boards or design their own application. The system includes all required software components to develop a feature-rich product and does not require an NRE, lowing overall system cost. The solution is supported by a stand-alone development kit that is ready to demo out-of-the-box. This easy to use, cost-effective solution will help simplify development and allow designers to enable more applications with VoIP capability. Target Markets • Commercial/Industrial Uses Gas pump Vending machine Toll booth ATM Medical equipment Production equipment Intercom • Residential Uses Security system Child monitor • Telephone Uses Basic VoIP telephone ColdFire ColdFire® Embedded Controllers MCF532x/7x Embedded VoIP Solution MCF53281CVM240 / MCF53721CVM240 Applications • Shell/telnet server • DHCP/NTP and networking applications • Webserver • Microwindows/NanoX for LCD GUI applications Full-Featured Bootloader • Persistent object support • Kernel API and CLI • TFTP client/server • Flash partitioning • Watchdog support Management Middleware • Device management API • WED UI, SSL remote provisioning, voice response VoIP/Media Middleware • Certified SIP signaling stack • Feature-rich telephony application • QoS and firewall traversal • Compatible with leading infrastructure equipment and open source PBX implementations • Simple command line API Protocol Stacks and Low Level Drivers Audio Internet CODEC Vocoders G.711, G.729, iLBC, AEC/LEC Call Control and Signaling (SIP) Ethernet MAC and PHY (Wired or Wireless) Hardware Software Hardware RTOS (μClinux) SSI API API API Analog to Digital and Digital to Analog Conversion Voice Compression and Decompression Call Setup and Control Packet Handling and Streaming Bit Transmission and Reception Ethernet Open source Linux (2.6) available separately as open source BSP Microphone Speaker Device Management Management Middleware from Arcturus including API, web user interface, remote provisioning, voice response Supplied by Encore Software as binary, with some parameters (such as echo cancelation) tunable. Suitable for 1 or 2 Audio channel applications. Algorithms supported: G. 168 LEC, AEC, DTMF, CPT, AGC, G.711, G.729AB, G.726, CID gen. iLBC & G.722 planned OpenSIP based telephony/media MiddleWare solution from Arcturus Networks with proprietary components. Open source portions supplied as source code, proprietary portions as binary. Telephony application includes support for: Caller-ID, Call Waiting, Hold/Retreive, Call Transfers, Conference, Hotline, Push-to-Call, Speed Dials, CID Privacy, Outgoing Call Blocking, Call Back on Busy... NRE-Free Software Solution BDM PLL SVGA LCD Controller 16-ch. DMA UART UART UART MiddleWare SIP SSI QSPI 4-ch., 32-bit Timer 4-ch. PWM I2C GPIO JTAG VoIP Software Vocoders System Bus Controller DDR/SDR SDRAM Controller and Chip Selects eMAC μClinux 32 KB SRAM USB Host USB h/d/OTG V3 ColdFire® Core 16 KB Unified Cache DMA CAN 10/100 FEC MCF532x Block Diagram ColdFire Learn More: For current information about Freescale products and documentation, please visit www.freescale.com/coldfire. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007 Document Number: CFM53281KITFS REV 0 VoIP Development System The ColdFire Embedded VoIP Development Kit, the M53281KIT, is a compact, easy-tointegrate development system designed by Freescale and Freescale Design Alliance Partner, Arcturus Networks, Inc., for enabling commercial VoIP functionality in embedded applications. The module is based on the 240 MHz Freescale ColdFire® MCF53281 microprocessor and includes all required system memory and terminations to enable most applications without the need for external circuitry. It features audio, Ethernet, CAN, serial, I/O and USB host communications systems as well as standard peripheral device connectivity using I2C or QSPI. The device also features an integrated SVGA LCD controller for applications requiring high-resolution graphical displays. Daughter cards are available for LCD-to-VGA scan conversion and FXS applications. The solution fits standard off-the-shelf enclosures to help accelerate proof-of-concept implementations and is certified by applicable regulatory agencies. Schematics and documentation are provided to assist customers with implementation or the creation of their own hardware designs. The development system includes an open source uClinuxTM embedded software BSP, complete with source code, GNU tools, kernel and broad collection of applications and drivers. A certified SIP telephony stack and audio subsystem is included with API, along with a device management middleware system. A host development board, power supply cable kit and manual are also included. Key ColdFire M53281KIT Features • Host board • M53281MOD Module • Video interface daughter card, audio headset, P&E BDM wiggler, power supply and GNU tools • VoIP and management software • All licenses for VoIP and management software use • Documentation and out-of-the-box VoIP demo • Part number: M53281KIT • Pricing: $749 (SRP) Key ColdFire M53281MOD Features • MCF53281CVM240 processor • 32 MB SDRAM and 16 MB NOR Flash • Ethernet PHY and CAN Transceiver • Audio codec/amplifier • VoIP and management software • All licenses for VoIP and management software use • Easy-to-integrate 50pin header or edge connector socket • Part number: M53281MOD • Pricing: $99 (SRP) at volume Key ColdFire MCF53281/ MCF53721 Features • V3 ColdFire core with EMAC offering up to 211 MIPS @ 240 MHz • 16 KB I/D cache and 32 KB SRAM • 16-bit DDR/32-bit SDR SDRAM controller • Integrated SVGA LCD controller (No LCD on MCF53721) • USB 2.0 low/full-speed host controller with on-chip transceivers • USB 2.0 low/full-speed On-The-Go controller with on-chip transceivers • 10/100 Fast Ethernet controller (FEC) • Enhanced CAN 2.0B controller • VoIP and management software • All licenses for VoIP and management software use • Part number: MCF53281CVM240 (256 MAPBGA) / MCF53721CVM240 (196 MAPBGA) • Pricing from: $12.94 (SRP) at volume Where to Go for Additional Information • M53281KIT Embedded VoIP Development Kit Webpage (design files, documentation and example code) • MCF532x Product Family Webpage (feature list, documentation, application notes) • ColdFire MCF53281 Reference Manual • Arcturus Networks, Inc.— Freescale Design Alliance Partner (www.arcturusnetworks.com) ColdFire M53281KIT ColdFire M53281MOD Ferric Chloride Etching Solution Description Ferric Chloride pellets for producing a solution for etching copper printed circuit boards and other metals. Preparation BEFORE HANDLING WEAR PROTECTIVE CLOTHING AND READ THE HEALTH AND SAFETY INFORMATION ON THE REAR OF THIS SHEET. For stainless steel, nickel and high nickel alloy use as supplied. For copper, brass and bronze use 30% water. Usage Use between 35ºC and 55ºC. For safe and efficient etching always use at the optimum temperature of approximately 45ºC in a Mega Temperature controlled etching tank. Part Numbers: 600-015 - 5 litres 600-016 - 25 litres Health and Safety Always wear protective clothing. Full Health and Safety details are on the rear of this instruction sheet. A report by an occupational hygienist concluded that under the test conditions, NO LOCAL VENTILATION IS REQUIRED using this etchant in Mega's PCB processing tanks. A copy of this report is available upon request. Ferric Stain Remover Stains left from drips or splashes of the etching solution can be removed with Mega's 600-039 Ferric Chloride Cleaner (1 Kg). Associated Products A range of associated products for use with this etchant are featured in our free product catalogue. Please telephone us for your free copy Mega Electronics Limited Mega House, Grip Industrial Estate, Linton, Cambridge, CB1 6NR. England. Telephone: +44 01223 893900 Fax: +44 01223 893894 email: sales@megauk.com Web: www.megauk.com E:6inst\ferric chloride etching solution (600-015-016).doc SECTION 1 PRODUCT IDENTIFICATION AND MANUFACTURE NAME: FERRIC CHLORIDE HEXAHYDRATE SOLUTION . PART NO: 600-015 5 Litres) 600-016 (25 Litres) (Molar aqueous solution) MANUFACTURER’S/SUPPLIERS NAME, REGISTERED ADDRESS AND EMERGENCY TEL NO: MEGA ELECTRONICS LTD., THE GRIP INDUSTRIAL ESTATE, LINTON, CAMBRIDGE. ENGLAND, CB1 6NR. TELEPHONE: +0044 01223 893900 ORGANISATIONS NAME & ADDRESS AT WHICH MANUFACTURED KEPETS GMBH. NORDSTRASSE 24 D-35641 SCHÖFFENGRUND LAUFDORF. GERMANY. TEL: 0049 064 45/50 23-4 SECTION 2 COMPOSITION/INFORMATION ON INGREDIENTS COMPONENT %BY WT CAS & EEC Nos.: HAZARD PHRASE NOS: FERRIC 100 N/A Xn R22, R36/38 CHLORIDE HEXAHYDRATE SECTION 3 HAZARDS IDENTIFICATION MAY BE CORROSIVE TO MUCOUS MEMBRANES, EYES AND SKIN. ITS EFFECTS ARE SIMILAR TO THOSE OF ANY CAUSTIC SUBSTANCE. THE ESTIMATED ONE TIME LETHAL DOSE FOR 70 kg MAN IS 30g. SECTION 4 FIRST AID MEASURES INHALATION: MOVE TO FRESH AIR AND KEEP AT REST. IF RECOVERY IS NOT RAPID, SEEK MEDICAL ATTENTION. SKIN CONTACT: REMOVE CONTAMINATED CLOTHING. WASH AFFECTED AREA WITH SOAP AND WATER. IF IRRITATION OCCURS AND PERSISTS, SEEK MEDICAL ATTENTION. EYE CONTACT: FLUSH WITH WATER FOR 15 MINUTES. SEEK MEDICAL ATTENTION INGESTION: RINSE MOUTH OUT WITH WATER. DO NOT INDUCE VOMITING. SEEK MEDICAL ATTENTION. MEDICAL NOTES: N/A SECTION 5 FIRE FIGHTING MEASURES EXTINGUISHING MEDIA NON FLAMMABLE, SO NO LIMITATIONS COMBUSTION PRODUCTS N/A FIRE/EXPLOSION SCENARIOS DECOMPOSES TO RELEASE CI AND HCI SPECIAL PROTECTIVE EQUIPMENT FOR FIRE FIGHTERS SELF CONTAINED BREATHING APPARATUS SHOULD BE WORN. SECTION 6 ACCIDENTAL RELEASE MEASURES PERSONAL PROTECTION REFER TO SECTION 8; PERSONAL PROTECTION ENVIRONMENTAL PRECAUTIONS . AVOID ENTRY INTO DRAINS & WATERWAYS. WORKPLACE PRECAUTIONS N/A METHODS FOR CLEARING UP: SWEEP AND GATHER PRODUCT; AVOID GENERATION OF DUST. SECTION 7 HANDLING AND STORAGE HANDLING PRECAUTIONS PREFERABLY HANDLE IN CONFINED SPACES. IF USING LARGE QUANTITIES, USE NON CORROSIVE EQUIPMENT. STORAGE INCLUDING ANY SPECIAL REQUIREMENTS (TEMPERATURE, VENTILATION, ETC) STORE IN COL DRY PLACE AWAY FROM CHILDREN AND FOODSTUFF. KEEP IN WELL VENTILATED AREA, AWAY FROM REACTIVE SUBSTANCES. SECTION 8 EXPOSURE CONTROL/PERSONAL PROTECTION ENGINEERING CONTROLS/ VENTILATION NORMAL GOOD ROOM VENTILATION SHOULD BE SUFFICIENT. RESPIRATORY PROTECTION N/A EYE PROTECTION RECOMMENDED SPLASHPROOF GOGGLES HAND PROTECTION RECOMMENDED IMPERVIOUS GLOVES e.g. NITRILE. SKIN PROTECTION RECOMMENDED IN FORM OF COVERALLS. SECTION 9 PHYSICAL AND CHEMICAL PROPERTIES THE INFORMATION AND RECOMMENDATIONS CONTAINED HEREIN ARE BELIEVED TO BE ACCURATE - HOWEVER NO GUARANTEE OR WARRANTY EXPRESSED OR IMPLIED IS GIVEN APPEARANCE: ODOURLESS LIQUID COLOUR: DEEP AMBER ODOUR: NONE ACIDITY/ALKALINITY pH: 2.0 BOILING POINT 111ºC MELTING POINT ºC: FLASH POINT ºC (Open/Closed Cup): N.A. AUTOIGNITION TEMP ºC: N.A. THERMAL DECOMPOSITION TEMP ºC :WHEN STRONGLY HEATED WILL LIBERATE HYDROGEN CHLORIDE OXIDISING PROPERTIES: EXPLOSIVE PROPERTIES: NON FLAMMABLE EXPLOSIVE LIMITS AT 25ºC (% VOL IN AIR) LOWER: UPPER: RELATIVE DENSITY: 1.45g/ml SOLID CONTENT %: SOLUBILITY IN WATER: COMPLETELY IN WATER INSOLUBILITY IN ALCOHOL, ETHER AND ACETONE. VOLATILE CONTENT: AVOID CONTACT WITH STRONG ACIDS, ALKALIS, OXIDISERS VAPOUR PRESSURE mmHg at 20ºC RELATIVE VAPOUR DENSITY (air = 1): (of principle component and name): EVAPORATION RATE CONDUCTIVITY: (n-butyl acetate = 1): SECTION 10 STABILITY AND REACTIVITY PROPERTIES CONDITIONS TO AVOID: NONE MATERIALS TO AVOID: SOLUTIONS OF FERRIC CHLORIDE ACT AS AN ACID AND ARE POWERFUL OXIDISING AGENTS, DISSOLVING THE MAJORITY OF METALS (Cu, Ni, Sn, Pb, Mn, Fe, Co, etc) HAZARDOUS DECOMPOSITION PRODUCTS: INCLUDE DI AND HCI HAZARDOUS POLYMERISATION WILL NOT OCCUR SECTION 11 TOXICOLOGICAL INFORMATION EFFECT OF EYE CONTACT: IRRITATION, TEARING, REDNESS, RISK OF BURNS. EFFECT OF SKIN CONTACT: IRRITATION WHEN IN CONTACT WITH DAMP SKIN. RISK OF BURNS, RISK OF DERMATITIS AFTER REPEATED CONTACT. PERSISTENT PIGMENTATION OF SKIN ON REPEATED CONTACT. EFFECT OF INHALATION: IRRITATION OF NOSE AND THROAT. COUGHING AND DIFFICULTY BREATHING AFTER PROLONGED OR REPEATED EXPOSURE. ULCERATION OF THE NOSE AND BROWN STAINING OF THE TEETH. EFFECT OF INGESTION: LOW PROBABILITY OF RISK DUE TO ACRID TASTE. IRRITATION AND BURNS TO MOUTH, THROAT AND STOMACH. NAUSEA, VOMITING, STOMACH CRAMPS SHOCK. LD50 (ORAL HUMAN):30g / 70kg (est.) LD50 (ORAL RAT): 900mg / kg. LD50 (ORAL MOUSE):440mg / kg. SECTION 12 ECOLOGICAL INFORMATION Possible environmental effects and behaviour/ODP/aquatic toxicity. EC50 (DAPHNIA): 7.3mg / 1 (iron) LC50 (FISH): 26mg / 1 (iron) ODP: N.A. - No other data available. SECTION 13 DISPOSAL CONSIDERATIONS Safe disposal of product, its residues and packaging materials: In accordance with local regulations via licensed contractor. May be neutralised to neutral pH. Dispose in a controlled landfill site. See also Sections 7 & 8 for handling precautions and personal protection where applicable. SECTION 14 TRANSPORT INFORMATION Not restricted SECTION 15 REGULATORY INFORMATION INDICATION OF DANGER: BLACK St. ANDREW’S CROSS, HARMFUL CONTAINS: FERRIC CHLORIDE HEXAHYDRATE RISK PHRASE Nos. & WORDS: R22 Harmful if swallowed R36/38 Irritating to eyes and skin. SAFETY PHRASE Nos. & WORDS: S2 Keep out of reach of children S26 In case of contact with eyes / rinse immediately with plenty of water and seek medical advice S37/39 Wear suitable protective clothing, gloves and eye / face protection OTHER INFORMATION RECOMMENDED USES AND RESTRICTIONS: Use only as directed. CC2560 Bluetooth® single-chip solution Product Bulletin The CC2560 from Texas Instruments is a complete Bluetooth Host Controller Interface (HCI) solution enabling ease of design as well as decreased time to market for Bluetoothenabled devices in medical, industrial and consumer electronics applications. Based on TI’s seventh-generation Bluetooth core, the CC2560 brings a product-proven solution that supports the Bluetooth 2.1 + EDR release, while the CC2564 is upgradable to Bluetooth Version 3.0 and Bluetooth low energy Version 4.0. The CC2560 is the industry’s first Bluetooth solution manufactured with TI’s cutting-edge 65-nm CMOS process and DRP technology, delivering the industry’s smallest single-chip solution along with low power and cost. • Based on TI’s cutting-edge 65-nm CMOS process and DRP technology, delivering the industry’s smallest Bluetooth single-chip solution along with low power and cost • Supports Bluetooth 2.1 + EDR release (CC2564 upgradable to Bluetooth Version 3.0 and Bluetooth Low Energy (BLE) Version 4.0) • Flexibility for easy Bluetooth stack integration and validation into various microcontrollers, such as Stellaris® and low-end MSP430™ microcontrollers • Best-in-class Bluetooth RF performance (Tx power, Rx sensitivity, blocking) • Enhanced performance: - Improved Bluetooth link robustness supports power levels of Bluetooth Class 2 devices with increased output power capabilities - Improved adaptive frequency hopping algorithm with minimum adoption time Overview Key benefits Audio processor Bluetooth® processor Modem DRP 2.4 GHz filter CC2560 I/O I/F HCI Power management Clock management Power Shutdown Slow clock Fast clock PCM/I2S Bluetooth® RF UART I2C CC2560 Bluetooth single-chip solution Advanced power management hardware and software algorithms provide significant power savings in the most commonly used Bluetooth modes of operation: active, page and inquiry scans. RF performance The CC2560 offers best-in-class Bluetooth RF performance for Tx power, Rx sensitivity and blocking. In addition, internal temperature detection and compensation ensures minimal variation in RF performance over temperature. The CC2560 RF transmitter is capable of receiving -95 dBm or transmitting up to +12 dBm (with level control) without the need for external power amplifiers or a Tx/Rx switch. © 2010 Texas Instruments Incorporated The platform bar, MSP430 and Stellaris are trademarks of Texas Instruments. The Bluetooth word mark and logos are owned by the Bluetooth SIG, Inc., and any use of such marks by Texas Instruments is under license. All other trademarks are the property of their respective owners. SLYT377 Physical interfaces TI’s CC2560 offers flexible interfaces for easy integration into various host systems. These interfaces include: • Standard HCI over H4 UART with a maximum rate of 4 Mbps • Flexible pulse code modulation and I2S digital audio/voice interfaces: - Full flexibility of data format (linear, A-law, μ-law), data width, data order, sampling and slot positioning, master/slave modes, and high clock rates up to 15 MHz for slave mode or 4.096 MHz for master mode - Lost packet concealment for improved audio • I2C to external EEPROM, which can be used for storing application-specific scripts. Evaluation and development tools To start developing today with the CC2560 Bluetooth solution, TI offers two evaluation and development options: • eZ430-RF2560: a complete, low-cost TI Bluetooth evaluation and software development tool in a convenient USB stick See www.ti.com/ez430-rf2560-pb • PAN1315 evaluation module kit (EMK): an advanced connectivity board based on Panasonic’s PAN1315 Bluetooth module with direct connection to the MSP-EXP430F5438 experimenter board to take advantage of MSP430F5438 peripherals. See www.ti.com/pan1315-pb B042210 Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringement of patents. The publication of information regarding any other company’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Parameter Value Condition/notes Power supply voltage 1.7 to 4.8 V Battery or DC to DC Operating ambient temperature range -40 to 85C Industrial temperature range Output power +12 dBm GFSK, typical Receiver sensitivity -95 dBm GFSK, typical, dirty Tx on Shut-down current 1 μA Typical Deep sleep current 40 μA Typical Ultra-low-power scan 135 μA 1.28-second interval EDR full throughput 39.2 mA Tx = 3-DH1, Rx = 3-DH5 eSCO 8.3 mA 2-EV3 64 Kbps, no retransmission Technical Specifications Key benefits • Advanced power management for extended battery life and ease of design: - On-chip power management, including direct connection to battery or DC to DC - Low power consumption for active, standby and scan Bluetooth modes - Proprietary low-power scan algorithm achieves page and inquiry scans at one-third the normal power - Shut-down and sleep modes to minimize power consumption when Bluetooth is not used • Flexible clock management interface with support for: - Automatic fast-clock detection mechanism - Frequency adjustment to offset and drift IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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The Analog Discovery is small enough to fit in your pocket and costs less than a textbook, but it is powerful enough to replace a stack of lab equipment. Powered by a Hi-Speed USB port and the free WaveForms software, the Analog Discovery lets you build and test analog and digital circuits outside of the lab. Designed in cooperation with: Powered by WaveForms™ Circuit Note CN-0326 Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0326. Devices Connected/Referenced AD7793 3-Channel, Low Noise, Low Power, 24-Bit Sigma Delta ADC ADuM5401 Quad-Channel Isolators with Integrated DC/DC Converter AD8603 MicroPower RRIO Low Noise Precision Single CMOS Op Amp Isolated Low Power pH Monitor with Temperature Compensation Rev. 0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. EVALUATION AND DESIGN SUPPORT Circuit Evaluation Boards CN0326 Evaluation Board (EVAL-CN0326-PMDZ) System Demonstration Platform (EVAL-SDP-CB1Z) SDP PMOD Interposer Board (SDP-PMD-IB1Z) Design and Integration Files Schematics, Layout Files, Bill of Materials CIRCUIT FUNCTION AND BENEFITS The circuit shown in Figure 1 is a completely isolated low power pH sensor signal conditioner and digitizer with automatic temperature compensation for high accuracy. The circuit gives 0.5% accurate readings for pH values from 0 to 14 with greater than 14-bits of noise-free code resolution and is suitable for a variety of industrial applications such as chemical, food processing, water, and wastewater analysis. This circuit supports a wide variety of pH sensors that have very high internal resistance that can range from 1 MΩ to several GΩ, and digital signal and power isolation provides immunity to noise and transient voltages often encountered in harsh industrial environments. Figure 1. pH Sensor Circuit (Simplified Schematic: All Connections and Decoupling Not Shown) AD7793GNDISOGND1VISOVDD1VOAVOBVOCVIDVIAVIBVICVODAIN1(+)AIN1(–)AIN2(+)AIN2(–)RFIN(+)/AIN3(+)RFIN(–)/AIN3(–)CSSCLKDINDOUT/RDYGNDDVDDAVDDpH SENSORIOUT2CSSCLKDINDOUT/RDY3.3V3.3VISO3.3VISO3.3VISOGNDISO10kΩ10kΩ10kΩ1μF1μF1μF5kΩTOPt1000RTDP1J11MΩAD8603FERRITE BEAD:MURATA BLM21PG331SN1DBEADADUM5401210μA11821-001 Circuit Note CN-0287 Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0287. Devices Connected/Referenced AD7193 4-Channel, 4.8 kHz, Ultralow Noise, 24- ADT7310 ±0.5°C Accurate, 16-Bit Digital SPI Temperature Sensor. AD8603 Precision Micropower, Low Noise CMOS R-to-R Input/Output ADR3440 4.096V, Micropower High Accuracy Voltage Reference. ADG738 CMOS, Low Voltage, 3-Wire Serially- Controlled, Matrix Switch. ADG702 CMOS Low Voltage 2 Ω SPST Switch. AD5201 33-Position Digital Potentiometer ADuM1280 3 kV RMS Dual Channel Digital Isolators ADuM5401 Quad-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter Isolated 4-Channel, Thermocouple/RTD Temperature Measurement System with 0.5°C Accuracy Rev. A Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. EVALUATION AND DESIGN SUPPORT Circuit Evaluation Boards CN-0287 Circuit Evaluation Board (EVAL-CN0287-SDPZ) System Demonstration Platform (EVAL-SDP-CB1Z) Design and Integration Files Schematics, Layout Files, Bill of Materials CIRCUIT FUNCTION AND BENEFITS The circuit shown in Figure 1 is a completely isolated 4-channel temperature measurement circuit optimized for performance, input flexibility, robustness, and low cost. It supports all types of thermocouples with cold junction compensation and any type of RTD (resistance temperature detector) with resistances up to 4 kΩ for 2-, 3-, or 4-wire connection configurations. The RTD excitation current are is programmable for optimum noise and linearity performance. RTD measurements achieve 0.1°C accuracy (typical), and Type-K thermocouple measurements achieve 0.05°C typical accuracy because of the 16-bit ADT7310 digital temperature sensor used for cold-junction compensation. The circuit uses a four-channel AD7193 24-bit sigma-delta ADC with on-chip PGA for high accuracy and low noise. Input transient and overvoltage protection are provided by low leakage transient voltage supressors (TVS) and Schottky diodes. The SPI-compatible digital inputs and outputs are isolated (2500 V rms), and the circuit is operated on a fully isolated power supply. CN-0287 Circuit Note Rev. A | Page 2 of 9 Figure 1. 4-Channel Thermocouple and RTD Circuit (Simplified Schematic: All Connections and Decoupling Not Shown) CIRCUIT DESCRIPTION Temperature Measurement Introduction Thermocouples and RTDs (resistance temperature detectors) are the most frequently used sensors for temperature measurement in industrial applications. Thermocouples are able to measure very high temperatures up to about +2300°C and also have a fast response time (measured in fractions of a second). RTDs are capable of higher accuracy and stability than thermocouples, and the resistance of long wire lengths (hundreds of meters) to a remote RTD can be compensated for with 3- or 4-wire connections. A thermocouple consists of two wires of different metals joined at one end. This end is placed at the temperature which is to be measured, refered to as the measurement junction. The other end is connected to a precision voltage measurement unit, and this connection is referred to as the reference junction or alternately the cold junction. The temperature difference between the measurement junction and the cold junction generates a voltage AD7193REFIN2(–)REFIN2(+)AIN8AIN7AIN2AIN11.69kΩ1.69kΩ+5V300Ω300Ω300Ω300Ω300Ω1nF1nF+5V+5V27nF1nF1nF+5V+5V+5V+5V+5V+5V27nFDSINADG7021kΩR3C2C2C2S1S2S7S8SCLKDDINSYNCADG738DOUTPWR-ONPRESETAWBSHDNVDDVSSCSCLKSDIGNDAD5201LOGICCONTROL+5V+4.096VP2 P3ADR3440VOUTFORCESENSEFORCESENSEGND+5VREFIN1(+)REFIN1(0)+4.096VAD8603ADT7310SCLKDOUTDINCTINTSCLKDOUTDINCTINTCOLD JUNCTIONCOMPENSATIONSCLKGNDCSADT7310_CSSCLKDINADG738_CSSCLKDOUTDINCSSCLKSCLKDOUTDOUTDINDINAD7193_CSDGNDAGND+5VSCLKDIN+5V+5VV–V+0.1μF10μF+5VAINCOMAIN4AIN3AIN6AIN5JP1JP4ADuM5401AD7193_CSAD7193_CSISOGND1GNDISOGNDISOGNDISODINISOSCLKISODOUTISOGNDISO+5VISOVDD1VDD1VISOGND2VDD2VIAVIBVOAVOBGND2GND1VDD2GND1VDD1VOAVOAVOAVOCVIDVIAVIBVICVODVOBVIAVIBADuM1280+5V+5VISO+5V+5VISO+5VCTINTCTISOINTISOADuM1280ADT7310_CSADG738_CSADT7310_CSISOADG738_CSISO+5VRTD 4WTC, RTD 2,3WRTD 4WTC, RTD 2,3WCH 1CH 44.02kΩ0.1%10ppm+5V5.6VZENER DIODE0Ω:ANALOG GROUND: DIGITAL GROUNDDVDDAVDD10926-001 Circuit Note CN-0287 Rev. A | Page 3 of 9 (known as the Seebeck effect voltage) that is related to the difference between the temperatures of the two junctions. The signal generated is typically from several microvolts to tens of millivolt depending on the temperature difference. For example, K-type thermocouples are capable of measuring −200°C to +1350°C with an output range of approximately −10 mV to +60 mV. It is important for the signal chain to maintain as high impedance and low leakage as possible to achieve the highest accuracy for the voltage measurement. In order to convert this voltage to an absolute temperature, the cold junction temperature must be accurately known. Traditionally 1°C to 2°C has been considered sufficient, although since the cold junction measurement error contributes directly to the absolute temperature error, a higher accuracy cold junction temperature measurement is beneficial An RTD is made from a pure material, such as platinum, nickel or copper, that has a predictable change in resistance as the temperature changes.The most widely used RTD is platinum (Pt100 and Pt1000). One method used to accurately measure the resistance is to measure the voltage across the RTD generated by a constant current source. Errors in the current source can be cancelled by referring the measurement to the voltage generated across a reference resistor that is driven with the same current (i.e. a ratiometric measurement). Minimizing the leakage current through the current path is important for achieving high accuracy because the excitation current is typically only a few hundred microamps to prevent self heating. For the industrial field applications both high performance as well as protection against both high-voltage transient events and dc over-voltage conditions are important design considerations. How this Circuit Works The circuit shown in Figure 1 is designed for precision temperature measurement applications in the industrial field environment and is optimized for flexibility, performance, robustness, and cost. This circuit uses the AD7193, low noise, 24-bit sigma-delta ADC to ensure high resolution and linearity for the entire circuit. The AD5201, 33-position digital potentiometer, AD8603 op amp, and ADG702 single channel switch constitute a simple programmable current source and bias voltage buffer for the RTD and thermocouple measurements. The ADG738 routes the current source to the active RTD channel and allows wire resistance compensation for the 3-W RTD configuration. The ADT7310 digital SPI temperature sensor has ±0.8°C maximum accuracy (+5 V supply) from −40°C to +105°C and is used for cold-junction compensation for the thermocouple measurement. The ADR3440 is a low noise and high accuracy 4.096 V reference connected to REFIN1(+)/REFIN1(−) of the AD7193 for the thermocouple measurements. Analog-to-Digital Converter The AD7193 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). This ADC achieves high resolution, low non-linearity, and low noise performance as well as very high 50 Hz/60 Hz rejection. The data output rate can be varied from 4.7 Hz (24 bits effective resolution, Gain = 1), to 4.8 kHz (18.6 bits effective resolution, Gain = 1). The on-chip low noise PGA amplifies the small differential signal from the thermocouple or RTD with a gain programmable from 1 up to 128, thereby allowing a direct interface. The gain stage buffer has high input impedance and limits the input leakage current to ± 3 nA maximum. The gain of theAD7193 must be configured properly depending on the temperature range and type of sensors. The on-chip multiplexer allows four differential input channels to be shared with the same ADC core, saving both space and cost. Programmable Current Source for RTDs and Bias Voltage Generator Circuit for Thermocouples RTD measurements require a low noise current source that drives the RTD and a reference resistor. Thermocouple measurements, on the other hand, need a common-mode bias voltage that shifts the small thermocouple voltage into the input range of the AD7193. The circuit shown in Figure 2 meets both requirements and utilizes the AD8603 a low noise CMOS rail-to-rail input/output op amp with only 1 pA maximum input bias current and 50 μV maximum offset voltage, combined with the ADG702 single channel, CMOS low voltage 2 Ω SPST switch, and the ADG738 eight-channel matrix switch. Figure 2. External Programmable Current Source and Bias Voltage Generator With the ADG738 opened and the ADG702 closed, the AD8603 acts as a low noise, low output impedance unity-gain buffer for the thermocouple application. The voltage from the AD5201 digital potentiometer is buffered and is used for the thermocouple common-mode voltage, usually 2.5 V, which is one-half the supply voltage. The 33-position AD5201 digital AD7193REFIN2(–)REFIN2(+)AIN2AIN1DSADG7021kΩR3C2DS1ADG738AWBAD5201+4.096VAD8603+5VRTDTCVWIEXCIEXC=VWRREFRREF10926-002 CN-0287 Circuit Note Rev. A | Page 4 of 9 potentiometer is driven with the ADR3440 low drift (5 ppm/°C) 4.096 V reference for accuracy. With the ADG738 closed and the ADG702 opened, the AD8603 generates the RTD excitation current, IEXC = VW/RREF. Temperature measurement is a high precision and low speed application, therefore there is adequate settling time available to switch the single current source between all 4 channels, providing excellent channel-to-channel matching, low cost, and small PCB footprint. The ADG738 is an 8-to-1 multiplexer that switches the current source between channels. In order to support the 2-, 3-, and 4-wire RTD configurations, each of the four channels need two switches. In many applications, the RTD may be located remotely from the measurement circuit. The resistance from the long lead wires can generate large errors, especially for low resistance RTDs. In order to minimize the effect of the lead resistance, a 3-wire RTD configuration is supported as shown in Figure 3. Figure 3. Connector and Jumper Configuration for3-Wire RTD Sensor With S1 of the ADG738 closed and S2 opened, the voltage at the input of AD7193 is V1. With S1 opened and S2 closed, the voltage on the input of AD7193 is V2, The voltage across the RTD sensor is VRTD, the exciting current from the current source is IEXC. V1 and V2 contain the error generated by the lead resistance as shown below: EXCW3RTD1IRRV×+=)( (1) EXCW3RTDW22IRRRV×++=)( (2) EXCRTDRTDIRV×= (3) Assuming RW1 = RW2 = RW3 and combining Equations 1, 2, and 3 yields: VRTD = 2V1 – V2 (4) RRTD = VRTD/IEXC = (2V1 – V2)/IEXC (5) Equation 5 shows that the 3-wire configuration requires two separate measurements (V1 and V2) in order to calculate RRTD, thereby decreasing the output data rate. In most applications this is not a problem. The 4-wire RTD connection requires two extra sense lines, but is insensitive to wiring resistances and only requires one measurement. Figure 4 summarizes the connector configuration and jumper placements for RTD 2-wire, RTD 3-wire, RTD 4-wire, and thermocouple applications. Figure 4. Connector Configuration and Jumper Placements for EVAL-CN0287-SDPZ Board AD7193REFIN2(-)REFIN2(+)AIN2AIN1S1DADG738RTDIEXCIEXCS2JP[x]+5VRRTDRREFRW1RW2RW3CURRENT SOURCE+5V10926-003RTD2-WIRERTD3-WIRERTD4-WIRETHERMOCOUPLEJPx2132134CNxRTDRTDJPx2132134CNxJPx2132134CNxJPx2132134CNxTC+–RTD10926-004 Circuit Note CN-0287 Rev. A | Page 5 of 9 Protection Circuits Transient and overvoltage conditions are possible both during manufacturing and in the field. To achieve a high level of protection, additional external protection circuitry is necessary to compliment the IC’s internal integrated protection circuitry. The external protection adds additional capacitance, resistance, and leakage. These effects should be carefully considered to achieve a high level of accuracy. The additional protection circuitry is shown in Figure 5. Figure 5. Transient and Overvoltage Protection Circuit Leakage currents can have a significant effect on RTD measurements so should be carefully considered. Leakage currents can also create some error in thermocouple measurements in the case where long thermocouple leads have significant resistance. In this circuit, the PTVS30VP1UP transient voltage suppressor (TVS) quickly clamps any transient voltages to 30 V with only 1 nA typical leakage current at 25°C. A 30 V TVS was chosen to allow for a 30 V dc overvoltage. A 1.69 kΩ resistor followed by low leakage BAV199LT1G Schottky diodes are used to clamp the voltage to the 5 V power rail during transient and dc overvoltage events. The 1.69 kΩ resistor limits the current through the external diodes to about 15 mA during a 30 V dc overvoltage condition. In order to ensure the power rail is able to sink this current, a Zener diode is used to clamp the power rail to ensure it does not exceed the absolute maximum rating of any of the IC’s connected to the supply. The 5.6 V Zener diode (NZH5V6B) is selected for this purpose. A 300 Ω resistor limits any further current that could flow into the AD7193 or the ADG738. Isolation The ADuM5401 and the ADuM1280 use ADI iCoupler® technology provide 2500 V rms isolation voltage between the measurement side and the controller side of the circuit. The ADuM5401 also provides the isolated power for measurement side of the circuit. The isoPower technique used in the ADuM5401 uses high frequency switching elements to transfer power through a transformer. Special care must be taken with the printed circuit board (PCB) layout to meet emissions standards. Refer to AN-0971 Application Note for board layout recommendations. Thermocouple Configuration Test Results The performance of the circuit is highly dependent on the sensor and the configuration of the AD7193. The Type-K thermocouple output varies from −10 mV to +60 mV, corresponding to −200°C to +1350°C. The AD7193 PGA is configured for G = 32. The voltage swing out of the PGA is −320 mV to +1.92 V, or 2.24 V p-p. With chop enabled, 50 Hz/60Hz noise reduction enabled, and filter word FS[9:0] = 96, the noise distribution histogram for 1024 samples is shown in Figure 6. Figure 6. Noise Distribution Histogram of CN-0287 (VDD = 5 V, VREF = 4.096 V, Differential Input, Bipolar, Input Buffer Enable, Output Data rate = 50 Hz, Gain = 32, Chop Enable, 60 Hz Rejection Enable, Sinc4) The resolution of the AD7193 is 24 bits, or 224 = 16,777,216 codes. The full dynamic range of the AD7193 is 2 × VREF = 2 × 4.096 V = 8.192 V. The output voltage of the thermocouple after the PGA is only 2.24 V p-p and does not occupy all the dynamic range of the AD7193. Therefore the range of the system is decreased by a factor of 2.24 V/8.192V. The noise distribution is about 40 codes peak-to-peak. The noise-free code resolution over the 2.24 Vp-p range of measurement is given by: bits8.16V192.8V24.2400216,777,16log2=×=ResolutionFreeNoise (6) The full-scale temperature range of the Type-K thermocouple is −200°C to +1350°C, or 1550°C p-p. The 16.8 bits of noise-free code resolution therefore corresponds to 0.013°C of noise-free temperature resolution. +5V1.69kΩTVS30V, 600WPTVS30VP1UP300ΩOVERVOLTAGEUP TO 30VSCHOTTKY DIODESBAV199LT1G+5V15mA+6V,−1VADCINPUT+5.3V,−0.3V3mA5.6V ZENER DIODENZH5V6B10926-00511010090807060NUMBER OF OCCURENCESNUMBER OF OCCURENCES5040302010838851083885158388520838852583885308388535838854083885458388550010926-006 CN-0287 Circuit Note Rev. A | Page 6 of 9 Thermocouple Measurement Linearity Figure 7 shows the approximate linearity of the type K thermocouple system. The “cold junction” temperature is 0°C in this plot. Figure 7. Type K Thermocouple Temperature vs. Output Voltage with 0°C Cold-Junction The precision voltage for calibration as well as testing is provided by the Fluke 5700A Calibrator high precision dc voltage source with a resolution of 10 nV. The voltage error in Figure 8 is within 0.2 μV of ideal, corresponding to about 0.004°C. This result is the short time accuracy result just after a system calibration at 25°C without the effects of temperature drift.The dominant error for this circuit is from the cold-junction compensation measurement. In this circuit the ADT7310 is used for cold-junction compensation and has a typical error of −0.05°C, and a worst case error of ±0.8°C over the −40°C to +105°C temperature range for a 5 V supply. The device has a ±0.4°C maximum error over this temperature range if a 3 V supply is used. Figure 8. Error of CN-0287 Configured for Type K Thermocouple (VDD = 5 V, VREF = 4.096 V, Differential Input, Bipolar, Input Buffer Enable, Output Data Rate = 50 Hz, Gain = 32, Chop Enable. 60 Hz Rejection Enable, Sinc4) RTD Configuration Test Results For a Pt100 RTD, the default ADC gain setting is G = 8, and for a Pt1000 RTD the default gain setting is G = 1. The reference voltage to the ADC is equal to the voltage across the 4.02 kΩ reference resistor. The temperature coefficient of a Pt100 RTD is approximately 0.385 Ω/°C, and at +850°C the resistance can be as high as 400 Ω. With a 400 μA default excitation current, the maximum RTD voltage is therefore about 160 mV. The reference voltage to the ADC is 4.02 kΩ × 400 μA = 1.608 V. For G = 8, the maximum RTD voltage is 160 mV × 8 = 1.28 V which is approximately 80% of the available range. For a Pt1000 RTD, the maximum resistance at +850°C is approximately 4000 Ω. The default excitation current is 380 μA, yielding a maximum RTD voltage of 1.52 V. The reference voltage to the ADC is 4.02 kΩ × 380 μA = 1.53 V. A default gain setting of G = 1 is used, and the maximum RTD voltage utilizes nearly all of the available range. The general expression for the RTD resistance, R, in terms of the ADC code (Code), resolution (N), reference resistor (RREF), and gain (G) is given by: =GRCodeRREFN2 (7) The leakage current from TVS, diodes, clamping diodes, and ADC are the largest sources of errors in the RTD measurement circuit, even though nanoamp devices were selected for the design. The total leakage current for each of the inputs is 9 nA (3 nA from AD7193, buffer on), 5 nA from clamping diode and 1 nA from the TVS diode). All four channels will thus generate 36 nA maximum leakage current. The feedback loop in Figure 2 maintains a constant current through the reference resistor. This means that leakage currents affect the RTD excitation current, thereby producing an error. The default exciting current is 400 μA for Pt100 and 380 μA for Pt1000. The approximate worst case system error due to the leakage currents for Pt100 RTDs is: readingofError(%)%01.0100μA400nA63≈×= (8) For a Pt100 with measurable range from −200°C to +850°C, this corresponds to a system accuracy of approximately C1.00001.0C/385.0400(≈×ΩΩ=)CAccuracy (9) The amount of the error depends on the configuration of the input terminals. After an input configuration is established, a room temperature calibration can reduce the error even further. An experiment was conducted to show the effects of leakage current. Each channel was first configured as a 4-W RTD. A 100 Ω fixed resistor was connected to Channel 1 in the RTD position. Zero ohm resistors were connected to the inputs of the other three channels. 6050–5000500TEMPERATURE (°C)VOLTAGE (mV)10001500403020100–1010926-0070.200.150.0516111621263136414651INPUT VOLTAGE (mV)VOLTAGE ERROR (μV)0.100 10926-008 Circuit Note CN-0287 Rev. A | Page 7 of 9 The gain was set for G = 1, and the excitation current for 380 μA (Pt1000 configuration). Data was collected, then the jumpers connecting Channel 4, Channel 3, and Channel 2 were removed sequentially, and data collected for each condition. The results are shown in Figure 9. Figure 9. Error Generated by Leakage Current on Channel 1 for 4-Channel Pt100 RTD with G = 1 The ADC code changed from approximately 437,800 to 437,600 corresponding to a measurement change of 104.9015 Ω to 104.8627, or 0.0388 Ω. This represents a measurement error of approximately 0.1°C; however it can be removed by calibrating at room temperature with a fixed input configuration. COMMON VARIATIONS The AD779x low noise, low power, 16-/24-bit sigma-delta ADC family is more suitable for signal channel or low power applications. The ADT7311, ±0.5°C accurate, 16-bit digital SPI temperature sensor is qualified for automotive applications. The cold junction compensation circuit accuracy can be improved by using a digital temperature sensor, such as ADT7320, with ±0.25°C accuracy. RMS isolation up to 5 kV is be available in the ADuM6401 digital isolator with dc-to-dc converter. CIRCUIT EVALUATION AND TEST This circuit uses the EVAL-CN0287-SDPZ circuit board and the SDP-B (EVAL-SDP-CB1Z) system demonstration platform controller board. The two boards have 120-pin mating connectors, allowing for the quick setup and evaluation of the performance of the circuit. The EVAL-CN0287-SDPZ board contains the circuit to be evaluated, as described in this note, and the SDP-B controller board is used with the CN0287 Evaluation Software to capture the data from the EVAL-CN0287-SDPZ circuit board. Equipment Needed The following equipment is needed: • A PC with a USB port and Windows® XP (32 bit), Windows Vista®, or Windows® 7 • The EVAL-CN0287-SDPZ circuit board • The EVAL-SDP-CB1Z SDP-B controller board • The CN-0287 SDP Evaluation Software • The EVAL-CFTL-6V-PWRZ dc power supply or equivalent 6 V/1 A bench supply • A RTD or thermocouple sensor or sensor simulator. (The evaluation software supports the following RTDs: Pt100, Pt1000; Thermocouple: Type K, Type J, Type T, Type S.) Getting Started Install the evaluation software by placing the CN0287 Evaluation Software into the CD drive of the PC. Using My Computer, locate the drive that contains the evaluation software. Functional Block Diagram See Figure 1 for the circuit block diagram and the EVAL-CN0287-SDPZ-PADSSchematic.pdf file for the complete circuit schematic. This file is contained in the CN0287 Design Support Package located at www.analog.com/CN0287-DesignSupport A functional block diagram of the test setup is shown in Figure 10. Figure 10. Test Setup Functional Block Diagram Setup Connect the 120-pin connector on the EVAL-CN0287-SDPZ circuit board to the CON A connector on the EVAL-SDP-CB1Z controller board (SDP-B). Use nylon hardware to firmly secure the two boards, using the holes provided at the ends of the 120-pin connectors. With power to the supply off, connect a 6 V power supply to the +6 V and GND pins on the board. If available, a 6 V wall wart can be connected to the barrel connector J2 on the board and used in place of the 6 V power supply. Connect the USB cable supplied with the SDP-B board to the USB port on the PC. Do not connect the USB cable to the Mini-USB connector on the SDP-B board at this time. Turn on the 6 V power supply to power up the evaluation board and SDP board, then plug in the Mini-USB cable into the Mini-USB port on the SDP board. 43786043784043776043782043778043780043774043772043770043768043766043764043762043760043758010926-009ALLLEAKAGEINCLUDEDLEAKAGEFROM CH4REMOVEDLEAKAGEFROM CH3REMOVEDLEAKAGEFROM CH2REMOVEDSENSORSEVAL-CFTL-6V-PWRZ6VWALLWARTCN(x)JP(x)(x) = 1, 2, 3, 4EVAL-CN0287-SDPZBOARDCN5 OR J2120PINSUSB CABLEUSBEVAL-SDP-CB1ZSDP BOARDPCSDPCONNECTORORSIGNALGENERATORS1.000V10926-010 CN-0287 Circuit Note Rev. A | Page 8 of 9 Test Launch the evaluation software. After USB communications are established, the SDP-B board can be used to send, receive, and capture data from the EVAL-CN0287-SDPZ board. Figure 11 shows a photo of the EVAL-CN0287-SDPZ evaluation board connected to the SDP board. Information regarding the SDP-B board can be found in the SDP-B User Guide. Information and details regarding test setup and calibration, and how to use the evaluation software for data capture can be found in the CN-0287 Software User Guide. Connectivity for Prototype Development The EVAL-CN0287-SDPZ evaluation board is designed to use the EVAL-SDP-CB1Z SDP-B board; however, any microprocessor can be used to interface to the SPI interface through the PMOD connector J6. The pin definition of PMOD connector can be found in the schematics of CN0287 evaluation board in CN0287 Design Support Package. In order for another controller to be used with the EVAL-CN0287-SDPZ evaluation board, software must be developed by a third party. Figure 11. EVAL-CN0287-SDPZ Evaluation Board Connected to the EVAL-SDP-CB1Z SDP-B Board 10926-011 CN-0287 Circuit Note Rev. A | Page 9 of 9 LEARN MORE CN0287 Design Support Package: www.analog.com/CN0287-DesignSupport SDP-B User Guide AN-880 Application Note, ADC Requirements for Temperature Measurement AN-892 Application Note, Temperature Measurement Theory and Practical Techniques. AN-0970 Application Note, RTD Interfacing and Linearization Using an ADuC706x Microcontroller CN0172, High Accuracy Multichannel Thermocouple Measurement Solution. CN0206, Complete Type T Thermocouple Measurement System with Cold Junction Compensation. CN0209, Fully Programmable Universal Analog Front End for Process Control Applications. CN 0221, USB-Based Temperature Monitor Using the ADuCM360 Precision Analog Microcontroller and an External Thermocouple. CN0271, K-Type Thermocouple Measurement System with Integrated Cold Junction Compensation. Kester, Walt. 1999. Sensor Signal Conditioning. Analog Devices. Chapter 7, "Temperature Sensors." Matthew Duff and Joseph Towey. Two Ways to Measure Temperature Using Thermocouples Feature Simplicity, Accuracy, and Flexibility, Analog Dialogue 44-10, Analog Devices. Mary McCarthy, AN-615 Application Note, Peak-to-Peak Resolution Versus Effective Resolution. MT-049 Tutorial, Op Amp Total Output Noise Calculations for Single-Pole System. MT-004 Tutorial, The Good, the Bad, and the Ugly Aspects of ADC Input Noise—Is No Noise Good Noise? Analog Devices. MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of “AGND” and “DGND”, Analog Devices. MT-035, Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail Issues, Analog Devices. MT-101 Tutorial, Decoupling Techniques, Analog Devices. Data Sheets and Evaluation Boards CN-0287 Circuit Evaluation Board (EVAL-CN0287-SDPZ) System Demonstration Platform (EVAL-SDP-CB1Z) AD7193 Datasheet AD8603 Datasheet ADG738 Datasheet ADG702 Datasheet ADT7310 Datasheet ADuM5401 Datasheet ADuM1280 Datasheet AD5201 Datasheet ADR3440 Datasheet REVISION HISTORY 8/13—Rev. 0 to Rev. A Changes to Title ................................................................................. 1 8/13—Revision 0: Initial Version (Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN10926-0-8/13(A) System pro M compact® Miniature Circuit Breaker S 200/S 200 M Data Sheet The miniature circuit breakers of the System pro M compact® series S 200 and S 200 M provide state-of-the-art safety and comfort. They stand out due to their high performance and the wide range of accessories and approvals. 2CDC021023S0012 Features −− Clear contact position indication in red/green (“real CPI”) −− Unique, patented twin terminal with captive screws and an increased opening for cables up to max. 35 mm2, finger-proof (IP20) −− Busbar slot in the back for best visibility during installation −− High performance at an increased rated voltage for marine and industrial applications: 10 kA/15 kA at Ue = 440 V AC acc. to IEC/EN 60947-2 −− Individual product identification code −− Approved acc. to IEC/EN 60898-1, IEC/EN 60947-2 and UL 1077/CSA 22.2 No. 235 for global use 2CDC021038S0012 2 - 2CDC002157D0202 Miniature Circuit Breaker S 200/S 200 M Technical data S 200 S 200 M General Data Standards IEC/EN 60898-1, IEC/EN 60947-2 UL 1077 IEC/EN 60898-1, IEC/EN 60947-2 UL 1077, CSA 22.2 No. 235 Poles 1P, 2P, 3P, 4P, 1P+N, 3P+N Tripping Characteristics B, C, D, K, Z Rated current In 0.5 up to 63 A Rated frequency 50/60 Hz Rated insulation voltage Ui 250 V AC (phase to ground), 500 V AC (phase to phase) Overvoltage Category III Pollution Degree 3 IEC/EN 60898-1 Rated operational voltage Un 1P: 230/400 V AC; 1P+N: 230 V AC; 2P, 3P, 4P: 400 V AC; 3P+N: 400 V AC Max. power frequency recovery voltage Umax 1P: 253 V AC; 1P+N: 253 V AC; 2P, 3P, 4P: 440 V AC; 3P+N: 440 V AC; 1P: 72 V DC; 2P: 125 V DC Min. operating voltage 12 V AC, 12 V DC Rated short-circuit capacity Icn 6 kA 10 kA Energy limiting class (B, C up to 40 A) 3 Rated impulse withstand voltage Uimp (1.2/50 μs) 4 kV (test voltage 6.2 kV at sea level, 5 kV at 2,000 m) Dielectric test voltage 2.0 kV (50/60 Hz, 1 min) Reference temperature for tripping characteristics B, C, D: 30 °C Electrical endurance In < 32 A: 20,000 ops. (AC), 1,000 ops. (DC); one cycle 2 s - ON, 13 s - OFF In ≥ 32 A: 10,000 ops. (AC), 1,000 ops. (DC); one cycle 2 s - ON, 28 s - OFF IEC/EN 60947-2 Rated operational voltage Ue 1P: 230 V AC; 1P+N: 230 V AC; 2P, 3P, 4P: 440 V AC; 3P+N: 440 V AC Max. power frequency recovery voltage Umax 1P: 253 V AC; 1P+N: 253 V AC; 2P, 3P,4P: 462 V AC; 3P+N: 462 V AC; 1P: 72 V DC; 2P: 125 V DC Min. operating voltage 12 V AC, 12 V DC Rated ultimate short-circuit breaking capacity Icu 10 kA 15 kA Rated service short-circuit breaking capacity Ics 7.5 kA ≤ 40 A: 11.25 kA 50, 63 A: 7.5 kA Rated impulse withstand voltage Uimp (1.2/50 μs) 4 kV (test voltage 6.2 kV at sea level, 5 kV at 2,000 m) Dielectric test voltage 2.0 kV (50/60 Hz, 1 min) Reference temperature for tripping characteristics B, C, D: 55 °C; K, Z: 20 °C Electrical endurance In < 32 A: 20,000 ops. (AC), 1,000 ops. (DC); one cycle 2 s - ON, 13 s - OFF In ≥ 32 A: 10,000 ops. (AC), 1,000 ops. (DC); one cycle 2 s - ON, 28 s - OFF UL/CSA Rated voltage 1P: 277 V AC, 60 V DC 2...4P: 480 Y/277 V AC, 110 V DC 1P: 277 V AC, 60 V DC 2...4P: 480 Y/277 V AC, 125 V DC Rated interrupting capacity 6 kA (AC), 10 kA (DC) Application Suppl. prot. for general use. Application Codes: TC2, OL0, SC: U1 Reference temperature for tripping characteristic B, C, D, K, Z: 25 °C Electrical endurance 6,000 ops. (AC), 6,000 ops. (DC); one cycle 1 s - ON, 9 s - OFF Mechanical data Housing Insulation group II, RAL 7035 Insulation group I, RAL 7035 Toggle Insulation group II, black, sealable Contact position indication Marking on toggle (I ON/0 OFF), Real CPI (red ON/green OFF) Protection degree acc. to EN 60529 IP201), IP40 in enclosure with cover Mechanical endurance 20,000 ops. Shock resistance acc. to IEC/EN 60068-2-27 25 g, 2 shocks, 13 ms Vibration resistance acc. to IEC/EN 60068-2-6 5 g, 20 cycles at 5…150…5 Hz with load 0.8 In Environmental conditions acc. to IEC/EN 60068-2-30 28 cycles with 55 °C/90-96 % and 25 °C/95-100 % Ambient temperature -25 ... +55 °C Storage temperature -40 ... +70 °C 1) Also fulfilling the requirements acc. to the protection degree IPXXB 2CDC002157D0202 - 3 Miniature Circuit Breaker S 200/S 200 M Technical data and tripping characteristics S 200 S 200 M Installation Terminal Failsafe bi-directional cylinder-lift terminal Cross-section of conductors (top/bottom) solid, stranded: 35 mm2 / 35 mm2 flexible: 25 mm2 / 25 mm2 14 – 4 AWG1) Cross-section of busbars (top/bottom) 10 mm2 / 10 mm2 14 – 8 AWG2) Torque 2.8 Nm 18 in-Ibs. Screwdriver No. 2 Pozidrive Mounting On DIN rail 35 mm acc. to EN 60715 by fast clip Mounting position any Supply optional Dimensions and weight Mounting dimensions acc. to DIN 43880 Mounting dimension 1 Pole dimensions (H x D x W) 88 x 69 x 17.5 Pole weight approx. 115 g Combination with auxiliary elements Auxiliary contact Yes Signal/auxiliary contact Yes Shunt trip Yes Undervoltage release Yes Motor Operating Device Yes Tripping characteristics Acc. to Tripping characteristics Rated current Thermal release 3) Electromagnetic release 4) In Currents: conventional non-tripping current I1 conventional tripping current I2 Tripping time Range of instantaneous tripping Tripping time IEC/EN 60898-1 B 6 to 63 A 1.13 · In 1.45 · In > 1 h < 1 h 5) 3 · In 5 · In 0.1 ... 45 s (In ≤ 32 A)/0.1 ... 90 s (In > 32 A) < 0.1 s C 0.5 to 63 A 1.13 · In 1.45 · In > 1 h < 1 h 5) 5 · In 10 · In 0.1 ... 15 s (In ≤ 32 A)/0.1 ... 30 s (In > 32 A) < 0.1 s D 0.5 to 63 A 1.13 · In 1.45 · In > 1 h < 1 h 5) 10 · In 20 · In 0.1 ... 4 s (In ≤ 32 A)/0.1 ... 8 s (In > 32 A) < 0.1 s IEC/EN 60947-2 K 0.5 to 63 A 1.05 · In 1.2 · In > 1 h < 1 h 5) 10 · In 14 · In > 0.2 s < 0.2 s Z 0.5 to 63 A 1.05 · In 1.2 · In > 1 h < 1 h 5) 2 · In 3 · In > 0.2 s < 0.2 s 3) The thermal releases are calibrated to a nominal reference ambient temperature; for B, C, D the reference value is 30 °C, for K and Z the reference value is 20 °C. In the case of higher ambient temperatures, the current values fall by approx. 6 % for each 10 K temperature rise. 4) The indicated tripping values of electromagnetic tripping devices apply to a frequency of 50/60 Hz. The thermal release operates independent of frequency. 5) As from operating temperature (after I1 > 1h) 1) AWG 18 – 4 acc. to UL 486A – 486B 2) AWG 18 – 8 acc. to UL 486A – 486B 4 - 2CDC002157D0202 Miniature Circuit Breaker S 200/S 200 M 2CDC022060F0211 Z characteristic Tripping characteristics 2CDC022006F0211 2CDC022008F0211 B characteristic C characteristic 2CDC022010F0211 K characteristic D characteristic 2CDC022108F0209 2CDC002157D0202 - 5 Miniature Circuit Breaker S 200/S 200 M Deviating ambient temperature For installations of miniature circuit breakers at other temperatures than the reference value derating factors have to be considered. The rated value of the current of a miniature circuit breaker refers to a reference ambient temperature of 30 °C for circuit Derating Influence of adjacent devices If several miniature circuit breakers are installed directly side by side with high load on all poles, a correction factor has to be applied to the rated current (see table). If distance pieces are used, the factor is not to be considered. No. of adjacent devices Factor F 1 1 2, 3 0.9 4, 5 0.8 ≥ 6 0.75 breakers with the characteristics B, C and D and 20 °C for circuit breakers with the characteristics K and Z. The following table contains the derating of the load capability at ambient temperatures from -40 °C to 70 °C for the characteristics B, C, D, K and Z. Example Installation of 8 adjacent miniature circuit breakers S201-C16 at 40 °C ambient temperature Rated current In = 16 A Max. operating current at 40 °C = 15,.1 A (see table above) Factor F = 0.75 (see left table) In = 15.1 A x 0.75 = 11.33 A Result: The operating current can only add up to max. 11.33 A Tripping Rated Maximum operating current at ambient temperature T charac- current teristics In A A - 40 °C - 30 °C - 20 °C - 10 °C 0 °C 10 °C 20 °C 30 °C 40 °C 50 °C 60 °C 70 °C B, C, D 0.5 0.67 0.65 0.62 0.60 0.58 0.55 0.53 0.50 0.47 0.44 0.41 0.37 1.0 1.33 1.29 1.25 1.20 1.15 1.11 1.05 1.00 0.94 0.88 0.82 0.75 1.6 2.13 2.07 2.00 1.92 1.85 1.77 1.69 1.60 1.51 1.41 1.31 1.19 2.0 2.67 2.58 2.49 2.40 2.31 2.21 2.11 2.00 1.89 1.76 1.63 1.49 3.0 4.0 3.9 3.7 3.6 3.5 3.3 3.2 3.0 2.8 2.6 2.4 2.2 4.0 5.3 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.5 3.3 3.0 6.0 8.0 7.7 7.5 7.2 6.9 6.6 6.3 6.0 5.7 5.3 4.9 4.5 8.0 10.7 10.3 10.0 9.6 9.2 8.8 8.4 8.0 7.5 7.1 6.5 6.0 10.0 13.3 12.9 12.5 12.0 11.5 11.1 10.5 10.0 9.4 8.8 8.2 7.5 13.0 17.3 16.8 16.2 15.6 15.0 14.4 13.7 13.0 12.3 11.5 10.6 9.7 16.0 21.3 20.7 20.0 19.2 18.5 17.7 16.9 16.0 15.1 14.1 13.1 11.9 20.0 26.7 25.8 24.9 24.0 23.1 22.1 21.1 20.0 18.9 17.6 16.3 14.9 25.0 33.3 32.3 31.2 30.0 28.9 27.6 26.4 25.0 23.6 22.0 20.4 18.6 32.0 42.7 41.3 39.9 38.5 37.0 35.4 33.7 32.0 30.2 28.2 26.1 23.9 40.0 53.3 51.6 49.9 48.1 46.2 44.2 42.2 40.0 37.7 35.3 32.7 29.8 50.0 66.7 64.5 62.4 60.1 57.7 55.3 52.7 50.0 47.1 44.1 40.8 37.3 63.0 84.0 81.3 78.6 75.7 72.7 69.6 66.4 63.0 59.4 55.6 51.4 47.0 K, Z 0.5 0.66 0.64 0.61 0.59 0.56 0.53 0.50 0.47 0.43 0.40 0.35 0.31 1.0 1.32 1.27 1.22 1.17 1.12 1.06 1.00 0.94 0.87 0.79 0.71 0.61 1.6 2.12 2.04 1.96 1.88 1.79 1.70 1.60 1.50 1.39 1.26 1.13 0.98 2.0 2.65 2.55 2.45 2.35 2.24 2.12 2.00 1.87 1.73 1.58 1.41 1.22 3.0 4.0 3.8 3.7 3.5 3.4 3.2 3.0 2.8 2.6 2.4 2.1 1.8 4.0 5.3 5.1 4.9 4.7 4.5 4.2 4.0 3.7 3.5 3.2 2.8 2.4 6.0 7.9 7.6 7.3 7.0 6.7 6.4 6.0 5.6 5.2 4.7 4.2 3.7 8.0 10.8 10.2 9.8 9.4 8.9 8.5 8.0 7.5 6.9 6.3 5.7 4.9 10.0 13.2 12.7 12.2 11.7 11.2 10.6 10.0 9.4 8.7 7.9 7.1 6.1 13.0 17.2 16.6 15.9 15.2 14.5 13.8 13.0 12.2 11.3 10.3 9.2 8.0 16.0 21.2 20.4 19.6 18.8 17.9 17.0 16.0 15.0 13.9 12.6 11.3 9.8 20.0 26.5 25.5 24.5 23.5 22.4 21.2 20.0 18.7 17.3 15.8 14.1 12.2 25.0 33.1 31.9 30.6 29.3 28.0 26.5 25.0 23.4 21.7 19.8 17.7 15.3 32.0 42.3 40.8 39.2 37.5 35.8 33.9 32.0 29.9 27.7 25.3 22.6 19.6 40.0 52.9 51.0 49.0 46.9 44.7 42.4 40.0 37.4 34.6 31.6 28.3 24.5 50.0 66.1 63.7 61.2 58.6 55.9 53.0 50.0 46.8 43.3 39.5 35.4 30.6 63.0 83.3 80.3 77.2 73.9 70.4 66.8 63.0 58.9 54.6 49.8 44.5 38.6 6 - 2CDC002157D0202 Miniature Circuit Breaker S 200/S 200 M Internal resistance and power loss Rated Tripping characteristic current B, C1) D K Z Internal resistance Power loss Internal resistance Power loss Internal resistance Power loss Internal resistance Power loss In Ri Pv Ri Pv Ri Pv Ri Pv A mΩ W mΩ W mΩ W mΩ W 0.5 5500 1.4 4300 1.1 4300 1.1 8100 2.4 1.0 1440 1.4 1250 1.25 1250 1.25 2100 2.3 1.6 630 1.6 600 1.5 600 1.5 1000 2.8 2.0 460 1.8 410 1.6 410 1.65 619 2.5 3.0 150 1.3 130 1.2 130 1.2 235 2.4 4.0 110 1.8 105 1.7 105 1.7 149 2.4 6.0 55 2.0 52 1.9 52 1.9 75 3.2 8.0 23 1.5 24 1.5 24 1.5 27 2.0 10.0 19 2.1 16 1.6 13.5 1.4 24 2.7 13.0 14 2.3 14 2.2 13.5 1.4 — — 16.0 8.5 2.5 8.5 2.5 7.7 2.0 10.9 2.8 20.0 6.25 2.5 6.1 2.3 6.7 2.7 6.0 2.4 25.0 5.0 3.2 4.3 3.1 4.6 2.9 4.5 3.3 32.0 3.6 3.7 3.5 3.6 3.5 3.6 3.5 3.6 40.0 3.0 4.8 2.2 4.2 2.2 4.2 2.5 4.1 50.0 1.3 3.25 1.25 2.9 1.25 3.1 1.5 4.1 63.0 1.2 4.8 1.2 4.8 1.0 4.4 1.3 5.2 1) Current ratings 0.5 – 4 A, 8 A apply to C characteristic only Internal resistances are subject to application-specific and environment-specific conditions and are therefore to be considered as typical values. Internal resistance and power loss per pole 2CDC002157D0202 - 7 Miniature Circuit Breaker S 200/S 200 M Let-through energy I2t Characteristics B, C - 230/400 V let-through energy 8 - 2CDC002157D0202 Miniature Circuit Breaker S 200/S 200 M Let-through energy I2t Characteristics D, K - 230/400 V let-through energy 2CDC002157D0202 - 9 Miniature Circuit Breaker S 200/S 200 M Let-through energy I2t Characteristic Z - 230/400 V let-through energy 10 - 2CDC002157D0202 Miniature Circuit Breaker S 200/S 200 M Accessory overview Dimensional drawing 2CDC022007F0010 Accessories and dimensional drawing H Auxiliary contact S2C-H6R (change-over contact) H-R Auxiliary contact S2C-H6-...R S/H Signal/Auxiliary contact S2C-S/H6R S/H (H) Signal/Auxiliary contact used as auxiliary contact S2C-S/H6R ST Shunt trip S2C-A... UR Undervoltage release S2C-UA OR Overvoltage release S2C-OVP 2CDC092002F0212 H-L Auxiliary contact S2C-H...L H-BF Auxiliary contact for bottom fitting S2C-H01 (1 per pole) S2C-H10 BP Mechanical tripping device S2C-BP NT Neutral disconnector S2C-Nt MOD-S1) Motor operating device S2C-CM DDA 200 RCD-block DDA 20... 1) In case of using S 200/S 200 M coupled with DDA 200, MOD-S does not operate in case of earth-leakage fault. 2CDC002157D0202 - 11 Miniature Circuit Breaker S 200/S 200 M Ship approvals Approval mark Description Country BV France GL Germany RINA Italy ABS USA Country approvals Approval mark Description Country RCM Australia ÖVE Austria CEBEC Belgium CSA Canada (S 200 M only) CCC China EZU Czech Republic DEMKO Denmark FIMKO Finland NF France VDE Germany IMQ Italy SIRIM Malaysia KEMA Netherlands NEMKO Norway BBJ Poland CERTIF Portugal GOST Russia GOST Fire HDB Singapore SIQ Slovenia AENOR Spain SEMKO Sweden S+ Switzerland UL1077 USA Approvals Not all approvals are printed on the MCBs. The indicated approvals generally cover all available approvals worldwide. To verify the approval status in your country please get in touch with your ABB contact person. ABB STOTZ-KONTAKT GmbH Eppelheimer Straße 82 69123 Heidelberg, Germany Phone: +49 (0) 6221 7 01-0 Fax: +49 (0) 6221 7 01-13 25 E-Mail: info.desto@de.abb.com You can find the address of your local sales organization on the ABB home page http://www.abb.com/contacts -> Low Voltage Products and Systems Contact us Note: We reserve the right to make technical changes or modify the contents of this document without prior notice. With regard to purchase orders, the agreed particulars shall prevail. ABB AG does not accept any responsibility whatsoever for potential errors or possible lack of information in this document. We reserve all rights in this document and in the subject matter and illustrations contained therein. Any reproduction, disclosure to third parties or utilization of its contents – in whole or in parts – is forbidden without prior written consent of ABB AG. Copyright© 2012 ABB All rights reserved Brochure number 2CDC002157D0202 (08/12-0.5-ZVD) ARADUR HY 1300 GB IDENTIFICATION DE LA SUBSTANCE/DU MÉLANGE ET DE LA SOCIÉTÉ/ENTREPRISE FICHE DE DONNÉES DE SÉCURITÉ Nom du produit ARADUR HY 1300 GB Conforme au règlement (CE) n° 1907/2006 (REACH), Annexe II - France 1. Numéro de téléphone d'appel d'urgence : Fournisseur : : Identification de la substance ou du mélange Type de produit : Liquide. Pour toutes questions de Sécurité, Hygiène et Environnement relatives à ce document ou son contenu, veuillez contacter: E-Mail: global_product_ehs_admat@huntsman.com Utilisation de la substance/du mélange : Composant utilisé pour la fabrication de parties pour l'isolation électrique EUROPE: +32 35 75 1234 France ORFILA: +33(0)145425959 ASIA: +65 6336-6011 China: +86 20 39377888 Australia: 1800 786 152 New Zealand: 0800 767 437 USA: +1/800/424.9300 Huntsman Advanced Materials (Europe)BVBA Everslaan 45 3078 Everberg / Belgium Tel.: +41 61 299 20 41 Fax: +41 61 299 20 40 Description du produit : Préparation 2. IDENTIFICATION DES DANGERS Classification Xn; R21/22 C; R34 R43 : Le produit est classé dangereux selon la directive 1999/45/CE et ses amendements. Dangers pour la santé : humaine Nocif par contact avec la peau et par ingestion. Provoque des brûlures. Peut entraîner une sensibilisation par contact avec la peau. Pour plus de détails sur les conséquences en termes de santé et les symptômes, reportez-vous à la section 11. 3. COMPOSITION/INFORMATIONS SUR LES COMPOSANTS Substance/préparation Préparation polyoxypropylenetriamine 39423-51-3 60 - 100 Xn; R21/22 C; R34 [1] triéthylènetétramine 112-24-3 13 - 30 Xn; R21 C; R34 R43 R52/53 [1] acide-salicylique 69-72-7 3 - 7 Xn; R20/22 Xi; R41 [1] : Numéro CAS Nom des composants % Nombre Classification Voir section 16 pour le texte intégral des phrases R mentionnées ci-dessus Dans l'état actuel des connaissances du fournisseur et dans les concentrations d'application, aucun autre ingrédient présent n'est classé comme dangereux pour la santé ou l'environnement, et donc nécessiterait de figurer dans cette section. Date d'édition/Date de révision : 8/19/2010. 1/10 ARADUR HY 1300 GB COMPOSITION/INFORMATIONS 3. SUR LES COMPOSANTS Les limites d'exposition professionnelle, quand elles sont disponibles, sont énumérées à la section 8. [1] Substance classée avec un danger pour la santé ou l'environnement [2] Substance avec une limite d'exposition au poste de travail [3] Substance PBT [4] Substance vPvB Consulter un médecin immédiatement. Rincez la bouche avec de l'eau. Enlever les prothèses dentaires s'il y a lieu. Transporter la personne incommodée à l'air frais. Garder la personne au chaud et au repos. Si une personne a avalé de ce produit et est consciente, lui faire boire de petites quantités d’eau. Si la personne est indisposée, cesser de la faire boire car des vomissements pourraient entraîner un risque supplémentaire. Ne pas faire vomir sauf indication contraire émanant du personnel médical. En cas de vomissement, maintenez la tête vers le bas pour empêcher le passage des vomissures dans les poumons. Les brûlures chimiques doivent être traitées sans tarder par un médecin. Ne rien faire ingérer à une personne inconsciente. En cas d'évanouissement, placez la personne en position latérale de sécurité et appelez un médecin immédiatement. Assurez-vous d'une bonne circulation d'air. Détacher tout ce qui pourrait être serré, comme un col, une cravate, une ceinture ou un ceinturon. Contact avec la peau Consulter un médecin immédiatement. Rincer immédiatement les yeux à grande eau, en soulevant de temps en temps les paupières supérieures et inférieures. Vérifier si la victime porte des verres de contact et dans ce cas, les lui enlever. Continuez de rincer pendant 10 minutes au moins. Les brûlures chimiques doivent être traitées sans tarder par un médecin. Consulter un médecin immédiatement. Rincer la peau contaminée à grande eau. Retirer les vêtements et les chaussures contaminés. Laver abondamment à l'eau les vêtements contaminés avant de les retirer, ou porter des gants. Continuez de rincer pendant 10 minutes au moins. Les brûlures chimiques doivent être traitées sans tarder par un médecin. En cas d'affections ou de symptômes, évitez d'exposer plus longuement. Laver les vêtements avant de les réutiliser. Laver les chaussures à fond avant de les remettre. 4. Premiers secours Consulter un médecin immédiatement. Transporter la personne incommodée à l'air frais. Si l'on soupçonne que des fumées sont encore présentes, le sauveteur devra porter un masque adéquat ou un appareil de protection respiratoire autonome. Garder la personne au chaud et au repos. S'il ne respire pas, en cas de respiration irrégulière ou d'arrêt respiratoire, que le personnel qualifié pratique la respiration artificielle ou administre de l'oxygène. Il peut être dangereux pour la personne assistant une victime de pratiquer le bouche à bouche. En cas d'évanouissement, placez la personne en position latérale de sécurité et appelez un médecin immédiatement. Assurez-vous d'une bonne circulation d'air. Détacher tout ce qui pourrait être serré, comme un col, une cravate, une ceinture ou un ceinturon. En cas d’inhalation de produits de décomposition lors d’un incendie, les symptômes peuvent être différés. La personne exposée peut avoir besoin de rester sous surveillance médicale pendant 48 heures. Note au médecin traitant En cas d’inhalation de produits de décomposition lors d’un incendie, les symptômes peuvent être différés. La personne exposée peut avoir besoin de rester sous surveillance médicale pendant 48 heures. Ingestion Inhalation Contact avec les yeux : : : : : PREMIERS SECOURS Pour plus de détails sur les conséquences en termes de santé et les symptômes, reportez-vous à la section 11. Protection des sauveteurs : Aucune initiative ne doit être prise qui implique un risque individuel ou en l’absence de formation appropriée. Si l'on soupçonne que des fumées sont encore présentes, le sauveteur devra porter un masque adéquat ou un appareil de protection respiratoire autonome. Il peut être dangereux pour la personne assistant une victime de pratiquer le bouche à bouche. Laver abondamment à l'eau les vêtements contaminés avant de les retirer, ou porter des gants. Date d'édition/Date de révision : 8/19/2010. 2/10 ARADUR HY 1300 GB MESURES DE LUTTE 5. CONTRE L'INCENDIE En présence d'incendie, circonscrire rapidement le site en évacuant toute personne se trouvant près des lieux de l'accident. Aucune initiative ne doit être prise qui implique un risque individuel ou en l’absence de formation appropriée. Risque lié aux produits de décomposition thermique Risques particuliers liés à l’exposition au produit L’augmentation de pression résultant d’un incendie ou d’une exposition à des températures élevées peut provoquer l’explosion du conteneur. Les pompiers devront porter un équipement de protection approprié ainsi qu'un appareil de protection respiratoire autonome avec masque intégral fonctionnant en mode pression positive. Équipement de protection spécial pour le personnel préposé à la lutte contre l'incendie Utiliser un agent extincteur approprié pour étouffer l'incendie avoisinant. Moyens d'extinction : : : Aucun connu. Utilisables : Non utilisables : Oxydes de carbone., La combustion produit des fumées nauséabondes et toxiques., Oxydes d'azote. Précautions relatives à l'environnement Précautions individuelles Arrêter la fuite si cela ne présente aucun risque. Écarter les conteneurs de la zone de déversement accidentel. S'approcher des émanations dans la même direction que le vent. Bloquer toute pénétration possible dans les égouts, les cours d’eau, les caves ou les zones confinées. Laver le produit répandu dans une installation de traitement des effluents ou procéder comme suit. Contenir les fuites et les ramasser à l'aide de matières absorbantes non combustibles telles que le sable, la terre, la vermiculite, la terre à diatomées. Les placer ensuite dans un récipient pour élimination conformément à la réglementation locale (voir section 13). Élimination par une entreprise autorisée de collecte des déchets. Les matériaux absorbants contaminés peuvent présenter les mêmes risques que le produit répandu. Nota : Voir section 1 pour le contact en cas d'urgence et voir section 13 pour l'élimination des déchets. 6. MESURES À PRENDRE EN CAS DE REJET ACCIDENTEL : : Aucune initiative ne doit être prise qui implique un risque individuel ou en l’absence de formation appropriée. Évacuer les environs. Empêcher l'accès aux personnes non requises et ne portant pas de vêtements de protection. NE PAS TOUCHER ni marcher dans le produit répandu. Ne pas respirer les vapeurs ou le brouillard. Assurer une ventilation adéquate. Porter un appareil de protection respiratoire approprié lorsque le système de ventilation est inadéquat. Revêtir un équipement de protection individuelle approprié (voir Section 8). Évitez la dispersion des matériaux déversés, ainsi que leur écoulement et tout contact avec le sol, les cours d'eau, les égouts et conduits d'évacuation. Informez les autorités compétentes en cas de pollution de l'environnement (égouts, voies d'eau, sol et air) par le produit. Grand déversement accidentel : Arrêter la fuite si cela ne présente aucun risque. Écarter les conteneurs de la zone de déversement accidentel. Diluer avec de l'eau et éponger si la matière est soluble dans l'eau. Sinon, ou si la matière est insoluble dans l'eau, absorber avec un matériau sec inerte et placer dans un conteneur à déchets approprié. Élimination par une entreprise autorisée de collecte des déchets. Petit déversement accidentel : Méthodes de nettoyage Manipulation 7. MANIPULATION ET STOCKAGE Revêtir un équipement de protection individuelle approprié (voir Section 8). Il est interdit de manger, boire ou fumer dans les endroits où ce produit est manipulé, entreposé ou mis en oeuvre. Il est recommandé au personnel de se laver les mains et la figure avant de manger, boire ou fumer. Les personnes ayant des antécédents de sensibilisation cutanée ne doivent pas intervenir dans les processus utilisant ce produit. Ne pas mettre en contact avec les yeux, la peau ou les vêtements. Ne pas respirer les vapeurs ou le brouillard. Ne pas ingérer. Si au cours d'une utilisation normale, la substance présente un danger respiratoire, une ventilation adéquate ou le port d'un appareil respiratoire est obligatoire. Garder dans le conteneur d'origine ou dans un autre conteneur de substitution homologué fabriqué à partir d'un matériau compatible et tenu hermétiquement clos lorsqu'il n'est pas utilisé. Les conteneurs vides retiennent des résidus de produit et peuvent présenter un danger. Ne pas : Date d'édition/Date de révision : 8/19/2010. 3/10 ARADUR HY 1300 GB MANIPULATION 7. ET STOCKAGE Stockage réutiliser ce conteneur. Matériaux d'emballage Stocker entre les températures suivantes:Stocker conformément à la réglementation locale. Stocker dans le récipient d'origine à l'abri de la lumière directe du soleil dans un endroit sec, frais et bien ventilé à l'écart des matériaux incompatibles (cf. la section 10). Garder le récipient hermétiquement fermé lorsque le produit n'est pas utilisé. Les récipients ayant été ouverts doivent être refermés avec soin et maintenus en position verticale afin d'éviter les fuites. Ne pas stocker dans des conteneurs non étiquetés. Utiliser un récipient approprié pour éviter toute contamination du milieu ambiant. : Recommandé : Utiliser le récipient d'origine. Classe de danger de stockage Huntsman Advanced Materials : Classe de stockage 8, Matériel corrosif Nom des composants Limites d'exposition professionnelle Procédures de surveillance recommandées Valeurs limites d'exposition Si ce produit contient des ingrédients présentant des limites d'exposition, il peut s'avérer nécessaire d'effectuer un examen suivi des personnes, de l'atmosphère sur le lieu de travail ou des organismes vivants pour déterminer l'efficacité de la ventilation ou d'autres mesures de contrôle ou évaluer le besoin d'utiliser du matériel de protection des voies respiratoires. Il importe de vous reporter à la norme européenne EN 689 concernant les méthodes pour évaluer l'exposition par inhalation aux agents chimiques et aux documents de politique générale nationaux relatifs aux méthodes pour déterminer les substances dangereuses. 8. CONTRÔLE DE L'EXPOSITION/PROTECTION INDIVIDUELLE Porter un appareil de protection respiratoire muni d'un purificateur d'air ou à adduction d' air, parfaitement ajusté et conforme à une norme en vigueur si une évaluation du risque indique que cela est nécessaire. Le choix de l'appareil de protection respiratoire doit être fondé sur les niveaux d'expositions prévus ou connus, les dangers du produit et les limites d'utilisation sans danger de l'appareil de protection respiratoire retenu. Protection respiratoire Aucune valeur de limite d'exposition connue. : : Contrôle de l'exposition professionnelle : Si les manipulations de l'utilisateur provoquent de la poussière, des fumées, des gaz, des vapeurs ou du brouillard, utiliser des enceintes fermées, une ventilation par aspiration à la source, ou d'autres systèmes de contrôle automatique intégrés afin de maintenir le seuil d'exposition du technicien aux contaminants en suspension dans l'air inférieur aux limites recommandées ou légales. Se laver abondamment les mains, les avant-bras et le visage après avoir manipulé des produits chimiques, avant de manger, de fumer et d'aller aux toilettes ainsi qu'à la fin de la journée de travail. Il est recommandé d'utiliser les techniques appropriées pour retirer les vêtements potentiellement contaminés. Laver les vêtements contaminés avant de les réutiliser. S'assurer que les dispositifs rince-oeil automatiques et les douches de sécurité se trouvent à proximité de l'emplacement des postes de travail. Contrôle de l'exposition Mesures d'hygiène : Alcool éthylvinylique laminé (EVAL), caoutchouc butyle Protection des mains : Matériaux pour gants pour utilisation à long terme (BTT>480 min): Matériaux pour gants pour utilisation à court terme/projection (10 min200°C (>392°F) PROPRIÉTÉS PHYSIQUES ET CHIMIQUES État physique Point d'ébullition Pression de vapeur Liquide. <0.1 kPa (<0.75 mm Hg) Odeur Amine. pH Couleur Brun clair. Point d'éclair Coupe fermée: >150°C (>302°F) [DIN 51758 EN 22719 (Pensky-Martens Closed Cup)] 9. 11 [Conc. (% poids / poids): 50%] Viscosité Dynamique: 160 à 200 mPa·s (160 à 200 cP) : : : : : : : : Informations générales Aspect Informations importantes relatives à la santé, à la sécurité et à l'environnement 25 deg C 20 deg C 20 deg C Masse volumique : 1 g/cm3 [25°C (77°F)] Solubilité dans l'eau : partiellement miscible Température de décomposition : >200°C (>392°F) Eau Produits de décomposition dangereux Conditions à éviter Aucune donnée spécifique. STABILITÉ ET RÉACTIVITÉ Dans des conditions normales de stockage et d'utilisation, aucun produit de décomposition dangereux ne devrait apparaître. Stabilité chimique Le produit est stable. 10. acides forts, bases fortes, agents oxydants forts : : : Matières à éviter : Risque de réactions dangereuses : Dans des conditions normales de stockage et d'utilisation, aucune réaction dangereuse ne se produit. Oxydes de carbone., La combustion produit des fumées nauséabondes et toxiques., Oxydes d'azote. Non disponible. 11. INFORMATIONS TOXICOLOGIQUES Toxicocinétique Absorption : Distribution : Contient des produits causant des lésions aux organes suivants : reins, système nerveux central (SNC), pancréas. Métabolisme : Non disponible. Élimination : Non disponible. Date d'édition/Date de révision : 8/19/2010. 5/10 ARADUR HY 1300 GB INFORMATIONS 11. TOXICOLOGIQUES Effets chroniques potentiels pour la santé Effets aigus potentiels sur la santé Inhalation : Dégagement possible de gaz, vapeur ou poussière très irritants ou corrosifs pour le système respiratoire. L'exposition aux produits de décomposition peut présenter des risques pour la santé. Les effets graves d’une exposition peuvent être différés. Nocif en cas d'ingestion. Peut causer des brûlures à la bouche, à la gorge et à l'estomac. Ingestion : Contact avec la peau : Corrosif pour la peau. Provoque des brûlures. Nocif par contact avec la peau. Peut entraîner une sensibilisation par contact avec la peau. Contact avec les yeux : Corrosif pour les yeux. Provoque des brûlures. Une fois sensibilisé, une vive réaction allergique peut éventuellement se déclencher lors d'une exposition ultérieure à de très faibles niveaux. Effets chroniques : Cancérogénicité : Aucun effet important ou danger critique connu. Mutagénicité : Aucun effet important ou danger critique connu. Tératogénicité : Aucun effet important ou danger critique connu. Toxicité aiguë polyoxypropylenetriamine DL50 Cutané Lapin 610 mg/kg - DL50 Orale Rat 220 mg/kg - acide-salicylique DL50 Cutané Lapin >2000 mg/kg - DL50 Orale Rat 891 mg/kg - CL50 Inhalation Poussière et brouillards Rat 0.9 mg/L 4 heures ARADUR HY 1300 GB DL50 Orale Rat 265 mg/kg - Nom du produit/composant Résultat Espèces Dosage Exposition Conclusion/Résumé : Non disponible. Toxicité chronique Conclusion/Résumé : Non disponible. Cancérogénicité Conclusion/Résumé : Non disponible. Mutagénicité Conclusion/Résumé : Non disponible. Tératogénicité Conclusion/Résumé : Non disponible. Toxicité pour la reproduction Conclusion/Résumé : Non disponible. Effets sur le développement : Aucun effet important ou danger critique connu. Effets sur la fertilité : Aucun effet important ou danger critique connu. Signes/symptômes de surexposition Peau Ingestion Inhalation Aucune donnée spécifique. Les symptômes néfastes peuvent éventuellement comprendre ce qui suit: douleurs stomacales Les symptômes néfastes peuvent éventuellement comprendre ce qui suit: douleur ou irritation rougeur la formation d'ampoules peut éventuellement apparaître : : : Irritation/Corrosion Conclusion/Résumé : Non disponible. Sensibilisant ARADUR HY 1300 GB peau cobaye Sensibilisant Nom du produit/composant Voie d'exposition Espèces Résultat Conclusion/Résumé : Non disponible. Date d'édition/Date de révision : 8/19/2010. 6/10 ARADUR HY 1300 GB INFORMATIONS 11. TOXICOLOGIQUES Yeux : Les symptômes néfastes peuvent éventuellement comprendre ce qui suit: douleur larmoiement rougeur 12. INFORMATIONS ÉCOLOGIQUES Autres effets nocifs : Aucun effet important ou danger critique connu. Écotoxicité en milieu aquatique Conclusion/Résumé : Non disponible. Biodégradabilité Conclusion/Résumé : Non disponible. Effets sur l'environnement : Aucun effet important ou danger critique connu. 13. CONSIDÉRATIONS RELATIVES À L'ÉLIMINATION 070204 Catalogue Européen des Déchets : Déchets Dangereux : Il se peut que la classification du produit satisfasse les critères de déchets dangereux. Il est recommandé d'éviter ou réduire autant que possible la production de déchets. Les conteneurs vides ou les sachets internes peuvent retenir des restes de produit. Ne se débarrasser de ce produit et de son récipient qu'en prenant toutes précautions d'usage. Élimination des produits excédentaires et non recyclables par une entreprise autorisée de collecte des déchets. La mise au rebut de ce produit, des solutions et des sous-produits devra en permanence respecter les exigences légales en matière de protection de l'environnement et de mise au rebut des déchets ainsi que les exigences de toutes les autorités locales. Évitez la dispersion des matériaux déversés, ainsi que leur écoulement et tout contact avec le sol, les cours d'eau, les égouts et conduits d'évacuation. Méthodes d'élimination des : déchets 07 02 04* autres solvants, liquides de lavage et liqueurs mères organiques Il faut dans tous les cas appliquer toutes les lois locales régionales et nationales ainsi que les directives européennes. Il appartient à l'utilisateur final de déterminer le code des déchets spécifique à chaque secteur industriel en utilisant le code Européen approprié du catalogue européen des déchets. Il est recommandé que tous les détails soient indiqués par le responsable des déchets. 14. Réglementation internationale du transport INFORMATIONS RELATIVES AU TRANSPORT Nom d'expédition ADR : Liquide organique corrosif, basique, n.s.a. ALIPHATIC POLYAMINE IMDG : Corrosive liquid, basic, organic, n.o.s. (ALIPHATIC POLYAMINE) IATA : Corrosive liquid, basic, organic, n.o.s. (ALIPHATIC POLYAMINE) Informations réglementaires Numéro ONU Classes Groupe d'emballage Étiquette Autres informations Terre- UN3267 8 III Route/Chemin de fer Classe ADR/RID Voie maritime Classe IMDG UN3267 8 III Emergency schedules (EmS) F-A, S-B Code de classificationC7 Numéro d'identification du danger 80 Date d'édition/Date de révision : 8/19/2010. 7/10 ARADUR HY 1300 GB 14. INFORMATIONS RELATIVES AU TRANSPORT Passenger and Cargo Aircraft Quantity limitation: 5 L Packaging instructions: 818 Cargo Aircraft OnlyQuantity limitation: 60 L Packaging instructions: 820 Air UN3267 8 III Classe IATA 15. INFORMATIONS RÉGLEMENTAIRES Conseils de prudence S26- En cas de contact avec les yeux, laver immédiatement et abondamment avec de l'eau et consulter un spécialiste. S36/37/39- Porter un vêtement de protection approprié, des gants et un appareil de protection des yeux/du visage. S45- En cas d'accident ou de malaise, consulter immédiatement un médecin (si possible lui montrer l'étiquette). R21/22- Nocif par contact avec la peau et par ingestion. R34- Provoque des brûlures. R43- Peut entraîner une sensibilisation par contact avec la peau. Symbole(s) de danger Phrases de risque Réglementations de l'Union Européenne Réglementations nationales Contient du (de la) : : : : Corrosif polyoxypropylenetriamine triéthylènetétramine Déterminés en accord avec les directives de l'UE 67/548/EEC et 1999/45/EC (y compris les amendements), la classification et l'étiquetage prennent en compte l'usage prévu du produit. Surveillance médicale renforcée : Arrêté du 11 Juillet 1977 fixant la liste des travaux nécessitant une surveillance médicale renforcée: non concerné Réglementations Internationales Listes internationales C Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Tous les composants sont répertoriés ou exclus. Inventaire d'Europe : Inventaire des États-Unis (TSCA 8b) : Inventaire du Canada : Inventaire des substances chimiques d'Australie (AICS) : Inventaire des substances chimiques existantes en Chine (IECSC) : Inventaire du Japon (ENCS) : Inventaire de Corée (KECI) : Inventaire des substances chimiques des Philippines (PICCS) : Date d'édition/Date de révision : 8/19/2010. 8/10 ARADUR HY 1300 GB AUTRES DONNÉES 8/19/2010. Historique 16. Date d'impression Date d'édition/ Date de révision Version Avis au lecteur Date de la précédente édition : : : : R21- Nocif par contact avec la peau. R20/22- Nocif par inhalation et par ingestion. R21/22- Nocif par contact avec la peau et par ingestion. R34- Provoque des brûlures. R41- Risque de lésions oculaires graves. R43- Peut entraîner une sensibilisation par contact avec la peau. R52/53- Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. Texte complet des phrases : R citées dans les sections 2 et 3 - France Référence du texte complet des classifications se trouvant dans les Sections 2 et 3 - France : C - Corrosif Xn - Nocif Xi - Irritant Indique quels renseignements ont été modifiés depuis la version précédente. 8/19/2010. 2/19/2010. 2 Epoxy Resins and Curing Agents; Toxicology, Health, Safety and Environmental Aspects (Plastics Europe, May 2006) Les informations et recommandations figurant dans cette publication sont fondées sur notre expérience générale et sont fournies de bonne foi au mieux de nos connaissances actuelles, MAIS RIEN DANS LES PRESENTES NE DOIT ÊTRE INTERPRETE COMME CONSTITUANT UNE GARANTIE OU UNE DECLARATION, EXPRESSE, IMPLICITE OU AUTRE. DANS TOUS LES CAS, IL INCOMBE A L'UTILISATEUR DE DETERMINER ET DE VERIFIER L'EXACTITUDE, AINSI QUE LE CARACTERE SUFFISANT ET APPLICABLE DE TELLES INFORMATIONS ET RECOMMANDATIONS, DE MEME QUE L'ADEQUATION ET L'ADAPTATION D'UN QUELCONQUE PRODUIT A UNE UTILISATION SPECIFIQUE OU DANS UN BUT PARTICULIER. LES PRODUITS MENTIONNES PEUVENT PRESENTER DES RISQUES INCONNUS ET DOIVENT ETRE UTILISES AVEC PRECAUTION. MEME SI CERTAINS RISQUES SONT DECRITS DANS CETTE PUBLICATION, IL N'EXISTE AUCUNE GARANTIE QU'IL S'AGIT DES SEULS RISQUES EXISTANTS. Les risques, la toxicité et le comportement des produits peuvent différer lorsque ceux-ci sont utilisés avec d'autres matériaux et dépendent des conditions de fabrication et d'autres processus. Ces risques, cette toxicité et ces comportements doivent être déterminés par l'utilisateur et portés à la connaissance des personnes ou entités chargés du transport ou de la manutention, du traitement ou de la transformation, ainsi que de tous utilisateurs finaux. Pour toute demande, contactez le bureau commercial Huntsman Sales le plus proche ou directement Huntsman (Belgium) BVBA, Everslaan 45, B-3078 Everberg, Belgique. Tél. +32 2 758 9211 - Fax +32 758 9946. Huntsman Belgium (BVBA) Everslaan 45 B-3078 Everberg Belgium Tel.:+32-(0)2-758-9211 NO PERSON OR ORGANIZATION EXCEPT A DULY AUTHORIZED HUNTSMAN EMPLOYEE IS AUTHORIZED TO PROVIDE OR MAKE AVAILABLE DATA SHEETS FOR HUNTSMAN PRODUCTS. DATA SHEETS FROM UNAUTHORIZED SOURCES MAY CONTAIN INFORMATION THAT IS NO LONGER CURRENT OR ACCURATE. NO PART OF THIS DATA SHEET MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM, OR BY ANY MEANS, WITHOUT PERMISSION IN WRITING FROM HUNTSMAN. ALL REQUESTS FOR PERMISSION TO REPRODUCE MATERIAL FROM THIS DATA SHEET SHOULD BE DIRECTED TO HUNTSMAN, MANAGER, PRODUCT SAFETY AT THE ABOVE ADDRESS. Références Date d'édition/Date de révision : 8/19/2010. 9/10 ARADUR HY 1300 GB Date d'édition/Date de révision : 8/19/2010. 10/10 3M FRANCE Boulevard de l'Oise 95006 Cergy Pontoise Cedex ======================================================================== Fiche de Données de Sécurité ======================================================================== Numéro de document: 06-6544-8 Fiche établie le : 30/03/2001 Version : 1.01 Annule et remplace : 26/01/1999 Statut du document: Final Format : 17 ------------------------------------------------------------------------ 1 IDENTIFICATION DU PRODUIT ------------------------------------------------------------------------ Nom du produit : RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 Code d'identification : Identification de la société : Adresse : 3M FRANCE Boulevard de l'Oise 95006 Cergy Pontoise Cedex Téléphone : 01.30.31.61.61 N° d'appel d'urgence : ORFILA Téléphone : 01.45.42.59.59 ------------------------------------------------------------------------ 2 INFORMATIONS SUR LES COMPOSANTS ------------------------------------------------------------------------ Nom chimique Numéro CAS Pourcentage ------------------------------------- ------------------ ------------- RESINE 56275-01-5 15 - 40 SILOXANES ET SILICONES, DI-ME, DI-PH 68083-14-7 15 - 40 POLYMERE DE L'ANHYDRIDE 25038-81-7 15 - 40 PYROMELLITIQUE ET DE L'OXYDE DE 4,4'-DIAMINODIPHENYLE Nature chimique : Voir ci-dessus. RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 ------------------------------------------------------------------------ Classification des ingrédients : ------------------------------------------------------------------------ 3 IDENTIFICATION DES DANGERS ------------------------------------------------------------------------ Principaux dangers : ------------------------------------------------------------------------ 4 PREMIERS SECOURS ------------------------------------------------------------------------ En cas d'inhalation : En cas d'inhalation , il n'est pas nécessaire de prévoir des soins d'urgence. En cas de contact avec la peau : En cas de contact avec la peau, il n'est pas nécessaire de prévoir de soins d'urgence. En cas de contact avec les yeux : En cas de contact avec les yeux, il n'est pas nécessaire de prévoir de soins d'urgence. En cas d'ingestion : En cas d'ingestion, il n'est pas nécessaire de prévoir des soins d'urgence. ------------------------------------------------------------------------ 5 MESURES DE LUTTE CONTRE L'INCENDIE ------------------------------------------------------------------------ Moyens d'extinction appropriés : Eau. Dioxyde de carbone. Agent extincteur chimique sec. Mousse. Dangers spécifiques : Pas de risques particuliers d'incendie ou d'explosion. Mesures particulières d'intervention : Néant ------------------------------------------------------------------------ 6 MESURES A PRENDRE EN CAS DE DISPERSION ACCIDENTELLE ------------------------------------------------------------------------ RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 ------------------------------------------------------------------------ Précautions individuelles : Observer les mesures de précaution indiquées dans les autres sections. Mesures après fuite ou déversement : non applicable Méthodes de nettoyage : Mise en décharge agréée des déchets de produits. Autre méthode d'élimination: Mélanger avec un matériau inflammable et incinérer dans une installation industrielle appropriée. ------------------------------------------------------------------------ 7 MANIPULATION ET STOCKAGE ------------------------------------------------------------------------ Conseils d'utilisation : Prévention des incendies et des explosions : Non applicable. Conditions de stockage recommandées : Matières incompatibles : ------------------------------------------------------------------------ 8 CONTROLE DE L'EXPOSITION / PROTECTION INDIVIDUELLE ------------------------------------------------------------------------ Protection respiratoire : Eviter l'inhalation des produits de décomposition thermique. Protection des yeux : Non applicable. Protection de la peau et du corps : Eviter le contact prolongé ou répété avec la peau. Ingestion : Non applicable. Ventilation recommandée : Fournir une ventilation locale appropriée quand le produit est chauffé. RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 ------------------------------------------------------------------------ ------------------------------------------------------------------------ 9 PROPRIETES PHYSIQUES ET CHIMIQUES ------------------------------------------------------------------------ Etat physique,couleur,odeur : Ruban en rouleau marron, inodore. pH : non applicable Point/intervalle d'ébullition (°C) : non applicable Point/intervalle de fusion : non déterminé Point d'éclair - Coupe fermée (°C) : non applicable Température d'auto-inflammation : non applicable Limites d'explosivité dans l'air : - Inférieure (% en volume) : non applicable - Supérieure (% en volume) : non applicable Pression de vapeur (hPa) : non applicable Hydrosolubilité : nulle Densité relative (Eau=1) : non déterminé Densité de vapeur (Air=1) : non applicable Composés organiques volatils (g/l) : non déterminé Vitesse d'évaporation (Eau=1) : non applicable Viscosité (mPa.s) : non applicable Teneur en matières volatiles (%) : non déterminé ------------------------------------------------------------------------ 10 STABILITE ET REACTIVITE ------------------------------------------------------------------------ Stabilité : Stable. Pas de polymérisation dangereuse. RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 ------------------------------------------------------------------------ Matières à éviter : Eviter d'exposer le produit à 200°C sans une ventilation appropriée. Produits de décomposition dangereux : Monoxyde et dioxyde de carbone. Aldéhyde formique. ------------------------------------------------------------------------ 11 INFORMATIONS TOXICOLOGIQUES ------------------------------------------------------------------------ Effets en cas d'inhalation : Considéré sans effet sur la santé sauf si le produit est trop chauffé. Effets en cas de contact avec la peau : Le contact avec la peau est vraisemblablement sans effet sur la santé. Une exposition prolongée ou répétée peut causer: Irritation mécanique de la peau: les symptômes peuvent inclure démangeaisons et rougeurs. Effets en cas de contact avec les yeux : Le contact avec les yeux est peu probable dans les conditions normales d'utilisation. Effets en cas d'ingestion : L'ingestion n'est pas une voie d'exposition probable pour ce produit. Données complémentaires : Ce produit ne présente pas de risque d'émission ou d'exposition à des produits chimiques dangereux dans les conditions normales d'utilisation. Cependant, une utilisation anormale de ce produit peut affecter sa performance et présenter des dangers potentiels pour la santé et la sécurité. ------------------------------------------------------------------------ 12 INFORMATIONS ECOLOGIQUES ------------------------------------------------------------------------ Données et informations complémentaires : Non déterminé. Etant donné la diversité des réglementations, vérifier celles qui sont applicables ou consulter les autorités compétentes avant élimination. RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 ------------------------------------------------------------------------ ------------------------------------------------------------------------ 13 CONSIDERATIONS RELATIVES A L'ELIMINATION ------------------------------------------------------------------------ Déchets résultant de l'utilisation : Collecte et incinération par des sociétés spécialisées. Emballages souillés : Collecte et incinération par des sociétés spécialisées. Nomenclature des déchets : 20 01 03 ------------------------------------------------------------------------ 14 INFORMATIONS RELATIVES AU TRANSPORT ------------------------------------------------------------------------ Numéro ONU : Groupe d'emballage : VOIES TERRESTRES (RTMD, ADR/RID) - Classe,Chiffre de l'énumération : Non réglementé MARITIME (IMDG) - Classe : Non réglementé AERIEN (ICAO/IATA) - Classe : Non réglementé ------------------------------------------------------------------------ 15 INFORMATIONS REGLEMENTAIRES ------------------------------------------------------------------------ Etiquetage réglementaire : Symbole(s) Contient : Phrases de risque : Conseils de prudence : RUBAN FILM PLASTIQUE SCOTCH N°5413 ET 5433 ------------------------------------------------------------------------ Tableau des maladies professionnelles: ------------------------------------------------------------------------ 16 AUTRES INFORMATIONS ------------------------------------------------------------------------ Utilisation du produit : Raison de la réédition : Révision globale de la fiche. ARALDITE CW 1312 CH IDENTIFICATION DE LA SUBSTANCE/PRÉPARATION ET DE LA SOCIÉTÉ/ENTREPRISE FICHE DE DONNÉES DE SÉCURITÉ Nom du produit ARALDITE CW 1312 CH Conforme au règlement (CE) n° 1907/2006 (REACH), Annexe II - France 1. Numéro de téléphone d'appel d'urgence : Fournisseur : : Identification de la substance ou de la préparation Type de produit : Liquide. Pour toutes questions de Sécurité, Hygiène et Environnement relatives à ce document ou son contenu, veuillez contacter: E-Mail: global_product_ehs_admat@huntsman.com Utilisation de la substance/préparation : Composant utilisé pour la fabrication de parties pour l'isolation électrique EUROPE: +32 35 75 1234 France ORFILA: +33(0)145425959 ASIA: +65 6336-6011 China: +86 20 39377888 Australia: 1800 786 152 New Zealand: 0800 767 437 USA: +1/800/424.9300 Huntsman Advanced Materials (Europe)BVBA Everslaan 45 3078 Everberg / Belgium Tel.: +41 61 299 20 41 Fax: +41 61 299 20 40 Description du produit : Préparation 2. IDENTIFICATION DES DANGERS Classification R43 R52/53 : Le produit est classé dangereux selon la directive 1999/45/CE et ses amendements. Dangers physiques ou chimiques : Non applicable. Dangers pour la santé : humaine Peut entraîner une sensibilisation par contact avec la peau. Dangers pour : l'environnement Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. Pour plus de détails sur les conséquences en termes de santé et les symptômes, reportez-vous à la section 11. 3. COMPOSITION/INFORMATIONS SUR LES COMPOSANTS Substance/préparation Préparation produit de réaction: bisphénol-A-épichlorhydrine; résines époxydiques (poids moléculaire moyen < 700) 25068-38-6 13 - 30 Xi; R36/38 R43 N; R51/53 [1] diglycidylether de polypropyleneglycol 9072-62-2 7 - 13 R43 [1] : Numéro CAS Nom des composants % Nombre Classification Voir section 16 pour le texte intégral des phrases R mentionnées ci-dessus Date d'édition/Date de révision : 11/4/2009. 1/9 ARALDITE CW 1312 CH COMPOSITION/INFORMATIONS 3. SUR LES COMPOSANTS Les limites d'exposition professionnelle, quand elles sont disponibles, sont énumérées à la section 8. [1] Substance classée avec un danger pour la santé ou l'environnement [2] Substance avec une limite d'exposition au poste de travail Dans l'état actuel des connaissances du fournisseur et dans les concentrations d'application, aucun autre ingrédient présent n'est classé comme dangereux pour la santé ou l'environnement, et donc nécessiterait de figurer dans cette section. [3] Substance PBT [4] Substance vPvB Rincez la bouche avec de l'eau. Enlever les prothèses dentaires s'il y a lieu. Transporter la personne incommodée à l'air frais. Garder la personne au chaud et au repos. Si une personne a avalé de ce produit et est consciente, lui faire boire de petites quantités d’eau. Si la personne est indisposée, cesser de la faire boire car des vomissements pourraient entraîner un risque supplémentaire. Ne pas faire vomir sauf indication contraire émanant du personnel médical. En cas de vomissement, maintenez la tête vers le bas pour empêcher le passage des vomissures dans les poumons. Appelez un médecin en cas de persistance ou d'aggravation des effets néfastes sur la santé. Ne rien faire ingérer à une personne inconsciente. En cas d'évanouissement, placez la personne en position latérale de sécurité et appelez un médecin immédiatement. Assurez-vous d'une bonne circulation d'air. Détacher tout ce qui pourrait être serré, comme un col, une cravate, une ceinture ou un ceinturon. Contact avec la peau Rincer immédiatement les yeux à grande eau, en soulevant de temps en temps les paupières supérieures et inférieures. Vérifier si la victime porte des verres de contact et dans ce cas, les lui enlever. Continuez de rincer pendant 10 minutes au moins. En cas d'irritation, consulter un médecin. Rincer la peau contaminée à grande eau. Retirer les vêtements et les chaussures contaminés. Laver abondamment à l'eau les vêtements contaminés avant de les retirer, ou porter des gants. Continuez de rincer pendant 10 minutes au moins. Consulter un médecin. En cas d'affections ou de symptômes, évitez d'exposer plus longuement. Laver les vêtements avant de les réutiliser. Laver les chaussures à fond avant de les remettre. 4. Premiers secours Transporter la personne incommodée à l'air frais. Garder la personne au chaud et au repos. S'il ne respire pas, en cas de respiration irrégulière ou d'arrêt respiratoire, que le personnel qualifié pratique la respiration artificielle ou administre de l'oxygène. Il peut être dangereux pour la personne assistant une victime de pratiquer le bouche à bouche. Appelez un médecin en cas de persistance ou d'aggravation des effets néfastes sur la santé. En cas d'évanouissement, placez la personne en position latérale de sécurité et appelez un médecin immédiatement. Assurez-vous d'une bonne circulation d'air. Détacher tout ce qui pourrait être serré, comme un col, une cravate, une ceinture ou un ceinturon. Note au médecin traitant Pas de traitement particulier. Traitement symptomatique requis. Contacter immédiatement un spécialiste pour le traitement des intoxications, si de grandes quantités ont été ingérées ou inhalées. Ingestion Inhalation Contact avec les yeux : : : : : PREMIERS SECOURS Pour plus de détails sur les conséquences en termes de santé et les symptômes, reportez-vous à la section 11. Protection des sauveteurs : Aucune initiative ne doit être prise qui implique un risque individuel ou en l’absence de formation appropriée. Il peut être dangereux pour la personne assistant une victime de pratiquer le bouche à bouche. Laver abondamment à l'eau les vêtements contaminés avant de les retirer, ou porter des gants. Date d'édition/Date de révision : 11/4/2009. 2/9 ARALDITE CW 1312 CH MESURES DE LUTTE 5. CONTRE L'INCENDIE En présence d'incendie, circonscrire rapidement le site en évacuant toute personne se trouvant près des lieux de l'accident. Aucune initiative ne doit être prise qui implique un risque individuel ou en l’absence de formation appropriée. Ce produit est nocif pour les organismes aquatiques. L'eau du réseau d'extinction d'incendie qui a été contaminée par ce produit doit être conservée en milieu fermé et ne doit être déversée ni dans le milieu aquatique, ni aucun égout ou conduit d'évacuation. Risque lié aux produits de décomposition thermique Risques particuliers liés à l’exposition au produit L’augmentation de pression résultant d’un incendie ou d’une exposition à des températures élevées peut provoquer l’explosion du conteneur. Les pompiers devront porter un équipement de protection approprié ainsi qu'un appareil de protection respiratoire autonome avec masque intégral fonctionnant en mode pression positive. Équipement de protection spécial pour le personnel préposé à la lutte contre l'incendie Utiliser un agent extincteur approprié pour étouffer l'incendie avoisinant. Moyens d'extinction : : : Aucun connu. Utilisables : Non utilisables : La combustion produit des fumées nauséabondes et toxiques., Oxydes de carbone. Précautions relatives à l'environnement Précautions individuelles Arrêter la fuite si cela ne présente aucun risque. Écarter les conteneurs de la zone de déversement accidentel. S'approcher des émanations face au vent. Bloquer toute pénétration possible dans les égouts, les cours d’eau, les caves ou les zones confinées. Laver le produit répandu dans une installation de traitement des effluents ou procéder comme suit. Contenir les fuites et les ramasser à l'aide de matières absorbantes non combustibles telles que le sable, la terre, la vermiculite, la terre à diatomées. Les placer ensuite dans un récipient pour élimination conformément à la réglementation locale (voir section 13). Élimination par une entreprise autorisée de collecte des déchets. Les matériaux absorbants contaminés peuvent présenter les mêmes risques que le produit répandu. Nota : Voir section 1 pour le contact en cas d'urgence et voir section 13 pour l'élimination des déchets. 6. MESURES À PRENDRE EN CAS DE REJET ACCIDENTEL : : Aucune initiative ne doit être prise qui implique un risque individuel ou en l’absence de formation appropriée. Évacuer les environs. Empêcher l'accès aux personnes non requises et ne portant pas de vêtements de protection. NE PAS TOUCHER ni marcher dans le produit répandu. Éviter de respirer les vapeurs ou le brouillard. Assurer une ventilation adéquate. Porter un appareil de protection respiratoire approprié lorsque le système de ventilation est inadéquat. Revêtir un équipement de protection individuelle approprié (voir Section 8). Évitez la dispersion des matériaux déversés, ainsi que leur écoulement et tout contact avec le sol, les cours d'eau, les égouts et conduits d'évacuation. Informez les autorités compétentes en cas de pollution de l'environnement (égouts, voies d'eau, sol et air) par le produit. Matière propre à polluer l’eau. Grand déversement accidentel : Arrêter la fuite si cela ne présente aucun risque. Écarter les conteneurs de la zone de déversement accidentel. Diluer avec de l'eau et éponger si la matière est soluble dans l'eau ou absorber avec un matériau sec inerte et placer dans un contenant à déchets approprié. Élimination par une entreprise autorisée de collecte des déchets. Petit déversement accidentel : Méthodes de nettoyage Manipulation 7. MANIPULATION ET STOCKAGE Revêtir un équipement de protection individuelle approprié (voir Section 8). Il est interdit de manger, boire ou fumer dans les endroits où ce produit est manipulé, entreposé ou mis en oeuvre. Il est recommandé au personnel de se laver les mains et la figure avant de manger, boire ou fumer. Les personnes ayant des antécédents de sensibilisation cutanée ne doivent pas intervenir dans les processus utilisant ce produit. Ne pas mettre en contact avec les yeux, la peau ou les vêtements. Ne pas ingérer. Éviter de respirer les vapeurs ou le brouillard. Garder dans le conteneur d'origine ou dans un autre conteneur de substitution homologué fabriqué à partir d'un matériau compatible et tenu hermétiquement clos lorsqu'il n'est pas utilisé. Les : Date d'édition/Date de révision : 11/4/2009. 3/9 ARALDITE CW 1312 CH MANIPULATION 7. ET STOCKAGE Stockage conteneurs vides retiennent des résidus de produit et peuvent présenter un danger. Ne pas réutiliser ce conteneur. Matériaux d'emballage Stocker conformément à la réglementation locale. Stocker dans le récipient d'origine à l'abri de la lumière directe du soleil dans un endroit sec, frais et bien ventilé à l'écart des matériaux incompatibles (cf. la section 10). Garder le récipient hermétiquement fermé lorsque le produit n'est pas utilisé. Les récipients ayant été ouverts doivent être refermés avec soin et maintenus en position verticale afin d'éviter les fuites. Ne pas stocker dans des conteneurs non étiquetés. Utiliser un récipient approprié pour éviter toute contamination du milieu ambiant. : Recommandé : Utiliser le récipient d'origine. Température de stockage : Stocker conformément à la réglementation locale. Stocker dans le récipient d'origine à l'abri de la lumière directe du soleil dans un endroit sec, frais et bien ventilé à l'écart des matériaux incompatibles (cf. la section 10). Garder le récipient hermétiquement fermé lorsque le produit n'est pas utilisé. Les récipients ayant été ouverts doivent être refermés avec soin et maintenus en position verticale afin d'éviter les fuites. Ne pas stocker dans des conteneurs non étiquetés. Utiliser un récipient approprié pour éviter toute contamination du milieu ambiant. Stocker entre les températures suivantes: 2 à 40°C (35.6 à 104°F). Classe de danger de stockage Huntsman Advanced Materials : Classe de stockage 12, Liquide non dangereux Nom des composants Limites d'exposition professionnelle Procédures de surveillance recommandées Valeurs limites d'exposition Si ce produit contient des ingrédients présentant des limites d'exposition, il peut s'avérer nécessaire d'effectuer un examen suivi des personnes, de l'atmosphère sur le lieu de travail ou des organismes vivants pour déterminer l'efficacité de la ventilation ou d'autres mesures de contrôle ou évaluer le besoin d'utiliser du matériel de protection des voies respiratoires. Il importe de vous reporter à la norme européenne EN 689 concernant les méthodes pour évaluer l'exposition par inhalation aux agents chimiques et aux documents de politique générale nationaux relatifs aux méthodes pour déterminer les substances dangereuses. 8. CONTRÔLE DE L'EXPOSITION/PROTECTION INDIVIDUELLE Aucune valeur de limite d'exposition connue. : Contrôle de l'exposition professionnelle : Aucune ventilation particulière requise. Une bonne ventilation générale devrait être suffisante pour contrôler l'exposition du technicien aux contaminants en suspension dans l'air. Si ce produit contient des composants pour lesquels des contraintes liées à l'exposition existent, utiliser des enceintes de protection, une ventilation locale par aspiration, ou d'autres moyens de contrôle automatiques intégrés afin de maintenir le seuil d'exposition du technicien inférieur aux les limites recommandées ou légales. Se laver abondamment les mains, les avant-bras et le visage après avoir manipulé des produits chimiques, avant de manger, de fumer et d'aller aux toilettes ainsi qu'à la fin de la journée de travail. Il est recommandé d'utiliser les techniques appropriées pour retirer les vêtements potentiellement contaminés. Laver les vêtements contaminés avant de les réutiliser. S'assurer que les dispositifs rince-oeil automatiques et les douches de sécurité se trouvent à proximité de l'emplacement des postes de travail. Contrôle de l'exposition Mesures d'hygiène : Date d'édition/Date de révision : 11/4/2009. 4/9 ARALDITE CW 1312 CH 8. CONTRÔLE DE L'EXPOSITION/PROTECTION INDIVIDUELLE Porter un appareil de protection respiratoire muni d'un purificateur d'air ou à adduction d' air, parfaitement ajusté et conforme à une norme en vigueur si une évaluation du risque indique que cela est nécessaire. Le choix de l'appareil de protection respiratoire doit être fondé sur les niveaux d'expositions prévus ou connus, les dangers du produit et les limites d'utilisation sans danger de l'appareil de protection respiratoire retenu. Utiliser une protection oculaire conforme à une norme approuvée dès lors qu'une évaluation du risque indique qu'il est nécessaire d'éviter l'exposition aux projections de liquides, aux fines particules pulvérisées ou aux poussières. Protection des yeux Protection respiratoire : : Protection de la peau L'équipement de protection personnel pour le corps devra être choisi en fonction de la tâche à réaliser ainsi que des risques encourus, et il est recommandé de le faire valider par un spécialiste avant de procéder à la manipulation du produit. : Contrôle de l'exposition de l'environnement : Il importe de tester les émissions provenant des systèmes de ventilation ou du matériel de fabrication pour vous assurer qu'elles sont conformes aux exigences de la législation sur la protection de l'environnement. Dans certains cas, il sera nécessaire d'équiper le matériel de fabrication d'un épurateur de gaz ou d'un filtre ou de le modifier techniquement afin de réduire les émissions à des niveaux acceptables. Alcool éthylvinylique laminé (EVAL), caoutchouc butyle Matériaux pour gants pour utilisation à long Protection des mains : terme (BTT>480 min): Matériaux pour gants pour utilisation à court terme/projection (10 min200°C (>392°F) PROPRIÉTÉS PHYSIQUES ET CHIMIQUES État physique Point d'ébullition Pression de vapeur Liquide. [Pâte.] <0.00001 kPa (<0.000075 mm Hg) Odeur Faible Couleur Blanc à crème Point d'éclair Coupe fermée: >200°C (>392°F) [DIN 51758 EN 22719 (Pensky-Martens Closed Cup)] 9. Viscosité Dynamique: 15000 à 22000 mPa·s (15000 à 22000 cP) : : : : : : : Informations générales Aspect Informations importantes relatives à la santé, à la sécurité et à l'environnement 25 deg C 20 deg C Masse volumique : 1.85 à 1.87 g/cm3 [20°C (68°F)] Solubilité dans l'eau : pratiquement insoluble Température de décomposition : >200°C (>392°F) Conditions à éviter Aucune donnée spécifique. STABILITÉ ET RÉACTIVITÉ Stabilité chimique Le produit est stable. 10. acides forts, bases fortes, agents oxydants forts : : Matières à éviter : Risque de réactions dangereuses : Dans des conditions normales de stockage et d'utilisation, aucune réaction dangereuse ne se produit. Date d'édition/Date de révision : 11/4/2009. 5/9 ARALDITE CW 1312 CH STABILITÉ 10. ET RÉACTIVITÉ Produits de décomposition dangereux Dans des conditions normales de stockage et d'utilisation, aucun produit de décomposition dangereux ne devrait apparaître. : La combustion produit des fumées nauséabondes et toxiques., Oxydes de carbone. Non disponible. Non disponible. Effets chroniques potentiels pour la santé 11. INFORMATIONS TOXICOLOGIQUES Effets aigus potentiels sur la santé Inhalation : Aucun effet important ou danger critique connu. Ingestion : Aucun effet important ou danger critique connu. Contact avec la peau : Peut entraîner une sensibilisation par contact avec la peau. Contact avec les yeux : Aucun effet important ou danger critique connu. Une fois sensibilisé, une vive réaction allergique peut éventuellement se déclencher lors d'une exposition ultérieure à de très faibles niveaux. Effets chroniques : Cancérogénicité : Aucun effet important ou danger critique connu. Mutagénicité : Aucun effet important ou danger critique connu. Tératogénicité : Aucun effet important ou danger critique connu. Toxicité aiguë ARALDITE CW 1312 CH DL50 Orale Rat >5000 mg/kg - Nom du produit/composant Résultat Espèces Dosage Exposition Conclusion/Résumé : Non disponible. Toxicité chronique Conclusion/Résumé : Non disponible. Cancérogénicité Conclusion/Résumé : Non disponible. Mutagénicité Conclusion/Résumé : Non disponible. Tératogénicité Conclusion/Résumé : Non disponible. Toxicité pour la reproduction Conclusion/Résumé : Non disponible. Effets sur le développement : Aucun effet important ou danger critique connu. Effets sur la fertilité : Aucun effet important ou danger critique connu. Signes/symptômes de surexposition Ingestion Inhalation Aucune donnée spécifique. : Aucune donnée spécifique. : Irritation/Corrosion Conclusion/Résumé : Non disponible. Sensibilisant ARALDITE CW 1312 CH peau cobaye Sensibilisant Nom du produit/composant Voie d'exposition Espèces Résultat Conclusion/Résumé : Non disponible. Toxicocinétique Absorption : Distribution : Métabolisme : Non disponible. Élimination : Non disponible. Date d'édition/Date de révision : 11/4/2009. 6/9 ARALDITE CW 1312 CH INFORMATIONS 11. TOXICOLOGIQUES Peau Les symptômes néfastes peuvent éventuellement comprendre ce qui suit: irritation rougeur : Yeux : Aucune donnée spécifique. 12. INFORMATIONS ÉCOLOGIQUES Autres effets nocifs : Aucun effet important ou danger critique connu. Écotoxicité en milieu aquatique Conclusion/Résumé : Non disponible. Biodégradabilité Conclusion/Résumé : Non disponible. Effets sur l'environnement : Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. 13. CONSIDÉRATIONS RELATIVES À L'ÉLIMINATION 070208 Catalogue Européen des Déchets : Déchets Dangereux : Il se peut que la classification du produit satisfasse les critères de déchets dangereux. Il est recommandé d'éviter ou réduire autant que possible la production de déchets. Les conteneurs vides ou les saches internes peuvent retenir des restes de produit. Ne se débarrasser de ce produit et de son récipient qu'en prenant toutes précautions d'usage. Élimination des produits excédentaires et non recyclables par une entreprise autorisée de collecte des déchets. La mise au rebut de ce produit, des solutions et des sous-produits devra en permanence respecter les exigences légales en matière de protection de l'environnement et de mise au rebut des déchets ainsi que les exigences de toutes les autorités locales. Évitez la dispersion des matériaux déversés, ainsi que leur écoulement et tout contact avec le sol, les cours d'eau, les égouts et conduits d'évacuation. Méthodes d'élimination des : déchets 07 02 08* autres résidus de réaction et résidus de distillation Il faut dans tous les cas appliquer toutes les lois locales régionales et nationales ainsi que les directives européennes. Il appartient à l'utilisateur final de déterminer le code des déchets spécifique à chaque secteur industriel en utilisant le code Européen approprié du catalogue européen des déchets. Il est recommandé que tous les détails soient indiqués par le responsable des déchets. 14. Réglementation internationale du transport INFORMATIONS RELATIVES AU TRANSPORT Informations réglementaires Numéro ONU Classes Groupe d'emballage Étiquette Autres informations Non - - réglementé. Classe ADR/RID Classe IMDG Not regulated. - - Emergency schedules (EmS) Not - - - regulated. Classe IATA - Date d'édition/Date de révision : 11/4/2009. 7/9 ARALDITE CW 1312 CH INFORMATIONS 15. RÉGLEMENTAIRES Conseils de prudence S24- Éviter le contact avec la peau. S37- Porter des gants appropriés. R43- Peut entraîner une sensibilisation par contact avec la peau. R52/53- Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. Symbole(s) de danger Phrases de risque Réglementations de l'Union Européenne Réglementations nationales Contient du (de la) : : : : Phrases d'avertissement supplémentaire : Non applicable. Irritant produit de réaction: bisphénol-A-épichlorhydrine; résines époxydiques (poids moléculaire moyen < 700) diglycidylether de polypropyleneglycol Déterminés en accord avec les directives de l'UE 67/548/EEC et 1999/45/EC (y compris les amendements), la classification et l'étiquetage prennent en compte l'usage prévu du produit. Surveillance médicale renforcée : Arrêté du 11 Juillet 1977 fixant la liste des travaux nécessitant une surveillance médicale renforcée: non concerné Réglementations Internationales Listes internationales : Inventaire des substances chimiques d'Australie (AICS): Tous les composants sont répertoriés ou exclus. Inventaire des substances chimiques existantes en Chine (IECSC): Tous les composants sont répertoriés ou exclus. Inventaire du Japon (ENCS): Tous les composants sont répertoriés ou exclus. Inventaire du Japon (ISHL): Indéterminé. Inventaire de Corée (KECI): Un composant au moins n'est pas répertorié. Inventaire néo-zélandais des substances chimiques (NZIoC): Indéterminé. Inventaire des substances chimiques des Philippines (PICCS): Tous les composants sont répertoriés ou exclus. Inventaire des États-Unis (TSCA 8b): Tous les composants sont répertoriés ou exclus. Inventaire d'Europe: Tous les composants sont répertoriés ou exclus. Inventaire du Canada: Tous les composants sont répertoriés ou exclus. Xi Etiquetage exceptionnel pour préparations spéciales : Contient des composés époxydiques. Voir les informations transmises par le fabricant. AUTRES DONNÉES 11/4/2009. Historique 16. Date d'impression : R36/38- Irritant pour les yeux et la peau. R43- Peut entraîner une sensibilisation par contact avec la peau. R51/53- Toxique pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. R52/53- Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. Texte complet des phrases : R citées dans les sections 2 et 3 - France Référence du texte complet des classifications se trouvant dans les Sections 2 et 3 - France : Xi - Irritant N - Dangereux pour l'environnement Epoxy Resins and Curing Agents; Toxicology, Health, Safety and Environmental Aspects (Plastics Europe, May 2006) Références Date d'édition/Date de révision : 11/4/2009. 8/9 ARALDITE CW 1312 CH 16. AUTRES DONNÉES Date d'édition/ Date de révision Version Avis au lecteur Date de la précédente édition : : : Indique quels renseignements ont été modifiés depuis la version précédente. 11/4/2009. Aucune validation antérieure. 1 Les informations et recommandations figurant dans cette publication sont fondées sur notre expérience générale et sont fournies de bonne foi au mieux de nos connaissances actuelles, MAIS RIEN DANS LES PRESENTES NE DOIT ÊTRE INTERPRETE COMME CONSTITUANT UNE GARANTIE OU UNE DECLARATION, EXPRESSE, IMPLICITE OU AUTRE. DANS TOUS LES CAS, IL INCOMBE A L'UTILISATEUR DE DETERMINER ET DE VERIFIER L'EXACTITUDE, AINSI QUE LE CARACTERE SUFFISANT ET APPLICABLE DE TELLES INFORMATIONS ET RECOMMANDATIONS, DE MEME QUE L'ADEQUATION ET L'ADAPTATION D'UN QUELCONQUE PRODUIT A UNE UTILISATION SPECIFIQUE OU DANS UN BUT PARTICULIER. LES PRODUITS MENTIONNES PEUVENT PRESENTER DES RISQUES INCONNUS ET DOIVENT ETRE UTILISES AVEC PRECAUTION. MEME SI CERTAINS RISQUES SONT DECRITS DANS CETTE PUBLICATION, IL N'EXISTE AUCUNE GARANTIE QU'IL S'AGIT DES SEULS RISQUES EXISTANTS. Les risques, la toxicité et le comportement des produits peuvent différer lorsque ceux-ci sont utilisés avec d'autres matériaux et dépendent des conditions de fabrication et d'autres processus. Ces risques, cette toxicité et ces comportements doivent être déterminés par l'utilisateur et portés à la connaissance des personnes ou entités chargés du transport ou de la manutention, du traitement ou de la transformation, ainsi que de tous utilisateurs finaux. Pour toute demande, contactez le bureau commercial Huntsman Sales le plus proche ou directement Huntsman (Belgium) BVBA, Everslaan 45, B-3078 Everberg, Belgique. Tél. +32 2 758 9211 - Fax +32 758 9946. Huntsman Belgium (BVBA) Everslaan 45 B-3078 Everberg Belgium Tel.:+32-(0)2-758-9211 NO PERSON OR ORGANIZATION EXCEPT A DULY AUTHORIZED HUNTSMAN EMPLOYEE IS AUTHORIZED TO PROVIDE OR MAKE AVAILABLE DATA SHEETS FOR HUNTSMAN PRODUCTS. DATA SHEETS FROM UNAUTHORIZED SOURCES MAY CONTAIN INFORMATION THAT IS NO LONGER CURRENT OR ACCURATE. NO PART OF THIS DATA SHEET MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM, OR BY ANY MEANS, WITHOUT PERMISSION IN WRITING FROM HUNTSMAN. ALL REQUESTS FOR PERMISSION TO REPRODUCE MATERIAL FROM THIS DATA SHEET SHOULD BE DIRECTED TO HUNTSMAN, MANAGER, PRODUCT SAFETY AT THE ABOVE ADDRESS. Date d'édition/Date de révision : 11/4/2009. 9/9 FICHE DE DONNEES DE SECURITE Page : 1 Edition révisée n° : 6 BA ISO 9001 version 2008 Date : 17/4/2009 GALVA A FROID MAT Remplace la fiche : 21/10/2008 005801 www.lisam.com êF F+ : Extrêmement inflammable Producteur ITW Spraytec 5 bis, rue Retrou F-92600 Asnières sur Seine France Tel : 01.40.80.32.32 - Fax : 01.40.80.32.30 infofds@itwpc.com 1 IDENTIFICATION DE LA SUBSTANCE / PRÉPARATION ET DE LA SOCIÉTÉ / ENTREPRISE Nom commercial : GALVA A FROID MAT Identification du produit : Aérosol. Type de produit : Peinture. Identification de la société : Voir producteur. N° de téléphone en cas d'urgence : INRS : 01.45.42.59.59 2 IDENTIFICATION DES DANGERS Phrases relatives aux dangers : Extrêmement inflammable. Lors de l'utilisation, formation possible de mélange vapeur-air inflammable/explosif. Mode d'exposition dominant : Inhalation. Symptômes liés à l'utilisation - Inhalation : Essoufflement. Somnolence. Maux de tête. - Contact avec la peau : Le contact répété ou prolongé avec la peau peut provoquer une irritation. Peut provoquer un dessèchement ou gerçure de la peau. - Contact avec les yeux : Irritant au contact direct avec les yeux. Rougeur. Douleur. - Ingestion : L'ingestion de ce produit peut présenter un danger pour la santé. 3 COMPOSITION / INFORMATIONS SUR LES COMPOSANTS Ce produit est considéré comme dangereux et contient des composants dangereux. Nom de la substance Contenance (%) No CAS / No CE / Numéro index Symbole(s) Phrase(s) R Butane : 20 à 60 % 106-97-8 / 203-448-7 / 601-004-00-0 F+ 12 Propane : 10 à 30 % 74-98-6 / 200-827-9 / 601-003-00-5 F+ 12 Acétone : 1 à 20 % 67-64-1 / 200-662-2 / 606-001-00-8 F Xi 11-36-66-67 Xylène : 1 à 12,5 % 1330-20-7 / 215-535-7 / 601-022-00-9 Xn 10-20/21-38 Zinc en poudre - poussières de zinc ( : 1 à 30 % 7440-66-6 / 231-175-3 / 030-001-00-1 F N 15-17-50/53 stabilisés) 1-nitropropane : < 5 % 108-03-2 / 203-544-9 / 609-001-00-6 Xn 10-20/21/22 Nitroéthane : < 5 % 79-24-3 / 201-188-9 / 609-035-00-1 Xn 10-20/22 Oxyde de zinc : < 5 % 1314-13-2 / 215-222-5 / 030-013-00-7 N 50/53 Butanol : < 1 % 71-36-3 / 200-751-6 / 603-004-00-6 Xn 10-22-37/38-41- 67 ITW Spraytec 5 bis, rue Retrou F-92600 Asnières sur Seine France FICHE DE DONNEES DE SECURITE Page : 2 Edition révisée n° : 6 BA ISO 9001 version 2008 Date : 17/4/2009 GALVA A FROID MAT Remplace la fiche : 21/10/2008 005801 www.lisam.com 4 PREMIERS SECOURS Premiers secours - Inhalation : En cas de malaise par suite d'exposition, transporter immédiatement la victime à l'air frais. Mettre la victime au repos. Appeler un médecin. - Contact avec la peau : Enlever vêtements et chaussures contaminés. Laver abondamment la peau avec de l'eau savonneuse. - Contact avec les yeux : Rincer immédiatement et abondamment à l'eau. Consulter un médecin si l'indisposition ou l'irritation se développe. - Ingestion : Ingestion peu probable. Rincer la bouche. Consulter immédiatement un médecin. 5 MESURES DE LUTTE CONTRE L'INCENDIE Risques spécifiques : Les vapeurs se mélangent facilement à l'air en formant des mélanges explosifs. L'exposition à la chaleur ou la contamination par certaines impuretés peut provoquer une décomposition produisant des gaz très volatils, d'où un risque de surpression pouvant provoquer une violente rupture de conteneurs fermés. Moyens d'extinction - Agents d'extinction appropriés : Poudre. Dioxyde de carbone. Mousse. Brouillard d'eau. - Agents d'extinction non appropriés : Ne pas utiliser un fort courant d'eau. Protection contre l'incendie : Ne pas pénétrer dans la zone de feu sans équipement de protection, y compris une protection respiratoire. Procédures spéciales : Refroidir les conteneurs exposés par pulvérisation ou brouillard d'eau. 6 MESURES À PRENDRE EN CAS DE DISPERSION ACCIDENTELLE Précautions individuelles : Fournir une protection adéquate aux équipes de nettoyage. Précautions pour l'environnement : Avertir les autorités si le produit pénètre dans les égouts ou dans les eaux du domaine public. Méthodes de nettoyage : Ecarter toute source d'ignition. Nettoyer dès que possible tout épandage, en le récoltant au moyen d'un produit absorbant. Diluer les résidus et rincer. Sur le sol, balayer ou pelleter dans des conteneurs de rejet adéquats. Les mélanges de déchets contenant du propane/butane ne doivent pas pénétrer dans les canalisations ou les égouts où des vapeurs pourraient s'accumuler et s'enflammer. 7 MANIPULATION ET STOCKAGE Précautions lors du maniement et de : Conserver à l'écart de toute source d'ignition - Ne pas fumer. l'entreposage Stockage : Protéger du gel. Conserver à une température ne dépassant pas 50° C. Conserver dans un endroit sec, frais et bien ventilé. Prendre des précautions spéciales pour éviter des charges d'électricité statique. Ne pas fumer. Stockage - à l'abri de : Rayons directs du soleil. Sources de chaleur. Etincelles. Flamme nue. Manipulation : Produit à manipuler en suivant une bonne hygiène industrielle et des procédures de sécurité. Conserver à l'écart des aliments et boissons y compris ceux pour animaux. 8 CONTRÔLE DE L'EXPOSITION / PROTECTION INDIVIDUELLE Protection individuelle - Protection respiratoire : Aucun équipement de protection respiratoire n'est requis dans des conditions normales d'utilisation prévue avec une ventilation adéquate. - Protection des mains : Gants. Le choix d'un gant approprié est non seulement dépendant du matériel, mais aussi d'autres critères de qualité, qui peuvent varier d'un fabricant à l'autre. Puisque le produit représente une préparation composée de plusieurs substances, la résistance des matériaux de gants ne peut pas être calculée d'avance et doit être contrôlée avant l'utilisation. Le temps de pénétration exact du matériau des gants est à déterminer par le fabricant des gants de protection et à respecter. - Protection de la peau : Porter un vêtement de protection approprié. ITW Spraytec 5 bis, rue Retrou F-92600 Asnières sur Seine France FICHE DE DONNEES DE SECURITE Page : 3 Edition révisée n° : 6 BA ISO 9001 version 2008 Date : 17/4/2009 GALVA A FROID MAT Remplace la fiche : 21/10/2008 005801 www.lisam.com 8 CONTRÔLE DE L'EXPOSITION / PROTECTION INDIVIDUELLE (suite) - Protection des yeux : Lunettes de sécurité. Hygiène industrielle : Prévoir une ventilation suffisante pour réduire les concentrations de poussières et/ ou de vapeurs. Ne pas manger, ne pas boire et ne pas fumer pendant l'utilisation. Limites d'exposition professionnelle : Butane : VME (ppm) : 800 Butane : VME (mg/m3) : 1900 Acétone : VME (mg/m3) : 1210 Acétone : VME (ppm) : 500 Xylène : VME (ppm) : 50 Xylène : VME (mg/m3) : 221 Xylène : VLE (ppm) : 100 Xylène : VLE (mg/m3) : 442 Butanol : VLE (ppm) : 50 Butanol : VLE (mg/m3) : 150 Oxyde de zinc : VME (mg/m3) : 10 1-nitropropane : VME (mg/m3) : 90 1-nitropropane : VME (ppm) : 25 Nitroéthane : VME (mg/m3) : 310 Nitroéthane : VME (ppm) : 100 9 PROPRIÉTÉS PHYSIQUES ET CHIMIQUES Aspect : Liquide. Couleur : Gris(e). Odeur : Aromatique. Point d'ébullition [°C] : < 0°C Densité : 0.70 Solubilité dans : Solvant. Point d'éclair [°C] : < 0°C 10 STABILITÉ ET RÉACTIVITÉ Produits de décomposition dangereux : Aucun(es) dans des conditions normales. La décomposition thermique génère : Dioxyde de carbone. Monoxyde de carbone. Fumées toxiques. Oxydes d'azote. Réactions dangereuses : Lors de l'utilisation, peut former des mélanges vapeur-air inflammables/explosifs. Matières à éviter : Acides forts. Bases fortes. Oxydants forts. Conditions à éviter : Chaleur. Rayons directs du soleil. Flamme nue. Etincelles. 11 INFORMATIONS TOXICOLOGIQUES Informations toxicologiques : Aucune donnée disponible. Toxicité aiguë : Aucune donnée disponible. Toxicité chronique - Inhalation : L'inhalation de vapeurs peut irriter les voies respiratoires. L'inhalation de vapeurs peut provoquer somnolence et vertiges. Maux de tête. Vertige. - Cutanée : L'exposition répétée peut provoquer déssèchement ou gerçures de la peau. - Oculaire : Le contact direct avec les yeux est probablement irritant. Sensation de brûlure. - Ingestion : L'ingestion peut provoquer des nausées, vomissements et diarrhée. 12 INFORMATIONS ÉCOLOGIQUES * Sur le produit : Toxique pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. ITW Spraytec 5 bis, rue Retrou F-92600 Asnières sur Seine France FICHE DE DONNEES DE SECURITE Page : 4 Edition révisée n° : 6 BA ISO 9001 version 2008 Date : 17/4/2009 GALVA A FROID MAT Remplace la fiche : 21/10/2008 005801 www.lisam.com 13 CONSIDÉRATIONS RELATIVES À L'ÉLIMINATION Généralités :Récipient sous pression - Ne pas percer ou brûler même après usage. S'il n'est pas vide éliminer ce récipient dans un centre de collecte des déchets dangereux ou spéciaux. Détruire conformément aux règlements de sécurité locaux/nationaux en vigueur. Ne pas jeter les résidus à l'égout. 14 INFORMATIONS RELATIVES AU TRANSPORT Shipping name : UN1950 AÉROSOLS, 2.1, 5F No ONU : 1950 Transport terrestre ADR/RID : Groupe d'emballage : 5F Classe : 2 Transport par mer - Code IMO-IMDG : Classe 2.1 - N° de fiche de sécurité : 2-13 - IMDG-Pollution marine : Non. Transport aérien - IATA - Classe ou division : Classe 2.1 - Etiquette IATA : Flamm. Gas 15 INFORMATIONS RÉGLEMENTAIRES - Symbole(s) F N : F+ : Extrêmement inflammable - Phrase(s) R : R12 : Extrêmement inflammable. R51/53 : Toxique pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. - Phrase(s) S : S2 : Conserver hors de portée des enfants. S16 : Conserver à l'écart de toute flamme ou source d'étincelles - Ne pas fumer. S23 : Ne pas respirer les aérosols. S29 : Ne pas jeter les résidus à l'égout. S46 : En cas d'ingestion, consulter immédiatement un médecin et lui montrer l'emballage ou l'étiquette. S51 : Utiliser seulement dans des zones bien ventilées. Conseils de sécurité : Récipient sous pression. A protéger contre les rayons solaires et à ne pas exposer à une température supérieure à 50°C. Ne pas percer ou brûler même après usage. Ne pas vaporiser vers une flamme ou un corps incandescent. Utiliser cet aérosol uniquement pour les applications auxquelles il est destiné. France : Tableaux des maladies professionnelles prévus à l'article R, 461-3 du code du travail. Tableau n°84 - Affections engendrées par les solvants organiques liquides à usage professionnel. Tableau n° 4 BIS : Affections gastro-intestinales provoquées par le benzène, le toulène, les xylènes et tous les produits en renfermant. 16 AUTRES INFORMATIONS Utilisations recommandées & : Voir fiche technique pour des informations détaillées. restrictions Texte des Phrases R du § 3 : R10 : Inflammable. R11 : Facilement inflammable. R12 : Extrêmement inflammable. R15 : Au contact de l'eau dégage des gaz très inflammables. R17 : Spontanément inflammable à l'air. R20/21 : Nocif par inhalation et par contact avec la peau. R20/21/22 : Nocif par inhalation, par contact avec la peau et par ingestion. ITW Spraytec 5 bis, rue Retrou F-92600 Asnières sur Seine France FICHE DE DONNEES DE SECURITE Page : 5 Edition révisée n° : 6 BA ISO 9001 version 2008 Date : 17/4/2009 GALVA A FROID MAT Remplace la fiche : 21/10/2008 005801 www.lisam.com 16 AUTRES INFORMATIONS (suite) R20/22 : Nocif par inhalation et par ingestion. R22 : Nocif en cas d'ingestion. R36 : Irritant pour les yeux. R37/38 : Irritant pour les voies respiratoires et la peau. R38 : Irritant pour la peau. R41 : Risque de lésions oculaires graves. R50/53 : Très toxique pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. R66 : L'exposition répétée peut provoquer déssèchement ou gerçures de la peau. R67 : L'inhalation de vapeurs peut provoquer somnolence et vertiges. Autres données : Révision - Voir : * Le contenu et le format de cette fiche de données de sécurité sont conformes au RÈGLEMENT (CE) N° 1907/2006 DU PARLEMENT EUROPÉEN ET DU CONSEIL DENEGATION DE RESPONSABILITE Les informations contenues dans cette fiche proviennent de sources que nous considérons être dignes de foi. Néanmoins, elles sont fournies sans aucune garantie, expresse ou tacite, de leur exactitude. Les conditions ou méthodes de manutention, stockage, utilisation ou élimination du produit sont hors de notre contrôle et peuvent ne pas être du ressort de nos compétences. C'est pour ces raisons entre autres que nous déclinons toute responsabilité en cas de perte, dommage ou frais occasionnés par ou liés d'une manière quelconque à la manutention, au stockage, à l'utilisation ou à l'élimination du produit. Cette FDS a été rédigée et doit être utilisée uniquement pour ce produit. Si le produit est utilisé en tant que composant d'un autre produit, les informations s'y trouvant peuvent ne pas être applicables. Fin du document ITW Spraytec 5 bis, rue Retrou F-92600 Asnières sur Seine France Supercapacitors Can Replace a Backup Battery for Power Ride-Through Applications − Design Note 450 Jim Drew 09/08/450 Figure 1. 5V Ride-Through Application Circuit Delivers 20W for 1.42 seconds Introduction Supercapacitors (or ultracapacitors) are fi nding their way into an increasing number of applications for short-term energy storage and applications that require intermittent high energy pulses. One such application is a power ridethrough circuit, in which a backup energy source cuts in and powers the load if the main power supply fails for a short time. This type of application has typically been dominated by batteries, but electric double layer capacitors (EDLCs) are fast making inroads as their price-per-farad, size and effective series resistance per capacitance (ESR/C) continue to decrease. Figure 1 shows a 5V power ride-through application where two series-connected 10F, 2.7V supercapacitors charged to 4.8V can support 20W for over a second. The LTC3225, a new charge-pump-based supercapacitor charger, is used to charge the supercapacitors at 150mA and maintain cell balancing while the LTC4412 provides automatic switchover between the supercapacitor and the main supply. The LTM4616 dual output DC/DC μModuleTM regulator creates the 1.8V and 1.2V outputs. With a 20W load, the output voltages remain in regulation for 1.42 seconds after the main power is removed. Supercapacitor Characteristics A 10F, 2.7V supercapacitor is available in a 10mm × 30mm 2-terminal radial can with an ESR of 25mΩ. One advantage supercapacitors offer over batteries is their long lifetime. A capacitor’s cycle life is quoted as greater than 500,000 cycles, whereas batteries are specifi ed for only a few hundred cycles. This makes the supercapacitor an ideal “set and forget” device, requiring little or no maintenance. Two critical parameters of a supercapacitor in any application are cell voltage and initial leakage current. Initial leakage current is really dielectric absorption current, which disappears after some time. The manufacturers of supercapacitors rate their leakage current after 100 hours of applied voltage while the initial leakage current in those fi rst 100 hours may be as much as 50 times the specifi ed leakage current. The voltage across the capacitor has a signifi cant effect on its operating life. When used in series, the supercapacitors must have balanced cell voltages to prevent overcharging of one of the series capacitors. Passive cell L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. μModule is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. VIN C+ C– SHDN VSEL COUT CX GND PROG LTC3225 C2 10F 2.7V C3 10F 2.7V R2 470k Q1 Si4421DY Q2 Si4421DY R1 12k C1 1μF C4 2.2μF 5V C5 22μF VIN GND CTL SENSE GATE STAT LTC4412 R3 4.78k R4 10k VIN1 VIN2 GND LTM4616 C6 100μF C8 100μF C7 100μF VOUT1 FB1 ITHM1 VOUT2 FB2 ITHM2 VOUT1 = IO1 = 7A 1.8V VOUT2 = IO2 = 6A 1.2V © LINEAR TECHNOLOGY CORPORATION 2007 dn450 LT/TP 0908 246K • PRINTED IN THE USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com For applications help, call (978) 656-3768 Data Sheet Download www.linear.com balancing, where a resistor is placed across the capacitor, is a popular and simple technique. The disadvantage of this technique is that the capacitor discharges through the balancing resistor when the charging circuit is disabled. The rule of thumb for this scheme is to set the balancing resistor to 50 times the worst case leakage current, estimated at 2μA/Farad. Given these parameters, a 10F, 2.5V supercapacitor would require a 2.5k balancing resistor. This resistor would drain 1mA of current from the supercapacitor when the charging circuit is disabled. A better alternative is to use a non-dissipative active cell balancing circuit, such as the LTC3225, to maintain cell voltage. The LTC3225 presents less than 4μA of load to the supercapacitor when in shutdown mode and less than 1μA when input power is removed. The LTC3225 features a programmable charging current of up to 150mA, charging two series supercapacitors to either 4.8V or 5.3V while balancing the individual capacitor voltages. To provide a constant voltage to the load, a DC/DC converter is required between the load and the supercapacitor. As the voltage across the supercapacitor decreases, the current drawn by the DC/DC converter increases to maintain constant power to the load. The DC/DC converter drops out of regulation when its input voltage reaches the minimum operating voltage (VUV). To estimate the requirements for the supercapacitor, the effective circuit resistance (RT) needs to be determined. RT is the sum of the capacitors’ ESRs plus the circuit distribution resistances, as follows: RT =ESR+RDIST Assuming 10% of the input power is lost in the effective circuit resistance when the DC/DC converter is at the minimum operating voltage, the worst case RT is: R V T MAX P UV IN ( ) . • = 0 1 2 The voltage required across the supercapacitor at the minimum operating voltage of the DC/DC converter is: V V P R C UV V UV IN T UV ( ) • = 2+ The required effective capacitance can then be calculated based on the required ride-through time (TRT), and the initial voltage on the capacitor (VC(0)) and VC(UV) shown by: C P T V V EFF IN RT C CUV = − 2 0 2 2 • • ( ) ( ) The effective capacitance of a series-connected bank of capacitors is the effective capacitance of a single capacitor divided by the number of capacitors while the total ESR is the sum of all the series ESRs. The ESR of a supercapacitor decreases with increasing frequency. Manufacturers usually specify the ESR at 1kHz, while some manufacturers publish both the value at DC and at 1kHz. The capacitance of supercapacitors also decreases as frequency increases and is usually specifi ed at DC. The capacitance at 1kHz is about 10% of the value at DC. When using a supercapacitor in a ride-through application where the power is being sourced for seconds to minutes, use the effective capacitance and ESR measurements at a low frequency, such at 0.3Hz. Figure 2 shows the ESR effect manifested as a 180mV drop in voltage when input power is removed. Conclusion Supercapacitors can meet the needs of power ride-through applications where the time requirements are in the seconds to minutes range. Supercapacitors offer long life, low maintenance, light weight and environmentally friendly solutions when compared to batteries. To this end, the LTC3225 provides a compact, low noise solution for charging and cell balancing series-connected supercapacitors, without degrading performance. 5V SUPERCAPACITOR RIDE-THROUGH VIN = 5V, VCAP = 4.8V, POWER = 20W 5V INPUT (1V/DIV) 1.8V OUTPUT (500mV/DIV) 1.2V OUTPUT (500mV/DIV) VCAP (1V/DIV) 180mV STEP DUE TO ESR 1.42 SECONDS 800ms/DIV Figure 2. 5V Ride-Through Application Timing I n d u s t r i e Réf ft005801 FICHE PRODUIT ET D'INFORMATIONS TECHNIQUES GALVA MAT Revêtement de protection anticorrosion Cette fiche technique a été établie le 30/03/09 et annule toutes les fiches précédentes. Les renseignements fournis sont basés sur nos connaissances et expérience à ce jour. L’attention des utilisateurs est attirée sur les risques éventuels encourus lorsque le produit est utilisé à d’autres usages que ceux pour lesquels il est conçu. Elle ne dispense en aucun cas l’utilisateur de connaître et d’appliquer l’ensemble des textes réglementant son activité. Il prendra sous sa seule responsabilité les précautions liées à l’utilisation qu’il fait du produit. Les Fiches Techniques & Fiches de Données de Sécurité sont disponibles sur Internet : http://www.itwpc.com ITW Spraytec - 5 bis rue Retrou - 92600 ASNIÈRES SUR SEINE -  01.40.80.32.32 Fax 01.40.80.32.40 1. CARACTERISTIQUES PRINCIPALES GALVA MAT est un agent de protection anti-corrosion, délivré en aérosol. Il est constitué d’additifs, de poudre de zinc de haute pureté et de résines synthétiques en dispersion dans des solvants. Il résiste ainsi 3000 heures au brouillard salin. Le zinc agit par protection électrochimique tandis que les résines synthétiques forment une barrière physique résistante aux agressions extérieures. GALVA MAT présente une remarquable adhérence sur support métallique grâce aux promoteurs d’adhérence incorporés dans sa formulation. Ses propriétés anti-corrosion sont excellentes grâce à la présence de zinc et d’agents anti-corrosion complémentaires dans le film sec. Ce dernier résiste à des températures montant jusqu'à 350°C. 2. DOMAINE D'APPLICATION Bâtiment : Protection des charpentes métalliques, couvertures, huisseries métalliques, pylônes, portes de garage, vérandas, abris de jardin, pattes d'ancrage... Sanitaire, Plomberie : Protection des tuyauteries, canalisations, chaudières, cuves, réservoirs, raccords, brides, boulonneries... Automobile : Protection des bas de caisse, pots d'échappement, bas de portières, crochets d'attelage, remorques, châssis de caravanes, intérieur des ailes, jerrycans... La protection peut servir de finition gris mat mais peut également servir d'apprêt pour être recouverte par d'autres peintures de finition de la gamme COLORJELT (Peintures de retouche professionnelle à la teinte exacte). 3. UTILISATION - MODE D'EMPLOI  Secouer l'aérosol tête en bas, vigoureusement de manière à décoller la bille de l'amalgame de zinc. La surface à traiter doit être exempte de graisse, de produit gras, et débarrassée de la rouille labile.  Pulvériser à environ 20-30 cm de la surface en couches croisées. Attendre 15 à 20 minutes pour la deuxième couche. Le séchage complet intervient sous 24 heures.  Purger l'aérosol tête en bas. En cas de bouchage, le diffuseur peut être nettoyé à l'acétone. 4. CARACTERISTIQUES PHYSICO-CHIMIQUES  Aspect : liquide épais gris conduisant à un film mat par séchage  Odeur : solvantée  Densité du produit actif à 20°C : 0,74 g/cm3  Test de résistance au brouillard salin : 3000 heures (test ASTM B117)  Pouvoir couvrant : 3 à 4 m² pour une protection optimale  Gaz propulseur : mélange d'hydrocarbures  Pureté du zinc : 99%  Epaisseur d’une couche :  35 μm  Vieillissement du zinc en atmosphère marine : 2 à 5 microns par année 5. PRECAUTIONS D'EMPLOI Consulter la fiche de données de sécurité. Récipient sous pression. Ne pas vaporiser vers une flamme ou un corps incandescent. Ne pas fumer. Conserver hors de la portée des enfants. 6. CONDITIONNEMENT ET STOCKAGE Aérosol de 650/500ml net (12 aérosols / carton). Référence 005801. A protéger contre les rayons solaires et à ne pas exposer à une température supérieure à 50°C. Conserver à l'écart de toute flamme, source d'étincelles ou d'ignition. Ne pas percer ou brûler après usage. Conserver à l'abri de l'humidité dans un endroit bien ventilé. Stocker à une température supérieure à 5°C. Current Transducer HAIS 50..400-P and HAIS 50..100-TP For the electronic measurement of currents : DC, AC, pulsed, mixed, with a galvanic isolation between the primary circuit (high power) and the secondary circuit (electronic circuit). All Data are given with a RL = 10 kW Electrical data Primary nominal Primary current, Type RoHS since current rms measuring range date code IPN (A) IPM (A) 50 ± 150 HAIS 50-P, HAIS 50-TP1) 45231, 46272 100 ± 300 HAIS 100-P, HAIS 100-TP1) 45231, 46012 150 ± 450 HAIS 150-P 46172 200 ± 600 HAIS 200-P 45231 400 ± 600 HAIS 400-P planned VOUT Output voltage (Analog) @ IP VREF ±(0.625·IP/IPN) V IP = 0 VREF ± 0.025 V VREF Reference voltage 2) - Output voltage 2.5 ± 0.025 V VREF Output impedance typ. 200 W VREF Load impedance ³ 200 kW R L Load resistance ³ 2 kW ROUT Output internal resistance < 10 W CL Capacitive loading < 1 μF VC Supply voltage (± 5 %) 5 V IC Current consumption @ VC = 5 V 22 mA Accuracy - Dynamic performance data X Accuracy 3) @ IPN , TA = 25°C £ ± 1 % of IPN eL Linearity error 0 .. 3 x IPN £ ± 0.5 % of IPN TCVOE Temperature coefficient of VOE @ IP = 0 £ ± 0.3 mV/K TCVREF Temperature coefficient of VREF £ ± 0.01 %/K TCVOUT / VREF Temperature coefficient of VOUT / VREF @ IP = 0 £ ± 0.2 mV/K TCVOUT Temperature coefficient of VOUT £ ± 0.05% of reading/K VOM Magnetic offset voltage@ IP = 0, after an overload of 3 x IPN DC < ± 0.4 % of IPN tra Reaction time @ 10 % of IPN < 3 μs tr Response time to 90 % of IPN step < 5 μs di/dt di/dt accurately followed > 100 A/μs Vno Output voltage noise (DC ..10 kHz) < 15 mVpp (DC .. 1 MHz) < 40 mVpp BW Frequency bandwidth (-3 dB) 4) DC .. 50 kHz Features · Hall effect measuring principle · Galvanic isolation between primary and secondary circuit · Isolation test voltage 2500V · Low power consumption · Single power supply +5V · Fixed offset & gain · Bus bar version available for 50A and 100A ratings. · Isolated plastic case recognized according to UL94-V0. Advantages · Small size and space saving · Only one design for wide current ratings range · High immunity to external interference. · VREF. IN/OUT Applications · AC variable speed drives · Static converters for DC motor drives · Battery supplied applications · Uninterruptible Power Supplies (UPS) · Switched Mode Power Supplies (SMPS) · Power supplies for welding applications. Application domain · Industrial IPN = 50 .. 400 A Notes : 1) -TP version is equipped with a primary bus bar. 2) It is possible to overdrive VREF with an external reference voltage between 2 - 2.8 V providing its ability to sink or source approximately 2.5 mA. 3) Excluding offset and hysteresis. 4) Small signal only to avoid excessive heatings of the magnetic core. 070827/7 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 1/3 Current Transducer HAIS 50..400-P and HAIS 50..100-TP General data TA Ambient operating temperature - 40 .. + 85 °C TS Ambient storage temperature - 40 .. + 85 °C m Mass (in brackets : TP version) 20 (30) g Standards EN 50178: 1997 Isolation characteristics Vb Rated isolation voltage rms 300 V rms with IEC 61010-1 standards and following conditions - Single insulation - Over voltage category III - Pollution degree 2 - Heterogeneous field Vb Rated isolation voltage rms 600 V rms with EN 50178 standards and following conditions - Reinforced insulation - Over voltage category III - Pollution degree 2 - Heterogeneous field Vd Rms voltage for AC isolation test, 50 Hz, 1 min 2.5 kV Ve Partial discharge extinction voltage rms @ 10pC HAIS 50..400-P > 1 kV HAIS 50..100-TP > 1.4 kV Vw Impulse withstand voltage 1.2/50 μs 8 kV dCp Creepage distance > 8 mm dCl Clearance distance > 8 mm CTI Comparative tracking index (Group I) > 600 If insulated cable is used for the primary circuit, the voltage category could be improved with the following table : Cable insulation (primary) Category HAR 03 450V CAT III HAR 05 550V CAT III HAR 07 650V CAT III 070827/7 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 2/3 Safety This transducer must be used in electric/electronic equipment with respect to applicable standards and safety requirements in accordance with the following manufacturer's operating instructions. Caution! Risk of electrical shock When operating the transducer, certain parts of the module can carry hazardous voltage (eg. primary busbar, power supply). Ignoring this warning can lead to injury and/or cause serious damage. This transducer is a built-in device, whose conducting parts must be inaccessible after installation. A protective housing or additional shield could be used. Main supply must be able to be disconnected. 0.5 8 16 15 33 29 3 3.5 2-D1.0 1.5 6.5 11 6 14.5 11 33 29 0.5 2-D1.0 10 14.5 11 1.5 6.5 11 14 1.5 1.5 3 3.5 6 25.9 19.9 4 1 4 1 5 5 6 6 Terminal Pin Identification Recommended connection circuit 1...+5V HAIS 50..400-P HAIS 50..100-TP 2...0V 3...OUTPUT 4...Vref. (IN/OUT) 5...Core Earth 6...NC. 1 2 3 4 5 +5V 0V OUTPUT Vref. (IN/OUT) 47nF 47nF 4.3 3-P1.8 4.3 3-P1.8 4-0.25x0.45 (*) 4.7nF Front view Front view Right view Bottom view Bottom view (*) should be connected to 0V of Power Supply for better dv/dt immunity. Arrow indicates positive current direction. General tolerance : ±0.2mm Unit : mm Recommended PCB hole Pin 1-4 : 0.7 ±0.1mm Pin 5-6 : 1.5 ±0.1mm Primary bus bar : 2.3 ±0.1mm Ip 0V Vref.(IN/OUT) Vout +Vc Operation Principle Required Connection Circuit Dimensions HAIS 50..400-P and HAIS 50..100-TP (in mm. 1 mm = 0.0394 inch) 070827/7 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 3/3 120425/12 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 1/3 IPN = 50 .. 400 A Features ●● Hall effect measuring principle ●● Galvanic isolation between primary and secondary circuit ●● Isolation voltage 2500 V ●● Low power consumption ●● Wide power supply: ± 12 ..15 V ●● Primary bus bar option for 50 A and 100 A version for ease of connection Advantages ●● Small size and space saving ●● Only one design for wide current ratings range ●● High immunity to external interference. Applications ●● AC variable speed drives ●● Static converters for DC motor drives ●● Battery supplied applications ●● Uninterruptible Power Supplies (UPS) ●● Switched Mode Power Supplies (SMPS) ●● Power supplies for welding applications Application domain ●● Industrial Current Transducer HTB 50 .. 400 - P and HTB 50 .. 100 - TP For the electronic measurement of currents: DC, AC, pulsed..., with a galvanic isolation between the primary circuit (high power) and the secondary circuit (electronic circuit). Electrical data Primary nominal Primary current Type current rms measuring range IPN (A) IPM (A) ± 50 ± 150 HTB 50-P, HTB 50-TP1) ± 100 ± 300 HTB 100-P, HTB 100-TP1) ± 150 ± 450 HTB 150-P ± 200 ± 500 HTB 200-P ± 300 ± 600 HTB 300-P ± 400 ± 600 HTB 400-P VC Supply voltage (± 5 %) 2) ± 12 ..15 V IC Current consumption ± 15 mA Vd Rms voltage for AC isolation test, 50 Hz, 1 min 2.5 kV RIS Isolation resistance @ 500 VDC > 500 MW VOUT Output voltage (Analog)@ ± IPN, RL = 10kW, TA = 25°C ± 4 V ROUT Output internal resistance 100 W RL Load resistance > 10 kW Accuracy - Dynamic performance data X Accuracy @ IPN, TA = 25°C (excluding offset) < ± 1 % of IPN eL Linearity error (0 .. ± IPN) < ± 1 % of IPN VOE Electrical offset voltage @ TA = 25°C < ± 30 mV VOH Hysteresis offset voltage @ IP = 0; after an excursion of 1 x IPN < ± 1 % of IPN TCVOE Temperature coefficient of VOE HTB 50-(T)P < ± 2.0 mV/K HTB 100-(T)P .. 400-P < ± 1.0 mV/K TCVOUT Temperature coefficient of VOUT (% of reading) < ± 0.1 %/K tr Response time to 90% of IPN step < 3 μs BW Frequency bandwidth (- 3 dB) 3) DC .. 50 kHz General data TA Ambient operating temperature - 40 .. + 80 °C TS Ambient storage temperature - 40 .. + 85 °C m Mass < 30 ( < 36) g Standards EN 50178 : 1997 2 pins of Ø2mm diameter are available on transducer for PCB soldering Notes : 1) -TP version is equipped with a primary bus bar. 2) Operating at ±12V ≤ Vc < ±15V will reduce the measuring range. 3) Derating is needed to avoid excessive core heating at high frequency. 120425/12 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 2/3 Current Transducer HTB 50 .. 400-P and HTB 50 .. 100-TP Isolation characteristics Vd Rms voltage for AC isolation test, 50 Hz, 1 min 2.5 kV Ve Partial discharge extinction voltage rms @ 10pC > 500 V Vw Impulse withstand voltage 1.2/50 μs 4 kV dCp Creepage distance > 4.5 mm dCl Clearance distance > 4.5 mm CTI Comparative tracking index (Group IIIa) 275 Application examples According to EN 50178 and CEI 61010-1 standards and following conditions : - Over voltage category III - Pollution degree 2 - Heterogeneous field EN 50178 IEC 61010-1 Single isolation 300 V 300 V Reinforced isolation 150 V 150 V Safety This transducer must be used in electric/electronic equipment with respect to applicable standards and safety requirements in accordance with the manufacturer’s operating instructions. Caution, risk of electrical shock When operating the transducer, certain parts of the module can carry hazardous voltage (eg. primary busbar, power supply). Ignoring this warning can lead to injury and/or cause serious damage. This transducer is a built-in device, whose conducting parts must be inaccessible after installation. A protective housing or additional shield could be used. Main supply must be able to be disconnected. 120425/12 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 3/3 Dimensions HTB 50 .. 400-P and HTB 50 .. 100-TP (in mm. 1 mm = 0.0394 inch) 第一视角 第三视角 第一视角 第三视角 第一视角 第三视角 第一视角 第三视角 100507/11 www.lem.com Page 1/3 Current Transducer HAIS 50..400-P and HAIS 50..100-TP For the electronic measurement of currents: DC, AC, pulsed..., with a galvanic isolation between the primary circuit (high power) and the secondary circuit (electronic circuit). Primary nominal Primary current Type RoHS since current rms measuring range date code IPN (A) IPM (A) 50 ± 150 HAIS 50-P, HAIS 50-TP 1) 45231, 46272 100 ± 300 HAIS 100-P, HAIS 100-TP 1) 45231, 46012 150 ± 450 HAIS 150-P 46172 200 ± 600 HAIS 200-P 45231 400 ± 600 HAIS 400-P 47096 VOUT Output voltage (Analog) @ IP VOE ± (0.625· IP/IPN) V GTH Theoretical sensitivity 0.625 V/IPN VREF Reference voltage 2) - Output voltage 2.5 ± 0.025 V VREF Output impedance typ. 200 W VREF Load impedance ≥ 200 kW RL Load resistance ≥ 2 kW ROUT Output internal resistance < 5 W CL Capacitive loading (± 20 %) =4.7 nF VC Supply voltage (± 5 %)3) 5 V IC Current consumption @ VC = 5 V 19 mA X Accuracy 4) @ IPN , TA = 25°C ≤ ± 1 % of IPN εL Linearity error 0 .. IPM ≤ ± 0.5 % of IPN TCVOE Temperature coefficient of VOE ≤ ± 0.3 mV/K TCVREF Temperature coefficient of VREF, +25°C...+85°C ≤ ± 0.01 %/K -40°C...+25°C ≤ ± 0.015 %/K TCVOE/VREFTemperature coefficient of VOE / VREF ≤ ± 0.2 mV/K TCG Temperature coefficient of G ≤ ± 0.05 % of reading/K VOE Electrical offset voltage @ IP = 0, TA = 25°C VREF ± 0.025 V VOM Magnetic offset voltage @ IP = 0, after an overload of IPM HAIS 50-(T)P < ± 0.5 % of IPN HAIS 100-(T)P..400-P < ± 0.4 % of IPN tra Reaction time @ 10 % of IPN < 3 μs tr Response time to 90 % of IPN step < 5 μs di/dt di/dt accurately followed > 100 A/μs Vno Output voltage noise (DC ..10 kHz) < 15 mVpp (DC .. 1 MHz) < 40 mVpp BW Frequency bandwidth (- 3 dB) 5) DC .. 50 kHz Notes: 1)-TP version is equipped with a primary bus bar. 2) It is possible to overdrive VREF with an external reference voltage between 1.5 - 2.8 V providing its ability to sink or source approximately 5 mA. 3) Maximum supply voltage (not operating) < 6.5 V 4) Excluding Offset and Magnetic offset voltage. 5) Small signal only to avoid excessive heatings of the magnetic core. LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. IPN = 50 .. 400 A Features ●● Hall effect measuring principle ●● Galvanic isolation between primary and secondary circuit ●● Isolation test voltage 2500V ●● Low power consumption ●● Single power supply +5V ●● Fixed offset & gain ●● Bus bar version available for 50A and 100A ratings. ●● Isolated plastic case recognized according to UL94-V0. Advantages ●● Small size and space saving ●● Only one design for wide current ratings range ●● High immunity to external interference. ●● VREF. IN/OUT Applications ●● AC variable speed drives ●● Static converters for DC motor drives ●● Battery supplied applications ●● Uninterruptible Power Supplies (UPS) ●● Switched Mode Power Supplies (SMPS) ●● Power supplies for welding applications. Application domain ●● Industrial All data are given with a RL = 10 kW Accuracy - Dynamic performance data Electrical data 100507/11 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 2/3 Current Transducer HAIS 50..400-P and HAIS 50..100-TP TA Ambient operating temperature - 40 .. + 85 °C General data TS Ambient storage temperature - 40 .. + 85 °C m Mass (in brackets : TP version) 20 (30) g Standards EN 50178: 1997 Isolation characteristics Vb Rated isolation voltage rms with EN50178, IEC61010-1 standards at following conditions - Over voltage category III - Pollution degree 2 - Heterogeneous field Vd Rms voltage for AC isolation test, 50 Hz, 1 min 2.5 kV Ve Partial discharge extinction voltage rms @ 10pC HAIS 50..400-P > 1 kV HAIS 50..100-TP > 1.4 kV Vw Impulse withstand voltage 1.2/50 μs 8 kV dCp Creepage distance > 8 mm dCl Clearance distance > 8 mm CTI Comparative tracking index (Group I) > 600 If insulated cable is used for the primary circuit, the voltage category could be improved with the following table : Cable insulation (primary) Category HAR 03 450V CAT III HAR 05 550V CAT III HAR 07 650V CAT III Safety This transducer must be used in electric/electronic equipment with respect to applicable standards and safety requirements in accordance with the manufacturer’s operating instructions. Caution, risk of electrical shock When operating the transducer, certain parts of the module can carry hazardous voltage (eg. primary busbar, power supply). Ignoring this warning can lead to injury and/or cause serious damage. This transducer is a built-in device, whose conducting parts must be inaccessible after installation. A protective housing or additional shield could be used. Main supply must be able to be disconnected. 100507/11 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 3/3 Dimensions HAIS 50..400-P and HAIS 50..100-TP (in mm) 0.5 8 16 15 33 29 3 3.5 2-D1.0 1.5 6.5 11 6 14.5 11 33 29 0.5 2-D1.0 10 14.5 11 1.5 6.5 11 14 1.5 1.5 3 6 3.5 25.9 19.9 4 1 4 1 5 5 6 6 Terminal Pin Identification Recommended connection circuit 1...+5V HAIS 50..400-P HAIS 50..100-TP 2...0V 3...OUTPUT 4...Vref. (IN/OUT) 5...Core Earth 6...NC. 1 2 3 4 5 +5V 0V OUTPUT Vref. (IN/OUT) 47nF 47nF 4.3 3-P1.8 4.3 3-P1.8 4-0.25x0.45 (*) 4.7nF Front view Front view Right view Bottom view Bottom view (*) should be connected to 0V of Power Supply for better dv/dt immunity. Arrow indicates positive current direction. General tolerance : ±0.2mm Unit : mm Recommended PCB hole Pin 1-4 : 0.7 ±0.1mm Pin 5-6 : 1.5 ±0.1mm Primary bus bar : 2.3 ±0.1mm Ip 0V Vref.(IN/OUT) Vout +Vc Operation Principle Required Connection Circuit Dimensions HAIS 50..400-P and HAIS 50..100-TP (in mm. 1 mm = 0.0394 inch) 080821/8 LEM reserves the right to carry out modifications on its transducers, in order to improve them, without prior notice. www.lem.com Page 3/3 I n d u s t r i e Réf ft005411 FICHE PRODUIT ET D'INFORMATIONS TECHNIQUES GRAISSE HAUTES TEMPERATURES Lubrifiant anti-grippant micro-métal Cette fiche technique a été établie le 30/03/09 et annule toutes les fiches précédentes. Les renseignements fournis sont basés sur nos connaissances et expérience à ce jour. L’attention des utilisateurs est attirée sur les risques éventuels encourus lorsque le produit est utilisé à d’autres usages que ceux pour lesquels il est conçu. Elle ne dispense en aucun cas l’utilisateur de connaître et d’appliquer l’ensemble des textes réglementant son activité. Il prendra sous sa seule responsabilité les précautions liées à l’utilisation qu’il fait du produit. Les Fiches Techniques & Fiches de Données de Sécurité sont disponibles sur Internet : http://www.itwpc.com ITW Spraytec - 5 bis rue Retrou - 92600 ASNIÈRES SUR SEINE -  01.40.80.32.32 Fax 01.40.80.32.40 1. CARACTERISTIQUES PRINCIPALES La GRAISSE HAUTES TEMPERATURES est un lubrifiant micro-métal de haute performance pour les cas extrêmes ; elle permet d'assurer une lubrification d'assemblages entre -20°C à +1200°C. Insensible à l'eau et à la corrosion, cette graisse sans silicone apporte en outre des propriétés d'étanchéité, d'anticorrosion, et demeure anti-grippante. 2. DOMAINE D'APPLICATION La GRAISSE HAUTES TEMPERATURES trouve son application dans les domaines suivants :  Joints et clapets de chaudières, brûleurs, régulateurs, convoyeurs,  Pièces automobiles, cosses de batterie, chaînes, câbles, mécanismes de grues,  Industrie chimique, matériels agricoles, travaux publics... 3. UTILISATION - MODE D'EMPLOI Bien agiter l'aérosol de manière à décoller la bille. Éliminer les anciennes graisses, vaporiser par pressions courtes sur les assemblages à protéger. Faire pénétrer la graisse en manoeuvrant les pièces lubrifiées. Après pulvérisation, purger l'aérosol la tête en bas pour éviter un bouchage par les particules métalliques. 4. CARACTERISTIQUES PHYSICO-CHIMIQUES Produit actif :  Aspect : liquide épais couleur métallique  Fluide de base : huile minérale  Viscosité de l'huile : 96 cSt à 40°C  Masse volumique à 20°C : 0.80 g/cm3  Tenue en température : -20°C à +1200°C  Épaississant : inorganique  Point de goutte : sans  Pénétrabilité : 310-340(NLGI 1)  Point d'écoulement : -10°C  Teneur en lubrifiants solides : 16%  Coefficient de friction : inférieur de 30% aux huiles ou graphite  Protection en chaleur humide : 5000 heures à 50°C - 100% H.R.  Inflammable  Ne contient pas de silicone 5. PRECAUTIONS D'EMPLOI Consulter la fiche de données de sécurité. Extrêmement inflammable. Nocif pour les organismes aquatiques, peut entraîner des effets néfastes à long terme pour l'environnement aquatique. L’inhalation de vapeurs peut provoquer somnolence et vertiges. Récipient sous pression. A protéger contre les rayons solaires et ne pas exposer à une température supérieure à 50°C. Ne pas percer ou brûler, même après usage. Conserver hors de portée des enfants. Ne pas vaporiser vers une flamme ou un corps incandescent. Conserver à l’écart de toute flamme ou source d’étincelles – Ne pas fumer. Ne pas respirer les aérosols. En cas de ventilation insuffisante, porter un appareil respiratoire approprié. En cas d’ingestion, consulter immédiatement un médecin et lui montrer l’emballage ou l’étiquette. Utiliser cet aérosol uniquement pour les applications auxquelles il est destiné. Bien ventiler après usage. 6. CONDITIONNEMENT ET STOCKAGE Aérosol de 650ml (12 aérosols / carton). Référence 005411. A protéger contre les rayons solaires et à ne pas exposer à une température supérieure à 50°C. Conserver à l'abri de l'humidité et sous abri, dans un endroit bien ventilé et aéré. http://www.farnell.com/datasheets/319343.pdf Fiche Technique LOCTITE® 542 Mai-2004 DESCRIPTION DU PRODUIT LOCTITE® 542 présente les caractéristiques suivantes: Technologie Acrylique Nature chimique Ester Diméthacrylate Aspect Liquide marronLMS Composants Monocomposant Viscosité Faible Polymérisation Anaérobie Polymérisation secondaire Activateur Application Etanchéité filetée Résistance Moyenne LOCTITE® 542 est conçu pour freiner et étancher les tubes et raccords filetés métalliques. Le produit polymérise lorsqu'il se trouve en l'absence d'air entre des surfaces métalliques avec un faible jeu, et il a pour fonction d'empêcher le desserrage et les fuites dus aux chocs et vibrations. Une des propriétés du LOCTITE® 542 est d'être thixotrope, ce qui lui évite de couler ou de migrer après application sur les surfaces. PROPRIETES DU PRODUIT LIQUIDE Densité à 25 °C 1,06 Point éclair - se reporter à la FDS Viscosité, Brookfield - RVT, 25 °C, mPa.s (cP): Mobile 2, vitesse 2,5 tr/min 1 200 à 2 750LMS Mobile 2, vitesse 20 tr/mn 400 à 800LMS Viscosité, EN 12092 MV, 25 °C, après 180 s, mPa.s (cP): Cisaillement 277 s-1 150 DONNEES TYPIQUES SUR LA POLYMERISATION Vitesse de polymérisation en fonction du substrat La vitesse de polymérisation dépend du substrat utilisé. Le graphique ci-dessous montre l'évolution du couple de rupture en fonction du temps sur des boulons M10 en acier, par comparaison avec d'autres métaux, tests effectués selon la norme ISO 10964. % résistance finale sur acier Polymérisation (h) 100 75 50 25 0 1min 5min10min 30min 1h 3h 6h 24h 72h Laiton Acier Acier Zn bichromaté Acier inoxydable Vitesse de polymérisation en fonction du jeu La vitesse de polymérisation dépend du jeu fonctionnel dans l'assemblage. Le jeu dans les assemblages filetés dépend du type de filetage, de la qualité des filets, et des dimensions. Le graphe ci-dessous montre l'évolution de la résistance au cisaillement en fonction du temps sur des éprouvettes axe-bague en acier avec différents jeux contrôlés, tests effectués selon la norme ISO 10123. % résistance finale sur acier Polymérisation (h) 100 75 50 25 0 1min 5min10min 30min 1h 3h 6h 24h 72h 0,15mm 0,25mm 0,05mm Vitesse de polymérisation en fonction de la température La vitesse de polymérisation dépend de la température à l'application. Le graphique ci-dessous présente l'évolution du couple de rupture en fonction du temps à différentes températures sur des boulons M10 en acier, tests effectués selon la norme ISO 10964. % résistance finale sur acier Polymérisation (h) 100 75 50 25 0 1min 5min10min 30min 1h 3h 6h 24h 72h 40°C 22°C 5°C Vitesse de polymérisation en fonction de l'activateur Lorsque la vitesse de polymérisation est beaucoup trop longue, ou que l'on est en présence de jeux importants, l'utilisation d'un activateur appliqué sur l'une des surfaces permettra d'augmenter cette vitesse. Le graphique ci-dessous montre l'évolution du couple de rupture en fonction du temps lors de l'utilisation de Loctite Activateur 7471 (T) ou 7649 (N) sur des boulons M10 en acier zingué bichromaté , tests effectués selon la norme ISO 10964. FT LOCTITE® 542, Mai-2004 % résistance finale sur acier Polymérisation (h) 100 75 50 25 0 1min 5min10min 30min 1h 3h 6h 24h 72h Activateur 7471 T Activateur 7649 N Sans Activateur PROPRIETES DU PRODUIT POLYMERISE Propriétés physiques: Coef. de dilatation linéique , ASTM D 696, K-1 80×10-6 Coef. de conductivité thermique, ASTM C 177, W/(m·K) 0,1 Chaleur spécifique, kJ/(kg·K) 0,3 PERFORMANCES DU PRODUIT POLYMERISE Propriétés de l'adhésif Après 24 heures à 22 °C Couple de dévissage, ISO 10964: Boulons M10 en acier N·m 15 (lb.in.) (130) Couple résiduel au dévissage, ISO 10964: Boulons M10 en acier N·m 9 (lb.in.) (80) Couple de rupture, ISO 10964, pré-charge à 5 N·m: Boulons M10 en acier N·m 25 (lb.in.) (220) Couple résiduel maxi après desserrage, ISO 10964, pré-charge à 5 N·m: Boulons M10 en acier N·m 25 (lb.in.) (220) Résistance au cisaillement, ISO 10123: éprouvettes axe-bague acier N/mm² ≥6,5LMS (psi) (940) PERFORMANCES DE TENUE A L'ENVIRONNEMENT Polymérisation 1 semaine à 22 °C Couple de rupture, ISO 10964, pré-charge à 5 N·m: Boulons M10 acier avec phosphatation zinc Résistance à chaud Mesurée à la température % Résistance , à T amb. Température, °C 100 75 50 25 0 0 50 100 150 Vieillissement à chaud Vieillissement à la température indiquée et mesure effectuée après retour à 22 °C % Résistance , T amb. Heures 100 75 50 25 0 0 1000 2000 3000 4000 5000 120°C 150°C Résistance aux produits chimiques Veillissement dans les conditions indiquées et mesure après retour à 22 °C. % de la résistance initiale conservée après Agent chimique °C 100 h 500 h 1000 h Huile moteur 125 100 100 100 Essence sans plomb 22 100 100 95 Liquide de frein 22 100 100 95 Eau/Glycol 50/50 87 90 90 90 Ethanol 22 100 100 95 Acétone 22 100 80 80 INFORMATIONS GENERALES L'utilisation de ce produit n'est pas recommandé dans des installations véhiculant de l'oxygène pur ou des mélanges riches en oxygène, et il ne doit pas être utilisé comme produit d'étanchéité vis à vis du chlore ou pour d'autres corps fortement oxydants. Pour obtenir les informations relatives à la sécurité de mise en oeuvre de ce produit, consultez obligatoirement la Fiches de Données de Sécurité (FDS). Lorsqu'un système de lavage en phase aqueuse est utilisé pour nettoyer les pièces avant collage, il est important de vérifier la compatibilité de la solution lessivielle avec l'adhésif utilisé. Dans certains cas, les nettoyages en phase aqueuse affectent la polymérisation et les performances de l'adhésif. Henkel Loctite Americas +860.571.5100 Henkel Loctite Europe +49.89.9268.0 Henkel Loctite Asia Pacific +81.45.758.1810 Pour contacter votre representant local ou obtenir une aide technique : www.loctite.com FT LOCTITE® 542, Mai-2004 Ce produit n'est normalement pas recommandé pour l'utilisation sur les plastiques (particulièrement sur les thermoplastiques, sur lesquels peut apparaître une fissuration suite à la libération de contraintes, appelée "stress cracking"). Il est recommandé aux utilisateurs de vérifier la compatibilité de ce produit avec de tels matériaux. Recommandations de mise en oeuvre Assemblage 1. Pour obtenir les meilleurs résultats, les surfaces doivent être propres et exemptes de graisse (surface interne et externe), utiliser un solvant de dégraissage Loctite, puis sécher parfaitement. 2. Dans le cas où le substrat est un métal peu actif, ou si la vitesse de polymérisation est trop lente, vaporiser l'activateur 7471 (T) ou l'activateur 7649 (N) sur tous les filetages, et laisser sécher. 3. Appliquer un cordon à 360° sur le filetage mâle en évitant de mettre du produit sur le premier filet. Appuyer suffisamment de façon à ce que le produit remplisse bien les filets. Dans le cas de filetage de gros diamètre ou grossier, appliquer une quantité de produit plus importante, et déposer aussi un cordon à 360° sur la partie femelle du filetage. 4. Assembler et serrer les parties à raccorder pour obtenir l'alignement souhaité. 5. Après serrage correct de l'assemblage, l'étanchéité est immédiate sous pression modérée. La résistance maximum à la pression ainsi que la résistance aux solvants sont obtenues après un temps de polymérisation de 24 heures minimum. Désassemblage 1. Démonter avec des outils à main conventionnels. 2. Lorsqu'il n'est pas possible de démonter à l'aide d'outils à main conventionnels, du fait d'une longueur d'engagement importante ou pour des filetages de grand diamètre (> 20 mm), il est nécessaire de chauffer localement l'assemblage vers 250 °C, pour démonter à chaud. Nettoyage de l'adhésif 1. Le produit polymérisé peut être éliminé en immergeant la pièce dans un solvant adapté Loctite et en frottant à l'aide d'une brosse métallique. Loctite Material SpecificationLMS LMS en date du Septembre-1, 1995. Les résultats des contrôles pour chaque lot de fabrication sont disponibles pour les caractéristiques identifiées LMS. Les rapports de contrôle LMS mentionnent aussi des contrôles qualité QC en accord avec les spécifications appropriées aux utilisations clients. De plus, des contrôles permanents existent en parallèle pour garantir la qualité du produit et la stabilité de la production. Toute demande spécifique liée à des exigences particulières d'un client sera transmise et gérée par le service Qualité Henkel Loctite. Stockage Conserver le produit dans son emballage d'origine fermé dans un local sec. Certaines informations de stockage peuvent être indiquées sur l'étiquettage de l'emballage. Température de stockage : 8 °C à 21 °C. Une température de stockage inférieure à 8 °C ou supérieure à 28 °C peut affecter les propriétés du produit. Pour éviter de contaminer le produit, ne jamais remettre dans son contenant d'origine un produit sorti de son emballage. Henkel Corporation n'assure aucune responsabilité pour les produits stockés dans d'autres conditions que celles indiquées, ou pour des produits contaminés par une mauvaise utilisation. Pour obtenir des informations supplémentaires, contacter votre Service Technique local ou votre représentant local. Conversions (°C x 1.8) + 32 = °F kV/mm x 25.4 = V/mil mm / 25.4 = inches N x 0.225 = lb N/mm x 5.71 = lb/in N/mm² x 145 = psi MPa x 145 = psi N·m x 8.851 = lb·in N·mm x 0.142 = oz·in mPa·s = cP Note Les données contenues dans ce document sont fournies à titre d'information seulement et sont considérées comme fiables. Nous ne pouvons pas assumer la responsabilité de résultats obtenus par des tiers à partir de méthodes sur lesquelles nous n'avons aucun contrôle. Il est de la responsabilité de l'utilisateur de déterminer l'adéquation à son besoin de toute méthode de production décrite dans ce document, et de mettre en oeuvre toutes les mesures qui s'imposent pour la protection des personnes et des biens contre tous risques pouvant résulter de la mise en oeuvre et de l'utilisation des produits. En fonction de ce qui précède, Henkel Corporation dénie toutes garanties implicites ou explicites, y compris les garanties liées à l'aptitude à la vente ou d'adéquation à un besoin particulier, résultant de la vente ou de l'utilisation de produits de Henkel Corporation. Henkel Corporation dénie notamment toutes poursuites pour des dommages incidents ou conséquents quels qu'ils soient, y compris les pertes financières d'exploitation. La présentation dans ce document de processus ou de composition ne doit pas être interprétée comme le fait qu'ils sont libres de tous brevets détenus par des tiers ainsi que comme une licence de brevet détenue par Henkel Corporation pouvant couvrir de tels procédés ou compositions. Nous recommandons ici à l'utilisateur potentiel de vérifier par des essais l'application envisagée avant de passer à une application répétitive, les données présentées ici ne servant que de guide. Ce produit peut être couvert par un ou plusieurs brevets ou licences ou demandes de brevet tant aux USA que dans d'autres pays. Marque commerciale LOCTITE est une marque de Henkel Corporation Référence 1 Henkel Loctite Americas +860.571.5100 Henkel Loctite Europe +49.89.9268.0 Henkel Loctite Asia Pacific +81.45.758.1810 Pour contacter votre representant local ou obtenir une aide technique : www.loctite.com Une filiale de Premier Farnell Développez avec le meilleur Directive relative aux produits consommant de l’énergie (Eup) Version 6 - Avril 2009 Mise à jour des études menées (phase 1) et détail des 17 études (phase 2) Web: www.global-legislation.com Q&R: glegislation@premierfarnell.com 1 L’éco-conception de la directive (2005/32/CE) relative aux produits consommant de l’énergie (EuP) a été adoptée au sein de l’Union européenne (UE) le 11 août 2005 et transposée en loi nationale par les Etats membres le 11 août 2007. Des mesures de mise en oeuvre spécifiques entreront en application courant 2009 et les années suivantes. Celles-ci impliqueront des obligations pour les fabricants. La première mesure de mise en oeuvre de la directive EuP concerne une réglementation qui est entrée en vigueur en janvier 2009. Cette réglementation EuP devrait avoir un impact significatif sur la phase conception d’une grande diversité de produits électriques. L’objectif principal de la directive EuP est d’apporter des améliorations dans l’efficacité énergétique des produits consommant de l’énergie, sur l’ensemble du cycle de vie, depuis l’extraction de la matière première jusqu’au recyclage en fin de vie. L’accent est mis sur la phase conception, qui est considérée comme l’étape déterminante affectant les ressources utilisées dans un produit. La directive ne s’applique pas aux moyens de transport (avions, automobiles, etc.) mais, à part cette exception, son champ d’application est délibérément étendu, couvrant, en principe, tout produit qui, lors de son utilisation, dépend de, génère, transfère ou mesure l’énergie (électricité, combustible fossile ou renouvelable). EuP est une directive « cadre » qui définit le contexte juridique au sein duquel des mesures d’exécution seront élaborées, visant des groupes de produits spécifiques. Lorsque ces mesures d’exécution seront présentées, elles exposeront clairement les exigences à respecter pour certains types de produits avant leur mise sur le marché au sein de l’UE. Une mesure d’exécution détaillera les exigences en matière de « éco-conception » , telles que les objectifs de consommation énergétique, et la réglementation devra être essentiellement la même dans tous les pays de l’UE, comme pour la directive RoHS (une directive de marché unique). Avant l’application d’une mesure d’exécution pour un secteur de produits particulier (ex., chaudières), il est primordial de se conformer à certains critères afin de s’assurer que celle-ci est réellement nécessaire et profitable. Ces critères sont les suivants : Un produit doit zz se vendre à plus de 200.000 unités par an dans l’UE zz avoir un impact environnemental significatif zz présenter un important potentiel d’évolution Les mesures d’exécution ne doivent pas avoir un « impact négatif significatif » sur zz le prix ou la performance d’un produit, ou zz sur la compétitivité de l’industrie de l’UE Après avoir tenu compte de tout ceci, il est possible que la Commission européenne (CE) décide de ne pas présenter de mesure d’exécution. Cela pourrait se produire dans le cas où elle considère que la croissance de l’industrie est satisfaisante (ex., par des accords volontaires ou des objectifs pour réduire la consommation d’énergie). La directive EuP définit une procédure d’application pour les mesures de mise en oeuvre, mais la Commission européenne a déjà identifié une liste de produits candidats offrant « …un potentiel élevé pour réduire de manière économiquement rentable les gaz à effet de serre », et pour lesquels un accord de mesures d’exécution pourrait intervenir plus tôt. Résumé 2 Des études sont en cours dont une vingtaine déjà finalisées. Il devient évident que la consommation d’énergie en fonctionnement sera l’objectif prioritaire de nombreuses mesures de mise en oeuvre. Plusieurs études ont déjà identifié des points importants en matière d’amélioration, comparé aux produits commercialisés les plus performants. Quand des avantages significatifs sont identifiés et réalisables, cela peut entraîner des mesures de mise en oeuvre. Des réglementations couvrant cinq catégories de produits ont été proposées jusqu’à présent et celle concernant les pertes d’énergie en mode veille et arrêt est déjà appliquée. Autres produits en vue d’une éventuelle inclusion : L’article 16(1) de la directive sur la démarche d’éco-conception impose à la Communauté européenne d’établir un plan d’action définissant pour les trois années à venir une liste indicative d’autres groupes de produits à considérer en priorité en vue de l’adoption de mesures d’exécution. Dans le cadre de ce plan, une évaluation a été réalisée par un groupe d’étude du réseau parlementaire européen d’évaluation technologique (EPTA, Grèce). Celle-ci visait à couvrir et classifier tous les produits consommant de l’énergie (EuP) potentiels. Plus de 1300 EuP ont été répertoriés et classés en 57 catégories. Parmi cellesci, 34 catégories de produits ont été considérées comme prioritaires, selon la directive. Un degré de priorité a donc été défini, avec répartition par groupes : Priorité A (25 catégories – la CE a indiqué qu’elle voulait une liste détaillée) et Priorité B (les 9 catégories restantes). Pour connaitre les dernières mises à jour des études EuP, rendez vous sur le Programme de Transformation du Marché (Market Transformation Programme): www.mtprog.com/cms/eup/ Les produits concernés sont : Statut Chaudières et chaudières mixtes (gaz/mazout/électrique) Radiateurs (gaz/mazout/électrique) Ordinateurs personnels (de bureau & portables) et moniteurs d’ordinateur Equipement d’imagerie : copieurs, fax, imprimantes, scanneurs, appareils multifonctions, etc. Electronique grand public : téléviseurs Pertes en mode veille et éteint des EuP Chargeurs de batterie et sources d’alimentation externes Eclairage des bureaux Eclairage domestique Eclairage public Appareils de climatisation grand public (climatiseurs et ventilateurs) Moteurs électriques 1-150 kW, pompes à eau (dans les bâtiments commerciaux, pompage eau potable, industrie alimentaire, agriculture), systèmes d’aération dans les bâtiments, machines soufflantes pour la ventilation (bâtiments non résidentiels) Réfrigérateurs et congélateurs professionnels, comprenant les compresseurs frigorifiques, meubles présentoir et distributeurs automatiques Réfrigérateurs et congélateurs à usage domestique Lave-vaisselle et lave-linge à usage domestique Petites installations à combustible solide (chauffage, en particulier) Séche-linge Aspirateurs Boîtiers multimédias (Set Top Boxe) Boîtiers de conversion simples pour la télévision numérique C C V V P R P P P P S C P C P P S S S C Symbole Statut / Février 2009 S Etude en cours C Etude achevée P Cadre législatif proposé V Accord volontaire possible R Réglementation UE en place Un « plan d’action » s’appuyant sur les travaux entrepris par Epta, basé à Athènes et qui regroupe des ingénieurs et consultants en environnement, a été adopté et la Commission européenne a annoncé que 17 autres études seraient réalisées selon le même modèle que les 20 études existantes, suivi d’une évaluation de l’impact, d’un débat sur la plate-forme dédiée à l’éco-conception et d’un projet de mesures de mise en oeuvre. Liste des 17 études prévues et contrats attribués concernant 11 d’entre elles : 3 Veuillez noter : Les informations contenues dans ce guide sont de nature générale et non destinées à répondre au cas particulier de toute personne ou entité. Malgré le soin apporté à fournir des informations précises et actuelles, nous ne pouvons pas garantir l’exactitude de ces informations, liée à la date de réception de celles-ci, ou qu’elles continueront à être exactes à l’avenir. Il n’est pas conseillé d’agir sur la base de ces informations sans avoir pris conseil auprès d’un professionnel compétent après un examen approfondi de la situation spécifique. Produits: Statut Equipement de réfrigération et de congélation : armoires frigorifiques, chambres froides, compresseurs frigorifiques, machines à glace, machines à crème glacée et milk-shake, minibars Transformateurs : transformateurs de distribution, transformateurs de puissance Equipement son & image : lecteurs enregistreurs de DVD, vidéoprojecteurs, consoles de jeux vidéo Produits de chauffage individuel Systèmes de chauffage central par air chaud pour la distribution de la chaleur (autre que les systèmes à chaleur et puissance combinées - CHP) Fours à usage domestique et commercial (électriques, gaz, micro-ondes), y compris ceux intégrés aux cuisinières Plaques chauffantes et grills à usage domestique et commercial, y compris ceux intégrés aux cuisinières Lave-linge, sèche-linge et lave-vaisselle à usage professionnel Machines à café hors secteur tertiaire Pertes en mode veille des EuP connectés en réseau Onduleurs et sources d’alimentation ininterrompue (UPS) à usage domestique Systèmes de ventilation et de climatisation Equipement de chauffage électrique et par combustibles fossiles Chaudières et fours industriels et de laboratoire Machines-outils Equipement de stockage de données, traitement de données et de réseau Equipement utilisant de l’eau S S S A A A A A A A A N N N N N N Point sur la situation : février 2009 Contrats attribués à des bureaux d’étude et de consultation : démarrage des projets prévu courant 2009 Appels d’offre pas encore émis si bien que les études ne devraient pas démarrer avant fin 2009, début 2010 S A Version 6. Rédigé en collaboration avec ERA Technology - www.era.co.uk/rfa © 2009 Premier Farnell plc. Toute reproduction intégrale ou partielle de ce document est soumise à l’accord préalable de Premier Farnell plc SMSC EMC1182 Revision 1.0 (07-11-13) DATASHEET PRODUCT FEATURES Datasheet EMC1182 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications General Description The EMC1182 is a high accuracy, low cost, 1.8V System Management Bus (SMBus) compatible temperature sensor. Advanced features such as Resistance Error Correction (REC), Beta Compensation (to support CPU diodes requiring the BJT/transistor model including 65nm and lower geometry processors) and automatic diode type detection combine to provide a robust solution for complex environmental monitoring applications. The ability to communicate at 1.8V SMBus levels provides compatible I/O for the advanced processors found in today’s tablet and smartphone applications. The EMC1182 monitors two temperature channels (one external and one internal), providing ±1°C accuracy for both external and internal diode temperatures. REC automatically eliminates the temperature error caused by series resistance allowing greater flexibility in routing thermal diodes. Frequency hopping* and analog filters ensure remote diode traces can be as far as eight (8) inches without degrading the signal. Beta Compensation eliminates temperature errors caused by low, variable beta transistors common in today's fine geometry processors. The automatic beta detection feature monitors the external diode/transistor and determines the optimum sensor settings for accurate temperature measurements regardless of processor technology. This frees the user from providing unique sensor configurations for each temperature monitoring application. These advanced features plus ±1°C measurement accuracy provide a low-cost, highly flexible and accurate solution for critical temperature monitoring applications. Applications  Notebook Computers  Desktop Computers  Industrial  Embedded applications Features  Support for diodes requiring the BJT/transistor model — Supports 65nm and lower geometry CPU thermal diodes  Pin and register compatible with EMC1412  Automatically determines external diode type and optimal settings  Resistance Error Correction  Frequency hops the remote sample frequency to reject DC converter and other coherent noise sources*  Consecutive Alert queue to further reduce false Alerts  Up to 1 External Temperature Monitor — 25°C typ, ±1°C max accuracy (20°C < TDIODE < 110°C) — 0.125°C resolution — Supports up to 2.2nF diode filter capacitor  Internal Temperature Monitor — ±1°C accuracy — 0.125°C resolution  3.3V Supply Voltage  1.8V SMBus operation  Programmable temperature limits for ALERT/THERM2 (85°C default high limit and 0°C default low limit) and THERM (85°C default)  Available in small 8-pin 2mm x 3mm TDFN RoHS compliant package  Available in small 8-pin 3mm x 3mm DFN RoHS compliant package * Technology covered under the US patent 7,193,543. CPU / GPU EMC1182 Host DP DN SMDATA Thermal Junction SMCLK SMBus Interface THERM / ADDR ALERT / THERM2 Power Control VDD GND VDD = 3.3V 1.8V 1.8V – 3.3V THERM / ADDR ALERT / THERM2 Internal Temp Diode Switching Current Analog Mux Internal Temperature Register Digital Mux Digital Mux Limit Comparator Low Limit Registers High Limit Registers Conversion Rate Register Interupt Masking Status Registers Configuration Register SMBus Interface SMCLK SMDATA DP 1D N1 VDD GND External Temperature ΔΣADC Register(s) THERM Limit Register THERM Hysteresis Register SMBus Address Decode EMC1182 Ordering Information: This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. ORDERING NUMBER PACKAGE FEATURES SMBUS ADDRESS EMC1182-A-AC3-TR 8-pin TDFN 2mm x 3mm (RoHS compliant) Two temperature sensors, ALERT/THERM2 and THERM pins, fixed SMBus address Selectable via THERM pull-up EMC1182-1-AIA-TR 8-pin DFN 3mm x 3mm (RoHS compliant) Two temperature sensors, ALERT/THERM2 and THERM pins, fixed SMBus address 1001_100(r/w) EMC1182-1-AC3-TR 8-pin TDFN 2mm x 3mm (RoHS compliant) Two temperature sensors, ALERT/THERM2 and THERM pins, fixed SMBus address 1001_100(r/w) EMC1182-2-AIA-TR 8-pin DFN 3mm x 3mm (RoHS compliant) Two temperature sensors, ALERT/THERM2 and THERM pins, fixed SMBus address 1001_101(r/w) EMC1182-2-AC3-TR 8-pin TDFN 2mm x 3mm (RoHS compliant) Two temperature sensors, ALERT/THERM2 and THERM pins, fixed SMBus address 1001_101(r/w) Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 2 SMSC EMC1182 DATASHEET Copyright © 2013 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 3 Revision 1.0 (07-11-13) DATASHEET Table of Contents Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 SMBus Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.3 THERM Pin Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.5 SMBus Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.6 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1.7 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.8 SMBus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.9 SMBus and I2C Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 5 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 THERM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.1 THERM Pin Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5 ALERT / THERM2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.1 ALERT / THERM2 Pin InterruptALERT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5.2 ALERT / THERM2 Pin ComparatorTHERM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6.1 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6.2 Resistance Error Correction (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6.3 Programmable External Diode Ideality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.8 Consecutive Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.9 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10 Temperature Measurement Results and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Chapter 6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Data Read Interlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3 Status Register 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 4 SMSC EMC1182 DATASHEET 6.4 Configuration Register 03h / 09h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 Conversion Rate Register 04h / 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 Scratchpad Registers 11h and 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.8 One Shot Register 0Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.9 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.10 Channel Mask Register 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.11 Consecutive ALERT Register 22h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.12 Beta Configuration Register 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.13 External Diode Ideality Factor Register 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.14 Filter Control Register 40h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.15 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.16 SMSC ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.17 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Chapter 7 Typical Operating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 9 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 5 Revision 1.0 (07-11-13) DATASHEET List of Figures Figure 1.1 EMC1182 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2.1 EMC1182 Pin Diagram, TDFN-8 2mm x 3mm / DFN-8 3mm x 3mm . . . . . . . . . . . . . . . . . . . 8 Figure 4.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4.4 Isolating the THERM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5.1 System Diagram for EMC1182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5.2 Isolating THERM Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5.3 Isolating ALERT and SYS_SHDN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5.4 Temperature Filter Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5.5 Temperature Filter Impulse Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8.1 2mm x 3mm TDFN Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 8.3 2mm x 3mm TDFN Package PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 8.2 2mm x 3mm TDFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 8.4 3mm x 3mm DFN Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 8.5 3mm x 3mm DFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 8.6 8 Pin DFN PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 8.7 EMC1182-1 8-Pin TDFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 8.8 EMC1182-2 8-Pin TDFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 8.9 EMC1182-A 8-Pin TDFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 8.10 EMC1182-1 8-Pin DFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 8.11 EMC1182-2 8-Pin DFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 6 SMSC EMC1182 DATASHEET List of Tables Table 2.1 EMC1182 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4.1 SMBus Address Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5.1 Supply Current vs. Conversion Rate for EMC1182 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5.2 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6.5 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6.6 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6.7 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6.8 Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6.9 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 6.10 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 6.11 Consecutive ALERT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.12 Consecutive Alert / Therm Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.13 Beta Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.14 Ideality Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6.15 Ideality Factor Look-Up Table (Diode Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6.16 Substrate Diode Ideality Factor Look-Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.17 Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.18 FILTER Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.19 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.20 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.21 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Internal Temp DiodeSwitchingCurrentAnalog MuxInternal Temperature RegisterDigital MuxDigital MuxLimit ComparatorLow Limit RegistersHigh Limit RegistersConversion Rate RegisterInterupt MaskingStatus RegistersConfiguration RegisterSMBus InterfaceSMCLKSMDATADPDNVDDGNDExternal Temperature Register(s)ΔΣADCTHERM Limit RegisterTHERM Hysteresis RegisterSMBus Address DecodeALERTEMC1182THERM / ADDR Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 7 Revision 1.0 (07-11-13) DATASHEET Chapter 1 Block Diagram Figure 1.1 EMC1182 Block Diagram SMDATASMCLK1234ALERT / THERM2DNTHERM / ADDRGNDExposed padDPVDD8765EMC1182 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 8 SMSC EMC1182 DATASHEET Chapter 2 Pin Description Figure 2.1 EMC1182 Pin Diagram, TDFN-8 2mm x 3mm / DFN-8 3mm x 3mm Table 2.1 EMC1182 Pin Description PIN NUMBER NAME FUNCTION TYPE 1 VDD Power supply Power 2 DP External diode positive (anode) connection AIO 3 DN External diode negative (cathode) connection AIO 4 THERM / ADDR THERM - Active low Critical THERM output signal - requires pull-up resistor OD (5V) ADDR - Selects SMBus address based on pullup resistor OD (5V) 5 GND Ground Power 6 ALERT / THERM2 Active low digital ALERT / THERM2 output signal - requires pull-up resistor OD (5V) 7 SMDATA SMBus Data input/output - requires pull-up resistor DIOD (5V) 8 SMCLK SMBus Clock input - requires pull-up resistor DI (5V) Bottom Pad Exposed Pad Not internally connected, but recommend grounding. - Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 9 Revision 1.0 (07-11-13) DATASHEET The pin types are described Table 2.2. Table 2.2 Pin Types PIN TYPE DESCRIPTION Power This pin is used to supply power or ground to the device. AIO Analog Input / Output -This pin is used as an I/O for analog signals. DI Digital Input - This pin is used as a digital input. This pin is 5V tolerant. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 10 SMSC EMC1182 DATASHEET Chapter 3 Electrical Specifications 3.1 Absolute Maximum Ratings Note: Stresses at or above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3.1 For the 5V tolerant pins that have a pull-up resistor (SMCLK, SMDATA, THERM, and ALERT / THERM2), the pull-up voltage must not exceed 3.6V when the device is unpowered. 3.2 Electrical Specifications Table 3.1 Absolute Maximum Ratings DESCRIPTION RATING UNIT Supply Voltage (VDD) -0.3 to 4.0 V Voltage on 5V tolerant pins (V5VT_pin) -0.3 to 5.5 V Voltage on 5V tolerant pins (|V5VT_pin - VDD|) (see Note 3.1) 0 to 3.6 V Voltage on any other pin to Ground -0.3 to VDD +0.3 V Operating Temperature Range -40 to +125 °C Storage Temperature Range -55 to +150 °C Lead Temperature Range Refer to JEDEC Spec. J-STD-020 Package Thermal Characteristics for TDFN-8 Thermal Resistance (θj-a) 89 °C/W ESD Rating, All pins HBM 2000 V Table 3.2 Electrical Specifications VDD = 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS DC Power Supply Voltage VDD 3.0 3.3 3.6 V Supply Current IDD 200 410 μA 0.0625 conversion / sec, dynamic averaging disabled 215 425 μA 1 conversion / sec, dynamic averaging disabled Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 11 Revision 1.0 (07-11-13) DATASHEET 325 465 μA 4 conversions / sec, dynamic averaging disabled 890 1050 μA 4 conversions / sec, dynamic averaging enabled 1120 μA > 16 conversions / sec, dynamic averaging enabled Standby Supply Current IDD 170 230 μA Device in Standby mode, no SMBus communications, ALERT and THERM pins not asserted. Internal Temperature Monitor Temperature Accuracy ±0.25 ±1 °C -5°C < TA < 100°C ±2 °C -40°C < TA < 125°C Temperature Resolution 0.125 °C External Temperature Monitor Temperature Accuracy ±0.25 ±1 °C +20°C < TDIODE < +110°C 0°C < TA < 100°C ±0.5 ±2 °C -40°C < TDIODE < 127°C Temperature Resolution 0.125 °C Conversion Time all Channels tCONV 190 ms default settings Capacitive Filter CFILTER 2.2 2.7 nF Connected across external diode ALERT / THERM2 and THERM pins Output Low Voltage VOL 0.4 V ISINK = 8mA Leakage Current ILEAK ±5 μA ALERT / THERM2 and SYS_SHDN pins Device powered or unpowered TA < 85°C pull-up voltage < 3.6V Table 3.2 Electrical Specifications (continued) VDD = 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 12 SMSC EMC1182 DATASHEET 3.3 SMBus Electrical Characteristics Table 3.3 SMBus Electrical Specifications VDD = 3.0 to 3.6V, TA = -40°C to 125°C, all typical values are at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS SMBus Interface Input High Voltage VIH 1.4 VDD V 5V Tolerant. Voltage threshold based on 1.8V operation Input Low Voltage VIL -0.3 0.8 V 5V Tolerant. Voltage threshold based on 1.8V operation Leakage Current ILEAK ±5 μA Powered or unpowered TA < 85°C Hysteresis 50 mV Input Capacitance CIN 5 pF Output Low Sink Current IOL 8.2 15 mA SMDATA = 0.4V SMBus Timing Clock Frequency fSMB 10 400 kHz Spike Suppression tSP 50 ns Bus Free Time Stop to Start tBUF 1.3 μs Hold Time: Start tHD:STA 0.6 μs Setup Time: Start tSU:STA 0.6 μs Setup Time: Stop tSU:STO 0.6 μs Data Hold Time tHD:DAT 0 μs When transmitting to the master Data Hold Time tHD:DAT 0.3 μs When receiving from the master Data Setup Time tSU:DAT 100 ns Clock Low Period tLOW 1.3 μs Clock High Period tHIGH 0.6 μs Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line Timeout tTIMEOUT 25 35 ms Disabled by default Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 13 Revision 1.0 (07-11-13) DATASHEET Chapter 4 System Management Bus Interface Protocol 4.1 Communications Protocol The EMC1182 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4.1. For the first 15ms after power-up the device may not respond to SMBus communications. . 4.1.1 SMBus Start Bit The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.1.2 SMBus Address and RD / WR Bit The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit is a logic ‘1’, the SMBus Host is reading data from the client device. The EMC1182-A SMBus slave address is determined by the pull-up resistor on the THERM pin as shown in Table 4.1, "SMBus Address Decode". The Address decode is performed by pulling known currents from VDD through the external resistor causing the pin voltage to drop based on the respective current / resistor relationship. This pin voltage is compared against a threshold that determines the value of the pull-up resistor. Figure 4.1 SMBus Timing Diagram Table 4.1 SMBus Address Decode PULL UP RESISTOR ON THERM PIN (±5%) SMBUS ADDRESS 4.7k 1111_100(r/w)b 6.8k 1011_100(r/w)b SMDATA SMCLK TBUF P S S - Start Condition S P - Stop Condition P T LOW T HIGH T HD:STA T SU:STO T HD:STA T HD:DAT T SU:DAT T SU:STA T FALL T RISE Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 14 SMSC EMC1182 DATASHEET The EMC1182-1 SMBus address is hard coded to 1001_100(r/w). The EMC1182-2 SMBus address is hard coded to 1001_101(r/w). 4.1.3 THERM Pin Considerations Because of the decode method used to determine the SMBus Address, it is important that the pull-up resistance on the THERM pin be within the tolerances shown in Table 4.1. Additionally, the pull-up resistor on the THERM pin must be connected to the same 3.3V supply that drives the VDD pin. For 15ms after power up, the THERM pin must not be pulled low or the SMBus address will not be decoded properly. If the system requirements do not permit these conditions, the THERM pin must be isolated from its hard-wired OR’d bus during this time. One method of isolating this pin is shown in Figure 4.4, "Isolating the THERM pin". 4.1.5 SMBus Data Bytes All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.1.6 SMBus ACK and NACK Bits The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the Write Byte protocol. The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line high after the 8th data bit has been sent. 10k 1001_100(r/w)b 15k 1101_100(r/w)b 22k 0011_100(r/w)b 33k 0111_100(r/w)b Figure 4.4 Isolating the THERM pin Table 4.1 SMBus Address Decode (continued) PULL UP RESISTOR ON THERM PIN (±5%) SMBUS ADDRESS +3.3V Shared THERM 22K 4.7K - 33K +2.5 - 5V EMC1182 8 7 6 5 SMDATA 1 SMCLK 2 3 4 ALERT / ADDR VDD DP DN THERM GND Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 15 Revision 1.0 (07-11-13) DATASHEET 4.1.7 SMBus Stop Bit The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the device detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. 4.1.8 SMBus Timeout The EMC1182 supports SMBus Timeout. If the clock line is held low for longer than tTIMEOUT, the device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see Section 6.11, "Consecutive ALERT Register 22h"). 4.1.9 SMBus and I2C Compatibility The EMC1182 is compatible with SMBus and I2C. The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the EMC1182 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I2C Systems. 1.EMC1182 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2.Minimum frequency for SMBus communications is 10kHz. 3.The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the EMC1182 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4.I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). Attempting to communicate with the EMC1182 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents. Stretching of the SMCLK signal is supported, provided other devices on the SMBus control the timing. 4.2 SMBus Protocols The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address as valid protocols as shown below. All of the below protocols use the convention in Table 4.1. Table 4.1 Protocol Format DATA SENT TO DEVICE DATA SENT TO THE HOST # of bits sent # of bits sent Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 16 SMSC EMC1182 DATASHEET 4.2.1 Write Byte The Write Byte is used to write one byte of data to the registers, as shown in Table 4.2. 4.2.2 Read Byte The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3. 4.2.3 Send Byte The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4. 4.2.4 Receive Byte The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4.5. Table 4.2 Write Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK REGISTER DATA ACK STOP 1 -> 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1 Table 4.3 Read Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK START SLAVE ADDRESS RD ACK REGISTER DATA NACK STOP 1 -> 0 YYYY_ YYY 0 0 XXh 0 1 -> 0 YYYY_ YYY 1 0 XX 1 0 -> 1 Table 4.4 Send Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK STOP 1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 Table 4.5 Receive Byte Protocol START SLAVE ADDRESS RD ACK REGISTER DATA NACK STOP 1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 17 Revision 1.0 (07-11-13) DATASHEET 4.3 Alert Response Address The ALERT output can be used as a processor interrupt or as an SMBus Alert. When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100xb. All devices with active interrupts will respond with their client address as shown in Table 4.6. The EMC1182 will respond to the ARA in the following way: 1.Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2.Set the MASK_ALL bit to clear the ALERT pin. APPLICATION NOTE: The ARA does not clear the Status Register and if the MASK_ALL bit is cleared prior to the Status Register being cleared, the ALERT pin will be reasserted. Table 4.6 Alert Response Address Protocol START ALERT RESPONSE ADDRESS RD ACK DEVICE ADDRESS NACK STOP 1 -> 0 0001_100 1 0 YYYY_YYY 1 0 -> 1 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 18 SMSC EMC1182 DATASHEET Chapter 5 Product Description The is an SMBus temperature sensor. The EMC1182 monitors one internal diode and one externally connected temperature diode. Thermal management is performed in cooperation with a host device. This consists of the host reading the temperature data of both the external and internal temperature diodes of the EMC1182 and using that data to control the speed of one or more fans. The EMC1182 has two levels of monitoring. The first provides a maskable ALERT / THERM2 signal to the host when the measured temperatures exceeds user programmable limits. This allows theEMC1182 to be used as an independent thermal watchdog to warn the host of temperature hot spots without direct control by the host. The second level of monitoring provides a non-maskable interrupt on the THERM pin if the measured temperatures meet or exceed a second programmable limit. Figure 5.1 shows a system level block diagram of the EMC1182. 5.1 Modes of Operation The EMC1182 has two modes of operation.  Active (Run) - In this mode of operation, the ADC is converting on all temperature channels at the programmed conversion rate. The temperature data is updated at the end of every conversion and the limits are checked. In Active mode, writing to the one-shot register will do nothing.  Standby (Stop) - In this mode of operation, the majority of circuitry is powered down to reduce supply current. The temperature data is not updated and the limits are not checked. In this mode of operation, the SMBus is fully active and the part will return requested data. Writing to the oneshot register will enable the device to update all temperature channels. Once all the channels are updated, the device will return to the Standby mode. Figure 5.1 System Diagram for EMC1182 CPU / GPU EMC1182 Host DP DN SMDATA Thermal Junction SMCLK SMBus Interface THERM / ADDR ALERT / THERM2 Power Control VDD GND VDD = 3.3V 1.8V 1.8V – 3.3V Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 19 Revision 1.0 (07-11-13) DATASHEET 5.2 Conversion Rates The EMC1182 may be configured for different conversion rates based on the system requirements.The conversion rate is configured as described in Section 6.5. The default conversion rate is 4 conversions per second. Other available conversion rates are shown in Table 6.6, "Conversion Rate". 5.3 Dynamic Averaging Dynamic averaging causes the EMC1182 to measure the external diode channels for an extended time based on the selected conversion rate. This functionality can be disabled for increased power savings at the lower conversion rates (see Section 6.4, "Configuration Register 03h / 09h"). When dynamic averaging is enabled, the device will automatically adjust the sampling and measurement time for the external diode channels. This allows the device to average 2x or 16x longer than the normal 11 bit operation (nominally 21ms per channel) while still maintaining the selected conversion rate. The benefits of dynamic averaging are improved noise rejection due to the longer integration time as well as less random variation of the temperature measurement. When enabled, the dynamic averaging applies when a one-shot command is issued. The device will perform the desired averaging during the one-shot operation according to the selected conversion rate. When enabled, the dynamic averaging will affect the average supply current based on the chosen conversion rate as shown in Table 5.1. 5.4 THERM Output The THERM output is asserted independently of the ALERT output and cannot be masked. Whenever any of the measured temperatures exceed the user programmed Therm Limit values for the programmed number of consecutive measurements, the THERM output is asserted. Once it has been asserted, it will remain asserted until all measured temperatures drop below the Therm Limit minus the Therm Hysteresis (also programmable). Table 5.1 Supply Current vs. Conversion Rate for EMC1182 CONVERSION RATE AVERAGE SUPPLY CURRENT (TYPICAL) AVERAGING FACTOR (BASED ON 11-BIT OPERATION) ENABLED (DEFAULT) DISABLED ENABLED (DEFAULT) DISABLED 1 / 16 sec 210uA 200uA 16x 1x 1 / 8 sec 265uA 200uA 16x 1x 1 / 4 sec 330uA 200uA 16x 1x 1 / 2 sec 395uA 200uA 16x 1x 1 / sec 460uA 215uA 16x 1x 4 / sec (default) 890uA 325uA 8x 1x 8 / sec 1010uA 630uA 4x 1x 16 / sec 1120uA 775uA 2x 1x 32 / sec 1200uA 1050uA 1x 1x 64 / sec 1400uA 1100uA 0.5x 0.5x Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 20 SMSC EMC1182 DATASHEET When the THERM pin is asserted, the THERM status bits will likewise be set. Reading these bits will not clear them until the THERM pin is deasserted. Once the THERM pin is deasserted, the THERM status bits will be automatically cleared. 5.4.1 THERM Pin Considerations Because of the decode method used to determine the SMBus Address, it is important that the pull-up resistance on THERM pin be within ±10% tolerance. Additionally, the pull-up resistor on the THERMpin must be connected to the same 3.3V supply that drives the VDD pin. For 15ms after power up, the THERM pin must not be pulled low or the SMBus Address will not be decoded properly. If the system requirements do not permit these conditions, the THERM pin must be isolated from the bus during this time. One method of isolating this pin is shown in Figure 5.2. . 5.5 ALERT / THERM2 Output The ALERT / THERM2 pin is an open drain output and requires a pull-up resistor to VDD and has two modes of operation: interrupt mode and comparator mode. The mode of the ALERT / THERM2 output is selected via the ALERT / COMPALERT/THERM bit in the Configuration Register (see Section 6.4). 5.5.1 ALERT / THERM2 Pin InterruptALERT Mode When configured to operate in interrupt mode, the ALERT / THERM2 pin asserts low when an out of limit measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected, functioning as any standard ALERT in on the SMBus. The ALERT / THERM2 pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit condition has been removed, the ALERT / THERM2 pin will remain asserted until the appropriate status bits are cleared. The ALERT/ THERM2 pin can be masked by setting the MASK_ALL bit. Once the ALERT / THERM2pin has been masked, it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any interrupt conditions that occur while the ALERT / THERM2 pin is masked will update the Status Register normally. There are also individual channel masks (see Section 6.10). The ALERT / THERM2 pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave to communicate an error condition to the master. One or more ALERT / THERM2 outputs can be hard-wired together. 5.5.2 ALERT / THERM2 Pin ComparatorTHERM Mode When the ALERT / THERM2 pin is configured to operate in comparator mode, it will be asserted if any of the measured temperatures exceeds the respective high limit, acting as a second THERM function Figure 5.2 Isolating THERM Pin EMC1182 SMDATA SMCLK ALERT VDD DP DN THERM / ADDR GND 1 2 3 4 8 7 6 5 +3.3V Shared THERM 22 K 4.73K3 - K +2.5 - 5V Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 21 Revision 1.0 (07-11-13) DATASHEET in. The ALERT / THERM2 pin will remain asserted until all temperatures drop below the corresponding high limit minus the Therm Hysteresis value. When the ALERT / THERM2 pin is asserted in comparator mode, the corresponding high limit status bits will be set. Reading these bits will not clear them until the ALERT / THERM2 pin is deasserted. Once the ALERT pin is deasserted, the status bits will be automatically cleared. The MASK_ALL bit will not block the ALERT / THERM2 pin in this mode; however, the individual channel masks (see Section 6.10) will prevent the respective channel from asserting the ALERT/ THERM2 pin. 5.6 Temperature Measurement The EMC1182 can monitor the temperature of one externally connected diode. The device contains programmable High, Low, and Therm limits for all measured temperature channels. If the measured temperature goes below the Low limit or above the High limit, the ALERTpin can be asserted (based on user settings). If the measured temperature meets or exceeds the Therm Limit, the THERM pin is asserted unconditionally, providing two tiers of temperature detection. 5.6.1 Beta Compensation The EMC1182 is configured to monitor the temperature of basic diodes (e.g., 2N3904) or CPU thermal diodes. For External Diode 1, it automatically detects the type of external diode (CPU diode or diode connected transistor) and determines the optimal setting to reduce temperature errors introduced by beta variation. Compensating for this error is also known as implementing the transistor or BJT model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C. 5.6.2 Resistance Error Correction (REC) Parasitic resistance in series with the external diodes will limit the accuracy obtainable from temperature measurement devices. The voltage developed across this resistance by the switching diode currents cause the temperature measurement to read higher than the true temperature. Contributors to series resistance are PCB trace resistance, on die (i.e. on the processor) metal resistance, bulk resistance in the base and emitter of the temperature transistor. Typically, the error caused by series resistance is +0.7°C per ohm. The EMC1182 automatically corrects up to 100 ohms of series resistance. 5.6.3 Programmable External Diode Ideality Factor The EMC1182 is designed for external diodes with an ideality factor of 1.008. Not all external diodes, processor or discrete, will have this exact value. This variation of the ideality factor introduces error in the temperature measurement which must be corrected for. This correction is typically done using programmable offset registers. Since an ideality factor mismatch introduces an error that is a function of temperature, this correction is only accurate within a small range of temperatures. To provide maximum flexibility to the user, the EMC1182 provides a 6-bit register for each external diode where the ideality factor of the diode used is programmed to eliminate errors across all temperatures. Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 22 SMSC EMC1182 DATASHEET APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most ideality errors. 5.7 Diode Faults The EMC1182 detects an open on the DP and DN pins, and a short across the DP and DN pins. For each temperature measurement made, the device checks for a diode fault on the external diode channel(s). When a diode fault is detected, the ALERT / THERM2 pin asserts (unless masked, see Section 5.8) and the temperature data reads 00h in the MSB and LSB registers (note: the low limit will not be checked). A diode fault is defined as one of the following: an open between DP and DN, a short from VDD to DP, or a short from VDD to DN. If a short occurs across DP and DN or a short occurs from DP to GND, the low limit status bit is set and the ALERT / THERM2 pin asserts (unless masked). This condition is indistinguishable from a temperature measurement of 0.000°C (-64°C in extended range) resulting in temperature data of 00h in the MSB and LSB registers. If a short from DN to GND occurs (with a diode connected), temperature measurements will continue as normal with no alerts. 5.8 Consecutive Alerts The EMC1182 contains multiple consecutive alert counters. One set of counters applies to the ALERT / THERM2 pin and the second set of counters applies to the THERM pin. Each temperature measurement channel has a separate consecutive alert counter for each of the ALERT / THERM2 and THERM pins. All counters are user programmable and determine the number of consecutive measurements that a temperature channel(s) must be out-of-limit or reporting a diode fault before the corresponding pin is asserted. See Section 6.11, "Consecutive ALERT Register 22h" for more details on the consecutive alert function. 5.9 Digital Filter To reduce the effect of noise and temperature spikes on the reported temperature, the External Diodechannel uses a programmable digital filter. This filter can be configured as Level 1, Level 2, or Disabled (default) (see Section 6.14). The typical filter performance is shown in Figure 5.4 and Figure 5.5. Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 23 Revision 1.0 (07-11-13) DATASHEET Figure 5.4 Temperature Filter Step Response Figure 5.5 Temperature Filter Impulse Response Filter Step Response 0 10 20 30 40 50 60 70 80 90 0 2 4 6 8 10 12 14 Samples Temperature (C) Disabled Level1 Level2 Filter Impulse Response 0 10 20 30 40 50 60 70 80 90 0 2 4 6 8 10 12 14 Samples Temperature (C) Disabled Level1 Level2 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 24 SMSC EMC1182 DATASHEET 5.10 Temperature Measurement Results and Data The temperature measurement results are stored in the internal and external temperature registers. These are then compared with the values stored in the high and low limit registers. Both external and internal temperature measurements are stored in 11-bit format with the eight (8) most significant bits stored in a high byte register and the three (3) least significant bits stored in the three (3) MSB positions of the low byte register. All other bits of the low byte register are set to zero. The EMC1182 has two selectable temperature ranges. The default range is from 0°C to +127°C and the temperature is represented as binary number able to report a temperature from 0°C to +127.875°C in 0.125°C steps. The extended range is an extended temperature range from -64°C to +191°C. The data format is a binary number offset by 64°C. The extended range is used to measure temperature diodes with a large known offset (such as AMD processor diodes) where the diode temperature plus the offset would be equivalent to a temperature higher than +127°C. Table 5.2 shows the default and extended range formats. Table 5.2 Temperature Data Format TEMPERATURE (°C) DEFAULT RANGE 0°C TO 127°C EXTENDED RANGE -64°C TO 191°C Diode Fault 000 0000 0000 000 0000 0000 -64 000 0000 0000 000 0000 0000 -1 000 0000 0000 001 1111 1000 0 000 0000 0000 010 0000 0000 0.125 000 0000 0001 010 0000 0001 1 000 0000 1000 010 0000 1000 64 010 0000 0000 100 0000 0000 65 010 0000 1000 100 0000 1000 127 011 1111 1000 101 1111 1000 127.875 011 1111 1111 101 1111 1111 128 011 1111 1111 110 0000 0000 190 011 1111 1111 111 1111 0000 191 011 1111 1111 111 1111 1000 >= 191.875 011 1111 1111 111 1111 1111 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 25 Revision 1.0 (07-11-13) DATASHEET Chapter 6 Register Description The registers shown in Table 6.1 are accessible through the SMBus. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. Table 6.1 Register Set in Hexadecimal Order REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE PAGE 00h R Internal Diode Data High Byte Stores the integer data for the Internal Diode 00h Page 27 01h R External Diode Data High Byte Stores the integer data for the External Diode 00h 02h R-C Status Stores status bits for the Internal Diode and External Diode 00h Page 28 03h R/W Configuration Controls the general operation of the device (mirrored at address 09h) 00h Page 28 04h R/W Conversion Rate Controls the conversion rate for updating temperature data (mirrored at address 0Ah) 06h (4/sec) Page 29 05h R/W Internal Diode High Limit Stores the 8-bit high limit for the Internal Diode (mirrored at address 0Bh) 55h (85°C) Page 30 06h R/W Internal Diode Low Limit Stores the 8-bit low limit for the Internal Diode (mirrored at address 0Ch) 00h (0°C) 07h R/W External Diode High Limit High Byte Stores the integer portion of the high limit for the External Diode (mirrored at register 0Dh) 55h (85°C) 08h R/W External Diode Low Limit High Byte Stores the integer portion of the low limit for the External Diode (mirrored at register 0Eh) 00h (0°C) 09h R/W Configuration Controls the general operation of the device (mirrored at address 03h) 00h Page 28 0Ah R/W Conversion Rate Controls the conversion rate for updating temperature data (mirrored at address 04h) 06h (4/sec) Page 29 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 26 SMSC EMC1182 DATASHEET 0Bh R/W Internal Diode High Limit Stores the 8-bit high limit for the Internal Diode (mirrored at address 05h) 55h (85°C) Page 30 0Ch R/W Internal Diode Low Limit Stores the 8-bit low limit for the Internal Diode (mirrored at address 06h) 00h (0°C) 0Dh R/W External Diode High Limit High Byte Stores the integer portion of the high limit for the External Diode (mirrored at register 07h) 55h (85°C) 0Eh R/W External Diode Low Limit High Byte Stores the integer portion of the low limit for the External Diode (mirrored at register 08h) 00h (0°C) 0Fh W One Shot A write to this register initiates a one shot update. 00h Page 31 10h R External Diode Data Low Byte Stores the fractional data for the External Diode 00h Page 27 11h R/W Scratchpad Scratchpad register for software compatibility 00h Page 31 12h R/W Scratchpad Scratchpad register for software compatibility 00h Page 31 13h R/W External Diode High Limit Low Byte Stores the fractional portion of the high limit for the External Diode 00h Page 30 14h R/W External Diode Low Limit Low Byte Stores the fractional portion of the low limit for the External Diode 00h 19h R/W External Diode Therm Limit Stores the 8-bit critical temperature limit for the External Diode 55h (85°C) Page 32 1Fh R/W Channel Mask Register Controls the masking of individual channels 00h Page 32 20h R/W Internal Diode Therm Limit Stores the 8-bit critical temperature limit for the Internal Diode 55h (85°C Page 32 21h R/W Therm Hysteresis Stores the 8-bit hysteresis value that applies to all Therm limits 0Ah (10°C) 22h R/W Consecutive ALERT Controls the number of out-of-limit conditions that must occur before an interrupt is asserted 70h Page 33 25h R/W External Diode1 Beta Configuration Stores the Beta Compensation circuitry settings for External Diode1 08h Page 35 27h R/W External Diode Ideality Factor Stores the ideality factor for the External Diode 12h (1.008) Page 35 Table 6.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE PAGE Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 27 Revision 1.0 (07-11-13) DATASHEET 6.1 Data Read Interlock When any temperature channel high byte register is read, the corresponding low byte is copied into an internal ‘shadow’ register. The user is free to read the low byte at any time and be guaranteed that it will correspond to the previously read high byte. Regardless if the low byte is read or not, reading from the same high byte register again will automatically refresh this stored low byte data. 6.2 Temperature Data Registers As shown in Table 6.2, all temperatures are stored as an 11-bit value with the high byte representing the integer value and the low byte representing the fractional value left justified to occupy the MSBits. 29h R Internal Diode Data Low Byte Stores the fractional data for the Internal Diode 00h Page 27 40h R/W Filter Control Controls the digital filter setting for the External Diode channel 00h Page 37 FDh R Product ID Stores a fixed value that identifies the device 20h Page 37 FEh R Manufacturer ID Stores a fixed value that represents SMSC 5Dh Page 37 FFh R Revision Stores a fixed value that represents the revision number 07h Page 38 Table 6.2 Temperature Data Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 00h R Internal Diode High Byte 128 64 32 16 8 4 2 1 00h 29h R Internal Diode Low Byte 0.5 0.25 0.125 - - - - - 00h 01h R External Diode High Byte 128 64 32 16 8 4 2 1 00h 10h R External Diode Low Byte 0.5 0.25 0.125 - - - - - 00h Table 6.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE PAGE Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 28 SMSC EMC1182 DATASHEET 6.3 Status Register 02h The Status Register reports the operating status of the Internal Diode and External Diode channels. When any of the bits are set (excluding the BUSY bit) either the ALERT / THERM2 or THERM pin is being asserted. The ALERT / THERM2 and THERM pins are controlled by the respective consecutive alert counters (see Section 6.11) and will not be asserted until the programmed consecutive alert count has been reached. The status bits (except ETHERM and ITHERM) will remain set until read unless the ALERTpin is configured as a second THERM output (see Section 5.4). Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either the ALERT / THERM2 or THERM pin to be asserted. Bit 6 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit. When set, this bit will assert the ALERT / THERM2 pin. Bit 5 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit. When set, this bit will assert the ALERT / THERM2 pin. Bit 4 - EHIGH - This bit is set when the External Diode channel exceeds its programmed high limit. When set, this bit will assert the ALERT / THERM2 pin. Bit 3 - ELOW - This bit is set when the External Diode channel drops below its programmed low limit. When set, this bit will assert the ALERT / THERM2 pin. Bit 2 - FAULT - This bit is asserted when a diode fault is detected. When set, this bit will assert the ALERT / THERM2 pin. Bit 1 - ETHERM - This bit is set when the External Diode channel exceeds the programmed Therm Limit. When set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is released at which point it will be automatically cleared. Bit 0 - ITHERM - This bit is set when the Internal Diode channel exceeds the programmed Therm Limit. When set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is released at which point it will be automatically cleared. 6.4 Configuration Register 03h / 09h The Configuration Register controls the basic operation of the device. This register is fully accessible at either address. Table 6.3 Status Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 02h R-C Status BUSY IHIGH ILOW EHIGH ELOW FAULT ETHERM ITHERM 00h Table 6.4 Configuration Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 03h R/W Configuration MASK_ ALL RUN/ STOP ALERT/ THERM2 RECD - RANGE DAVG_ DIS - 00h 09h Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 29 Revision 1.0 (07-11-13) DATASHEET Bit 7 - MASK_ALL - Masks the ALERT / THERM2 pin from asserting.  ‘0’ - (default) - The ALERT / THERM2 pin is not masked. If any of the appropriate status bits are set the ALERT / THERM2 pin will be asserted.  ‘1’ - The ALERT/ THERM2 pin is masked. It will not be asserted for any interrupt condition unless it is configured in comparator mode. The Status Registers will be updated normally. Bit 6 - RUN / STOP - Controls Active/Standby modes.  ‘0’ (default) - The device is in Active mode and converting on all channels.  ‘1’ - The device is in Standby mode and not converting. Bit 5 - ALERT/THERM2 - Controls the operation of the ALERT / THERM2 pin.  ‘0’ (default) - The ALERT / THERM2 acts as an Alert pin and has interrupt behavior as described in Section 5.5.1.  ‘1’ - The ALERT / THERM2 acts as a THERM pin and has comparator behavior as described in Section 5.5.2. In this mode the MASK_ALL bit is ignored. Bit 4 - RECD - Disables the Resistance Error Correction (REC) for the External Diode.  ‘0’ (default) - REC is enabled for the External Diode.  ‘1’ - REC is disabled for the External Diode. Bit 2 - RANGE - Configures the measurement range and data format of the temperature channels.  ‘0’ (default) - The temperature measurement range is 0°C to +127.875°C and the data format is binary.  ‘1’ -The temperature measurement range is -64°C to +191.875°C and the data format is offset binary (see Table 5.2). Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels.  ‘0’ (default) - The dynamic averaging feature is enabled. All temperature channels will be converted with an averaging factor that is based on the conversion rate as shown in Table 6.6.  ‘1’ - The dynamic averaging feature is disabled. All temperature channels will be converted with a maximum averaging factor of 1x (equivalent to 11-bit conversion). For higher conversion rates, this averaging factor will be reduced as shown in Table 6.6. 6.5 Conversion Rate Register 04h / 0Ah The Conversion Rate Register controls how often the temperature measurement channels are updated and compared against the limits. This register is fully accessible at either address. Bits 3-0 - CONV[3:0] - Determines the conversion rate as shown in Table 6.6. Table 6.5 Conversion Rate Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 04h R/W Conversion Rate - - - - CONV[3:0] 06h 0Ah (4/sec) Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 30 SMSC EMC1182 DATASHEET 6.6 Limit Registers Table 6.6 Conversion Rate CONV[3:0] HEX 3 2 1 0 CONVERSIONS / SECOND 0h 0 0 0 0 / 16 1h 0 0 0 1 1 / 8 2h 0 0 1 0 1 / 4 3h 0 0 1 1 1 / 21 4h 0 1 0 0 1 5h 0 1 0 1 2 6h 0 1 1 0 4 (default) 7h 0 1 1 1 8 8h 1 0 0 0 16 9h 1 0 0 1 32 Ah 1 0 1 0 64 Bh - Fh All others 1 Table 6.7 Temperature Limit Registers ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 05h R/W Internal Diode High Limit 128 64 32 16 8 4 2 1 55h 0Bh (85°C) 06h R/W Internal Diode Low Limit 128 64 32 16 8 4 2 1 00h 0Ch (0°C) 07h R/W External Diode High Limit High Byte 128 64 32 16 8 4 2 1 55h 0Dh (85°C) 13h R/W External Diode High Limit Low Byte 0.5 0.25 0.125 - - - - - 00h Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 31 Revision 1.0 (07-11-13) DATASHEET The device contains both high and low limits for all temperature channels. If the measured temperature exceeds the high limit, then the corresponding status bit is set and the ALERT / THERM2 pin is asserted. Likewise, if the measured temperature is less than or equal to the low limit, the corresponding status bit is set and the ALERT / THERM2 pin is asserted. The data format for the limits must match the selected data format for the temperature so that if the extended temperature range is used, the limits must be programmed in the extended data format. The limit registers with multiple addresses are fully accessible at either address. When the device is in Standby mode, updating the limit registers will have no effect until the next conversion cycle occurs. This can be initiated via a write to the One Shot Register (see Section 6.8, "One Shot Register 0Fh") or by clearing the RUN / STOP bit (see Section 6.4, "Configuration Register 03h / 09h"). 6.7 Scratchpad Registers 11h and 12h The Scratchpad Registers are Read / Write registers that are used for place holders to be software compatible with legacy programs. Reading from the registers will return what is written to them. 6.8 One Shot Register 0Fh The One Shot Register is used to initiate a one shot command. Writing to the one shot register when the device is in Standby mode and BUSY bit (in Status Register) is ‘0’, will immediately cause the ADC to update all temperature measurements. Writing to the One Shot Register while the device is in Active mode will have no effect. 08h R/W External Diode Low Limit High Byte 128 64 32 16 8 4 2 1 00h 0Eh (0°C) 14h R/W External Diode Low Limit Low Byte 0.5 0.25 0.125 - - - - - 00h Table 6.8 Scratchpad Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 11h R/W Scratchpad 7 6 5 4 3 2 1 0 00h 12h R/W Scratchpad 7 6 5 4 3 2 1 0 00h Table 6.7 Temperature Limit Registers (continued) ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 32 SMSC EMC1182 DATASHEET 6.9 Therm Limit Registers The Therm Limit Registers are used to determine whether a critical thermal event has occurred. If the measured temperature exceeds the Therm Limit, the THERM pin is asserted. The limit setting must match the chosen data format of the temperature reading registers. Unlike the ALERT / THERM2 pin, the THERM pin cannot be masked. Additionally, the THERM pin will be released once the temperature drops below the corresponding threshold minus the Therm Hysteresis. 6.10 Channel Mask Register 1Fh The Channel Mask Register controls individual channel masking. When a channel is masked, the ALERT / THERM2 pin will not be asserted when the masked channel reads a diode fault or out of limit error. The channel mask does not mask the THERM pin. Bit 1 - EXTMASK - Masks the ALERT / THERM2 pin from asserting when the External Diode channel is out of limit or reports a diode fault.  ‘0’ (default) - The External Diode channel will cause the ALERT / THERM2 pin to be asserted if it is out of limit or reports a diode fault.  ‘1’ - The External Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out of limit or reports a diode fault. Bit 0 - INTMASK - Masks the ALERT / THERM2 pin from asserting when the Internal Diode temperature is out of limit.  ‘0’ (default) - The Internal Diode channel will cause the ALERT / THERM2 pin to be asserted if it is out of limit.  ‘1’ - The Internal Diode channel will not cause the ALERT / THERM2 pin to be asserted if it is out of limit. Table 6.9 Therm Limit Registers ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 19h R/W External Diode Therm Limit 128 64 32 16 8 4 2 1 55h (85°C) 20h R/W Internal Diode Therm Limit 128 64 32 16 8 4 2 1 55h (85°C) 21h R/W Therm Hysteresis 128 64 32 16 8 4 2 1 0Ah (10°C) Table 6.10 Channel Mask Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 1Fh R/W Channel Mask - - - - - - EXT MASK INT MASK 00h Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 33 Revision 1.0 (07-11-13) DATASHEET 6.11 Consecutive ALERT Register 22h The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must be detected in consecutive measurements before the ALERT / THERM2 or THERM pin is asserted. Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality. An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in consecutive measurements will increment the consecutive alert counter. The counters will also be reset if no out-of-limit condition or diode fault condition occurs in a consecutive reading. When the ALERT / THERM2 pin is configured as an interrupt, when the consecutive alert counter reaches its programmed value, the following will occur: the STATUS bit(s) for that channel and the last error condition(s) (i.e. EHIGH) will be set to ‘1’, the ALERT / THERM2 pin will be asserted, the consecutive alert counter will be cleared, and measurements will continue. When the ALERT / THERM2 pin is configured as a comparator, the consecutive alert counter will ignore diode fault and low limit errors and only increment if the measured temperature exceeds the High Limit. Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT/ THERM2 pin will be asserted, but the counter will not be reset. It will remain set until the temperature drops below the High Limit minus the Therm Hysteresis value. For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1182 device, the high limits are set at 70°C, and none of the channels are masked, the ALERT / THERM2 pin will be asserted after the following four measurements: 1.Internal Diode reads 71°C and the external diode reads 69°C. Consecutive alert counter for INT is incremented to 1. 2.Both the Internal Diode and the External Diode read 71°C. Consecutive alert counter for INT is incremented to 2 and for EXT is set to 1. 3.The External Diode reads 71°C and the Internal Diode reads 69°C. Consecutive alert counter for INT is cleared and EXT is incremented to 2. 4.The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for INT is set to 1 and EXT is incremented to 3. 5.The Internal Diode reads 71°C and the external diode reads 71°C. Consecutive alert counter for INT is incremented to 2 and EXT is incremented to 4. The appropriate status bits are set for EXTand the ALERT / THERM2 pin is asserted. EXT counter is reset to 0 and all other counters hold the last value until the next temperature measurement. Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.  ‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely without the device resetting its SMBus protocol.  ‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than tTIMEOUT, the device will reset the SMBus protocol. Bits 6-4 CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the corresponding Therm Limit and Hardware Thermal Shutdown Limit before the SYS_SHDN pin is asserted. All temperature channels use this value to set the respective counters. The consecutive THERM counter is incremented whenever any of the measurements exceed the corresponding Therm Limit or if the External Diode measurement exceeds the Hardware Thermal Shutdown Limit. Table 6.11 Consecutive ALERT Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 22h R/W Consecutive ALERT TIME OUT CTHRM[2:0] CALRT[2:0] - 70h Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 34 SMSC EMC1182 DATASHEET If the temperature drops below the Therm Limit or Hardware Thermal Shutdown Limit, the counter is reset. If the programmed number of consecutive measurements exceed the Therm Limit or Hardware Thermal Shutdown Limit, and the appropriate channel is linked to the SYS_SHDN pin, the SYS_SHDNpin will be asserted low. Once the SYS_SHDN pin is asserted, the consecutive Therm counter will not reset until the corresponding temperature drops below the appropriate limit minus the corresponding hysteresis. Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the corresponding Therm Limit before the THERM pin is asserted. All temperature channels use this value to set the respective counters. The consecutive Therm counter is incremented whenever any measurement exceed the corresponding Therm Limit. If the temperature drops below the Therm Limit, the counter is reset. If a number of consecutive measurements above the Therm Limit occurs, the THERM pin is asserted low. Once the THERM pin has been asserted, the consecutive therm counter will not reset until the corresponding temperature drops below the Therm Limit minus the Therm Hysteresis value. The bits are decoded as shown in Table 6.12. The default setting is 4 consecutive out of limit conversions. Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of limit condition or diode fault before the ALERT / THERM2 pin is asserted. Both temperature channels use this value to set the respective counters. The bits are decoded as shown in Table 6.12. The default setting is 1 consecutive out of limit conversion. 6.12 Beta Configuration Register 25h This register is used to set the Beta Compensation factor that is used for the external diode channel.  ‘0’ - The Beta Compensation Factor auto-detection circuitry is disabled. ‘1’ (default) - The Beta Compensation factor auto-detection circuitry is enabled. At the beginning of every conversion, the optimal Beta Compensation factor setting will be determined and applied. Table 6.12 Consecutive Alert / Therm Settings 2 1 0 NUMBER OF CONSECUTIVE OUT OF LIMIT MEASUREMENTS 0 0 0 1 (default for CALRT[2:0]) 0 0 1 2 0 1 1 3 1 1 1 4 (default for CTHRM[2:0]) Table 6.13 Beta Configuration Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 25h R/W External Diode Beta Configuration - - - - ENABLE BETA[2:0] 08h Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 35 Revision 1.0 (07-11-13) DATASHEET 6.13 External Diode Ideality Factor Register 27h This register stores the ideality factors that are applied to the external diode. Table 6.15 defines each setting and the corresponding ideality factor. Beta Compensation and Resistance Error Correction automatically correct for most diode ideality errors; therefore, it is not recommended that these settings be updated without consulting SMSC. For CPU substrate transistors that require the BJT transistor model, the ideality factor behaves slightly differently than for discrete diode-connected transistors. Refer to Table 6.16 when using a CPU substrate transistor. Table 6.14 Ideality Configuration Registers ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 27h R/W External Diode Ideality Factor - - IDEALITY[5:0] 12h Table 6.15 Ideality Factor Look-Up Table (Diode Model) SETTING FACTOR SETTING FACTOR SETTING FACTOR 08h 0.9949 18h 1.0159 28h 1.0371 09h 0.9962 19h 1.0172 29h 1.0384 0Ah 0.9975 1Ah 1.0185 2Ah 1.0397 0Bh 0.9988 1Bh 1.0200 2Bh 1.0410 0Ch 1.0001 1Ch 1.0212 2Ch 1.0423 0Dh 1.0014 1Dh 1.0226 2Dh 1.0436 0Eh 1.0027 1Eh 1.0239 2Eh 1.0449 0Fh 1.0040 1Fh 1.0253 2Fh 1.0462 10h 1.0053 20h 1.0267 30h 1.0475 11h 1.0066 21h 1.0280 31h 1.0488 12h 1.0080 22h 1.0293 32h 1.0501 13h 1.0093 23h 1.0306 33h 1.0514 14h 1.0106 24h 1.0319 34h 1.0527 15h 1.0119 25h 1.0332 35h 1.0540 16h 1.0133 26h 1.0345 36h 1.0553 17h 1.0146 27h 1.0358 37h 1.0566 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 36 SMSC EMC1182 DATASHEET APPLICATION NOTE: When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When measuring a 45nm Intel CPU, the Ideality Setting should be 15h. Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit. Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit. Bit 1 - ELOW - This bit is set when the External Diode channel drops below its programmed low limit. Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit. Bit 1 - ETHERM - This bit is set when the External Diode channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin. Bit 0- ITHERM - This bit is set when the Internal Diode channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin. Table 6.16 Substrate Diode Ideality Factor Look-Up Table (BJT Model) SETTING FACTOR SETTING FACTOR SETTING FACTOR 08h 0.9869 18h 1.0079 28h 1.0291 09h 0.9882 19h 1.0092 29h 1.0304 0Ah 0.9895 1Ah 1.0105 2Ah 1.0317 0Bh 0.9908 1Bh 1.0120 2Bh 1.0330 0Ch 0.9921 1Ch 1.0132 2Ch 1.0343 0Dh 0.9934 1Dh 1.0146 2Dh 1.0356 0Eh 0.9947 1Eh 1.0159 2Eh 1.0369 0Fh 0.9960 1Fh 1.0173 2Fh 1.0382 10h 0.9973 20h 1.0187 30h 1.0395 11h 0.9986 21h 1.0200 31h 1.0408 12h 1.0000 22h 1.0213 32h 1.0421 13h 1.0013 23h 1.0226 33h 1.0434 14h 1.0026 24h 1.0239 34h 1.0447 15h 1.0039 25h 1.0252 35h 1.0460 16h 1.0053 26h 1.0265 36h 1.0473 17h 1.0066 27h 1.0278 37h 1.0486 Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 37 Revision 1.0 (07-11-13) DATASHEET 6.14 Filter Control Register 40h The Filter Configuration Register controls the digital filter on the External Diode channel. Bits 1-0 - FILTER[1:0] - Control the level of digital filtering that is applied to the External Diodetemperature measurement as shown in Table 6.18. See Figure 5.4 and Figure 5.5 for examples on the filter behavior. 6.15 Product ID Register The Product ID Register holds a unique value that identifies the device. 6.16 SMSC ID Register The Manufacturer ID register contains an 8-bit word that identifies the SMSC as the manufacturer of the EMC1182. Table 6.17 Filter Configuration Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 40h R/W Filter Control - - - - - - FILTER[1:0] 00h Table 6.18 FILTER Decode FILTER[1:0] 1 0 AVERAGING 0 0 Disabled (default) 0 1 Level 1 1 0 Level 1 1 1 Level 2 Table 6.19 Product ID Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FDh R Product ID 0 0 1 0 0 0 0 0 20h Table 6.20 Manufacturer ID Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FEh R SMSC ID 0 1 0 1 1 1 0 1 5Dh Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 38 SMSC EMC1182 DATASHEET 6.17 Revision Register The Revision register contains an 8-bit word that identifies the die revision. Table 6.21 Revision Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FFh R Revision 0 0 0 0 0 1 1 1 07h Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 39 Revision 1.0 (07-11-13) DATASHEET Chapter 7 Typical Operating Curves Temperature Error vs. Filter Capacitor (2N3904, TA = 27°C, TDIODE = 27°C, VDD = 3.3V) -1.0 -0.8 -0.5 -0.3 0.0 0.3 0.5 0.8 1.0 0 1000 2000 3000 4000 Filter Capacitor (pF) Temperature Error (°C) Temperature Error vs. Ambient Temperature (2N3904, TDIODE = 42.5°C, VDD = 3.3V) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ambient Temperature (°C) Temperature Error (°C) Temperature Error vs. External Diode Temperature (2N3904, TA = 42.5°C, VDD = 3.3V) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 External Diode Temperature (°C) Temperature Error (°C) Temperature Error vs. CPU Temperature Typical 65nm CPU from major vendor (TA = 27°C, VDD = 3.3V, BETA = 011, CFILTER = 470pF) -1 0 1 2 3 4 5 20 40 60 80 100 120 CPU Temperature (°C) Temperature Error (°C) Beta Compensation Disabled Beta Compensation Enabled Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 40 SMSC EMC1182 DATASHEET Chapter 8 Package Information Figure 8.1 2mm x 3mm TDFN Package Drawing Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 41 Revision 1.0 (07-11-13) DATASHEET Figure 8.2 2mm x 3mm TDFN Package Dimensions Figure 8.3 2mm x 3mm TDFN Package PCB Land Pattern Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 42 SMSC EMC1182 DATASHEET Figure 8.4 3mm x 3mm DFN Package Drawing Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 43 Revision 1.0 (07-11-13) DATASHEET Figure 8.5 3mm x 3mm DFN Package Dimensions Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 44 SMSC EMC1182 DATASHEET Figure 8.6 8 Pin DFN PCB Footprint Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 45 Revision 1.0 (07-11-13) DATASHEET 8.1 Package Markings The EMC1182 devices will be marked as shown in Figure 8.7, Figure 8.8., Figure 8.9, Figure 8.10 and Figure 8.11. Figure 8.7 EMC1182-1 8-Pin TDFN Package Markings Figure 8.8 EMC1182-2 8-Pin TDFN Package Markings BOTTOM LINE 1: Preface, First digit of Device Code LINE 2: Second digit of Device Code, Revision TOP PIN 1 E 3 BOTTOM MARKING IS NOT ALLOWED C R BOTTOM LINE 1: Preface, First digit of Device Code LINE 2: Second digit of Device Code, Revision TOP PIN 1 E 3 BOTTOM MARKING IS NOT ALLOWED D R Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 46 SMSC EMC1182 DATASHEET Figure 8.9 EMC1182-A 8-Pin TDFN Package Markings Figure 8.10 EMC1182-1 8-Pin DFN Package Markings BOTTOM LINE 1: Preface, First digit of Device Code LINE 2: Second digit of Device Code, Revision TOP PIN 1 E 3 BOTTOM MARKING IS NOT ALLOWED A R BOTTOM LINE 1: Device Code, First two digits of 6 digits of lot number LINE 2: Last 4 digits of lot number TOP PIN 1 4 4 BOTTOM MARKING IS NOT ALLOWED L L L L L L Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet SMSC EMC1182 47 Revision 1.0 (07-11-13) DATASHEET Figure 8.11 EMC1182-2 8-Pin DFN Package Markings BOTTOM LINE 1: Device Code, First two digits of 6 digits of lot number LINE 2: Last 4 digits of lot number TOP PIN 1 4 4 BOTTOM MARKING IS NOT ALLOWED L L L L L L Dual Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 48 SMSC EMC1182 DATASHEET Chapter 9 Datasheet Revision History Table 9.1 Customer Revision History REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION Rev. 1.0 (07-11-13) Formal document release 8235E–AVR–03/2013 Features  High performance, low power 8-bit AVR® microcontroller  Advanced RISC architecture  112 powerful instructions – most single clock cycle execution  16 x 8 general purpose working registers  Fully static operation  Up to 12 MIPS throughput at 12MHz  Non-volatile program and data memories  2K bytes of in-system programmable flash program memory  128 bytes internal SRAM  Flash write/erase cycles: 10,000  Data retention: 20 years at 85oC / 100 years at 25oC  Peripheral features  One 8-bit timer/counter with two PWM channels  One 16-bit timer/counter with two PWM channels  10-bit analog to digital converter  8 single-ended channels  Programmable watchdog timer with separate on-chip oscillator  On-chip analog comparator  Master/slave SPI serial interface  Slave TWI serial interface  Special microcontroller features  In-system programmable  External and internal interrupt sources  Low power idle, ADC noise reduction, stand-by and power-down modes  Enhanced power-on reset circuit  Internal calibrated oscillator  I/O and packages  14-pin SOIC/TSSOP: 12 programmable I/O lines  12-ball WLCSP: 10 programmable I/O lines  15-ball UFBGA: 12 programmable I/O lines  20-pad VQFN: 12 programmable I/O lines  Operating voltage:  1.8 – 5.5V  Programming voltage:  5V  Speed grade  0 – 4MHz @ 1.8 – 5.5V  0 – 8MHz @ 2.7 – 5.5V  0 – 12MHz @ 4.5 – 5.5V  Industrial temperature range  Low power consumption  Active mode:  200 μA at 1MHz and 1.8V  Idle mode:  25μA at 1MHz and 1.8V  Power-down mode:  < 0.1μA at 1.8V ATtiny20 8-bit AVR Microcontroller with 2K Bytes In-System Programmable Flash DATASHEET ATtiny20 [DATASHEET] 2 8235E–AVR–03/2013 1. Pin Configurations 1.1 SOIC & TSSOP Figure 1-1. SOIC/TSSOP 1.2 VQFN Figure 1-2. VQFN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC (PCINT8/TPICLK/T0/CLKI) PB0 (PCINT9/TPIDATA/MOSI/SDA/OC1A) PB1 (PCINT11/RESET) PB3 (PCINT10/INT0/MISO/OC1B/OC0A/CKOUT) PB2 (PCINT7/SCL/SCK/T1/ICP1/OC0B/ADC7) PA7 (PCINT6/SS/ADC6) PA6 GND PA0 (ADC0/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) 1 2 3 4 5 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect DNC DNC GND VCC DNC PA7 (ADC7/OC0B/ICP1/T1/SCL/SCK/PCINT7) PB2 (CKOUT/OC0A/OC1B/MISO/INT0/PCINT10) PB3 (RESET/PCINT11) PB1 (OC1A/SDA/MOSI/TPIDATA/PCINT9) PB0 (CLKI/T0/TPICLK/PCINT8) DNC DNC DNC PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6/SS) (PCINT4/ADC4) PA4 (PCINT3/ADC3) PA3 (PCINT2/AIN1/ADC2) PA2 (PCINT1/AIN0/ADC1) PA1 (PCINT0/ADC0) PA0 ATtiny20 [DATASHEET] 3 8235E–AVR–03/2013 1.3 UFBGA Figure 1-3. UFBGA Table 1-1. UFBGA Pin Configuration 1.4 Wafer Level Chip Scale Package Figure 1-4. WLCSP Table 1-2. WLCSP Ball Configuration 1 2 3 4 A PA5 PA6 PB2 B PA4 PA7 PB1 PB3 C PA3 PA2 PA1 PB0 D PA0 GND GND VCC A B C D 1 2 3 4 A B C D 4 3 2 1 TOP VIEW BOTTOM VIEW 1 2 3 4 5 6 A PA4 PA1 PA2 B PA6 GND VDD C PA5 PA7 PB1 D PB2 PB3 PB0 A B C D 1 2 3 4 A B C D 6 5 4 3 2 1 TOP VIEW BOTTOM VIEW ATtiny20 [DATASHEET] 4 8235E–AVR–03/2013 1.5 Pin Description 1.5.1 VCC Supply voltage. 1.5.2 GND Ground. 1.5.3 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 170. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.5.4 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in “Alternate Port Functions” on page 47. 1.5.5 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny20, as listed on page 37. ATtiny20 [DATASHEET] 5 8235E–AVR–03/2013 2. Overview ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram STACK POINTER SRAM PROGRAM COUNTER PROGRAMMING LOGIC ISP INTERFACE INTERNAL OSCILLATOR WATCHDOG TIMER RESET FLAG REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 CALIBRATED OSCILLATOR TIMING AND CONTROL INTERRUPT UNIT ANALOG COMPARATOR ADC GENERAL PURPOSE REGISTERS X Y Z ALU STATUS REGISTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES VCC RESET DATA REGISTER PORT A DIRECTION REG. PORT A DRIVERS PORT A PA[7:0] GND 8-BIT DATA BUS TIMER/ COUNTER1 TWI SPI DATA REGISTER PORT B DIRECTION REG. PORT B DRIVERS PORT B PB[3:0] ATtiny20 [DATASHEET] 6 8235E–AVR–03/2013 The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. ATtiny20 provides the following features:  2K bytes of in-system programmable Flash  128 bytes of SRAM  Twelve general purpose I/O lines  16 general purpose working registers  An 8-bit Timer/Counter with two PWM channels  A 16-bit Timer/Counter with two PWM channels  Internal and external interrupts  An eight-channel, 10-bit ADC  A programmable Watchdog Timer with internal oscillator  A slave two-wire interface  A master/slave serial peripheral interface  An internal calibrated oscillator  Four software selectable power saving modes The device includes the following modes for saving power:  Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt system to continue functioning  ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC  Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset  Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. ATtiny20 [DATASHEET] 7 8235E–AVR–03/2013 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 3.3 Capacitive Touch Sensing Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. ATtiny20 [DATASHEET] 8 8235E–AVR–03/2013 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 16 x 8 General Purpose Registrers ALU Status and Control I/O Lines Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit Watchdog Timer Analog Comparator Timer/Counter 0 ADC TWI Slave SPI Timer/Counter 1 ATtiny20 [DATASHEET] 9 8235E–AVR–03/2013 Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the four different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruction Set Summary” on page 205. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:  One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input  One 16-bit output operand and one 16-bit result input Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU. ATtiny20 [DATASHEET] 10 8235E–AVR–03/2013 Figure 4-2. AVR CPU General Purpose Working Registers Note: A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny20 implements only 16 registers. For reasons of compatibility the registers are numbered R16:R31 and not R0:R15. Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. 4.4.1 The X-register, Y-register, and Z-register Registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. Figure 4-3. The X-, Y-, and Z-registers In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for details). 4.5 Stack Pointer The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack grows from higher memory locations to lower memory locations. This means that the PUSH instructions decreases and the POP instruction increases the stack pointer value. 7 0 R16 R16 R17 R17 General R18 R18 Purpose … ... Working R26 R26 X-register Low Byte Registers R27 R27 X-register High Byte R28 R28 Y-register Low Byte R29 R29 Y-register High Byte R30 R30 Z-register Low Byte R31 R31 Z-register High Byte 15 XH XL 0 X-register 7 07 0 R27 R26 15 YH YL 0 Y-register 7 07 0 R29 R28 15 ZH ZL 0 Z-register 7 07 0 R31 R30 ATtiny20 [DATASHEET] 11 8235E–AVR–03/2013 The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack space must be defined by the program before any subroutine calls are executed or interrupts are enabled. The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by one when data is fetched with the POP instruction. It is decremented by two when the return address is put on the stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by a return from subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction). The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack pointer and the number of bits implemented is device dependent. In some AVR devices all data memory can be addressed using SPL, only. In this case, the SPH register is not implemented. The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of SRAM. See Figure 5-1 on page 15. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU ATtiny20 [DATASHEET] 12 8235E–AVR–03/2013 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 36. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Note: See “Code Examples” on page 7. 4.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) ATtiny20 [DATASHEET] 13 8235E–AVR–03/2013 4.8 Register Description 4.8.1 CCP – Configuration Change Protection Register  Bits 7:0 – CCP[7:0]: Configuration Change Protection In order to change the contents of a protected I/O register the CCP register must first be written with the correct signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending interrupts will be executed according to their priority. When the protected I/O register signature is written, CCP0 will read as one as long as the protected feature is enabled, while CCP[7:1] will always read as zero. Table 4-1 shows the signatures that are recognised. Table 4-1. Signatures Recognised by the Configuration Change Protection Register Notes: 1. Only WDE and WDP[3:0] bits are protected in WDTCSR. 2. Only BODS bit is protected in MCUCR. 4.8.2 SPH and SPL — Stack Pointer Registers  Bits 7:0 – SP[7:0]: Stack Pointer The Stack Pointer register points to the top of the stack, which is implemented growing from higher memory locations to lower memory locations. Hence, a stack PUSH command decreases the stack pointer. The stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. In ATtiny20, the SPH register has not been implemented. Bit 7 6 5 4 3 2 1 0 0x3C CCP[7:0] CCP Read/Write W W W W W W W R/W Initial Value 0 0 0 0 0 0 0 0 Signature Group Description 0xD8 IOREG: CLKMSR, CLKPSR, WDTCSR(1), MCUCR(2) Protected I/O register Initial Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Bit 15 14 13 12 11 10 9 8 0x3E – – – – – – – – SPH 0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND ATtiny20 [DATASHEET] 14 8235E–AVR–03/2013 4.8.3 SREG – Status Register  Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the document “AVR Instruction Set” and “Instruction Set Summary” on page 205.  Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.  Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for detailed information.  Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for detailed information.  Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for detailed information.  Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for detailed information.  Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for detailed information.  Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for detailed information. Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ATtiny20 [DATASHEET] 15 8235E–AVR–03/2013 5. Memories This section describes the different memories in the ATtiny20. The device has two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny20 contains 2K byte on-chip, in-system reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1024 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny20 Program Counter (PC) is 10 bits wide, thus capable of addressing the 1024 program memory locations, starting at 0x000. “Memory Programming” on page 159 contains a detailed description on Flash data serial downloading. Constant tables can be allocated within the entire address space of program memory. Since program memory can not be accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte address 0x4000 in data memory (see Figure 5-1 on page 15). Although programs are executed starting from address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data memory. Internal write operations to Flash program memory have been disabled and program memory therefore appears to firmware as read-only. Flash memory can still be written to externally but internal write operations to the program memory area will not be succesful. Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Timing” on page 11. 5.2 Data Memory Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile memory lock bits, and the Flash memory. See Figure 5-1 for an illustration on how the ATtiny20 memory space is organized. Figure 5-1. Data Memory Map (Byte Addressing) The first 64 locations are reserved for I/O memory, while the following 128 data memory locations (from 0x0040 to 0x00BF) address the internal data SRAM. 0x0000 ... 0x003F 0x0040 ... 0x00BF 0x00C0 ... 0x3EFF 0x3F00 ... 0x3F01 0x3F02 ... 0x3F3F 0x3F40 ... 0x3F41 0x3F42 ... 0x3F7F 0x3F80 ... 0x3F81 0x3F82 ... 0x3FBF 0x3FC0 ... 0x3FC3 0x3FC4 ... 0x3FFF 0x4000 ... 0x47FF 0x4800 ... 0xFFFF I/O SPACE SRAM DATA MEMORY (reserved) NVM LOCK BITS (reserved) CONFIGURATION BITS (reserved) CALIBRATION BITS (reserved) DEVICE ID BITS (reserved) FLASH PROGRAM MEMORY (reserved) ATtiny20 [DATASHEET] 16 8235E–AVR–03/2013 The non-volatile memory lock bits and all the Flash memory sections are mapped to the data memory space. These locations appear as read-only for device firmware. The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing. The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF. The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-2. Figure 5-2. On-chip Data SRAM Access Cycles 5.3 I/O Memory The I/O space definition of the ATtiny20 is shown in “Register Summary” on page 203. All ATtiny20 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 205 for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work on registers in the address range 0x00 to 0x1F, only. The I/O and Peripherals Control Registers are explained in later sections. clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address Read Write CPU Memory Access Instruction Next Instruction ATtiny20 [DATASHEET] 17 8235E–AVR–03/2013 6. Clock System Figure 6-1 presents the principal clock systems and their distribution in ATtiny20. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 23. The clock systems is detailed below. Figure 6-1. Clock Distribution 6.1 Clock Subsystems The clock subsystems are detailed in the sections below. 6.1.1 CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR Core. Examples of such modules are the General Purpose Register File, the System Registers and the SRAM data memory. Halting the CPU clock inhibits the core from performing general operations and calculations. 6.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 6.1.3 NVM clock - clkNVM The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active simultaneously with the CPU clock. CLOCK CONTROL UNIT GENERAL I/O MODULES ANALOG-TO-DIGITAL CONVERTER CPU CORE WATCHDOG TIMER RESET LOGIC CLOCK PRESCALER RAM CLOCK SWITCH NVM CALIBRATED OSCILLATOR clkADC SOURCE CLOCK clk I/O clkCPU clkNVM WATCHDOG CLOCK WATCHDOG OSCILLATOR EXTERNAL CLOCK ATtiny20 [DATASHEET] 18 8235E–AVR–03/2013 6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.2 Clock Sources All synchronous clock signals are derived from the main clock. The device has three alternative sources for the main clock, as follows:  Calibrated Internal 8 MHz Oscillator (see page 18)  External Clock (see page 18)  Internal 128 kHz Oscillator (see page 18) See Table 6-3 on page 21 on how to select and change the active clock source. 6.2.1 Calibrated Internal 8 MHz Oscillator The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 20-2 on page 169, and “Internal Oscillator Speed” on page 200 for more details. This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0] in CLKMSR to 0b00. Once enabled, the oscillator will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL register and thereby automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory calibration in Table 20-2 on page 169. When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog timer and reset time-out. For more information on the pre-programmed calibration value, see section “Calibration Section” on page 162. 6.2.2 External Clock To use the device with an external clock source, CLKI should be driven as shown in Figure 6-2. The external clock is selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10. Figure 6-2. External Clock Drive Configuration When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock frequency. 6.2.3 Internal 128 kHz Oscillator The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the CLKMS[1:0] bits in CLKMSR to 0b01. EXTERNAL CLOCK SIGNAL CLKI GND ATtiny20 [DATASHEET] 19 8235E–AVR–03/2013 6.2.4 Switching Clock Source The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page 20. When switching between any clock sources, the clock system ensures that no glitch occurs in the main clock. 6.2.5 Default Clock Source The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has been reset. The synchronous system clock is the main clock divided by 8, controlled by the System Clock Prescaler. The Clock Prescaler Select Bits can be written later to change the system clock frequency. See “System Clock Prescaler”. 6.3 System Clock Prescaler The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided by setting the “CLKPSR – Clock Prescale Register” on page 21. The system clock prescaler can be used to decrease power consumption at times when requirements for processing power is low or to bring the system clock within limits of maximum frequency. The prescaler can be used with all main clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. 6.3.1 Switching Prescaler Setting When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting. 6.4 Starting 6.4.1 Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows. 1. The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels. The reset start-up time is counted using the internal 128 kHz oscillator. See Table 6-1 for details of reset start-up time. Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the reset startup time has elapsed even if the device has reached sufficient supply voltage levels earlier. 2. The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscillator has reached a stable state before it is used by the other parts of the system. The calibrated internal oscillator needs to oscillate for a minimum number of cycles before it can be considered stable. See Table 6-1 for details of the oscillator start-up time. 3. The last step before releasing the internal reset is to load the calibration and the configuration values from the Non-Volatile Memory to configure the device properly. The configuration time is listed in Table 6-1. ATtiny20 [DATASHEET] 20 8235E–AVR–03/2013 Table 6-1. Start-up Times when Using the Internal Calibrated Oscillator Notes: 1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscillator, divided by 8 2. When the Brown-out Detection is enabled, the reset start-up time is 128 ms after powering up the device. 6.4.2 Starting from Power-Down Mode When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level and only the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is counted on the selected main clock, and the start-up time depends on the clock selected. See Table 6-2 for details. Table 6-2. Start-up Time from Power-Down Sleep Mode Notes: 1. The start-up time is measured in main clock oscillator cycles. 2. When using software BOD disable, the wake-up time from sleep mode will be approximately 60 μs. 6.4.3 Starting from Idle / ADC Noise Reduction / Standby Mode When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscillator start-up time is introduced. 6.5 Register Description 6.5.1 CLKMSR – Clock Main Settings Register  Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read as zero.  Bits 1:0 – CLKMS[1:0]: Clock Main Select Bits These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source. The main clock alternatives are shown in Table 6-3. Reset Oscillator Configuration Total start-up time 64 ms 6 cycles 21 cycles 64 ms + 6 oscillator cycles + 21 system clock cycles (1)(2) Oscillator start-up time Total start-up time 6 cycles 6 oscillator cycles (1)(2) Bit 7 6 5 4 3 2 1 0 0x37 – – – – – – CLKMS1 CLKMS0 CLKMSR Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 ATtiny20 [DATASHEET] 21 8235E–AVR–03/2013 Table 6-3. Selection of Main Clock To avoid unintentional switching of main clock source, a protected change sequence must be followed to change the CLKMS bits, as follows: 1. Write the signature for change enable of protected I/O register to register CCP 2. Within four instruction cycles, write the CLKMS bits with the desired value 6.5.2 CLKPSR – Clock Prescale Register  Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero.  Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written at run-time to vary the clock frequency and suit the application requirements. As the prescaler divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The division factors are given in Table 6-4. Table 6-4. Clock Prescaler Select CLKM1 CLKM0 Main Clock Source 0 0 Calibrated Internal 8 MHz Oscillator 0 1 Internal 128 kHz Oscillator (WDT Oscillator) 1 0 External clock 1 1 Reserved Bit 7 6 5 4 3 2 1 0 0x36 – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPSR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 1 1 CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 (default) 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved ATtiny20 [DATASHEET] 22 8235E–AVR–03/2013 To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS bits: 1. Write the signature for change enable of protected I/O register to register CCP 2. Within four instruction cycles, write the desired value to CLKPS bits At start-up, the CLKPS bits will be reset to 0b0011 to select the clock division factor of 8. The application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. 6.5.3 OSCCAL – Oscillator Calibration Register .  Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in Table 20-2, “Calibration Accuracy of Internal RC Oscillator,” on page 169. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 20-2, “Calibration Accuracy of Internal RC Oscillator,” on page 169. Calibration outside the range given is not guaranteed. The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a setting of 0xFF gives the highest frequency. 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor Bit 7 6 5 4 3 2 1 0 0x39 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ATtiny20 [DATASHEET] 23 8235E–AVR–03/2013 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 17 presents the different clock systems and their distribution in ATtiny20. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources. Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes Notes: 1. For INT0, only level interrupt. 2. Only TWI address match interrupt. To enter any of the four sleep modes, the SE bits in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM[2:0] bits in the MCUCR register select which sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the SLEEP instruction. See Table 7-2 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 37 for details. 7.1.1 Idle Mode When bits SM[2:0] are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the analog comparator, ADC, timer/counters, watchdog, TWI, SPI and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkNVM, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the ACD bit in “ACSRA – Analog Comparator Control and Status Register” on page 106. This will reduce power consumption in idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. Sleep Mode Active Clock Domains Oscillators Wake-up Sources clkCPU clkNVM clkIO clkADC Main Clock Source Enabled INT0 and Pin Change Watchdog Interrupt TWI Slave ADC Other I/O Idle X X X X X X X X ADC Noise Reduction X X X(1) X X(2) X Standby X X(1) X X(2) Power-down X(1) X X(2) ATtiny20 [DATASHEET] 24 8235E–AVR–03/2013 7.1.2 ADC Noise Reduction Mode When bits SM[2:0] are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, TWI and the watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkNVM, while allowing the other clocks to run. This mode improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.3 Power-down Mode When bits SM[2:0] are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the oscillator is stopped, while the external interrupts, TWI and the watchdog continue operating (if enabled). Only a watchdog reset, an external level interrupt on INT0, a pin change interrupt, or a TWI slave interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only. 7.1.4 Standby Mode When bits SM[2:0] are written to 100, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the oscillator is kept running. This reduces wake-up time, because the oscillator is already running and doesn't need to be started up. 7.2 Software BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 19-5 on page 161), the BOD is actively monitoring the supply voltage during a sleep period. In some devices it is possible to save power by disabling the BOD by software in Power-Down and Stand-By sleep modes. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled by software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the VCC level has dropped during the sleep period. When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60μs to ensure that the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by the BODS (BOD Sleep) bit of MCU Control Register, see “MCUCR – MCU Control Register” on page 26. Writing this bit to one turns off BOD in Power-Down and Stand-By, while writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence, see “MCUCR – MCU Control Register” on page 26. 7.3 Power Reduction Register The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 27, provides a method to reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is stopped then:  The current state of the peripheral is frozen.  The associated registers can not be read or written.  Resources used by the peripheral will remain occupied. The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the peripheral and puts it in the same state as before shutdown. Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See “Supply Current of I/O Modules” on page 174 for examples. In all other sleep modes, the clock is already stopped. ATtiny20 [DATASHEET] 25 8235E–AVR–03/2013 7.4 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR Core controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 7.4.1 Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used. In the power-down mode, the analog comparator is automatically disabled. See “Analog Comparator” on page 105 for further details. 7.4.2 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See “Analog to Digital Converter” on page 109 for details on ADC operation. 7.4.3 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 31 for details on how to configure the Watchdog Timer. 7.4.4 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See “Brown-out Detection” on page 30 and “Software BOD Disable” on page 24 for details on how to configure the Brown-out Detector. 7.4.5 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 46 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 108 for details. ATtiny20 [DATASHEET] 26 8235E–AVR–03/2013 7.5 Register Description 7.5.1 MCUCR – MCU Control Register The MCU Control Register contains bits for controlling external interrupt sensing and power management.  Bit 5 – Res: Reserved Bit This bit is reserved and will always read as zero.  Bit 4 – BODS: BOD Sleep In order to disable BOD during sleep (see Table 7-1 on page 23) the BODS bit must be written to logic one. This is controlled by a protected change sequence, as follows: 1. Write the signature for change enable of protected I/O registers to register CCP. 2. Within four instruction cycles write the BODS bit. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared when the device wakes up. Alternatively the BODS bit can be cleared by writing logic zero to it. This does not require protected sequence.  Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2 - 0 These bits select between available sleep modes, as shown in Table 7-2. Table 7-2. Sleep Mode Select  Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. Bit 7 6 5 4 3 2 1 0 0x3A ISC01 ISC00 – BODS SM2 SM1 SM0 SE MCUCR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 ADC noise reduction 0 1 0 Power-down 0 1 1 Reserved 1 0 0 Standby 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved ATtiny20 [DATASHEET] 27 8235E–AVR–03/2013 7.5.2 PRR – Power Reduction Register  Bits 7:5 – Res: Reserved Bits These bits are reserved and will always read as z