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EPCOS - Farnell Element 14
EPCOS - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
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Logiciels :
Tutoriels :
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http://www.farnell.com/datasheets/1734386.pdf
1. Product profile
1.1 General description
NPN/NPN general-purpose transistor pair in a small SOT457 (SC-74) Surface-Mounted
Device (SMD) plastic package.
1.2 Features
■ Low collector capacitance
■ Low collector-emitter saturation voltage
■ Closely matched current gain
■ Reduces number of components and board space
■ No mutual interference between the transistors
■ AEC-Q101 qualified
1.3 Applications
■ General-purpose switching and amplification
1.4 Quick reference data
BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
Rev. 01 — 25 August 2009 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
VCEO collector-emitter voltage open base - - 45 V
IC collector current - - 100 mA
hFE DC current gain VCE = 5 V; IC = 2 mA 200 300 450BC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 2 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
2. Pinning information
3. Ordering information
4. Marking
5. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
1 emitter TR1
2 base TR1
3 collector TR2
4 emitter TR2
5 base TR2
6 collector TR1
1 3 2
6 5 4
sym020
1 2 3
6 5
TR1
TR2
4
Table 3. Ordering information
Type number Package
Name Description Version
BC847DS SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
Table 4. Marking codes
Type number Marking code
BC847DS ZL
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor
VCBO collector-base voltage open emitter - 50 V
VCEO collector-emitter voltage open base - 45 V
VEBO emitter-base voltage open collector - 6 V
IC collector current - 100 mA
ICM peak collector current single pulse;
tp ≤ 1 ms
- 200 mA
IBM peak base current single pulse;
tp ≤ 1 ms
- 200 mA
Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW
Per device
Ptot total power dissipation Tamb ≤ 25 °C [1] - 380 mWBC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 3 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Tj junction temperature - 150 °C
Tamb ambient temperature −55 +150 °C
Tstg storage temperature −65 +150 °C
FR4 PCB, standard footprint
Fig 1. Per device: Power derating curve SOT457 (SC-74)
Table 5. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Tamb (°C)
−75 175 −25 25 75 125
006aab621
200
300
100
400
500
Ptot
(mW)
0
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
Rth(j-a) thermal resistance from
junction to ambient
in free air [1] - - 500 K/W
Rth(j-sp) thermal resistance from
junction to solder point
- - 250 K/W
Per device
Rth(j-a) thermal resistance from
junction to ambient
in free air [1] - - 328 K/WBC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 4 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
7. Characteristics
FR4 PCB, standard footprint
Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aab622
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
102
10
103
Zth(j-a)
(K/W)
1
δ = 1
0.75
0.50
0.33
0.10
0.05
0.02
0.01
0
0.20
Table 7. Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
ICBO collector-base cut-off
current
VCB = 30 V; IE = 0 A - - 15 nA
VCB = 30 V; IE = 0 A;
Tj = 150 °C
--5 µA
IEBO emitter-base cut-off
current
VEB = 6 V; IC = 0 A - - 100 nA
hFE DC current gain VCE =5V
IC = 10 µA - 280 -
IC = 2 mA 200 300 450
VCEsat collector-emitter
saturation voltage
IC = 10 mA; IB = 0.5 mA - 55 100 mV
IC = 100 mA; IB = 5 mA - 200 300 mV
VBEsat base-emitter
saturation voltage
IC = 10 mA; IB = 0.5 mA - 755 850 mV
IC = 100 mA; IB = 5 mA - 1000 - mV
VBE base-emitter voltage VCE =5V
IC = 2 mA 580 650 700 mV
IC = 10 mA - - 770 mVBC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 5 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
Cc collector capacitance VCB = 10 V; IE = ie = 0 A;
f = 1 MHz
- 1.9 - pF
Ce emitter capacitance VEB = 0.5 V; IC = ic = 0 A;
f = 1 MHz
- 11 - pF
fT transition frequency VCE = 5 V; IC = 10 mA;
f = 100 MHz
100 - - MHz
NF noise figure VCE = 5 V; IC = 0.2 mA;
RS =2kΩ;
f = 10 Hz to 15.7 kHz
- 1.9 - dB
VCE = 5 V; IC = 0.2 mA;
RS =2kΩ; f = 1 kHz;
B = 200 Hz
- 3.1 - dB
Table 7. Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCE =5V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Tamb = 25 °C
Fig 3. Per transistor: DC current gain as a function of
collector current; typical values
Fig 4. Per transistor: Collector current as a function
of collector-emitter voltage; typical values
006aaa533
200
400
600
hFE
0
IC (mA)
10−2 103 102 10−1 1 10
(3)
(1)
(2)
006aaa532
VCE (V)
0 10 2 4 6 8
0.08
0.12
0.04
0.16
0.20
IC
(A)
0
IB (mA) = 4.50
2.70
3.15
4.05
3.60
0.45
0.90
1.35
1.80
2.25BC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 6 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
VCE = 5 V; Tamb = 25 °C IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig 5. Per transistor: Base-emitter voltage as a
function of collector current; typical values
Fig 6. Per transistor: Base-emitter saturation voltage
as a function of collector current;
typical values
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
VCE = 5 V; Tamb = 25 °C
Fig 7. Per transistor: Collector-emitter saturation
voltage as a function of collector current;
typical values
Fig 8. Per transistor: Transition frequency as a
function of collector current; typical values
006aaa536
0.6
0.8
1
VBE
(V)
0.4
IC (mA)
10−1 103 102 1 10
006aaa534
IC (mA)
10−1 103 102 1 10
0.5
0.9
1.3
0.3
0.7
1.1
VBEsat
(V)
0.1
(1)
(2)
(3)
006aaa535
1
10−1
10
VCEsat
(V)
10−2
IC (mA)
10−1 103 102 1 10
(1)
(2)
(3)
006aaa537
IC (mA)
1 102 10
102
103
fT
(MHz)
10BC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 7 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
f = 1 MHz; Tamb = 25 °C f = 1 MHz; Tamb = 25 °C
Fig 9. Per transistor: Collector capacitance as a
function of collector-base voltage;
typical values
Fig 10. Per transistor: Emitter capacitance as a
function of emitter-base voltage; typical values
VCB (V)
0 10 2 4 6 8
006aab620
2
4
6
Cc
(pF)
0
006aaa539
VEB (V)
0 6 2 4
9
11
7
13
15
Ce
(pF)
5BC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 8 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
[2] T1: normal taping
[3] T2: reverse taping
Fig 11. Package outline SOT457 (SC-74)
Dimensions in mm 04-11-08
3.0
2.5
1.7
1.3
3.1
2.7
pin 1 index
1.9
0.26
0.10
0.40
0.25 0.95
1.1
0.9
0.6
0.2
1 3 2
6 5 4
Table 8. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 10000
BC847DS SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135
4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165BC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 9 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
11. Soldering
Fig 12. Reflow soldering footprint SOT457 (SC-74)
Fig 13. Wave soldering footprint SOT457 (SC-74)
solder lands
solder resist
occupied area
solder paste
sot457_fr
3.45
1.95
3.3 2.825
0.45
(6×)
0.55
(6×)
0.7
(6×)
0.8
(6×)
2.4
0.95
0.95
Dimensions in mm
sot457_fw
5.3
5.05
1.45
(6×)
0.45
(2×)
1.5
(4×)
2.85
1.475
1.475
solder lands
solder resist
occupied area
preferred transport
direction during soldering
Dimensions in mmBC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 10 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
12. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BC847DS_1 20090825 Product data sheet - -BC847DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 25 August 2009 11 of 12
NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
13. Legal information
13.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BC847DS
45 V, 100 mA NPN/NPN general-purpose transistor
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 August 2009
Document identifier: BC847DS_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
15. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8
8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 8
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Packing information. . . . . . . . . . . . . . . . . . . . . . 8
11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Contact information. . . . . . . . . . . . . . . . . . . . . 11
15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
http://www.farnell.com/datasheets/480916.pdf
Plug and Play Wireless CPU®
Fastrack Supreme
User Guide
Revision: 003
Date: November 2007
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without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Plug and Play Wireless CPU®
Fastrack Supreme
User Guide
Reference: WA_DEV_Fastrk_UGD_001
Revision: 003
Date: November 5, 2007
Supports Open AT® embedded ANSI C applications
Fastrack Supreme User Guide
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WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Document History
Revision Date List of revisions
001 June 5, 2007 First Issue
002 September 6, 2007 Update
003 November 5, 2007 Update
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WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Overview
The Fastrack Supreme 10 and Fastrack Supreme 20 are discrete, rugged cellular Plug
& Play Wireless CPU® offering state-of-the-art GSM/GPRS (and EGPRS for Fastrack
Supreme 20) connectivity for machine to machine applications.
Proven for reliable, stable performance on wireless networks worldwide, Wavecom’s
latest generation of Fastrack Supreme continues to deliver rapid time to market and
painless integration.
Having comparable size with the previous M1306B generation, and updated with
new features, the Fastrack Supreme offers an Internal Expansion Socket (IES)
interface accessible for customer use. Expanding application features is easy without
voiding the warrantee of the Fastrack Supreme by simply plugging in of an Internal
Expansion Socket Module (IESM) board.
Fully certified, the quad band 850/900/1800/1900 MHz Fastrack Supreme 10 offers
GPRS Class 10 capability and Fastrack Supreme 20 offers GPRS/EGPRS Class 10
capability. Both support a powerful open software platform (Open AT®). Open AT® is
the world’s most comprehensive cellular development environment, which allows
embedded standard ANSI C applications to be natively executed directly on the
Wireless CPU®.
Fastrack Supreme is controlled by firmware through a set of AT commands.
This document describes the Fastrack Supreme and gives information on the
following topics:
• general presentation,
• functional description,
• basic services available,
• technical characteristics,
• installing and using the Fastrack Supreme,
• user-level troubleshooting.
• recommended accessories to be used with the product.
Note:
This document covers the Fastrack Supreme Plug & Play alone and does not include
The programmable capabilities provided via the use of Open AT® Software
Suites.
The development guide for IESM for expanding the application feature through
the IES interface.
For detailed, please refer to the documents shown in the "Reference Documents"
section.
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without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
RoHS Directive
The Fastrack Supreme is now compliant with RoHS Directive 2002/95/EC, which sets
limits for the use of certain restricted hazardous substances. This directive states that
"from 1st July 2006, new electrical and electronic equipment put on the market does
not contain lead, mercury, cadmium, hexavalent chromium, polybrominated
biphenyls (PBB), and polybrominated diphenyl ethers (PBDE)".
Plug & Plays which are compliant with this directive are
identified by the RoHS logo on their label.
Disposing of the product
This electronic product is subject to the EU Directive
2002/96/EC for Waste Electrical and Electronic Equipment
(WEEE). As such, this product must not be disposed off at a
municipal waste collection point. Please refer to local
regulations for directions on how to dispose off this product
in an environmental friendly manner.
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without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Cautions
Information furnished herein by WAVECOM is accurate and reliable. However, no
responsibility is assumed for its use. Please read carefully the safety
recommendations given in Section 9 for an application based on Fastrack Supreme
Plug & Play.
Trademarks
®, WAVECOM®, Wireless CPU®, Open AT® and certain other trademarks and logos
appearing on this document, are filed or registered trademarks of Wavecom S.A. in
France or in other countries. All other company and/or product names mentioned may
be filed or registered trademarks of their respective owners.
Copyright
This manual is copyrighted by WAVECOM with all rights reserved. No part of this
manual may be reproduced in any form without the prior written permission of
WAVECOM. No patent liability is assumed with respect to the use of their respective
owners.
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without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Web Site Support
General information about Wavecom and its
range of products:
www.wavecom.com
Specific support is available for the Fastrack
Supreme Plug & Play Wireless CPU®:
www.wavecom.com/fastracksupreme
Open AT® Introduction: www.wavecom.com/OpenAT
Developer community for software and
hardware:
www.wavecom.com/forum
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without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Contents
DOCUMENT HISTORY ...............................................................................................2
OVERVIEW................................................................................................................3
CAUTIONS ................................................................................................................5
TRADEMARKS ..........................................................................................................5
COPYRIGHT ..............................................................................................................5
WEB SITE SUPPORT .................................................................................................6
CONTENTS ...............................................................................................................7
LIST OF FIGURES ....................................................................................................11
LIST OF TABLES......................................................................................................12
1 REFERENCES.....................................................................................................14
1.1 Reference Documents..................................................................................... 14
1.1.1 Open AT® Software Documentation ........................................................ 14
1.1.2 AT Software Documentation................................................................... 14
1.1.3 Delta between M1306B Documents ....................................................... 14
1.1.4 IESM Related Documents ....................................................................... 14
1.2 Abbreviations ................................................................................................. 15
2 PACKAGING ......................................................................................................18
2.1 Contents......................................................................................................... 18
2.2 Packaging Box................................................................................................ 19
2.3 Production Labelling ....................................................................................... 20
3 GENERAL PRESENTATION.................................................................................21
3.1 Description ..................................................................................................... 21
3.2 External Connections...................................................................................... 23
3.2.1 Connectors ............................................................................................. 23
3.2.1.1 Antenna Connector ........................................................................... 23
3.2.1.2 Power Supply Connector................................................................... 23
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3.2.1.3 Sub HD 15-pin Connector ................................................................. 24
3.2.1.4 IES Connector ................................................................................... 26
3.2.2 Power Supply Cable................................................................................ 30
4 FEATURES AND SERVICES................................................................................31
4.1 Basic Features and Services ........................................................................... 31
4.2 Additional NEW Features................................................................................ 33
4.2.1 Support Additional GSM850/PCS1900 Bands......................................... 33
4.2.2 IES Interface for Easy Expansion of Application Features ........................ 33
4.2.3 Serial Port Auto Shut Down or Improving Power Consumption .............. 33
4.2.4 Real Time Clock (RTC) for Saving Date and Time .................................... 34
4.2.5 SIM Card Lock Feature............................................................................ 34
5 USING THE FASTRACK SUPREME PLUG & PLAY...............................................35
5.1 Getting Started ............................................................................................... 35
5.1.1 Mount the Fastrack Supreme.................................................................. 35
5.1.2 Insert/extract the SIM card to/from the Fastrack Supreme....................... 35
5.1.3 Set up the Fastrack Supreme .................................................................. 37
5.1.4 Check the communication with the Fastrack Supreme............................ 38
5.1.5 Reset the Fastrack Supreme.................................................................... 39
5.2 Specific Recommendations when Using the Fastrack Supreme on Trucks...... 39
5.2.1 Recommended Power Supply Connection on Trucks .............................. 39
5.2.2 Technical Constraints on Trucks ............................................................. 40
5.3 Fastrack Supreme Operational Status............................................................. 41
5.4 Echo Function Disabled .................................................................................. 42
5.5 Verify the Received Signal Strength ................................................................ 43
5.6 Check the Pin Code Status.............................................................................. 43
5.7 Switch between EU/US Band(s) ...................................................................... 44
5.8 Check the Band(s) Selection ........................................................................... 44
5.9 Verify the Fastrack Supreme Network Registration ......................................... 45
5.10 Main AT Commands for the Plug & Play ........................................................ 46
5.11 Firmware Upgrade Procedure ......................................................................... 48
6 TROUBLESHOOTING.........................................................................................49
6.1 No Communication with the Fastrack Supreme through the Serial Link.......... 49
6.2 Receiving "ERROR" Message ........................................................................... 50
6.3 Receiving "NO CARRIER" Message .................................................................. 50
7 FUNCTIONAL DESCRIPTION..............................................................................53
7.1 Architecture.................................................................................................... 53
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7.2 EU and US Bands ........................................................................................... 54
7.2.1 General Presentation............................................................................... 54
7.2.2 AT COMMAND for Bands Switch ........................................................... 54
7.3 Power Supply ................................................................................................. 54
7.3.1 General Presentation............................................................................... 54
7.3.2 Protections.............................................................................................. 54
7.4 RS232 Serial Link............................................................................................ 55
7.4.1 General Presentation............................................................................... 55
7.4.2 Autobauding Mode................................................................................. 56
7.4.3 Pin Description........................................................................................ 56
7.4.4 Serial Port Auto shut down Feature ........................................................ 56
7.5 General Purpose Input/Output (GPIO) ............................................................. 57
7.6 BOOT ............................................................................................................. 57
7.7 RESET ............................................................................................................ 58
7.7.1 General Presentation............................................................................... 58
7.7.2 Reset Sequence ...................................................................................... 58
7.8 Audio.............................................................................................................. 59
7.8.1 Microphone Inputs.................................................................................. 59
7.8.2 Speaker Outputs ..................................................................................... 60
7.9 Real Time Clock (RTC)..................................................................................... 60
7.10 FLASH LED 61
8 TECHNICAL CHARACTERISTICS ........................................................................62
8.1 Mechanical Characteristics ............................................................................. 62
8.2 Electrical Characteristics ................................................................................. 64
8.2.1 Power Supply ......................................................................................... 64
8.2.2 Power Consumption ............................................................................... 65
8.2.3 Audio Interface ....................................................................................... 68
8.2.4 General Purpose Input/Output................................................................. 69
8.2.5 SIM Interface .......................................................................................... 69
8.2.6 RESET Signal .......................................................................................... 69
8.2.7 RF Characteristics ................................................................................... 70
8.2.7.1 Frequency Ranges ............................................................................ 70
8.2.7.2 RF Performances............................................................................... 71
8.2.7.3 External Antenna .............................................................................. 71
8.3 Environmental Characteristics ........................................................................ 72
8.4 Conformity...................................................................................................... 75
8.5 Protections ..................................................................................................... 75
8.5.1 Power Supply ......................................................................................... 75
8.5.2 Overvoltage............................................................................................. 76
8.5.3 Electrostatic Discharge............................................................................ 76
8.5.4 Miscellaneous......................................................................................... 76
9 SAFETY RECOMMENDATIONS..........................................................................77
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9.1 General Safety ................................................................................................ 77
9.2 Vehicle Safety ................................................................................................. 78
9.3 Care and Maintenance.................................................................................... 78
9.4 Your Responsibility ......................................................................................... 79
10 RECOMMENDED ACCESSORIES........................................................................80
11 ONLINE SUPPORT .............................................................................................82
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WA_DEV_Fastrk_UGD_001-003 November 5, 2007
List of Figures
Figure 1: Complete package contents ....................................................................... 18
Figure 2: Packaging box ........................................................................................... 19
Figure 3: Production Label ........................................................................................ 20
Figure 4: Fastrack Supreme general description........................................................ 21
Figure 5: Fastrack Supreme holding bridles .............................................................. 22
Figure 6: SMA connector for antenna connection ..................................................... 23
Figure 7: Power supply connector ............................................................................ 24
Figure 8: Sub HD 15-pin connector .......................................................................... 25
Figure 9: IES connector for feature expansion........................................................... 27
Figure 10: Power supply cable.................................................................................. 30
Figure 11: SIM card lock feature ............................................................................... 34
Figure 12: Fastrack Supreme mounting .................................................................... 35
Figure 13: Procedure for SIM card insertion.............................................................. 36
Figure 14: Procedure for SIM card extraction............................................................ 37
Figure 15: Recommended power supply connection on trucks ................................. 40
Figure 16: Example of electrical connection which may dramatically damage the
Fastrack Supreme................................................................................... 41
Figure 17: Functional architecture ............................................................................ 53
Figure 18: RS232 Serial Link signals......................................................................... 55
Figure 19: Reset sequence diagram.......................................................................... 59
Figure 20: Dimensioning diagram............................................................................. 63
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WA_DEV_Fastrk_UGD_001-003 November 5, 2007
List of Tables
.
Table 1: Power supply connector pin description...................................................... 24
Table 2: Sub HD 15-pin connector description.......................................................... 25
Table 3: IES Connector Description........................................................................... 27
Table 4: Basic features of the Fastrack Supreme....................................................... 31
Table 5: Fastrack Supreme operational status .......................................................... 42
Table 6: Values of received signal strength............................................................... 43
Table 7: AT+CPIN Responses ................................................................................... 43
Table 8: AT+WMBS Band Selection ......................................................................... 44
Table 9: AT+WMBS Responses................................................................................ 44
Table 10: Values of network registration................................................................... 45
Table 11: Main usual AT commands for the Plug & Play .......................................... 46
Table 12: Solutions for no connection with Fastrack Supreme through serial link..... 49
Table 13: Solutions for "NO CARRIER" message ........................................................ 51
Table 14: Interpretation of extended error code ........................................................ 52
Table 15: Mechanical characteristics ........................................................................ 62
Table 16: Electrical characteristics ............................................................................ 64
Table 17: Effects of power supply defect .................................................................. 64
Table 18: Power consumption in connected modes (1*)........................................... 65
Table 19: Power consumption in non-connected modes(1*)..................................... 66
Table 20: Audio parameters caracteristics ................................................................ 68
Table 21: Microphone inputs internal audio filter characteristics .............................. 68
Table 22: Recommended characteristics for the microphone: ................................... 68
Table 23: Recommended characteristics for the speaker: ......................................... 69
Table 24: Operating conditions................................................................................. 69
Table 25: SIM card characteristics............................................................................ 69
Table 26: Electrical characteristics ............................................................................ 69
Table 27: Operating conditions................................................................................. 70
Table 28: Frequency ranges...................................................................................... 70
Table 29: Receiver and transmitter RF performances................................................ 71
Table 30: External antenna characteristics................................................................ 71
Table 31: Ranges of temperature.............................................................................. 72
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Table 32: Environmental standard constraints.......................................................... 73
Table 33: List of recommended accessories.............................................................. 80
Table 34: Fastrack Supreme Family .......................................................................... 81
Fastrack Supreme User Guide
References
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1 References
1.1 Reference Documents
For more details, several reference documents may be consulted. The Wavecom
reference documents are provided in the Wavecom documents package contrary to
the general reference documents, which are not Wavecom owned.
1.1.1 Open AT® Software Documentation
[1] Getting started with Open AT® SDK v4.22 (Ref.WM_DEV_OAT_UGD_048)
[2] Tutorial for Open AT® IDE V1.04 (Ref. WM_DEV_OAT_UGD_044)
[3] Tools Manual for Open AT® IDE V1.04 (Ref. WM_DEV_OAT_UGD_045)
[4] Basic Development Guide for Open AT®V4.21 (Ref. WM_DEV_OAT_UGD_050)
[5] ADL User Guide for Open AT®V4.21 (Ref. WM_DEV_OAT_UGD_051)
[6] Open AT® v4.22 Official Release Note (Ref. WM_DEV_OAT_DVD_338)
1.1.2 AT Software Documentation
[7] AT commands interface Guide for FW v6.63 (Ref. WM_DEV_OAT_UGD_049)
[8] Open AT® Firmware v6.63 Customer Release Note
(Ref.WM_PGM_OAT_CRN_001)
1.1.3 Delta between M1306B Documents
[9] Delta between M1306B and Fastrack Supreme (Ref. WA_DEV_Fastrk_UGD_004)
1.1.4 IESM Related Documents
[10] IESM Product Technical Specification (Ref. WA_DEV_Fastrk_PTS_001)
[11] IESM-GPS+USB User Guide (Ref. WA_DEV_Fastrk_UGD_002)
[12] IESM-GPS+USB Installation Guide (Ref. WA_DEV_Fastrk_UGD_003)
[13] IESM-IO+USB Installation Guide (Ref. WA_DEV_Fastrk_UGD_005)
[14] IESM-IO+USB User Guide (Ref. WA_DEV_Fastrk_UGD_006)
[15] IESM-IO+USB+GPS Installation Guide (Ref. WA_DEV_Fastrk_UGD_007)
[16] IESM-IO+USB+GPS User Guide (Ref. WA_DEV_Fastrk_UGD_008)
Note:
New versions of software may be available. Wavecom recommends customers to
check the web site for the latest documentation.
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References
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1.2 Abbreviations
Abbreviation Definition
AC Alternating Current
ACM Accumulated Call Meter
AMR Adaptive Multi-Rate
AT ATtention (prefix for Wireless CPU® commands)
CLK CLocK
CMOS Complementary Metal Oxide Semiconductor
CS Coding Scheme
CTS Clear To Send
dB Decibel
dBc Decibel relative to the Carrier power
dBi Decibel relative to an Isotropic radiator
dBm Decibel relative to one milliwatt
DC Direct Current
DCD Data Carrier Detect
DCE Data Communication Equipment
DCS Digital Cellular System
DSR Data Set Ready
DTE Data Terminal Equipment
DTMF Dual Tone Multi-Frequency
DTR Data Terminal Ready
EEPROM Electrically Erasable Programmable Read-Only Memory
EFR Enhanced Full Rate
E-GSM Extended GSM
EMC ElectroMagnetic Compatibility
EMI ElectroMagnetic Interference
ESD ElectroStatic Discharges
ETSI European Telecommunications Standards Institute
FIT Series of connectors (micro-FIT)
FR Full Rate
FTA Full Type Approval
GCF Global Certification Forum
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Abbreviation Definition
GND GrouND
GPIO General Purpose Input Output
GPRS General Packet Radio Service
GSM Global System for Mobile communications
HR Half Rate
I Input
IEC International Electrotechnical Commission
IES Internal Expansion Socket
IESM Internal Expansion Socket Module
IMEI International Mobile Equipment Identification
I/O Input / Output
LED Light Emitting Diode
MAX MAXimum
ME Mobile Equipment
MIC MICrophone
Micro-Fit Family of connectors from Molex
MIN MINimum
MNP Microcom Networking Protocol
MO Mobile Originated
MS Mobile Station
MT Mobile Terminated
NOM NOMinal
O Output
Pa Pascal (for speaker sound pressure measurements)
PBCCH Packet Broadcast Control CHannel
PC Personal Computer
PCL Power Control Level
PDP Packet Data Protocol
PIN Personal Identity Number
PLMN Public Land Mobile Network
PUK Personal Unblocking Key
RF Radio Frequency
RFI Radio Frequency Interference
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References
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Abbreviation Definition
RI Ring Indicator
RMS Root Mean Square
RTS Request To Send
RX Receive
SIM Subscriber Identification Module
SMA SubMiniature version A RF connector
SMS Short Message Service
SNR Signal-to-Noise Ratio
SPL Sound Pressure Level
SPK SpeaKer
SRAM Static RAM
TCP/IP Transmission Control Protocol / Internet Protocol
TDMA Time Division Multiple Access
TU Typical Urban fading profile
TUHigh Typical Urban, High speed fading profile
TX Transmit
TYP TYPical
VSWR Voltage Stationary Wave Ratio
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Packaging
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2 Packaging
2.1 Contents
The complete package content of the Fastrack Supreme consists of (see):
• one packaging box (A),
• one Fastrack Supreme (B),
• two holding bridles (C),
• one power supply cable with fuse integrated (D)
• a mini notice (E) with:
a summary of the main technical features,
safety recommendations,
EC declaration of conformity.
Figure 1: Complete package contents
A
D
E C
B
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2.2 Packaging Box
The packaging box is a carton box (see) with the following external dimensions:
• width: 54.5 mm,
• height: 68 mm,
• length: 108 mm.
A packaging label is slicked on the packaging box cover and supports the:
• WAVECOM logo,
• Product reference (Fastrack Supreme 20 or Fastrack Supreme 10),
• CE marking
• 15-digit IMEI code
• Open AT® Logo
• WEEE logo
Figure 2: Packaging box
The packaging label dimensions are:
• height: 40 mm,
• length: 65 mm.
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Packaging
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2.3 Production Labelling
A production label (see Figure 3) located at the Fastrack Supreme back side gives the
following information:
• product reference (Fastrack Supreme 10 or Fastrack Supreme 20),
• part number (WM20230),
• CE marking,
• 15-digit IMEI code,
• Open AT® logo
• Made by Wavecom
Figure 3: Production Label
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General Presentation
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3 General Presentation
3.1 Description
The Fastrack Supreme description is given in the Figure 4 below.
IES connector for
expanding feature, like
GPS, USB, I/O
expander…
Refer to Section
3.2.1.4
Removed Screw
for Back Plate
Sub HD
connector
Micro- Fit
connector
Back Plate
SIM card inside Back Cap
SIM connector
Lock switch of
SIM connector
SMA
connector
GSM LED
Indicator
Screw for Back
Plate
Removed Back
Plate
Back Cap with 5
screws
Figure 4: Fastrack Supreme general description
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CAUTION: Users are free to remove the back plate for IESM board plug in/unplug
without voiding the warrantee of the Fastrack Supreme. However, the warrantee will
be voided if unscrewing any screw of the back cap.
In addition, two holding bridles are provided to tighten the Fastrack Supreme on a
support.
Figure 5: Fastrack Supreme holding bridles
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3.2 External Connections
3.2.1 Connectors
3.2.1.1 Antenna Connector
The antenna connector is a SMA type connector for a 50 Ω RF connection.
Figure 6: SMA connector for antenna connection
3.2.1.2 Power Supply Connector
The power supply connector is a 4-pin Micro FIT connector for:
• external DC Power Supply connection,
• GPIOs connection (two General Purpose Input/Output signals available).
SMA connector
for antenna
connection
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General Presentation
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1 2
3 4
Figure 7: Power supply connector
Table 1: Power supply connector pin description
Pin
#
Signal I/O I/O type Description Reset
State
Comment
1 V+BATTERY I Power
supply
Battery voltage input:
5.5 V Min.
13.2 V Typ.
32 V Max.
High current
2 GND Power
supply
Ground
3 GPIO21 I/O 2V8 General Purpose
Input/output
Undefined Not mux
4 GPIO25 I/O 2V8 General Purpose
Input/output
Z Multiplex with
INT1
Warning:
Both pin 3 and pin 4 are used by GPIO interface. It is strictly prohibited to connect
them to any power supply at the risk of damage to the Fastrack Supreme.
3.2.1.3 Sub HD 15-pin Connector
The Sub D high density 15-pin connector is used for:
• RS232 serial link connection,
• Audio lines (microphone and speaker) connection,
• BOOT and RESET signal connection.
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5 4 3 2 1
10 9 8 7 6
15 14 13 12 11
Figure 8: Sub HD 15-pin connector
Table 2: Sub HD 15-pin connector description
Pin # Signal
(CCITT / EIA)
I/O I/O type Description Comment
1 CDCD/CT109 O STANDARD
RS232
RS232
Data Carrier Detect
2 CTXD/CT103 I STANDARD
RS232
RS232
Transmit serial data
3 BOOT I CMOS Boot This signal must
not be
connected. Its
use is strictly
reserved to
Wavecom or
competent
retailers.
4 CMIC2P I Analog Microphone
positive line
5 CMIC2N I Analog Microphone
negative line
6 CRXD/CT104 O STANDARD
RS232
RS232
Receive serial data
7 CDSR/CT107 O STANDARD
RS232
RS232
Data Set Ready
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Pin # Signal
(CCITT / EIA)
I/O I/O type Description Comment
8 CDTR/CT108-2 I STANDARD
RS232
RS232
Data Terminal Ready
9 GND - GND Ground
10 CSPK2P O Analog Speaker
positive line
11 CCTS/CT106 O STANDARD
RS232
RS232
Clear To Send
12 CRTS/CT105 I STANDARD
RS232
RS232
Request To Send
13 CRI/CT125 O STANDARD
RS232
RS232
Ring Indicator
14 RESET I/O Schmitt Supreme Plug & Play
reset
Active low
15 CSPK2N O Analog Speaker
negative line
3.2.1.4 IES Connector
The IES connector is a 50 pins board-to-board connector for expanding application
features like GPS, USB, I/O expander… Currently there are already 3 IESM boards
available for customer to expand the Fastrack Supreme features immediately. They
are:
IESM GPS+USB
IESM I/O+USB
IESM I/O+USB+GPS
For detail, please refer to Document in Section 1.1.4.
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For sales and support, please contact Wavecom sales/FAE or your distributor.
Figure 9: IES connector for feature expansion
Table 3: IES Connector Description
Pin Signal Name
Number Nominal Mux
I/O
type Voltage I/O* Reset
State Description Dealing with
unused pins
1 GND Ground
2 GND Ground
3 GPIO4 COL0 C8 GSM-1V8 I/O Pull-up Keypad column 0 NC
4 GPIO5 COL1 C8 GSM-1V8 I/O Pull-up Keypad column 1 NC
5 GPIO6 COL2 C8 GSM-1V8 I/O Pull-up Keypad column 2 NC
6 GPIO7 COL3 C8 GSM-1V8 I/O Pull-up Keypad column 3 NC
7 VPADUSB
VPAD-USB I USB Power supply
input
NC
8 USB-DP VPAD-USB I/O USB Data NC
9 USB-DM VPAD-USB I/O USB Data NC
10 GSM-
1V8*
GSM-1V8 O
1.8V Supply Output
(for GPIO pull-up
only)
NC
11 GSM-
2V8*
GSM-1V8 O
2.8V Supply Output
(for GPIO pull-up
only)
NC
12 BOOT
GSM-1V8 I Not Used
Add a test point / a
jumper/ a switch to
VCC_1V8 (Pin 10) in
case Download
Specific mode is
used (See product
specification for
details)
Pin 2
Pin 1
Pin 50
Pin 49
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Pin Signal Name
Number Nominal Mux
I/O
type Voltage I/O* Reset
State Description Dealing with
unused pins
13 ~RESET C4 GSM-1V8 I/O RESET Input NC or add a test
point
14 AUX-ADC A2 Analog I Analog to Digital
Input
Pull to GND
15 ~SPI1-CS GPIO31 C1 GSM-2V8 O Z SPI1 Chip Select NC
16 SPI1-CLK GPIO32 C1 GSM-2V8 O Z SPI1 Clock NC
17 SPI1-I GPIO30 C1 GSM-2V8 I Z SPI1 Data Input NC
18 SPI1-IO GPIO29 C1 GSM-2V8 I/O Z SPI1 Data Input /
Output
NC
19 SPI2-CLK GPIO32 C1 GSM-2V8 O Z SPI2 Clock NC
20 SPI2-IO GPIO33 C1 GSM-2V8 I/O Z SPI2 Data Input /
Output
NC
21 ~SPI2-CS GPIO35 C1 GSM-2V8 O Z SPI2 Chip Select NC
22 SPI2-I GPIO34 C1 GSM-2V8 I Z SPI2 Data Input NC
23 CT104-
RXD2
GPIO15 C1 GSM-1V8 O Z Auxiliary RS232
Receive
Add a test point for
firmware upgrade
24 CT103-
TXD2 GPIO14
C1
GSM-1V8 I Z
Auxiliary RS232
Transmit
(TXD2) Pull-up to
VCC_1V8 with
100k and add a
test point for
firmware update
25 ~CT106-
CTS2 GPIO16
C1
GSM-1V8 O Z
Auxiliary RS232
Clear To Send
(CTS2) Add a test
point for firmware
update
26 ~CT105-
RTS2
GPIO17
C1
GSM-1V8 I Z
Auxiliary RS232
Request To Send
(RTS2) Pull-up to
VCC_1V8 with
100k and add a
test point for
firmware update
27 GPIO8 COL4 C8 GSM-1V8 I/O Pull-up Keypad column 4 NC
28 GPIO26 SCL A1 Open Drain O Z I²C Clock NC
29 GPIO19 C1 GSM-2V8 I/O Z NC
30 GPIO27 SDA A1 Open Drain I/O Z I²C Data NC
31 GPIO20 C1 GSM-2V8 I/O Undefine
d
NC
32 INT0 GPIO3
C1
GSM-1V8 I Z Interruption 0 Input
If INT0 is not used,
it should be
configured as GPIO
33 GPIO23 ** C1 GSM-2V8 I/O Z NC
34 GPIO22 ** C1 GSM-2V8 I/O Z NC
35 ~CT108-
2-DTR1 GPIO41
C1
GSM-2V8 I Z
Main RS232 Data
Terminal Ready
(DTR1) Pull-up to
VCC_2V8 with
100k
36 PCMSYNC
GSM-1V8 O Pulldown
PCM Frame
Synchro
NC
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Pin Signal Name
Number Nominal Mux
I/O
type Voltage I/O* Reset
State Description Dealing with
unused pins
37 PCM-IN C5 GSM-1V8 I Pull-up PCM Data Input NC
38 PCM-CLK GSM-1V8 O Pulldown
PCM Clock NC
39 PCM-OUT GSM-1V8 O Pull-up PCM Data Output NC
40 AUX-DAC Analog O Digital to Analog
Output
NC
41 VCC-2V8 VCC_2V8 O LDO 2.8V Supply
Output
NC
42 GND Ground
43 DC-IN
DC-IN from
5.5V~32V
DC
O
DC voltage input
through Micro-Fit
connector
NC
44 DC-IN
DC-IN from
5.5V~32V
DC
O
DC voltage input
through Micro-Fit
connector
NC
45 GND Ground
46 4V 4V O 4V DC/DC converter
Output
NC
47 4V 4V O 4V DC/DC converter
Output
NC
48 GND Ground
49 GND Ground
50 GND Ground
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3.2.2 Power Supply Cable
Figure 10: Power supply cable
Component Characteristics
Micro-Fit connector
4-pin
Part number: MOLEX 43025-0400
Cable Cable length: ∼1.5 m
Wire Core: tinned copper 24 x 0.2 mm
Section: 0.75 mm2
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4 Features and Services
4.1 Basic Features and Services
Basic features of the Fastrack Supreme and available services are summarized in the
table below.
Table 4: Basic features of the Fastrack Supreme
Features GSM850 / GSM900 DCS1800 / PCS1900
Open AT® Open AT® programmable:
Native execution of embedded standard ANSI C applications,
Custom AT command creation,
Custom application library creation,
Standalone operation.
Standard 850MHz / 900 MHz.
E-GSM compliant.
Output power: class 4 (2W).
Fully compliant with ETSI GSM
phase 2 + small MS.
1800 MHz / 1900MHz
Output power: class 1 (1W).
Fully compliant with ETSI GSM
phase 2 + small MS.
GPRS Class 10.
PBCCH support.
Coding schemes: CS1 to CS4.
Compliant with SMG31bis.
Embedded TCP/IP stack.
EGPRS Output power: 0.5W Output power: 0.4W
(for
Fastrack
Supreme
20 only)
Class 10.
PBCCH support.
Coding schemes: MCS1 to MCS9.
Compliant with SMG31bis.
Embedded TCP/IP stack.
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Features GSM850 / GSM900 DCS1800 / PCS1900
Interfaces RS232 (V.24/V.28) Serial interface supporting:
Baud rate (bits/s): 300, 600, 1200, 2400, 4800, 9600, 19200,
38400, 57600, 115200, 230400, 460800 and 921600.
Autobauding (bits/s): from 1200 to 921600.
2 General Purpose Input/Output gates (GPIOs) available.
1.8 V / 3 V SIM interface.
AT command set based on V.25ter and GSM 07.05 & 07.07.
Open AT® interface for embedded application.
Open AT® Plug-In Compatible.
SMS Text & PDU.
Point to point (MT/MO).
Cell broadcast.
Data Data circuit asynchronous.
Transparent and Non Transparent modes.
Up to 14.400 bits/s.
MNP Class 2 error correction.
V42.bis data compression.
Fax Automatic fax group 3 (class 1 and Class 2).
Audio Echo cancellation
Noise reduction
Telephony.
Emergency calls.
Full Rate, Enhanced Full Rate, Half Rate operation and Adaptive
Multi-Rate (FR/EFR/HR/AMR).
Dual Tone Multi Frequency function (DTMF).
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Features GSM850 / GSM900 DCS1800 / PCS1900
GSM
supplement
services
Call forwarding.
Call barring.
Multiparty.
Call waiting and call hold.
Calling line identity.
Advice of charge.
USSD
Other DC power supply
Real Time Clock with calendar
Complete shielding
For other detailed technical characteristics, refer to Section 8.
4.2 Additional NEW Features
4.2.1 Support Additional GSM850/PCS1900 Bands
Apart from GSM900/DCS1800, the Fastrack Supreme Plug & Play now supports also
the GSM850/PCS1900 bands. Fastrack Supreme is fully compliant to PTCRB and
FCC also.
4.2.2 IES Interface for Easy Expansion of Application Features
The Fastrack Supreme Plug & Play offers a 50 pin Internal Expansion Socket (IES)
Interface accessible for customer use. It is the additional interface which is easy for
customers to expand their application features without voiding the warrantee of the
Fastrack Supreme, by simply plugging in an Internal Expansion Socket Module (IESM)
board through the matting connector of the IES interface.
Thanks to the flexible IES interface, customers are ready to expand the application
features by plugging in the corresponding Internal Expansion Socket Module (IESM)
of GPS, I/O expander…, etc.
For brief description of the interface, please refer to Section 3.2.1.4.
For technical detail, please refer to Document [10] or contact your Wavecom
distributor or Wavecom FAE.
4.2.3 Serial Port Auto Shut Down or Improving Power Consumption
In order to save power consumption when there is no data communication between
the Plug & Play and the DTE, Fastrack Supreme has now implement the Serial Port
Auto Shut Down feature. User can activate or deactivate the Serial Port Auto Shut
Down mode by simple AT-command.
For detail, please refer to Section 7.4.4.
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4.2.4 Real Time Clock (RTC) for Saving Date and Time
The Fastrack Supreme has now implemented the Real Time Clock for saving date and
time when the Plug & Play is unplugged from the DC power supply through the DC
power cable.
For detail, please refer to Section 7.9.
4.2.5 SIM Card Lock Feature
The Fastrack Supreme has now implemented a SIM connector having a carrier with
lock. This helps ensuring the user to have proper SIM card insertion and locked
before proper use of GSM network.
SIM card is inserted but not locked. GSM
network is not ready for use. Only
emergency call 112 is possible.
SIM card is inserted and being locked
properly. GSM network is ready for use.
Figure 11: SIM card lock feature
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5 Using the Fastrack Supreme Plug & Play
5.1 Getting Started
5.1.1 Mount the Fastrack Supreme
To mount the Fastrack Supreme on its support, bind it using the holding bridles as
shown in the Figure 12 below.
Figure 12: Fastrack Supreme mounting
For the drill template, refer to Figure 20.
5.1.2 Insert/extract the SIM card to/from the Fastrack Supreme
In order to insert the SIM card to the Fastrack Supreme, please follow the procedure
in Figure 13.
Step 1: Ready the SIM card in the
orientation as shown.
Step 2: Slide in the SIM card inside the SIM
holder.
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Step 3: Use a tool to help pushing the SIM
card inside the SIM holder.
Step 4: Push until you hear a “click” sound.
Step 5: Release the tool. The SIM card is
now put inside the SIM holder.
Step 6: Move the carrier toward center to
lock properly the SIM card. GSM network
is ready for use.
Figure 13: Procedure for SIM card insertion
Caution: Please make sure the SIM card is horizontally inserted into the SIM holder.
Otherwise, the SIM card may be blocked inside the Fastrack Supreme.
In order to extract the SIM card from the Fastrack Supreme, please follow the
procedure in Figure 14.
Step 1: SIM card is put inside the SIM
holder and locked properly before
extraction.
Step 2: Move the carrier toward the edge
to unlock the SIM card.
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Step 3: Use a tool to help pushing the SIM
card a little bit inside the SIM holder until
you hear a “click” sound.
Step 4: The SIM card spring out a little bit.
Step 5: You can easily extract the SIM card
by hand now.
Step 6: SIM card is extracted.
Figure 14: Procedure for SIM card extraction
5.1.3 Set up the Fastrack Supreme
To set up the Fastrack Supreme, perform the following operations:
• Insert the SIM card into the SIM card holder of the Fastrack Supreme.
• Lock the SIM card by sliding the lever towards the SIM card.
• Connect the antenna to the SMA connector.
• Connect both sides of the serial and control cable (15-pin Sub HD connector on
the Fastrack Supreme side).
• Connect the power supply cable to the external power supply source.
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WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Note:
For automotive application, it is recommended to connect the V+BATTERY line of the
Fastrack Supreme directly to the battery positive terminal.
• Plug the power supply cable into the Fastrack Supreme and switch on the
external power supply source.
• The Fastrack Supreme is ready to work. Refer to Section 5.10 for the
description of AT commands used to configure the Fastrack Supreme.
5.1.4 Check the communication with the Fastrack Supreme
To check the communication with the Fastrack Supreme, do the following operations:
• Connect the RS232 link between the DTE (port COM) and the Fastrack
Supreme (DCE).
• Configure the RS232 port of the DTE as follows:
Bits per second: 115.200 bps,
Data bits: 8,
Parity: None,
Stop bits: 1,
Flow control: hardware.
• Using a communication software such as a HyperTerminal, enter the AT↵
command. The response of the Fastrack Supreme must be OK displayed in
the HyperTerminal window.
• If the communication cannot be established with the Fastrack Supreme, do
the following:
Check the RS232 connection between the DTE and the Fastrack
Supreme (DCE),
Check the configuration of the port COM used on the DTE.
• Example of AT commands which can be used after getting started the
Fastrack Supreme:
AT+CGMI: Fastrack Supreme answer is "WAVECOM MODEM"
when serial link is OK.
AT+CPIN=xxxx: to enter a PIN code xxxx (if activated).
AT+CSQ: to verify the received signal strength.
AT+CREG?: to verify the registration of the Fastrack Supreme Plug
& Play on the network.
ATD: to initiate a voice call.
ATH: to hang up (end of call).
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For further information on these AT commands and their associated parameters,
refer to "AT Commands Interface Guide" [7].
5.1.5 Reset the Fastrack Supreme
To reset the Fastrack Supreme, a hardware reset signal is available on pin 14 of the
Sub HD 15-pin connector (RESET).
The Fastrack Supreme reset is carried out when this pin is low for at least 200 μs.
Warning This signal has to be considered as an emergency reset only. For further
details on the Fastrack Supreme reset, refer to Section 7.7.
5.2 Specific Recommendations when Using the Fastrack
Supreme on Trucks
Warning: The power supply connection of the Fastrack Supreme must NEVER be
directly connected to the truck battery.
5.2.1 Recommended Power Supply Connection on Trucks
All trucks have a circuit breaker on the exterior of the cabin. The circuit breaker is
used for safety reasons: if a fire blazes in the trucks, (for example, on the wiring
trunk) the driver may cut the current source to avoid any damage (explosion). The
circuit breaker is connected to the truck ground, most often associated with the fuse
box.
Most of truck circuit breakers do not cut the Positive Supply line of the battery, but
cut the ground line of the later.
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FASTRACK
Supreme
Figure 15: Recommended power supply connection on trucks
Figure 15 gives the recommended power supply connection where the ground
connection of the Fastrack Supreme is not directly connected to the battery but is
connected after the Circuit Breaker (on the truck ground or the fuse box).
5.2.2 Technical Constraints on Trucks
It is highly not recommended to connect directly the power supply on the battery
rather than on the circuit breaker. The Fastrack Supreme may be damaged when
starting the truck if the circuit breaker is switched OFF (in this case, the truck ground
and the battery ground will be connected through the Fastrack Supreme as shown in
the Figure 16).
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FASTRACK
Supreme
Figure 16: Example of electrical connection which may dramatically damage the
Fastrack Supreme
Figure 16 gives an example of electrical connection which may dramatically damage
the Fastrack Supreme when its ground connection is directly connected to the battery
ground.
In this example, when the circuit breaker is switched OFF, the current flows through
the Fastrack Supreme and powers the electrical circuit of the truck (for example,
dashboard).
Furthermore, when the Starter Engine command will be used, it will destroy the
cables or the Fastrack Supreme.
Since the internal tracks are not designed to support high current (up to 60 A when
starting the truck), they will be destroyed.
5.3 Fastrack Supreme Operational Status
The Fastrack Supreme operational status is given by the red LED status located next
to the SIM connector on the Fastrack Supreme panel.
The Table 5 below gives the meaning of the various statuses available.
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Table 5: Fastrack Supreme operational status
LED Status LED light activity Fastrack Supreme Plug & Play status
LED ON permanent Fastrack Supreme is switched ON but
not registered on the network
LED Flashing slowly Fastrack Supreme is switched ON and
registered on the network, but no
communication is in progress (Idle mode)
ON
LED Flashing rapidly Fastrack Supreme is switched ON and
registered on the network, and a
communication is in progress
OFF LED OFF Fastrack Supreme is switched OFF, or
Flash LED is disabled* by the user.
*: Flash LED can be disabled by user when in Slow Standby mode in order to save
power consumption. For detail, please refer to Section 7.10.
5.4 Echo Function Disabled
If no echo is displayed when entering an AT command, that means:
• The "local echo" parameter of your communication software (such as
HyperTerminal) is disabled.
• The Fastrack Supreme echo function is disabled.
To enable the Fastrack Supreme echo function, enter the ATE1.
When sending AT commands to the Fastrack Supreme by using a communication
software, it is recommended:
• to disable the "local echo" parameter of your communication software (such as
HyperTerminal),
• to enable the Fastrack Supreme echo function (ATE1 command).
In a Machine To Machine communication with the Fastrack Supreme, it is
recommended to disable the Fastrack Supreme echo function (ATE0 command) in
order to avoid useless CPU processing.
For further information on ATE0 and ATE1 commands, refer to "AT Commands
Interface Guide" [7].
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5.5 Verify the Received Signal Strength
The Fastrack Supreme establishes a call only if the received signal is sufficiently
strong.
To verify the received signal strength, do the following operations:
• Using a communication software such as HyperTerminal, enter the AT
command AT+CSQ.
The response returned has the following format:
+CSQ: , with:
• = received signal strength indication,
• = channel bit error rate.
• Verify the value returned using the Table 6 below.
Table 6: Values of received signal strength
Value of received signal
strength indication ()
Interpretation of the
received signal strength
0 - 10 Insufficient(*)
11 - 31 Sufficient(*)
32 - 98 Not defined
99 No measure available
(*) Based on general observations.
For further information on AT commands, refer to "AT Commands Interface Guide" [7].
5.6 Check the Pin Code Status
To check that the pin code has been entered, use a communication software such as
a HyperTerminal, then enter AT+CPIN? command.
The table below gives the main responses returned:
Table 7: AT+CPIN Responses
AT+CPIN response (*) Interpretation
+CPIN: READY Code PIN has been entered
+CPIN: SIM PIN Code PIN has not been entered
(*)For further information on the other possible responses and their meaning, refer to
"AT Commands Interface Guide" [7].
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5.7 Switch between EU/US Band(s)
To switch between EU/US band(s) for the Fastrack Supreme, use a communication
software such as a HyperTerminal, then enter AT+WMBS=[,]
command.
The table below gives the commands for various band(s) selection:
Table 8: AT+WMBS Band Selection
AT+WMBS response (*) Interpretation
AT+WMBS=0,x Select mono band mode 850MHz.
AT+WMBS=1,x Select mono band mode extended 900MHz
AT+WMBS=2,x Select mono band mode 1800MHz
AT+WMBS=3,x Select mono band mode 1900MHz
AT+WMBS=4,x Select dual band mode 850/1900MHz
AT+WMBS=5,x Select dual band mode extended
900MHz/1800MHz
AT+WMBS=6,x Select dual band mode extended
900MHz/1900MHz
(*)For further information on the other possible responses and their meaning, refer to
"AT Commands Interface Guide" [7].
Remark:
x=0 : The Plug & Play will have to be reset to start on specified band(s).
x=1 : The change is effective immediately. This mode is forbidden while in
communication and during Plug & Play initialization.
Refer to "AT Commands Interface Guide" [7] for further information on AT commands.
5.8 Check the Band(s) Selection
To check the band selection for the Fastrack Supreme, use a communication software
such as a HyperTerminal, then enter AT+WMBS? command.
The table below gives the main responses returned:
Table 9: AT+WMBS Responses
AT+WMBS response (*) Interpretation
+WMBS: 0,x Mono band mode 850MHz is selected
+WMBS: 1,x Mono band mode extended 900MHz is selected
+WMBS: 2,x Mono band mode 1800MHz is selected
+WMBS: 3,x Mono band mode 1900MHz is selected
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AT+WMBS response (*) Interpretation
+WMBS: 4,x Dual band mode 850/1900MHz are selected
+WMBS: 5,x Dual band mode extended 900MHz/1800MHz
are selected
+WMBS: 6,x Dual band mode extended 900MHz/1900MHz
are selected
(*)For further information on the other possible responses and their meaning, refer to
"AT Commands Interface Guide" [7].
5.9 Verify the Fastrack Supreme Network Registration
1. Make sure a valid SIM card has been previously inserted and locked in the
Fastrack Supreme SIM card holder.
2. Using a communication software such as a HyperTerminal, enter the following
AT commands:
a. AT+CPIN=xxxx to enter PIN code xxxx.
b. AT+WMBS? To check the current band setting in the Plug & Play
c. AT+WMBS=[,] To switch band/mode when needed
d. AT+CREG?. To ascertain the registration status.
The format of the returned response is as follows:
+CREG: , with:
• = unsolicited registration message configuration,
• = registration state.
3. Verify the state of registration according the returned value given in the table
below.
Table 10: Values of network registration
Returned Value (*)
,
Network registration
+CREG: 0,0 No (not registered)
+CREG: 0,1 Yes (registered, home network)
+CREG: 0,5 Yes (registered, roaming)
(*)For further information on the other returned values and their meaning, refer to "AT
Commands Interface Guide" [7].
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If the Fastrack Supreme is not registered, perform the following procedure:
• Check the connection between the Fastrack Supreme and the antenna.
• Verify the signal strength to determine the received signal strength (refer to
Section 5.5).
Note: For information on AT command relating to the network registration in GPRS
mode, and in particular: CGREG, CGCLASS, CGATT, refer to "AT Commands Interface
Guide" [7].
5.10 Main AT Commands for the Plug & Play
The table below lists the main AT commands required for starting the Plug & Play.
For other AT commands available or further information on the AT commands, refer
to "AT Commands Interface Guide" [7].
Table 11: Main usual AT commands for the Plug & Play
Description AT commands Fastrack Supreme Plug & Play
response
Comment
Check for
selected
band(s)
AT+WMBS? +WMBS:,
OK
Current
selected band
mode is return
AT+WMBS= OK Band switch is
accepted, Plug
& Play has to
be reset for
change to be
effective
AT+WMBS=,0 OK Band switch is
accepted, Plug
& Play has to
be reset for
change to be
effective
AT+WMBS=,1 OK Band switch is
accepted and
GSMS stack
restarted
Band(s) switch
AT+WMBS= +CME ERROR: 3 Band not
allowed
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Description AT commands Fastrack Supreme Plug & Play
response
Comment
OK PIN Code
accepted.
+CME ERROR: 16 Incorrect PIN
Code
(with +CMEE =
1 mode) (1*)
Enter PIN Code AT+CPIN=xxxx
(xxxx = PIN code)
+CME ERROR: 3 PIN code already
entered
(with +CMEE =
1 mode) (1*)
+CREG: 0,1 Fastrack
Supreme Plug
& Play
registered on
the network.
+CREG: 0,2 Fastrack
Supreme Plug
& Play not
registered
on the
network,
registration
attempt.
Network
registration
checking
AT+CREG?
+CREG: 0,0 Fastrack
Supreme Plug
& Play not
registered
on the
network, no
registration
attempt.
Receiving an
incoming call
ATA OK Answer the
call.
OK Communication
established.
+CME ERROR: 11 PIN code not
entered (with
+CMEE =
1 mode).
Initiate a call ATD;
(Don’t forget the « ; »
at the end for « voice »
call)
+CME ERROR: 3 AOC credit
exceeded or a
communication
is already
established.
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Description AT commands Fastrack Supreme Plug & Play
response
Comment
Initiate an
emergency call
ATD112;
(Don’t forget the « ; »
at the end for « voice »
call)
OK Communication
established.
Communication
loss
NO CARRIER
Hang up ATH OK
Store the
parameters in
EEPROM
AT&W OK The
configuration
settings are
stored in
EEPROM.
(1*) The command "AT+CMEE=1" switch to a mode enabling more complete error diagnostics.
5.11 Firmware Upgrade Procedure
The firmware upgrade procedure is used to update the firmware embedded into the
Fastrack Supreme.
That procedure consists in downloading the firmware into internal memories through
the RS232 serial link available on the SUB-D 15-pin connector.
Refer to "Firmware upgrade procedure" document for a detailed description of this
procedure.
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6 Troubleshooting
This section of the document describes possible problems encountered when using
the Fastrack Supreme and their solutions.
To review other troubleshooting information, refer the ‘FAQs’ (Frequently Asked
Questions) page at www.wavecom.com/fastracksupreme.
6.1 No Communication with the Fastrack Supreme through the
Serial Link
If the Fastrack Supreme does not answer to AT commands through the serial link,
refer to the table below for possible causes and solutions.
Table 12: Solutions for no connection with Fastrack Supreme through serial link
If the Supreme
returns
then ask Action
Is the Fastrack Supreme
powered correctly?
Make sure the external power
supply is connected to the Fastrack
Supreme and provides a voltage in
the range of 5.5 V to 32 V.
Is the serial cable connected at
both sides?
Check the serial cable connection
Nothing
Does the serial cable follow
correctly pin assignment
shown in paragraph 3.2.1.2.
Connect the cable by following pin
assignment given in paragraph
3.2.1.1.
Is the communication program
properly configured on PC?
Ensure the setting of the
communication program is fit to
setting of Fastrack Supreme.
Fastrack Supreme factory setting
is:
Data bits = 8
Parity = none
Stop bits = 1
Baud = 115 200 bps.
Flow control = hardware
Nothing or nonsignificant
characters
Is there another program
interfering with the
communication program (i.e.
Conflict on communication
port access)
Close the interfering program.
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6.2 Receiving "ERROR" Message
The Fastrack Supreme returns an "ERROR" message (in reply to an AT command) in
the following cases:
• AT command syntax is incorrect: check the command syntax (refer to "AT
Commands Interface Guide" [7]),
• AT command syntax is correct, but transmitted with wrong parameters:
• Enter the AT+CMEE=1 command in order to change the error report method to
the verbose method, which includes the error codes.
• Enter again the AT command which previously caused the reception of
"ERROR" message in order to get the Mobile Equipment error code.
When the verbose error report method is enabled, the response of the Fastrack
Supreme in case of error is as follows:
• Either +CME ERROR: ,
• Or +CMS ERROR: .
Refer to "AT Commands Interface Guide" [7] for error result code description and
further details on the AT +CMEE command.
Note: It is strongly recommended to always enable the verbose error report method to
get the Mobile Equipment error code (enter AT +CMEE=1 command).
6.3 Receiving "NO CARRIER" Message
If the Fastrack Supreme returns a "NO CARRIER" message upon an attempted call
(voice or data), then refer to the table below for possible causes and solutions.
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Table 13: Solutions for "NO CARRIER" message
If the Supreme
returns…
Then ask… Action…
Is the received signal strong
enough?
Refer to section 5.5 to verify
the strength of the received
signal.
Is the Fastrack Supreme registered
on the network?
Refer to section 5.9 to verify
the registration.
Is the antenna properly
connected?
Refer to section 8.2.7.3 for
antenna requirements.
"NO CARRIER"
Is the band selection correction? Refer to Section 7.2 for band
switch
"NO CARRIER"
(when trying to
issue a voice
communication)
Is the semicolon (;) entered
immediately after the phone
number in the AT command?
Ensure that the semicolon (;)
is entered immediately after
the phone number in the AT
command.
e.g. ATD######;
Is the SIM card configured for data
/ fax calls?
Configure the SIM card for
data / fax calls (Ask your
network provider if
necessary).
Is the selected bearer type
supported by the called party?
Ensure that the selected
bearer type is supported by
the called party.
"NO CARRIER"
(when trying to
issue a data
communication)
Is the selected bearer type
supported by the network?
Ensure that the selected
bearer type is supported by
the network.
If no success, try bearer
selection type by AT
command: AT+CBST=0,0,3
If the Fastrack Supreme returns a "NO CARRIER" message, you may have the
extended error code by using AT command AT+CEER. Refer to the table below for
interpretation of extended error code.
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Table 14: Interpretation of extended error code
Error Code Diagnostic Hint
1 Unallocated phone number
16 Normal call clearing
17 User busy
18 No user responding
19 User alerting, no answer
21 Call rejected
22 Number changed
31 Normal, unspecified
50 Requested facility not subscribed Check your subscription (data
subscription available?).
68 ACM equal or greater than
ACMmax
Credit of your pre-paid SIM card
expired.
252 Call barring on outgoing calls
253 Call barring on incoming calls
3, 6, 8, 29, 34,
38, 41, 42, 43,
44, 47, 49, 57,
58, 63, 65, 69,
70, 79, 254
Network causes
See "AT Commands Interface
Guide" [7] for further details or
call network provider.
Note: For all other codes, and/or details, see AT commands documentation [7].
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7 Functional Description
7.1 Architecture
Internal Quik
Q26 series
RS232
Interface
SMA
Audio
Interface
DC / DC
Power
Supply
BOOT
RESET
V+BATT
GROUND
Micro-FIT
4 pins
SUB HD 15
pins
VCC
Microphone Microphone
Speaker Speaker
VCC
VCC
SIM card
Holder
Operating
Status
FASTRACK Supreme Plug & Play
GPIO-21
GPIO-25
50 pin IES Interface
Figure 17: Functional architecture
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7.2 EU and US Bands
7.2.1 General Presentation
The Fastrack Supreme is a quad band Plug & Play. It supports either EU bands
(EGSM900/DCS1800) or US bands (GSM850/ PCS1900), depending on the band
setting within the Plug & Play. Users are free to switch between EU bands and US
bands by simple AT commands when the selected bands are supported.
7.2.2 AT COMMAND for Bands Switch
EU/US band is easily switched/checked by AT command AT+WMBS.
For detail, please refer to Section 5.7 and 5.8.
7.3 Power Supply
7.3.1 General Presentation
The Fastrack Supreme is supplied by an external DC voltage (V+BATTERY) from +5.5
V to +32 V at 2.2 A.
Main regulation is made with an internal DC/DC converter in order to supply all the
internal functions with a DC voltage.
Correct operation of the Fastrack Supreme in communication mode is not guaranteed
if input voltage (V+BATTERY) falls below 5.5 V.
Note: The minimum input voltage specified here is at the Fastrack Supreme input. Be
careful of the input voltage decrease caused by the power cable. See paragraph 8.2.1
for more information.
7.3.2 Protections
The Fastrack Supreme is protected by a 800 mA / 250 V fuse directly bonded on the
power supply cable.
The Fastrack Supreme is also protected against voltage over +32 V.
Filtering guarantees:
• EMI/RFI protection in input and output,
• Signal smoothing.
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7.4 RS232 Serial Link
7.4.1 General Presentation
The RS232 interface performs the voltage level adaptation (V24/CMOS ⇔ V24/V28)
between the internal Fastrack Supreme Plug & Play (DCE) and the external world
(DTE).
The RS232 interface is internally protected (by ESD protection) against electrostatic
surges on the RS232 lines.
Filtering guarantees:
• EMI/RFI protection in input and output,
• Signal smoothing.
Signals available on the RS232 serial link are:
• TX data (CT103/TX),
• RX data (CT104/RX),
• Request To Send (CT105/RTS),
• Clear To Send (CT106/CTS),
• Data Terminal Ready (CT108-2/DTR),
• Data Set Ready (CT107/DSR),
• Data Carrier Detect (CT109/DCD),
• Ring Indicator (CT125/RI).
FASTRACK
Supreme
(DCE)
DTE
CT103 / TX
CT108-2 / DTR
CT105 / RTS
CT104 / RX
CT106 / CTS
CT107 / DSR
CT109 / DCD
CT125 / RI
Figure 18: RS232 Serial Link signals
RS232 interface has been designed to allow flexibility in the use of the serial interface
signals. However, the use of TX, RX, CTS and RTS signals is mandatory, which is not
the case for DTR, DSR, DCD and RI signals which can be not used.
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7.4.2 Autobauding Mode
The autobauding mode allows the Fastrack Supreme to detect the baud rate used by
the DTE connected to the RS232 serial link.
Autobauding mode is controlled by AT commands. See "AT Commands Interface
Guide" [7] for details on this function.
7.4.3 Pin Description
Signal Sub HD connector
Pin number
I/O I/O type
RS232
STANDARD
Description
CTXD/CT103 2 I TX Transmit serial data
CRXD/CT104 6 O RX Receive serial data
CRTS/CT105 12 I RTS Request To Send
CCTS/CT106 11 O CTS Clear To Send
CDSR/CT107 7 O DSR Data Set Ready
CDTR/CT108-2 8 I DTR Data Terminal Ready
CDCD/CT109 1 O DCD Data Carrier Detect
CRI/CT125 13 O RI Ring Indicator
CT102/GND 9 GND Ground
7.4.4 Serial Port Auto shut down Feature
The UART1 can be shut down when there is no activity between the DTE and the
Fastrack Supreme Plug & Play. This can help for improving power consumption
performance.
Serial Port Auto shut down feature is easily controlled by AT command AT+WASR.
AT+WASR=1 for entering the serial port auto shut down mode
AT+WASR=0 for exiting the serial port auto shut down mode
Refer to "AT Commands Interface Guide" [7] for further information on AT commands.
CAUTION: GPIO24 is reserved for serial port auto shut down feature. It is prohibited
for customer use. Improper access to GPIO24 by customer may lead to unexpected
behavior on UART1 performance.
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7.5 General Purpose Input/Output (GPIO)
The Fastrack Supreme provides two General Purpose Input / Output lines available for
external use: GPIO21 and GPIO25.
These GPIOs may be controlled by AT commands:
• AT+WIOW for a write access to the GPIO value, when the GPIO is used as an
output,
• AT+WIOR for a read access to the GPIO value, when the GPIO is used as an
input.
Refer to "AT Commands Interface Guide" [7] for further information on AT commands.
After reset, both GPIOs are configured as inputs. The AT+WIOM command has to be
used to change this configuration (refer to "AT Commands Interface Guide" [7] for
further details).
Pin description
Signal
Power Supply
connector
(4-pin Micro-Fit)
I/O I/O
Voltage
Reset
state Description Mulitplex
with
GPIO21 3 I/O 2V8 Undefine
d
General Purpose
I/O
No mux
GPIO25 4 I/O 2V8 Z General Purpose
I/O
INT1
Notes:
• The power supply cable may need to be modified due to the GPIO signals
(GPIO21 & GPIO25) available on the 4-pin Micro-FIT connector of the Fastrack
Supreme.
• The previous generation M1306B have GPIO4 and GPIO5 being replaced by
GPIO21 and GPIO25 respectively, for which both are of LOW level at reset
state.
7.6 BOOT
This signal must not be connected. Its use is strictly reserved to Wavecom or
competent retailers.
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7.7 RESET
7.7.1 General Presentation
This signal is used to force a reset procedure by providing low level during at least
200 μs.
This signal must be considered as an emergency reset only. A reset procedure is
automatically driven by an internal hardware during the power-up sequence.
This signal may also be used to provide a reset to an external device. It then behaves
as an output. If no external reset is necessary, this input may be left open, if used
(emergency reset), it has to be driven either by an open collector or an open drain
output:
• RESET pin 14 = 0, for Fastrack Supreme Reset,
• RESET pin 14 = 1, for normal mode.
Pin description
Signal
Sub HD 15-Pin
connector
Pin number
I/O I/O type Voltage Description
RESET 14 I/O Open Drain 1V8 Fastrack
Supreme Reset
Additional comments on RESET:
The RESET process is activated either by the external RESET signal or by an internal
signal (coming from a RESET generator). This automatic reset is activated at Powerup.
The Fastrack Supreme remains in RESET mode as long as the RESET signal is held
low.
Caution: This signal should be used only for "emergency" reset.
A software reset is always preferred to a hardware reset.
Note: See "AT Commands Interface Guide" [7] for further information on software
reset.
7.7.2 Reset Sequence
To activate the "emergency" reset sequence, the RESET signal has to be set to low for
200 μs minimum.
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As soon as the reset is done, the AT interface answers "OK" to the application. For
this, the application must send AT↵.
If the application manages hardware flow control, the AT command may be sent
during the initialization phase. Another solution is to use the AT+WIND command to
get an unsolicited status from the Fastrack Supreme.
For further details, refer to AT commands "AT Commands Interface Guide" [7].
RESET mode
IBB+RF=20 to
40mA
~RESET
STATE OF THE
Wireless CPU®
Wireless
CPU®
READY
Rt = Min1:200μs
or Typ2 = 40ms
AT answers “OK”
Wireless
CPU® READY
SIM and network
dependent
Wireless CPU®
ON
IBB+RF<120mA
without loc update
Ct = Typ:34ms
Figure 19: Reset sequence diagram
7.8 Audio
Audio interface is a standard one for connecting a phone handset.
Echo cancellation and noise reduction features are also available to improve the audio
quality in case of hand-free application.
7.8.1 Microphone Inputs
The microphone inputs are differential ones in order to reject common mode noise
and TDMA noise.
They already include the convenient biasing for an electret microphone (0.5 mA and 2
Volts) and are ESD protected.
This electret microphone may be directly connected to these inputs allowing an easy
connection to a handset.
The microphone impedance must be around 2 kΩ.
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AC coupling is already embedded in the Wireless CPU®.
The gain of the microphone inputs is internally adjusted and may be tuned from 7 dB
to 35 dB using an AT +VGT command (refer to AT commands documentation [7]).
Pin description
Signal Sub D 15-pin
Pin #
I/O I/O type Description
CMIC2P 4 I Analog Microphone positive input
CMIC2N 5 I Analog Microphone negative input
7.8.2 Speaker Outputs
This connection is differential to reject common mode noise and TDMA noise.
Speaker outputs are connected to internal push-pull amplifiers and may be loaded
down between 32 to 150 Ohms and up to 1 nF (see details in table Speaker gain vs
Max output voltage, in "AT Commands Interface Guide" [7]). These outputs may be
directly connected to a speaker.
The output power may be adjusted by step of 2 dB. The gain of the speaker outputs
is internally adjusted and may be tuned using an AT +VGR command (refer to AT
commands documentation [7]).
Pin description
Signal Sub D 15-pin Pin # I/O I/O type Description
CSPK2P 10 O Analog Speaker positive output
CSPK2N 15 O Analog Speaker negative output
7.9 Real Time Clock (RTC)
The Fastrack Supreme has now implemented the Real Time Clock for saving date and
time when the Plug & Play is unplugged from the DC power supply through the DC
power cable.
Item Min Typical Max
Charging Time start from fully discharged to fully
charged
940 min
Guarantee 2475 min
RTC Time Period* Nonguarantee
5225 min
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Remark:
1. This RTC time period is measured when the RTC battery is fully charged
before the Fastrack Supreme is being unplugged from the DC power
source.
2. This RTC time period is for temperature from -20°C to +60°C. Once the
operating/storage temperature is beyond this range, this time period is not
guaranteed.
Caution: When the Fastrack Supreme is shipped out, the charging voltage of the RTC
battery is not guaranteed. Once the Fastrack Supreme is on power, the RTC battery
will start charging and the RTC feature can then be resumed.
7.10 FLASH LED
The Fastrack Supreme has a red LED indicator to show the status of the GSM
network. For detail description of the various status, please refer to Section 5.3.
However, during operation mode of Slow Standby, there will be no network
registration and so the red LED indicator will always be ON. It is possible for user to
deactivate the LED indication during Slow Standby mode, in order to reduce power
consumption.
The Flash LED can be deactivated by AT command at+whcnf=1,0
The Flash LED can be activated by AT command at+whcnf=1,1
However, the new setting will be taken into account only after a restart. For detail,
please refer to Document [7].
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8 Technical Characteristics
8.1 Mechanical Characteristics
Table 15: Mechanical characteristics
Dimensions 73 x 54.5 x 25.5 mm (excluding connectors)
Overall Dimension 88 x 54.5 x 25.5 mm
Weight ≈ 89 grams (Fastrack Supreme only)
≈ 126 grams (Fastrack Supreme + bridles + power supply
cable)
Volume 101.5 cm3
Housing Aluminum profiled
The next page gives the dimensioning diagram of the Fastrack Supreme including the
clearance areas to take into account for the Fastrack Supreme installation.
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Figure 20: Dimensioning diagram
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8.2 Electrical Characteristics
8.2.1 Power Supply
Table 16: Electrical characteristics
Operating Voltage
ranges
5.5 V to 32 V DC, nominal at 13.2V DC.
Maximum current 500 mA Average at 5.5V.
2.5 A Peak at 5.5 V.
Note:
The Fastrack Supreme is permanently powered once the power supply is connected.
The following table describes the consequences of over-voltage and under-voltage
with the Fastrack Supreme.
Warning:
All the input voltages specification described in this Section are at the Fastrack
Supreme input. While powering the Fastrack Supreme, take into account the input
drop caused by the power cable. With the delivered cable, this input drop is around
700 mV at 5.5 V and 220 mV at 32V.
Table 17: Effects of power supply defect
If the voltage then
falls below 5.5 V, the GSM communication is not guaranteed.
is over 32 V
(Transient peaks),
the Fastrack Supreme guarantees its own
protection.
Is over 32 V
(continuous overvoltage)
the protection of the Fastrack Supreme is done
by the fuse (the supply voltage is
disconnected).
The fuse is a 800 mA / 250 V FAST-ACTING 5*20mm. See Section 10 for
recommended references.
The following table provides information on power consumption of the Fastrack
Supreme, assuming an operating temperature of +25 °C and using a 3 V SIM card.
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8.2.2 Power Consumption
The following table provides information on power consumption of the Fastrack
Supreme, assuming an operating temperature of +25 °C and using a 3 V SIM card.
Table 18: Power consumption in connected modes (1*)
Power Consumption in
E-GSM 900/DCS 1800 MHz - GPRS class 10 (Serial Port ON)
GSM 850 E-GSM
900
DCS 1800 PCS 1900
@ 5.5V 2500 / 309 2338 / 328 2224 / 325 2210 / 334
I peak
GSM850 / E-GSM900:
During TX bursts @ PCL5 / PCL19
DCS1800 / PCS1900 :
During TX bursts @ PCL0 / PCL15 @ 13.2V 953 / 133 794 / 100 755 / 137 722 / 139
@ 5.5V 267 / 98 237 / 100 227 / 100 226 / 100
@ 13.2V 117 / 50 106 / 52 111 / 52 102 / 51
GSM
I avg
GSM850 / E-GSM900:
Average @ PCL5 / PCL19
DCS1800 / PCS1900 :
Average @ PCL0 / PCL15 @ 32V 52 / 23 47 / 23 45 / 23 45 / 23
@ 5.5V 2485 / 288 2314 / 307 2195 / 307 2211 / 311
I peak
GSM850 / E-GSM900:
During 1TX bursts @ PCL5(Gamma 3) /
PCL19(Gamma 17)
DCS1800 / PCS1900 :
During 1TX bursts @ PCL0(Gamma 2) /
PCL15(Gamma 18)
@ 13.2V 943 / 124 784 / 132 737 / 139 724 / 131
@ 5.5V 255 / 94 228 / 96 218 / 96 219 / 97
@ 13.2V 112 / 48 102 / 50 99 / 50 99 / 51
GPRS Class 2
I avg
GSM850 / E-GSM900 :
Average 1TX/1RX @PCL5(Gamma 3) /
PCL19(Gamma 17)
DCS1800 / PCS1900:
Average 1TX/1RX @PCL0(Gamma 2) /
PCL15(Gamma 18) @ 32V 49 / 22 45 / 23 44 / 23 44 / 23
@ 5.5V 2418 / 294 1269 / 315 2215 / 317 2240 / 320
I peak
GSM850 / E-GSM900:
During 2TX bursts @ PCL5(Gamma 3) /
PCL19(Gamma 17)
DCS1800 / PCS1900:
During 2TX bursts @ PCL0(Gamma 2) /
PCL15(Gamma 18)
@ 13.2V 950 / 125 790 / 135 750 / 142 733 / 131
@ 5.5V 459 / 126 396 / 129 375 / 129 377 / 130
@ 13.2V 191 / 62 170 / 65 163 / 65 163 / 64
GPRS Class 10
I avg
GSM850 / E-GSM900 :
Average 2TX/3RX @ PCL5 (Gamma 3) /
PCL19(Gamma 17)
DCS1800 / PCS1900:
Average 2TX/3RX @ PCL0 (Gamma 2) /
PCL15(Gamma 18) @ 32V 84 / 29 75 / 30 71 / 29 71 / 30
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Power Consumption in
E-GSM 900/DCS 1800 MHz - GPRS class 10 (Serial Port ON)
GSM 850 E-GSM
900
DCS 1800 PCS 1900
@ 5.5V 2493 / 361 2334 / 391 2211 / 387 2225 / 389
I peak
GSM850 / E-GSM900:
During 1TX bursts @ PCL8 (Gamma 6) /
PCL19(Gamma 17)
DCS1800 / PCS1900:
During 1TX bursts @ PCL2 (Gamma 5) /
PCL15(Gamma 18)
@ 13.2V 958 / 150 801 / 161 744 / 162 743 / 158
@ 5.5V 170 / 100 163 / 102 173 / 103 176 / 103
@ 13.2V 79 / 51 77 / 53 82 / 53 82 / 52
EGPRS Class 2
I avg
GSM850 / E-GSM900 :
Average 1TX/1RX @ PCL8 (Gamma 6) / PCL
19(Gamma 17)
DCS1800 / PCS1900:
Average 1TX/1RX @ PCL2 (Gamma 5) / PCL
15(Gamma 18) @ 32V 36 / 23 34 / 24 36 / 24 36 / 24
@ 5.5V 2492 / 367 2328 / 395 2206 / 390 2218 / 394
I peak
GSM850 / E-GSM900:
During 2TX bursts @ PCL8 (Gamma 6) / PCL
19(Gamma 17)
DCS1800 / PCS1900:
During 2TX bursts @ PCL2 (Gamma 5) / PCL
15(Gamma 18)
@ 13.2V 961 / 568 802 / 162 735 / 166 743 / 160
@ 5.5V 280 / 137 264 / 142 287 / 142 295 / 143
@ 13.2V 125 / 73 119 / 69 129 / 70 130 / 70
EGPRS Class 10
I avg
GSM 850 / E-GSM900 :
Average 2TX/3RX @ PCL8 (Gamma 6) / PCL
19(Gamma 17)
DCS1800 / PCS1900:
Average 2TX/3RX @ PCL2 (Gamma 5) / PCL
15(Gamma 18)
@ 32V 55 / 31 52 / 32 58 / 32 57 / 32
Table 19: Power consumption in non-connected modes(1*)
Non-connected mode Serial Port status Voltage Current (mA)
@ 5.5V 34.3
ON @ 13.2V 17.8
@ 32V 9.2
@ 5.5V 16.5
@ 13.2V 9.4
I avg in Fast Idle mode Page 9
(2*)
OFF
@ 32V 5.2
@ 5.5V 23.5
ON @ 13.2V 13.4
@ 32V 6.9
@ 5.5V 5.1
@ 13.2V 3.5
I avg in Slow Idle mode Page 9
(3*)
OFF
@ 32V 2.8
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Non-connected mode Serial Port status Voltage Current (mA)
@ 5.5V 51.4
ON @ 13.2V 25.9
@ 32V 13.2
@ 5.5V 33.9
@ 13.2V 18.0
I avg in Fast Standby mode
(4*)
OFF
@ 32V 9.3
@ 5.5V 24.2
ON @ 13.2V 13.8
@ 32V 7.0
@ 5.5V 6.6
@ 13.2V 3.9
I avg in Slow Standby mode
(with FLASH LED activated)
(4*)
OFF
@ 32V 3.0
@ 5.5V 22.8
ON @ 13.2V 13.0
@ 32V 6.7
@ 5.5V 4.1
@ 13.2V 3.1
I avg in Slow Standby mode
(with FLASH LED deactivated)
(4*)
OFF
@ 32V 2.7
(1*):The power consumption might vary by 5 % over the whole operating temperature range (-
20 °C to +55 °C).
(2*): In this Mode, the RF function is active and the Fastrack Supreme synchronized with the
network, but there is no communication.
(3*): In this Mode, the RF function is disabled, but regularly activated to keep the
synchronization with the network. This Mode works only when the DTE send AT command to
shut down the serial link by software approach (DTE turns DTR in inactive state).
(4*): In this Mode, the RF function is disabled, and there is no synchronization with the
network.
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8.2.3 Audio Interface
The audio interface is available through the Sub HD 15-pin connector.
Table 20: Audio parameters caracteristics
Audio parameters Min Typ Max Unit Comments
Microphone input current @2 V/2 kΩ 0.5 mA
Absolute microphone input voltage 100 mVpp AC voltage
Speaker output current 150 Ω //1 nF 16 mA
Absolute speaker impedance 32 50 Ω
Impedance of the speaker amplifier
output in differential mode
1 Ω +/-10 %
Table 21: Microphone inputs internal audio filter characteristics
Frequency Gain
0-150 Hz < -22 dB
150-180 Hz < -11 dB
180-200 Hz < -3 dB
200-3700 Hz 0 dB
>4000 Hz < -60 dB
Table 22: Recommended characteristics for the microphone:
Feature Value
Type Electret 2 V / 0.5 mA
Impedance Z = 2 kΩ
Sensitivity -40 dB to –50 dB
SNR > 50 dB
Frequency response compatible with the GSM specifications
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Table 23: Recommended characteristics for the speaker:
Feature Value
Type 10 mW, electro-magnetic
Impedance Z = 32 to 50 Ω
Sensitivity 110 dB SPL min. (0 dB = 20 μPa)
Frequency response compatible with the GSM specifications
8.2.4 General Purpose Input/Output
Both GPIO21 and GPIO25 may be interfaced with a component that comply with 3
Volts CMOS levels.
Table 24: Operating conditions
Parameter I/O type Min Typ Max Condition
VIL CMOS 0.84 V
VIH CMOS 1.96 V
VOL CMOS 0.4 V IOL = -4 mA
VOH CMOS 2.4 V IOH = 4 mA
IOH 4mA
IOL -4mA
Clamping diodes are present on I/O pads.
8.2.5 SIM Interface
Table 25: SIM card characteristics
SIM card 1.8V / 3 V
8.2.6 RESET Signal
Table 26: Electrical characteristics
Parameter Min Typ Max Unit
Input Impedance ( R )* 330K kΩ
Input Impedance ( C ) 10n nF
*Internal pull-up
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Table 27: Operating conditions
Parameter Minimum Typ Maximum Unit
~RESET time (Rt) 1 200 μs
~RESET time (Rt) 2 at power up
only
20 40 100 ms
Cancellation time (Ct) 34 ms
VH 0.57 V
VIL 0 0.57 V
VIH 1.33 V
* VH: Hysterisis Voltage
1 This reset time is the minimum to be carried out on the ~RESET signal when the power supply is
already stabilized.
2 This reset time is internally carried out by the Wireless CPU® power supply supervisor only when
the Wireless CPU® power supplies are powered ON.
8.2.7 RF Characteristics
8.2.7.1 Frequency Ranges
Table 28: Frequency ranges
Characteristic GSM 850 E-GSM 900 DCS 1800 PCS 1900
Frequency TX 824 to 849
MHz
880 to 915
MHz
1710 to 1785
MHz
1850 to 1910
MHz
Frequency RX 869 to 894
MHz
925 to 960
MHz
1805 to 1880
MHz
1930 to 1990
MHz
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8.2.7.2 RF Performances
RF performances are compliant with the ETSI recommendation GSM 05.05.
The RF performances for receiver and transmitter are given in the table below.
Table 29: Receiver and transmitter RF performances
Receiver
E-GSM900/GSM850 Reference Sensitivity -104 dBm Static & TUHigh
DCS1800/PCS1900 Reference Sensitivity -102 dBm Static & TUHigh
Selectivity @ 200 kHz > +9 dBc
Selectivity @ 400 kHz > +41 dBc
Linear dynamic range 63 dB
Co-channel rejection >= 9 dBc
Transmitter
Maximum output power (E-GSM
900/GSM850)
at ambient temperature
33 dBm +/- 2 dB
Maximum output power
(DCS1800/PCS1900)
at ambient temperature
30 dBm +/- 2 dB
Minimum output power (E-GSM
900/GSM850)
at ambient temperature
5 dBm +/- 5 dB
Minimum output power
(DCS1800/PCS1900)
at ambient temperature
0 dBm +/- 5 dB
8.2.7.3 External Antenna
The external antenna is connected to the Fastrack Supreme via the SMA connector.
The external antenna must fulfill the characteristics listed in the table below.
Table 30: External antenna characteristics
Antenna frequency range Quad-band GSM 850/GSM900/DCS1800/PCS1900 MHz
Impedance 50 Ohms nominal
DC impedance 0 Ohm
Gain (antenna + cable) 0 dBi
VSWR (antenna + cable) 2
Note: Refer to Section 10 for recommended antenna.
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8.3 Environmental Characteristics
The Fastrack Supreme Plug & Play is compliant with the following operating class.
To ensure the proper operation of the Fastrack Supreme, the temperature of the
environment must be within a specific range as described in the table below.
Table 31: Ranges of temperature
No IESM Current Drain
Conditions Temperature Range
Operating / Class A -20°C ~ +55°C
Operating / Class B Note1 -30°C ~ +75°C
Operating / Class C Note1 -30°C ~ +85°C
Storage Note1 -40°C ~ +85°C
Note1: Please refer to the Remark in Section 7.9 for RTC battery related issue.
Function Status Classification:
Class A:
The Fastrack Supreme remains fully functional, meeting GSM performance criteria in
accordance with ETSI requirements, across the specified temperature range.
Class B:
The Fastrack Supreme remains fully functional, across the specified temperature
range. Some GSM parameters may occasionally deviate from the ETSI/PTCRB
specified requirements and this deviation does not affect the ability of the Fastrack
Supreme to connect to the cellular network and function fully, as it does within the
Class A range.
Class C:
The functional requirements will not be fulfilled during external influence, but will
return to fully functional automatically, after the external influence has been removed.
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The detailed climatic and mechanics standard environmental constraints applicable to
the Fastrack Supreme are listed in the table below:
Table 32: Environmental standard constraints
Environmental Tests
(IEC TR 60721-4)
Environmental Classes
(IEC 60721-3)
Operation
Tests Standards
Storage
(IEC 60721-
3-1)
Class IE13
Transportation
(IEC 60721-3-2)
Class IE23
Stationary
(IEC 60721-3-
3)
Class IE35
Non-Stationary
(IEC 60721-3-7)
Class IE73
Cold IEC 60068-2-1 :
Ab/Ad
-25°C, 16 h -40°C, 16 h -5°C, 16 h -5°C, 16 h
Dry heat IEC 60068-2-2 :
Bb/Bd
+70°C, 16 h +70°C, 16 h +55°C, 16 h +55°C, 16 h
Change of
temperature
IEC 60068-2-14
: Na/Nb
-33°C to
ambient
2 cycles, t1=3
h
1 °C.min-1
-40°C to ambient
5 cycles, t1=3 h
t2<3 min
-5°C to ambient
2 cycles, t1=3 h
0,5 °C.min-1
-5°C to ambient
5 cycles, t1=3 h
t2<3 min
Damp heat IEC 60068-2-56
: Cb
+30°C, 93% RH
96 h
+40°C, 93% RH
96 h minimum
+30°C, 93% RH,
96 h
+30°C, 93% RH, 96 h
Damp heat,
cyclic
60068-2-30 : Db
Variant 1 or 2
+40°C, 90% to
100% RH
One cycle
Variant 2
+55°C, 90% to 100% RH
Two cycles
Variant 2
+30°C, 90% to
100% RH
Two cycles
Variant 2
+40°C, 90% to 100%
RH
Two cycles
Variant 1
Vibration
(sinusoidal)
IEC 60068-2-6 :
Fc
1-200 Hz
2 m.s-2
0,75 mm
3 axes
10 sweep
cycles
1-500 Hz
10 m.s-2
3,5 mm
3 axes
10 sweep cycles
1-150 Hz
2 m.s-2
0,75 mm
3 axes
5 sweep cycles
1-500 Hz
10 m.s-2
3,5 mm
3 axes
10 sweep cycles
Vibration
(random)
IEC 60068-2-64
: Fh
- 10-100 Hz / 1,0 m2.s-3
100-200 Hz / -3
dB.octave-1
200-2000 Hz / 0,5 m2.s-3
3 axes
30 min
-
-
Shock
(half-sine)
IEC 60068-2-27
: Ea
- - 50 m.s-2
6 ms
3 shocks
6 directions
150 m.s-2
11 ms
3 shocks
6 directions
Bump
IEC 60068-2-29
: Eb
- 250 m.s-2
6 ms
50 bumps
vertical direction
-
-
Free fall ISO 4180-2 - Two falls in each
specified attitude
- 2 falls in each
specified attitude
0,025 m (<1kg)
Drop and topple
IEC 60068-2-31
: Ec
-
One drop on relevant
corner
One topple about each
bottom edge
-
One drop on each
relevant corner
One topple on each of
4 bottom edges
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Notes:
Short description of Class IE13 (For more information see standard IEC 60721-3-1)
"Locations without controlled temperature and humidity, where heating may be used
to raise low temperatures, locations in buildings providing minimal protection against
daily variations of external climate, prone to receiving rainfall from carrying wind".
Short description of Class IE23 (For more information, see standard IEC 60721-3-2)
"Transportation in unventilated compartments and in conditions without protection
against bad weather, in all sorts of trucks and trailers in areas of well developed road
network, in trains equipped with buffers specially designed to reduce shocks and by
boat".
Short description of Class IE35 (For more information see standard IEC 60721-3-3)
"Locations with no control on heat or humidity where heating may be used to raise
low temperatures, to places inside a building to avoid extremely high temperatures,
to places such as hallways, building staircases, cellars, certain workshops,
equipment stations without surveillance".
Short description of Class IE73 (For more information see standard IEC 60721-3-7)
"Transfer to places where neither temperature nor humidity are controlled but where
heating may be used to raise low temperatures, to places exposed to water droplets,
products can be subjected to ice formation, these conditions are found in hallways
and building staircases, garages, certain workshops, factory building and places for
industrial processes and hardware stations without surveillance".
Warning: The specification in the above table applies to the Fastrack Supreme
product only. Customers are advised to verify that the environmental specification of
the SIM Card used is compliant with the Fastrack Supreme environmental
specifications. Any application must be qualified by the customer with the SIM Card
in storage, transportation and operation.
The use of standard SIM cards may drastically reduce the environmental conditions in
which the Product can be used. These cards are particularly sensible to humidity and
temperature changes. These conditions may produce oxidation of the SIM card
metallic layers and cause, in the long term, electrical discontinuities. This is
particularly true in left alone applications, where no frequent extraction/insertion of
the SIM card is performed.
In case of mobility when the application is moved through different environments
with temperature variations, some condensation may appear. These events have a
negative impact on the SIM and may favor oxidation.
If the use of standard SIM card, with exposition to the environmental conditions
described above, can not be avoided, special care must be taken in the integration of
the final application in order to minimize the impact of these conditions. The solutions
that may be proposed are:
• Lubrication of the SIM card to protect the SIM Contact from oxidation.
• Putting the Fastrack Supreme Plug & Play in a waterproof enclosure with
desiccant bags.
Fastrack Supreme User Guide
Technical Characteristics
© Restricted Page: 75 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Lubrication of the SIM card had been tested by Wavecom (using Tutela Fluid 43EM
from MOLYDUVAL) and gives very good results.
If waterproof enclosure with a desiccant solution is used, check with your desiccant
retailer the quantity that must be used according to the enclosure dimensions. Ensure
humidity has been removed before sealing the enclosure.
Any solution selected must be qualified by the customer on the final application.
To minimize oxidation problem on the SIM card, its manipulation must be done with
the greatest precautions. In particular, the metallic contacts of the card must never be
touched with bare fingers or any matter which may contain polluted materials liable
to produce oxidation (such as, e.g. substances including chlorine). In case a cleaning
of the Card is necessary, a dry cloth must be used (never use any chemical
substance).
8.4 Conformity
The complete product complies with the essential requirements of article 3 of R&TTE
1999/5/EC Directive and satisfied the following standards:
Domain Applicable standard
Safety standard EN 60950 (ed.1999)
Efficient use of the radio
frequency spectrum
EN 301 419-(v 4.1.1)
EN 301 511 (V 9.0.2)
EMC EN 301 489–1 (edition 2002)
EN 301 489-7 (edition 2002)
Global Certification Forum –
Certification Criteria
GCF-CC V3.26.0
PTCRB NAPRD.03 V3.11.0
FCC FCC Part 15
FCC Part 22, 24
IC RSS-132 Issue 2
RSS-133 Issue 3
8.5 Protections
8.5.1 Power Supply
The Fastrack Supreme is protected by a 800 mA / 250 V fuse directly bonded on the
power supply cable.
The model of fuse used is: FSD 800 mA / 250 V FAST-ACTING.
Fastrack Supreme User Guide
Technical Characteristics
© Restricted Page: 76 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
8.5.2 Overvoltage
The Fastrack Supreme is protected against voltage over +32 V.
When input voltages exceed +32 V, the supply voltage is disconnected in order to
protect the internal electronic components from an overvoltage.
8.5.3 Electrostatic Discharge
The Fastrack Supreme withstands ESD according to IEC 1000-4-2 requirements for all
accessible parts of the Fastrack Supreme except the RF part:
• 8 kV of air discharge,
• 4 kV of contact discharge.
8.5.4 Miscellaneous
Filtering guarantees:
• EMI/RFI protection in input and output,
• Signal smoothing.
Fastrack Supreme User Guide
Safety Recommendations
© Restricted Page: 77 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
9 Safety Recommendations
9.1 General Safety
It is important to follow any special regulations regarding the use of radio equipment
due in particular to the possibility of radio frequency (RF) interference. Please follow
the safety advice given below carefully.
Switch OFF your Wireless CPU®:
• When in an aircraft. The use of cellular telephones in an aircraft may endanger
the operation of the aircraft, disrupt the cellular network and is illegal. Failure to
observe this instruction may lead to suspension or denial of cellular telephone
services to the offender, or legal action or both,
• When at a refueling point,
• When in any area with a potentially explosive atmosphere which could cause
an explosion or fire,
• In hospitals and any other place where medical equipment may be in use.
Respect restrictions on the use of radio equipment in:
• Fuel depots,
• Chemical plants,
• Places where blasting operations are in progress,
• Any other area where signalization reminds that the use of cellular telephone is
forbidden or dangerous.
• Any other area where you would normally be advised to turn off your vehicle
engine.
There may be a hazard associated with the operation of your Fastrack Supreme Plug
& Play close to inadequately protected personal medical devices such as hearing aids
and pacemakers. Consult the manufacturers of the medical device to determine if it is
adequately protected.
Operation of your Fastrack Supreme Plug & Play close to other electronic equipment
may also cause interference if the equipment is inadequately protected. Observe any
warning signs and manufacturers’ recommendations.
The Fastrack Supreme Plug & Play is designed for and intended to be used in "fixed"
and "mobile" applications:
"Fixed" means that the device is physically secured at one location and is not able
to be easily moved to another location.
"Mobile" means that the device is designed to be used in other than fixed locations
and generally in such a way that a separation distance of at least 20 cm (8
inches) is normally maintained between the transmitter’s antenna and the body of
the user or nearby persons.
Fastrack Supreme User Guide
Safety Recommendations
© Restricted Page: 78 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
The Fastrack Supreme Plug & Play is not designed for and intended to be used in
portable applications (within 20 cm or 8 inches of the body of the user) and such
uses are strictly prohibited.
9.2 Vehicle Safety
Do not use your Fastrack Supreme Plug & Play while driving, unless equipped with a
correctly installed vehicle kit allowing ’Hands-Free’ Operation.
Respect national regulations on the use of cellular telephones in vehicles. Road safety
always comes first.
If incorrectly installed in a vehicle, the operation of Fastrack Supreme Plug & Play
telephone could interfere with the correct functioning of vehicle electronics. To avoid
such problems, make sure that the installation has been performed by a qualified
personnel. Verification of the protection of vehicle electronics should form part of the
installation.
The use of an alert device to operate a vehicle’s lights or horn on public roads is not
permitted.
9.3 Care and Maintenance
Your Fastrack Supreme Plug & Play is the product of advanced engineering, design
and craftsmanship and should be treated with care. The suggestion below will help
you to enjoy this product for many years.
Do not expose the Fastrack Supreme Plug & Play to any extreme environment where
the temperature or humidity is high.
Do not use or store the Fastrack Supreme Plug & Play in dusty or dirty areas. Its
moving parts (SIM holder for example) can be damaged.
Do not attempt to disassemble the Wireless CPU®. There are no user serviceable parts
inside.
Do not expose the Fastrack Supreme Plug & Play to water, rain or spilt beverages. It
is not waterproof.
Do not abuse your Fastrack Supreme Plug & Play by dropping, knocking, or violently
shaking it. Rough handling can damage it.
Do not place the Fastrack Supreme Plug & Play alongside computer discs, credit or
travel cards or other magnetic media. The information contained on discs or cards
may be affected by the Wireless CPU®.
The use of third party equipment or accessories, not made or authorized by Wavecom
may invalidate the warranty of the Wireless CPU®.
Do contact an authorized Service Center in the unlikely event of a fault in the Wireless
CPU®.
Fastrack Supreme User Guide
Safety Recommendations
© Restricted Page: 79 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
9.4 Your Responsibility
This Fastrack Supreme Plug & Play is under your responsibility. Please treat it with
care respecting all local regulations. It is not a toy. Therefore, keep it in a safe place at
all times and out of the reach of children.
Try to remember your Unlock and PIN codes. Become familiar with and use the
security features to block unauthorized use and theft.
Fastrack Supreme User Guide
Recommended Accessories
© Restricted Page: 80 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
10 Recommended Accessories
Accessories recommended by Wavecom for the Fastrack Supreme are given in the
table below.
Table 33: List of recommended accessories
Designation Part number Supplier
1140.26 ALLGON
Quad-band antenna MA112VX00 MAT Equipment
MCA1890 MH/PB/SMA m HIRSCHMANN
SMA/FME Antenna
adaptor
PROCOM
Power adaptor
(Europe)
EGSTDW P2 EF9W3 24W
Out:12 V - 2A
In: 100 to 240 V – 50/60 Hz – 550 mA
Mounted with micro-fit connector
EGSTDW (for power
adaptor)
MOLEX (for micro-fit
connector)*
Fuse F800L250V Shanghai Fullness
IESM GPS + USB FSUE01 WAVECOM
IESM IO + USB FSUE02 WAVECOM
IESM IO + USB +
GPS
FSUE03 WAVECOM
IESM Ethernet FSUE04 WAVECOM
* Information not available for this preliminary version.
Fastrack Supreme User Guide
Recommended Accessories
© Restricted Page: 81 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
Table 34: Fastrack Supreme Family
Designation Part number Supplier
Fastrack Supreme 10 FSU001 WAVECOM
Fastrack Supreme 20 FSU002 WAVECOM
IESM GPS + USB FSUE01 WAVECOM
IESM IO + USB FSUE02 WAVECOM
IESM IO + USB + GPS FSUE03 WAVECOM
IESM Ethernet FSUE04 WAVECOM
FSU 10 IESM GPS+USB FSUP01 WAVECOM
FSU 20 IESM GPS+USB FSUP02 WAVECOM
FSU 10 IESM IO+USB FSUP03 WAVECOM
FSU 20 IESM IO+USB FSUP04 WAVECOM
FSU 10 IESM IO+USB+GPS FSUP05 WAVECOM
FSU 20 IESM IO+USB+GPS FSUP06 WAVECOM
FSU 10 IESM Ethernet FSUP07 WAVECOM
FSU 20 IESM Ethernet FSUP08 WAVECOM
Fastrack Supreme User Guide
Online Support
© Restricted Page: 82 / 82
This document is the sole and exclusive property of Wavecom. Not to be distributed or divulged
without prior written agreement.
WA_DEV_Fastrk_UGD_001-003 November 5, 2007
11 Online Support
Wavecom provides an extensive range on online support which includes the
following areas of Wavecom’s wireless expertise:
• the latest version of this document
• new versions of our Operating System user guides
• comprehensive support for Open AT®
• regulatory certifications
• carrier certifications
• application notes
To gain access to this support, simply visit our web site at
http://www.wavecom.com/fastracksupreme or click on the desire link in Page.
Privileged access via user login is provided to Wavecom authorized distributors.
WAVECOM S.A. - 3 esplanade du Foncet - 92442 Issy-les-Moulineaux Cedex - France - Tel: +33(0)1 46 29 08 00 - Fax: +33(0)1 46 29 08 08
Wavecom, Inc. - 4810 Eastgate Mall - Second Floor - San Diego, CA 92121 - USA - Tel: +1 858 362 0101 - Fax: +1 858 558 5485
WAVECOM Asia Pacific Ltd. - Unit 201-207, 2nd Floor, Bio-Informatics Centre – No.2 Science Park West Avenue - Hong Kong Science Park, Shatin
- New Territories, Hong Kong
2014 Microchip Technology Inc. DS00001658B-page 1
Product Features
• High Performance 32-bit Embedded Controller
• Low power ~4mA in active mode
• System in deep sleep consumes 0.26mA
• 3.3-Volt I/O
• Package
- 6mm x 6mm body, 84-TFBGA
Sensor Firmware
• Sensor fusion firmware is licensed from Bosch or
Movea. Common features include:
- Self-contained 9-axis sensor fusion
- Sensor data pass-through
- Fast in-use background calibration of all sensors
and calibration monitor
- Magnetic immunity: Enhanced magnetic distortion,
detection and suppression
- Gyroscope drift cancellation
- Ambient Light Sensor Support
• Windows 8/8.1 certification (HID over I2C)
• Easy to implement complete turnkey sensor
fusion solution
• Sensor power management
• Sensor agnostic
• Refer to Bosch and Movea sensor fusion firmware
addendums for additional sensor fusion details
and supported sensors
Hardware Features
The hardware features in the SSC7102 device include
the following:
• Two SMB/I2C Controllers
- Supports I2C bus speeds to 400kHz
- Multi-master Capable
- Supports Clock Stretching
• Windows 8 HID over I2C Support
• LPC Interface
- HID over LPC Support
• Low Power Modes
Target Markets
• PCs: Ultrabooks and 2-in-1 Convertibles
• Mobile: Tablets, Smartphones
• Remote Controls, Gaming
• Fitness Monitoring
Description
The SSC7102 sensor fusion hub is a Windows 8.1 certified,
HID over I2C, low-power, flexible, turnkey solution.
SSC7102 makes implementing sensor fusion
easy for ultrabooks, tablets, and smartphones. Microchip
partnered with multiple industry-leading sensor
manufacturers and sensor-fusion specialists to create
this solution, enabling faster time to market without the
need for sensor-fusion expertise. The SSC7102 is
extremely efficient. It consumes ~4mA while running
complex sensor-fusion algorithms, resulting in longer
battery life for Windows 8.1 tablet, laptop, ultrabook,
and smart phone applications.
SSC7102
Sensor Hub Product Brief
SSC7102
DS00001658B-page 2 2014 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2014 Microchip Technology Inc. DS00001658B-page 3
SSC7102
PACKAGE OUTLINE
84-pin TFBGA Package Outline
Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging.
SSC7102
DS00001658B-page 4 2014 Microchip Technology Inc.
SYSTEM BLOCK DIAGRAM
2014 Microchip Technology Inc. DS00001658B-page 5
SSC7102
APPENDIX A: REVISION HISTORY
Revision Section/Figure/Entry Correction
REV B Features
Product Identification System
Wording of first bullet under Product Features modified
for clarity.
URL in Note 2 modified.
REV A Document release
SSC7102
DS00001658B-page 6 2014 Microchip Technology Inc.
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains
the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars
and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification”
and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://microchip.com/support
2014 Microchip Technology Inc. DS00001658B-page 7
SSC7102
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.(1) XXX(2) XXX
Package Sensor
Fusion
Device
Device: SSC7102(1)
Package: GQ = 84 pin TFBGA(2)
Sensor Fusion
Firmware:
AA0 = Bosch 9-axis Sensor Fusion
BA0 = Movea 9-axis Sensor Fusion
Tape and Reel
Option:
Blank = Tray packaging
TR = Tape and Reel(3)
Examples:
a) SSC7102-GQ-AA0 = 84-TFBGA, Bosch 9-axis
sensor fusion.
b) SSC7102-GQ-BA0 = 84-TFBGA, Movea 9-axis
sensor fusion.
Note 3: Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
[X](3)
Tape and Reel
Option
Firmware
- - -
Series
Note 2: All package options are RoHS compliant.
For RoHS compliance and environmental
information, please visit http://www.microchip.
com/pagehandler/en-us/aboutus/
Note 1: These products meet the halogen maximum
concentration values per IEC61249-2-21.
SSC7102
DS00001658B-page 8 2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of
Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly
or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32
logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM,
MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and ZScale
are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
A more complete list of registered trademarks and common law trademarks owned by Standard Microsystems Corporation (“SMSC”)
is available at: www.smsc.com. The absence of a trademark (name, logo, etc.) from the list does not constitute a waiver of any
intellectual property rights that SMSC has established in any of its trademarks.
All other trademarks mentioned herein are property of their respective companies.
© 2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 9781620778326
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2014 Microchip Technology Inc. DS00001658B-page 9
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Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
10/28/13
http://www.farnell.com/datasheets/1793972.pdf
www.epcos.com
EPCOS
Leaded Transient Voltage/RFI Suppressors (SHCVs)
2011
© EPCOS AG · A Member of TDK-EPC Corporation
4th Edition 08/2011 · Ordering No. B72482S9999X2 · Printed in Germany · SO 0811.5
Sample Kit 2011
Leaded Transient Voltage/
RFI Suppressors (SHCVs)
for Combined Overvoltage and RFI Suppression in Electric Motors,
SR6
K20M105X
SR6
K35M474X
SR1
K20M474X
SR1
K20M105X
SR1
K20M155X
SR1
K20M225X
SR2
S14BM475X
SR2
K20M474X
SR2
K20M105X
Product Range
Electrical parameters of leaded transient voltage / RFI suppressors in the sample kit
What are leaded transient voltage/
RFI suppressors (SHCVs)?
� Leaded transient voltage / RFI suppressors (also called SHCV varistors) are leaded devices in a
single component for combined overvoltage protection and RFI noise suppression on DC lines
of small electric motors in industrial and automotive applications
� SHVC varistors are a combination of high capacitance multilayer capacitor with X7R characteristic
for RF filtering and a multilayer varistor for transient protection
Construction of
leaded transient voltage /
RFI suppressors (SHCVs)
Benefits for customer applications
� Combined protection against overvoltage transients and RFI suppression in a bidirectional
single component
� Reliable protection against automotive transients such as load dump and jump start
� Maximum surge current capability (8/20 µs) up to 1200 A
� High capacitance of up to 4.7 µF
� Automotive series approval based on AEC-Q200 Rev-C
� No temperature derating up to 125 °C
Important information: Some parts of this publication contain statements about the suitability of our products for certain areas of application. These
statements are based on our knowledge of typical requirements that are often placed on our products. We expressly point out that these statements
cannot be regarded as binding statements about the suitability of our products for a particular customer application. It is incumbent on the customer
to check and decide whether a product is suitable for use in a particular application. This publication is only a brief product survey which may be
changed from time to time. Our products are described in detail in our data sheets. The Important notes (www.epcos.com /ImportantNotes) and the
product-specific Cautions and warnings must be observed. All relevant information is available through our sales offices.
Ordering code EPCOS type VDC. max l
surge, max WLD Vjump VV Vclamp, max l
clamp Cnom
@ 8/20 µs 10 pulses @ 5 min @ 1 mA @ 8/20 µs
[V] [A] [J] [V] [V] [V] [A] [nF]
Automotive series
B72527G3200K000 SR6K20M105X 26 200 1.5 – 33 ±10% 54 1 1000 ±20%
B72527E3350K000 SR6K35M474X 45 100 1.5 – 56 ±10% 90 1 470 ±20%
B72587E3200K000 SR1K20M474X 26 800 6 26 33±10% 58 10 470 ±20%
B72587G3200K000 SR1K20M105X 26 800 6 26 33 ±10% 58 5 1000 ±20%
B72587H3200K000 SR1K20M155X 26 800 6 26 33 ±10% 58 5 1500 ±20%
B72587J3200K000 SR1K20M225X 26 800 6 26 33 ±10% 58 5 2200 ±20%
B72547L3140S200 SR2S14BM475X 16 1200 12 24.5 22 +23/-0% 40 10 4700 ±20%
B72547E3200K000 SR2K20M474X 26 1200 12 26 33 ±10% 58 10 470 ±20%
B72547G3200K000 SR2K20M105X 26 1200 12 26 33 ±10% 58 10 1000 ±20%
Leaded Transient Voltage/
RFI Suppressors (SHCVs)
for Combined Overvoltage and
RFI Suppression in Electric Motors
www.epcos.com
© EPCOS AG 2011,
SR6
K20M105X
SR6
K35M474X
SR1
K20M474X
SR1
K20M105X
SR1
K20M155X
SR1
K20M225X
SR2
S14BM475X
SR2
K20M474X
SR2
K20M105X
Product Range
Electrical parameters of leaded transient voltage / RFI suppressors in the sample kit
What are leaded transient voltage/
RFI suppressors (SHCVs)?
� Leaded transient voltage / RFI suppressors (also called SHCV varistors) are leaded devices in a
single component for combined overvoltage protection and RFI noise suppression on DC lines
of small electric motors in industrial and automotive applications
� SHVC varistors are a combination of high capacitance multilayer capacitor with X7R characteristic
for RF filtering and a multilayer varistor for transient protection
Construction of
leaded transient voltage /
RFI suppressors (SHCVs)
Benefits for customer applications
� Combined protection against overvoltage transients and RFI suppression in a bidirectional
single component
� Reliable protection against automotive transients such as load dump and jump start
� Maximum surge current capability (8/20 µs) up to 1200 A
� High capacitance of up to 4.7 µF
� Automotive series approval based on AEC-Q200 Rev-C
� No temperature derating up to 125 °C
Important information: Some parts of this publication contain statements about the suitability of our products for certain areas of application. These
statements are based on our knowledge of typical requirements that are often placed on our products. We expressly point out that these statements
cannot be regarded as binding statements about the suitability of our products for a particular customer application. It is incumbent on the customer
to check and decide whether a product is suitable for use in a particular application. This publication is only a brief product survey which may be
changed from time to time. Our products are described in detail in our data sheets. The Important notes (www.epcos.com /ImportantNotes) and the
product-specific Cautions and warnings must be observed. All relevant information is available through our sales offices.
Ordering code EPCOS type VDC. max l
surge, max WLD Vjump VV Vclamp, max l
clamp Cnom
@ 8/20 µs 10 pulses @ 5 min @ 1 mA @ 8/20 µs
[V] [A] [J] [V] [V] [V] [A] [nF]
Automotive series
B72527G3200K000 SR6K20M105X 26 200 1.5 – 33 ±10% 54 1 1000 ±20%
B72527E3350K000 SR6K35M474X 45 100 1.5 – 56 ±10% 90 1 470 ±20%
B72587E3200K000 SR1K20M474X 26 800 6 26 33±10% 58 10 470 ±20%
B72587G3200K000 SR1K20M105X 26 800 6 26 33 ±10% 58 5 1000 ±20%
B72587H3200K000 SR1K20M155X 26 800 6 26 33 ±10% 58 5 1500 ±20%
B72587J3200K000 SR1K20M225X 26 800 6 26 33 ±10% 58 5 2200 ±20%
B72547L3140S200 SR2S14BM475X 16 1200 12 24.5 22 +23/-0% 40 10 4700 ±20%
B72547E3200K000 SR2K20M474X 26 1200 12 26 33 ±10% 58 10 470 ±20%
B72547G3200K000 SR2K20M105X 26 1200 12 26 33 ±10% 58 10 1000 ±20%www.epcos.com
EPCOS
Leaded Transient Voltage/RFI Suppressors (SHCVs)
2011
© EPCOS AG · A Member of TDK-EPC Corporation
4th Edition 08/2011 · Ordering No. B72482S9999X2 · Printed in Germany · SO 0811.5
Sample Kit 2011
Leaded Transient Voltage/
RFI Suppressors (SHCVs)
for Combined Overvoltage and RFI Suppression in Electric Motors
© 2009 Microchip Technology Inc. DS21210N-page 1
24AA024/24LC024/24AA025/24LC025
Device Selection Table
Features:
• Single Supply with Operation from 1.7V to 5.5V
for 24AA024/24AA025 Devices, 2.5V for
24LC024/24LC025 Devices
• Low-Power CMOS Technology:
- Read current 1 mA, typical
- Standby current 1 μA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Maximum
• Self-timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect on 24XX024 Devices
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN and MSOP
• 6-Lead SOT-23 Package, 24XX025 only
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA024/24LC024/
24AA025/24LC025 is a 2 Kbit Serial Electrically
Erasable PROM with a voltage range of 1.7V to 5.5V.
The device is organized as a single block of 256 x 8-bit
memory with a 2-wire serial interface. Low current
design permits operation with typical standby and
active currents of only 1 μA and 1 mA, respectively.
The device has a page write capability for up to 16
bytes of data. Functional address lines allow the
connection of up to eight 24AA024/24LC024/
24AA025/24LC025 devices on the same bus for up to
16K bits of contiguous EEPROM memory. The device
is available in the standard 8-pin PDIP, 8-pin SOIC
(3.90 mm), TSSOP, 2x3 DFN and TDFN and MSOP
packages. The 24AA025/24LC025 is also available in
the 6-lead SOT-23 package.
Package Types
Block Diagram
Part
Number
VCC
Range
Max
Clock
Temp.
Range
Write
Protect
24AA024 1.7V-5.5V 400 kHz(1) I Yes
24AA025 1.7V-5.5V 400 kHz(1) I No
24LC024 2.5V-5.5V 400 kHz I, E Yes
24LC025 2.5V-5.5V 400 kHz I, E No
Note 1: 100 kHz for VCC < 2.5V
Note: WP pin is not internally connected on the
24XX025.
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP/SOIC/TSSOP/MSOP
A0
A1
A2
VSS
WP
SCL
SDA
8 VCC
7
6
5
1
2
3
4
SOT-23
SCL VCC
SDA
VSS A0
A1
DFN/TDFN
1
2
3 4
5
6
I/O
Control
Logic
Memory
Control
Logic XDEC
HV Generator
EEPROM
Array
Write-Protect
Circuitry
YDEC
VCC
VSS
Sense Amp.
R/W Control
SDA SCL
A0 A1 A2 WP*
2K I2C™ Serial EEPROM
24AA024/24LC024/24AA025/24LC025
DS21210N-page 2 © 2009 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1: DC SPECIFICATIONS
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Symbol Characteristic Min. Typ. Max. Units Conditions
— A0, A1, A2, SCL, SDA
and WP pins
— — — — —
D1 VIH High-level input voltage 0.7 VCC — — V —
D2 VIL Low-level input voltage — — 0.3 VCC V 0.2 VCC for VCC < 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger inputs
0.05 VCC — — V (Note)
D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V
D5 ILI Input leakage current — — ±1 μA VIN = VSS or VCC
D6 ILO Output leakage current — — ±1 μA VOUT = VSS or VCC
D7 CIN,
COUT
Pin capacitance
(all inputs/outputs)
— — 10 pF VCC = 5.5V (Note)
TA = 25°C, FCLK = 1 MHz
D8 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz
D9 ICC read — 0.05 1 mA —
D10 ICCS Standby current ——
0.01
—
15
μA
μA
Industrial
Automotive
SDA = SCL = VCC
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
© 2009 Microchip Technology Inc. DS21210N-page 3
24AA024/24LC024/24AA025/24LC025
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1 FCLK Clock frequency —
—
100
400
kHz 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
2 THIGH Clock high time 4000
600
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
3 TLOW Clock low time 4700
1300
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
4 TR SDA and SCL rise time (Note 1) ——
1000
300
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
5 TF SDA and SCL fall time (Note 1) ——
1000
300
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
6 THD:STA Start condition hold time 4000
600
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
7 TSU:STA Start condition setup time 4700
600
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
8 THD:DAT Data input hold time 0 — ns (Note 2)
9 TSU:DAT Data input setup time 250
100
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
10 TSU:STO Stop condition setup time 4000
600
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
11 TSU:WP WP setup time 4000
600
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
12 THD:WP WP hold time 4700
600
——
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
13 TAA Output valid from clock (Note 2) ——
3500
900
ns 1.7V ≤ VCC < 1.8V
1.8V ≤ VCC ≤ 5.5V
14 TBUF Bus free time: Time the bus must
be free before a new transmission
can start
1300
4700
——ns 1.7V ≤
VCC <
1.8V
1.8V ≤ VCC ≤ 5.5V
16 TSP Input filter spike suppression
(SDA and SCL pins)
— 50 ns (Note 1 and Note 3)
17 TWC Write cycle time (byte or page) — 5 ms —
18 — Endurance 1M — cycles 25°C, VCC = 5.5V, Block mode
(Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
24AA024/24LC024/24AA025/24LC025
DS21210N-page 4 © 2009 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
In
SDA
Out
WP
5
7
6
16
3
2
8 9
13
D4 4
10
11 12
14
© 2009 Microchip Technology Inc. DS21210N-page 5
24AA024/24LC024/24AA025/24LC025
2.0 PIN DESCRIPTIONS
Pin Function Table
2.1 SDA Serial Data
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal; therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2 SCL Serial Clock
The SCL input is used to synchronize the data transfer
from and to the device.
2.3 A0, A1, A2
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true. For the SOT-23
package only, pin A2 is not connected.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices (four for the SOT-23 package) may be connected
to the same bus by using different Chip Select
bit combinations. These inputs must be connected to
either VCC or VSS.
2.4 WP (24XX024 Only)
WP is the hardware write-protect pin. It must be tied to
VCC or VSS. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
2.5 Noise Protection
The 24AA024/24LC024/24AA025/24LC025 employs a
VCC threshold detector circuit which disables the
internal erase/write logic if the VCC is below 1.5V at
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
3.0 FUNCTIONAL DESCRIPTION
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
Name PDIP SOIC TSSOP DFN/TDFN MSOP SOT-23 Description
A0 1 1 1 1 1 5 Address Pin AO
A1 2 2 2 2 2 4 Address Pin A1
A2 3 3 3 3 3 — Address Pin A2
VSS 4 4 4 4 4 2 Ground
SDA 5 5 5 5 5 3 Serial Address/Data I/O
SCL 6 6 6 6 6 1 Serial Clock
WP 7 7 7 7 7 — Write-Protect Input
VCC 8 8 8 8 8 6 +1.7 to 5.5V Power Supply
24AA024/24LC024/24AA025/24LC025
DS21210N-page 6 © 2009 Microchip Technology Inc.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.5 Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
FIGURE 4-2: ACKNOWLEDGE TIMING
Note: The 24AA024/24LC024/24AA025/24LC025
does not generate any Acknowledge bits if
an internal programming cycle is in progress.
SCL (A) (B) (C) (D) (C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL 1 2 3 4 5 6 7 8 9 1 2 3
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
SDA
Acknowledge
Bit
Data from transmitter Data from transmitter
© 2009 Microchip Technology Inc. DS21210N-page 7
24AA024/24LC024/24AA025/24LC025
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code. For
the 24AA024/24LC024/24AA025/24LC025, this is set
as ‘1010’ binary for read and write operations. The next
three bits of the control byte are the Chip Select bits
(A2, A1, A0). The Chip Select bits allow the use of up
to eight 24AA024/24LC024/24AA025/24LC025
devices on the same bus and are used to select which
device is accessed. The Chip Select bits in the control
byte must correspond to the logic levels on the corresponding
A2, A1 and A0 pins for the device to respond.
These bits are in effect the three Most Significant bits of
the word address.
For the SOT-23 package, the A2 address pin is not
available. During device addressing, the A2 Chip
Select bit should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. Following the Start condition, the 24AA024/
24LC024/24AA025/24LC025 monitors the SDA bus
checking the control byte being transmitted. Upon
receiving a ‘1010’ code and appropriate Chip Select
bits, the slave device outputs an Acknowledge signal
on the SDA line. Depending on the state of the R/W bit,
the 24AA024/24LC024/24AA025/24LC025 will select a
read or write operation.
FIGURE 5-1: CONTROL BYTE FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24AA024/24LC024/24AA025/
24LC025 devices on the same bus. In this case, software
can use A0 of the control byte as address bit A8,
A1 as address bit A9 and A2 as address bit A10. It is
not possible to sequentially read across device
boundaries.
For the SOT-23 package, up to four 24AA025/24LC025
devices can be added for up to 8K bits of address
space. In this case, software can use A0 of the control
byte as address bit A8, and A1 as address bit A9. It is
not possible to sequentially read across device boundaries.
S 1 0 1 0 A2 A1 A0 R/W ACK
Control Code
Chip Select
Bits
Slave Address
Start Bit Acknowledge Bit
Read/Write Bit
24AA024/24LC024/24AA025/24LC025
DS21210N-page 8 © 2009 Microchip Technology Inc.
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit (which is a logic-low) is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24AA024/
24LC024/24AA025/24LC025. After receiving another
Acknowledge signal from the 24AA024/24LC024/
24AA025/24LC025, the master device will transmit the
data word to be written into the addressed memory
location. The 24AA024/24LC024/24AA025/24LC025
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and, during
this time, the 24AA024/24LC024/24AA025/
24LC025 will not generate Acknowledge signals
(Figure 6-1). If an attempt is made to write to the
protected portion of the array when the hardware write
protection (24XX024 only) has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if write protection is enabled.
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA024/24LC024/
24AA025/24LC025 in the same way as in a byte write.
However, instead of generating a Stop condition, the
master transmits up to 15 additional data bytes to the
24AA024/24LC024/24AA025/24LC025, which are
temporarily stored in the on-chip page buffer and will be
written into the memory once the master has transmitted
a Stop condition. Upon receipt of each word, the
four lower-order Address Pointer bits are internally
incremented by one.
The higher-order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte-write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if write protection is enabled.
6.3 Write Protection
The WP pin (available on 24XX024 only) must be tied
to VCC or VSS. If tied to VCC, the entire array will be
write-protected. If the WP pin is tied to VSS, write
operations to all address locations are allowed.
The WP pin is not available on the SOT-23 package.
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
Note: Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
ST
A
RT
ST
OP
Control
Byte
Word
Address Data
A
CK
A
CK
A
CK
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
ST
A
RT
Control
Byte
Word
Address (n) Data (n) Data (n + 15)
ST
OP
A
CK
A
CK
A
CK
A
CK
A
CK
Data (n +1)
© 2009 Microchip Technology Inc. DS21210N-page 9
24AA024/24LC024/24AA025/24LC025
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally-timed write cycle, with ACK
polling being initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a Write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If no
ACK is returned, the Start bit and control byte must be
re-sent. If the cycle is complete, the device will return
the ACK and the master can then proceed with the next
Read or Write command. See Figure 7-1 for a flow
diagram of this operation.
FIGURE 7-1: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
24AA024/24LC024/24AA025/24LC025
DS21210N-page 10 © 2009 Microchip Technology Inc.
8.0 READ OPERATIONS
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24AA024/24LC024/24AA025/24LC025 contains
an address counter that maintains the address of the
last word accessed, internally incremented by one.
Therefore, if the previous read access was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with the R/W bit set to ‘1’, the 24AA024/
24LC024/24AA025/24LC025 issues an acknowledge
and transmits the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the 24AA024/24LC024/24AA025/
24LC025 discontinues transmission (Figure 8-1).
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AA024/24LC024/24AA025/24LC025
as part of a write operation. Once the word address is
sent, the master generates a Start condition following
the acknowledge. This terminates the write operation,
but not before the internal Address Pointer is set. The
master then issues the control byte again, but with the
R/W bit set to a ‘1’. The 24AA024/24LC024/24AA025/
24LC025 will then issue an acknowledge and transmits
the eight bit data word. The master will not acknowledge
the transfer but does generate a Stop condition
and the 24AA024/24LC024/24AA025/24LC025
discontinues transmission (Figure 8-2). After this
command, the internal address counter will point to the
address location following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24AA024/24LC024/
24AA025/24LC025 transmits the first data byte, the
master issues an acknowledge (as opposed to a Stop
condition in a random read). This directs the 24AA024/
24LC024/24AA025/24LC025 to transmit the next
sequentially-addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24AA024/24LC024/
24AA025/24LC025 contains an internal Address
Pointer that is incremented by one upon completion of
each operation. This Address Pointer allows the entire
memory contents to be serially read during one
operation. The internal Address Pointer will
automatically roll over from address 0FFh to address
000h.
FIGURE 8-1: CURRENT ADDRESS
READ
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S P
STOP
Control
Byte
START
Data
A
C
K
NOACK
© 2009 Microchip Technology Inc. DS21210N-page 11
24AA024/24LC024/24AA025/24LC025
FIGURE 8-2: RANDOM READ
FIGURE 8-3: SEQUENTIAL READ
S S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
ST
A
RT
STOP
Control
Byte
ACK
Word
Address (n)
Control
Byte
START
Data (n)
ACK
ACK
NO
ACK
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
Control
Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x)
N
OA
CK
A
CK
A
CK
A
CK
A
CK
STOP
P
24AA024/24LC024/24AA025/24LC025
DS21210N-page 12 © 2009 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (3.90 mm) Example:
8-Lead TSSOP Example:
24LC024
I/P 13F
0519
24LC024I
SN 0519
13F
8-Lead MSOP Example:
XXXX
TYWW
NNN
XXXXT
YWWNNN
4L24
I519
13F
4L24I
51913F
XXXXXXXT
XXXXYYWW
NNN
8-Lead 2x3 DFN Example:
e3
e3
XXX
YWW
NN
2P4
519
13
8-Lead 2x3 TDFN Example:
XXX
YWW
NN
AP4
519
13
© 2009 Microchip Technology Inc. DS21210N-page 13
24AA024/24LC024/24AA025/24LC025
Part Number
1st Line Marking Codes
TSSOP MSOP
DFN TDFN SOT-23
I-TEMP E-TEMP I-TEMP E-TEMP I-TEMP E-TEMP
24AA024 4A24 4A24T 2P1 — AP1 — — —
24LC024 4L24 4L24T 2P4 AP5 AP4 2P5 — —
24AA025 4A25 4A25T 2R1 — AR1 — HQNN HRNN
24LC025 4L25 4L25T 2R4 AR5 AR4 2R5 HMNN HPNN
Note: T = Temperature grade (I, E)
6-Lead SOT-23
XXNN HQEC
Example:
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
e3
e3
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
24AA024/24LC024/24AA025/24LC025
DS21210N-page 14 © 2009 Microchip Technology Inc.
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24AA024/24LC024/24AA025/24LC025
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DS21210N-page 16 © 2009 Microchip Technology Inc.
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© 2009 Microchip Technology Inc. DS21210N-page 17
24AA024/24LC024/24AA025/24LC025
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© 2009 Microchip Technology Inc. DS21210N-page 19
24AA024/24LC024/24AA025/24LC025
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24AA024/24LC024/24AA025/24LC025
DS21210N-page 20 © 2009 Microchip Technology Inc.
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24AA024/24LC024/24AA025/24LC025
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9 # 4!! < = ?
9 #>#& ) =
b
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24AA024/24LC024/24AA025/24LC025
DS21210N-page 24 © 2009 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
Revision G
Added part number 24AA025 to document.
Correction to Section 1.0, Ambient Temperature.
Revision H
Added DFN package.
Revision J (02/2007)
Revised Features section; Revised Pin Function Table;
Changed 1.8V to 1.7V, Table 1-1 and Table 1-2;
Replaced Package Drawings; Replaced On-line
Support page; Revised Product ID section.
Revision K (03/2007)
Replaced Package Drawings (Rev. AM).
Revision L (04/2008)
Replaced Package Drawings; Added TDFN package;
Revised Product ID section.
Revision M (10/2009)
Added E-temp; Revised Section 1.0; Table 1-2; Figure
1-1; 1st Line Marking Codes table in Section 9.1;
Product ID section.
Revision N (10/2009)
Added 6-lead SOT-23 Package. Revised Sections 5.0,
5.1 and 6.3.
© 2009 Microchip Technology Inc. DS21210N-page 25
24AA024/24LC024/24AA025/24LC025
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
24AA024/24LC024/24AA025/24LC025
DS21210N-page 26 © 2009 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
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Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
24AA024/24LC024/24AA025/24LC025 DS21210N
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2009 Microchip Technology Inc. DS21210N-page 27
24AA024/24LC024/24AA025/24LC025
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: 24AA024: 1.7V, 2 Kbit Addressable Serial EEPROM with
WP pin.
24AA024T:1.7V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel) with WP pin.
24LC024: 2.5V, 2 Kbit Addressable Serial EEPROM with
WP pin.
24LC024T:2.5V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel) with WP pin.
24AA025: 1.7V, 2 Kbit Addressable Serial EEPROM with
no WP pin.
24AA025T:1.7V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel) with no WP pin.
24LC025: 2.5V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel) with no WP pin.
24LC025T:2.5V, 2 Kbit Addressable Serial EEPROM
(Tape and Reel) with no WP pin.
Temperature Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: OT = Plastic Small Outline (SOT-23), (Tape and Reel
only), (24XX025 only), 6-lead
P = Plastic DIP, (300 mil Body), 8-lead
SN = Plastic SOIC, (3.90 mm Body)
ST = TSSOP, 8-lead
MS = MSOP, 8-lead
MC = 2x3 DFN, 8-lead
MNY(1) = Plastic Dual Flat (TDFN), No lead package,
2x3 mm body, 8-lead
PART NO. X /XX
Temperature Package
Range
Device
Examples:
a) 24AA024-I/P: Industrial Temperature,
1.7V, PDIP Package
b) 24AA024-I/SN: Industrial Temperature,
1.7V, SOIC Package
c) 24AA025T-I/ST: Industrial Temperature,
1.7V, TSSOP Package, Tape and Reel
d) 24LC024-I/P: Industrial Temperature,
2.5V, PDIP Package
e) 24LC024-E/MS: Automotive Temperature,
2.5V, MSOP Package, Tape and
Reel
f) 24LC025T-I/OT: Industrial Temperature,
2.5V, SOT-23 Package, Tape and Reel
Note 1: “Y” indicates a Nickel, Palladium, Gold (NiPdAu) finish.
24AA024/24LC024/24AA025/24LC025
DS21210N-page 28 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS21210N-page 29
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21210N-page 30 © 2009 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
03/26/09
DATA SHEET
Product data sheet
Supersedes data of 1999 Apr 15
2004 Jan 21
DISCRETE SEMICONDUCTORS
PMBT4403
PNP switching transistor
dbook, halfpage
M3D088
2004 Jan 21 2
NXP Semiconductors Product data sheet
PNP switching transistor PMBT4403
FEATURES
•High current (max. 600 mA)
•Low voltage (max. 40 V).
APPLICATIONS
•Industrial and consumer switching applications.
DESCRIPTION
PNP switching transistor in a SOT23 plastic package. NPN complement: PMBT4401.
MARKING
Note
1.* = p : Made in Hong Kong.
* = t : Made in Malaysia.
* = W : Made in China.
PINNING
TYPE NUMBER
MARKING CODE(1)
PMBT4403
*2T
PIN
DESCRIPTION
1
base
2
emitter
3
collector
Fig.1 Simplified outline (SOT23) and symbol.handbook, halfpage213MAM256Top view231
ORDERING INFORMATION
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Note
1.Transistor mounted on an FR4 printed-circuit board.
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PMBT4403
−
plastic surface mounted package; 3 leads
SOT23
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCBO
collector-base voltage
open emitter
−
−40
V
VCEO
collector-emitter voltage
open base
−
−40
V
VEBO
emitter-base voltage
open collector
−
−5
V
IC
collector current (DC)
−
−600
mA
ICM
peak collector current
−
−800
mA
IBM
peak base current
−
−200
mA
Ptot
total power dissipation
Tamb ≤ 25 °C; note 1
−
250
mW
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
150
°C
Tamb
operating ambient temperature
−65
+150
°C
2004 Jan 21 3
NXP Semiconductors Product data sheet
PNP switching transistor PMBT4403
THERMAL CHARACTERISTICS
Note
1.Transistor mounted on an FR4 printed-circuit board.
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
note 1
500
K/W
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
ICBO
collector-base cut-off current
IE = 0; VCB = −40 V
−
−50
nA
IEBO
emitter-base cut-off current
IC = 0; VEB = −5 V
−
−50
nA
hFE
DC current gain
VCE = −1 V; (see Fig.2)
IC = −0.1 mA
30
−
IC = −1 mA
60
−
IC = −10 mA
100
−
VCE = −2 V
IC = −150 mA
100
300
IC = −500 mA
20
−
VCEsat
collector-emitter saturation voltage
IC = −150 mA; IB = −15 mA
−
−400
mV
IC = −500 mA; IB = −50 mA
−
−750
mV
VBEsat
base-emitter saturation voltage
IC = −150 mA; IB = −15 mA
−
−950
mV
IC = −500 mA; IB = −50 mA
−
−1.3
V
Cc
collector capacitance
IE = Ie = 0; VCB = −10 V; f = 1 MHz
−
8.5
pF
Ce
emitter capacitance
IC = Ic = 0; VEB = −500 mV; f = 1 MHz
−
35
pF
fT
transition frequency
IC = −20 mA; VCE = −10 V; f = 100 MHz
200
−
MHz
Switching times (between 10% and 90% levels); (see Fig.3)
ton
turn-on time
ICon = −150 mA; IBon = −15 mA; IBoff = 15 mA
−
40
ns
td
delay time
−
15
ns
tr
rise time
−
30
ns
toff
turn-off time
−
350
ns
ts
storage time
−
300
ns
tf
fall time
−
50
ns
2004 Jan 21 4
NXP Semiconductors Product data sheet
PNP switching transistor PMBT4403
Fig.2 DC current gain; typical values.ndbook, full pagewidth0300100200MGD812−10−1−1−10−102−103hFEIC mAVCE = −1 V
Fig.3 Test circuit for switching times.handbook, full pagewidthRCR2R1DUTMGD624VoRB(probe)450 Ω(probe)450 ΩoscilloscopeoscilloscopeVBBViVCCVi = −9.5 V; T = 500 μs; tp = 10 μs; tr = tf ≤ 3 ns.R1 = 68 Ω; R2 = 325 Ω; RB = 325 Ω; RC = 160 Ω.VBB = 3.5 V; VCC = −29.5 V.Oscilloscope: input impedance Zi = 50 Ω.
2004 Jan 21 5
NXP Semiconductors Product data sheet
PNP switching transistor PMBT4403
PACKAGE OUTLINEUNITA1max.bpcDE e1HELpQwv REFERENCESOUTLINEVERSIONEUROPEANPROJECTIONISSUE DATE04-11-0406-03-16 IEC JEDEC JEITAmm0.10.480.380.150.093.02.81.41.20.95e1.92.52.10.550.450.10.2DIMENSIONS (mm are the original dimensions)0.450.15 SOT23TO-236ABbpDe1eAA1LpQdetail XHEEwMvMABAB012 mmscaleA1.10.9cX123Plastic surface-mounted package; 3 leadsSOT23
2004 Jan 21 6
NXP Semiconductors Product data sheet
PNP switching transistor PMBT4403
DATA SHEET STATUS
Notes
1.Please consult the most recently issued document before initiating or completing a design.
2.The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
DOCUMENTSTATUS(1)
PRODUCT STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
DISCLAIMERS
General ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.
Terms and conditions of sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.
No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
NXP Semiconductors
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2009
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands R75/04/pp7 Date of release: 2004 Jan 21 Document order number: 9397 750 12501
© 2009 Microchip Technology Inc. DS39632E
PIC18F2455/2550/4455/4550
Data Sheet
28/40/44-Pin, High-Performance,
Enhanced Flash, USB Microcontrollers
with nanoWatt Technology
DS39632E-page ii © 2009 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc. DS39632E-page 1
PIC18F2455/2550/4455/4550
Universal Serial Bus Features:
• USB V2.0 Compliant
• Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
• Supports Control, Interrupt, Isochronous and Bulk
Transfers
• Supports up to 32 Endpoints (16 bidirectional)
• 1 Kbyte Dual Access RAM for USB
• On-Chip USB Transceiver with On-Chip Voltage
Regulator
• Interface for Off-Chip USB Transceiver
• Streaming Parallel Port (SPP) for USB streaming
transfers (40/44-pin devices only)
Power-Managed Modes:
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
• Sleep: CPU off, Peripherals off
• Idle mode Currents Down to 5.8 μA Typical
• Sleep mode Currents Down to 0.1 μA Typical
• Timer1 Oscillator: 1.1 μA Typical, 32 kHz, 2V
• Watchdog Timer: 2.1 μA Typical
• Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
• Four Crystal modes, including High-Precision PLL
for USB
• Two External Clock modes, Up to 48 MHz
• Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz
to 8 MHz
- User-tunable to compensate for frequency drift
• Secondary Oscillator using Timer1 @ 32 kHz
• Dual Oscillator Options allow Microcontroller and
USB module to Run at Different Clock Speeds
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
• High-Current Sink/Source: 25 mA/25 mA
• Three External Interrupts
• Four Timer modules (Timer0 to Timer3)
• Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
• Enhanced USART module:
- LIN bus support
• Master Synchronous Serial Port (MSSP) module
Supporting 3-Wire SPI (all 4 modes) and I2C™
Master and Slave modes
• 10-Bit, Up to 13-Channel Analog-to-Digital Converter
(A/D) module with Programmable Acquisition Time
• Dual Analog Comparators with Input Multiplexing
Special Microcontroller Features:
• C Compiler Optimized Architecture with Optional
Extended Instruction Set
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: > 40 Years
• Self-Programmable under Software Control
• Priority Levels for Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
• Programmable Code Protection
• Single-Supply 5V In-Circuit Serial
Programming™ (ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Optional Dedicated ICD/ICSP Port (44-pin, TQFP
package only)
• Wide Operating Voltage Range (2.0V to 5.5V)
Device
Program Memory Data Memory
I/O 10-Bit
A/D (ch)
CCP/ECCP
(PWM) SPP
MSSP
EUSART
Comparators
Timers
Flash 8/16-Bit
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes) SPI Master
I2C™
PIC18F2455 24K 12288 2048 256 24 10 2/0 No Y Y 1 2 1/3
PIC18F2550 32K 16384 2048 256 24 10 2/0 No Y Y 1 2 1/3
PIC18F4455 24K 12288 2048 256 35 13 1/1 Yes Y Y 1 2 1/3
PIC18F4550 32K 16384 2048 256 35 13 1/1 Yes Y Y 1 2 1/3
28/40/44-Pin, High-Performance, Enhanced Flash,
USB Microcontrollers with nanoWatt Technology
PIC18F2455/2550/4455/4550
DS39632E-page 2 © 2009 Microchip Technology Inc.
Pin Diagrams
40-Pin PDIP
PIC18F2455
28-Pin PDIP, SOIC
PIC18F2550
10
11
2
345
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
12
34
56789
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4455
PIC18F4550
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
© 2009 Microchip Technology Inc. DS39632E-page 3
PIC18F2455/2550/4455/4550
Pin Diagrams (Continued)
PIC18F4455
44-Pin TQFP
44-Pin QFN
PIC18F4455
PIC18F4550
PIC18F4550
10
11
23
6
1
18
19
20
21
22
12
13
14
15
38
8 7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC/ICCK(2)/ICPGC(2)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC/ICDT(2)/ICPGD(2)
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
NC/ICRST(2)/ICVPP(2)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4
10
11
23
6
1
18
19
20
21
22
12
13
14
15
38
8 7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
NC
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
RD7/SPP7/P1D 5
4 VSS
VDD
VDD
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: Special ICPORT features available in select circumstances. See Section 25.9 “Special ICPORT Features (44-Pin TQFP
Package Only)” for more information.
PIC18F2455/2550/4455/4550
DS39632E-page 4 © 2009 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power-Managed Modes ............................................................................................................................................................. 35
4.0 Reset .......................................................................................................................................................................................... 45
5.0 Memory Organization ................................................................................................................................................................. 59
6.0 Flash Program Memory.............................................................................................................................................................. 81
7.0 Data EEPROM Memory ............................................................................................................................................................. 91
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 97
9.0 Interrupts .................................................................................................................................................................................... 99
10.0 I/O Ports ................................................................................................................................................................................... 113
11.0 Timer0 Module ......................................................................................................................................................................... 127
12.0 Timer1 Module ......................................................................................................................................................................... 131
13.0 Timer2 Module ......................................................................................................................................................................... 137
14.0 Timer3 Module ......................................................................................................................................................................... 139
15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 143
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 151
17.0 Universal Serial Bus (USB) ...................................................................................................................................................... 165
18.0 Streaming Parallel Port ............................................................................................................................................................ 191
19.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 197
20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 243
21.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 265
22.0 Comparator Module.................................................................................................................................................................. 275
23.0 Comparator Voltage Reference Module................................................................................................................................... 281
24.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 285
25.0 Special Features of the CPU.................................................................................................................................................... 291
26.0 Instruction Set Summary .......................................................................................................................................................... 313
27.0 Development Support............................................................................................................................................................... 363
28.0 Electrical Characteristics .......................................................................................................................................................... 367
29.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 407
30.0 Packaging Information.............................................................................................................................................................. 409
Appendix A: Revision History............................................................................................................................................................. 419
Appendix B: Device Differences......................................................................................................................................................... 419
Appendix C: Conversion Considerations ........................................................................................................................................... 420
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 420
Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 421
Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 421
Index .................................................................................................................................................................................................. 423
The Microchip Web Site ..................................................................................................................................................................... 433
Customer Change Notification Service .............................................................................................................................................. 433
Customer Support .............................................................................................................................................................................. 433
Reader Response .............................................................................................................................................................................. 434
PIC18F2455/2550/4455/4550 Product Identification System ............................................................................................................ 435
© 2009 Microchip Technology Inc. DS39632E-page 5
PIC18F2455/2550/4455/4550
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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PIC18F2455/2550/4455/4550
DS39632E-page 6 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 7
PIC18F2455/2550/4455/4550
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
This family of devices offers the advantages of all
PIC18 microcontrollers – namely, high computational
performance at an economical price – with the addition
of high-endurance, Enhanced Flash program
memory. In addition to these features, the
PIC18F2455/2550/4455/4550 family introduces design
enhancements that make these microcontrollers a logical
choice for many high-performance, power sensitive
applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2455/2550/4455/4550
family incorporate a range of features that can significantly
reduce power consumption during operation.
Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4%, of normal
operation requirements.
• On-the-Fly Mode Switching: The
power-managed modes are invoked by user code
during operation, allowing the user to incorporate
power-saving ideas into their application’s
software design.
• Low Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer are minimized. See Section 28.0
“Electrical Characteristics” for values.
1.1.2 UNIVERSAL SERIAL BUS (USB)
Devices in the PIC18F2455/2550/4455/4550 family
incorporate a fully featured Universal Serial Bus
communications module that is compliant with the USB
Specification Revision 2.0. The module supports both
low-speed and full-speed communication for all supported
data transfer types. It also incorporates its own
on-chip transceiver and 3.3V regulator and supports
the use of external transceivers and voltage regulators.
1.1.3 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2455/2550/4455/4550
family offer twelve different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:
• Four Crystal modes using crystals or ceramic
resonators.
• Four External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O).
• An internal oscillator block which provides an
8 MHz clock (±2% accuracy) and an INTRC
source (approximately 31 kHz, stable over
temperature and VDD), as well as a range of
6 user-selectable clock frequencies, between
125 kHz to 4 MHz, for a total of 8 clock
frequencies. This option frees an oscillator pin for
use as an additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the High-Speed Crystal and
External Oscillator modes, which allows a wide
range of clock speeds from 4 MHz to 48 MHz.
• Asynchronous dual clock operation, allowing the
USB module to run from a high-frequency
oscillator while the rest of the microcontroller is
clocked from an internal low-power oscillator.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a
reference signal provided by the internal
oscillator. If a clock failure occurs, the controller is
switched to the internal oscillator block, allowing
for continued low-speed operation or a safe
application shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F2455 • PIC18LF2455
• PIC18F2550 • PIC18LF2550
• PIC18F4455 • PIC18LF4455
• PIC18F4550 • PIC18LF4550
PIC18F2455/2550/4455/4550
DS39632E-page 8 © 2009 Microchip Technology Inc.
1.2 Other Special Features
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Self-Programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine,
located in the protected Boot Block at the top of
program memory, it becomes possible to create an
application that can update itself in the field.
• Extended Instruction Set: The
PIC18F2455/2550/4455/4550 family introduces
an optional extension to the PIC18 instruction set,
which adds 8 new instructions and an Indexed
Literal Offset Addressing mode. This extension,
enabled as a device configuration option, has
been specifically designed to optimize re-entrant
application code originally developed in high-level
languages such as C.
• Enhanced CCP Module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include auto-shutdown for
disabling PWM outputs on interrupt or other select
conditions, and auto-restart to reactivate outputs
once the condition has cleared.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. The TX/CK and RX/DT signals can
be inverted, eliminating the need for inverting
buffers. Other enhancements include Automatic
Baud Rate Detection and a 16-bit Baud Rate
Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the EUSART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-Bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated, without waiting for a sampling period and
thus, reducing code overhead.
• Dedicated ICD/ICSP Port: These devices
introduce the use of debugger and programming
pins that are not multiplexed with other microcontroller
features. Offered as an option in select
packages, this feature allows users to develop I/O
intensive applications while retaining the ability to
program and debug in the circuit.
1.3 Details on Individual Family
Members
Devices in the PIC18F2455/2550/4455/4550 family are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in six
ways:
1. Flash program memory (24 Kbytes for
PIC18FX455 devices, 32 Kbytes for
PIC18FX550 devices).
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectional ports and 1 input only
port on 28-pin devices, 5 bidirectional ports on
40/44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have two standard CCP
modules, 40/44-pin devices have one standard
CCP module and one ECCP module).
5. Streaming Parallel Port (present only on
40/44-pin devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2455/2550/4455/4550 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2550),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2550), function over an extended VDD range
of 2.0V to 5.5V.
© 2009 Microchip Technology Inc. DS39632E-page 9
PIC18F2455/2550/4455/4550
TABLE 1-1: DEVICE FEATURES
Features PIC18F2455 PIC18F2550 PIC18F4455 PIC18F4550
Operating Frequency DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz
Program Memory (Bytes) 24576 32768 24576 32768
Program Memory (Instructions) 12288 16384 12288 16384
Data Memory (Bytes) 2048 2048 2048 2048
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced Capture/
Compare/PWM Modules
0 0 1 1
Serial Communications MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Universal Serial Bus (USB)
Module
1 1 1 1
Streaming Parallel Port (SPP) No No Yes Yes
10-Bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Comparators 2 2 2 2
Resets (and Delays) POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST),
MCLR (optional),
WDT
Programmable Low-Voltage
Detect
Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions;
83 with Extended
Instruction Set
enabled
75 Instructions;
83 with Extended
Instruction Set
enabled
75 Instructions;
83 with Extended
Instruction Set
enabled
75 Instructions;
83 with Extended
Instruction Set
enabled
Packages 28-Pin PDIP
28-Pin SOIC
28-Pin PDIP
28-Pin SOIC
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
PIC18F2455/2550/4455/4550
DS39632E-page 10 © 2009 Microchip Technology Inc.
FIGURE 1-1: PIC18F2455/2550 (28-PIN) BLOCK DIAGRAM
Data Latch
Data Memory
(2 Kbytes)
Address Latch
Data Address<12>
12
BSR Access
4 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
8
8 8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: RB3 is the alternate pin for CCP2 multiplexing.
W
Instruction Bus <16>
STKPTR Bank
8
8
8
BITOP
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
Comparator MSSP EUSART 10-Bit
ADC
HLVD Timer0 Timer1 Timer2 Timer3
CCP2
BOR Data
EEPROM
USB
Instruction
Decode &
Control
State Machine
Control Signals
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
VSS
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
USB Voltage
VUSB Regulator
PORTB
PORTC
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
PORTA
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
OSC2/CLKO/RA6
CCP1
© 2009 Microchip Technology Inc. DS39632E-page 11
PIC18F2455/2550/4455/4550
FIGURE 1-2: PIC18F4455/4550 (40/44-PIN) BLOCK DIAGRAM
Instruction
Decode &
Control
Data Latch
Data Memory
(2 Kbytes)
Address Latch
Data Address<12>
12
BSR Access
4 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
8
BITOP
8 8
ALU<8>
Address Latch
Program Memory
(24/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/SPP0:RD4/SPP4
PCLATU
PCU
PORTE
MCLR/VPP/RE3(1)
RE2/AN7/OESPP
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: These pins are only available on 44-pin TQFP packages under certain conditions. Refer to Section 25.9 “Special ICPORT Features
(44-Pin TQFP Package Only)” for additional information.
4: RB3 is the alternate pin for CCP2 multiplexing.
Comparator MSSP EUSART 10-Bit
ADC
Timer0 Timer1 Timer2 Timer3
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State Machine
Control Signals
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(2)
OSC2(2)
VDD, VSS
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Reference
Band Gap
MCLR(1)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RB0/AN12/INT0/FLT0/SDI/SDA
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
OSC2/CLKO/RA6
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
USB
FSR0
FSR1
FSR2
inc/dec
Address
12
Decode
logic
USB Voltage
Regulator
VUSB
ICRST(3)
ICPGC(3)
ICPGD(3)
ICPORTS(3)
PIC18F2455/2550/4455/4550
DS39632E-page 12 © 2009 Microchip Technology Inc.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
PDIP,
SOIC
MCLR/VPP/RE3
MCLR
VPP
RE3
1
I
PI
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
9
II
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with pin
function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode.
In select modes, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc. DS39632E-page 13
PIC18F2455/2550/4455/4550
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4
I/O
IIO
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5
I/O
II
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV
6
I/O
IOI
ST
ST
—
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7
I/O
IIIO
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 — — — See the OSC2/CLKO/RA6 pin.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
PDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
PIC18F2455/2550/4455/4550
DS39632E-page 14 © 2009 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/FLT0/
SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
21
I/O
IIII
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
22
I/O
II
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
23
I/O
IIO
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
24
I/O
I
I/O
O
TTL
Analog
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0
RB4
AN11
KBI0
25
I/O
II
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
26
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
27
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
PDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
© 2009 Microchip Technology Inc. DS39632E-page 15
PIC18F2455/2550/4455/4550
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11
I/O
OI
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE
12
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
RC2/CCP1
RC2
CCP1
13
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
RC4/D-/VM
RC4
DVM
15
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
16
I
I/O
O
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
17
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
RE3 — — — See MCLR/VPP/RE3 pin.
VUSB 14 P — Internal USB 3.3V voltage regulator output, positive supply for
internal USB transceiver.
VSS 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18F2455/2550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Number Pin
Type
Buffer
Type Description
PDIP,
SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
PIC18F2455/2550/4455/4550
DS39632E-page 16 © 2009 Microchip Technology Inc.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
VPP
RE3
1 18 18
I
PI
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI
OSC1
CLKI
13 32 30
II
Analog
Analog
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc. DS39632E-page 17
PIC18F2455/2550/4455/4550
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2 19 19
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3 20 20
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREFCVREF
4 21 21
I/O
IIO
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5 22 22
I/O
II
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV
6 23 23
I/O
IOI
ST
ST
—
TTL
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7 24 24
I/O
IIIO
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 — — — — — See the OSC2/CLKO/RA6 pin.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632E-page 18 © 2009 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33 9 8
I/O
IIII
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I2C™ data I/O.
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
34 10 9
I/O
II
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35 11 10
I/O
IIO
TTL
Analog
ST
—
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
36 12 11
I/O
I
I/O
O
TTL
Analog
ST
—
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver VPO output.
RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP
37 14 14
I/O
IIO
TTL
Analog
TTL
—
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc. DS39632E-page 19
PIC18F2455/2550/4455/4550
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15 34 32
I/O
OI
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE
16 35 35
I/O
I
I/O
O
ST
CMOS
ST
—
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36
I/O
I/O
O
ST
ST
TTL
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 PWM output, channel A.
RC4/D-/VM
RC4
DVM
23 42 42
I
I/O
I
TTL
—
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
RC5/D+/VP
RC5
D+
VP
24 43 43
I
I/O
I
TTL
—
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
RC6/TX/CK
RC6
TX
CK
25 44 44
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
RC7/RX/DT/SDO
RC7
RX
DT
SDO
26 1 1
I/O
I
I/O
O
ST
ST
ST
—
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632E-page 20 © 2009 Microchip Technology Inc.
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). These pins have TTL input buffers
when the SPP module is enabled.
RD0/SPP0
RD0
SPP0
19 38 38
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD1/SPP1
RD1
SPP1
20 39 39
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD2/SPP2
RD2
SPP2
21 40 40
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD3/SPP3
RD3
SPP3
22 41 41
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD4/SPP4
RD4
SPP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
RD5/SPP5/P1B
RD5
SPP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel B.
RD6/SPP6/P1C
RD6
SPP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel C.
RD7/SPP7/P1D
RD7
SPP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Streaming Parallel Port data.
Enhanced CCP1 PWM output, channel D.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
© 2009 Microchip Technology Inc. DS39632E-page 21
PIC18F2455/2550/4455/4550
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
8 25 25
I/O
IO
ST
Analog
—
Digital I/O.
Analog input 5.
SPP clock 1 output.
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
9 26 26
I/O
IO
ST
Analog
—
Digital I/O.
Analog input 6.
SPP clock 2 output.
RE2/AN7/OESPP
RE2
AN7
OESPP
10 27 27
I/O
IO
ST
Analog
—
Digital I/O.
Analog input 7.
SPP output enable output.
RE3 — — — — — See MCLR/VPP/RE3 pin.
VSS 12, 31 6, 30,
31
6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29
7, 28 P — Positive supply for logic and I/O pins.
VUSB 18 37 37 P — Internal USB 3.3V voltage regulator output, positive
supply for the USB transceiver.
NC/ICCK/ICPGC(3)
ICCK
ICPGC
— — 12
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP™ port clock.
In-Circuit Debugger clock.
ICSP programming clock.
NC/ICDT/ICPGD(3)
ICDT
ICPGD
— — 13
I/O
I/O
ST
ST
No Connect or dedicated ICD/ICSP port clock.
In-Circuit Debugger data.
ICSP programming data.
NC/ICRST/ICVPP(3)
ICRST
ICVPP
— — 33
IP
——
No Connect or dedicated ICD/ICSP port Reset.
Master Clear (Reset) input.
Programming voltage input.
NC/ICPORTS(3)
ICPORTS
— — 34 P — No Connect or 28-pin device emulation.
Enable 28-pin device emulation when connected
to VSS.
NC — 13 — — — No Connect.
TABLE 1-3: PIC18F4455/4550 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.
2: Default assignment for CCP2 when CCP2MX Configuration bit is set.
3: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No
Connect unless ICPRT is set and the DEBUG Configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632E-page 22 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 23
PIC18F2455/2550/4455/4550
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Overview
Devices in the PIC18F2455/2550/4455/4550 family
incorporate a different oscillator and microcontroller
clock system than previous PIC18F devices. The addition
of the USB module, with its unique requirements
for a stable clock source, make it necessary to provide
a separate clock source that is compliant with both
USB low-speed and full-speed specifications.
To accommodate these requirements, PIC18F2455/
2550/4455/4550 devices include a new clock branch to
provide a 48 MHz clock for full-speed USB operation.
Since it is driven from the primary clock source, an
additional system of prescalers and postscalers has
been added to accommodate a wide range of oscillator
frequencies. An overview of the oscillator structure is
shown in Figure 2-1.
Other oscillator features used in PIC18 enhanced
microcontrollers, such as the internal oscillator block
and clock switching, remain the same. They are
discussed later in this chapter.
2.1.1 OSCILLATOR CONTROL
The operation of the oscillator in PIC18F2455/2550/
4455/4550 devices is controlled through two Configuration
registers and two control registers. Configuration
registers, CONFIG1L and CONFIG1H, select the
oscillator mode and USB prescaler/postscaler options.
As Configuration bits, these are set when the device is
programmed and left in that configuration until the
device is reprogrammed.
The OSCCON register (Register 2-2) selects the Active
Clock mode; it is primarily used in controlling clock
switching in power-managed modes. Its use is
discussed in Section 2.4.1 “Oscillator Control
Register”.
The OSCTUNE register (Register 2-1) is used to trim
the INTRC frequency source, as well as select the
low-frequency clock source that drives several special
features. Its use is described in Section 2.2.5.2
“OSCTUNE Register”.
2.2 Oscillator Types
PIC18F2455/2550/4455/4550 devices can be operated
in twelve distinct oscillator modes. In contrast with previous
PIC18 enhanced microcontrollers, four of these
modes involve the use of two oscillator types at once.
Users can program the FOSC3:FOSC0 Configuration
bits to select one of these modes:
1. XT Crystal/Resonator
2. HS High-Speed Crystal/Resonator
3. HSPLL High-Speed Crystal/Resonator
with PLL Enabled
4. EC External Clock with FOSC/4 Output
5. ECIO External Clock with I/O on RA6
6. ECPLL External Clock with PLL Enabled
and FOSC/4 Output on RA6
7. ECPIO External Clock with PLL Enabled,
I/O on RA6
8. INTHS Internal Oscillator used as
Microcontroller Clock Source, HS
Oscillator used as USB Clock Source
9. INTIO Internal Oscillator used as
Microcontroller Clock Source, EC
Oscillator used as USB Clock Source,
Digital I/O on RA6
10. INTCKO Internal Oscillator used as
Microcontroller Clock Source, EC
Oscillator used as USB Clock Source,
FOSC/4 Output on RA6
2.2.1 OSCILLATOR MODES AND
USB OPERATION
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
previous PIC® devices, all core and peripheral clocks
were driven by a single oscillator source; the usual
sources were primary, secondary or the internal oscillator.
With PIC18F2455/2550/4455/4550 devices, the primary
oscillator becomes part of the USB module and
cannot be associated to any other clock source. Thus,
the USB module must be clocked from the primary clock
source; however, the microcontroller core and other
peripherals can be separately clocked from the
secondary or internal oscillators as before.
Because of the timing requirements imposed by USB,
an internal clock of either 6 MHz or 48 MHz is required
while the USB module is enabled. Fortunately, the
microcontroller and other peripherals are not required
to run at this clock speed when using the primary
oscillator. There are numerous options to achieve the
USB module clock requirement and still provide flexibility
for clocking the rest of the device from the primary
oscillator source. These are detailed in Section 2.3
“Oscillator Settings for USB”.
PIC18F2455/2550/4455/4550
DS39632E-page 24 © 2009 Microchip Technology Inc.
FIGURE 2-1: PIC18F2455/2550/4455/4550 CLOCK DIAGRAM
PIC18F2455/2550/4455/4550
FOSC3:FOS C0
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
Primary Oscillator
XT, HS, EC, ECIO
T1OSC
CPU
Peripherals
IDLEN
INTOSC Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
31 kHz 000
INTRC
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
Clock
Control
Source OSCCON< 1:0>
8 MHz
31 kHz (INTRC)
0
1
OSCTUNE<7>
and Two-Speed Start-up
96 MHz
PLL
PLLDIV
CPUDIV
0
1
0
÷ 2 1
PLL Prescaler
MUX
111
110
101
100
011
010
001
000 ÷ 1
÷ 2
÷ 3
÷ 4
÷ 5
÷ 6
÷ 10
÷ 12
11
10
01
00
PLL Postscaler
÷ 2
÷ 3
÷ 4
÷ 6
USB
USBDIV
FOSC3:FOSC0
HSPLL, ECPLL,
11
10
01
00
Oscillator Postscaler
÷ 1
÷ 2
÷ 3
÷ 4
CPUDIV
1
0
Peripheral
FSEN
÷ 4
USB Clock Source
XTPLL, ECPIO
Primary
Clock
(4 MHz Input Only)
© 2009 Microchip Technology Inc. DS39632E-page 25
PIC18F2455/2550/4455/4550
2.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS, HSPLL, XT and XTPLL Oscillator modes, a
crystal or ceramic resonator is connected to the OSC1
and OSC2 pins to establish oscillation. Figure 2-2
shows the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
FIGURE 2-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, HS OR HSPLL
CONFIGURATION)
TABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Use of a series cut crystal may give a frequency
out of the crystal manufacturer’s
specifications.
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18FXXXX
RS(2)
Internal
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 4.0 MHz 33 pF 33 pF
HS 8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Resonators Used:
4.0 MHz
8.0 MHz
16.0 MHz
When using ceramic resonators with frequencies
above 3.5 MHz, HS mode is recommended over XT
mode. HS mode may be used at any VDD for which
the controller is rated. If HS is selected, the gain of the
oscillator may overdrive the resonator. Therefore, a
series resistor should be placed between the OSC2
pin and the resonator. As a good starting point, the
recommended value of RS is 330 Ω.
PIC18F2455/2550/4455/4550
DS39632E-page 26 © 2009 Microchip Technology Inc.
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
An internal postscaler allows users to select a clock
frequency other than that of the crystal or resonator.
Frequency division is determined by the CPUDIV
Configuration bits. Users may select a clock frequency
of the oscillator frequency, or 1/2, 1/3 or 1/4 of the
frequency.
An external clock may also be used when the microcontroller
is in HS Oscillator mode. In this case, the
OSC2/CLKO pin is left open (Figure 2-3).
FIGURE 2-3: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
2.2.3 EXTERNAL CLOCK INPUT
The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK
INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)
The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.
FIGURE 2-5: EXTERNAL CLOCK
INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)
The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.
Osc Type Crystal
Freq
Typical Capacitor Values
Tested:
C1 C2
XT 4 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Crystals Used:
4 MHz
8 MHz
20 MHz
Note 1: Higher capacitance increases the stability
of oscillator but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
OSC1
Open OSC2
Clock from
Ext. System PIC18FXXXX
(HS Mode)
OSC1/CLKI
FOSC/4 OSC2/CLKO
Clock from
Ext. System PIC18FXXXX
OSC1/CLKI
RA6 I/O (OSC2)
Clock from
Ext. System PIC18FXXXX
© 2009 Microchip Technology Inc. DS39632E-page 27
PIC18F2455/2550/4455/4550
2.2.4 PLL FREQUENCY MULTIPLIER
PIC18F2455/2550/4255/4550 devices include a Phase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.
There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.
FIGURE 2-6: PLL BLOCK DIAGRAM
(HS MODE)
2.2.5 INTERNAL OSCILLATOR BLOCK
The PIC18F2455/2550/4455/4550 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. If the USB peripheral is not used, the
internal oscillator may eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler which can provide a
range of clock frequencies from 31 kHz to 4 MHz. The
INTOSC output is enabled when a clock frequency
from 125 kHz to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 25.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 33).
2.2.5.1 Internal Oscillator Modes
When the internal oscillator is used as the microcontroller
clock source, one of the other oscillator
modes (External Clock or External Crystal/Resonator)
must be used as the USB clock source. The choice of
the USB clock source is determined by the particular
internal oscillator mode.
There are four distinct modes available:
1. INTHS mode: The USB clock is provided by the
oscillator in HS mode.
2. INTXT mode: The USB clock is provided by the
oscillator in XT mode.
3. INTCKO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin outputs FOSC/4.
4. INTIO mode: The USB clock is provided by an
external clock input on OSC1/CLKI; the OSC2/
CLKO pin functions as a digital I/O (RA6).
Of these four modes, only INTIO mode frees up an
additional pin (OSC2/CLKO/RA6) for port I/O use.
MUX
VCO
Loop
Filter
and
Prescaler
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS/EC/ECIO/XT Oscillator Enable
÷24
(from CONFIG1H Register)
Oscillator
PIC18F2455/2550/4455/4550
DS39632E-page 28 © 2009 Microchip Technology Inc.
2.2.5.2 OSCTUNE Register
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s application.
This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
The INTOSC clock will stabilize within 1 ms. Code execution
continues during this shift. There is no indication
that the shift has occurred.
The OSCTUNE register also contains the INTSRC bit.
The INTSRC bit allows users to select which internal
oscillator provides the clock source when the 31 kHz
frequency option is selected. This is covered in greater
detail in Section 2.4.1 “Oscillator Control Register”.
2.2.5.3 Internal Oscillator Output Frequency
and Drift
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
However, this frequency may drift as VDD or temperature
changes, which can affect the controller operation
in a variety of ways.
The low-frequency INTRC oscillator operates independently
of the INTOSC source. Any changes in INTOSC
across voltage and temperature are not necessarily
reflected by changes in INTRC and vice versa.
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6-5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
© 2009 Microchip Technology Inc. DS39632E-page 29
PIC18F2455/2550/4455/4550
2.2.5.4 Compensating for INTOSC Drift
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register. This has
no effect on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. When using the EUSART, for example, an
adjustment may be required when it begins to generate
framing errors or receives data with errors while in
Asynchronous mode. Framing errors indicate that the
device clock frequency is too high; to adjust for this,
decrement the value in OSCTUNE to reduce the clock
frequency. On the other hand, errors in data may suggest
that the clock speed is too low; to compensate,
increment OSCTUNE to increase the clock frequency.
It is also possible to verify device clock speed against
a reference clock. Two timers may be used: one timer
is clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator. Both timers are cleared but the timer
clocked by the reference generates interrupts. When
an interrupt occurs, the internally clocked timer is read
and both timers are cleared. If the internally clocked
timer value is greater than expected, then the internal
oscillator block is running too fast. To adjust for this,
decrement the OSCTUNE register.
Finally, a CCP module can use free-running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calculated
time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.
PIC18F2455/2550/4455/4550
DS39632E-page 30 © 2009 Microchip Technology Inc.
2.3 Oscillator Settings for USB
When these devices are used for USB connectivity,
they must have either a 6 MHz or 48 MHz clock for
USB operation, depending on whether Low-Speed or
Full-Speed mode is being used. This may require some
forethought in selecting an oscillator frequency and
programming the device.
The full range of possible oscillator configurations
compatible with USB operation is shown in Table 2-3.
2.3.1 LOW-SPEED OPERATION
The USB clock for Low-Speed mode is derived from the
primary oscillator chain and not directly from the PLL. It
is divided by 4 to produce the actual 6 MHz clock.
Because of this, the microcontroller can only use a
clock frequency of 24 MHz when the USB module is
active and the controller clock source is one of the
primary oscillator modes (XT, HS or EC, with or without
the PLL).
This restriction does not apply if the microcontroller
clock source is the secondary oscillator or internal
oscillator block.
2.3.2 RUNNING DIFFERENT USB AND
MICROCONTROLLER CLOCKS
The USB module, in either mode, can run asynchronously
with respect to the microcontroller core and
other peripherals. This means that applications can use
the primary oscillator for the USB clock while the microcontroller
runs from a separate clock source at a lower
speed. If it is necessary to run the entire application
from only one clock source, full-speed operation
provides a greater selection of microcontroller clock
frequencies.
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION
Input Oscillator
Frequency
PLL Division
(PLLDIV2:PLLDIV0)
Clock Mode
(FOSC3:FOSC0)
MCU Clock Division
(CPUDIV1:CPUDIV0)
Microcontroller
Clock Frequency
48 MHz N/A(1) EC, ECIO None (00) 48 MHz
÷2 (01) 24 MHz
÷3 (10) 16 MHz
÷4 (11) 12 MHz
48 MHz ÷12 (111) EC, ECIO None (00) 48 MHz
÷2 (01) 24 MHz
÷3 (10) 16 MHz
÷4 (11) 12 MHz
ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
40 MHz ÷10 (110) EC, ECIO None (00) 40 MHz
÷2 (01) 20 MHz
÷3 (10) 13.33 MHz
÷4 (11) 10 MHz
ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
24 MHz ÷6 (101) HS, EC, ECIO None (00) 24 MHz
÷2 (01) 12 MHz
÷3 (10) 8MHz
÷4 (11) 6MHz
HSPLL, ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Note 1: Only valid when the USBDIV Configuration bit is cleared.
© 2009 Microchip Technology Inc. DS39632E-page 31
PIC18F2455/2550/4455/4550
20 MHz ÷5 (100) HS, EC, ECIO None (00) 20 MHz
÷2 (01) 10 MHz
÷3 (10) 6.67 MHz
÷4 (11) 5MHz
HSPLL, ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
16 MHz ÷4 (011) HS, EC, ECIO None (00) 16 MHz
÷2 (01) 8MHz
÷3 (10) 5.33 MHz
÷4 (11) 4MHz
HSPLL, ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
12 MHz ÷3 (010) HS, EC, ECIO None (00) 12 MHz
÷2 (01) 6MHz
÷3 (10) 4MHz
÷4 (11) 3MHz
HSPLL, ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
8 MHz ÷2 (001) HS, EC, ECIO None (00) 8MHz
÷2 (01) 4MHz
÷3 (10) 2.67 MHz
÷4 (11) 2MHz
HSPLL, ECPLL, ECPIO ÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
4 MHz ÷1 (000) XT, HS, EC, ECIO None (00) 4MHz
÷2 (01) 2MHz
÷3 (10) 1.33 MHz
÷4 (11) 1MHz
HSPLL, ECPLL, XTPLL,
ECPIO
÷2 (00) 48 MHz
÷3 (01) 32 MHz
÷4 (10) 24 MHz
÷6 (11) 16 MHz
TABLE 2-3: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION (CONTINUED)
Input Oscillator
Frequency
PLL Division
(PLLDIV2:PLLDIV0)
Clock Mode
(FOSC3:FOSC0)
MCU Clock Division
(CPUDIV1:CPUDIV0)
Microcontroller
Clock Frequency
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz).
Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz,
USB clock of 6 MHz).
Note 1: Only valid when the USBDIV Configuration bit is cleared.
PIC18F2455/2550/4455/4550
DS39632E-page 32 © 2009 Microchip Technology Inc.
2.4 Clock Sources and Oscillator
Switching
Like previous PIC18 enhanced devices, the
PIC18F2455/2550/4455/4550 family includes a feature
that allows the device clock source to be switched from
the main oscillator to an alternate, low-frequency clock
source. These devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External Clock modes and
the internal oscillator block. The particular mode is
defined by the FOSC3:FOSC0 Configuration bits. The
details of these modes are covered earlier in this
chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F2455/2550/4455/4550 devices offer the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC). Most
often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI/
UOE pins. Like the XT and HS Oscillator mode circuits,
loading capacitors are also connected from each pin to
ground. The Timer1 oscillator is discussed in greater
detail in Section 12.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power-managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
2.4.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 Configuration
bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The Internal Oscillator Frequency Select bits,
IRCF2:IRCF0, select the frequency output of the internal
oscillator block to drive the device clock. The choices are
the INTRC source, the INTOSC source (8 MHz) or one
of the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the internal oscillator block is
supplying the device clock, changing the states of these
bits will have an immediate change on the internal oscillator’s
output. On device Resets, the default output
frequency of the internal oscillator block is set at 1 MHz.
When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The OSTS
bit indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The IOFS bit indicates
when the internal oscillator block has stabilized and is
providing the device clock in RC Clock modes. The
T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator
is providing the device clock in secondary clock
modes. In power-managed modes, only one of these
three bits will be set at any time. If none of these bits are
set, the INTRC is providing the clock or the internal
oscillator block has just started and is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register
(T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable prior to
switching to it as the clock source; otherwise,
a very long delay may occur while
the Timer1 oscillator starts.
© 2009 Microchip Technology Inc. DS39632E-page 33
PIC18F2455/2550/4455/4550
2.4.2 OSCILLATOR TRANSITIONS
PIC18F2455/2550/4455/4550 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz(3)
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x = Internal oscillator
01 = Timer1 oscillator
00 = Primary oscillator
Note 1: Depends on the state of the IESO Configuration bit.
2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3: Default output frequency of INTOSC on Reset.
PIC18F2455/2550/4455/4550
DS39632E-page 34 © 2009 Microchip Technology Inc.
2.5 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. Unless the USB
module is enabled, the OSC1 pin (and OSC2 pin if
used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features regardless of the
power-managed mode (see Section 25.2 “Watchdog
Timer (WDT)”, Section 25.3 “Two-Speed Start-up”
and Section 25.4 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz
may be used directly to clock the device or may be
divided down by the postscaler. The INTOSC output is
disabled if the clock is provided directly from the INTRC
output.
Regardless of the Run or Idle mode selected, the USB
clock source will continue to operate. If the device is
operating from a crystal or resonator-based oscillator,
that oscillator will continue to clock the USB module.
The core and all other modules will switch to the new
clock source.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Sleep mode should never be invoked while the USB
module is operating and connected. The only exception
is when the device has been issued a “Suspend”
command over the USB. Once the module has suspended
operation and shifted to a low-power state, the
microcontroller may be safely put into Sleep mode.
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
Real-Time Clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant current consumption are listed in
Section 28.2 “DC Characteristics: Power-Down and
Supply Current”.
2.6 Power-up Delays
Power-up delays are controlled by two timers so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal circumstances
and the primary clock is operating and stable.
For additional information on power-up delays, see
Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 28-12). It is enabled by clearing (= 0) the
PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval, TCSD (parameter 38,
Table 28-12), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC or internal
oscillator modes are used as the primary clock source.
TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
INTCKO Floating, pulled by external clock At logic low (clock/4 output)
INTIO Floating, pulled by external clock Configured as PORTA, bit 6
ECIO, ECPIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
XT and HS Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
© 2009 Microchip Technology Inc. DS39632E-page 35
PIC18F2455/2550/4455/4550
3.0 POWER-MANAGED MODES
PIC18F2455/2550/4455/4550 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power-managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power-managed modes include several
power-saving features offered on previous PIC®
devices. One is the clock switching feature, offered in
other PIC18 devices, allowing the controller to use the
Timer1 oscillator in place of the primary oscillator. Also
included is the Sleep mode, offered by all PIC devices,
where all device clocks are stopped.
3.1 Selecting Power-Managed Modes
Selecting a power-managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of a clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power-managed modes. They are:
• The primary clock, as defined by the
FOSC3:FOSC0 Configuration bits
• The secondary clock (the Timer1 oscillator)
• The internal oscillator block (for RC modes)
3.1.2 ENTERING POWER-MANAGED
MODES
Switching from one power-managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the power-managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power-managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator
select bits, or changing the IDLEN bit, prior to issuing a
SLEEP instruction. If the IDLEN bit is already
configured correctly, it may only be necessary to
perform a SLEEP instruction to switch to the desired
mode.
TABLE 3-1: POWER-MANAGED MODES
Mode
OSCCON<7,1:0> Module Clocking
Available Clock and Oscillator Source
IDLEN(1) SCS1:SCS0 CPU Peripherals
Sleep 0 N/A Off Off None – all clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – all oscillator modes.
This is the normal full-power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 oscillator
RC_RUN N/A 1x Clocked Clocked Internal oscillator block(2)
PRI_IDLE 1 00 Off Clocked Primary – all oscillator modes
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 oscillator
RC_IDLE 1 1x Off Clocked Internal oscillator block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
PIC18F2455/2550/4455/4550
DS39632E-page 36 © 2009 Microchip Technology Inc.
3.1.3 CLOCK TRANSITIONS AND
STATUS INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Three bits indicate the current clock source and its
status. They are:
• OSTS (OSCCON<3>)
• IOFS (OSCCON<2>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power-managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is providing
a stable, 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.
If the internal oscillator block is configured as the
primary clock source by the FOSC3:FOSC0 Configuration
bits, then both the OSTS and IOFS bits may
be set when in PRI_RUN or PRI_IDLE modes. This
indicates that the primary clock (INTOSC output) is
generating a stable 8 MHz output. Entering another
power-managed RC mode at the same frequency
would clear the OSTS bit.
3.1.4 MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power-managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power-managed mode specified by the new
setting.
Upon resuming normal operation after waking from
Sleep or Idle, the internal state machines require at
least one TCY delay before another SLEEP instruction
can be executed. If two back to back SLEEP instructions
will be executed, the process shown in
Example 3-1 should be used.
EXAMPLE 3-1: EXECUTING BACK TO BACK SLEEP INSTRUCTIONS
3.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full-power execution
mode of the microcontroller. This is also the default
mode upon a device Reset unless Two-Speed Start-up
is enabled (see Section 25.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the
primary clock source (see Section 2.4.1 “Oscillator
Control Register”).
3.2.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high-accuracy clock source.
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode, or
one of the Idle modes, depending on the
setting of the IDLEN bit.
SLEEP
NOP ;Wait at least 1 Tcy before executing another sleep instruction
SLEEP
© 2009 Microchip Technology Inc. DS39632E-page 37
PIC18F2455/2550/4455/4550
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary
oscillator is shut down, the T1RUN bit (T1CON<6>) is
set and the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, device clocks will be delayed until
the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC PC + 2
1 2 3 n-1 n
Clock Transition(1)
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
Q1 Q3 Q4
OSC1
Peripheral
Program PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
SCS1:SCS0 bits Changed
TPLL(1)
1 2 n-1 n
Clock(2)
OSTS bit Set
Transition
TOST(1)
PIC18F2455/2550/4455/4550
DS39632E-page 38 © 2009 Microchip Technology Inc.
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides the
best power conservation of all the Run modes while still
executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distinguishable
differences between the PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
TIOBST.
If the IRCF bits were previously at a non-zero value or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
Note: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
© 2009 Microchip Technology Inc. DS39632E-page 39
PIC18F2455/2550/4455/4550
FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC PC + 2
1 2 3 n-1 n
Clock Transition(1)
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
Q1 Q3 Q4
OSC1
Peripheral
Program PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
SCS1:SCS0 bits Changed
TPLL(1)
1 2 n-1 n
Clock(2)
OSTS bit Set
Transition
Multiplexer
TOST(1)
PIC18F2455/2550/4455/4550
DS39632E-page 40 © 2009 Microchip Technology Inc.
3.3 Sleep Mode
The power-managed Sleep mode in the
PIC18F2455/2550/4455/4550 devices is identical to
the legacy Sleep mode offered in all other PIC devices.
It is entered by clearing the IDLEN bit (the default state
on device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 25.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
3.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 28-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-out
will result in a WDT wake-up to the Run mode currently
specified by the SCS1:SCS0 bits.
FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4
OSC1
Peripheral
Sleep
Program
Q1 Q1
Counter
Clock
CPU
Clock
PC PC + 2
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 4 PC + 6
Q1 Q2 Q3 Q4
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit Set
PC + 2
© 2009 Microchip Technology Inc. DS39632E-page 41
PIC18F2455/2550/4455/4550
3.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction.
If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
3.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting
the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set IDLEN first, then
set SCS1:SCS0 to ‘01’ and execute SLEEP. When the
clock source is switched to the Timer1 oscillator, the
primary oscillator is shut down, the OSTS bit is cleared
and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing
code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
PIC18F2455/2550/4455/4550
DS39632E-page 42 © 2009 Microchip Technology Inc.
3.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals
continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 28-12). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was
executed and the INTOSC source was already stable,
the IOFS bit will remain set. If the IRCF bits and
INTSRC are all clear, the INTOSC output will not be
enabled, the IOFS bit will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins
executing code being clocked by the INTOSC multiplexer.
The IDLEN and SCS bits are not affected by the
wake-up. The INTRC source will continue to run if
either the WDT or the Fail-Safe Clock Monitor is
enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
3.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or Sleep mode to a
Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power-managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power-managed mode (see Section 3.2 “Run
Modes” and Section 3.3 “Sleep Mode”). If the device
is executing code (all Run modes), the time-out will
result in a WDT Reset (see Section 25.2 “Watchdog
Timer (WDT)”).
The WDT timer and postscaler are cleared by executing
a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.
3.5.3 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the IOFS bit is set instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 25.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 25.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the
internal oscillator block. Execution is clocked by the
internal oscillator block until either the primary clock
becomes ready or a power-managed mode is entered
before the primary clock becomes ready; the primary
clock is then shut down.
© 2009 Microchip Technology Inc. DS39632E-page 43
PIC18F2455/2550/4455/4550
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is not any of the XT or
HS modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source
Exit Delay Clock Ready Status
Before Wake-up After Wake-up Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
XT, HS
None
XTPLL, HSPLL OSTS
EC
INTOSC(3) IOFS
T1OSC or INTRC(1)
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc OSTS
(4)
EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
INTOSC(3)
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc OSTS
(4)
EC TCSD(2)
INTOSC(3) None IOFS
None
(Sleep mode)
XT, HS TOST(4)
XTPLL, HSPLL TOST + trc OSTS
(4)
EC TCSD(2)
INTOSC(3) TIOBST(5) IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38, Table 28-12) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer period (parameter 32, Table 28-12). trc is the PLL lock time-out
(parameter F12, Table 28-9); it is also designated as TPLL.
5: Execution continues during TIOBST (parameter 39, Table 28-12), the INTOSC stabilization period.
PIC18F2455/2550/4455/4550
DS39632E-page 44 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 45
PIC18F2455/2550/4455/4550
4.0 RESET
The PIC18F2455/2550/4455/4550 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 25.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R Q
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC(1)
POR Pulse
OST
10-Bit Ripple Counter
PWRT
Chip_Reset
11-Bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the low-frequency INTRC source from the internal oscillator block.
2: See Table 4-2 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
32 μs 65.5 ms
MCLRE
PIC18F2455/2550/4455/4550
DS39632E-page 46 © 2009 Microchip Technology Inc.
REGISTER 4-1: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after a
Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-Down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the notes following this
register and Section 4.6 “Reset State of Registers” for additional information.
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent
Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to
‘1’ by software immediately after POR).
© 2009 Microchip Technology Inc. DS39632E-page 47
PIC18F2455/2550/4455/4550
4.2 Master Clear Reset (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F2455/2550/4455/4550 devices, the MCLR
input can be disabled with the MCLRE Configuration
bit. When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
4.3 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR pin
through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004, Section 28.1 “DC
Characteristics”). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to Electrostatic
Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
D R
VDD
MCLR
PIC18FXXXX
VDD
PIC18F2455/2550/4455/4550
DS39632E-page 48 © 2009 Microchip Technology Inc.
4.4 Brown-out Reset (BOR)
PIC18F2455/2550/4455/4550 devices implement a
BOR circuit that provides the user with a number of
configuration and power-saving options. The BOR
is controlled by the BORV1:BORV0 and
BOREN1:BOREN0 Configuration bits. There are a total
of four BOR configurations which are summarized in
Table 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any values of BOREN1:BOREN0
except ‘00’), any drop of VDD below VBOR (parameter
D005, Section 28.1 “DC Characteristics”) for
greater than TBOR (parameter 35, Table 28-12) will
reset the device. A Reset may or may not occur if VDD
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33, Table 28-12). If VDD drops below VBOR
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once VDD rises above VBOR, the
Power-up Timer will execute the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
4.4.1 SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise, it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by eliminating
the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
4.4.2 DETECTING BOR
When BOR is enabled, the BOR bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any POR event. IF BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a BOR event
has occurred.
4.4.3 DISABLING BOR IN SLEEP MODE
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1: BOR CONFIGURATIONS
Note: Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV1:BORV0 Configuration bits. It
cannot be changed in software.
BOR Configuration Status of
SBOREN
(RCON<6>)
BOR Operation
BOREN1 BOREN0
0 0 Unavailable BOR disabled; must be enabled by reprogramming the Configuration bits.
0 1 Available BOR enabled in software; operation controlled by SBOREN.
1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during Sleep
mode.
1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
© 2009 Microchip Technology Inc. DS39632E-page 49
PIC18F2455/2550/4455/4550
4.5 Device Reset Timers
PIC18F2455/2550/4455/4550 devices incorporate
three separate on-chip timers that help regulate the
Power-on Reset process. Their main function is to
ensure that the device clock is stable before code is
executed. These timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of the PIC18F2455/2550/
4455/4550 devices is an 11-bit counter which uses the
INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs = 65.6ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 (Table 28-12)
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.5.2 OSCILLATOR START-UP
TIMER (OST)
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 28-12). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, HS and
HSPLL modes and only on Power-on Reset or on exit
from most power-managed modes.
4.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly different
from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR condition has cleared, PWRT
time-out is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator configuration
and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devices operating in XT mode. For devices in RC
mode and with the PWRT disabled, on the other hand,
there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
PWRTEN = 0 PWRTEN = 1 Power-Managed Mode
HS, XT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
HSPLL, XTPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
EC, ECIO 66 ms(1) — —
ECPLL, ECPIO 66 ms(1) + 2 ms(2) 2 ms(2) 2 ms(2)
INTIO, INTCKO 66 ms(1) — —
INTHS, INTXT 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
PIC18F2455/2550/4455/4550
DS39632E-page 50 © 2009 Microchip Technology Inc.
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
© 2009 Microchip Technology Inc. DS39632E-page 51
PIC18F2455/2550/4455/4550
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V 1V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the Power-up Timer.
PIC18F2455/2550/4455/4550
DS39632E-page 52 © 2009 Microchip Technology Inc.
4.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation.
Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition Program
Counter
RCON Register STKPTR Register
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 0 0 0 0
RESET instruction 0000h 0 u u u u u u
Brown-out Reset 0000h 1 1 1 u 0 u u
MCLR Reset during power-managed Run
modes
0000h u 1 u u u u u
MCLR Reset during power-managed Idle
modes and Sleep mode
0000h u 1 0 u u u u
WDT time-out during full power or
power-managed Run modes
0000h u 0 u u u u u
MCLR Reset during full-power execution 0000h u u u u u u u
Stack Full Reset (STVREN = 1) 0000h u u u u u 1 u
Stack Underflow Reset (STVREN = 1) 0000h u u u u u u 1
Stack Underflow Error (not an actual Reset,
STVREN = 0)
0000h u u u u u u 1
WDT time-out during power-managed Idle or
Sleep modes
PC + 2 u 0 0 u u u u
Interrupt exit from power-managed modes PC + 2(1) u u 0 u u u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
© 2009 Microchip Technology Inc. DS39632E-page 53
PIC18F2455/2550/4455/4550
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---0 uuuu(1)
TOSH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1)
TOSL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(1)
STKPTR 2455 2550 4455 4550 00-0 0000 uu-0 0000 uu-u uuuu(1)
PCLATU 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PCL 2455 2550 4455 4550 0000 0000 0000 0000 PC + 2(3)
TBLPTRU 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TABLAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PRODH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2455 2550 4455 4550 0000 000x 0000 000u uuuu uuuu(2)
INTCON2 2455 2550 4455 4550 1111 -1-1 1111 -1-1 uuuu -u-u(2)
INTCON3 2455 2550 4455 4550 11-0 0-00 11-0 0-00 uu-u u-uu(2)
INDF0 2455 2550 4455 4550 N/A N/A N/A
POSTINC0 2455 2550 4455 4550 N/A N/A N/A
POSTDEC0 2455 2550 4455 4550 N/A N/A N/A
PREINC0 2455 2550 4455 4550 N/A N/A N/A
PLUSW0 2455 2550 4455 4550 N/A N/A N/A
FSR0H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2455 2550 4455 4550 N/A N/A N/A
POSTINC1 2455 2550 4455 4550 N/A N/A N/A
POSTDEC1 2455 2550 4455 4550 N/A N/A N/A
PREINC1 2455 2550 4455 4550 N/A N/A N/A
PLUSW1 2455 2550 4455 4550 N/A N/A N/A
FSR1H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F2455/2550/4455/4550
DS39632E-page 54 © 2009 Microchip Technology Inc.
INDF2 2455 2550 4455 4550 N/A N/A N/A
POSTINC2 2455 2550 4455 4550 N/A N/A N/A
POSTDEC2 2455 2550 4455 4550 N/A N/A N/A
PREINC2 2455 2550 4455 4550 N/A N/A N/A
PLUSW2 2455 2550 4455 4550 N/A N/A N/A
FSR2H 2455 2550 4455 4550 ---- 0000 ---- 0000 ---- uuuu
FSR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 2455 2550 4455 4550 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TMR0L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
OSCCON 2455 2550 4455 4550 0100 q000 0100 00q0 uuuu uuqu
HLVDCON 2455 2550 4455 4550 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 2455 2550 4455 4550 ---- ---0 ---- ---0 ---- ---u
RCON(4) 2455 2550 4455 4550 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2455 2550 4455 4550 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
PR2 2455 2550 4455 4550 1111 1111 1111 1111 1111 1111
T2CON 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
SSPBUF 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPCON1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SSPCON2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
ADRESH 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
ADCON1 2455 2550 4455 4550 --00 0qqq --00 0qqq --uu uuuu
ADCON2 2455 2550 4455 4550 0-00 0000 0-00 0000 u-uu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
© 2009 Microchip Technology Inc. DS39632E-page 55
PIC18F2455/2550/4455/4550
CCPR1H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CCPR2H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 2455 2550 4455 4550 --00 0000 --00 0000 --uu uuuu
BAUDCON 2455 2550 4455 4550 0100 0-00 0100 0-00 uuuu u-uu
ECCP1DEL 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
ECCP1AS 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CVRCON 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
CMCON 2455 2550 4455 4550 0000 0111 0000 0111 uuuu uuuu
TMR3H 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 2455 2550 4455 4550 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SPBRG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
RCREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TXREG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TXSTA 2455 2550 4455 4550 0000 0010 0000 0010 uuuu uuuu
RCSTA 2455 2550 4455 4550 0000 000x 0000 000x uuuu uuuu
EEADR 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
EEDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
EECON2 2455 2550 4455 4550 0000 0000 0000 0000 0000 0000
EECON1 2455 2550 4455 4550 xx-0 x000 uu-0 u000 uu-0 u000
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F2455/2550/4455/4550
DS39632E-page 56 © 2009 Microchip Technology Inc.
IPR2 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
PIR2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(2)
PIE2 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
IPR1 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
2455 2550 4455 4550 -111 1111 -111 1111 -uuu uuuu
PIR1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu(2)
2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
PIE1 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
TRISE 2455 2550 4455 4550 ---- -111 ---- -111 ---- -uuu
TRISD 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
TRISC 2455 2550 4455 4550 11-- -111 11-- -111 uu-- -uuu
TRISB 2455 2550 4455 4550 1111 1111 1111 1111 uuuu uuuu
TRISA(5) 2455 2550 4455 4550 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 2455 2550 4455 4550 ---- -xxx ---- -uuu ---- -uuu
LATD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 2455 2550 4455 4550 xx-- -xxx uu-- -uuu uu-- -uuu
LATB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 2455 2550 4455 4550 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 2455 2550 4455 4550 0--- x000 0--- x000 u--- uuuu
PORTD 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2455 2550 4455 4550 xxxx -xxx uuuu -uuu uuuu -uuu
PORTB 2455 2550 4455 4550 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5) 2455 2550 4455 4550 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
© 2009 Microchip Technology Inc. DS39632E-page 57
PIC18F2455/2550/4455/4550
UEP15 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP14 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP13 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP12 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP11 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP10 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP9 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP8 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP7 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP6 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP5 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP4 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP3 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP2 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP1 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UEP0 2455 2550 4455 4550 ---0 0000 ---0 0000 ---u uuuu
UCFG 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu
UADDR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
UCON 2455 2550 4455 4550 -0x0 000- -0x0 000- -uuu uuu-
USTAT 2455 2550 4455 4550 -xxx xxx- -xxx xxx- -uuu uuu-
UEIE 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
UEIR 2455 2550 4455 4550 0--0 0000 0--0 0000 u--u uuuu
UIE 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
UIR 2455 2550 4455 4550 -000 0000 -000 0000 -uuu uuuu
UFRMH 2455 2550 4455 4550 ---- -xxx ---- -xxx ---- -uuu
UFRML 2455 2550 4455 4550 xxxx xxxx xxxx xxxx uuuu uuuu
SPPCON 2455 2550 4455 4550 ---- --00 ---- --00 ---- --uu
SPPEPS 2455 2550 4455 4550 00-0 0000 00-0 0000 uu-u uuuu
SPPCFG 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
SPPDATA 2455 2550 4455 4550 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
4: See Table 4-3 for Reset value for specific condition.
5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not
enabled as PORTA pins, they are disabled and read ‘0’.
PIC18F2455/2550/4455/4550
DS39632E-page 58 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 59
PIC18F2455/2550/4455/4550
5.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for concurrent
access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 7.0 “Data EEPROM
Memory”.
5.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The PIC18F2455 and PIC18F4455 each have 24 Kbytes
of Flash memory and can store up to 12,288 single-word
instructions. The PIC18F2550 and PIC18F4550 each
have 32 Kbytes of Flash memory and can store up to
16,384 single-word instructions.
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory maps for PIC18FX455 and
PIC18FX550 devices are shown in Figure 5-1.
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK
PC<20:0>
Stack Level 1
•
Stack Level 31
Reset Vector
Low-Priority Interrupt Vector
••
CALL, RCALL, RETURN,
RETFIE, RETLW, CALLW,
21
0000h
0018h
On-Chip
Program Memory
High-Priority Interrupt Vector 0008h
User Memory Space
1FFFFFh
6000h
5FFFh
Read ‘0’
200000h
PC<20:0>
Stack Level 1
•
Stack Level 31
Reset Vector
Low-Priority Interrupt Vector
••
CALL, RCALL, RETURN,
RETFIE, RETLW, CALLW,
21
0000h
0018h
8000h
7FFFh
On-Chip
Program Memory
High-Priority Interrupt Vector 0008h
User Memory Space
Read ‘0’
1FFFFFh
200000h
24 Kbyte Devices 32 Kbyte Device
ADDULNK, SUBULNK ADDULNK, SUBULNK
PIC18F2455/2550/4455/4550
DS39632E-page 60 © 2009 Microchip Technology Inc.
5.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL and GOTO program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction
is executed or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW or
a RETFIE instruction. PCLATU and PCLATH are not
affected by any of the RETURN or CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit Stack Pointer, STKPTR. The stack space is not
part of either program or data space. The Stack Pointer
is readable and writable and the address on the top of
the stack is readable and writable through the
Top-of-Stack Special Function Registers. Data can also
be pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack.
The Stack Pointer is first incremented and the location
pointed to by the Stack Pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack. The contents of the location
pointed to by the STKPTR are transferred to the PC
and then the Stack Pointer is decremented.
The Stack Pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a Stack Pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full, has overflowed or has underflowed.
5.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack location
pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALL or interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a user-defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack<20:0>
Top-of-Stack
000D58h
TOSU TOSH TOSL
00h 1Ah 34h
STKPTR<4:0>
Top-of-Stack Registers Stack Pointer
© 2009 Microchip Technology Inc. DS39632E-page 61
PIC18F2455/2550/4455/4550
5.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the Stack
Pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bit. The value of
the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. On Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System (RTOS) for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack
Overflow Reset Enable) Configuration bit. (Refer to
Section 25.1 “Configuration Bits” for a description of
the device Configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the Stack
Pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and the STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack, without disturbing normal program execution,
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the Stack Pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by decrementing
the Stack Pointer. The previous value pushed
onto the stack then becomes the TOS value.
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
REGISTER 5-1: STKPTR: STACK POINTER REGISTER
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
PIC18F2455/2550/4455/4550
DS39632E-page 62 © 2009 Microchip Technology Inc.
5.1.2.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by user software or a Power-on Reset.
5.1.3 FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers to provide a “fast return”
option for interrupts. Each stack is only one level deep
and is neither readable nor writable. It is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. All interrupt sources
will push values into the stack registers. The values in
the registers are then loaded back into their associated
registers if the RETFIE, FAST instruction is used to
return from the interrupt.
If both low and high-priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the stack
register values stored by the low-priority interrupt will
be overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
Fast Register Stack for returns from interrupt. If no
interrupts are used, the Fast Register Stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the Fast Register
Stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the Fast Register Stack. A
RETURN, FAST instruction is then executed to restore
these registers from the Fast Register Stack.
Example 5-1 shows a source code example that uses
the Fast Register Stack during a subroutine call and
return.
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
5.1.4 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-2: COMPUTED GOTO USING
AN OFFSET VALUE
5.1.4.2 Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per
program word by using table reads and writes. The
Table Pointer (TBLPTR) register specifies the byte
address and the Table Latch (TABLAT) register
contains the data that is read from or written to program
memory. Data is transferred to or from program
memory one byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1 •
•
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
© 2009 Microchip Technology Inc. DS39632E-page 63
PIC18F2455/2550/4455/4550
5.2 PIC18 Instruction Cycle
5.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an
internal or external source, is internally divided by four
to generate four non-overlapping quadrature clocks
(Q1, Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruction
Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
5.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are pipelined
in such a manner that a fetch takes one instruction
cycle, while the decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change (e.g.,
GOTO), then two cycles are required to complete the
instruction (Example 5-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F2455/2550/4455/4550
DS39632E-page 64 © 2009 Microchip Technology Inc.
5.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions
are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSb will always read ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction.
Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction, GOTO 0006h, is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 26.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY
5.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction
specifies a special form of NOP. If the instruction is
executed in proper sequence, immediately after the
first word, the data in the second word is accessed and
used by the instruction sequence. If the first word is
skipped for some reason and the second word is
executed by itself, a NOP is executed instead. This is
necessary for cases when the two-word instruction is
preceded by a conditional instruction that changes the
PC. Example 5-4 shows how this works.
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1 LSB = 0 ↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 5.5 “Program Memory and
the Extended Instruction Set” for
information on two-word instruction in the
extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
© 2009 Microchip Technology Inc. DS39632E-page 65
PIC18F2455/2550/4455/4550
5.3 Data Memory Organization
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each.
PIC18F2455/2550/4455/4550 devices implement eight
complete banks, for a total of 2048 bytes. Figure 5-5
shows the data memory organization for the devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.3 “Access Bank” provides a
detailed description of the Access RAM.
5.3.1 USB RAM
Banks 4 through 7 of the data memory are actually
mapped to special dual port RAM. When the USB
module is disabled, the GPRs in these banks are used
like any other GPR in the data memory space.
When the USB module is enabled, the memory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use the areas of USB RAM
that are not allocated as USB buffers for normal
scratchpad memory or other variable storage. In practice,
the dynamic nature of buffer allocation makes this
risky at best. Additionally, Bank 4 is used for USB buffer
management when the module is enabled and should
not be used for any other purposes during that time.
Additional information on USB RAM and buffer
operation is provided in Section 17.0 “Universal
Serial Bus (USB)”.
5.3.2 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished
with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit Bank Pointer.
Most instructions in the PIC18 instruction set make use
of the Bank Pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
eight Least Significant bits. Only the four lower bits of
the BSR are implemented (BSR3:BSR0). The upper
four bits are unused; they will always read ‘0’ and cannot
be written to. The BSR can be loaded directly by
using the MOVLB instruction.
The value of the BSR indicates the bank in data
memory. The eight bits in the instruction show the location
in the bank and can be thought of as an offset from
the bank’s lower boundary. The relationship between
the BSR’s value and the bank division in data memory
is shown in Figure 5-6.
Since up to sixteen registers may share the same
low-order address, the user must always be careful to
ensure that the proper bank is selected before performing
a data read or write. For example, writing what
should be program data to an 8-bit address of F9h,
while the BSR is 0Fh, will end up resetting the program
counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the STATUS register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.6 “Data Memory and the
Extended Instruction Set” for more
information.
PIC18F2455/2550/4455/4550
DS39632E-page 66 © 2009 Microchip Technology Inc.
FIGURE 5-5: DATA MEMORY MAP
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
060h
05Fh
F60h
FFFh
00h
5Fh
60h
FFh
Access Bank
When a = 0:
The BSR is ignored and the
Access Bank is used.
The first 96 bytes are
general purpose RAM
(from Bank 0).
The remaining 160 bytes are
Special Function Registers
(from Bank 15).
When a = 1:
The BSR specifies the bank
used by the instruction.
F5Fh
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
800h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
00h
GPR
GPR(1)
GPR
GPR(1)
GPR(1)
GPR(1)
FFh
= 0011
= 0100
= 0101
= 0111
= 1000
Unused
to Read as 00h
= 1110
Note 1: These banks also serve as RAM buffer for USB operation. See Section 5.3.1 “USB RAM” for more
information.
Unused
© 2009 Microchip Technology Inc. DS39632E-page 67
PIC18F2455/2550/4455/4550
FIGURE 5-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
5.3.3 ACCESS BANK
While the use of the BSR, with an embedded 8-bit
address, allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 96 bytes of
memory (00h-5Fh) in Bank 0 and the last 160 bytes of
memory (60h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. The
upper half is where the device’s SFRs are mapped.
These two areas are mapped contiguously in the
Access Bank and can be addressed in a linear fashion
by an 8-bit address (Figure 5-5).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle without
updating the BSR first. For 8-bit addresses of 60h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 60h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail
in Section 5.6.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.4 GENERAL PURPOSE
REGISTER FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom
of the SFR area. GPRs are not initialized by a
Power-on Reset and are unchanged on all other
Resets.
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
7 0
From Opcode(2)
0 0 0 0
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0 0 1 1 1 1 1 1 1 1 1 1
7 0
BSR(1)
PIC18F2455/2550/4455/4550
DS39632E-page 68 © 2009 Microchip Technology Inc.
5.3.5 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend downward
to occupy the top segment of Bank 15, from F60h
to FFFh. A list of these registers is given in Table 5-1
and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP
Address Name Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1 F7Fh UEP15
FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1 F7Eh UEP14
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1 F7Dh UEP13
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2) F7Ch UEP12
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE F7Bh UEP11
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2) F7Ah UEP10
FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2) F79h UEP9
FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2) F78h UEP8
FF7h TBLPTRH FD7h TMR0H FB7h ECCP1DEL F97h —(2) F77h UEP7
FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE(3) F76h UEP6
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3) F75h UEP5
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h UEP4
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h UEP3
FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA F72h UEP2
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2) F71h UEP1
FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2) F70h UEP0
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2) F6Fh UCFG
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2) F6Eh UADDR
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3) F6Dh UCON
FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3) F6Ch USTAT
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC F6Bh UEIE
FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB F6Ah UEIR
FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA F69h UIE
FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2) F68h UIR
FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2) F67h UFRMH
FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2) F66h UFRML
FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2) F65h SPPCON(3)
FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE F64h SPPEPS(3)
FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3) F63h SPPCFG(3)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SPPDATA(3)
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h —(2)
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h —(2)
Note 1: Not a physical register.
2: Unimplemented registers are read as ‘0’.
3: These registers are implemented only on 40/44-pin devices.
© 2009 Microchip Technology Inc. DS39632E-page 69
PIC18F2455/2550/4455/4550
TABLE 5-2: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 53, 60
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 53, 60
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 53, 60
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 53, 61
PCLATU — — — Holding Register for PC<20:16> ---0 0000 53, 60
PCLATH Holding Register for PC<15:8> 0000 0000 53, 60
PCL PC Low Byte (PC<7:0>) 0000 0000 53, 60
TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 53, 84
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 53, 84
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 53, 84
TABLAT Program Memory Table Latch 0000 0000 53, 84
PRODH Product Register High Byte xxxx xxxx 53, 97
PRODL Product Register Low Byte xxxx xxxx 53, 97
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 53, 101
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 53, 102
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 53, 103
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 53, 75
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 53, 76
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 53, 76
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 53, 76
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 53, 76
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 53, 75
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 53, 75
WREG Working Register xxxx xxxx 53
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 53, 75
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 53, 76
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 53, 76
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 53, 76
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 53, 76
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 53, 75
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 53, 75
BSR — — — — Bank Select Register ---- 0000 54, 65
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 54, 75
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 54, 76
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 54, 76
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 54, 76
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 54, 76
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 54, 75
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 54, 75
STATUS — — — N OV Z DC C ---x xxxx 54, 73
TMR0H Timer0 Register High Byte 0000 0000 54, 129
TMR0L Timer0 Register Low Byte xxxx xxxx 54, 129
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 54, 127
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C™ Slave mode only.
PIC18F2455/2550/4455/4550
DS39632E-page 70 © 2009 Microchip Technology Inc.
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 54, 33
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 54, 285
WDTCON — — — — — — — SWDTEN --- ---0 54, 304
RCON IPEN SBOREN(2) — RI TO PD POR BOR 0q-1 11q0 54, 46
TMR1H Timer1 Register High Byte xxxx xxxx 54, 136
TMR1L Timer1 Register Low Byte xxxx xxxx 54, 136
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 54, 131
TMR2 Timer2 Register 0000 0000 54, 138
PR2 Timer2 Period Register 1111 1111 54, 138
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54, 137
SSPBUF MSSP Receive Buffer/Transmit Register xxxx xxxx 54, 198,
207
SSPADD MSSP Address Register in I2C™ Slave mode. MSSP Baud Rate Reload Register in I2C™ Master mode. 0000 0000 54, 207
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 54, 198,
208
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 54, 199,
209
SSPCON2 GCEN ACKSTAT ACKDT/
ADMSK5(7)
ACKEN/
ADMSK4(7)
RCEN/
ADMSK3(7)
PEN/
ADMSK2(7)
RSEN/
ADMSK1(7)
SEN 0000 0000 54, 210
ADRESH A/D Result Register High Byte xxxx xxxx 54, 274
ADRESL A/D Result Register Low Byte xxxx xxxx 54, 274
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 54, 265
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 54, 266
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 54, 267
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 55, 144
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 55, 144
CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 55, 143,
151
CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 55, 144
CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 55, 144
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 55, 143
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 0100 0-00 55, 246
ECCP1DEL PRSEN PDC6(3) PDC5(3) PDC4(3) PDC3(3) PDC2(3) PDC1(3) PDC0(3) 0000 0000 55, 160
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(3) PSSBD0(3) 0000 0000 55, 161
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 55, 281
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 55, 275
TMR3H Timer3 Register High Byte xxxx xxxx 55, 141
TMR3L Timer3 Register Low Byte xxxx xxxx 55, 141
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 55, 139
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 55, 247
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 55, 247
RCREG EUSART Receive Register 0000 0000 55, 256
TXREG EUSART Transmit Register 0000 0000 55, 253
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 55, 244
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 55, 245
TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C™ Slave mode only.
© 2009 Microchip Technology Inc. DS39632E-page 71
PIC18F2455/2550/4455/4550
EEADR EEPROM Address Register 0000 0000 55, 91
EEDATA EEPROM Data Register 0000 0000 55, 91
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 55, 82
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 55, 83
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 1111 1111 56, 109
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 0000 0000 56, 105
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 0000 0000 56, 107
IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 56, 108
PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 56, 104
PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 56, 106
OSCTUNE INTSRC — — TUN4 TUN3 TUN2 TUN1 TUN0 0--0 0000 56, 28
TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 ---- -111 56, 126
TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 56, 124
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 11-- -111 56, 121
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 56, 118
TRISA — TRISA6(4) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 -111 1111 56, 115
LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -xxx 56, 126
LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 56, 124
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 xx-- -xxx 56, 121
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 56, 118
LATA — LATA6(4) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 -xxx xxxx 56, 115
PORTE RDPU(3) — — — RE3(5) RE2(3) RE1(3) RE0(3) 0--- x000 56, 125
PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 56, 124
PORTC RC7 RC6 RC5(6) RC4(6) — RC2 RC1 RC0 xxxx -xxx 56, 121
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 56, 118
PORTA — RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 -x0x 0000 56, 115
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 57, 172
TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C™ Slave mode only.
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DS39632E-page 72 © 2009 Microchip Technology Inc.
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 00-0 0000 57, 168
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 -000 0000 57, 173
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — -0x0 000- 57, 166
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — -xxx xxx- 57, 171
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 0--0 0000 57, 185
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 0--0 0000 57, 184
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 57, 183
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 57, 181
UFRMH — — — — — FRM10 FRM9 FRM8 ---- -xxx 57, 173
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 xxxx xxxx 57, 173
SPPCON(3) — — — — — — SPPOWN SPPEN ---- --00 57, 191
SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 00-0 0000 57, 195
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 0000 0000 57, 192
SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0000 0000 57, 196
TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
2: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
3: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
4: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
5: RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
7: I2C™ Slave mode only.
© 2009 Microchip Technology Inc. DS39632E-page 73
PIC18F2455/2550/4455/4550
5.3.6 STATUS REGISTER
The STATUS register, shown in Register 5-2, contains
the arithmetic status of the ALU. As with any other SFR,
it can be the operand for any instruction.
If the STATUS register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results
of the instruction are not written; instead, the STATUS
register is updated according to the instruction
performed. Therefore, the result of an instruction with
the STATUS register as its destination may be different
than intended. As an example, CLRF STATUS will set
the Z bit and leave the remaining Status bits
unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the STATUS
register because these instructions do not affect the Z,
C, DC, OV or N bits in the STATUS register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 26-2 and
Table 26-3.
Note: The C and DC bits operate as the Borrow
and Digit Borrow bits, respectively, in
subtraction.
REGISTER 5-2: STATUS REGISTER
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC(1) C(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative
(ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude
which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit(1)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(2)
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.
2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the
source register.
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5.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.6.1 “Indexed
Addressing with Literal Offset”.
5.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2 DIRECT ADDRESSING
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.4 “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.3 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.2 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original
contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
5.4.3 INDIRECT ADDRESSING
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special Function Registers, they can also be directly
manipulated under program control. This makes FSRs
very useful in implementing data structures, such as
tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 5.6 “Data
Memory and the Extended Instruction
Set” for more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
© 2009 Microchip Technology Inc. DS39632E-page 75
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5.4.3.1 FSR Registers and the
INDF Operand
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers: FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs, then, serve
as pointers to data memory locations.
Indirect Addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers; they are
mapped in the SFR space but are not physically implemented.
Reading or writing to a particular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use the
contents of their corresponding FSR as a pointer to the
instruction’s target. The INDF operand is just a
convenient way of using the pointer.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
FIGURE 5-7: INDIRECT ADDRESSING
FSR1H:FSR1L
7 0
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
7 0
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
x x x x 1 1 1 0 1 1 0 0 1 1 0 0
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DS39632E-page 76 © 2009 Microchip Technology Inc.
5.4.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by ‘1’ afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by ‘1’ afterwards
• PREINC: increments the FSR value by ‘1’, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them. Similarly,
accessing a PLUSW register gives the FSR value
offset by that in the W register; neither value is actually
changed in the operation. Accessing the other virtual
registers changes the value of the FSR registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is,
rollovers of the FSRnL register, from FFh to 00h, carry
over to the FSRnH register. On the other hand, results
of these operations do not change the value of any
flags in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form
of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3 Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs
or virtual registers represent special cases. For example,
using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of INDF1,
using INDF0 as an operand, will return 00h. Attempts
to write to INDF1, using INDF0 as the operand, will
result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses Indirect Addressing.
Similarly, operations by Indirect Addressing are generally
permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
© 2009 Microchip Technology Inc. DS39632E-page 77
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5.5 Program Memory and the
Extended Instruction Set
The operation of program memory is unaffected by the
use of the extended instruction set.
Enabling the extended instruction set adds eight
additional two-word commands to the existing
PIC18 instruction set: ADDFSR, ADDULNK, CALLW,
MOVSF, MOVSS, PUSHL, SUBFSR and SUBULNK. These
instructions are executed as described in
Section 5.2.4 “Two-Word Instructions”.
5.6 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
Configuration bit = 1) significantly changes certain
aspects of data memory and its addressing.
Specifically, the use of the Access Bank for many of the
core PIC18 instructions is different. This is due to the
introduction of a new addressing mode for the data
memory space. This mode also alters the behavior of
Indirect Addressing using FSR2 and its associated
operands.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect Addressing
with FSR0 and FSR1 also remains unchanged.
5.6.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of Indirect Addressing using the FSR2
register pair and its associated file operands. Under the
proper conditions, instructions that use the Access
Bank – that is, most bit-oriented and byte-oriented
instructions – can invoke a form of Indexed Addressing
using an offset specified in the instruction. This special
addressing mode is known as Indexed Addressing with
Literal Offset or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0);
and
• The file address argument is less than or equal
to 5Fh.
Under these conditions, the file address of the instruction
is not interpreted as the lower byte of an address
(used with the BSR in Direct Addressing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an Address Pointer
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.6.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use Direct
Addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set. Instructions
that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’) or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the
different possible addressing modes when the
extended instruction set is enabled in shown in
Figure 5-8.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 26.2.1
“Extended Instruction Syntax”.
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FIGURE 5-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is interpreted
as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs or locations F60h to
0FFh (Bank 15) of data
memory.
Locations below 60h are not
available in this addressing
mode.
When a = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When a = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is interpreted
as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F60h
FFFh
Valid range
00h
60h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
080h
100h
F00h
F60h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
001001da ffffffff
001001da ffffffff
000h
080h
100h
F00h
F60h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
080h
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5.6.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the lower portion of Access
RAM (00h to 5Fh) is mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 5.3.3 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 5-9.
Remapping of the Access Bank applies only to operations
using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use Direct Addressing as before. Any indirect or
indexed operation that explicitly uses any of the indirect
file operands (including FSR2) will continue to operate
as standard Indirect Addressing. Any instruction that
uses the Access Bank, but includes a register address
of greater than 05Fh, will use Direct Addressing and
the normal Access Bank map.
5.6.4 BSR IN INDEXED LITERAL
OFFSET MODE
Although the Access Bank is remapped when the
extended instruction set is enabled, the operation of the
BSR remains unchanged. Direct Addressing, using the
BSR to select the data memory bank, operates in the
same manner as previously described.
FIGURE 5-9: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL
OFFSET ADDRESSING
Data Memory
000h
100h
200h
F60h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Special Function Registers
at F60h through FFFh are
mapped to 60h through
FFh as usual.
Bank 0 addresses below
5Fh are not available in
this mode. They can still
be addressed by using the
BSR.
Access Bank
00h
60h
FFh
Bank 0
SFRs
Bank 1 “Window”
Window
Example Situation:
120h
17Fh
5Fh
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NOTES:
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6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable, during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 32 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A Bulk Erase
operation may not be issued from user code.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word-aligned.
FIGURE 6-1: TABLE READ OPERATION
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
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FIGURE 6-2: TABLE WRITE OPERATION
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 25.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer actually points to one of 32 holding registers, the address of which is determined by
TBLPTRL<4:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Holding Registers
Program Memory
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
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REGISTER 6-1: EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR(1) WREN WR RD
bit 7 bit 0
Legend: S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
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6.2.2 TABLE LATCH REGISTER (TABLAT)
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3 TABLE POINTER REGISTER
(TBLPTR)
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the user ID and the Configuration bits.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways based on the table operation.
These operations are shown in Table 6-1. These
operations on the TBLPTR only affect the low-order
21 bits.
6.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the five LSbs of the Table
Pointer register (TBLPTR<4:0>) determine which of
the 32 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 32 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of the
TBLPTR based on Flash program memory operations.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21 16 15 8 7 0
TABLE ERASE
TABLE READ – TBLPTR<21:0>
TBLPTRU TBLPTRH TBLPTRL
TBLPTR<21:6>
TABLE WRITE – TBLPTR<21:5>
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6.3 Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD TABLAT
TBLPTR = xxxxx1
FETCH Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVF WORD_ODD
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6.4 Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
Bulk Erased. Word Erase in the Flash array is not
supported.
When initiating an erase sequence from the microcontroller
itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
6.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory is:
1. Load Table Pointer register with address of row
being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the Row Erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
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6.5 Writing to Flash Program Memory
The minimum programming block is 16 words or
32 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 32 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 32 times for
each programming operation. All of the table write operations
will essentially be short writes because only the
holding registers are written. At the end of updating the
32 holding registers, the EECON1 register must be
written to in order to start the programming operation
with a long write.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the Row Erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write 32 bytes into the holding registers with
auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Repeat steps 6 through 14 once more to write
64 bytes.
15. Verify the memory (table read).
This procedure will require about 8 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 32 holding registers
before executing a write operation.
TBLPTR = xxxx00 TBLPTR = xxxx01 TBLPTR = xxxx02 TBLPTR = xxxx1F
Program Memory
Holding Register Holding Register Holding Register Holding Register
8 8 8 8
TABLAT
Write Register
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 32 bytes in
the holding register.
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64’ ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW D’2’
MOVWF COUNTER1
WRITE_BUFFER_BACK
MOVLW D’32’ ; number of bytes in holding register
MOVWF COUNTER
WRITE_BYTE_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_WORD_TO_HREGS
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EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed
if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
6.5.4 PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 25.0 “Special Features of the
CPU” for more detail.
6.6 Flash Program Operation During
Code Protection
See Section 25.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
DECFSZ COUNTER1
BRA WRITE_BUFFER_BACK
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TBLPTRU — — bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 53
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 53
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 53
TABLAT Program Memory Table Latch 53
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
EECON2 EEPROM Control Register 2 (not a physical register) 55
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 55
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
Note 1: Bit 21 of the TBLPTRU allows access to the device Configuration bits.
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7.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array,
separate from the data RAM and program memory, that
is used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space, but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writable during normal operation over the
entire VDD range.
Four SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR register
holds the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip
to chip. Please refer to parameter D122 (Table 28-1 in
Section 28.0 “Electrical Characteristics”) for exact
limits.
7.1 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 7-1) is the control
register for data and program memory access. Control
bit, EEPGD, determines if the access will be to program
or data EEPROM memory. When clear, operations will
access the data EEPROM memory. When set, program
memory is accessed.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers. When CFGS is clear,
the EEPGD bit selects either Flash program or data
EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WREN bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
PIC18F2455/2550/4455/4550
DS39632E-page 92 © 2009 Microchip Technology Inc.
REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR(1) WREN WR RD
bit 7 bit 0
Legend: S = Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by
completion of erase operation)
0 = Perform write-only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit(1)
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
operation or an improper write attempt)
0 = The write operation completed
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error
condition.
© 2009 Microchip Technology Inc. DS39632E-page 93
PIC18F2455/2550/4455/4550
7.2 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation or until it is written to
by the user (during a write operation).
The basic process is shown in Example 7-1.
7.3 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution
(i.e., runaway programs). The WREN bit should
be kept clear at all times except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruction.
Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt,
or poll this bit. EEIF must be cleared by software.
7.4 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 7-1: DATA EEPROM READ
EXAMPLE 7-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Lower bits of Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Lower bits of Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
; User code execution
BCF EECON1, WREN ; Disable writes on write complete (EEIF set)
PIC18F2455/2550/4455/4550
DS39632E-page 94 © 2009 Microchip Technology Inc.
7.5 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM regardless of the state of the
code-protect Configuration bit. Refer to Section 25.0
“Special Features of the CPU” for additional
information.
7.6 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33, Table 28-12).
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.7 Using the Data EEPROM
The data EEPROM is a high-endurance, byteaddressable
array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specification D124 or D124A.
If this is not the case, an array refresh must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
© 2009 Microchip Technology Inc. DS39632E-page 95
PIC18F2455/2550/4455/4550
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
EEADR EEPROM Address Register 55
EEDATA EEPROM Data Register 55
EECON2 EEPROM Control Register 2 (not a physical register) 55
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 55
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PIC18F2455/2550/4455/4550
DS39632E-page 96 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 97
PIC18F2455/2550/4455/4550
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the STATUS
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications
previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2 Operation
Example 8-1 shows the instruction sequence for an
8 x 8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded
in the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed
Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs
Hardware multiply 6 6 600 ns 2.4 μs 6 μs
16 x 16 unsigned
Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs
Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs
16 x 16 signed
Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs
Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs
PIC18F2455/2550/4455/4550
DS39632E-page 98 © 2009 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the
arguments, the MSb for each argument pair is tested
and the appropriate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L,W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
© 2009 Microchip Technology Inc. DS39632E-page 99
PIC18F2455/2550/4455/4550
9.0 INTERRUPTS
The PIC18F2455/2550/4455/4550 devices have
multiple interrupt sources and an interrupt priority feature
that allows each interrupt source to be assigned a highpriority
level or a low-priority level. The high-priority
interrupt vector is at 000008h and the low-priority
interrupt vector is at 000018h. High-priority interrupt
events will interrupt any low-priority interrupts that may
be in progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual interrupts
can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High-priority interrupt sources can interrupt a lowpriority
interrupt. Low-priority interrupts are not
processed while high-priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used) which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
9.1 USB Interrupts
Unlike other peripherals, the USB module is capable of
generating a wide range of interrupts for many types of
events. These include several types of normal communication
and status events and several module level
error events.
To handle these events, the USB module is equipped
with its own interrupt logic. The logic functions in a
manner similar to the microcontroller level interrupt funnel,
with each interrupt source having separate flag and
enable bits. All events are funneled to a single device
level interrupt, USBIF (PIR2<5>). Unlike the device
level interrupt logic, the individual USB interrupt events
cannot be individually assigned their own priority. This
is determined at the device level interrupt funnel for all
USB events by the USBIP bit.
For additional details on USB interrupt logic, refer to
Section 17.5 “USB Interrupts”.
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
PIC18F2455/2550/4455/4550
DS39632E-page 100 © 2009 Microchip Technology Inc.
FIGURE 9-1: INTERRUPT LOGIC
TMR0IE
GIE/GIEH
PEIE/GIEL
Wake-up if in Sleep Mode
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
PEIE/GIEL
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
USBIF
USBIE
USBIP
Additional Peripheral Interrupts
TMR1IF
TMR1IE
TMR1IP
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
USBIF
USBIE
USBIP
Additional Peripheral Interrupts
GIE/GIEH
From USB
Interrupt Logic
From USB
Interrupt Logic
© 2009 Microchip Technology Inc. DS39632E-page 101
PIC18F2455/2550/4455/4550
9.2 INTCON Registers
The INTCON registers are readable and writable
registers which contain various enable, priority and flag
bits.
Note: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
REGISTER 9-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high-priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low-priority peripheral interrupts (if GIE/GIEH = 1)
0 = Disables all low-priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit(1)
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: A mismatch condition will continue to set this bit. Reading PORTB, and then waiting one additional instruction
cycle, will end the mismatch condition and allow the bit to be cleared.
PIC18F2455/2550/4455/4550
DS39632E-page 102 © 2009 Microchip Technology Inc.
REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
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REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding
enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt. This feature allows for software polling.
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9.3 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1 and PIR2).
Note 1: Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the appropriate
interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPPIF: Streaming Parallel Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
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REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5 USBIF: USB Interrupt Flag bit
1 = USB has requested an interrupt (must be cleared in software)
0 = No USB interrupt request
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A high/low-voltage condition occurred (must be cleared in software)
0 = No high/low-voltage event has occurred
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 or TMR3 register capture occurred (must be cleared in software)
0 = No TMR1 or TMR3 register capture occurred
Compare mode:
1 = A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0 = No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
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9.4 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPPIE: Streaming Parallel Port Read/Write Interrupt Enable bit(1)
1 = Enables the SPP read/write interrupt
0 = Disables the SPP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
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REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 USBIE: USB Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
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9.5 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority registers (IPR1 and IPR2). Using the
priority bits requires that the Interrupt Priority Enable
(IPEN) bit be set.
REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPPIP: Streaming Parallel Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Note 1: This bit is reserved on 28-pin devices; always maintain this bit clear.
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REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 USBIP: USB Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
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9.6 RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
REGISTER 9-10: RCON: RESET CONTROL REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
For details of bit operation, see Register 4-1.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-1.
bit 2 PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-1.
bit 1 POR: Power-on Reset Status bit(2)
For details of bit operation, see Register 4-1.
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’. See Register 4-1 for additional information.
2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional
information.
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9.7 INTx Pin Interrupts
External interrupts on the RB0/AN12/INT0/FLT0/SDI/
SDA, RB1/AN10/INT1/SCK/SCL and RB2/AN8/INT2/
VMO pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxIF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxIE. Flag bit,
INTxIF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1 and INT2) can wakeup
the processor from the power-managed modes if bit,
INTxIE, was set prior to going into the power-managed
modes. If the Global Interrupt Enable bit, GIE, is set, the
processor will branch to the interrupt vector following
wake-up.
Interrupt priority for INT1 and INT2 is determined by
the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>).
There is no priority bit associated with INT0. It is
always a high-priority interrupt source.
9.8 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt
priority bit, TMR0IP (INTCON2<2>). See Section 11.0
“Timer0 Module” for further details on the Timer0
module.
9.9 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.10 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 5.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 9-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
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NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 113
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10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch register (LATA) is useful for readmodify-
write operations on the value driven by the I/O
pins.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The corresponding
Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins; writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA6 pin
is multiplexed with the main oscillator pin; it is enabled
as an oscillator or I/O pin by the selection of the main
oscillator in Configuration Register 1H (see
Section 25.1 “Configuration Bits” for details). When
not used as a port pin, RA6 and its associated TRIS
and LAT bits are read as ‘0’.
RA4 is also multiplexed with the USB module; it serves
as a receiver input from an external USB transceiver.
For details on configuration of the USB module, see
Section 17.2 “USB Status and Control”.
Several PORTA pins are multiplexed with analog inputs,
the analog VREF+ and VREF- inputs and the comparator
voltage reference output. The operation of pins RA5
and RA3:RA0 as A/D converter inputs is selected by
clearing/setting the control bits in the ADCON1 register
(A/D Control Register 1).
All other PORTA pins have TTL input levels and full
CMOS output drivers.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1: INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
D Q
CK
D Q
CK
EN
Q D
EN
RD LAT
or PORT
Note 1: I/O pins have diode protection to VDD and VSS.
Note: On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 0Fh ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 07h ; Configure comparators
MOVWF CMCON ; for digital input
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
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TABLE 10-1: PORTA I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RA0/AN0 RA0 0 OUT DIG LATA<0> data output; not affected by analog input.
1 IN TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1 IN ANA A/D Input Channel 0 and Comparator C1- input. Default configuration
on POR; does not affect digital output.
RA1/AN1 RA1 0 OUT DIG LATA<1> data output; not affected by analog input.
1 IN TTL PORTA<1> data input; reads ‘0’ on POR.
AN1 1 IN ANA A/D Input Channel 1 and Comparator C2- input. Default configuration
on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF
RA2 0 OUT DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1 IN TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2 1 IN ANA A/D Input Channel 2 and Comparator C2+ input. Default configuration
on POR; not affected by analog output.
VREF- 1 IN ANA A/D and comparator voltage reference low input.
CVREF x OUT ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/
VREF+
RA3 0 OUT DIG LATA<3> data output; not affected by analog input.
1 IN TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1 IN ANA A/D Input Channel 3 and Comparator C1+ input. Default configuration
on POR.
VREF+ 1 IN ANA A/D and comparator voltage reference high input.
RA4/T0CKI/
C1OUT/RCV
RA4 0 OUT DIG LATA<4> data output; not affected by analog input.
1 IN ST PORTA<4> data input; disabled when analog input enabled.
T0CKI 1 IN ST Timer0 clock input.
C1OUT 0 OUT DIG Comparator 1 output; takes priority over port data.
RCV x IN TTL External USB transceiver RCV input.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5 0 OUT DIG LATA<5> data output; not affected by analog input.
1 IN TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 IN ANA A/D Input Channel 4. Default configuration on POR.
SS 1 IN TTL Slave select input for MSSP module.
HLVDIN 1 IN ANA High/Low-Voltage Detect external trip point input.
C2OUT 0 OUT DIG Comparator 2 output; takes priority over port data.
OSC2/CLKO/
RA6
OSC2 x OUT ANA Main oscillator feedback output connection (all XT and HS modes).
CLKO x OUT DIG System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6 0 OUT DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
1 IN TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
© 2009 Microchip Technology Inc. DS39632E-page 115
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TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTA — RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 56
LATA — LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 56
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
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10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding
Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an interrupton-
change feature. Only pins configured as inputs can
cause this interrupt to occur. Any RB7:RB4 pin
configured as an output is excluded from the interrupton-
change comparison. The pins are compared with
the old value latched on the last read of PORTB. The
“mismatch” outputs of RB7:RB4 are ORed together to
generate the RB Port Change Interrupt with Flag bit,
RBIF (INTCON<0>).
The interrupt-on-change can be used to wake the
device from Sleep. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Wait one TCY delay (for example, execute one
NOP instruction).
c) Clear flag bit, RBIF
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after a one TCY delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Pins, RB2 and RB3, are multiplexed with the USB
peripheral and serve as the differential signal outputs
for an external USB transceiver (TRIS configuration).
Refer to Section 17.2.2.2 “External Transceiver” for
additional information on configuring the USB module
for operation with an external transceiver.
RB4 is multiplexed with CSSPP, the chip select
function for the Streaming Parallel Port (SPP) – TRIS
setting. Details of its operation are discussed in
Section 18.0 “Streaming Parallel Port”.
EXAMPLE 10-2: INITIALIZING PORTB
Note: On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
By programming the Configuration bit,
PBADEN (CONFIG3H<1>), RB4:RB0 will
alternatively be configured as digital inputs
on POR.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0Eh ; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
© 2009 Microchip Technology Inc. DS39632E-page 117
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TABLE 10-3: PORTB I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RB0/AN12/
INT0/FLT0/
SDI/SDA
RB0 0 OUT DIG LATB<0> data output; not affected by analog input.
1 IN TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN12 1 IN ANA A/D Input Channel 12.(1)
INT0 1 IN ST External Interrupt 0 input.
FLT0 1 IN ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
SDI 1 IN ST SPI data input (MSSP module).
SDA 1 OUT DIG I2C™ data output (MSSP module); takes priority over port data.
1 IN I2C/SMB I2C data input (MSSP module); input type depends on module setting.
RB1/AN10/
INT1/SCK/
SCL
RB1 0 OUT DIG LATB<1> data output; not affected by analog input.
1 IN TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN10 1 IN ANA A/D Input Channel 10.(1)
INT1 1 IN ST External Interrupt 1 input.
SCK 0 OUT DIG SPI clock output (MSSP module); takes priority over port data.
1 IN ST SPI clock input (MSSP module).
SCL 0 OUT DIG I2C clock output (MSSP module); takes priority over port data.
1 IN I2C/SMB I2C clock input (MSSP module); input type depends on module setting.
RB2/AN8/
INT2/VMO
RB2 0 OUT DIG LATB<2> data output; not affected by analog input.
1 IN TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN8 1 IN ANA A/D input channel 8.(1)
INT2 1 IN ST External Interrupt 2 input.
VMO 0 OUT DIG External USB transceiver VMO data output.
RB3/AN9/
CCP2/VPO
RB3 0 OUT DIG LATB<3> data output; not affected by analog input.
1 IN TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN9 1 IN ANA A/D Input Channel 9.(1)
CCP2(2) 0 OUT DIG CCP2 compare and PWM output.
1 IN ST CCP2 capture input.
VPO 0 OUT DIG External USB transceiver VPO data output.
RB4/AN11/
KBI0/CSSPP
RB4 0 OUT DIG LATB<4> data output; not affected by analog input.
1 IN TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN11 1 IN ANA A/D Input Channel 11.(1)
KBI0 1 IN TTL Interrupt-on-pin change.
CSSPP(4) 0 OUT DIG SPP chip select control output.
RB5/KBI1/
PGM
RB5 0 OUT DIG LATB<5> data output.
1 IN TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1 1 IN TTL Interrupt-on-pin change.
PGM x IN ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
Configuration bit; all other pin functions disabled.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
3: All other pin functions are disabled when ICSP™ or ICD operation is enabled.
4: 40/44-pin devices only.
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TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB6/KBI2/
PGC
RB6 0 OUT DIG LATB<6> data output.
1 IN TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2 1 IN TTL Interrupt-on-pin change.
PGC x IN ST Serial execution (ICSP™) clock input for ICSP and ICD operation.(3)
RB7/KBI3/
PGD
RB7 0 OUT DIG LATB<7> data output.
1 IN TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3 1 IN TTL Interrupt-on-pin change.
PGD x OUT DIG Serial execution data output for ICSP and ICD operation.(3)
x IN ST Serial execution data input for ICSP and ICD operation.(3)
TABLE 10-3: PORTB I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I/O I/O Type Description
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
I2C/SMB = I2C/SMBus input buffer, TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is
overridden for this option)
Note 1: Configuration on POR is determined by PBADEN Configuration bit. Pins are configured as analog inputs when
PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate pin assignment for CCP2 when CCP2MX = 0. Default assignment is RC1.
3: All other pin functions are disabled when ICSP™ or ICD operation is enabled.
4: 40/44-pin devices only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 56
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 56
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 53
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 53
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54
SPPCON(1) — — — — — — SPPOWN SPPEN 57
SPPCFG(1) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1: These registers are unimplemented on 28-pin devices.
© 2009 Microchip Technology Inc. DS39632E-page 119
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10.3 PORTC, TRISC and LATC
Registers
PORTC is a 7-bit wide, bidirectional port. The corresponding
Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The RC3 pin is not implemented in these devices.
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is primarily multiplexed with serial communication
modules, including the EUSART, MSSP module
and the USB module (Table 10-5). Except for RC4 and
RC5, PORTC uses Schmitt Trigger input buffers.
Pins RC4 and RC5 are multiplexed with the USB
module. Depending on the configuration of the module,
they can serve as the differential data lines for the onchip
USB transceiver, or the data inputs from an
external USB transceiver. Both RC4 and RC5 have
TTL input buffers instead of the Schmitt Trigger buffers
on the other pins.
Unlike other PORTC pins, RC4 and RC5 do not have
TRISC bits associated with them. As digital ports, they
can only function as digital inputs. When configured for
USB operation, the data direction is determined by the
configuration and status of the USB module at a given
time. If an external transceiver is used, RC4 and RC5
always function as inputs from the transceiver. If the
on-chip transceiver is used, the data direction is
determined by the operation being performed by the
module at that time.
When the external transceiver is enabled, RC2 also
serves as the output enable control to the transceiver.
Additional information on configuring USB options is
provided in Section 17.2.2.2 “External Transceiver”.
When enabling peripheral functions on PORTC pins
other than RC4 and RC5, care should be taken in defining
the TRIS bits. Some peripherals override the TRIS
bit to make a pin an output, while other peripherals
override the TRIS bit to make a pin an input. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3: INITIALIZING PORTC
Note: On a Power-on Reset, these pins, except
RC4 and RC5, are configured as digital
inputs. To use pins RC4 and RC5 as
digital inputs, the USB module must be
disabled (UCON<3> = 0) and the on-chip
USB transceiver must be disabled
(UCFG<3> = 1).
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 07h ; Value used to
; initialize data
; direction
MOVWF TRISC ; RC<5:0> as outputs
; RC<7:6> as inputs
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TABLE 10-5: PORTC I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RC0/T1OSO/
T13CKI
RC0 0 OUT DIG LATC<0> data output.
1 IN ST PORTC<0> data input.
T1OSO x OUT ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T13CKI 1 IN ST Timer1/Timer3 counter input.
RC1/T1OSI/
CCP2/UOE
RC1 0 OUT DIG LATC<1> data output.
1 IN ST PORTC<1> data input.
T1OSI x IN ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2(1) 0 OUT DIG CCP2 compare and PWM output; takes priority over port data.
1 IN ST CCP2 capture input.
UOE 0 OUT DIG External USB transceiver OE output.
RC2/CCP1/
P1A
RC2 0 OUT DIG LATC<2> data output.
1 IN ST PORTC<2> data input.
CCP1 0 OUT DIG ECCP1 compare and PWM output; takes priority over port data.
1 IN ST ECCP1 capture input.
P1A(3) 0 OUT DIG ECCP1 Enhanced PWM output, Channel A; takes priority over port
data. May be configured for tri-state during Enhanced PWM shutdown
events.
RC4/D-/VM RC4 —(2) IN TTL PORTC<4> data input; disabled when USB module or on-chip
transceiver are enabled.
D- —(2) OUT XCVR USB bus differential minus line output (internal transceiver).
—(2) IN XCVR USB bus differential minus line input (internal transceiver).
VM —(2) IN TTL External USB transceiver VM input.
RC5/D+/VP RC5 —(2) IN TTL PORTC<5> data input; disabled when USB module or on-chip
transceiver are enabled.
D+ —(2) OUT XCVR USB bus differential plus line output (internal transceiver).
—(2) IN XCVR USB bus differential plus line input (internal transceiver).
VP —(2) IN TTL External USB transceiver VP input.
RC6/TX/CK RC6 0 OUT DIG LATC<6> data output.
1 IN ST PORTC<6> data input.
TX 0 OUT DIG Asynchronous serial transmit data output (EUSART module); takes
priority over port data. User must configure as output.
CK 0 OUT DIG Synchronous serial clock output (EUSART module); takes priority
over port data.
1 IN ST Synchronous serial clock input (EUSART module).
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden
for this option)
Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).
2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
3: 40/44-pin devices only.
© 2009 Microchip Technology Inc. DS39632E-page 121
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TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
RC7/RX/DT/
SDO
RC7 0 OUT DIG LATC<7> data output.
1 IN ST PORTC<7> data input.
RX 1 IN ST Asynchronous serial receive data input (EUSART module).
DT 1 OUT DIG Synchronous serial data output (EUSART module); takes priority over
SPI and port data.
1 IN ST Synchronous serial data input (EUSART module). User must
configure as an input.
SDO 0 OUT DIG SPI data output (MSSP module); takes priority over port data.
TABLE 10-5: PORTC I/O SUMMARY (CONTINUED)
Pin Function TRIS
Setting I/O I/O Type Description
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, XCVR = USB transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden
for this option)
Note 1: Default pin assignment. Alternate pin assignment is RB3 (when CCP2MX = 0).
2: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is
determined by the USB configuration.
3: 40/44-pin devices only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTC RC7 RC6 RC5(1) RC4(1) — RC2 RC1 RC0 56
LATC LATC7 LATC6 — — — LATC2 LATC1 LATC0 56
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTC.
Note 1: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
PIC18F2455/2550/4455/4550
DS39632E-page 122 © 2009 Microchip Technology Inc.
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corresponding
Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Each of the PORTD pins has a weak internal pull-up. A
single control bit, RDPU (PORTE<7>), can turn on all
the pull-ups. This is performed by setting RDPU. The
weak pull-up is automatically turned off when the port
pin is configured as a digital output or as one of the
other multiplexed peripherals. The pull-ups are
disabled on a Power-on Reset. The PORTE register is
shown in Section 10.5 “PORTE, TRISE and LATE
Registers”.
Three of the PORTD pins are multiplexed with outputs,
P1B, P1C and P1D, of the Enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
PORTD can also be configured as an 8-bit wide
Streaming Parallel Port (SPP). In this mode, the input
buffers are TTL. For additional information on configuration
and uses of the SPP, see Section 18.0
“Streaming Parallel Port”.
EXAMPLE 10-4: INITIALIZING PORTD
Note: PORTD is only available on 40/44-pin
devices.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Note: When the Enhanced PWM mode is used
with either dual or quad outputs, the MSSP
functions of PORTD are automatically
disabled.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
© 2009 Microchip Technology Inc. DS39632E-page 123
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TABLE 10-7: PORTD I/O SUMMARY
Pin Function TRIS
Setting I/O I/O Type Description
RD0/SPP0 RD0 0 OUT DIG LATD<0> data output.
1 IN ST PORTD<0> data input.
SPP0 1 OUT DIG SPP<0> output data; takes priority over port data.
1 IN TTL SPP<0> input data.
RD1/SPP1 RD1 0 OUT DIG LATD<1> data output.
1 IN ST PORTD<1> data input.
SPP1 1 OUT DIG SPP<1> output data; takes priority over port data.
1 IN TTL SPP<1> input data.
RD2/SPP2 RD2 0 OUT DIG LATD<2> data output.
1 IN ST PORTD<2> data input.
SPP2 1 OUT DIG SPP<2> output data; takes priority over port data.
1 IN TTL SPP<2> input data.
RD3/SPP3 RD3 0 OUT DIG LATD<3> data output.
1 IN ST PORTD<3> data input.
SPP3 1 OUT DIG SPP<3> output data; takes priority over port data.
1 IN TTL SPP<3> input data.
RD4/SPP4 RD4 0 OUT DIG LATD<4> data output.
1 IN ST PORTD<4> data input.
SPP4 1 OUT DIG SPP<4> output data; takes priority over port data.
1 IN TTL SPP<4> input data.
RD5/SPP5/P1B RD5 0 OUT DIG LATD<5> data output
1 IN ST PORTD<5> data input
SPP5 1 OUT DIG SPP<5> output data; takes priority over port data.
1 IN TTL SPP<5> input data.
P1B 0 OUT DIG ECCP1 Enhanced PWM output, Channel B; takes priority over
port and SPP data.(1)
RD6/SPP6/P1C RD6 0 OUT DIG LATD<6> data output.
1 IN ST PORTD<6> data input.
SPP6 1 OUT DIG SPP<6> output data; takes priority over port data.
1 IN TTL SPP<6> input data.
P1C 0 OUT DIG ECCP1 Enhanced PWM output, Channel C; takes priority over
port and SPP data.(1)
RD7/SPP7/P1D RD7 0 OUT DIG LATD<7> data output.
1 IN ST PORTD<7> data input.
SPP7 1 OUT DIG SPP<7> output data; takes priority over port data.
1 IN TTL SPP<7> input data.
P1D 0 OUT DIG ECCP1 Enhanced PWM output, Channel D; takes priority over
port and SPP data.(1)
Legend: OUT = Output, IN = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input
Note 1: May be configured for tri-state during Enhanced PWM shutdown events.
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TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD(3) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 56
LATD(3) LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 56
TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56
PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56
CCP1CON P1M1(3) P1M0(3) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55
SPPCON(3) — — — — — — SPPOWN SPPEN 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.
© 2009 Microchip Technology Inc. DS39632E-page 125
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10.5 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2455/2550/4455/
4550 device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP
and RE2/AN7/OESPP) are individually configurable as
inputs or outputs. These pins have Schmitt Trigger
input buffers. When selected as an analog input, these
pins will read as ‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
In addition to port data, the PORTE register
(Register 10-1) also contains the RDPU control bit
(PORTE<7>); this enables or disables the weak
pull-ups on PORTD.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE Configuration
bit. When selected as a port pin (MCLRE = 0), it
functions as a digital input only pin; as such, it does not
have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear input.
In either configuration, RE3 also functions as the
programming voltage input during programming.
EXAMPLE 10-5: INITIALIZING PORTE
10.5.1 PORTE IN 28-PIN DEVICES
For 28-pin devices, PORTE is only available when Master
Clear functionality is disabled (MCLRE = 0). In these
cases, PORTE is a single bit, input only port comprised
of RE3 only. The pin operates as previously described.
Note: On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Note: On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 0Ah ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 03h ; Value used to
; initialize data
; direction
MOVLW 07h ; Turn off
MOVWF CMCON ; comparators
MOVWF TRISC ; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
REGISTER 10-1: PORTE REGISTER
R/W-0 U-0 U-0 U-0 R/W-x R/W-0 R/W-0 R/W-0
RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual port latch values
0 = All PORTD pull-ups are disabled
bit 6-4 Unimplemented: Read as ‘0’
bit 3-0 RE3:RE0: PORTE Data Input bits(1,2,3)
Note 1: implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: Unimplemented in 28-pin devices; read as ‘0’.
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DS39632E-page 126 © 2009 Microchip Technology Inc.
TABLE 10-9: PORTE I/O SUMMARY
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Function TRIS
Setting I/O I/O Type Description
RE0/AN5/
CK1SPP
RE0 0 OUT DIG LATE<0> data output; not affected by analog input.
1 IN ST PORTE<0> data input; disabled when analog input enabled.
AN5 1 IN ANA A/D Input Channel 5; default configuration on POR.
CK1SPP 0 OUT DIG SPP clock 1 output (SPP enabled).
RE1/AN6/
CK2SPP
RE1 0 OUT DIG LATE<1> data output; not affected by analog input.
1 IN ST PORTE<1> data input; disabled when analog input enabled.
AN6 1 IN ANA A/D Input Channel 6; default configuration on POR.
CK2SPP 0 OUT DIG SPP clock 2 output (SPP enabled).
RE2/AN7/
OESPP
RE2 0 OUT DIG LATE<2> data output; not affected by analog input.
1 IN ST PORTE<2> data input; disabled when analog input enabled.
AN7 1 IN ANA A/D Input Channel 7; default configuration on POR.
OESPP 0 OUT DIG SPP enable output (SPP enabled).
MCLR/VPP/
RE3
MCLR —(1) IN ST External Master Clear input; enabled when MCLRE Configuration bit
is set.
VPP — (1) IN ANA High-voltage detection, used for ICSP™ mode entry detection.
Always available regardless of pin mode.
RE3 — (1) IN ST PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input
Note 1: RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56
LATE(3) — — — — — LATE2 LATE1 LATE0 56
TRISE(3) — — — — — TRISE2 TRISE1 TRISE0 56
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55
SPPCON(3) — — — — — — SPPOWN SPPEN 57
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers or bits are unimplemented on 28-pin devices.
© 2009 Microchip Technology Inc. DS39632E-page 127
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11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or counter
in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt on overflow
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 Prescale value
110 = 1:128 Prescale value
101 = 1:64 Prescale value
100 = 1:32 Prescale value
011 = 1:16 Prescale value
010 = 1:8 Prescale value
001 = 1:4 Prescale value
000 = 1:2 Prescale value
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11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected by clearing the T0CS bit
(T0CON<5>). In Timer mode, the module increments
on every clock by default unless a different prescaler
value is selected (see Section 11.3 “Prescaler”). If
the TMR0 register is written to, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In Counter mode, Timer0 increments either on
every rising or falling edge of pin RA4/T0CKI/C1OUT/
RCV. The incrementing edge is determined by the
Timer0 Source Edge Select bit, T0SE (T0CON<4>);
clearing this bit selects the rising edge. Restrictions on
the external clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor
writable (refer to Figure 11-2). TMR0H is updated with
the contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
T0CKI pin
T0SE
0
1
1
0
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
PSA Internal Data Bus
T0PS2:T0PS0
Set
TMR0IF
on Overflow
3 8
8
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
T0CKI pin
T0SE
0
1
1
0
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS2:T0PS0
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
8
8
8
Read TMR0L
Write TMR0L
8
© 2009 Microchip Technology Inc. DS39632E-page 129
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11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256, in power-of-2 increments, are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0,etc.) clear the prescaler count.
11.3.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before reenabling
the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TMR0L Timer0 Register Low Byte 54
TMR0H Timer0 Register High Byte 54
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 53
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 54
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.
Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.
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NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 131
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12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power-managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
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12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI/UOE and
RC0/T1OSO/T13CKI pins become inputs. This means
the values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 12-1: TIMER1 BLOCK DIAGRAM
FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L TMR1
Clear TMR1 High Byte
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Set
TMR1IF
on Overflow
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
© 2009 Microchip Technology Inc. DS39632E-page 133
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12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will
continue to run during all power-managed modes. The
circuit for a typical LP oscillator is shown in Figure 12-3.
Table 12-1 shows the capacitor selection for the Timer1
oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3: EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR(2,3,4)
12.3.1 USING TIMER1 AS A CLOCK
SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode. Both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power-Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
12.3.2 LOW-POWER TIMER1 OPTION
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC Configuration bit is set, the Timer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
level. Power consumption for a particular mode is relatively
constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
As the low-power Timer1 mode tends to be more
sensitive to interference, high noise environments may
cause some oscillator instability. The low-power option
is, therefore, best suited for low noise applications
where power conservation is an important design
consideration.
Note: See the notes with Table 12-1 for additional
information about capacitor selection.
C1
C2
XTAL
PIC18FXXXX
T1OSI
T1OSO
32.768 kHz
27 pF
27 pF
Osc Type Freq C1 C2
LP 32 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
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12.3.3 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator
(such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 12-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
12.5 Resetting Timer1 Using the CCP
Special Event Trigger
If either of the CCP modules is configured in Compare
mode to generate a Special Event Trigger
(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011),
this signal will reset Timer1. The trigger from CCP2 will
also start an A/D conversion if the A/D module is
enabled (see Section 15.3.4 “Special Event Trigger”
for more information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
Special Event Trigger, the write operation will take
precedence.
12.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one. Additional counters for minutes and hours are
incremented as the previous counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to preload
it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The Special Event Triggers from the CCP2
module will not set the TMR1IF interrupt
flag bit (PIR1<0>).
© 2009 Microchip Technology Inc. DS39632E-page 135
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12.7 Considerations in Asynchronous
Counter Mode
Following a Timer1 interrupt and an update to the
TMR1 registers, the Timer1 module uses a falling edge
on its clock source to trigger the next register update on
the rising edge. If the update is completed after the
clock input has fallen, the next rising edge will not be
counted.
If the application can reliably update TMR1 before the
timer input goes low, no additional action is needed.
Otherwise, an adjusted update can be performed
following a later Timer1 increment. This can be done
by monitoring TMR1L within the interrupt routine until it
increments, and then updating the TMR1H:TMR1L register
pair while the clock is low, or one-half of the period
of the clock source. Assuming that Timer1 is being
used as a Real-Time Clock, the clock source is a
32.768 kHz crystal oscillator; in this case, one-half
period of the clock is 15.25 μs.
The Real-Time Clock application code in Example 12-1
shows a typical ISR for Timer1, as well as the optional
code required if the update cannot be done reliably
within the required interval.
EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
; Insert the next 4 lines of code when TMR1
; can not be reliably updated before clock pulse goes low
BTFSC TMR1L,0 ; wait for TMR1L to become clear
BRA $-2 ; (may already be clear)
BTFSS TMR1L,0 ; wait for TMR1L to become set
BRA $-2 ; TMR1 has just incremented
; If TMR1 update can be completed before clock pulse goes low
; Start ISR here
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done
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TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
TMR1L Timer1 Register Low Byte 54
TMR1H TImer1 Register High Byte 54
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2009 Microchip Technology Inc. DS39632E-page 137
PIC18F2455/2550/4455/4550
13.0 TIMER2 MODULE
The Timer2 module timer incorporates the following
features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2 to PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
(Register 13-1) which enables or disables the timer and
configures the prescaler and postscaler. Timer2 can be
shut off by clearing control bit, TMR2ON (T2CON<2>),
to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 13-1.
13.1 Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 2-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
16 prescale options. These are selected by the prescaler
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
value of TMR2 is compared to that of the Period register,
PR2, on each clock cycle. When the two values match,
the comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/postscaler
(see Section 13.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
PIC18F2455/2550/4455/4550
DS39632E-page 138 © 2009 Microchip Technology Inc.
13.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) provides
the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
13.3 TMR2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 19.0
“Master Synchronous Serial Port (MSSP) Module”.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
Set TMR2IF
Internal Data Bus
8
Reset
TMR2/PR2
8 8
(to PWM or MSSP)
Match
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
TMR2 Timer2 Register 54
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54
PR2 Timer2 Period Register 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2009 Microchip Technology Inc. DS39632E-page 139
PIC18F2455/2550/4455/4550
14.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt on overflow
• Module Reset on CCP Special Event Trigger
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules (see Section 15.1.1
“CCP Modules and Timer Resources” for more
information).
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RD16: 16-Bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for both CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for both CCP modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
PIC18F2455/2550/4455/4550
DS39632E-page 140 © 2009 Microchip Technology Inc.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI/UOE and RC0/
T1OSO/T13CKI pins become inputs when the Timer1
oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 14-1: TIMER3 BLOCK DIAGRAM
FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L
Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
Timer1 Clock Input
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1/CCP2 Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 Clock Input
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
© 2009 Microchip Technology Inc. DS39632E-page 141
PIC18F2455/2550/4455/4550
14.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the CCP
Special Event Trigger
If the CCP2 module is configured to generate a
Special Event Trigger in Compare mode
(CCP2M3:CCP2M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information.).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The Special Event Triggers from the CCP2
module will not set the TMR3IF interrupt
flag bit (PIR2<1>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
TMR3L Timer3 Register Low Byte 55
TMR3H Timer3 Register High Byte 55
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
PIC18F2455/2550/4455/4550
DS39632E-page 142 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 143
PIC18F2455/2550/4455/4550
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F2455/2550/4455/4550 devices all have two
CCP (Capture/Compare/PWM) modules. Each module
contains a 16-bit register, which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules (CCP1
and CCP2) operate as described in this chapter. In
40/44-pin devices, CCP1 is implemented as an
Enhanced CCP module, with standard Capture and
Compare modes and Enhanced PWM modes. The
ECCP implementation is discussed in Section 16.0
“Enhanced Capture/Compare/PWM (ECCP) Module”.
The Capture and Compare operations described in this
chapter apply to all standard and Enhanced CCP
modules.
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to generically
by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the
module control register regardless of whether
the CCP module is a standard or Enhanced
implementation.
REGISTER 15-1: CCPxCON: STANDARD CCPx CONTROL REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—(1) —(1) DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’(1)
bit 5-4 DCxB1:DCxB0: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs of the duty
cycle are found in CCPR1L.
bit 3-0 CCPxM3:CCPxM0: CCPx Module Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode: toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit
is set)
1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit
is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin
reflects I/O state)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on CCPx match
(CCPxIF bit is set)
11xx = PWM mode
Note 1: These bits are not implemented on 28-pin devices and are read as ‘0’.
PIC18F2455/2550/4455/4550
DS39632E-page 144 © 2009 Microchip Technology Inc.
15.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
15.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 15-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer to CCP enable bits in the
T3CON register (Register 14-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time. The
interactions between the two modules are summarized in
Figure 15-2. In Timer1 in Asynchronous Counter mode,
the capture operation will not work.
15.1.2 CCP2 PIN ASSIGNMENT
The pin assignment for CCP2 (capture input, compare
and PWM output) can change, based on device configuration.
The CCP2MX Configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the Configuration bit
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not
automatically change any requirements for configuring
the port pin. Users must always verify that the appropriate
TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP/ECCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare Capture CCP1 be configured for the Special Event Trigger to reset TMR1 or TMR3 (depending
upon which time base is used). Operation of CCP2 could be affected if it is using the
same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM(1) None
Compare PWM(1) None
PWM(1) Capture None
PWM(1) Compare None
PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and Enhanced PWM operation.
© 2009 Microchip Technology Inc. DS39632E-page 145
PIC18F2455/2550/4455/4550
15.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
15.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
15.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).
15.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false
interrupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
15.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCPxM3:CCPxM0).
Whenever the CCP module is turned off or Capture
mode is disabled, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1: CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
CLRF CCP2CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP2CON ; Load CCP2CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set CCP2IF
TMR3
Enable
CCP2CON<3:0>
CCP2 pin
Prescaler
÷ 1, 4, 16
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
TMR3H TMR3L
and
Edge Detect
4
4
4
PIC18F2455/2550/4455/4550
DS39632E-page 146 © 2009 Microchip Technology Inc.
15.3 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
15.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
15.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled, and the CCPxIE bit is set.
15.3.4 SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
Period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
S Q
R
Output
Logic
Special Event Trigger
Set CCP1IF
CCP1 pin
TRIS
CCP1CON<3:0>
Output Enable
TMR3H TMR3L
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
Set CCP2IF
1
0
Compare
4
(Timer1/Timer3 Reset)
S Q
R
Output
Logic
Special Event Trigger
CCP2 pin
TRIS
CCP2CON<3:0>
4 Output Enable
(Timer1/Timer3 Reset, A/D Trigger)
Match
Compare
Match
© 2009 Microchip Technology Inc. DS39632E-page 147
PIC18F2455/2550/4455/4550
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
RCON IPEN SBOREN(1) — RI TO PD POR BOR 54
PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56
TMR1L Timer1 Register Low Byte 54
TMR1H Timer1 Register High Byte 54
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54
TMR3H Timer3 Register High Byte 55
TMR3L Timer3 Register Low Byte 55
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55
CCPR1L Capture/Compare/PWM Register 1 Low Byte 55
CCPR1H Capture/Compare/PWM Register 1 High Byte 55
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55
CCPR2L Capture/Compare/PWM Register 2 Low Byte 55
CCPR2H Capture/Compare/PWM Register 2 High Byte 55
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632E-page 148 © 2009 Microchip Technology Inc.
15.4 PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.4
“Setup for PWM Operation”.
FIGURE 15-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-4: PWM OUTPUT
15.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
15.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> bits contain
the two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 15-2:
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.
Note: Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending
on device configuration) to the default low
level. This is not the PORTB or PORTC
I/O data latch.
CCPRxL
CCPRxH (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R Q
S
Duty Cycle Registers CCPxCON<5:4>
Clear Timer,
CCPx pin and
latch D.C.
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
CCPx
Corresponding
TRIS bit
Output
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
© 2009 Microchip Technology Inc. DS39632E-page 149
PIC18F2455/2550/4455/4550
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCPx pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 15-3:
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
15.4.3 PWM AUTO-SHUTDOWN
(CCP1 ONLY)
The PWM auto-shutdown features of the Enhanced CCP
module are also available to CCP1 in 28-pin devices. The
operation of this feature is discussed in detail in
Section 16.4.7 “Enhanced PWM Auto-Shutdown”.
Auto-shutdown features are not available for CCP2.
15.4.4 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCPx module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
3. Make the CCPx pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCPx module for PWM operation.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCPx pin will not be
cleared.
FOSC
FPWM
⎝---------------⎠
log⎛ ⎞
= -------l--o---g----(--2----)-------bits PWM Resolution (max)
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
PIC18F2455/2550/4455/4550
DS39632E-page 150 © 2009 Microchip Technology Inc.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
RCON IPEN SBOREN(1) — RI TO PD POR BOR 54
PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56
TMR2 Timer2 Register 54
PR2 Timer2 Period Register 54
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54
CCPR1L Capture/Compare/PWM Register 1 Low Byte 55
CCPR1H Capture/Compare/PWM Register 1 High Byte 55
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55
CCPR2L Capture/Compare/PWM Register 2 Low Byte 55
CCPR2H Capture/Compare/PWM Register 2 High Byte 55
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 55
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 55
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2009 Microchip Technology Inc. DS39632E-page 151
PIC18F2455/2550/4455/4550
16.0 ENHANCED
CAPTURE/COMPARE/PWM
(ECCP) MODULE
In 28-pin devices, CCP1 is implemented as a standard
CCP module with Enhanced PWM capabilities. These
include the provision for 2 or 4 output channels,
user-selectable polarity, dead-band control and
automatic shutdown and restart. The Enhanced
features are discussed in detail in Section 16.4
“Enhanced PWM Mode”. Capture, Compare and
single output PWM functions of the ECCP module are
the same as described for the standard CCP module.
The control register for the Enhanced CCP module is
shown in Register 16-1. It differs from the CCPxCON
registers in 28-pin devices in that the two Most Significant
bits are implemented to control PWM functionality.
Note: The ECCP module is implemented only in
40/44-pin devices.
REGISTER 16-1: CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B1:DC1B0: PWM Duty Cycle Bit 1 and Bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found
in CCPR1L.
bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (CCP1 resets TMR1 or TMR3, sets CCP1IF bit)
1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low
PIC18F2455/2550/4455/4550
DS39632E-page 152 © 2009 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register, the ECCP module has
two additional registers associated with Enhanced
PWM operation and auto-shutdown features. They are:
• ECCP1DEL (PWM Dead-Band Delay)
• ECCP1AS (ECCP Auto-Shutdown Control)
16.1 ECCP Outputs and Configuration
The Enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the CCP operating
mode selected. The pin assignments are summarized
in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
P1M1:P1M0 and CCP1M3:CCP1M0 bits. The
appropriate TRISC and TRISD direction bits for the port
pins must also be set as outputs.
16.1.1 ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP module can
utilize Timers 1, 2 or 3, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 is
available for modules in PWM mode. Interactions
between the standard and Enhanced CCP modules are
identical to those described for standard CCP modules.
Additional details on timer resources are provided in
Section 15.1.1 “CCP Modules and Timer
Resources”.
16.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare
Mode”.
16.2.1 SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP resets the
TMR1 or TMR3 register pair, depending on which timer
resource is currently selected. This allows the
CCPR1H:CCPR1L registers to effectively be a 16-bit
programmable period register for Timer1 or Timer3.
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode, as in Table 16-1.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES
Note: When setting up single output PWM
operations, users are free to use either of
the processes described in Section 15.4.4
“Setup for PWM Operation” or
Section 16.4.9 “Setup for PWM Operation”.
The latter is more generic but will
work for either single or multi-output PWM.
ECCP Mode CCP1CON
Configuration RC2 RD5 RD6 RD7
All PIC18F4455/4550 devices:
Compatible CCP 00xx 11xx CCP1 RD5/SPP5 RD6/SPP6 RD7/SPP7
Dual PWM 10xx 11xx P1A P1B RD6/SPP6 RD7/SPP7
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
© 2009 Microchip Technology Inc. DS39632E-page 153
PIC18F2455/2550/4455/4550
16.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applications.
The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the PWM Dead-Band Delay register, ECCP1DEL,
which is loaded at either the duty cycle boundary or the
boundary period (whichever comes first). Because of
the buffering, the module waits until the assigned timer
resets instead of starting immediately. This means that
Enhanced PWM waveforms do not exactly match the
standard PWM waveforms, but are instead offset by
one full instruction cycle (4 TOSC).
As before, the user must manually configure the
appropriate TRIS bits for output.
16.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation:
EQUATION 16-1:
PWM frequency is defined as 1/ [PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Note: The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R Q
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
set CCP1 pin and
latch D.C.
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
base.
TRISD<4>
CCP1/P1A
TRISD<5>
P1B
TRISD<6>
TRISD<7>
P1D
Output
Controller
P1M1:P1M0
2
CCP1M3:CCP1M0
4
ECCP1DEL
CCP1/P1A
P1B
P1C
P1D
P1C
PIC18F2455/2550/4455/4550
DS39632E-page 154 © 2009 Microchip Technology Inc.
16.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation.
EQUATION 16-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
EQUATION 16-3:
16.4.3 PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2 and
Figure 16-3.
TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4> •
TOSC • (TMR2 Prescale Value)
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
( )
PWM Resolution (max) =
FOSC
FPWM
log
log(2)
bits
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
© 2009 Microchip Technology Inc. DS39632E-page 155
PIC18F2455/2550/4455/4550
FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
SIGNAL
PR2 + 1
CCP1CON
<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
0
Period
00
10
01
11
SIGNAL
PR2 + 1
CCP1CON
<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (ECCP1DEL<6:0>)
Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”).
PIC18F2455/2550/4455/4550
DS39632E-page 156 © 2009 Microchip Technology Inc.
16.4.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary
PWM output signal is output on the P1B pin
(Figure 16-4). This mode can be used for half-bridge
applications, as shown in Figure 16-5, or for full-bridge
applications where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
PDC6:PDC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4: HALF-BRIDGE PWM
OUTPUT
FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Period
Duty Cycle
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
PIC18FX455/X550
P1A
P1B
FET
Driver
FET
Driver
V+
VLoad
+
V-
+
VFET
Driver
FET
Driver
V+
VLoad
FET
Driver
FET
Driver
PIC18FX455/X550
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
© 2009 Microchip Technology Inc. DS39632E-page 157
PIC18F2455/2550/4455/4550
16.4.5 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 16-6.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2>, PORTD<5>, PORTD<6> and
PORTD<7> data latches. The TRISC<2>, TRISD<5>,
TRISD<6> and TRISD<7> bits must be cleared to
make the P1A, P1B, P1C and P1D pins outputs.
FIGURE 16-6: FULL-BRIDGE PWM OUTPUT
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forward Mode
(1)
Period
Duty Cycle
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
PIC18F2455/2550/4455/4550
DS39632E-page 158 © 2009 Microchip Technology Inc.
FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION
16.4.5.1 Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows the user to control the
forward/reverse direction. When the application firmware
changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of (4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16,
depending on the value of the T2CKPS1:T2CKPS0 bits
(T2CON<1:0>). During the interval from the switch of
the unmodulated outputs to the beginning of the next
period, the modulated outputs (P1B and P1D) remain
inactive. This relationship is shown in Figure 16-8.
Note that in the Full-Bridge Output mode, the ECCP
module does not provide any dead-band delay. In general,
since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
Figure 16-9 shows an example where the PWM direction
changes from forward to reverse at a near 100%
duty cycle. At time t1, the outputs, P1A and P1D,
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices, QC and QD,
(see Figure 16-7) for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for a PWM period before
changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
P1A
P1C
FET
Driver
FET
Driver
V+
VLoad
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
PIC18FX455/X550 QC
© 2009 Microchip Technology Inc. DS39632E-page 159
PIC18F2455/2550/4455/4550
FIGURE 16-8: PWM DIRECTION CHANGE
FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
DC
Period(1)
SIGNAL
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
Period
(Note 2)
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
DC
Forward Period Reverse Period
P1A(1)
tON
(2)
tOFF
(3)
t = tOFF – tON
(2, 3)
P1B(1)
P1C(1)
P1D(1)
External Switch D(1)
Potential
Shoot-Through Current(1)
Note 1: All signals are shown as active-high.
2: tON is the turn-on delay of power switch QC and its driver.
3: tOFF is the turn-off delay of power switch QD and its driver.
External Switch C(1)
t1
DC
DC
PIC18F2455/2550/4455/4550
DS39632E-page 160 © 2009 Microchip Technology Inc.
16.4.6 PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on and the other
turned off), both switches may be on for a short period of
time until one switch completely turns off. During this
brief interval, a very high current (shoot-through current)
may flow through both power switches, shorting the
bridge supply. To avoid this potentially destructive
shoot-through current from flowing during switching,
turning on either of the power switches is normally
delayed to allow the other switch to completely turn off.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid
shoot-through current from destroying the bridge
power switches. The delay occurs at the signal transition
from the non-active state to the active state. See
Figure 16-4 for illustration. Bits PDC6:PDC0 of the
ECCP1DEL register (Register 16-2) set the delay
period in terms of microcontroller instruction cycles
(TCY or 4 TOSC). These bits are not available on 28-pin
devices, as the standard CCP module does not support
half-bridge operation.
16.4.7 ENHANCED PWM AUTO-SHUTDOWN
When ECCP is programmed for any of the Enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the Enhanced PWM output pins into a defined shutdown
state when a shutdown event occurs.
A shutdown event can be caused by either of the
comparator modules, a low level on the
RB0/AN12/INT0/FLT0/SDI/SDA pin, or any combination
of these three sources. The comparators may be used to
monitor a voltage input proportional to a current being
monitored in the bridge circuit. If the voltage exceeds a
threshold, the comparator switches state and triggers a
shutdown. Alternatively, a digital signal on the INT0 pin
can also trigger a shutdown. The auto-shutdown feature
can be disabled by not selecting any auto-shutdown
sources. The auto-shutdown sources to be used are
selected using the ECCPAS2:ECCPAS0 bits (bits<6:4>
of the ECCP1AS register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states,
specified by the PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits (ECCP1AS3:ECCP1AS0). Each
pin pair (P1A/P1C and P1B/P1D) may be set to drive
high, drive low or be tri-stated (not driving). The
ECCPASE bit (ECCP1AS<7>) is also set to hold the
Enhanced PWM outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
Note: Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
REGISTER 16-2: ECCP1DEL: PWM DEAD-BAND DELAY REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;
the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC6:PDC0: PWM Delay Count bits(1)
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for a PWM
signal to transition to active.
Note 1: Reserved on 28-pin devices; maintain these bits clear.
© 2009 Microchip Technology Inc. DS39632E-page 161
PIC18F2455/2550/4455/4550
REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits
111 = FLT0 or Comparator 1 or Comparator 2
110 = FLT0 or Comparator 2
101 = FLT0 or Comparator 1
100 = FLT0
011 = Either Comparator 1 or 2
010 = Comparator 2 output
001 = Comparator 1 output
000 = Auto-shutdown is disabled
bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits
1x = Pins A and C tri-state (40/44-pin devices)
01 = Drive Pins A and C to ‘1’
00 = Drive Pins A and C to ‘0’
bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)
1x = Pins B and D tri-state
01 = Drive Pins B and D to ‘1’
00 = Drive Pins B and D to ‘0’
Note 1: Reserved on 28-pin devices; maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632E-page 162 © 2009 Microchip Technology Inc.
16.4.7.1 Auto-Shutdown and Auto-Restart
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
ECCP1DEL register (ECCP1DEL<7>).
In Shutdown mode with PRSEN = 1 (Figure 16-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condition
clears, the ECCP1ASE bit is cleared. If PRSEN = 0
(Figure 16-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared by
firmware. Once ECCPASE is cleared, the Enhanced
PWM will resume at the beginning of the next PWM
period.
Independent of the PRSEN bit setting, if the
auto-shutdown source is one of the comparators, the
shutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
16.4.8 START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pull-up
and/or pull-down resistors on the PWM output pins. When
the microcontroller is released from Reset, all of the I/O
pins are in the high-impedance state. The external circuits
must keep the power switch devices in the OFF state until
the microcontroller drives the I/O pins with the proper
signal levels or activates the PWM output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configuration
while the PWM pins are configured as outputs is
not recommended, since it may result in damage to the
application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the application
circuit. The ECCP module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The completion
of a full PWM cycle is indicated by the TMR2IF
bit being set as the second PWM period begins.
FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Shutdown
PWM
ECCPASE bit
Activity
Event
PWM Period PWM Period PWM Period
Duty Cycle
Dead Time
Duty Cycle
Dead Time
Duty Cycle
Dead Time
Shutdown
PWM
ECCPASE bit
Activity
Event
PWM Period PWM Period PWM Period
ECCPASE
Cleared by Firmware
Duty Cycle
Dead Time
Duty Cycle
Dead Time Dead Time
Duty Cycle
© 2009 Microchip Technology Inc. DS39632E-page 163
PIC18F2455/2550/4455/4550
16.4.9 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRIS bits.
2. Set the PWM period by loading the PR2 register.
3. If auto-shutdown is required, do the following:
• Disable auto-shutdown (ECCPASE = 0)
• Configure source (FLT0, Comparator 1 or
Comparator 2)
• Wait for non-shutdown condition
4. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
5. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
6. For Half-Bridge Output mode, set the
dead-band delay by loading ECCP1DEL<6:0>
with the appropriate value.
7. If auto-shutdown operation is required, load the
ECCP1AS register:
• Select the auto-shutdown sources using the
ECCPAS2:ECCPAS0 bits.
• Select the shutdown states of the PWM
output pins using the PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCP1AS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
8. If auto-restart operation is required, set the
PRSEN bit (ECCP1DEL<7>).
9. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
10. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMRx overflows (TMRxIF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRIS
bits.
• Clear the ECCPASE bit (ECCP1AS<7>).
16.4.10 OPERATION IN POWER-MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will continue
to drive that value. When the device wakes up, it will
continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC and
the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2. Other power-managed
mode clocks will most likely be different than the
primary clock frequency.
16.4.10.1 Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the power-managed RC_RUN
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source, which may have a different clock
frequency than the primary clock.
See the previous section for additional details.
16.4.11 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F2455/2550/4455/4550
DS39632E-page 164 © 2009 Microchip Technology Inc.
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
RCON IPEN SBOREN(1) — RI TO PD POR BOR 54
IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56
TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56
TMR1L Timer1 Register Low Byte 54
TMR1H Timer1 Register High Byte 54
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 54
TMR2 Timer2 Module Register 54
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 54
PR2 Timer2 Period Register 54
TMR3L Timer3 Register Low Byte 55
TMR3H Timer3 Register High Byte 55
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 55
CCPR1L Capture/Compare/PWM Register 1 (LSB) 55
CCPR1H Capture/Compare/PWM Register 1 (MSB) 55
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 55
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 55
ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
2: These bits or registers are unimplemented in 28-pin devices; always maintain these bits clear.
© 2009 Microchip Technology Inc. DS39632E-page 165
PIC18F2455/2550/4455/4550
17.0 UNIVERSAL SERIAL BUS
(USB)
This section describes the details of the USB
peripheral. Because of the very specific nature of the
module, knowledge of USB is expected. Some
high-level USB information is provided in
Section 17.10 “Overview of USB” only for application
design reference. Designers are encouraged to refer to
the official specification published by the USB Implementers
Forum (USB-IF) for the latest information.
USB specification Revision 2.0 is the most current
specification at the time of publication of this document.
17.1 Overview of the USB Peripheral
The PIC18FX455/X550 device family contains a
full-speed and low-speed compatible USB Serial Interface
Engine (SIE) that allows fast communication
between any USB host and the PIC® microcontroller.
The SIE can be interfaced directly to the USB, utilizing
the internal transceiver, or it can be connected through
an external transceiver. An internal 3.3V regulator is
also available to power the internal transceiver in 5V
applications.
Some special hardware features have been included to
improve performance. Dual port memory in the
device’s data memory space (USB RAM) has been
supplied to share direct memory access between the
microcontroller core and the SIE. Buffer descriptors are
also provided, allowing users to freely program endpoint
memory usage within the USB RAM space. A
Streaming Parallel Port has been provided to support
the uninterrupted transfer of large volumes of data,
such as isochronous data, to external memory buffers.
Figure 17-1 presents a general overview of the USB
peripheral and its features.
FIGURE 17-1: USB PERIPHERAL AND OPTIONS
UOE(1)
1 Kbyte
USB RAM
USB
SIE
USB Control and VM(1)
VP(1)
RCV(1)
VMO(1)
VPO(1)
Transceiver
External
Transceiver
P
P
EN
3.3V Regulator
D+
DInternal
Pull-ups
UOE
VUSB External 3.3V
Supply(3)
FSEN
UPUEN
UTRDIS
USB Clock from the
Oscillator Module
VREGEN
Optional
External
Pull-ups(2)
(Full (Low
PIC18FX455/X550 Family
SPP7:SPP0
USB Bus
USB Bus
FS
Speed) Speed)
Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).
2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.
3: Do not enable the internal regulator when using an external 3.3V supply.
Configuration
CK1SPP
CK2SPP
CSSPP
OESPP
PIC18F2455/2550/4455/4550
DS39632E-page 166 © 2009 Microchip Technology Inc.
17.2 USB Status and Control
The operation of the USB module is configured and
managed through three control registers. In addition, a
total of 22 registers are used to manage the actual USB
transactions. The registers are:
• USB Control register (UCON)
• USB Configuration register (UCFG)
• USB Transfer Status register (USTAT)
• USB Device Address register (UADDR)
• Frame Number registers (UFRMH:UFRML)
• Endpoint Enable registers 0 through 15 (UEPn)
17.2.1 USB CONTROL REGISTER (UCON)
The USB Control register (Register 17-1) contains bits
needed to control the module behavior during transfers.
The register contains bits that control the following:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend mode
• Packet Transfer Disable
In addition, the USB Control register contains a status bit,
SE0 (UCON<5>), which is used to indicate the occurrence
of a single-ended zero on the bus. When the USB
module is enabled, this bit should be monitored to determine
whether the differential data lines have come out of
a single-ended zero condition. This helps to differentiate
the initial power-up state from the USB Reset signal.
The overall operation of the USB module is controlled by
the USBEN bit (UCON<3>). Setting this bit activates the
module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. This bit also activates the on-chip
voltage regulator (if the VREGEN Configuration bit is
set) and connects internal pull-up resistors, if they are
enabled. Thus, this bit can be used as a soft
attach/detach to the USB. Although all status and control
bits are ignored when this bit is clear, the module needs
to be fully preconfigured prior to setting this bit.
Note: When disabling the USB module, make
sure the SUSPND bit (UCON<1>) is clear
prior to clearing the USBEN bit. Clearing
the USBEN bit when the module is in the
suspended state may prevent the module
from fully powering down.
REGISTER 17-1: UCON: USB CONTROL REGISTER
U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
bit 7 bit 0
Legend: C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
bit 0 Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc. DS39632E-page 167
PIC18F2455/2550/4455/4550
The PPBRST bit (UCON<6>) controls the Reset status
when Double-Buffering mode (ping-pong buffering) is
used. When the PPBRST bit is set, all Ping-Pong Buffer
Pointers are set to the Even buffers. PPBRST has
to be cleared by firmware. This bit is ignored in buffering
modes not using ping-pong buffering.
The PKTDIS bit (UCON<4>) is a flag indicating that the
SIE has disabled packet transmission and reception.
This bit is set by the SIE when a SETUP token is
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register’s FIFO buffer.
The RESUME bit (UCON<2>) allows the peripheral to
perform a remote wake-up by executing Resume
signaling. To generate a valid remote wake-up,
firmware must set RESUME for 10 ms and then clear
the bit. For more information on Resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0
specification.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry (i.e., voltage regulator) in a
low-power mode. The input clock to the SIE is also
disabled. This bit should be set by the software in
response to an IDLEIF interrupt. It should be reset by
the microcontroller firmware after an ACTVIF interrupt
is observed. When this bit is active, the device remains
attached to the bus but the transceiver outputs remain
Idle. The voltage on the VUSB pin may vary depending
on the value of this bit. Setting this bit before a IDLEIF
request will result in unpredictable bus behavior.
17.2.2 USB CONFIGURATION REGISTER
(UCFG)
Prior to communicating over USB, the module’s
associated internal and/or external hardware must be
configured. Most of the configuration is performed with
the UCFG register (Register 17-2). The separate USB
voltage regulator (see Section 17.2.2.8 “Internal
Regulator”) is controlled through the Configuration
registers.
The UFCG register contains most of the bits that
control the system level behavior of the USB module.
These include:
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage
The UCFG register also contains two bits which aid in
module testing, debugging and USB certifications.
These bits control output enable state monitoring and
eye pattern generation.
17.2.2.1 Internal Transceiver
The USB peripheral has a built-in, USB 2.0, full-speed
and low-speed compliant transceiver, internally connected
to the SIE. This feature is useful for low-cost
single chip applications. The UTRDIS bit (UCFG<3>)
controls the transceiver; it is enabled by default
(UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
transceiver speed; setting the bit enables full-speed
operation.
The on-chip USB pull-up resistors are controlled by the
UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The USB specification requires 3.3V operation for
communications; however, the rest of the chip may be
running at a higher voltage. Thus, the transceiver is
supplied power from a separate source, VUSB.
17.2.2.2 External Transceiver
This module provides support for use with an off-chip
transceiver. The off-chip transceiver is intended for
applications where physical conditions dictate the
location of the transceiver to be away from the SIE.
External transceiver operation is enabled by setting the
UTRDIS bit.
FIGURE 17-2: TYPICAL EXTERNAL
TRANSCEIVER WITH
ISOLATION
Note: While in Suspend mode, a typical bus
powered USB device is limited to 2.5 mA
of current. Care should be taken to assure
minimum current draw when the device
enters Suspend mode.
Note: The USB speed, transceiver and pull-up
should only be configured during the module
setup phase. It is not recommended to
switch these settings while the module is
enabled.
PIC®
Microcontroller
Transceiver
VPO
UOE
Note: The above setting shows a simplified schematic
for a full-speed configuration using an external
transceiver with isolation.
VP
RCV
VMO
VM
D+
DIsolation
1.5 kΩ
3.3V Derived
from USB
VUSB
VDD
VDD Isolated
from USB
PIC18F2455/2550/4455/4550
DS39632E-page 168 © 2009 Microchip Technology Inc.
There are 6 signals from the module to communicate
with and control an external transceiver:
• VM: Input from the single-ended D- line
• VP: Input from the single-ended D+ line
• RCV: Input from the differential receiver
• VMO: Output to the differential line driver
• VPO: Output to the differential line driver
• UOE: Output enable
The VPO and VMO signals are outputs from the SIE to
the external transceiver. The RCV signal is the output
from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
into a single pulse train. The VM and VP signals are
used to report conditions on the serial bus to the SIE
that can’t be captured with the RCV signal. The
combinations of states of these signals and their
interpretation are listed in Table 17-1 and Table 17-2.
REGISTER 17-2: UCFG: USB CONFIGURATION REGISTER
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UTEYE UOEMON(1) — UPUEN(2,3) UTRDIS(2) FSEN(2) PPB1 PPB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6 UOEMON: USB OE Monitor Enable bit(1)
1 = UOE signal active; it indicates intervals during which the D+/D- lines are driving
0 = UOE signal inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 UTRDIS: On-Chip Transceiver Disable bit(2)
1 = On-chip transceiver disabled; digital transceiver interface enabled
0 = On-chip transceiver active
bit 2 FSEN: Full-Speed Enable bit(2)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
© 2009 Microchip Technology Inc. DS39632E-page 169
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TABLE 17-1: DIFFERENTIAL OUTPUTS TO
TRANSCEIVER
TABLE 17-2: SINGLE-ENDED INPUTS
FROM TRANSCEIVER
The UOE signal toggles the state of the external transceiver.
This line is pulled low by the device to enable
the transmission of data from the SIE to an external
device.
17.2.2.3 Internal Pull-up Resistors
The PIC18FX455/X550 devices have built-in pull-up
resistors designed to meet the requirements for
low-speed and full-speed USB. The UPUEN bit
(UCFG<4>) enables the internal pull-ups. Figure 17-1
shows the pull-ups and their control.
17.2.2.4 External Pull-up Resistors
External pull-up may also be used if the internal resistors
are not used. The VUSB pin may be used to pull up
D+ or D-. The pull-up resistor must be 1.5 kΩ (±5%) as
required by the USB specifications. Figure 17-3 shows
an example.
FIGURE 17-3: EXTERNAL CIRCUITRY
17.2.2.5 Ping-Pong Buffer Configuration
The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
17.2.2.6 USB Output Enable Monitor
The USB OE monitor provides indication as to whether
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
transceiver or when UCFG<6> = 1.
The USB OE monitoring is useful for initial system
debugging, as well as scope triggering during eye
pattern generation tests.
17.2.2.7 Eye Pattern Test Enable
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB certification
tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
VPO VMO Bus State
0 0 Single-Ended Zero
0 1 Differential ‘0’
1 0 Differential ‘1’
1 1 Illegal Condition
VP VM Bus State
0 0 Single-Ended Zero
0 1 Low Speed
1 0 High Speed
1 1 Error
PIC®
Microcontroller
Host
Controller/HUB
VUSB
D+
DNote:
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
1.5 kΩ
PIC18F2455/2550/4455/4550
DS39632E-page 170 © 2009 Microchip Technology Inc.
17.2.2.8 Internal Regulator
The PIC18FX455/X550 devices have a built-in 3.3V regulator
to provide power to the internal transceiver and
provide a source for the internal/external pull-ups. An
external 220 nF (±20%) capacitor is required for stability.
The regulator can be enabled or disabled through the
VREGEN Configuration bit. When enabled, the voltage
is visible on pin VUSB whenever the USBEN bit is also
set. When the regulator is disabled (VREGEN = 0), a
3.3V source must be provided through the VUSB pin for
the internal transceiver.
17.2.3 USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 17-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will reassert the
interrupt within 5 TCY of clearing TRNIF. If no additional
data is present, TRNIF will remain clear; USTAT data
will no longer be reliable.
FIGURE 17-4: USTAT FIFO
Note: The drive from VUSB is sufficient to only
drive an external pull-up in addition to the
internal transceiver.
Note 1: Do not enable the internal regulator if an
external regulator is connected to VUSB.
2: VDD must be equal to or greater than
VUSB at all times, even with the regulator
disabled.
Note: The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
Note: If an endpoint request is received while the
USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
Data Bus
USTAT from SIE
4-byte FIFO
for USTAT
Clearing TRNIF
Advances FIFO
© 2009 Microchip Technology Inc. DS39632E-page 171
PIC18F2455/2550/4455/4550
REGISTER 17-3: USTAT: USB STATUS REGISTER
U-0 R-x R-x R-x R-x R-x R-x U-0
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6-3 ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.
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DS39632E-page 172 © 2009 Microchip Technology Inc.
17.2.4 USB ENDPOINT CONTROL
Each of the 16 possible bidirectional endpoints has its
own independent control register, UEPn (where ‘n’ represents
the endpoint number). Each register has an
identical complement of control bits. The prototype is
shown in Register 17-4.
The EPHSHK bit (UEPn<4>) controls handshaking for
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using
isochronous endpoints.
The EPCONDIS bit (UEPn<3>) is used to enable or
disable USB control operations (SETUP) through the
endpoint. Clearing this bit enables SETUP transactions.
Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT
transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Endpoint 0 as the default control endpoint.
The EPOUTEN bit (UEPn<2>) is used to enable or disable
USB OUT transactions from the host. Setting this
bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
from the host.
The EPSTALL bit (UEPn<0>) is used to indicate a
STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that endpoint
pair will be set by the SIE. This bit remains set
until it is cleared through firmware, or until the SIE is
reset.
REGISTER 17-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0 EPSTALL: Endpoint Stall Indicator bit
1 = Endpoint n has issued one or more STALL packets
0 = Endpoint n has not issued any STALL packets
© 2009 Microchip Technology Inc. DS39632E-page 173
PIC18F2455/2550/4455/4550
17.2.5 USB ADDRESS REGISTER
(UADDR)
The USB Address register contains the unique USB
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received,
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written
by the microcontroller during the USB setup phase
(enumeration) as part of the Microchip USB firmware
support.
17.2.6 USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number register is primarily used for
isochronous transfers.
17.3 USB RAM
USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
mapped into the normal data memory space in Banks 4
through 7 (400h to 7FFh) for a total of 1 Kbyte
(Figure 17-5).
Bank 4 (400h through 4FFh) is used specifically for
endpoint buffer control, while Banks 5 through 7 are
available for USB data. Depending on the type of
buffering being used, all but 8 bytes of Bank 4 may also
be available for use as USB buffer space.
Although USB RAM is available to the microcontroller
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 17.4.1.1 “Buffer
Ownership”.
FIGURE 17-5: IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
400h
4FFh
7FFh
500h
USB Data or
Buffer Descriptors,
USB Data or User Data
User Data
User Data
Unused
SFRs
3FFh
000h
F60h
FFFh
Banks 0
Banks 4
Bank15
(USB RAM)
F00h
Banks 8
800h
to 14
to 3
to 7
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DS39632E-page 174 © 2009 Microchip Technology Inc.
17.4 Buffer Descriptors and the Buffer
Descriptor Table
The registers in Bank 4 are used specifically for endpoint
buffer control in a structure known as the Buffer
Descriptor Table (BDT). This provides a flexible method
for users to construct and control endpoint buffers of
various lengths and configuration.
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the
USB RAM space. Each BD, in turn, consists of four registers,
where n represents one of the 64 possible BDs
(range of 0 to 63):
• BDnSTAT: BD Status register
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
BDs always occur as a four-byte block in the sequence,
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is always an offset of (4n – 1) (in hexadecimal)
from 400h, with n being the buffer descriptor
number.
Depending on the buffering configuration used
(Section 17.4.4 “Ping-Pong Buffering”), there are up
to 32, 33 or 64 sets of buffer descriptors. At a minimum,
the BDT must be at least 8 bytes long. This is because
the USB specification mandates that every device must
have Endpoint 0 with both input and output for initial
setup. Depending on the endpoint and buffering
configuration, the BDT can be as long as 256 bytes.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs in Bank 15 are. If the endpoint corresponding
to a particular BD is not enabled, its registers
are not used. Instead of appearing as unimplemented
addresses, however, they appear as available RAM.
Only when an endpoint is enabled by setting the
UEPn<1> bit does the memory at those addresses
become functional as BD registers. As with any address
in the data memory space, the BD registers have an
indeterminate value on any device Reset.
An example of a BD for a 64-byte buffer, starting at
500h, is shown in Figure 17-6. A particular set of BD
registers is only valid if the corresponding endpoint has
been enabled using the UEPn register. All BD registers
are available in USB RAM. The BD for each endpoint
should be set up prior to enabling the endpoint.
17.4.1 BD STATUS AND CONFIGURATION
Buffer descriptors not only define the size of an endpoint
buffer, but also determine its configuration and
control. Most of the configuration is done with the BD
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.
FIGURE 17-6: EXAMPLE OF A BUFFER
DESCRIPTOR
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive. There are
two distinct configurations, depending on whether the
microcontroller or the USB module is modifying the BD
and buffer at a particular time. Only three bit definitions
are shared between the two.
17.4.1.1 Buffer Ownership
Because the buffers and their BDs are shared between
the CPU and the USB module, a simple semaphore
mechanism is used to distinguish which is allowed to
update the BD and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as
a semaphore to distinguish which is allowed to update
the BD and associated buffers in memory. UOWN is the
only bit that is shared between the two configurations
of BDnSTAT.
When UOWN is clear, the BD entry is “owned” by the
microcontroller core. When the UOWN bit is set, the BD
entry and the buffer memory are “owned” by the USB
peripheral. The core should not modify the BD or its
corresponding data buffer during this time. Note that
the microcontroller core can still read BDnSTAT while
the SIE owns the buffer and vice versa.
The buffer descriptors have a different meaning based
on the source of the register update. Prior to placing
ownership with the USB peripheral, the user can configure
the basic operation of the peripheral through the
BDnSTAT bits. During this time, the byte count and buffer
location registers can also be set.
When UOWN is set, the user can no longer depend on
the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated
by the SIE with the token PID and the transfer count,
BDnCNT, is updated.
400h
USB Data
Buffer
Buffer
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
401h
402h
403h
500h
53Fh
Descriptor
Note: Memory regions not to scale.
40h
00h
05h
Starting
Size of Block
(xxh)
Address Registers Contents
Address
© 2009 Microchip Technology Inc. DS39632E-page 175
PIC18F2455/2550/4455/4550
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed. The only exception to this is when KEN
is enabled and/or BSTALL is enabled.
No hardware mechanism exists to block access when
the UOWN bit is set. Thus, unexpected behavior can
occur if the microcontroller attempts to modify memory
when the SIE owns it. Similarly, reading such memory
may produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
17.4.1.2 BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD. At this point, the other seven bits of the register
take on control functions.
The Keep Enable bit, KEN (BDnSTAT<5>), determines
if a BD stays enabled. If the bit is set, once the UOWN
bit is set, it will remain owned by the SIE independent
of the endpoint activity. This prevents the USTAT FIFO
from being updated, as well as the transaction
complete interrupt from being set for the endpoint. This
feature should only be enabled when the Streaming
Parallel Port is selected as the data I/O channel instead
of USB RAM.
The Address Increment Disable bit, INCDIS
(BDnSTAT<4>), controls the SIE’s automatic address
increment function. Setting INCDIS disables the
auto-increment of the buffer address by the SIE for
each byte transmitted or received. This feature should
only be enabled when using the Streaming Parallel
Port, where each data byte is processed to or from the
same memory location.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by
the SIE. When enabled, it checks the data packet’s parity
against the value of DTS (BDnSTAT<6>). If a packet
arrives with an incorrect synchronization, the data will
essentially be ignored. It will not be written to the USB
RAM and the USB transfer complete interrupt flag will
not be set. The SIE will send an ACK token back to the
host to Acknowledge receipt, however. The effects of
the DTSEN bit on the SIE are summarized in
Table 17-3.
The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE commands specified
in Chapter 9 of the USB specification; typically,
continuous STALLs to any endpoint other than the
default control endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control register
is set and a STALL interrupt is generated when a
STALL is issued to the host. The UOWN bit remains set
and the BDs are not changed unless a SETUP token is
received. In this case, the STALL condition is cleared
and the ownership of the BD is returned to the
microcontroller core.
The BD9:BD8 bits (BDnSTAT<1:0>) store the two most
significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 17.4.2 “BD Byte Count” for more
information.
TABLE 17-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
OUT Packet
from Host
BDnSTAT Settings Device Response after Receiving Packet
DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0 1 0 ACK 0 1 Updated
DATA1 1 0 ACK 1 0 Not Updated
DATA1 1 1 ACK 0 1 Updated
DATA0 1 1 ACK 1 0 Not Updated
Either 0 x ACK 0 1 Updated
Either, with error x x NAK 1 0 Not Updated
Legend: x = don’t care
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REGISTER 17-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS(2) KEN INCDIS DTSEN BSTALL BC9 BC8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UOWN: USB Own bit(1)
0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5 KEN: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set (required for SPP endpoint configuration)
0 = USB will hand back the BD once a token has been processed
bit 4 INCDIS: Address Increment Disable bit
1 = Address increment disabled (required for SPP endpoint configuration)
0 = Address increment enabled
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC9:BC8: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.
© 2009 Microchip Technology Inc. DS39632E-page 177
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17.4.1.3 BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 17-6. Once UOWN
is set, any data or control settings previously written
there by the user will be overwritten with data from the
SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID) which is stored in
BDnSTAT<5:3>. The transfer count in the corresponding
BDnCNT register is updated. Values that overflow
the 8-bit register carry over to the two most significant
digits of the count, stored in BDnSTAT<1:0>.
17.4.2 BD BYTE COUNT
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
register. The upper two bits reside in BDnSTAT<1:0>.
This represents a valid byte range of 0 to 1023.
17.4.3 BD ADDRESS VALIDATION
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
For an endpoint starting location to be valid, it must fall
in the range of the USB RAM, 400h to 7FFh. No
mechanism is available in hardware to validate the BD
address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB
applications, the user may want to consider the
inclusion of software-based address validation in their
code.
REGISTER 17-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)
R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN — PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UOWN: USB Own bit
1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC9:BC8: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
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17.4.4 PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
except Endpoint 0
The ping-pong buffer settings are configured using the
PPB1:PPB0 bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 17-7 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 17-4. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
FIGURE 17-7: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP1 IN
EP15 IN
EP1 OUT
EP0 OUT
PPB1:PPB0 = 00
EP0 IN
EP1 IN
No Ping-Pong
EP15 IN
EP0 IN
EP0 OUT Even
PPB1:PPB0 = 01
EP0 OUT Odd
EP1 OUT
Ping-Pong Buffer
EP15 IN Odd
EP0 IN Even
EP0 OUT Even
PPB1:PPB0 = 10
EP0 OUT Odd
EP0 IN Odd
Ping-Pong Buffers
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
Descriptor
400h
4FFh 4FFh 4FFh
400h 400h
47Fh
483h
Available
as
Data RAM Available
as
Data RAM
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
Maximum Memory
Used: 132 bytes
Maximum BDs:
33 (BD0 to BD32)
Maximum Memory
Used: 256 bytes
Maximum BDs:
64 (BD0 to BD63)
Note: Memory area not shown to scale.
Descriptor
Descriptor
Descriptor
Descriptor
Buffers on EP0 OUT on all EPs
EP1 IN Even
EP1 OUT Even
EP1 OUT Odd
EP1 IN Odd
Descriptor
Descriptor
Descriptor
Descriptor
EP15 IN Odd
EP0 OUT
PPB1:PPB0 = 11
EP0 IN
Ping-Pong Buffers
Descriptor
Descriptor
Descriptor
4FFh
400h
Maximum Memory
Used: 248 bytes
Maximum BDs:
62 (BD0 to BD61)
on all other EPs
except EP0
Available
as
Data RAM
4F7h
© 2009 Microchip Technology Inc. DS39632E-page 179
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TABLE 17-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
TABLE 17-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS
Endpoint
BDs Assigned to Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 2
(Ping-Pong on all EPs)
Mode 3
(Ping-Pong on all other EPs,
except EP0)
Out In Out In Out In Out In
0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1
1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)
5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O)
9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O)
10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O)
11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O)
12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O)
13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O)
14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O)
15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BDnSTAT(1) UOWN DTS(4) PID3(2)
KEN(3)
PID2(2)
INCDIS(3)
PID1(2)
DTSEN(3)
PID0(2)
BSTALL(3)
BC9 BC8
BDnCNT(1) Byte Count
BDnADRL(1) Buffer Address Low
BDnADRH(1) Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.
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17.5 USB Interrupts
The USB module can generate multiple interrupt conditions.
To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<5>), in the microcontroller’s
interrupt logic.
Figure 17-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction. Figure 17-9 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 17-8: USB INTERRUPT LOGIC FUNNEL
FIGURE 17-9: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
STALLIF
STALLIE
ACTVIF
ACTVIE
URSTIF
URSTIE
UERRIF
UERRIE
USBIF
Second Level USB Interrupts
(USB Error Conditions)
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
UIR (Flag) and UIE (Enable) Registers
USB Reset
RESET SOF SETUP DATA STATUS SOF
SETUPToken Data ACK
Start-Of-Frame OUT Token Empty Data ACK
IN Token Data ACK
SOFIF
URSTIF
1 ms Frame
Differential Data
From Host From Host To Host
From Host To Host From Host
From Host From Host To Host
Transaction
Control Transfer(1)
Transaction
Complete
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
Set TRNIF
Set TRNIF
Set TRNIF
© 2009 Microchip Technology Inc. DS39632E-page 181
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17.5.1 USB INTERRUPT STATUS
REGISTER (UIR)
The USB Interrupt Status register (Register 17-7) contains
the flag bits for each of the USB status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller’s interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.
When the USB module is in the Low-Power Suspend
mode (UCON<1> = 1), the SIE does not get clocked.
When in this state, the SIE cannot process packets,
and therefore, cannot detect new interrupt conditions
other than the Activity Detect Interrupt, ACTVIF. The
ACTVIF bit is typically used by USB firmware to detect
when the microcontroller should bring the USB module
out of the Low-Power Suspend mode (UCON<1> = 0).
REGISTER 17-7: UIR: USB INTERRUPT STATUS REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIF: Start-Of-Frame Token Interrupt bit
1 = A Start-Of-Frame token received by the SIE
0 = No Start-Of-Frame token received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred
Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
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17.5.1.1 Bus Activity Detect Interrupt Bit
(ACTVIF)
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the
USB module is suspended. A few clock cycles are
required to synchronize the internal hardware state
machine before the ACTVIF bit can be cleared by
firmware. Clearing the ACTVIF bit before the internal
hardware is synchronized may not have an effect on
the value of ACTVIF. Additionally, if the USB module
uses the clock from the 96 MHz PLL source, then after
clearing the SUSPND bit, the USB module may not be
immediately operational while waiting for the 96 MHz
PLL to lock. The application code should clear the
ACTVIF flag as shown in Example 17-1.
EXAMPLE 17-1: CLEARING ACTVIF BIT (UIR<2>)
Note: Only one ACTVIF interrupt is generated
when resuming from the USB bus Idle
condition. If user firmware clears the
ACTVIF bit, the bit will not immediately
become set again, even when there is
continuous bus traffic. Bus traffic must
cease long enough to generate another
IDLEIF condition before another ACTVIF
interrupt can be generated.
Assembly:
BCF UCON, SUSPND
Loop:
BCF UIR, ACTVIF
BTFSC UIR, ACTVIF
BRA Loop
Done:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
© 2009 Microchip Technology Inc. DS39632E-page 183
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17.5.2 USB INTERRUPT ENABLE
REGISTER (UIE)
The USB Interrupt Enable register (Register 17-8)
contains the enable bits for the USB status interrupt
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
The values in this register only affect the propagation
of an interrupt condition to the microcontroller’s interrupt
logic. The flag bits are still set by their interrupt
conditions, allowing them to be polled and serviced
without actually generating an interrupt.
REGISTER 17-8: UIE: USB INTERRUPT ENABLE REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 SOFIE: Start-Of-Frame Token Interrupt Enable bit
1 = Start-Of-Frame token interrupt enabled
0 = Start-Of-Frame token interrupt disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled
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17.5.3 USB ERROR INTERRUPT STATUS
REGISTER (UEIR)
The USB Error Interrupt Status register (Register 17-9)
contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources is
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.
Each error bit is set as soon as the error condition is
detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’.
REGISTER 17-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER
R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
bit 7 bit 0
Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTSEF: Bit Stuff Error Flag bit
1 = A bit stuff error has been detected
0 = No bit stuff error
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed
© 2009 Microchip Technology Inc. DS39632E-page 185
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17.5.4 USB ERROR INTERRUPT ENABLE
REGISTER (UEIE)
The USB Error Interrupt Enable register
(Register 17-10) contains the enable bits for each of
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the microcontroller’s
interrupt logic. The flag bits are still set by
their interrupt conditions, allowing them to be polled
and serviced without actually generating an interrupt.
REGISTER 17-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled
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17.6 USB Power Modes
Many USB applications will likely have several different
sets of power requirements and configuration. The
most common power modes encountered are Bus
Power Only, Self-Power Only and Dual Power with
Self-Power Dominance. The most common cases are
presented here.
17.6.1 BUS POWER ONLY
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 17-10). This is
effectively the simplest power method for the device.
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 μF. If not, some kind of inrush limiting is
required. For more details, see Section 7.2.4 of the
USB 2.0 specification.
According to the USB 2.0 specification, all USB devices
must also support a Low-Power Suspend mode. In the
USB Suspend mode, devices must consume no more
than 2.5 mA from the 5V VBUS line of the USB cable.
The host signals the USB device to enter the Suspend
mode by stopping all USB traffic to that device for more
than 3 ms. This condition will cause the IDLEIF bit in
the UIR register to become set.
During the USB Suspend mode, the D+ or D- pull-up
resistor must remain active, which will consume some
of the allowed suspend current: 2.5 mA budget.
FIGURE 17-10: BUS POWER ONLY
17.6.2 SELF-POWER ONLY
In Self-Power Only mode, the USB application provides
its own power, with very little power being pulled from
the USB. Figure 17-11 shows an example. Note that an
attach indication is added to indicate when the USB
has been connected and the host is actively powering
VBUS.
In order to meet compliance specifications, the USB
module (and the D+ or D- pull-up resistor) should not
be enabled until the host actively drives VBUS high. One
of the I/O pins may be used for this purpose.
The application should never source any current onto
the 5V VBUS pin of the USB cable.
FIGURE 17-11: SELF-POWER ONLY
17.6.3 DUAL POWER WITH SELF-POWER
DOMINANCE
Some applications may require a dual power option.
This allows the application to use internal power primarily,
but switch to power from the USB when no internal
power is available. Figure 17-12 shows a simple
Dual Power with Self-Power Dominance example,
which automatically switches between Self-Power Only
and USB Bus Power Only modes.
Dual power devices also must meet all of the special
requirements for inrush current and Suspend mode
current and must not enable the USB module until
VBUS is driven high. For descriptions of those requirements,
see Section 17.6.1 “Bus Power Only” and
Section 17.6.2 “Self-Power Only”.
Additionally, dual power devices must never source
current onto the 5V VBUS pin of the USB cable.
FIGURE 17-12: DUAL POWER EXAMPLE
VDD
VUSB
VSS
VBUS
~5V
Note: Users should keep in mind the limits for
devices drawing power from the USB.
According to USB specification 2.0, this
cannot exceed 100 mA per low-power
device or 500 mA per high-power device.
VDD
VUSB
VSS
VSELF
~5V
I/O pin
Attach Sense
100 kΩ
VBUS
~5V
100 kΩ
VDD
VUSB
I/O pin
VSS
Attach Sense
VBUS
VSELF
100 kΩ
~5V
~5V
100 kΩ
© 2009 Microchip Technology Inc. DS39632E-page 187
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17.7 Streaming Parallel Port
The Streaming Parallel Port (SPP) is an alternate route
option for data besides USB RAM. Using the SPP, an
endpoint can be configured to send data to or receive
data directly from external hardware.
This methodology presents design possibilities where
the microcontroller acts as a data manager, allowing
the SPP to pass large blocks of data without the microcontroller
actually processing it. An application
example might include a data acquisition system,
where data is streamed from an external FIFO through
USB to the host computer. In this case, endpoint
control is managed by the microcontroller and raw data
movement is processed externally.
The SPP is enabled as a USB endpoint port through
the associated endpoint buffer descriptor. The endpoint
must be enabled as follows:
1. Set BDnADRL:BDnADRH to point to FFFFh.
2. Set the KEN bit (BDnSTAT<5>) to let SIE keep
control of the buffer.
3. Set the INCDIS bit (BDnSTAT<4>) to disable
automatic address increment.
Refer to Section 18.0 “Streaming Parallel Port” for
more information about the SPP.
17.8 Oscillator
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed or even from
the same clock source. Available clocking options are
described in detail in Section 2.3 “Oscillator Settings
for USB”.
TABLE 17-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Note 1: If an endpoint is configured to use the
SPP, the SPP module must also be
configured to use the USB module.
Otherwise, unexpected operation may
occur.
2: In addition, if an endpoint is configured to
use the SPP, the data transfer type of that
endpoint must be isochronous only.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on
page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.
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PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 57
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 57
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 57
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 57
UFRMH — — — — — FRM10 FRM9 FRM8 57
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 57
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 57
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 57
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 57
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on
page
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.
© 2009 Microchip Technology Inc. DS39632E-page 189
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17.10 Overview of USB
This section presents some of the basic USB concepts
and useful information necessary to design a USB
device. Although much information is provided in this
section, there is a plethora of information provided
within the USB specifications and class specifications.
Thus, the reader is encouraged to refer to the USB
specifications for more information (www.usb.org). If
you are very familiar with the details of USB, then this
section serves as a basic, high-level refresher of USB.
17.10.1 LAYERED FRAMEWORK
USB device functionality is structured into a layered
framework graphically shown in Figure 17-13. Each
level is associated with a functional level within the
device. The highest layer, other than the device, is the
configuration. A device may have multiple configurations.
For example, a particular device may have
multiple power requirements based on Self-Power Only
or Bus Power Only modes.
For each configuration, there may be multiple
interfaces. Each interface could support a particular
mode of that configuration.
Below the interface is the endpoint(s). Data is directly
moved at this level. There can be as many as
16 bidirectional endpoints. Endpoint 0 is always a
control endpoint and by default, when the device is on
the bus, Endpoint 0 must be available to configure the
device.
17.10.2 FRAMES
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 17-9 shows an example of a
transaction within a frame.
17.10.3 TRANSFERS
There are four transfer types defined in the USB
specification.
• Isochronous: This type provides a transfer
method for large amounts of data (up to
1023 bytes) with timely delivery ensured;
however, the data integrity is not ensured. This is
good for streaming applications where small data
loss is not critical, such as audio.
• Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
data integrity; however, the delivery timeliness is
not ensured.
• Interrupt: This type of transfer provides for
ensured timely delivery for small blocks of data,
plus data integrity is ensured.
• Control: This type provides for device setup
control.
While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
transfers only.
17.10.4 POWER
Power is available from the Universal Serial Bus. The
USB specification defines the bus power requirements.
Devices may either be self-powered or bus powered.
Self-powered devices draw power from an external
source, while bus powered devices use power supplied
from the bus.
FIGURE 17-13: USB LAYERS
Device
Configuration
Interface
Endpoint
Interface
Endpoint Endpoint Endpoint Endpoint
To other Configurations (if any)
To other Interfaces (if any)
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The USB specification limits the power taken from the
bus. Each device is ensured 100 mA at approximately
5V (one unit load). Additional power may be requested,
up to a maximum of 500 mA. Note that power above
one unit load is a request and the host or hub is not
obligated to provide the extra current. Thus, a device
capable of consuming more than one unit load must be
able to maintain a low-power configuration of a one unit
load or less, if necessary.
The USB specification also defines a Suspend mode.
In this situation, current must be limited to 2.5 mA,
averaged over 1 second. A device must enter a
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode
must drop current consumption within 10 ms after
Suspend. Likewise, when signaling a wake-up, the
device must signal a wake-up within 10 ms of drawing
current above the Suspend limit.
17.10.5 ENUMERATION
When the device is initially attached to the bus, the host
enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,
gathering information such as power consumption, data
rates and sizes, protocol and other descriptive
information; descriptors contain this information. A
typical enumeration process would be as follows:
1. USB Reset: Reset the device. Thus, the device
is not configured and does not have an address
(address 0).
2. Get Device Descriptor: The host requests a
small portion of the device descriptor.
3. USB Reset: Reset the device again.
4. Set Address: The host assigns an address to the
device.
5. Get Device Descriptor: The host retrieves the
device descriptor, gathering info such as
manufacturer, type of device, maximum control
packet size.
6. Get configuration descriptors.
7. Get any other descriptors.
8. Set a configuration.
The exact enumeration process depends on the host.
17.10.6 DESCRIPTORS
There are eight different standard descriptor types of
which five are most important for this device.
17.10.6.1 Device Descriptor
The device descriptor provides general information,
such as manufacturer, product number, serial number,
the class of the device and the number of configurations.
There is only one device descriptor.
17.10.6.2 Configuration Descriptor
The configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this configuration.
There may be more than one configuration for a
device (i.e., low-power and high-power configurations).
17.10.6.3 Interface Descriptor
The interface descriptor details the number of endpoints
used in this interface, as well as the class of the
interface. There may be more than one interface for a
configuration.
17.10.6.4 Endpoint Descriptor
The endpoint descriptor identifies the transfer type
(Section 17.10.3 “Transfers”) and direction, as well
as some other specifics for the endpoint. There may be
many endpoints in a device and endpoints may be
shared in different configurations.
17.10.6.5 String Descriptor
Many of the previous descriptors reference one or
more string descriptors. String descriptors provide
human readable information about the layer
(Section 17.10.1 “Layered Framework”) they
describe. Often these strings show up in the host to
help the user identify the device. String descriptors are
generally optional to save memory and are encoded in
a unicode format.
17.10.7 BUS SPEED
Each USB device must indicate its bus presence and
speed to the host. This is accomplished through a
1.5 kΩ resistor which is connected to the bus at the
time of the attachment event.
Depending on the speed of the device, the resistor
either pulls up the D+ or D- line to 3.3V. For a
low-speed device, the pull-up resistor is connected to
the D- line. For a full-speed device, the pull-up resistor
is connected to the D+ line.
17.10.8 CLASS SPECIFICATIONS AND
DRIVERS
USB specifications include class specifications which
operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
Communications and Human Interface (HID). In most
cases, a driver is required at the host side to ‘talk’ to the
USB device. In custom applications, a driver may need
to be developed. Fortunately, drivers are available for
most common host systems for the most common
classes of devices. Thus, these drivers can be reused.
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18.0 STREAMING PARALLEL PORT
PIC18F4455/4550 USB devices provide a Streaming
Parallel Port as a high-speed interface for moving data
to and from an external system. This parallel port
operates as a master port, complete with chip select
and clock outputs to control the movement of data to
slave devices. Data can be channelled either directly to
the USB SIE or to the microprocessor core. Figure 18-1
shows a block view of the SPP data path.
FIGURE 18-1: SPP DATA PATH
In addition, the SPP can provide time multiplexed
addressing information along with the data by using the
second strobe output. Thus, the USB endpoint number
can be written in conjunction with the data for that
endpoint.
18.1 SPP Configuration
The operation of the SPP is controlled by two registers:
SPPCON and SPPCFG. The SPPCON register
(Register 18-1) controls the overall operation of the
parallel port and determines if it operates under USB or
microcontroller control. The SPPCFG register
(Register 18-2) controls timing configuration and pin
outputs.
18.1.1 ENABLING THE SPP
To enable the SPP, set the SPPEN bit (SPPCON<0>).
In addition, the TRIS bits for the corresponding SPP
pins must be properly configured. At a minimum:
• Bits TRISD<7:0> must be set (= 1)
• Bits TRISE<2:1> must be cleared (= 0)
If CK1SPP is to be used:
• Bit TRISE<0> must be cleared (= 0)
If CSPP is to be used:
• Bit TRISB<4> must be cleared (= 0)
Note: The Streaming Parallel Port is only
available on 40/44-pin devices.
SPP
Logic
CK2SPP
OESPP
CSSPP
SPP<7:0>
USB CK1SPP
CPU
PIC18F4455/4550
SIE
REGISTER 18-1: SPPCON: SPP CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPPOWN SPPEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1 SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP
bit 0 SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled
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18.1.2 CLOCKING DATA
The SPP has four control outputs:
• Two separate clock outputs (CK1SPP and
CK2SPP)
• Output enable (OESPP)
• Chip select (CSSPP)
Together, they allow for several different configurations
for controlling the flow of data to slave devices. When
all control outputs are used, the three main options are:
• CLK1 clocks endpoint address information while
CLK2 clocks data
• CLK1 clocks write operations while CLK2 clocks
reads
• CLK1 clocks Odd address data while CLK2 clocks
Even address data
Additional control options are derived by disabling the
CK1SPP and CSSPP outputs. These are enabled or
disabled with the CLK1EN and CSEN bits, respectively,
located in Register 18-2.
18.1.3 WAIT STATES
The SPP is designed with the capability of adding wait
states to read and write operations. This allows access
to parallel devices that require extra time for access.
Wait state clocking is based on the data source clock.
If the SPP is configured to operate as a USB endpoint,
then wait states are based on the USB clock. Likewise,
if the SPP is configured to operate from the microcontroller,
then wait states are based on the instruction
rate (FOSC/4).
The WS3:WS0 bits set the wait states used by the SPP,
with a range of no wait states to 30 wait states, in multiples
of two. The wait states are added symmetrically to
all transactions, with one-half added following each of the
two clock cycles normally required for the transaction.
Figure 18-3 and Figure 18-4 show signalling examples
with 4 wait states added to each transaction.
18.1.4 SPP PULL-UPS
The SPP data lines (SPP<7:0>) are equipped with
internal pull-ups for applications that may leave the port
in a high-impedance condition. The pull-ups are
enabled using the control bit, RDPU (PORTE<7>).
REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits
1x = CLK1 toggles on read or write of an Odd endpoint address;
CLK2 toggles on read or write of an Even endpoint address
01 = CLK1 toggles on write; CLK2 toggles on read
00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write
bit 5 CSEN: SPP Chip Select Pin Enable bit
1 = RB4 pin is controlled by the SPP module and functions as SPP CS output
0 = RB4 functions as a digital I/O port
bit 4 CLK1EN: SPP CLK1 Pin Enable bit
1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output
0 = RE0 functions as a digital I/O port
bit 3-0 WS3:WS0: SPP Wait States bits
1111 = 30 additional wait states
1110 = 28 additional wait states
• •
• •
0001 = 2 additional wait states
0000 = 0 additional wait states
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FIGURE 18-2: TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND
READ DATA (NO WAIT STATES)
FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)
FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)
FOSC/4
OESPP
CK1SPP
CK2SPP
CSSPP
SPP<7:0>
MOVWF SPPEPS MOVWF SPPDATA
Write Address Write Data
MOVF SPPDATA, W
Read Data
ADDR DATA DATA
USB Clock
OESPP
CK1SPP
CK2SPP
CSSPP
SPP<7:0>
2 Wait States 2 Wait States 2 Wait States 2 Wait States
Write Address Write Data
USB Clock
OESPP
CK1SPP
CK2SPP
CSSPP
SPP<7:0> Write Address Read Data
2 Wait States 2 Wait States 2 Wait States 2 Wait States
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18.2 Setup for USB Control
When the SPP is configured for USB operation, data
can be clocked directly to and from the USB peripheral
without intervention of the microcontroller; thus, no
process time is required. Data is clocked into or out
from the SPP with endpoint (address) information first,
followed by one or more bytes of data, as shown in
Figure 18-5. This is ideal for applications that require
isochronous, large volume data movement.
The following steps are required to set up the SPP for
USB control:
1. Configure the SPP as desired, including wait
states and clocks.
2. Set the SPPOWN bit for USB ownership.
3. Set the buffer descriptor starting address
(BDnADRL:BDnADRH) to FFFFh.
4. Set the KEN bit (BDnSTAT<5>) so the buffer
descriptor is kept indefinitely by the SIE.
5. Set the INCDIS bit (BDnSTAT<4>) to disable
automatic buffer address increment.
6. Set the SPPEN bit to enable the module.
18.3 Setup for Microcontroller Control
The SPP can also act as a parallel port for the
microcontroller. In this mode, the SPPEPS register
(Register 18-3) provides status and address write
control. Data is written to and read from the SPPDATA
register. When the SPP is owned by the
microcontroller, the SPP clock is driven by the
instruction clock (FOSC/4).
The following steps are required to set up the SPP for
microcontroller operation:
1. Configure the SPP as desired, including wait
states and clocks.
2. Clear the SPPOWN bit.
3. Set SPPEN to enable the module.
18.3.1 SPP INTERRUPTS
When owned by the microcontroller core, control can
generate an interrupt to notify the application when
each read and write operation is completed. The
interrupt flag bit is SPPIF (PIR1<7>) and is enabled by
the SPPIE bit (PIE1<7>). Like all other microcontroller
level interrupts, it can be set to a low or high priority.
This is done with the SPPIP bit (IPR1<7>).
18.3.2 WRITING TO THE SPP
Once configured, writing to the SPP is performed by
writing to the SPPEPS and SPPDATA registers. If the
SPP is configured to clock out endpoint address information
with the data, writing to the SPPEPS register
initiates the address write cycle. Otherwise, the write is
started by writing the data to the SPPDATA register.
The SPPBUSY bit indicates the status of the address
and the data write cycles.
The following is an example write sequence:
1. Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing the
address. If address write is not used, then skip
to step 3.
2. Monitor the SPPBUSY bit to determine when the
address has been sent. The duration depends
on the wait states.
3. Write the data to the SPPDATA register. The
SPP automatically starts writing the data.
4. Monitor the SPPBUSY bit to determine when the
data has been sent. The duration depends on
the wait states.
5. Go back to steps 1 or 3 to write a new address
or data.
FIGURE 18-5: TRANSFER OF DATA BETWEEN USB SIE AND SPP
Note: If a USB endpoint is configured to use the
SPP, the data transfer type of that
endpoint must be isochronous only.
Note: The SPPBUSY bit should be polled to
make certain that successive writes to the
SPPEPS or SPPDATA registers do not
overrun the wait time due to the wait state
setting.
Endpoint Byte 0 Byte 1 Byte 2 Byte 3 Byte n
Address
Write USB endpoint number to SPP
Write outbound USB data to SPP or
read inbound USB data from SPP
© 2009 Microchip Technology Inc. DS39632E-page 195
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18.3.3 READING FROM THE SPP
Reading from the SPP involves reading the SPPDATA
register. Reading the register the first time initiates the
read operation. When the read is finished, indicated by
the SPPBUSY bit, the SPPDATA will be loaded with the
current data.
The following is an example read sequence:
1. Write the 4-bit address to the SPPEPS register.
The SPP automatically starts writing the
address. If address write is not used then skip to
step 3.
2. Monitor the SPPBUSY bit to determine when the
address has been sent. The duration depends
on the wait states.
3. Read the data from the SPPDATA register; the
data from the previous read operation is
returned. The SPP automatically starts the read
cycle for the next read.
4. Monitor the SPPBUSY bit to determine when the
data has been read. The duration depends on
the wait states.
5. Go back to step 3 to read the current byte from
the SPP and start the next read cycle.
REGISTER 18-3: SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER
R-0 R-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RDSPP: SPP Read Status bit (Valid when SPPCON = 1, USB)
1 = The last transaction was a read from the SPP
0 = The last transaction was not a read from the SPP
bit 6 WRSPP: SPP Write Status bit (Valid when SPPCON = 1, USB)
1 = The last transaction was a write to the SPP
0 = The last transaction was not a write to the SPP
bit 5 Unimplemented: Read as ‘0’
bit 4 SPPBUSY: SPP Handshaking Override bit
1 = The SPP is busy
0 = The SPP is ready to accept another read or write request
bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits
1111 = Endpoint Address 15
• •
• •
0001
0000 = Endpoint Address 0
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TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
SPPCON(3) — — — — — — SPPOWN SPPEN 57
SPPCFG(3) CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57
SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 57
SPPDATA(3) DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 57
PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PORTE RDPU(3) — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.
© 2009 Microchip Technology Inc. DS39632E-page 197
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19.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
19.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
19.2 Control Registers
The MSSP module has three associated control registers.
These include a status register (SSPSTAT) and
two control registers (SSPCON1 and SSPCON2). The
use of these registers and their individual Configuration
bits differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
19.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of the SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC7/RX/DT/SDO
• Serial Data In (SDI) – RB0/AN12/INT0/FLT0/SDI/SDA
• Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/SS/HLVDIN/C2OUT
Figure 19-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 19-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
Prescaler TOSC
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
SDO
SSPBUF reg
SDI
SS
SCK
Note: Only those pin functions relevant to SPI
operation are shown here.
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19.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower six bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not doublebuffered.
A write to SSPBUF will write to both SSPBUF
and SSPSR.
REGISTER 19-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE(1) D/A P S R/W UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit(1)
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
© 2009 Microchip Technology Inc. DS39632E-page 199
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REGISTER 19-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV(1) SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit(1)
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins(2)
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin(3)
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled(3)
0011 = SPI Master mode, clock = TMR2 output/2(3,4)
0010 = SPI Master mode, clock = FOSC/64(3)
0001 = SPI Master mode, clock = FOSC/16(3)
0000 = SPI Master mode, clock = FOSC/4(3)
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.
4: PR2 = 0x00 is not supported when running the SPI module in TMR2 Output/2 mode.
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19.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP module consists of a transmit/receive shift
register (SSPSR) and a buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the eight
bits of data have been received, that byte is moved to
the SSPBUF register. Then, the Buffer Full detect bit,
BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed
successfully.
The Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur. Example 19-1
shows the loading of the SSPBUF (SSPSR) for data
transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) REGISTER
Note: When the application software is expecting
to receive valid data, the SSPBUF
should be read before the next byte of
data to transfer is written to the SSPBUF.
Application software should follow this
process even when the current contents of
SSPBUF are not important.
Note: The SSPBUF register cannot be used with
read-modify-write instructions, such as
BCF, BTFSC and COMF.
TransmitSPI:
BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous
transmission).
MOVF SSPBUF, W ;Perform read, even if the data in SSPBUF is not important
MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful
MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send)
MOVWF SSPBUF ;Load data to send into transmit buffer
WaitComplete: ;Loop until data has finished transmitting
BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete
BRA WaitComplete
© 2009 Microchip Technology Inc. DS39632E-page 201
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19.3.3 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the SSPCON
registers and then set the SSPEN bit. This configures
the SDI, SDO, SCK and SS pins as serial port pins. For
the pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed as follows:
• SDI must have TRISB<0> bit set (configure as
digital in ADCON1)
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<1> bit
cleared
• SCK (Slave mode) must have TRISB<1> bit set
(configure as digital in ADCON1)
• SS must have TRISA<5> bit set (configure as
digital in ADCON1)
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value. Input
functions which will not be used do not need to be
configured as digital inputs.
19.3.4 TYPICAL CONNECTION
Figure 19-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be programmed
to the same Clock Polarity (CKP), then both
controllers would send and receive data at the same
time. Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
FIGURE 19-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
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19.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 19-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This, then,
would give waveforms for SPI communication as
shown in Figure 19-3, Figure 19-5 and Figure 19-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user-programmable to be one
of the following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 48 MHz) of
12.00 Mbps.
When used in Timer2 Output/2 mode, the bit rate can
be configured using the PR2 Period register and the
Timer2 prescaler. However, writing to SSPBUF does
not clear the current TMR2 value in hardware. Depending
upon the current value of TMR2 when the user firmware
writes to SSPBUF, this can result in an
unpredictable MSb bit width, unless the procedure of
Example 19-2 is used.
Figure 19-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
EXAMPLE 19-2: LOADING SSPBUF WITH THE TIMER2/2 CLOCK MODE
TransmitSPI:
BCF PIR1, SSPIF ;Make sure interrupt flag is clear (may have been set from previous
transmission)
MOVF SSPBUF, W ;Perform read, even if the data in SSPBUF is not important
MOVWF RXDATA ;Save previously received byte in user RAM, if the data is meaningful
BCF T2CON, TMR2ON ;Turn off timer when loading SSPBUF
CLRF TMR2 ;Set timer to a known state
MOVF TXDATA, W ;WREG = Contents of TXDATA (user data to send)
MOVWF SSPBUF ;Load data to send into transmit buffer
BSF T2CON, TMR2ON ;Start timer to begin transmission
WaitComplete: ;Loop until data has finished transmitting
BTFSS PIR1, SSPIF ;Interrupt flag set when transmit is complete
BRA WaitComplete
© 2009 Microchip Technology Inc. DS39632E-page 203
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FIGURE 19-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2↓
bit 0
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19.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device can be configured
to wake-up from Sleep.
19.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with the SS pin control
enabled (SSPCON1<3:0> = 04h). When the SS pin is
low, transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of a
transmitted byte and becomes a floating output. External
pull-up/pull-down resistors may be desirable
depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 19-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI module is in Slave mode
with SS pin control enabled
(SSPCON1<3:0> = 0100), the SPI module
will reset if the SS pin is set to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
Next Q4 Cycle
after Q2↓
© 2009 Microchip Technology Inc. DS39632E-page 205
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FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2↓
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2↓
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19.3.8 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
In most Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock
source, the secondary clock (Timer1 oscillator) or the
INTOSC source. See Section 2.4 “Clock Sources
and Oscillator Switching” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the controller
from Sleep mode or one of the Idle modes when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all eight bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
19.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
19.3.10 BUS MODE COMPATIBILITY
Table 19-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 19-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56
SSPBUF MSSP Receive Buffer/Transmit Register 54
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54
SSPSTAT SMP CKE D/A P S R/W UA BF 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled,
all of the associated bits read ‘0’.
© 2009 Microchip Technology Inc. DS39632E-page 207
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19.4 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RB1/AN10/INT1/SCK/SCL
• Serial data (SDA) – RB0/AN12/INT0/FLT0/SDI/SDA
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 19-7: MSSP BLOCK DIAGRAM
(I2C™ MODE)
19.4.1 REGISTERS
The MSSP module has six registers for I2C operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the MSSP is configured in I2C Slave mode. When the
MSSP is configured in Master mode, the lower seven
bits of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not doublebuffered.
A write to SSPBUF will write to both SSPBUF
and SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
Shift
Clock
MSb LSb
Note: Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
SCL
SDA
Start and
Stop bit Detect
Address Mask
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REGISTER 19-3: SSPSTAT: MSSP STATUS REGISTER (I2C™ MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P(1) S(1) R/W(2,3) UA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit(1)
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit(1)
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
bit 2 R/W: Read/Write Information bit(2,3)
In Slave mode:
1 = Read
0 = Write
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
bit 1 UA: Update Address bit (10-Bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Note 1: This bit is cleared on Reset and when SSPEN is cleared.
2: This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next Start bit, Stop bit or not ACK bit.
3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
© 2009 Microchip Technology Inc. DS39632E-page 209
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REGISTER 19-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C™ MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins(1)
0 = Disables serial port and configures these pins as I/O port pins(1)
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled(2)
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled(2)
1011 = I2C Firmware Controlled Master mode (slave Idle)(2)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))(2,3)
0111 = I2C Slave mode, 10-bit address(2)
0110 = I2C Slave mode, 7-bit address(2)
Note 1: When enabled, the SDA and SCL pins must be properly configured as input or output.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3: Guideline only; exact baud rate slightly dependent upon circuit conditions, but the highest clock rate
should not exceed this formula. SSPADD values of ‘0’ and ‘1’ are not supported.
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REGISTER 19-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MASTER MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit (Slave mode only)
Unused in Master mode.
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit(2)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit(2)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit(2)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit(2)
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
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REGISTER 19-6: SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ SLAVE MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits
1 = Masking of corresponding bits of SSPADD enabled
0 = Masking of corresponding bits of SSPADD disabled
bit 1 ADMSK1: Slave Address Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SPADD<1> only enabled
0 = Masking of SPADD<1> only disabled
In 10-Bit Addressing mode:
1 = Masking of SSPADD<1:0> enabled
0 = Masking of SSPADD<1:0> disabled
bit 0 SEN: Stretch Enable bit(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
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19.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:
• I2C Master mode, clock
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISC or TRISD bits. To ensure
proper operation of the module, pull-up resistors must
be provided externally to the SCL and SDA pins.
19.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Address masking will
allow the hardware to generate an interrupt for more
than one address (up to 31 in 7-bit addressing and up
to 63 in 10-bit addressing). Through the mode select
bits, the user can also choose to interrupt on Start and
Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware automatically
will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit, SSPIF, is set. The BF bit is
cleared by reading the SSPBUF register, while bit,
SSPOV, is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
19.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. The MSSP Interrupt Flag bit, SSPIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte
would equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’
are the two MSbs of the address. The sequence of
events for 10-bit addressing is as follows, with steps
7 through 9 for the slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set on address
match).
2. Update the SSPADD register with second (low)
byte of address (clears bit, UA, and releases the
SCL line).
3. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (bits,
SSPIF, BF and UA, are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit, UA.
6. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits, SSPIF
and BF, are set).
9. Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
© 2009 Microchip Technology Inc. DS39632E-page 213
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19.4.3.2 Address Masking
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 19-3).
The I2C Slave behaves the same way whether address
masking is used or not. However, when address
masking is used, the I2C slave can Acknowledge
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In 7-Bit Address mode, address mask bits
ADMSK<5:1> (SSPCON2<5:1>) mask the corresponding
address bits in the SSPADD register. For any
ADMSK bits that are set (ADMSK = 1), the
corresponding address bit is ignored
(SSPADD = x). For the module to issue an address
Acknowledge, it is sufficient to match only on
addresses that do not have an active address mask.
In 10-Bit Address mode, bits ADMSK<5:2> mask the
corresponding address bits in the SSPADD register. In
addition, ADMSK1 simultaneously masks the two LSbs
of the address (SSPADD<1:0>). For any ADMSK bits
that are active (ADMSK = 1), the corresponding
address bit is ignored (SSPADD = x). Also note
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits, the
address mask bits do not interact with those bits. They
only affect the lower address bits.
EXAMPLE 19-3: ADDRESS MASKING EXAMPLES
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
7-bit addressing:
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged : A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-bit addressing:
SSPADD<7:0> = A0h (10100000) (The two MSbs of the address are ignored in this example, since
they are not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh,
AEh, AFh
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19.4.3.3 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit, BF (SSPSTAT<0>), is
set, or bit, SSPOV (SSPCON1<6>), is set.
An MSSP interrupt is generated for each data transfer
byte. The Interrupt Flag bit, SSPIF, must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RB1/AN10/
INT1/SCK/SCL will be held low (clock stretch) following
each data transfer. The clock must be released by
setting bit, CKP (SSPCON1<4>). See Section 19.4.4
“Clock Stretching” for more detail.
19.4.3.4 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RB1/AN10/INT1/SCK/
SCL is held low regardless of SEN (see Section 19.4.4
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data. The transmit data must be loaded into the
SSPBUF register which also loads the SSPSR register.
Then the RB1/AN10/INT1/SCK/SCL pin should be
enabled by setting bit, CKP (SSPCON1<4>). The eight
data bits are shifted out on the falling edge of the SCL
input. This ensures that the SDA signal is valid during
the SCL high time (Figure 19-10).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT register)
and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, the RB1/AN10/INT1/SCK/SCL pin must be
enabled by setting bit CKP (SSPCON1<4>).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
© 2009 Microchip Technology Inc. DS39632E-page 215
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FIGURE 19-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ when SEN = 0)
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FIGURE 19-9: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011
(RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 X A3 X X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
CKP
(CKP does not reset to ‘0’ when SEN = 0)
Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.
© 2009 Microchip Technology Inc. DS39632E-page 217
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FIGURE 19-10: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is written in software
Cleared in software
Data in
sampled
S
ACK
R/W = 1 Transmitting Data
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSPBUF is written in software
Cleared in software
From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CKP is set in software CKP is set in software
From SSPIF ISR
SCL held low
while CPU
responds to SSPIF
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FIGURE 19-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>)
Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
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FIGURE 19-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001
(RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).
2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.
3: Note that the Most Significant bits of the address are not affected by the bit masking.
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FIGURE 19-13: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8
R/W = 1
ACK ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Completion of
clears BF flag
CKP (SSPCON1<4>)
CKP is set in software
CKP is automatically cleared in hardware, holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
third address sequence
BF flag is clear
at the end of the
© 2009 Microchip Technology Inc. DS39632E-page 221
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19.4.4 CLOCK STRETCHING
Both 7-Bit and 10-Bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
19.4.4.1 Clock Stretching for 7-Bit Slave
Receive Mode (SEN = 1)
In 7-Bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP bit being cleared to ‘0’ will assert
the SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 19-15).
19.4.4.2 Clock Stretching for 10-Bit Slave
Receive Mode (SEN = 1)
In 10-Bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
19.4.4.3 Clock Stretching for 7-Bit Slave
Transmit Mode
7-Bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmission
is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 19-10).
19.4.4.4 Clock Stretching for 10-Bit Slave
Transmit Mode
In 10-Bit Slave Transmit mode, clock stretching is
controlled during the first two address sequences by
the state of the UA bit, just as it is in 10-Bit Slave
Receive mode. The first two addresses are followed
by a third address sequence which contains the highorder
bits of the 10-bit address and the R/W bit set to
‘1’. After the third address sequence is performed, the
UA bit is not set, the module is now configured in
Transmit mode and clock stretching is controlled by
the BF flag as in 7-Bit Slave Transmit mode (see
Figure 19-13).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading
the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
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19.4.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already
sampled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 19-14).
FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX DX – 1
Write
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON1
CKP
Master device
deasserts clock
Master device
asserts clock
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FIGURE 19-15: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the ninth clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because Buffer Full (BF) bit is
clear prior to falling edge
of ninth clock
Clock is not held low
because ACK = 1
BF is set after falling
edge of the ninth clock,
CKP is reset to ‘0’ and
clock stretching occurs
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FIGURE 19-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
CKP written to ‘1’
Note: An update of the SSPADD register before
the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because ACK = 1
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19.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General
Call Enable (GCEN) bit is enabled (SSPCON2<7>
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-Bit Addressing mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 19-17).
FIGURE 19-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESSING MODE)
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
R/W = 0
General Call Address ACK
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
‘0’
‘1’
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19.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware if the TRIS bits
are set.
Master mode operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options:
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause the MSSP Interrupt
Flag bit, SSPIF, to be set (and MSSP interrupt, if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 19-18: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Note: The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset S, P, WCOL (SSPSTAT, SSPCON1);
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
set SSPIF, BCLIF;
reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
Start bit Detect
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19.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (seven bits) and the Read/Write (R/W)
bit. In this case, the R/W bit will be logic ‘0’. Serial data
is transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
Stop conditions are output to indicate the beginning
and the end of a serial transfer.
In Master Receive mode, the first byte transmitted contains
the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’ Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 19.4.7 “Baud Rate” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all eight
bits are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all eight bits
are transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
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19.4.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower seven bits of the
SSPADD register (Figure 19-19). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmission
of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 19-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD. SSPADD values of less than 2 are not
supported. Due to the need to support I2C clock
stretching capability, I2C baud rates are partially
dependent upon system parameters, such as line
capacitance and pull-up strength. The parameters
provided in Table 19-3 are guidelines, and the actual
baud rate may be slightly slower than that predicted in
the table. The baud rate formula shown in the bit
description of Register 19-4 sets the maximum baud
rate that can occur for a given SSPADD value.
FIGURE 19-19: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 19-3: I2C™ CLOCK RATE W/BRG
SSPM3:SSPM0
CLKO BRG Down Counter FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY FCY * 2 BRG Value FSCL
(2 Rollovers of BRG)
10 MHz 20 MHz 18h 400 kHz(1)
10 MHz 20 MHz 1Fh 312.5 kHz
10 MHz 20 MHz 63h 100 kHz
4 MHz 8 MHz 09h 400 kHz(1)
4 MHz 8 MHz 0Ch 308 kHz
4 MHz 8 MHz 27h 100 kHz
1 MHz 2 MHz 02h 333 kHz(1)
1 MHz 2 MHz 09h 100 kHz
Note 1: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
© 2009 Microchip Technology Inc. DS39632E-page 229
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19.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 19-20).
FIGURE 19-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX DX – 1
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
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19.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
19.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL bit is set and the contents of
the buffer are unchanged (the write doesn’t occur).
FIGURE 19-21: FIRST START BIT TIMING
Note: If, at the beginning of the Start condition,
the SDA and SCL pins are already sampled
low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower five bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1,
SCL = 1 At completion of Start bit,
TBRG Write to SSPBUF occurs here
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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19.4.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled
low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator
times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
19.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 19-22: REPEATED START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower five bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
Falling edge of ninth clock, Write to SSPBUF occurs here
end of Xmit
At completion of Start bit,
hardware clears RSEN bit
1st bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change).
SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
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19.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time specification
parameter 107). When the SCL pin is released
high, it is held that way for TBRG. The data on the SDA
pin must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 19-23).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPCON2<6>). Following the falling edge of the ninth
clock transmission of the address, the SSPIF is set, the
BF flag is cleared and the Baud Rate Generator is
turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
19.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all eight bits are shifted out.
19.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur) after
2 TCY after the SSPBUF write. If SSPBUF is rewritten
within 2 TCY, the WCOL bit is set and SSPBUF is
updated. This may result in a corrupted transfer.
The user should verify that the WCOL is clear after
each write to SSPBUF to ensure the transfer is correct.
In all cases, WCOL must be cleared in software.
19.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowledge
(ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
19.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate Generator
is suspended from counting, holding SCL low. The
MSSP is now in Idle state awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
19.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
19.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
19.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
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FIGURE 19-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Cleared in software service routine
SSPBUF is written in software
from MSSP interrupt
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-Bit Address
Write SSPCON2<0> SEN = 1,
Start condition begins From slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared in software
SSPBUF written
PEN
R/W
Cleared in software
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FIGURE 19-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
5 6 7 8 9 P
D7 D6 D5 D4 D3 D2 D1 D0
S
SDA A7 A6 A5 A4 A3 A2 A1
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
Bus master
terminates
transfer
ACK
Receiving Data from Slave Receiving Data from Slave
ACK D7 D6 D5 D4 D3 D2 D1 D0
Transmit Address to Slave R/W = 1
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here,
ACK from Slave
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared in software Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
ACK from master,
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknowledge
sequence
of receive
Set ACKEN, start Acknowledge sequence,
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start Condition
Cleared in software
SDA = ACKDT = 0
Cleared in
software
SSPOV is set because
SSPBUF is still full
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
© 2009 Microchip Technology Inc. DS39632E-page 235
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19.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate
an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into an inactive state
(Figure 19-25).
19.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
19.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Enable bit, PEN
(SSPCON2<2>). At the end of a receive/transmit, the
SCL line is held low after the falling edge of the ninth
clock. When the PEN bit is set, the master will assert
the SDA line low. When the SDA line is sampled low,
the Baud Rate Generator is reloaded and counts down
to 0. When the Baud Rate Generator times out, the
SCL pin will be brought high and one TBRG (Baud Rate
Generator rollover count) later, the SDA pin will be
deasserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 19-26).
19.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 19-25: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 19-26: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
Set SSPIF at the
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
Cleared in
TBRG TBRG
end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
ninth clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
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19.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
19.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
19.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
19.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration.
When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF, and reset the
I2C port to its Idle state (Figure 19-27).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are deasserted and the respective control bits in
the SSPCON2 register are cleared. When the user services
the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF bit will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination
of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register,
or the bus is Idle and the S and P bits are cleared.
FIGURE 19-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Bus collision has occurred.
Set Bus Collision
Interrupt Flag (BCLIF)
by the master.
by master
Data changes
while SCL = 0
© 2009 Microchip Technology Inc. DS39632E-page 237
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19.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 19-28).
b) SCL is sampled low before SDA is asserted low
(Figure 19-29).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its inactive state
(Figure 19-28).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 19-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘0’,
during this time a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 19-28: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
MSSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
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FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 19-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN
bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’ ‘0’
‘0’ ‘0’
SDA
SCL
SEN
Set S
Less than TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
set SSPIF in software
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPIF
‘0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
© 2009 Microchip Technology Inc. DS39632E-page 239
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19.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to ‘0’. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, see
Figure 19-31). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from high-tolow
before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition
(see Figure 19-32).
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 19-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 19-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
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19.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’. (Figure 19-33). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 19-34).
FIGURE 19-33: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 19-34: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
© 2009 Microchip Technology Inc. DS39632E-page 241
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TABLE 19-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 56
TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 56
SSPBUF MSSP Receive Buffer/Transmit Register 54
SSPADD MSSP Address Register in I2C Slave mode.
MSSP Baud Rate Reload Register in I2C Master mode.
54
TMR2 Timer2 Register 54
PR2 Timer2 Period Register 54
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 54
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 54
SSPSTAT SMP CKE D/A P S R/W UA BF 54
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in I2C™ mode.
Note 1: These registers or bits are not implemented in 28-pin devices.
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NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 243
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20.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of the
two serial I/O modules. (Generically, the USART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a halfduplex
synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break reception
and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full-duplex) with:
- Auto-wake-up on Break signal
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half-duplex) with
selectable clock polarity
• Synchronous – Slave (half-duplex) with selectable
clock polarity
The pins of the Enhanced USART are multiplexed
with PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT/SDO as an EUSART:
• SPEN bit (RCSTA<7>) must be set (= 1)
• TRISC<7> bit must be set (= 1)
• TRISC<6> bit must be set (= 1)
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These are detailed on the following pages in
Register 20-1, Register 20-2 and Register 20-3,
respectively.
Note: The EUSART control will automatically
reconfigure the pin from input to output as
needed.
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REGISTER 20-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous
Slave mode.
© 2009 Microchip Technology Inc. DS39632E-page 245
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REGISTER 20-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
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REGISTER 20-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 5 RXDTP: Received Data Polarity Select bit
Asynchronous mode:
1 = RX data is inverted
0 = RX data received is not inverted
Synchronous modes:
1 = Received Data (DT) is inverted. Idle state is a low level.
0 = No inversion of Data (DT). Idle state is a high level.
bit 4 TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1 = TX data is inverted
0 = TX data is not inverted
Synchronous modes:
1 = Clock (CK) is inverted. Idle state is a high level.
0 = No inversion of Clock (CK). Idle state is a low level.
bit 3 BRG16: 16-Bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in
hardware on following rising edge
0 = RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
cleared in hardware upon completion.
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
© 2009 Microchip Technology Inc. DS39632E-page 247
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20.1 Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit, or 16-bit, generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits,
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>), also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 20-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 20-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 20-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 20-2. It may be advantageous
to use the high baud rate (BRGH = 1), or the 16-bit BRG
to reduce the baud rate error, or achieve a slow baud
rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
20.1.1 OPERATION IN POWER-MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
20.1.2 SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 20-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)]
0 0 1 8-bit/Asynchronous
FOSC/[16 (n + 1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
PIC18F2455/2550/4455/4550
DS39632E-page 248 © 2009 Microchip Technology Inc.
EXAMPLE 20-1: CALCULATING BAUD RATE ERROR
TABLE 20-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2009 Microchip Technology Inc. DS39632E-page 249
PIC18F2455/2550/4455/4550
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51
1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12
2.4 2.404 0.16 25 2.403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
PIC18F2455/2550/4455/4550
DS39632E-page 250 © 2009 Microchip Technology Inc.
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207
1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51
2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25
9.6 9.615 0.16 25 9.615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832
1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207
2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103
9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25
19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12
57.6 58.824 2.12 16 55.555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
© 2009 Microchip Technology Inc. DS39632E-page 251
PIC18F2455/2550/4455/4550
20.1.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 20-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value, 55h (ASCII
“U”, which is also the LIN bus Sync character), in order
to calculate the proper bit rate. The measurement is
taken over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming
signal. After a Start bit, the SPBRG begins counting up,
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin, or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG register pair.
Once the 5th edge is seen (this should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG
rollovers and can be set or cleared by the user in
software. ABD mode remains active after rollover
events and the ABDEN bit remains set (Figure 20-2).
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 20-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
TABLE 20-4: BRG COUNTER
CLOCK RATES
20.1.3.1 ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisition,
the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
BRG16 BRGH BRG Counter Clock
0 0 FOSC/512
0 1 FOSC/128
1 0 FOSC/128
1 1 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
PIC18F2455/2550/4455/4550
DS39632E-page 252 © 2009 Microchip Technology Inc.
FIGURE 20-1: AUTOMATIC BAUD RATE CALCULATION
FIGURE 20-2: BRG OVERFLOW SEQUENCE
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Set by User Auto-Cleared
XXXXh 0000h
Edge #1
bit 2 bit 3
Edge #2
bit 4 bit 5
Edge #3
bit 6 bit 7
Edge #4
001Ch
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
SPBRG XXXXh 1Ch
SPBRGH XXXXh 00h
Stop bit
Edge #5
Start bit 0
XXXXh 0000h 0000h
FFFFh
BRG Clock
ABDEN bit
RX pin
ABDOVF bit
BRG Value
© 2009 Microchip Technology Inc. DS39632E-page 253
PIC18F2455/2550/4455/4550
20.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ)
format (one Start bit, eight or nine data bits and one
Stop bit). The most common data format is 8 bits. An
on-chip dedicated 8-bit/16-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
The TXCKP (BAUDCON<4>) and RXDTP
(BAUDCON<5>) bits allow the TX and RX signals to be
inverted (polarity reversed). Devices that buffer signals
between TTL and RS-232 levels also invert the signal.
Setting the TXCKP and RXDTP bits allows for the use of
circuits that provide buffering without inverting the signal.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Break signal
• 12-Bit Break Character Transmit
• Auto-Baud Rate Detection
• Pin State Polarity
20.2.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
The TXCKP bit (BAUDCON<4>) allows the TX signal to
be inverted (polarity reversed). Devices that buffer
signals from TTL to RS-232 levels also invert the signal
(when TTL = 1, RS-232 = negative). Inverting the polarity
of the TX pin data by setting the TXCKP bit allows for
use of circuits that provide buffering without inverting the
signal.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If the signal from the TX pin is to be inverted, set
the TXCKP bit.
4. If interrupts are desired, set enable bit, TXIE.
5. If 9-bit transmission is desired, set transmit bit,
TX9. Can be used as address/data bit.
6. Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
8. Load data to the TXREG register (starts
transmission).
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit, TXIF, is set when enable bit,
TXEN, is set.
PIC18F2455/2550/4455/4550
DS39632E-page 254 © 2009 Microchip Technology Inc.
FIGURE 20-3: EUSART TRANSMIT BLOCK DIAGRAM
FIGURE 20-4: ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TX NOT INVERTED)
FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK),
TXCKP = 0 (TX NOT INVERTED)
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
TX pin
Pin Buffer
and Control
8
• • •
BRG16 SPBRGH
TXCKP
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit
© 2009 Microchip Technology Inc. DS39632E-page 255
PIC18F2455/2550/4455/4550
TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
TXREG EUSART Transmit Register 55
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632E-page 256 © 2009 Microchip Technology Inc.
20.2.2 EUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 20-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
The RXDTP bit (BAUDCON<5>) allows the RX signal to
be inverted (polarity reversed). Devices that buffer
signals from RS-232 to TTL levels also perform an inversion
of the signal (when RS-232 = positive, TTL = 0).
Inverting the polarity of the RX pin data by setting the
RXDTP bit allows for the use of circuits that provide
buffering without inverting the signal.
To set up an Asynchronous Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
3. If the signal at the RX pin is to be inverted, set
the RXDTP bit.
4. If interrupts are desired, set enable bit, RCIE.
5. If 9-bit reception is desired, set bit, RX9.
6. Enable the reception by setting bit, CREN.
7. Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCIE, was set.
8. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
enable bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
20.2.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If the signal at the RX pin is to be inverted, set
the RXDTP bit. If the signal from the TX pin is to
be inverted, set the TXCKP bit.
4. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
5. Set the RX9 bit to enable 9-bit reception.
6. Set the ADDEN bit to enable address detect.
7. Enable reception by setting the CREN bit.
8. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
9. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
10. Read RCREG to determine if the device is being
addressed.
11. If any error occurred, clear the CREN bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
© 2009 Microchip Technology Inc. DS39632E-page 257
PIC18F2455/2550/4455/4550
FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM
FIGURE 20-7: ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED)
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
RCREG EUSART Receive Register 55
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
x64 Baud Rate CLK
Baud Rate Generator
RX
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
MSb RSR Register LSb
RX9D RCREG Register
FIFO
Interrupt RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or
Stop (8) 7 1 0 Start
RX9
• • •
BRG16 SPBRGH SPBRG
or
÷ 4
RXDTP
Start
bit bit 0 bit 1 bit 7/8 Stop bit 0 bit 7/8
bit
Start
bit
Start
bit 7/8 Stop bit
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
PIC18F2455/2550/4455/4550
DS39632E-page 258 © 2009 Microchip Technology Inc.
20.2.4 AUTO-WAKE-UP ON SYNC
BREAK CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be performed.
The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event
consists of a high-to-low transition on the RX/DT line.
(This coincides with the start of a Sync Break or a
Wake-up Signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchronously
to the Q clocks in normal operating modes
(Figure 20-8) and asynchronously, if the device is in
Sleep mode (Figure 20-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-tohigh
transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
20.2.4.1 Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state
changes before the Stop bit may signal a false End-Of-
Character and cause data or framing errors. To work
properly, therefore, the initial character in the transmission
must be all ‘0’s. This can be 00h (8 bits) for
standard RS-232 devices or 000h (12 bits) for LIN bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
20.2.4.2 Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit is
cleared after this when a rising edge is seen on RX/DT.
The interrupt condition is then cleared by reading the
RCREG register. Ordinarily, the data in RCREG will be
dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 20-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
FIGURE 20-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX/DT Line
RCIF
Note 1: The EUSART remains in Idle while the WUE bit is set.
Bit set by user
Cleared due to user read of RCREG
Auto-Cleared
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX/DT Line
RCIF
Bit set by user
Cleared due to user read of RCREG
Sleep Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
Note 1
Auto-Cleared
© 2009 Microchip Technology Inc. DS39632E-page 259
PIC18F2455/2550/4455/4550
20.2.5 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set while the Transmit Shift Register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmission.
See Figure 20-10 for the timing of the Break
character sequence.
20.2.5.1 Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to set up the
Break character.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
20.2.6 RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and 8 data
bits for typical data).
The second method uses the auto-wake-up feature
described in Section 20.2.4 “Auto-Wake-up on Sync
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.
FIGURE 20-10: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
BRG Output
(Shift Clock)
Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TX (pin)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here Auto-Cleared
Dummy Write
PIC18F2455/2550/4455/4550
DS39632E-page 260 © 2009 Microchip Technology Inc.
20.3 EUSART Synchronous
Master Mode
The Synchronous Master mode is entered by setting
the CSRC bit (TXSTA<7>). In this mode, the data is
transmitted in a half-duplex manner (i.e., transmission
and reception do not occur at the same time). When
transmitting data, the reception is inhibited and vice
versa. Synchronous mode is entered by setting bit,
SYNC (TXSTA<4>). In addition, enable bit, SPEN
(RCSTA<7>), is set in order to configure the TX and RX
pins to CK (clock) and DT (data) lines, respectively.
The Master mode indicates that the processor
transmits the master clock on the CK line.
Clock polarity (CK) is selected with the TXCKP bit
(BAUDCON<4>). Setting TXCKP sets the Idle state on
CK as high, while clearing the bit sets the Idle state as
low. Data polarity (DT) is selected with the RXDTP bit
(BAUDCON<5>). Setting RXDTP sets the Idle state on
DT as high, while clearing the bit sets the Idle state as
low. DT is sampled when CK returns to its idle state.
This option is provided to support Microwire devices
with this module.
20.3.1 EUSART SYNCHRONOUS MASTER
TRANSMISSION
The EUSART transmitter block diagram is shown in
Figure 20-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG is empty and
the TXIF flag bit (PIR1<4>) is set. The interrupt can be
enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF is set regardless of
the state of enable bit, TXIE; it cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register.
While flag bit, TXIF, indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. TRMT is a read-only bit which
is set when the TSR is empty. No interrupt logic is tied to
this bit so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not
mapped in data memory so it is not available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit, TXIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting bit, TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 20-11: SYNCHRONOUS TRANSMISSION
bit 0 bit 1 bit 7
Word 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4 Q1Q2 Q3 Q4Q1 Q2 Q3 Q4
bit 2 bit 0 bit 1 bit 7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit ‘1’ ‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
RC6/TX/CK pin
(TXCKP = 0)
(TXCKP = 1)
RC7/RX/DT/
SDO pin
© 2009 Microchip Technology Inc. DS39632E-page 261
PIC18F2455/2550/4455/4550
FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RC7/RX/DT/SDO pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
TXREG EUSART Transmit Register 55
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632E-page 262 © 2009 Microchip Technology Inc.
20.3.2 EUSART SYNCHRONOUS
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>), or the Continuous Receive
Enable bit, CREN (RCSTA<4>). Data is sampled on the
RX pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRG16
bit, as required, to achieve the desired baud rate.
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Ensure bits, CREN and SREN, are clear.
4. If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
5. If interrupts are desired, set enable bit, RCIE.
6. If 9-bit reception is desired, set bit, RX9.
7. If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
8. Interrupt flag bit, RCIF, will be set when reception
is complete and an interrupt will be generated if
the enable bit, RCIE, was set.
9. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If any error occurred, clear the error by clearing
bit, CREN.
12. If using interrupts, ensure that the GIE and PEIE bits
in the INTCON register (INTCON<7:6>) are set.
FIGURE 20-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
RCREG EUSART Receive Register 55
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RC7/RX/DT/SDO
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
RC6/TX/CK pin
pin
(TXCKP = 0)
(TXCKP = 1)
© 2009 Microchip Technology Inc. DS39632E-page 263
PIC18F2455/2550/4455/4550
20.4 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is supplied
externally at the CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any power-managed
mode.
20.4.1 EUSART SYNCHRONOUS
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in the TXREG
register.
c) Flag bit, TXIF, will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit, TXIF, will now be set.
e) If enable bit, TXIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXIE.
4. If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
5. If 9-bit transmission is desired, set bit, TX9.
6. Enable the transmission by setting enable bit,
TXEN.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
8. Start transmission by loading data to the TXREG
register.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
TXREG EUSART Transmit Register 55
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
PIC18F2455/2550/4455/4550
DS39632E-page 264 © 2009 Microchip Technology Inc.
20.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the chip from the lowpower
mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RCIE.
3. If the signal from the CK pin is to be inverted, set
the TXCKP bit. If the signal from the DT pin is to
be inverted, set the RXDTP bit.
4. If 9-bit reception is desired, set bit, RX9.
5. To enable reception, set enable bit, CREN.
6. Flag bit, RCIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCIE, was set.
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
bit, CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 55
RCREG EUSART Receive Register 55
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 55
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 55
SPBRGH EUSART Baud Rate Generator Register High Byte 55
SPBRG EUSART Baud Rate Generator Register Low Byte 55
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
© 2009 Microchip Technology Inc. DS39632E-page 265
PIC18F2455/2550/4455/4550
21.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) converter module has
10 inputs for the 28-pin devices and 13 for the
40/44-pin devices. This module allows conversion of an
analog input signal to a corresponding 10-bit digital
number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
The ADCON0 register, shown in Register 21-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 21-2, configures
the functions of the port pins. The ADCON2 register,
shown in Register 21-3, configures the A/D clock
source, programmed acquisition time and justification.
REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000 = Channel 0 (AN0)
0001 = Channel 1 (AN1)
0010 = Channel 2 (AN2)
0011 = Channel 3 (AN3)
0100 = Channel 4 (AN4)
0101 = Channel 5 (AN5)(1,2)
0110 = Channel 6 (AN6)(1,2)
0111 = Channel 7 (AN7)(1,2)
1000 = Channel 8 (AN8)
1001 = Channel 9 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = Unimplemented(2)
1110 = Unimplemented(2)
1111 = Unimplemented(2)
bit 1 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
bit 0 ADON: A/D On bit
1 = A/D converter module is enabled
0 = A/D converter module is disabled
Note 1: These channels are not implemented on 28-pin devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.
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REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0(1) R/W(1) R/W(1) R/W(1)
— — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = VSS
bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = VDD
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1: The POR value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2: AN5 through AN7 are available only on 40/44-pin devices.
A = Analog input D = Digital I/O
PCFG3:
PCFG0
AN12
AN11
AN10
AN9
AN8
AN7(2)
AN6(2)
AN5(2)
AN4
AN3
AN2
AN1
AN0
0000(1) A A A A A A A A A A A A A
0001 A A A A A A A A A A A A A
0010 A A A A A A A A A A A A A
0011 D A A A A A A A A A A A A
0100 D D A A A A A A A A A A A
0101 D D D A A A A A A A A A A
0110 D D D D A A A A A A A A A
0111(1) D D D D D A A A A A A A A
1000 D D D D D D A A A A A A A
1001 D D D D D D D A A A A A A
1010 D D D D D D D D A A A A A
1011 D D D D D D D D D A A A A
1100 D D D D D D D D D D A A A
1101 D D D D D D D D D D D A A
1110 D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D
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REGISTER 21-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6 Unimplemented: Read as ‘0’
bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 TAD
110 = 16 TAD
101 = 12 TAD
100 = 8 TAD
011 = 6 TAD
010 = 4 TAD
001 = 2 TAD
000 = 0 TAD(1)
bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator)(1)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator)(1)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
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The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF-/CVREF pins.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete,
the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The
block diagram of the A/D module is shown in
Figure 21-1.
FIGURE 21-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
Reference
Voltage
VDD(2)
VCFG1:VCFG0
CHS3:CHS0
AN7(1)
AN6(1)
AN5(1)
AN4
AN3
AN2
AN1
AN0
0111
0110
0101
0100
0011
0010
0001
0000
10-Bit
Converter
VREFVSS(
2)
A/D
AN12
AN11
AN10
AN9
AN8
1100
1011
1010
1001
1000
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
0X
1X
X1
X0
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The value in the ADRESH:ADRESL registers is
unknown following POR and BOR Resets and is not
affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion
is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 21.1
“A/D Acquisition Requirements”. After this acquisition
time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to perform an
A/D conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 3 TAD is
required before the next acquisition starts.
FIGURE 21-2: A/D TRANSFER FUNCTION
FIGURE 21-3: ANALOG INPUT MODEL
Digital Code Output
3FEh
003h
002h
001h
000h
0.5 LSB
1 LSB
1.5 LSB
2 LSB
2.5 LSB
1022 LSB
1022.5 LSB
3 LSB
Analog Input Voltage
3FFh
1023 LSB
1023.5 LSB
VAIN CPIN
Rs ANx
5 pF
VT = 0.6V
VT = 0.6V
ILEAKAGE
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD = 25 pF
VSS
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/hold Capacitance (from DAC)
various junctions
RSS = Sampling Switch Resistance
VDD
6V
Sampling Switch
5V
4V
3V
2V
1 2 3 4
(kΩ)
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21.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 21-3. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), the channel must be sampled for
at least the minimum acquisition time before starting a
conversion.
To calculate the minimum acquisition time,
Equation 21-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 21-3 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system
assumptions:
CHOLD = 25 pF
Rs = 2.5 kΩ
Conversion Error ≤ 1/2 LSb
VDD = 5V → RSS = 2 kΩ
Temperature = 85°C (system max.)
EQUATION 21-1: ACQUISITION TIME
EQUATION 21-2: A/D MINIMUM CHARGING TIME
EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note: When the conversion is started, the
holding capacitor is disconnected from the
input pin.
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)
TACQ = TAMP + TC + TCOFF
TAMP = 0.2 μs
TCOFF = (Temp – 25°C)(0.02 μs/°C)
(85°C – 25°C)(0.02 μs/°C)
1.2 μs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 μs.
TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) μs
-(25 pF) (1 kΩ + 2 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.05 μs
TACQ = 0.2 μs + 1.05 μs + 1.2 μs
2.45 μs
© 2009 Microchip Technology Inc. DS39632E-page 271
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21.2 Selecting and Configuring
Acquisition Time
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>) which provide a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisition
time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
Manual acquisition is selected when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
21.3 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 11 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible but greater than the
minimum TAD (see parameter 130 in Table 28-29 for
more information).
Table 21-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 21-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Assumes TAD Min. = 0.8 μs
Operation ADCS2:ADCS0 Maximum FOSC
2 TOSC 000 2.50 MHz
4 TOSC 100 5.00 MHz
8 TOSC 001 10.00 MHz
16 TOSC 101 20.00 MHz
32 TOSC 010 40.00 MHz
64 TOSC 110 48.00 MHz
RC(2) x11 1.00 MHz(1)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead. Otherwise, the A/D accuracy may be out of specification.
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21.4 Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ACQT2:ACQT0 and
ADCS2:ADCS0 bits in ADCON2 should be updated in
accordance with the clock source to be used in that
mode. After entering the mode, an A/D acquisition or
conversion may be started. Once started, the device
should continue to be clocked by the same clock
source until the conversion has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in the Sleep mode requires the A/D FRC
clock to be selected. If bits ACQT2:ACQT0 are set to
‘000’ and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
21.5 Configuring Analog Port Pins
The ADCON1, TRISA, TRISB and TRISE registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured
as digital inputs will convert as
analog inputs. Analog levels on a digitally
configured input will be accurately
converted.
2: Analog levels on any pin defined as a
digital input may cause the digital input
buffer to consume current out of the
device’s specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by controlling
how the PCFG0 bits in ADCON1 are
reset.
© 2009 Microchip Technology Inc. DS39632E-page 273
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21.6 A/D Conversions
Figure 21-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 21-5 shows the operation of the A/D converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 TAD acquisition time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D conversion sample. This means the
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 TCY wait is required before the next acquisition can be
started. After this wait, acquisition on the selected
channel is automatically started.
21.7 Discharge
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the
unity-gain amplifier as the circuit always needs to
charge the capacitor array, rather than
charge/discharge based on previous measurement
values.
FIGURE 21-4: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
FIGURE 21-5: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11
Set GO/DONE bit
Holding capacitor is disconnected from analog input (typically 100 ns)
TCY - TAD TAD9 TAD10
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion starts
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
On the following cycle:
TAD1
Discharge
(Typically 200 ns)
1 2 3 4 5 6 7 8 11
Set GO/DONE bit
(Holding capacitor is disconnected)
9 10
Conversion starts
1 2 3 4
(Holding capacitor continues
acquiring input)
TACQ Cycles TAD Cycles
Automatic
Acquisition
Time
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
On the following cycle:
TAD1
Discharge
(Typically
200 ns)
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21.8 Use of the CCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automatically
repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
desired location). The appropriate analog input channel
must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR1 SPPIF(4) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(4) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(4) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
ADRESH A/D Result Register High Byte 54
ADRESL A/D Result Register Low Byte 54
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 54
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 54
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 54
PORTA — RA6(2) RA5 RA4 RA3 RA2 RA1 RA0 56
TRISA — TRISA6(2) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 56
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 56
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 56
PORTE RDPU(4) — — — RE3(1,3) RE2(4) RE1(4) RE0(4) 56
TRISE(4) — — — — — TRISE2 TRISE1 TRISE0 56
LATE(4) — — — — — LATE2 LATE1 LATE0 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
4: These registers and/or bits are not implemented on 28-pin devices.
© 2009 Microchip Technology Inc. DS39632E-page 275
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22.0 COMPARATOR MODULE
The analog comparator module contains two comparators
that can be configured in a variety of ways. The
inputs can be selected from the analog inputs multiplexed
with pins RA0 through RA5, as well as the on-chip voltage
reference (see Section 23.0 “Comparator Voltage
Reference Module”). The digital outputs (normal or
inverted) are available at the pin level and can also be
read through the control register.
The CMCON register (Register 22-1) selects the
comparator input and output configuration. Block
diagrams of the various comparator configurations are
shown in Figure 22-1.
REGISTER 22-1: CMCON: COMPARATOR CONTROL REGISTER
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VINWhen
C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VINbit
6 C1OUT: Comparator 1 Output bit
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VINWhen
C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VINbit
5 C2INV: Comparator 2 Output Inversion bit
1 = C2 output inverted
0 = C2 output not inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 output inverted
0 = C1 output not inverted
bit 3 CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1 = C1 VIN- connects to RA3/AN3/VREF+
C2 VIN- connects to RA2/AN2/VREF-/CVREF
0 = C1 VIN- connects to RA0/AN0
C2 VIN- connects to RA1/AN1
bit 2-0 CM2:CM0: Comparator Mode bits
Figure 22-1 shows the Comparator modes and the CM2:CM0 bit settings.
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22.1 Comparator Configuration
There are eight modes of operation for the comparators,
shown in Figure 22-1. Bits, CM2:CM0 of the
CMCON register, are used to select these modes. The
TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Section 28.0 “Electrical Characteristics”.
FIGURE 22-1: COMPARATOR I/O OPERATING MODES
Note: Comparator interrupts should be disabled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
C1
RA0/AN0 VINRA3/
AN3/ VIN+
Off (Read as ‘0’)
Comparators Reset
A
A
CM2:CM0 = 000
C2
RA1/AN1 VINRA2/
AN2/ VIN+
Off (Read as ‘0’)
A
A
C1
VINVIN+
C1OUT
Two Independent Comparators
A
A
CM2:CM0 = 010
C2
VINVIN+
C2OUT
A
A
C1
VINVIN+
C1OUT
Two Common Reference Comparators
A
A
CM2:CM0 = 100
C2
VINVIN+
C2OUT
A
D
C2
VINVIN+
Off (Read as ‘0’)
One Independent Comparator with Output
D
D
CM2:CM0 = 001
C1
VINVIN+
C1OUT
A
A
C1
VINVIN+
Off (Read as ‘0’)
Comparators Off (POR Default Value)
D
D
CM2:CM0 = 111
C2
VINVIN+
Off (Read as ‘0’)
D
D
C1
VINVIN+
C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM2:CM0 = 110
C2
VINVIN+
C2OUT
A
A
From VREF Module
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
VINVIN+
C1OUT
Two Common Reference Comparators with Outputs
A
A
CM2:CM0 = 101
C2
VINVIN+
C2OUT
A
D
A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch
CVREF
C1
VINVIN+
C1OUT
Two Independent Comparators with Outputs
A
A
CM2:CM0 = 011
C2
VINVIN+
C2OUT
A
A
RA5/AN4/SS/HLVDIN/C2OUT*
RA4/T0CKI/C1OUT*/RCV
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
RA1/AN1
RA2/AN2/
VREF+
VREF-/CVREF
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
RA2/AN2/
VREF-/CVREF
RA4/T0CKI/C1OUT*/RCV
RA5/AN4/SS/HLVDIN/C2OUT*
RA0/AN0
RA3/AN3/
VREF+
RA1/AN1
RA2/AN2/
VREF-/CVREF
RA4/T0CKI/C1OUT*/
* Setting the TRISA<5:4> bits will disable the comparator outputs by configuring the pins as inputs.
RCV
© 2009 Microchip Technology Inc. DS39632E-page 277
PIC18F2455/2550/4455/4550
22.2 Comparator Operation
A single comparator is shown in Figure 22-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 22-2 represent
the uncertainty, due to input offsets and response time.
22.3 Comparator Reference
Depending on the comparator operating mode, either
an external or internal voltage reference may be used.
The analog signal present at VIN- is compared to the
signal at VIN+ and the digital output of the comparator
is adjusted accordingly (Figure 22-2).
FIGURE 22-2: SINGLE COMPARATOR
22.3.1 EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators
operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
22.3.2 INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference from the
comparator voltage reference module. This module is
described in more detail in Section 23.0 “Comparator
Voltage Reference Module”.
The internal reference is only available in the mode
where four inputs are multiplexed to two comparators
(CM2:CM0 = 110). In this mode, the internal voltage
reference is applied to the VIN+ pin of both
comparators.
22.4 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal reference
is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (see Section 28.0
“Electrical Characteristics”).
22.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RA4 and RA5
I/O pins. When enabled, multiplexors in the output path
of the RA4 and RA5 pins will switch and the output of
each pin will be the unsynchronized output of the
comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 22-3 shows the comparator output block
diagram.
The TRISA bits will still function as an output enable/
disable for the RA4 and RA5 pins while in this mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<5:4>).
–
VIN+ +
VINOutput
Output
VINVIN+
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
PIC18F2455/2550/4455/4550
DS39632E-page 278 © 2009 Microchip Technology Inc.
FIGURE 22-3: COMPARATOR OUTPUT BLOCK DIAGRAM
22.6 Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR2<6>) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing it. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<
6>) must be set to enable the interrupt. In addition,
the GIE bit (INTCON<7>) must also be set. If any
of these bits are clear, the interrupt is not enabled,
though the CMIF bit will still be set if an interrupt
condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
22.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current, as shown in the comparator specifications. To
minimize power consumption while in Sleep mode, turn
off the comparators (CM2:CM0 = 111) before entering
Sleep. If the device wakes up from Sleep, the contents
of the CMCON register are not affected.
22.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator modules to be turned off
(CM2:CM0 = 111). However, the input pins (RA0
through RA3) are configured as analog inputs by
default on device Reset. The I/O configuration for these
pins is determined by the setting of the PCFG3:PCFG0
bits (ADCON1<3:0>). Therefore, device current is
minimized when analog inputs are present at Reset
time.
D Q
EN
To CxOUT
pin
Bus
Data
Set
MULTIPLEX
CMIF
bit
+
Port Pins
Read CMCON
Reset
From
Other
Comparator
CxINV
D Q
EN CL
-
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR2<6>)
interrupt flag may not get set.
© 2009 Microchip Technology Inc. DS39632E-page 279
PIC18F2455/2550/4455/4550
22.9 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 22-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 22-4: COMPARATOR ANALOG INPUT MODEL
TABLE 22-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
VA
RS < 10k
AIN
CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
Comparator
Input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
PORTA — RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 56
LATA — LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 56
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various
oscillator modes. When disabled, these bits read as ‘0’.
PIC18F2455/2550/4455/4550
DS39632E-page 280 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 281
PIC18F2455/2550/4455/4550
23.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable reference
voltage. Although its primary purpose is to provide a
reference for the analog comparators, it may also be
used independently of them.
A block diagram of the module is shown in Figure 23-1.
The resistor ladder is segmented to provide two ranges
of CVREF values and has a power-down function to
conserve power when the reference is not being used.
The module’s supply reference can be provided from
either device VDD/VSS or an external voltage reference.
23.1 Configuring the Comparator
Voltage Reference
The voltage reference module is controlled through the
CVRCON register (Register 23-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
The equations used to calculate the output of the
comparator voltage reference are as follows:
If CVRR = 1:
CVREF = ((CVR3:CVR0)/24) x CVRSRC
If CVRR = 0:
CVREF = (CVRSRC/4) + (((CVR3:CVR0)/32) x
CVRSRC)
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF- that are multiplexed with RA2 and RA3. The
voltage source is selected by the CVRSS bit
(CVRCON<4>).
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output (see Table 28-3 in Section 28.0 “Electrical
Characteristics”).
REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CVREN: Comparator Voltage Reference Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down
bit 6 CVROE: Comparator VREF Output Enable bit(1)
1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF pin
0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF pin
bit 5 CVRR: Comparator VREF Range Selection bit
1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
bit 4 CVRSS: Comparator VREF Source Selection bit
1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator reference source, CVRSRC = VDD – VSS
bit 3-0 CVR3:CVR0: Comparator VREF Value Selection bits (0 ≤ (CVR3:CVR0) ≤ 15)
When CVRR = 1:
CVREF = ((CVR3:CVR0)/24) • (CVRSRC)
When CVRR = 0:
CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) • (CVRSRC)
Note 1: CVROE overrides the TRISA<2> bit setting.
PIC18F2455/2550/4455/4550
DS39632E-page 282 © 2009 Microchip Technology Inc.
FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
23.2 Voltage Reference Accuracy/Error
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 23-1) keep CVREF from approaching the reference
source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
23.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
23.4 Effects of a Reset
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
23.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RA2 pin if the
TRISA<2> bit and the CVROE bit are both set.
Enabling the voltage reference output onto RA2 when
it is configured as a digital input will increase current
consumption. Connecting RA2 as a digital output with
CVRSS enabled will also increase current
consumption.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to VREF.
Figure 23-2 shows an example buffering technique.
16-to-1 MUX
CVR3:CVR0
8R
CVREN R
CVRSS = 0
VDD
VREF+
CVRSS = 1
8R
CVRSS = 0
VREFCVRSS
= 1
R
R
R
R
R
R
16 Steps
CVRR
CVREF
© 2009 Microchip Technology Inc. DS39632E-page 283
PIC18F2455/2550/4455/4550
FIGURE 23-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CVREF Output
+–
CVREF
Module
Voltage
Reference
Output
Impedance
R(1)
RA2
Note 1: R is dependent upon the voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>.
PIC18FXXXX
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 55
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 55
TRISA — TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 56
Legend: Shaded cells are not used with the comparator voltage reference.
Note 1: PORTA<6> and its direction and latch bits are individually configured as port pins based on various
oscillator modes. When disabled, these bits read as ‘0’.
PIC18F2455/2550/4455/4550
DS39632E-page 284 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 285
PIC18F2455/2550/4455/4550
24.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
PIC18F2455/2550/4455/4550 devices have a
High/Low-Voltage Detect module (HLVD). This is a programmable
circuit that allows the user to specify both a
device voltage trip point and the direction of change
from that point. If the device experiences an excursion
past the trip point in that direction, an interrupt flag is
set. If the interrupt is enabled, the program execution
will branch to the interrupt vector address and the
software can then respond to the interrupt.
The High/Low-Voltage Detect Control register
(Register 24-1) completely controls the operation of the
HLVD module. This allows the circuitry to be “turned
off” by the user under software control which minimizes
the current consumption for the device.
The block diagram for the HLVD module is shown in
Figure 24-1.
REGISTER 24-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
VDIRMAG — IRVST HLVDEN HLVDL3(1) HLVDL2(1) HLVDL1(1) HLVDL0(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VDIRMAG: Voltage Direction Magnitude Select bit
1 = Event occurs when voltage equals or exceeds trip point (HLVDL3:HLDVL0)
0 = Event occurs when voltage equals or falls below trip point (HLVDL3:HLVDL0)
bit 6 Unimplemented: Read as ‘0’
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage range
0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage
range and the HLVD interrupt should not be enabled
bit 4 HLVDEN: High/Low-Voltage Detect Power Enable bit
1 = HLVD enabled
0 = HLVD disabled
bit 3-0 HLVDL3:HLVDL0: Voltage Detection Limit bits(1)
1111 = External analog input is used (input comes from the HLVDIN pin)
1110 = Maximum setting
.
.
.
0000 = Minimum setting
Note 1: See Table 28-6 in Section 28.0 “Electrical Characteristics” for specifications.
PIC18F2455/2550/4455/4550
DS39632E-page 286 © 2009 Microchip Technology Inc.
The module is enabled by setting the HLVDEN bit.
Each time that the HLVD module is enabled, the
circuitry requires some time to stabilize. The IRVST bit
is a read-only bit and is used to indicate when the circuit
is stable. The module can only generate an interrupt
after the circuit is stable and IRVST is set.
The VDIRMAG bit determines the overall operation of
the module. When VDIRMAG is cleared, the module
monitors for drops in VDD below a predetermined set
point. When the bit is set, the module monitors for rises
in VDD above the set point.
24.1 Operation
When the HLVD module is enabled, a comparator uses
an internally generated reference voltage as the set
point. The set point is compared with the trip point,
where each node in the resistor divider represents a
trip point voltage. The “trip point” voltage is the voltage
level at which the device detects a high or low-voltage
event, depending on the configuration of the module.
When the supply voltage is equal to the trip point, the
voltage tapped off of the resistor array is equal to the
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal by setting the HLVDIF bit.
The trip point voltage is software programmable to any
one of 16 values. The trip point is selected by
programming the HLVDL3:HLVDL0 bits
(HLVDCON<3:0>).
The HLVD module has an additional feature that allows
the user to supply the trip voltage to the module from an
external source. This mode is enabled when bits,
HLVDL3:HLVDL0, are set to ‘1111’. In this state, the
comparator input is multiplexed from the external input
pin, HLVDIN. This gives users flexibility because it
allows them to configure the High/Low-Voltage Detect
interrupt to occur at any voltage in the valid operating
range.
FIGURE 24-1: HLVD MODULE BLOCK DIAGRAM (WITH EXTERNAL INPUT)
Set
VDD
16-to-1 MUX
HLVDEN
HLVDL3:HLVDL0 HLVDCON
Register
HLVDIN
VDD
Externally Generated
Trip Point
HLVDIF
HLVDEN
BOREN
Internal Voltage
Reference
VDIRMAG
1.2V Typical
© 2009 Microchip Technology Inc. DS39632E-page 287
PIC18F2455/2550/4455/4550
24.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Disable the module by clearing the HLVDEN bit
(HLVDCON<4>).
2. Write the value to the HLVDL3:HLVDL0 bits that
selects the desired HLVD trip point.
3. Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
4. Enable the HLVD module by setting the
HLVDEN bit.
5. Clear the HLVD Interrupt Flag, HLVDIF
(PIR2<2>), which may have been set from a
previous interrupt.
6. Enable the HLVD interrupt, if interrupts are
desired, by setting the HLVDIE and GIE/GIEH
bits (PIE2<2> and INTCON<7>). An interrupt
will not be generated until the IRVST bit is set.
24.3 Current Consumption
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022
(Section 28.2 “DC Characteristics”).
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
24.4 HLVD Start-up Time
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420 (see
Table 28-6 in Section 28.0 “Electrical Characteristics”),
may be used by other internal circuitry, such as
the Programmable Brown-out Reset. If the HLVD or
other circuits using the voltage reference are disabled to
lower the device’s current consumption, the reference
voltage circuit will require time to become stable before
a low or high-voltage condition can be reliably detected.
This start-up time, TIRVST, is an interval that is independent
of device clock speed. It is specified in electrical
specification parameter 36 (Table 28-12).
The HLVD interrupt flag is not enabled until TIRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to
Figure 24-2 or Figure 24-3.
FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
VHLVD
VDD
HLVDIF
VHLVD
VDD
Enable HLVD
TIRVST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared in software
HLVDIF cleared in software
HLVDIF cleared in software,
CASE 1:
CASE 2:
HLVDIF remains set since HLVD condition still exists
TIRVST
Internal Reference is stable
Internal Reference is stable
IRVST
IRVST
PIC18F2455/2550/4455/4550
DS39632E-page 288 © 2009 Microchip Technology Inc.
FIGURE 24-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1)
24.5 Applications
In many applications, the ability to detect a drop below
or rise above a particular threshold is desirable. For
example, the HLVD module could be periodically
enabled to detect Universal Serial Bus (USB) attach or
detach. This assumes the device is powered by a lower
voltage source than the USB when detached. An attach
would indicate a high-voltage detect from, for example,
3.3V to 5V (the voltage on USB) and vice versa for a
detach. This feature could save a design a few extra
components and an attach signal (input pin).
For general battery applications, Figure 24-4 shows a
possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage,
VA, the HLVD logic generates an interrupt at time, TA.
The interrupt could cause the execution of an ISR,
which would allow the application to perform “housekeeping
tasks” and perform a controlled shutdown
before the device voltage exits the valid operating
range at TB. The HLVD, thus, would give the application
a time window, represented by the difference
between TA and TB, to safely exit.
FIGURE 24-4: TYPICAL
HIGH/LOW-VOLTAGE
DETECT APPLICATION
VHLVD
VDD
HLVDIF
VHLVD
VDD
Enable HLVD
TIRVST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared in software
HLVDIF cleared in software
HLVDIF cleared in software,
CASE 1:
CASE 2:
HLVDIF remains set since HLVD condition still exists
TIRVST
IRVST
Internal Reference is stable
Internal Reference is stable
IRVST
Time
Voltage
VA
VB
TA TB
VA = HLVD trip point
VB = Minimum valid device
operating voltage
Legend:
© 2009 Microchip Technology Inc. DS39632E-page 289
PIC18F2455/2550/4455/4550
24.6 Operation During Sleep
When enabled, the HLVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the HLVDIF bit will be set and the device will
wake-up from Sleep. Device execution will continue
from the interrupt vector address if interrupts have
been globally enabled.
24.7 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the HLVD module to be turned off.
TABLE 24-1: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 54
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module.
PIC18F2455/2550/4455/4550
DS39632E-page 290 © 2009 Microchip Technology Inc.
NOTES:
© 2009 Microchip Technology Inc. DS39632E-page 291
PIC18F2455/2550/4455/4550
25.0 SPECIAL FEATURES OF THE
CPU
PIC18F2455/2550/4455/4550 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up Timers
provided for Resets, PIC18F2455/2550/4455/4550
devices have a Watchdog Timer, which is either
permanently enabled via the Configuration bits or
software controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure.
Two-Speed Start-up enables code to be executed
almost immediately on start-up, while the primary clock
source completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
PIC18F2455/2550/4455/4550
DS39632E-page 292 © 2009 Microchip Technology Inc.
25.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads and
table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction, with the TBLPTR pointing to the
Configuration register, sets up the address and the
data for the Configuration register write. Setting the WR
bit starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 6.5 “Writing
to Flash Program Memory”.
TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
300000h CONFIG1L — — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0 --00 0000
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0101
300002h CONFIG2L — — VREGEN BORV1 BORV0 BOREN1 BOREN0 PWRTEN --01 1111
300003h CONFIG2H — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE — — — — LPT1OSC PBADEN CCP2MX 1--- -011
300006h CONFIG4L DEBUG XINST ICPRT(3) — — LVP — STVREN 100- -1-1
300008h CONFIG5L — — — — CP3(1) CP2 CP1 CP0 ---- 1111
300009h CONFIG5H CPD CPB — — — — — — 11-- ----
30000Ah CONFIG6L — — — — WRT3(1) WRT2 WRT1 WRT0 ---- 1111
30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ----
30000Ch CONFIG7L — — — — EBTR3(1) EBTR2 EBTR1 EBTR0 ---- 1111
30000Dh CONFIG7H — EBTRB — — — — — — -1-- ----
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(2)
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0001 0010(2)
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
2: See Register 25-13 and Register 25-14 for DEVID values. DEVID registers are read-only and cannot be programmed by
the user.
3: Available only on PIC18F4455/4550 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices.
© 2009 Microchip Technology Inc. DS39632E-page 293
PIC18F2455/2550/4455/4550
REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h)
U-0 U-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0 R/P-0
— — USBDIV CPUDIV1 CPUDIV0 PLLDIV2 PLLDIV1 PLLDIV0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7-6 Unimplemented: Read as ‘0’
bit 5 USBDIV: USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1)
1 = USB clock source comes from the 96 MHz PLL divided by 2
0 = USB clock source comes directly from the primary oscillator block with no postscale
bit 4-3 CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits
For XT, HS, EC and ECIO Oscillator modes:
11 = Primary oscillator divided by 4 to derive system clock
10 = Primary oscillator divided by 3 to derive system clock
01 = Primary oscillator divided by 2 to derive system clock
00 = Primary oscillator used directly for system clock (no postscaler)
For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:
11 = 96 MHz PLL divided by 6 to derive system clock
10 = 96 MHz PLL divided by 4 to derive system clock
01 = 96 MHz PLL divided by 3 to derive system clock
00 = 96 MHz PLL divided by 2 to derive system clock
bit 2-0 PLLDIV2:PLLDIV0: PLL Prescaler Selection bits
111 = Divide by 12 (48 MHz oscillator input)
110 = Divide by 10 (40 MHz oscillator input)
101 = Divide by 6 (24 MHz oscillator input)
100 = Divide by 5 (20 MHz oscillator input)
011 = Divide by 4 (16 MHz oscillator input)
010 = Divide by 3 (12 MHz oscillator input)
001 = Divide by 2 (8 MHz oscillator input)
000 = No prescale (4 MHz oscillator input drives PLL directly)
PIC18F2455/2550/4455/4550
DS39632E-page 294 © 2009 Microchip Technology Inc.
REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-0 R/P-1
IESO FCMEN — — FOSC3(1) FOSC2(1) FOSC1(1) FOSC0(1)
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed u = Unchanged from programmed state
bit 7 IESO: Internal/External Oscillator Switchover bit
1 = Oscillator Switchover mode enabled
0 = Oscillator Switchover mode disabled
bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor ena