LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 ... - NXP - Farnell Element 14 - Revenir à l'accueil
Farnell Element 14 :
Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K
Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06 959K
Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06 969K
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Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
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Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
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Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
Farnell-06-6544-8-PD..> 26-Mar-2014 17:56 2.7M
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Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464K1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series. 2. Features and benefits ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. On-chip SRAM includes: 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.4 — 4 April 2014 Product data sheet LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 2 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers. Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces: Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.) USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.) Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support. CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.) SPI controller with synchronous, serial, full duplex communication and programmable data length. Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.) Other peripherals: 70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2) Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. One motor control PWM with support for three-phase motor control. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 3 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. ARM Cortex-M3 system tick timer, including an external clock input option. Repetitive interrupt timer provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution. Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Single 3.3 V power supply (2.4 V to 3.6 V). Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources. Non-maskable Interrupt (NMI) input. Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock. The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI). Brownout detect with separate threshold for interrupt and forced reset. Power-On Reset (POR). Crystal oscillator with an operating range of 1 MHz to 25 MHz. 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. USB PLL for added flexibility. Code Read Protection (CRP) with different security levels. Unique device serial number for identification purposes. Available as LQFP100 (14 mm 14 mm 1.4 mm), TFBGA1001 (9 mm 9 mm 0.7 mm), and WLCSP100 (5.074 5.074 0.6 mm) package. 1. LPC1768/65 only. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 4 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 3. Applications 4. Ordering information 4.1 Ordering options eMetering Alarm systems Lighting White goods Industrial networking Motor control Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1 LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074 5.074 0.6 mm - LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1 LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 Table 2. Ordering options Type number Flash SRAM in kB Ethernet USB CAN I2S DAC Maximum CPU operating frequency CPU AHB SRAM0 AHB SRAM1 Total LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768UK 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 5 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Table 3. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘B’ Third device revision LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 6 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 6. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 32/64 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128 kB DMA CONTROLLER ETHERNET CONTROLLER WITH DMA(1) USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS XTAL1 XTAL2 RESET clocks and controls JTAG interface debug port USB PHY SSP0 UART2/3 I2S(1) I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM QUADRATURE ENCODER SSP1 UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT PWM1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS 32 kHz OSCILLATOR APB slave group 0 APB slave group 1 DAC(1) RTC POWER DOMAIN LPC1769/68/67/ 66/65/64/63 master master master 002aad944 slave slave slave slave slave ROM slave MULTILAYER AHB MATRIX P0 to P4 SDA2 SCL2 SCK0 SSEL0 MISO0 MOSI0 SCK1 SSEL1 MISO1 MOSI1 RXD2/3 TXD2/3 PHA, PHB INDEX EINT[3:0] AOUT MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT 4 × MAT2 2 × MAT3 2 × CAP2 2 × CAP3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1 RTCX2 VBAT PWM1[7:0] 2 × MAT0/1 2 × CAP0/1 RD1/2 TD1/2 SDA0/1 SCL0/1 AD0[7:0] SCK/SSEL MOSI/MISO 8 × UART1 RXD0/TXD0 P0, P2 PCAP1[1:0] RMII pins USB pins CLKOUT MPU = connected to DMA LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 7 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package LPC176xFBD100 50 1 25 75 51 26 76 100 002aad945 002aaf723 LPC1768/65FET100 Transparent top view J G K H F E D C B A 1 2 3 4 5 6 7 8 9 10 ball A1 index area LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 8 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 4. Pin configuration WLCSP100 package Transparent top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 LPC1768UK bump A1 index area aaa-009522 Table 4. Pin allocation table TFBGA100 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 11 - 12 - Row B 1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - Row D 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] 11 - 12 - Row E 1 VSSA 2 VDDA 3 VREFP 4 n.c. 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 7 P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/ RI1/TRACECLK LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 9 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ RXD2 8 P0[16]/RXD1/ SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 10 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Row J 1 P0[28]/SCL0/ USB_SCL 2 P0[27]/SDA0/ USB_SDA 3 P0[29]/USB_D+ 4 P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 5 P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 6 VSS 7 P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 8 P0[1]/TD1/RXD3/SCL1 9 P2[13]/EINT3/ I2STX_SDA 10 P2[10]/EINT0/NMI 11 - 12 - Row K 1 P3[26]/STCLK/ MAT0[1]/PWM1[3] 2 VDD(3V3) 3 VSS 4 P1[20]/MCI0/ PWM1[2]/SCK0 5 P1[23]/MCI1/ PWM1[4]/MISO0 6 P1[26]/MCOB1/ PWM1[6]/CAP0[0] 7 P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 8 P0[0]/RD1/TXD3/SDA1 9 P0[11]/RXD2/ SCL2/MAT3[1] 10 P2[12]/EINT2/ I2STX_WS 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 5. Pin description Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ SDA1 46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ SCL1 47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 11 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). I CAP2[1] — Capture input for Timer 2, channel 1. P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ I2STX_WS/ MISO1/MAT2[2] 77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ SDA2/MAT3[0] 48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 12 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[11]/RXD2/ SCL2/MAT3[1] 49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ SSEL0/SSEL 63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ MISO0/MISO 61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ MOSI0/MOSI 60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ SDA1 59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I/O SDA1 — I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 13 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] 8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ AOUT/RXD3 6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output (LPC1769/68/67/66/65/63 only). I RXD3 — Receiver input for UART3. P0[27]/SDA0/ USB_SDA 25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O USB_SDA — USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28]/SCL0/ USB_SCL 24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). I/O USB_SCL — USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 14 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ ENET_TXD0 95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1]/ ENET_TXD1 94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4]/ ENET_TX_EN 93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8]/ ENET_CRS 92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only). P1[9]/ ENET_RXD0 91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[10]/ ENET_RXD1 90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[14]/ ENET_RX_ER 89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15]/ ENET_REF_CLK 88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16]/ ENET_MDC 87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17]/ ENET_MDIO 86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 15 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0] 32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. (LPC1769/68/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1769/68/66/65 only). I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/MCI0/ PWM1[2]/SCK0 34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/MCABORT/ PWM1[3]/ SSEL0 35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ PWM1[4]/MISO0 37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ PWM1[5]/MOSI0 38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 16 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[25]/MCOA1/ MAT1[1] 39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/MCOB1/ PWM1[6]/CAP0[0] 40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin. O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65 only). I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ PCAP1[1]/ MAT0[1] 45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ TXD1 75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ RXD1 74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 17 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3] 73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2] 70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1] 69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0] 68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ RI1/TRACECLK 67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). O TXD2 — Transmitter output for UART2. P2[9]/ USB_CONNECT/ RXD2 64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 18 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[11]/EINT1/ I2STX_CLK 52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12]/EINT2/ I2STX_WS 51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13]/EINT3/ I2STX_SDA 50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin. I EINT3 — External interrupt 3 input. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25]/MAT0[0]/ PWM1[2] 27 H3 D8 [1] I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/STCLK/ MAT0[1]/PWM1[3] 26 K1 A10 [1] I/O P3[26] — General purpose digital input/output pin. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28]/RX_MCLK/ MAT2[0]/TXD3 82 C7 G1 [1] I/O P4[28] — General purpose digital input/output pin. O RX_MCLK — I2S receive master clock. (LPC1769/68/67/66/65 only). O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/TX_MCLK/ MAT2[1]/RXD3 85 E6 F1 [1] I/O P4[29] — General purpose digital input/output pin. O TX_MCLK — I2S transmit master clock. (LPC1769/68/67/66/65 only). O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 19 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller TDO/SWO 1 A1 A1 [1][7] O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. TDI 2 C3 C4 [1][8] I TDI — Test Data in for JTAG interface. TMS/SWDIO 3 B1 B3 [1][8] I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 4 C2 A2 [1][8] I TRST — Test Reset for JTAG interface. TCK/SWDCLK 5 C1 D4 [1][7] I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RTCK 100 B2 B2 [1][7] O RTCK — JTAG interface control signal. RSTOUT 14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. RESET 17 F3 C6 [9] I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22 H2 D7 [10][11] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23 G3 A9 [10][11] O Output from the oscillator amplifier. RTCX1 16 F2 A7 [10][11] I Input to the RTC oscillator circuit. RTCX2 18 G1 B7 [10] O Output from the RTC oscillator circuit. VSS 31, 41, 55, 72, 83, 97 B3, B7, C9, G7, J6, K3 E5, F5, F6, G5, G6, G7 [10] I ground: 0 V reference. VSSA 11 E1 B5 [10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, 71, 96 K2, H9, C10 , A3 E4, E6, F7, G4 [10] I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(REG)(3V3) 42, 84 H6, A7 F4, F0 [10] I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. VDDA 10 E2 A4 [10] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFP 12 E3 A5 [10] I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 20 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. VREFN 15 F1 A6 I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19 G2 A8 [10][12] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. n.c. 13 D4, E4 B6, D6 - not connected. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 21 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 8.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 8.3 On-chip flash program memory The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 8.4 On-chip SRAM The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 8.5 Memory Protection Unit (MPU) The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 22 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 8.6 Memory map The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 23 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2. Fig 5. LPC17xx memory map 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 C000 0x5020 0000 0x5001 0000 AHB peripherals Ethernet controller(1) USB controller(1) reserved 127- 4 reserved GPDMA controller 0 1 2 3 APB0 peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 WDT 0x4000 0000 timer 0 timer 1 UART0 UART1 reserved reserved SPI RTC + backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM(1) CAN AF registers(1) CAN common(1) CAN1(1) CAN2(1) 22 - 19 reserved I2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 reserved reserved 32 kB local SRAM (LPC1769/8/7/6/5/3) 16 kB local SRAM (LPC1764) reserved reserved private peripheral bus 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x0004 0000 0x0002 0000 0x0008 0000 0x1000 4000 0x1000 0000 0x1000 8000 0x1FFF 0000 0x1FFF 2000 0x2008 0000 0x2007 C000 0x2008 4000 0x2200 0000 0x200A 0000 0x2009 C000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved GPIO reserved reserved reserved reserved APB0 peripherals AHB peripherals APB1 peripherals AHB SRAM bit-band alias addressing peripheral bit-band alias addressing 16 kB AHB SRAM1 (LPC1769/8/7/6/5) 16 kB AHB SRAM0 256 kB on-chip flash (LPC1766/65/63) 128 kB on-chip flash (LPC1764) 512 kB on-chip flash (LPC1769/8/7) PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aad946 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC(1) timer 2 timer 3 UART2 UART3 reserved I2S(1) I2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 reserved repetitive interrupt timer 11 12 reserved motor control PWM 30 - 16 reserved 13 14 15 31 system control QEI LPC1769/68/67/66/65/64/63 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 24 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC17xx, the NVIC supports 33 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • Non-Maskable Interrupt (NMI) • Software interrupt generation 8.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 8.8 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 8.9 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers. Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 25 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 8.10 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 26 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 8.11 Ethernet Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 8.11.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 27 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 8.12 USB interface Remark: The USB controller is available as device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 15.1. 8.12.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. 8.12.1.1 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 28 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 8.12.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification. 8.12.2.1 Features • OHCI compliant. • One downstream port. • Supports port power switching. 8.12.3 USB OTG controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver. 8.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 8.13 CAN controller and acceptance filters Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 29 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 8.14 12-bit ADC The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support. 8.14.1 Features • 12-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range VREFN to VREFP. • 12-bit conversion rate: 200 kHz. • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 8.15 10-bit DAC The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. 8.15.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA support LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 30 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 8.16.1 Features • Maximum UART data bit rate of 6.25 Mbit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • Support for RS-485/9-bit/EIA-485 mode (UART1). • UART3 includes an IrDA mode to support infrared communication. • All UARTs have DMA support. 8.17 SPI serial I/O controller The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 8.17.1 Features • Maximum SPI data bit rate of 12.5 Mbit/s • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 8.18 SSP serial I/O controller The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 31 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.1 Features • Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 8.19 I2C-bus serial I/O controllers The LPC17xx each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 8.19.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 32 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.20 I2S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 8.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 8.21 General purpose 32-bit timers/external event counters The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.21.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 33 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 8.22.1 Features • One PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 34 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 8.23 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 8.24 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 8.24.1 Features • Tracks encoder position. • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 35 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.25.1 Features • 32-bit counter running from PCLK. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.26 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be clocked from the internal AHB clock or from a device pin. 8.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 8.27.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in multiples of Tcy(WDCLK) 4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC) oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 36 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC17xx is powered off. The RTC includes an alarm function that can wake up the LPC17xx from all reduced power modes with a time resolution of 1 s. 8.28.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 8.29 Clocking and power control 8.29.1 Crystal oscillators The LPC17xx include three independent oscillators. These are the main oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 37 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller See Figure 6 for an overview of the LPC17xx clock generation. 8.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.29.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 8.29.2 for additional information. 8.29.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU. Fig 6. LPC17xx clocking generation block diagram MAIN OSCILLATOR INTERNAL RC OSCILLATOR RTC OSCILLATOR MAIN PLL WATCHDOG TIMER REAL-TIME CLOCK CPU CLOCK DIVIDER PERIPHERAL CLOCK GENERATOR USB BLOCK ARM CORTEX-M3 ETHERNET BLOCK DMA GPIO NVIC USB CLOCK DIVIDER system clock select (CLKSRCSEL) USB clock config (USBCLKCFG) CPU clock config (CCLKCFG) pllclk CCLK/8 CCLK/6 CCLK/4 CCLK/2 CCLK pclkWDT rtclk = 1Hz usbclk (48 MHz) cclk USB PLL USB PLL enable main PLL enable 32 kHz APB peripherals LPC17xx 002aad947 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 38 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 8.29.3 USB PLL (PLL1) The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle. 8.29.4 RTC clock output The LPC17xx feature a clock output function intended for synchronizing with external devices and for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results. 8.29.5 Wake-up timer The LPC17xx begin operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 39 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 8.29.6 Power control The LPC17xx support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC17xx also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 8.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 40 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 8.29.6.3 Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 8.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 8.29.6.5 Wake-up interrupt controller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 8.29.7 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 41 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC17xx application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 42 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30 System control 8.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 8.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 7. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aad978 RTCX1 VBAT VDD(REG)(3V3) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VREFN VSSA LPC17xx ULTRA LOW-POWER REGULATOR POWER SELECTOR LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 43 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 8.30.3 Code security (Code Read Protection - CRP) This feature of the LPC17xx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. 8.30.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 44 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 8.30.6 External interrupt inputs The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 8.30.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC17xx is configured for 128 total interrupts. 8.31 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 45 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 8. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 19 for maximum operating voltage. [4] Including voltage on outputs in 3-state mode. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD 2.4 V [2][4] 0.5 +5.5 VI VDD = 0 V 0.5 +3.6 5 V tolerant open-drain pins PIO0_27 and PIO0_28 [2][5] 0.5 +5.5 IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature [6] 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 46 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C) • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal resistance (15 %) Symbol Parameter Conditions Max/Min Unit LQFP100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in 4 in); still air 38.01 C/W Single-layer (4.5 in 3 in); still air 55.09 C/W Rth(j-c) thermal resistance from junction to case 9.065 C/W TFBGA100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in 4 in); still air 55.2 C/W Single-layer (4.5 in 3 in); still air 45.6 C/W Rth(j-c) thermal resistance from junction to case 9.5 C/W Tj = Tamb + PD Rthj – a LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 47 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3][4] 2.5 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled; PCLK = CCLK⁄8 CCLK = 12 MHz; PLL disabled [6][7]- 7 - mA CCLK = 100 MHz; PLL enabled [6][7]- 42 - mA CCLK = 100 MHz; PLL enabled (LPC1769) [6][8]- 50 - mA CCLK = 120 MHz; PLL enabled (LPC1769) [6][8]- 67 - mA sleep mode [6][9]- 2 - mA deep sleep mode [6][10]- 240 - A power-down mode [6][10]- 31 - A deep power-down mode; RTC running [11]- 630 - nA IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present [12]- 530 - nA VDD(REG)(3V3) not present [13] - 1.1 - A IDD(IO) I/O supply current deep sleep mode [14][15]- 40 - nA power-down mode [14][15]- 40 - nA deep power-down mode [14]- 10 - nA LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 48 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller IDD(ADC) ADC supply current active mode; ADC powered [16][17]- 1.95 - mA ADC in Power-down mode [16][18]- <0.2 - A deep sleep mode [16]- 38 - nA power-down mode [16]- 38 - nA deep power-down mode [16]- 24 - nA II(ADC) ADC input current on pin VREFP deep sleep mode [19]- 100 - nA power-down mode [19]- 100 - nA deep power-down mode [19]- 100 - nA Standard port pins, RESET, RTCK IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [20][21] [22] 0 - 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3) 0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(3V3) 0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [23]- - 45 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [23]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A VDD(3V3) < VI < 5 V 0 0 0 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 49 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] VDDA for DAC specs are from 2.7 V to 3.6 V. I2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05 VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA - - 0.4 V ILI input leakage current VI = VDD(3V3) [24]- 2 4 A VI = 5 V - 10 22 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V USB pins (LPC1769/68/66/65/64 only) IOZ OFF-state output current 0 V < VI < 3.3 V [2]- - 10 A VBUS bus supply voltage [2]- - 5.25 V VDI differential input sensitivity voltage (D+) (D) [2] 0.2 - - V VCM differential common mode voltage range includes VDI range [2] 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage [2] 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V [2]- - 0.18 V VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND [2] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [2]- - 20 pF ZDRV driver output impedance for driver which is not high-speed capable with 33 series resistor; steady state drive [2][25] 36 - 44.1 Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 50 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [5] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [6] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. [7] Applies to LPC1768/67/66/65/64/63. [8] Applies to LPC1769 only. [9] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK⁄8. [10] BOD disabled. [11] On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [12] On pin VBAT; IDD(REG)(3V3) = 630 nA; VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [13] On pin VBAT; VBAT = 3.0 V; Tamb = 25 C. [14] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. [15] TCK/SWDCLK pin needs to be externally pulled LOW. [16] On pin VDDA; VDDA = 3.3 V; Tamb = 25 C. The ADC is powered if the PDN bit in the AD0CR register is set to 1 and in Power-down mode of the PDN bit is set to 0. [17] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360_1. [18] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360_1. [19] Vi(VREFP) = 3.3 V; Tamb = 25 C. [20] Including voltage on outputs in 3-state mode. [21] VDD(3V3) supply voltages must be present. [22] 3-state outputs go into 3-state mode in Deep power-down mode. [23] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [24] To VSS. [25] Includes external resistors of 33 1 % on D+ and D. 11.1 Power consumption Conditions: BOD disabled. Fig 8. Deep-sleep mode: typical regulator supply current IDD(Reg)(3V3) versus temperature 002aaf568 temperature (°C) −40 −15 10 35 60 85 250 350 300 400 IDD(Reg)(3V3) (μA) 200 3.6 V 3.3 V 2.4 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 51 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: BOD disabled. Fig 9. Power-down mode: Typical regulator supply current IDD(Reg)(3V3) versus temperature Conditions: VDD(REG)(3V3) floating; RTC running. Fig 10. Deep power-down mode: Typical battery supply current IBAT versus temperature 002aaf569 40 80 120 0 temperature (°C) −40 −15 10 35 60 85 IDD(Reg)(3V3) (μA) 3.6 V 3.3 V 2.4 V 002aag119 1.0 1.4 1.8 0.6 temperature (°C) -40 -15 10 35 60 85 IBAT) (μA) Vi(VBAT) = 3.6 V 3.3 V 3.0 V 2.4 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 52 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running. Fig 11. Deep power-down mode: Typical regulator supply current IDD(REG)(3V3) and battery supply current IBAT versus temperature 002aag120 temperature (°C) -40 -15 10 35 60 85 0.8 1.6 0.4 1.2 2.0 0 IDD(REG)(3V3) IBAT IDD(REG)(3V3)/IBAT (μA) LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 53 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock PCLK = CCLK/4. [1] The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. Table 9. Power consumption for individual analog and digital blocks Peripheral Conditions Typical supply current in mA; CCLK = Notes 12 MHz 48 MHz 100 MHz Timer 0.03 0.11 0.23 Average current per timer UART 0.07 0.26 0.53 Average current per UART PWM 0.05 0.20 0.41 Motor control PWM 0.05 0.21 0.42 I2C 0.02 0.08 0.16 Average current per I2C SPI 0.02 0.06 0.13 SSP1 0.04 0.16 0.32 ADC PCLK = 12 MHz for CCLK = 12 MHz and 48 MHz; PCLK = 12.5 MHz for CCLK = 100 MHz 2.12 2.09 2.07 CAN PCLK = CCLK/6 0.13 0.49 1.00 Average current per CAN CAN0, CAN1, acceptance filter PCLK = CCLK/6 0.22 0.85 1.73 Both CAN blocks and acceptance filter[1] DMA PCLK = CCLK 1.33 5.10 10.36 QEI 0.05 0.20 0.41 GPIO 0.33 1.27 2.58 I2S 0.09 0.34 0.70 USB and PLL1 0.94 1.32 1.94 Ethernet Ethernet block enabled in the PCONP register; Ethernet not connected. 0.49 1.87 3.79 Ethernet connected Ethernet initialized, connected to network, and running web server example. - - 5.19 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 54 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11.3 Electrical pin characteristics Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL IOH (mA) 0 8 16 24 002aaf112 2.8 2.4 3.2 3.6 VOH (V) 2.0 T = 85 °C 25 °C −40 °C VOL (V) 0 0.2 0.4 0.6 002aaf111 5 10 15 IOL (mA) 0 T = 85 °C 25 °C −40 °C LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 55 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 14. Typical pull-up current Ipu versus input voltage VI Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical pull-down current Ipd versus input voltage VI 0 1 2 3 4 5 002aaf108 −30 −50 −10 10 Ipu (μA) −70 T = 85 °C 25 °C −40 °C VI (V) 002aaf109 VI (V) 0 1 2 3 4 5 10 70 50 30 90 Ipd (μA) −10 T = 85 °C 25 °C −40 °C LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 56 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 12.2 External clock [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 10. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 11. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Fig 16. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 57 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 12.4 I/O pins [1] Applies to standard I/O pins. Table 12. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V VDD(REG)(3V3) 3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Conditions: Frequency values are typical values. 4 MHz 1 % accuracy is guaranteed for 2.7 V VDD(REG)(3V3) 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 4 MHz 1 % accuracy specification for voltages below 2.7 V. Fig 17. Internal RC oscillator frequency versus temperature 002aaf107 temperature (°C) -40 -15 10 35 60 85 4.024 4.032 4.020 4.028 4.036 fosc(RC) (MHz) 4.016 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V Table 13. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 58 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see the I2C-bus specification UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Table 14. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [3][4][5][6] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1 Cb 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s tHD;DAT data hold time [3][7][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 59 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.6 I2S-bus interface Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. [1] CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK⁄4; I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. Fig 18. I2C-bus pins clock timing 002aaf425 tf 70 % SDA 30 % tf 70 % 30 % S 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 70 % 30 % 70 % 30 % tVD;DAT tHIGH tLOW tSU;DAT Table 15. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time [1] - - 35 ns tf fall time [1] - - 35 ns tWH pulse width HIGH on pins I2STX_CLK and I2SRX_CLK [1] 0.495 Tcy(clk) - - - tWL pulse width LOW on pins I2STX_CLK and I2SRX_CLK [1] - - 0.505 Tcy(clk) ns output tv(Q) data output valid time on pin I2STX_SDA [1] - - 30 ns on pin I2STX_WS [1] - - 30 ns input tsu(D) data input set-up time on pin I2SRX_SDA [1] 3.5 - - ns th(D) data input hold time on pin I2SRX_SDA [1] 4.0 - - ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 60 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 19. I2S-bus timing (output) Fig 20. I2S-bus timing (input) 002aad992 I2STX_CLK I2STX_SDA I2STX_WS Tcy(clk) tf tr tWH tWL tv(Q) tv(Q) 002aae159 Tcy(clk) tf tr tWH tsu(D) th(D) tsu(D) tsu(D) tWL I2SRX_CLK I2SRX_SDA I2SRX_WS LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 61 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.7 SSP interface [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. Table 16. Dynamic characteristic: SSP interface Tamb = 25C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit SSP interface tsu(SPI_MISO) SPI_MISO set-up time measured in SPI Master mode; see Figure 21 [1] 30 - ns Fig 21. MISO line set-up time in SSP Master mode tsu(SPI_MISO) SCK shifting edges MOSI MISO 002aad326 sampling edges LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 62 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.8 USB interface Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. [1] Characterized but not implemented as production test. Guaranteed by design. Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V VDD(3V3) 3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 22 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 22 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 22 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 22 [1] 82 - - ns Fig 22. Differential data-to-EOP transition skew and EOP width 002aab561 TPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR1, tEOPR2 crossover point extended differential data to SE0/EOP skew n × TPERIOD + tFDEOP LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 63 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.9 SPI [1] TSPICYC = (Tcy(PCLK) n) 0.5 %, n is the SPI clock divider value (n 8); PCLK is derived from the processor clock CCLK. [2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %) edge of the data signal (MOSI or MISO). Table 18. Dynamic characteristics of SPI pins Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit Tcy(PCLK) PCLK cycle time 10 - - ns TSPICYC SPI cycle time [1] 79.6 - - ns tSPICLKH SPICLK HIGH time 0.485 TSPICYC - - ns tSPICLKL SPICLK LOW time - 0.515 TSPICYC ns SPI master tSPIDSU SPI data set-up time [2] 0 - - ns tSPIDH SPI data hold time [2] 2 Tcy(PCLK) 5 - - ns tSPIQV SPI data output valid time [2] 2 Tcy(PCLK) + 30 - - ns tSPIOH SPI output data hold time [2] 2 Tcy(PCLK) + 5 - - ns SPI slave tSPIDSU SPI data set-up time [2] 0 - - ns tSPIDH SPI data hold time [2] 2 Tcy(PCLK) + 5 - - ns tSPIQV SPI data output valid time [2] 2 Tcy(PCLK) + 35 - - ns tSPIOH SPI output data hold time [2] 2 Tcy(PCLK) + 15 - - ns Fig 23. SPI master timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad986 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 64 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 24. SPI master timing (CPHA = 0) Fig 25. SPI slave timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad987 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID tSPIQV SCK (CPOL = 0) MOSI MISO 002aad988 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 65 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 13. ADC electrical characteristics [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 27. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 27. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 27. [6] ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 27. [8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 27. [9] See Figure 28. [10] The conversion frequency corresponds to the number of samples per second. Fig 26. SPI slave timing (CPHA = 0) SCK (CPOL = 0) MOSI MISO 002aad989 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID Table 19. ADC characteristics (full resolution) VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.[1] Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA V Cia analog input capacitance - - 15 pF ED differential linearity error [2][3]- - 1 LSB EL(adj) integral non-linearity [4]- - 3 LSB EO offset error [5][6]- - 2 LSB EG gain error [7]- - 0.5 % ET absolute error [8]- - 4 LSB Rvsi voltage source interface resistance [9]- - 7.5 k fclk(ADC) ADC clock frequency - - 13 MHz fc(ADC) ADC conversion frequency [10]- - 200 kHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 66 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 27. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 27. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 27. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 27. [7] The conversion frequency corresponds to the number of samples per second. Table 20. ADC characteristics (lower resolution) Tamb = 40 C to +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC.[1] Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error [2][3] - 1 - LSB EL(adj) integral non-linearity [4] - 1.5 - LSB EO offset error [5] - 2 - LSB EG gain error [6] - 2 - LSB fclk(ADC) ADC clock frequency 3.0 V VDDA 3.6 V - - 33 MHz 2.7 V VDDA < 3.0 V - - 25 MHz fc(ADC) ADC conversion frequency 3 V VDDA 3.6 V [7]- - 500 kHz 2.7 V VDDA < 3.0 V [7]- - 400 kHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 67 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 27. 12-bit ADC characteristics 002aad948 4095 4094 4093 4092 4091 (2) (1) 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 LSB (ideal) code out VREFP − VREFN 4096 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 68 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 14. DAC electrical characteristics Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent (see Table 21). Parasitic resistance and capacitance from the pad are not included in this figure. Fig 28. ADC interface to pins AD0[n] Table 21. ADC interface components Component Range Description Ri1 2 k to 5.2 k Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. Ri2 100 to 600 Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. C1 750 fF Parasitic capacitance from the ADC block level. C2 65 fF Parasitic capacitance from the ADC block level. C3 2.2 pF Sampling capacitor. LPC17xx AD0[n] 750 fF 65 fF Cia 2.2 pF Rvsi Ri2 100 Ω - 600 Ω Ri1 2 kΩ - 5.2 kΩ VSS VEXT 002aaf197 ADC COMPARATOR BLOCK C1 C3 C2 Table 22. DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.6 - % CL load capacitance - 200 - pF RL load resistance 1 - - k LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 69 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15. Application information 15.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. If the LPC1769/68/67/66/65/64/63 VDD is always greater than 0 V while VBUS = 5 V, the VBUS pin can be connected directly to the VBUS pin on the USB connector. This applies to bus powered devices where the USB cable supplies the system power. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V. The maximum allowable voltage on the VBUS pin is 3.6 V. One method is to use a voltage divider to connect the VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the VBUS pin will be greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. Use the following operating conditions: VBUSmax = 5.25 V VDD = 3.6 V The voltage divider would need to provide a reduction of 3.6 V/5.25 V or ~0.686 V. Fig 29. USB interface on a bus-powered device LPC17xx VDD(3V3) R1 1.5 kΩ R2 USB_UP_LED 002aad940 USB-B connector USB_D+ USB_D− VBUS VSS RS = 33 Ω RS = 33 Ω LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 70 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 30. USB interface on a bus-powered device where VBUS = 5 V, VDD not present LPC17xx VDD R1 1.5 kΩ R2 R3 USB-B connector USB_D+ USB_DUSB_ VBUS VSS RS = 33 Ω RS = 33 Ω aaa-008962 R2 USB_UP_LED Fig 31. USB interface with soft-connect LPC17xx USB-B connector USB_D+ USB_CONNECT SoftConnect switch USB_D− VBUS VSS VDD(3V3) R1 1.5 kΩ RS = 33 Ω 002aad939 RS = 33 Ω USB_UP_LED LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 71 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 32. USB OTG port configuration USB_D+ USB_D− USB_SDA USB_SCL RSTOUT LPC17xx Mini-AB connector 33 Ω 33 Ω VDD VDD 002aad941 EINTn RESET_N ADR/PSW SPEED SUSPEND OE_N/INT_N SCL SDA INT_N VBUS ID DP DM ISP1302 VSS USB_UP_LED VDD Fig 33. USB host port configuration USB_UP_LED USB_D+ USB_D− USB_PWRD LPC17xx 15 kΩ 15 kΩ USB-A connector 33 Ω 33 Ω 002aad942 VDD USB_OVRCR USB_PPWR LM3526-L ENA IN 5 V FLAGA OUTA VDD D+ D− VBUS VSS LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 72 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 35), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 36 and in Table 23 and Table 24. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 36 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. Fig 34. USB device port configuration LPC17xx USB-B connector 33 Ω 33 Ω 002aad943 USB_UP_LED USB_CONNECT VDD VDD D+ D− USB_D+ USB_D− VBUS VBUS VSS Fig 35. Slave mode operation of the on-chip oscillator LPC1xxx XTAL1 Ci 100 pF Cg 002aae835 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 73 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 23. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1/CX2 1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 30 pF < 300 57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF Table 24. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 002aaf424 LPC1xxx XTALIN XTALOUT CX1 CX2 XTAL = CL CP RS L LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 74 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 15.4 Standard I/O pin configuration Figure 37 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver: Open-drain mode enabled/disabled • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. Fig 37. Standard I/O pin configuration with analog input PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aaf272 pin configured as digital output driver pin configured as digital input pin configured as analog input LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 75 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.5 Reset pin configuration Fig 38. Reset pin configuration VSS reset 002aaf274 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 76 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for part LPC1768. [1] IEC levels refer to Appendix D in the IEC61967-2 Specification. Table 25. ElectroMagnetic Compatibility (EMC) for part LPC1768 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = Unit 12 MHz 24 MHz 48 MHz 72 MHz 100 MHz Input clock: IRC (4 MHz) maximum peak level 150 kHz to 30 MHz 7 6 4 7 7 dBV 30 MHz to 150 MHz +1 +5 +11 +16 +9 dBV 150 MHz to 1 GHz 2 +4 +11 +12 +19 dBV IEC level[1] - O O N M L - Input clock: crystal oscillator (12 MHz) maximum peak level 150 kHz to 30 MHz 5 4 4 7 8 dBV 30 MHz to 150 MHz 1 +5 +10 +15 +7 dBV 150 MHz to 1 GHz 1 +6 +11 +10 +16 dBV IEC level[1] - O O N M M - LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 77 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 16. Package outline Fig 39. Package outline SOT407-1 (LQFP100) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o 1 0.2 0.08 0.08 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT407-1 136E20 MS-026 00-02-01 03-02-20 D(1) (1) (1) 14.1 13.9 HD 16.25 15.75 Z E 1.15 0.85 D bp e θ E A1 A Lp detail X L (A 3 ) B 25 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 100 76 75 51 50 26 y pin 1 index w M w M 0 5 10 mm scale LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 78 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 40. Package outline SOT926-1 (TFBGA100) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT926-1 - - - - - - - - - SOT926-1 05-12-09 05-12-22 UNIT A max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 A1 DIMENSIONS (mm are the original dimensions) TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm A2 b D E e2 7.2 e 0.8 e1 7.2 v 0.15 w 0.05 y 0.08 y1 0.1 0 2.5 5 mm scale b e2 e1 e e 1/2 e 1/2 e ∅ v M C A B ∅ w M C ball A1 index area A B C D E F H K G J 1 2 3 4 5 6 7 8 9 10 ball A1 index area B A E D C y1 C y X detail X A A1 A2 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 79 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 41. Package outline LPC1768UK (WLCSP100) Outline References version European projection Issue date IEC JEDEC JEITA wlcsp100_lpc1768uk_po Unit mm max nom min 0.65 0.60 0.55 0.27 0.24 0.21 0.35 0.32 0.29 5.104 5.074 5.044 5.104 5.074 5.044 4.5 4.5 0.15 A Dimensions (mm are the original dimensions) A1 A2 0.385 0.360 0.335 b D E 0.05 e y 0.5 e1 e2 v 0.05 w ball A1 index area X detail X C y A A2 A1 ball A1 index area LPC1768UK 11-10-19 13-11-04 WLCSP100: wafer level chip-scale package; 100 balls; 5.074 x 5.074 x 0.6 mm LPC1768UK 0 scale 3 mm D B E A 1 K J H G F E D C B A 2 3 4 5 6 7 8 9 10 e1 e b Ø v C A B Ø w C 1/2 e e2 e 1/2 e LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 80 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 17. Soldering Fig 42. Reflow soldering for the LQFP100 package SOT407-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP100 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy sot407-1 solder land C Generic footprint pattern Refer to the package outline drawing for actual layout 0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 81 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 43. Reflow soldering of the TFBGA100 package DIMENSIONS in mm P SL SP SR Hx Hy Hx Hy SOT926-1 solder land plus solder paste occupied area Footprint information for reflow soldering of TFBGA100 package solder land solder paste deposit solder resist P P SL SP SR Generic footprint pattern Refer to the package outline drawing for actual layout detail X see detail X sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 82 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 18. Abbreviations Table 26. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DMA Direct Memory Access EOP End Of Packet GPIO General Purpose Input/Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop PWM Pulse Width Modulator RIT Repetitive Interrupt Timer RMII Reduced Media Independent Interface SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCM Tightly Coupled Memory TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 83 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 19. Revision history Table 27. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1769_68_67_66_65_64_63 v.9.4 20140404 Product data sheet - LPC1769_68_67_66_65_64 v.9.3 Modifications: • Added LPC1768UK. • Table 5 “Pin description”: Changed RX_MCLK and TX_MCLK type from INPUT to OUTPUT. LPC1769_68_67_66_65_64_63 v.9.3 20140108 Product data sheet - LPC1769_68_67_66_65_64 v.9.2 Modifications: • Table 7 “Thermal resistance (±15 %)”: – Added TFBGA100. – Added 15 % to table title. LPC1769_68_67_66_65_64_63 v.9.2 20131021 Product data sheet - LPC1769_68_67_66_65_64 v.9.1 Modifications: • Table 8 “Static characteristics”: – Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” – Added Table note 4 “VDDA for DAC specs are from 2.7 V to 3.6 V.” – VDDA/VREFP spec changed from 2.7 V to 2.5 V. • Table 19 “ADC characteristics (full resolution)”: – Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” – VDDA changed from 2.7 V to 2.5 V. • Table 20 “ADC characteristics (lower resolution)”: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” LPC1769_68_67_66_65_64_63 v.9.1 20130916 Product data sheet - LPC1769_68_67_66_65_64 v.9 Modifications: • Added Table 7 “Thermal resistance”. • Table 6 “Limiting values”: – Updated min/max values for VDD(3V3) and VDD(REG)(3V3). – Updated conditions for VI. – Updated table notes. • Table 8 “Static characteristics”: Added Table note 15 “TCK/SWDCLK pin needs to be externally pulled LOW.” • Updated Section 15.1 “Suggested USB interface solutions”. • Added Section 5 “Marking”. • Changed title of Figure 31 from “USB interface on a self-powered device” to “USB interface with soft-connect”. LPC1769_68_67_66_65_64_63 v.9 20120810 Product data sheet - LPC1769_68_67_66_65_64 v.8 Modifications: • Remove table note “The peak current is limited to 25 times the corresponding maximum current.” from Table 5 “Limiting values”. • Change VDD(3V3) to VDD(REG)(3V3) in Section 11.3 “Internal oscillators”. • Glitch filter constant changed to 10 ns in Table note 6 in Table 4. • Description of RESET function updated in Table 4. • Pull-up value added for GPIO pins in Table 4. • Pin configuration diagram for LQFP100 package corrected (Figure 2). LPC1769_68_67_66_65_64_63 v.8 20111114 Product data sheet - LPC1769_68_67_66_65_64 v.7 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 84 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Modifications: • Pin description of USB_UP_LED pin updated in Table 4. • Ri1 and Ri2 labels in Figure 27 updated. • Part LPC1765FET100 added. • Table note 10 updated in Table 4. • Table note 1 updated in Table 12. • Pin description of STCLK pin updated in Table 4. • Electromagnetic compatibility data added in Section 14.6. • Section 16 added. LPC1769_68_67_66_65_64_63 v.7 20110405 Product data sheet - LPC1769_68_67_66_65_64 v.6 Modifications: • Pin description of pins P0[29] and P0[30] updated in Table note 5 of Table 4. Pins are not 5 V tolerant. • Typical value for Parameter Nendu added in Table 9. • Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD(3V3) in Table 7. • Condition 3.0 V VDD(3V3) 3.6 V added in Table 16. • Typical values for parameters IDD(REG)(3V3) and IBAT with condition Deep power-down mode corrected in Table 7 and Table note 9, Table note 10, and Table note 11 updated. • For Deep power-down mode, Figure 9 updated and Figure 10 added. LPC1769_68_67_66_65_64_63 v.6 20100825 Product data sheet - LPC1769_68_67_66_65_64 v.5 Modifications: • Part LPC1768TFBGA added. • Section 7.30.2; BOD level corrected. • Added Section 10.2. LPC1769_68_67_66_65_64_63 v.5 20100716 Product data sheet - LPC1769_68_67_66_65_64 v.4 LPC1769_68_67_66_65_64 v.4 20100201 Product data sheet - LPC1768_67_66_65_64 v.3 LPC1768_67_66_65_64 v.3 20091119 Product data sheet - LPC1768_66_65_64 v.2 LPC1768_66_65_64 v.2 20090211 Objective data sheet - LPC1768_66_65_64 v.1 LPC1768_66_65_64 v.1 20090115 Objective data sheet - - Table 27. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 85 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 86 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 87 of 88 continued >> NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 21 8.1 Architectural overview . . . . . . . . . . . . . . . . . . 21 8.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 21 8.3 On-chip flash program memory . . . . . . . . . . . 21 8.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Memory Protection Unit (MPU). . . . . . . . . . . . 21 8.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24 8.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24 8.9 General purpose DMA controller . . . . . . . . . . 24 8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10 Fast general purpose parallel I/O . . . . . . . . . . 25 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 27 8.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 28 8.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 28 8.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 CAN controller and acceptance filters . . . . . . 28 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 30 8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 30 8.18.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . 31 8.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 32 8.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 33 8.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 34 8.24 Quadrature Encoder Interface (QEI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 35 8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.26 ARM Cortex-M3 system tick timer . . . . . . . . . 35 8.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 35 8.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.28 RTC and backup registers . . . . . . . . . . . . . . . 36 8.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.29 Clocking and power control . . . . . . . . . . . . . . 36 8.29.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36 8.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 37 8.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 38 8.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 38 8.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 40 8.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 40 8.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 40 8.29.7 Peripheral power control . . . . . . . . . . . . . . . . 40 8.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 41 8.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 43 8.30.3 Code security (Code Read Protection - CRP) . . . . . . . . . . . 43 8.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 44 8.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 44 8.30.7 Memory mapping control . . . . . . . . . . . . . . . . 44 8.31 Emulation and debugging . . . . . . . . . . . . . . . 44 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 April 2014 Document identifier: LPC1769_68_67_66_65_64_63 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Thermal characteristics . . . . . . . . . . . . . . . . . 46 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 47 11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 50 11.2 Peripheral power consumption . . . . . . . . . . . . 53 11.3 Electrical pin characteristics . . . . . . . . . . . . . . 54 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 56 12.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 57 12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.6 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 59 12.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 62 12.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 ADC electrical characteristics . . . . . . . . . . . . 65 14 DAC electrical characteristics . . . . . . . . . . . . 68 15 Application information. . . . . . . . . . . . . . . . . . 69 15.1 Suggested USB interface solutions . . . . . . . . 69 15.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 73 15.4 Standard I/O pin configuration . . . . . . . . . . . . 74 15.5 Reset pin configuration. . . . . . . . . . . . . . . . . . 75 15.6 ElectroMagnetic Compatibility (EMC) . . . . . . . 76 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 77 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 82 19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 83 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 85 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 85 20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21 Contact information. . . . . . . . . . . . . . . . . . . . . 86 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1. General description The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I2C-bus (serial clock (SCL), serial data (SDA)). The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three hardware address inputs and interrupt output operating between 2.5 V and 6 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. System master can read from the input port or write to the output port through a single register. The low current consumption of 2.5 A (typical, static) is great for mobile applications and the latched output ports directly drive LEDs. The PCF8574 and PCF8574A are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I2C-bus, so there can be up to 16 of these I/O expanders PCF8574/74A together on the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs). The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic of the microcontroller and is activated when any input state differs from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogated without the microcontroller continuously polling the input register via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source. 2. Features and benefits I2C-bus to parallel port expander 100 kHz I2C-bus interface (Standard-mode I2C-bus) Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD with 100 A current source 8-bit remote I/O pins that default to inputs at power-up Latched outputs directly drive LEDs Total package sink capability of 80 mA Active LOW open-drain interrupt output Eight programmable slave addresses using three address pins Low standby current (2.5 A typical) 40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Rev. 5 — 27 May 2013 Product data sheet PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 2 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA Packages offered: DIP16, SO16, SSOP20 3. Applications LED signs and displays Servers Key pads Industrial control Medical equipment PLC Cellular telephones Mobile devices Gaming machines Instrumentation and test measurement 4. Ordering information 4.1 Ordering options Table 1. Ordering information Type number Topside mark Package Name Description Version PCF8574P PCF8574P DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 PCF8574AP PCF8574AP PCF8574T/3 PCF8574T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 PCF8574AT/3 PCF8574AT PCF8574TS/3 8574TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 PCF8574ATS/3 8574A Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature range PCF8574P PCF8574P,112 DIP16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCF8574AP PCF8574AP,112 DIP16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCF8574T/3 PCF8574T/3,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCF8574T/3,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCF8574AT/3 PCF8574AT/3,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCF8574AT/3,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 3 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 5. Block diagram PCF8574TS/3 PCF8574TS/3,112 SSOP20 Standard marking * IC’s tube - DSC bulk pack 1350 Tamb = 40 C to +85 C PCF8574TS/3,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCF8574ATS/3 PCF8574ATS/3,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C Table 2. Ordering options …continued Type number Orderable part number Package Packing method Minimum order quantity Temperature range Fig 1. Block diagram Fig 2. Simplified schematic diagram of P0 to P7 002aad624 INT I2C-BUS CONTROL LP FILTER PCF8574 PCF8574A INTERRUPT LOGIC A0 A1 A2 INPUT FILTER SHIFT REGISTER SDA SCL 8 bits write pulse read pulse POWER-ON VDD RESET VSS I/O PORT P0 P1 P2 P3 P4 P5 P6 P7 002aac109 write pulse read pulse D CI S FF Q power-on reset data from Shift Register Itrt(pu) 100 μA IOH IOL VDD P0 to P7 VSS D CI S FF Q data to Shift Register to interrupt logic PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 4 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration for DIP16 Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for SSOP20 PCF8574P PCF8574AP A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 002aad625 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 PCF8574T/3 PCF8574AT/3 002aad626 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 PCF8574TS/3 PCF8574ATS/3 P7 SCL P6 n.c. n.c. SDA P5 P4 A0 A1 P3 n.c. n.c. A2 P2 P0 P1 002aad627 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD INT VSS Table 3. Pin description Symbol Pin Description DIP16, SO16 SSOP20 A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 VSS 8 15 supply ground P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line VDD 16 5 supply voltage n.c. - 3, 8, 13, 18 not connected PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 5 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 7. Functional description Refer to Figure 1 “Block diagram”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address format of the PCF8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or LOW to choose one of eight slave addresses. To conserve power, no internal pull-up resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW. The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors. The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation (write operation is shown in Figure 6). 7.1.1 Address maps The PCF8574 and PCF8574A are functionally the same, but have a different fixed portion (A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the PCF8574A to be on the same I2C-bus without address conflict. a. PCF8574 b. PCF8574A Fig 6. PCF8574 and PCF8574A slave addresses R/W 002aad628 0 1 0 0 A2 A1 A0 hardware selectable slave address 0 fixed R/W 002aad629 0 1 1 1 A2 A1 A0 hardware selectable slave address 0 fixed Table 4. PCF8574 address map Pin connectivity Address of PCF8574 Address byte value 7-bit hexadecimal address without R/W A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read VSS VSS VSS 0 1 0 0 0 0 0 - 40h 41h 20h VSS VSS VDD 0 1 0 0 0 0 1 - 42h 43h 21h VSS VDD VSS 0 1 0 0 0 1 0 - 44h 45h 22h VSS VDD VDD 0 1 0 0 0 1 1 - 46h 47h 23h VDD VSS VSS 0 1 0 0 1 0 0 - 48h 49h 24h VDD VSS VDD 0 1 0 0 1 0 1 - 4Ah 4Bh 25h VDD VDD VSS 0 1 0 0 1 1 0 - 4Ch 4Dh 26h VDD VDD VDD 0 1 0 0 1 1 1 - 4Eh 4Fh 27h PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 6 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8. I/O programming 8.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O is an input or output port without using a direction control register. Whenever the master reads the register, the value returned to master depends on the actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte. Advantages of the quasi-bidirectional I/O over totem pole I/O include: • Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O have both n-channel and p-channel transistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels. • Simpler architecture — only a single register and the I/O can be both input and output at the same time. Totem pole I/O have a direction register that specifies the port pin direction and it is always in that configuration unless the direction is explicitly changed. • Does not require a command byte. The simplicity of one register (no need for the pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations. Table 5. PCF8574A address map Pin connectivity Address of PCF8574A Address byte value 7-bit hexadecimal address without R/W A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read VSS VSS VSS 0 1 1 1 0 0 0 - 70h 71h 38h VSS VSS VDD 0 1 1 1 0 0 1 - 72h 73h 39h VSS VDD VSS 0 1 1 1 0 1 0 - 74h 75h 3Ah VSS VDD VDD 0 1 1 1 0 1 1 - 76h 77h 3Bh VDD VSS VSS 0 1 1 1 1 0 0 - 78h 79h 3Ch VDD VSS VDD 0 1 1 1 1 0 1 - 7Ah 7Bh 3Dh VDD VDD VSS 0 1 1 1 1 1 0 - 7Ch 7Dh 3Eh VDD VDD VDD 0 1 1 1 1 1 1 - 7Eh 7Fh 3Fh PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 7 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW. Input HIGH: The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1. Input LOW: The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100 A current source, then the master will read the value of 0. Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH. Output LOW: The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time. Fig 7. Simple quasi-bidirectional I/O 002aah683 VDD weak 100 μA current source (inactive when output LOW) output HIGH VSS output LOW accelerator P port pull-up P7 - P0 pull-down with resistor to VSS or external drive LOW input LOW pull-up with resistor to VDD or external drive HIGH input HIGH PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 8 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8.2 Writing to the port (Output mode) The master (microcontroller) sends the START condition and slave address setting the last bit of the address byte to logic 0 for the write mode. The PCF8574/74A acknowledges and the master then sends the data byte for P7 to P0 to the port register. As the clock line goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by the PCF8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is written, the strong pull-up turns on for 1⁄2 of the clock cycle, then the line is held HIGH by the weak current source. The master can then send a STOP or ReSTART condition or continue sending data. The number of data bytes that can be sent successively is not limited and the previous data is overwritten every time a data byte has been sent and acknowledged. Ensure a logic 1 is written for any port that is being used as an input to ensure the strong external pull-down is turned off. Simple code WRITE mode:
Remark: Bold type = generated by slave device.
Fig 8. Write mode (output)
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
START condition R/W
acknowledge
from slave
002aah349
P7 P6 1
data 1
A
acknowledge
from slave
SCL 1 2 3 4 5 6 7 8 9
SDA A
acknowledge
from slave
write to port
data output from port
tv(Q)
P5
data 2
DATA 2 VALID
P4 P3 P2 P1 P0 P7 P6 P4 P3 P2 P1 P0
P5
0
tv(Q)
DATA 1 VALID
P5 output voltage
Itrt(pu)
IOH
P5 pull-up output current
td(rst)
INT
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 9 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after
power-on reset. To enter the Read mode the master (microcontroller) addresses the slave
device and sets the last bit of the address byte to logic 1 (address byte read). The slave
will acknowledge and then send the data byte to the master. The master will NACK and
then send the STOP condition or ACK and read the input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the
actual state of the pin.
If the data on the input port changes faster than the master can read, this data may be
lost. The DATA 2 and DATA3 are lost because these data did not meet the setup time and
hold time (see Figure 9).
Simple code for Read mode:
Remark: Bold type = generated by slave device.
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCF8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset
condition is released and the PCF8574/74A registers and I2C-bus/SMBus state machine
will initialize to their default states of all I/Os to inputs with weak current source to VDD.
Thereafter VDD must be lowered below VPOR and back up to the operation voltage for
power-on reset cycle.
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at
any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input
data is lost.
Fig 9. Read mode (input)
S A6 A5 A4 A3 A2 A1 A0 1 A
slave address
START condition R/W acknowledge
from slave
002aah383
data from port
A
acknowledge
from master
SDA 1
no acknowledge
from master
read from
port
data at
port
data from port
DATA 1
DATA 4
INT
DATA 4
DATA 2
DATA 3
P
STOP
condition
tv(INT) trst(INT)
th(D) tsu(D)
trst(INT)
DATA 1
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 10 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
8.5 Interrupt output (INT)
The PCF8574/74A provides an open-drain output (INT) which can be fed to a
corresponding input of the microcontroller (see Figure 10). As soon as a port input is
changed, the INT will be active (LOW) and notify the microcontroller.
An interrupt is generated at any rising or falling edge of the port inputs. After time tv(Q), the
signal INT is valid.
The interrupt will reset to HIGH when data on the port is changed to the original setting or
data is read or written by the master.
In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the
acknowledge bit of the address byte and also on the rising edge of the write to port pulse.
The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see
Figure 8).
The interrupt is reset (HIGH) in the Read mode on the rising edge of the read from port
pulse (see Figure 9).
During the interrupt reset, any I/O change close to the read or write pulse may not
generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is
reset, any change in I/Os will be detected and transmitted as an INT.
At power-on reset all ports are in Input mode and the initial state of the ports is HIGH,
therefore, for any port pin that is pulled LOW or driven LOW by external source, the
interrupt output will be active (output LOW).
Fig 10. Application of multiple PCF8574/74As with interrupt
002aad634
VDD
MICROCONTROLLER
INT
PCF8574
INT
PCF8574
INT
device 1 device 2
PCF8574A
INT
device 16
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 11 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
9. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-wire communication between different ICs or modules. The
two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12).
9.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).
Fig 11. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 12. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 12 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
9.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated
by the receiving device) that indicates to the transmitter that the data transfer was
successful.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that wants to issue an
acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of the acknowledge bit related
clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 13. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 14. Acknowledgement on the I2C-bus
002aaa987
S
START
condition
1 2 8 9
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 13 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and
P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and
P1) must be written as HIGH so the external devices fully control the input ports.
The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to
P7). If 10 A internal output HIGH is not enough current source, the port needs external
pull-up resistor. During a read, the logic levels of the external devices driving the input
ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be
read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the
microprocessor that there has been a change of data on its ports without having to
communicate via the I2C-bus.
10.2 How to read and write to I/O expander (example)
In the application example of PCF8574 shown in Figure 15, the microcontroller wants to
control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes.
1. When the system power on:
Core Processor needs to issue an initial command to set P0 and P1 as inputs and
P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off,
switch off and latch off).
2. Operation:
When the temperature changes above the threshold, the temperature sensor signal
will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core
processor’ that there have been changes on the input pins. Read the input register.
If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch.
3. Software code:
//System Power on
// write to PCF8574 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs
//Initial setting for PCF9574
Fig 15. Bidirectional I/O expander application
002aah384
VDD
temperature sensor
battery status
control for latch
control for switch
control for audio
control for camera
control for MP3
P0
P1
P2
P3
P4
P5
P6
P7
VDD
SDA
SCL
INT
A0
A1
A2
CORE
PROCESSOR
VDD
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 14 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
while (INT == 1); //Monitor the interrupt pin. If INT = 1 do nothing
//When INT = 0 then read input ports
//Read PCF8574 data
If (P0 == 0) //Temperature sensor activated
{
// write to PCF8574 with data 0010 1011b to turn on LED (P7), on Switch (P3)
and keep P[1:0] as input ports.
// Write to PCF8574
}
10.3 High current-drive load applications
The GPIO has a minimum guaranteed sinking current of 10 mA per bit at 5 V. In
applications requiring additional drive, two port pins may be connected together to sink up
to 20 mA current. Both bits must then always be turned on or off together. Up to five pins
can be connected together to drive 80 mA, which is the device recommended total limit.
Each pin needs its own limiting resistor as shown in Figure 16 to prevent damage to the
device should all ports not be turned on at the same time.
10.4 Migration path
NXP offers newer, more capable drop-in replacements for the PCF8574/74A in newer
space-saving packages.
PCA9670 replaces the interrupt output of the PCA9674 with hardware reset input to retain
the maximum number of addresses and the PCA9672 replaces address A2 of the
PCA9674 with hardware reset input to retain the interrupt but limit the number of
addresses.
Fig 16. High current-drive load application
002aah385
VDD
P0
P1
P2
P3
P4
P5
P6
P7
VDD
SDA
SCL
INT
A0
A1
A2
CORE
PROCESSOR
VDD
LOAD
Table 6. Migration path
Type number I2C-bus
frequency
Voltage range Number of
addresses
per device
Interrupt Reset Total package
sink current
PCF8574/74A 100 kHz 2.5 V to 6 V 8 yes no 80 mA
PCA8574/74A 400 kHz 2.3 V to 5.5 V 8 yes no 200 mA
PCA9674/74A 1 MHz Fm+ 2.3 V to 5.5 V 64 yes no 200 mA
PCA9670 1 MHz Fm+ 2.3 V to 5.5 V 64 no yes 200 mA
PCA9672 1 MHz Fm+ 2.3 V to 5.5 V 16 yes yes 200 mA
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 15 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
11. Limiting values
12. Thermal characteristics
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +7 V
IDD supply current - 100 mA
ISS ground supply current - 100 mA
VI input voltage VSS 0.5 VDD + 0.5 V
II input current - 20 mA
IO output current - 25 mA
Ptot total power dissipation - 400 mW
P/out power dissipation per output - 100 mW
Tj(max) maximum junction temperature - 125 C
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating 40 +85 C
Table 8. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction
to ambient
SO16 package 115 C/W
SSOP20 package 136 C/W
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 16 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
13. Static characteristics
[1] The power-on reset circuit resets the I2C-bus logic at VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD).
Table 9. Static characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 2.5 - 6.0 V
IDD supply current operating mode; VDD = 6 V; no load;
VI = VDD or VSS; fSCL = 100 kHz
- 40 100 A
Istb standby current standby mode; VDD = 6 V; no load;
VI = VDD or VSS
- 2.5 10 A
VPOR power-on reset voltage VDD = 6 V; no load; VI = VDD or VSS [1]- 1.3 2.4 V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V
IOL LOW-level output current VOL = 0.4 V 3 - - mA
IL leakage current VI = VDD or VSS 1 - +1 A
Ci input capacitance VI = VSS - - 7 pF
I/Os; P0 to P7
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V
IIHL(max) maximum allowed input current
through protection diode
VI VDD or VI VSS - - 400 A
IOL LOW-level output current VOL = 1 V; VDD = 5 V 10 25 - mA
IOH HIGH-level output current VOH = VSS 30 - 300 A
Itrt(pu) transient boosted pull-up current HIGH during acknowledge (see
Figure 8); VOH = VSS; VDD = 2.5 V
- 1 - mA
Ci input capacitance - - 10 pF
Co output capacitance - - 10 pF
Interrupt INT (see Figure 8)
IOL LOW-level output current VOL = 0.4 V 1.6 - - mA
IL leakage current VI = VDD or VSS 1 - +1 A
Select inputs A0, A1, A2
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V
ILI input leakage current pin at VDD or VSS 250 - +250 nA
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 17 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
14. Dynamic characteristics
[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
Table 10. Dynamic characteristics
VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
I2C-bus timing[1] (see Figure 17)
fSCL SCL clock frequency - - 100 kHz
tBUF bus free time between a STOP and
START condition
4.7 - - s
tHD;STA hold time (repeated) START condition 4 - - s
tSU;STA set-up time for a repeated START condition 4.7 - - s
tSU;STO set-up time for STOP condition 4 - - s
tHD;DAT data hold time 0 - - ns
tVD;DAT data valid time - - 3.4 s
tSU;DAT data set-up time 250 - - ns
tLOW LOW period of the SCL clock 4.7 - - s
tHIGH HIGH period of the SCL clock 4 - - s
tr rise time of both SDA and SCL signals - - 1 s
tf fall time of both SDA and SCL signals - - 0.3 s
Port timing (see Figure 8 and Figure 9)
tv(Q) data output valid time CL 100 pF - - 4 s
tsu(D) data input set-up time CL 100 pF 0 - - s
th(D) data input hold time CL 100 pF 4 - - s
Interrupt INT timing (see Figure 9)
tv(INT) valid time on pin INT from port to INT;
CL 100 pF
- - 4 s
trst(INT) reset time on pin INT from SCL to INT;
CL 100 pF
- - 4 s
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 18 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Rise and fall times refer to VIL and VIH.
Fig 17. I2C-bus timing diagram
002aab175
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
tHD;STA tSU;DAT tHD;DAT
tBUF tf
tSU;STA tLOW tHIGH
tVD;ACK tSU;STO
1 / fSCL
tr
tVD;DAT
0.3 × VDD
0.7 × VDD
0.3 × VDD
0.7 × VDD
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 19 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
15. Package outline
Fig 18. Package outline SOT38-4 (DIP16)
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4
95-01-14
03-02-13
MH
c
(e 1 )
ME
A
L
seating plane
A1
w M
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max.
1 2 b1
(1) (1) (1)
b2 c D E e M Z
L H
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min.
A
max. b
max.
e1 ME w
1.73
1.30
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
2.54 7.62 0.254
8.25
7.80
10.0
8.3
4.2 0.51 3.2 0.76
inches 0.068
0.051
0.021
0.015
0.014
0.009
1.25
0.85
0.049
0.033
0.77
0.73
0.26
0.24
0.14
0.12
0.1 0.3 0.01
0.32
0.31
0.39
0.33
0.17 0.02 0.13 0.03
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 20 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Fig 19. Package outline SOT162-1 (SO16)
UNIT
A
max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT162-1
8
16
w M
bp
D
detail X
Z
e
9
1
y
0.25
075E03 MS-013
pin 1 index
0.1 0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.41
0.40
0.30
0.29
0.05
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
v M A
(A 3 )
A
0 5 10 mm
scale
SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1
99-12-27
03-02-19
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 21 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Fig 20. Package outline SOT266-1 (SSOP20)
UNIT A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0
1.4
1.2
0.32
0.20
0.20
0.13
6.6
6.4
4.5
4.3
0.65 1 0.2
6.6
6.2
0.65
0.45
0.48
0.18
10
0
o
0.13 0.1 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
0.75
0.45
SOT266-1 MO-152
99-12-27
03-02-19
w M
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
v M A
X
(A 3 )
A
y
0.25
1 10
20 11
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1
A
max.
1.5
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 22 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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Product data sheet Rev. 5 — 27 May 2013 23 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 21) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and 12
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 21.
Table 11. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 12. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 24 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Soldering of through-hole mount packages
18.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages
on a printed-circuit board.
18.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder
pastes is increasing. Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb
or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic
body must not exceed the specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling may be necessary immediately
after soldering to keep the temperature within the permissible limit.
18.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is
less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is
between 300 C and 400 C, contact may be up to 5 seconds.
MSL: Moisture Sensitivity Level
Fig 21. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 25 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
18.4 Package related soldering information
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
[2] For PMFP packages hot bar soldering or manual soldering is suitable.
Table 13. Suitability of through-hole mount IC packages for dipping and wave soldering
Package Soldering method
Dipping Wave
CPGA, HCPGA - suitable
DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]
PMFP[2] - not suitable
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 26 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
19. Soldering: PCB footprints
Fig 22. PCB footprint for SOT162-1 (SO16); reflow soldering
DIMENSIONS in mm
P1 Ay By D1 D2 Gy Hy
11.200 6.400 2.400 0.700
C
0.800 10.040 8.600
Gx
11.450 sot162-1_fr
Hx
1.270 11.900
SOT162-1
solder land
occupied area
Footprint information for reflow soldering of SO16 package
Gy By Ay
C
Hy
Hx
Gx
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
P2
(0.125) (0.125)
D2 (4x) D1
P2
1.320
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 27 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Fig 23. PCB footprint for SOT266-1 (SSOP20); reflow soldering
DIMENSIONS in mm
P1 Ay By D1 D2 Gy Hy
7.200 4.500 1.350 0.400
C
0.600 6.900 5.300
Gx
7.450 sot266-1_fr
Hx
0.650 7.300
SOT266-1
solder land
occupied area
Footprint information for reflow soldering of SSOP20 package
P2
0.750
P2
Gy
C
Hy
(0.125)
By Ay
(0.125)
Hx
Gx
D2 (4x) P1 D1
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 28 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
20. Abbreviations
Table 14. Abbreviations
Acronym Description
CDM Charged-Device Model
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
I2C-bus Inter IC bus
ESD ElectroStatic Discharge
FF Flip-Flop
GPIO General Purpose Input/Output
HBM Human Body Model
IC Integrated Circuit
LED Light Emitting Diode
LP Low-Pass
PLC Programmable Logic Controller
POR Power-On Reset
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 29 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
21. Revision history
Table 15. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCF8574_PCF8574A v.5 20130527 Product data sheet - PCF8574 v.4
Modifications: • The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Electrical parameter letter-symbols and their definitions are updated to conform to NXP
presentation standards.
• Section 1 “General description”: updated
• Section 2 “Features and benefits”:
– third bullet item: appended “with non-overvoltage tolerant I/O held to VDD with 100 A
current source”
– added (new) fourth and seventh bullet items
– added sixth bullet item: “Total package sink capability of 80 mA”
– ninth bullet changed from “(10 A maximum)” to “(2.5 A typical)”
– deleted (old) 11th, 12th and 13th bullet items
• Added (new) eighth bullet item “Mobile devices”
• Table 1 “Ordering information”:
– Type number corrected from “PCF8574T” to “PCF8574/3”
– Type number corrected from “PCF8574AT” to “PCF8574AT/3”
– Type number corrected from “PCF8574TS” to “PCF8574TS/3”
– Type number corrected from “PCF8574ATS” to “PCF8574ATS/3”
• Added Section 4.1 “Ordering options”
• Figure 4 “Pin configuration for SO16”: updated type numbers (appended “/3”)
• Figure 5 “Pin configuration for SSOP20”: updated type numbers (appended “/3”)
• Section 6.2 “Pin description”: combined DIP16, SO16 and SSOP20 pin descriptions into
one table (Table 3)
• Section 7 “Functional description” reorganized
• Section 7.1 “Device address”, first paragraph, fourth sentence: appended “so they must be
externally held HIGH or LOW”
• Table 4 “PCF8574 address map” updated: added column for 7-bit hexadecimal address
without R/W
• Table 5 “PCF8574A address map” updated: added column for 7-bit hexadecimal address
without R/W
• Section 8.1 “Quasi-bidirectional I/Os”: re-written and placed before Section 8.4 “Power-on
reset”
• added Section 8.2 “Writing to the port (Output mode)”
• added Section 8.3 “Reading from a port (Input mode)”
• Figure 9 “Read mode (input)”: changed symbol “tps” to “tsu”
• Section 8.4 “Power-on reset” re-written
• Section 8.5 “Interrupt output (INT)” re-written
• Figure 10 “Application of multiple PCF8574/74As with interrupt” updated: changed
device 16 from “PCF8574” to “PCF8574A”
• Section 9.3 “Acknowledge”, first paragraph, third sentence re-written.
• Added Section 10 “Application design-in information”
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 30 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Modifications: (continued) • Table 7 “Limiting values”:
– changed parameter description for symbol II from “DC input current” to “input current”
– changed parameter description for symbol IO from “DC output current” to “output
current”
– changed parameter description for symbol ISS from “supply current” to “ground supply
current”
– changed symbol “PO” to “P/out”
– added Tj(max) limits
• Added Section 12 “Thermal characteristics”
• Table 9 “Static characteristics”:
– table title changed from “DC characteristics” to “Static characteristics”
– sub-section “I/Os; P0 to P7”: changed parameter description for symbol Itrt(pu)
from “transient pull-up current” to “transient boosted pull-up current”
– moved sub-section “Port timing” to Table 10 “Dynamic characteristics”
– sub-section “Interrupt INT”: moved sub-sub-section “Timing” to Table 10 “Dynamic
characteristics”
• Table 10 “Dynamic characteristics”:
– sub-section “I2C-bus timing”: deleted symbol/parameter “tSW, tolerable spike width on
bus”
– sub-section “Port timing”: changed symbol/parameter from “tpv, output data valid time”
to “tv(Q), data output valid time”
– sub-section “Port timing”: changed symbol/parameter from “tsu, input data set-up time”
to “tsu(D), data input set-up time”
– sub-section “Port timing”: changed symbol/parameter from “th, input data hold time”
to “th(D), data input hold time”
– sub-section “Interrupt INT”: changed parameter description for symbol tv(INT)
from “INT output valid time” to “valid time on pin INT”
– sub-section “Interrupt INT”: changed parameter description for symbol trst(INT)
from “INT reset delay time” to “reset time on pin INT”
• Added Section 19 “Soldering: PCB footprints”
PCF8574 v.4
(9397 750 10462)
20021122 Product specification - PCF8574 v.3
PCF8574 v.3
(9397 750 09911)
20020729 Product specification - PCF8574 v.2
PCF8574 v.2
(9397 750 01758)
19970402 Product specification - PCF8574_PCF8574A v.1
PCF8574_PCF8574A v.1
(9397 750 70011)
199409 Product specification - -
Table 15. Revision history …continued
Document ID Release date Data sheet status Change notice Supersedes
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 31 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
22. Legal information
22.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 32 of 33
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCF8574; PCF8574A
Remote 8-bit I/O expander for I2C-bus with interrupt
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 May 2013
Document identifier: PCF8574_PCF8574A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
24. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
7.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5
7.1.1 Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 6
8.1 Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 6
8.2 Writing to the port (Output mode) . . . . . . . . . . . 8
8.3 Reading from a port (Input mode) . . . . . . . . . . 9
8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
8.5 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 10
9 Characteristics of the I2C-bus . . . . . . . . . . . . 11
9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.1.1 START and STOP conditions . . . . . . . . . . . . . 11
9.2 System configuration . . . . . . . . . . . . . . . . . . . 11
9.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 12
10 Application design-in information . . . . . . . . . 13
10.1 Bidirectional I/O expander applications . . . . . 13
10.2 How to read and write to I/O expander
(example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.3 High current-drive load applications . . . . . . . . 14
10.4 Migration path . . . . . . . . . . . . . . . . . . . . . . . . . 14
11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15
12 Thermal characteristics . . . . . . . . . . . . . . . . . 15
13 Static characteristics. . . . . . . . . . . . . . . . . . . . 16
14 Dynamic characteristics . . . . . . . . . . . . . . . . . 17
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Handling information. . . . . . . . . . . . . . . . . . . . 22
17 Soldering of SMD packages . . . . . . . . . . . . . . 22
17.1 Introduction to soldering . . . . . . . . . . . . . . . . . 22
17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 22
17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22
17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23
18 Soldering of through-hole mount packages . 24
18.1 Introduction to soldering through-hole mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
18.2 Soldering by dipping or by solder wave . . . . . 24
18.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 24
18.4 Package related soldering information. . . . . . 25
19 Soldering: PCB footprints . . . . . . . . . . . . . . . 26
20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28
21 Revision history . . . . . . . . . . . . . . . . . . . . . . . 29
22 Legal information . . . . . . . . . . . . . . . . . . . . . . 31
22.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31
22.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
22.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 31
22.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32
23 Contact information . . . . . . . . . . . . . . . . . . . . 32
24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1. General description
The LPC408x/7x is an ARM Cortex-M4 based digital signal controller for embedded
applications requiring a high level of integration and low power dissipation.
The ARM Cortex-M4 is a next generation core that offers system enhancements such as
low power consumption, enhanced debug features, and a high level of support block
integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard
architecture with separate local instruction and data buses as well as a third bus for
peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core for several
versions of the part.
The LPC408x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC408x/7x is targeted to operate at
up to 120 MHz CPU frequency.
The peripheral complement of the LPC408x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,
External Memory controller (EMC), LCD, Ethernet, USB Device/Host/OTG, an SPI Flash
Interface (SPIFI), a General Purpose DMA controller, five UARTs, three SSP controllers,
three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers,
two general purpose PWMs with six outputs each and one motor control PWM, an
ultra-low power RTC with separate battery supply and event recorder, a windowed
watchdog timer, a CRC calculation engine and up to 165 general purpose I/O pins.
The analog peripherals include one eight-channel 12-bit ADC, two analog comparators,
and a DAC.
The pinout of LPC408x/7x is intended to allow pin function compatibility with the
LPC24xx/23xx as well as the LPC178x/7x families.
2. Features and benefits
Functional replacement for LPC23xx/24xx and LPC178x/7x family devices.
ARM Cortex-M4 core:
ARM Cortex-M4 processor, running at frequencies of up to 120 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit (not all versions).
Non-maskable Interrupt (NMI) input.
LPC408x/7x
32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM;
USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI
Rev. 3 — 1 May 2014 Product data sheet
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 2 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
points.
System tick timer.
System:
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, and General Purpose DMA controller. This
interconnect provides communication with no arbitration delays unless two masters
attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
Embedded Trace Macrocell (ETM) module supports real-time trace.
Boundary scan for simplified board testing.
Memory:
512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced
flash memory accelerator and location of the flash memory on the CPU local
code/data bus provides high code performance from flash.
Up to 96 kB on-chip SRAM includes:
64 kB of main SRAM on the CPU with local code/data bus for high-performance
CPU access.
Two 16 kB peripheral SRAM blocks with separate access paths for higher
throughput. These SRAM blocks may be used for DMA memory as well as for
general purpose instruction and data storage.
Up to 4032 byte on-chip EEPROM.
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistors (TFT) displays.
Dedicated DMA controller.
Selectable display resolution (up to 1024 768 pixels).
Supports up to 24-bit true-color mode.
External Memory Controller (EMC) provides support for asynchronous static memory
devices such as RAM, ROM and flash, as well as dynamic memories such as single
data rate SDRAM.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
Serial interfaces:
Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and
RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one
UART (USART4) supports IrDA, synchronous mode, and a smart card mode
conforming to ISO7816-3.
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 3 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
Three enhanced I2C-bus interfaces, one with a true open-drain output supporting
the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two
with standard port pins. Enhancements include multiple address recognition and
monitor mode.
I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with
the GPDMA.
CAN controller with two channels.
Digital peripherals:
SD/MMC memory card interface.
Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, with
configurable pull-up/down resistors, open-drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access and support Cortex-M4
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
Quadrature encoder interface that can monitor one external quadrature encoder.
Two standard PWM/timer blocks with external count input option.
One motor control PWM with support for three-phase motor control.
Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V lithium button cell.
The RTC will continue working when the battery voltage drops to as low as 2.1 V.
An RTC interrupt can wake up the CPU from any reduced power mode.
Event Recorder that can capture the clock value when an event occurs on any of
three inputs. The event identification and the time it occurred are stored in
registers. The Event Recorder is located in the RTC power domain and can
therefore operate as long as there is RTC power.
Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal
oscillator, watchdog warning interrupt, and safety features.
CRC Engine block can calculate a CRC on supplied data using one of three
standard polynomials. The CRC engine can be used in conjunction with the DMA
controller to generate a CRC without CPU involvement in the data transfer.
Analog peripherals:
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support.
Two analog comparators.
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 4 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Power control:
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up
from any priority interrupt that can occur while the clocks are stopped in
Deep-sleep, Power-down, and Deep power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate
during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2
pin interrupt, and NMI).
Brownout detect with separate threshold for interrupt and forced reset.
On-chip Power-On Reset (POR).
Clock generation:
Clock output function that can reflect the main oscillator clock, IRC clock, RTC
clock, CPU clock, USB clock, or the watchdog timer clock.
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz Internal RC oscillator (IRC) trimmed to 1 % accuracy that can optionally be
used as a system clock.
An on-chip PLL allows CPU operation up to the maximum CPU rate without the
need for a high-frequency crystal. May be run from the main oscillator or the
internal RC oscillator.
A second, dedicated PLL may be used for USB interface in order to allow added
flexibility for the Main PLL settings.
Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
Unique device serial number for identification purposes.
Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C.
Available as LQFP208, TFBGA208, TFBGA180, LQFP144, TFBGA80, and LQFP80
package.
3. Applications
Communications:
Point-of-sale terminals, web servers, multi-protocol bridges
Industrial/Medical:
Automation controllers, application control, robotics control, HVAC, PLC, inverters,
circuit breakers, medical scanning, security monitoring, motor drive, video intercom
Consumer/Appliance:
Audio, MP3 decoders, alarm systems, displays, printers, scanners, small
appliances, fitness equipment
Automotive:
After-market, car alarms, GPS/fleet monitors
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 5 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC4088
LPC4088FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
SOT950-1
LPC4088FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4088FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4078
LPC4078FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC4078FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 15 0.7 mm
SOT950-1
LPC4078FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4078FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4078FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1
LPC4078FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC4076
LPC4076FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4076FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4074
LPC4074FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4074FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1
LPC4072
LPC4072FET80 TFBGA80 plastic thin fine-pitch ball grid array package; 80 balls SOT1328-1
LPC4072FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12 12 1.4 mm SOT315-1
Table 2. Ordering options
Type number
Flash (kB)
SRAM (kB)
EEPROM (B)
EMC bus
width (bit)
LCD
Ethernet
USB
UART
QEI
SD/MMC
Comparator
FPU
Package
LPC4088
LPC4088FBD208 512 96 4032 32 yes yes H/O/D 5 yes yes yes yes LQFP208
LPC4088FET208 512 96 4032 32 yes yes H/O/D 5 yes yes yes yes TFBGA208
LPC4088FET180 512 96 4032 16 yes yes H/O/D 5 yes yes yes yes TFBGA180
LPC4088FBD144 512 96 4032 8 yes yes H/O/D 5 yes yes yes yes LQFP144
LPC4078
LPC4078FBD208 512 96 4032 32 no yes H/O/D 5 yes yes yes yes LQFP208
LPC4078FET208 512 96 4032 32 no yes H/O/D 5 yes yes yes yes TFBGA208
LPC4078FET180 512 96 4032 16 no yes H/O/D 5 yes yes yes yes TFBGA180
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 6 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
LPC4078FBD144 512 96 4032 8 no yes H/O/D 5 yes yes yes yes LQFP144
LPC4078FBD100 512 96 4032 - no yes H/O/D 5 yes yes yes yes LQFP100
LPC4078FBD80 512 96 4032 - no yes H/O/D 5 yes yes yes yes LQFP80
LPC4076
LPC4076FET180 256 80 2048 16 no yes H/O/D 5 yes yes yes yes TFBGA180
LPC4076FBD144 256 80 2048 8 no yes H/O/D 5 yes yes yes yes LQFP144
LPC4074
LPC4074FBD144 128 40 2048 - no no D 4 no no no no LQFP144
LPC4074FBD80 128 40 2048 - no no D 4 no no no no LQFP80
LPC4072
LPC4072FET80 64 24 2048 - no no D 4 no no no no TFBGA80
LPC4072FBD80 64 24 2048 - no no D 4 no no no no LQFP80
Table 2. Ordering options …continued
Type number
Flash (kB)
SRAM (kB)
EEPROM (B)
EMC bus
width (bit)
LCD
Ethernet
USB
UART
QEI
SD/MMC
Comparator
FPU
Package
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 7 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
5. Block diagram
(1) Not available on all parts.
Fig 1. Block diagram
SRAM
96/80/
40/24 kB
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
FLASH
ACCELERATOR
FLASH
512/256/128/64 kB
GPDMA
CONTROLLER
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE 0
HIGH-SPEED
GPIO AHB TO
APB
BRIDGE 1
4032 B/
2048 B
EEPROM
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
JTAG
interface
debug
port
SSP0/2
USART4(1)
UART2/3
SYSTEM CONTROL
2 x ANALOG COMPARATOR(1)
SSP1
UART0/1
I2C0/1
CAN 0/1
TIMER 0/1
WINDOWED WDT
12-bit ADC
PWM0/1
PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS
EVENT RECORDER
32 kHz
OSCILLATOR
APB slave group 1
APB slave group 0
RTC POWER DOMAIN
LPC408x/7x
master
ETHERNET(1)
master
USB
DEVICE/
HOST(1)/OTG(1)
master
002aag491
slave slave
CRC
slave
SPIFI
slave slave slave
slave
EMC(1) ROM
slave slave
LCD(1)
slave
MULTILAYER AHB MATRIX
I2C2
TIMER2/3
DAC
I2S
QUADRATURE ENCODER(1)
MOTOR CONTROL PWM
MPU FPU(1)
SD/MMC(1)
= connected to GPDMA
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 8 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
6. Pinning information
6.1 Pinning
Fig 2. Pin configuration (LQFP208)
Fig 3. Pin configuration (LQFP144)
Fig 4. Pin configuration (LQFP100)
LPC408x/7x
156
53
104
208
157
105
1
52
002aag732
LPC408x/7x
108
37
72
144
109
73
1
36
002aag735
LPC407x
50
1
25
75
51
26
76
100
002aah638
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 9 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 5. Pin configuration (LQFP80)
Fig 6. Pin configuration (TFBGA208)
40
1
20
60
41
21
61
80
002aag865
LPC408x/7x
002aag733
LPC408x/7x
Transparent top view
ball A1
index area
U
T
R
P
N
M
K
H
L
J
G
F
E
D
C
A
B
2 4 6 8 10 12
13
14
15 17
16
1 3 5 7 9 11
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 10 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
6.2 Pin description
I/O pins on the LPC408x/7x are 5 V tolerant and have input hysteresis unless otherwise
indicated in the table below. Crystal pins, power pins, and reference voltage pins are not
5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5 V
tolerant and the input voltage must be limited to the voltage at the ADC positive reference
pin (VREFP).
All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 in the
order defined by the FUNC bits of the corresponding IOCON register up to the highest
used function number. Each port pin can support up to eight multiplexed functions.
IOCON register FUNC values which are reserved are noted as “R” in the pin configuration
table.
Fig 7. Pin configuration (TFBGA180)
Fig 8. Pin configuration (TFBGA80)
002aag734
LPC408x/7x
1 2 3 4 5 6 7 8 9 10 11 12 13 14
ball A1
index area
P
N
M
L
K
J
G
E
H
F
D
C
B
A
Transparent top view
002aah684
LPC4072FET80
Transparent top view
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
ball A1
index area
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 11 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Table 3. Pin description
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction
controls for each bit. The operation of port 0 pins depends
upon the pin function selected via the pin connect block.
P0[0] 94 U15 M10 66 46 37 J9 [3] I; PU I/O P0[0] — General purpose digital input/output pin.
I CAN_RD1 — CAN1 receiver input.
O U3_TXD — Transmitter output for UART3.
I/O I2C1_SDA — I2C1 data input/output (this pin does not use
a specialized I2C pad).
O U0_TXD — Transmitter output for UART0.
P0[1] 96 T14 N11 67 47 38 J10 [3] I; PU I/O P0[1] — General purpose digital input/output pin.
O CAN_TD1 — CAN1 transmitter output.
I U3_RXD — Receiver input for UART3.
I/O I2C1_SCL — I2C1 clock input/output (this pin does not
use a specialized I2C pad).
I U0_RXD — Receiver input for UART0.
P0[2] 202 C4 D5 141 98 79 A2 [3] I; PU I/O P0[2] — General purpose digital input/output pin.
O U0_TXD — Transmitter output for UART0.
O U3_TXD — Transmitter output for UART3.
P0[3] 204 D6 A3 142 99 80 A1 [3] I; PU I/O P0[3] — General purpose digital input/output pin.
I U0_RXD — Receiver input for UART0.
I U3_RXD — Receiver input for UART3.
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Product data sheet Rev. 3 — 1 May 2014 12 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[4] 168 B12 A11 116 81 - - [3] I; PU I/O P0[4] — General purpose digital input/output pin.
I/O I2S_RX_SCK — I2S Receive clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I CAN_RD2 — CAN2 receiver input.
I T2_CAP0 — Capture input for Timer 2, channel 0.
- R — Function reserved.
I/O CMP_ROSC — Comparator relaxation oscillator for 555
timer applications.
- R — Function reserved.
O LCD_VD[0] — LCD data.
P0[5] 166 C12 B11 115 80 - - [3] I; PU I/O P0[5] — General purpose digital input/output pin.
I/O I2S_RX_WS — I2S Receive word select. It is driven by the
master and received by the slave. Corresponds to the
signal WS in the I2S-bus specification.
O CAN_TD2 — CAN2 transmitter output.
I T2_CAP1 — Capture input for Timer 2, channel 1.
- R — Function reserved.
I CMP_RESET — Comparator reset.
- R — Function reserved.
O LCD_VD[1] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 13 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[6] 164 D13 D11 113 79 64 A7 [3] I; PU I/O P0[6] — General purpose digital input/output pin.
I/O I2S_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I/O SSP1_SSEL — Slave Select for SSP1.
O T2_MAT0 — Match output for Timer 2, channel 0.
O U1_RTS — Request to Send output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable
signal for UART1.
I/O CMP_ROSC — Comparator relaxation oscillator for 555
timer applications.
- R — Function reserved.
O LCD_VD[8] — LCD data.
P0[7] 162 C13 B12 112 78 63 A8 [4] I; IA I/O P0[7] — General purpose digital input/output pin.
I/O I2S_TX_SCK — I2S transmit clock. It is driven by the
master and received by the slave. Corresponds to the
signal SCK in the I2S-bus specification.
I/O SSP1_SCK — Serial Clock for SSP1.
O T2_MAT1 — Match output for Timer 2, channel 1.
I RTC_EV0 — Event input 0 to Event Monitor/Recorder.
I CMP_VREF — Comparator reference voltage.
- R — Function reserved.
O LCD_VD[9] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 14 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[8] 160 A15 C12 111 77 62 A10 [4] I; IA I/O P0[8] — General purpose digital input/output pin.
I/O I2S_TX_WS — I2S Transmit word select. It is driven by the
master and received by the slave. Corresponds to the
signal WS in the I2S-bus specification.
I/O SSP1_MISO — Master In Slave Out for SSP1.
O T2_MAT2 — Match output for Timer 2, channel 2.
I RTC_EV1 — Event input 1 to Event Monitor/Recorder.
I CMP1_IN[3] — Comparator 1, input 3.
- R — Function reserved.
O LCD_VD[16] — LCD data.
P0[9] 158 C14 A13 109 76 61 A9 [4] I; IA I/O P0[9] — General purpose digital input/output pin.
I/O I2S_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
O T2_MAT3 — Match output for Timer 2, channel 3.
I RTC_EV2 — Event input 2 to Event Monitor/Recorder.
I CMP1_IN[2] — Comparator 1, input 2.
- R — Function reserved.
O LCD_VD[17] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 15 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[10] 98 T15 L10 69 48 39 K9 [3] I; PU I/O P0[10] — General purpose digital input/output pin.
O U2_TXD — Transmitter output for UART2.
I/O I2C2_SDA — I2C2 data input/output (this pin does not use
a specialized I2C pad).
O T3_MAT0 — Match output for Timer 3, channel 0.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[5] — LCD data.
P0[11] 100 R14 P12 70 49 40 K10 [3] I; PU I/O P0[11] — General purpose digital input/output pin.
I U2_RXD — Receiver input for UART2.
I/O I2C2_SCL — I2C2 clock input/output (this pin does not
use a specialized I2C pad).
O T3_MAT1 — Match output for Timer 3, channel 1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[10] — LCD data.
P0[12] 41 R1 J4 29 - - - [5] I; PU I/O P0[12] — General purpose digital input/output pin.
O USB_PPWR2 — Port Power enable signal for USB port 2.
I/O SSP1_MISO — Master In Slave Out for SSP1.
I ADC0_IN[6] — A/D converter 0, input 6. When configured
as an ADC input, the digital function of the pin must be
disabled.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 16 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[13] 45 R2 J5 32 - - - [5] I; PU I/O P0[13] — General purpose digital input/output pin.
O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It
is LOW when the device is configured (non-control
endpoints enabled), or when the host is enabled and has
detected a device on the bus. It is HIGH when the device
is not configured, or when host is enabled and has not
detected a device on the bus, or during global suspend. It
transitions between LOW and HIGH (flashes) when the
host is enabled and detects activity on the bus.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
I ADC0_IN[7] — A/D converter 0, input 7. When configured
as an ADC input, the digital function of the pin must be
disabled.
P0[14] 69 T7 M5 48 - - - [3] I; PU I/O P0[14] — General purpose digital input/output pin.
O USB_HSTEN2 — Host Enabled status for USB port 2.
I/O SSP1_SSEL — Slave Select for SSP1.
O USB_CONNECT2 — SoftConnect control for USB port 2.
Signal used to switch an external 1.5 k resistor under
software control. Used with the SoftConnect USB feature.
P0[15] 128 J16 H13 89 62 47 F9 [3] I; PU I/O P0[15] — General purpose digital input/output pin.
O U1_TXD — Transmitter output for UART1.
I/O SSP0_SCK — Serial clock for SSP0.
- R — Function reserved.
- R — Function reserved.
I/O SPIFI_IO[2] — Data bit 0 for SPIFI.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 17 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[16] 130 J14 H14 90 63 48 F8 [3] I; PU I/O P0[16] — General purpose digital input/output pin.
I U1_RXD — Receiver input for UART1.
I/O SSP0_SSEL — Slave Select for SSP0.
- R — Function reserved.
- R — Function reserved.
I/O SPIFI_IO[3] — Data bit 0 for SPIFI.
P0[17] 126 K17 J12 87 61 46 F10 [3] I; PU I/O P0[17] — General purpose digital input/output pin.
I U1_CTS — Clear to Send input for UART1.
I/O SSP0_MISO — Master In Slave Out for SSP0.
- R — Function reserved.
- R — Function reserved.
I/O SPIFI_IO[1] — Data bit 0 for SPIFI.
P0[18] 124 K15 J13 86 60 45 G10 [3] I; PU I/O P0[18] — General purpose digital input/output pin.
I U1_DCD — Data Carrier Detect input for UART1.
I/O SSP0_MOSI — Master Out Slave In for SSP0.
- R — Function reserved.
- R — Function reserved.
I/O SPIFI_IO[0] — Data bit 0 for SPIFI.
P0[19] 122 L17 J10 85 59 - - [3] I; PU I/O P0[19] — General purpose digital input/output pin.
I U1_DSR — Data Set Ready input for UART1.
O SD_CLK — Clock output line for SD card interface.
I/O I2C1_SDA — I2C1 data input/output (this pin does not use
a specialized I2C pad).
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[13] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 18 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[20] 120 M17 K14 83 58 - - [3] I; PU I/O P0[20] — General purpose digital input/output pin.
O U1_DTR — Data Terminal Ready output for UART1. Can
also be configured to be an RS-485/EIA-485 output enable
signal for UART1.
I/O SD_CMD — Command line for SD card interface.
I/O I2C1_SCL — I2C1 clock input/output (this pin does not
use a specialized I2C pad).
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[14] — LCD data.
P0[21] 118 M16 K11 82 57 - - [3] I; PU I/O P0[21] — General purpose digital input/output pin.
I U1_RI — Ring Indicator input for UART1.
O SD_PWR — Power Supply Enable for external SD card
power supply.
O U4_OE — RS-485/EIA-485 output enable signal for
UART4.
I CAN_RD1 — CAN1 receiver input.
I/O U4_SCLK — USART 4 clock input or output in
synchronous mode.
P0[22] 116 N17 L14 80 56 44 H10 [6] I; PU I/O P0[22] — General purpose digital input/output pin.
O U1_RTS — Request to Send output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable
signal for UART1.
I/O SD_DAT[0] — Data line 0 for SD card interface.
O U4_TXD — Transmitter output for USART4 (input/output
in smart card mode).
O CAN_TD1 — CAN1 transmitter output.
O SPIFI_CLK — Clock output for SPIFI.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 19 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[23] 18 H1 F5 13 9 - - [5] I; PU I/O P0[23] — General purpose digital input/output pin.
I ADC0_IN[0] — A/D converter 0, input 0. When configured
as an ADC input, the digital function of the pin must be
disabled.
I/O I2S_RX_SCK — Receive Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK
in the I2S-bus specification.
I T3_CAP0 — Capture input for Timer 3, channel 0.
P0[24] 16 G2 E1 11 8 - - [5] I; PU I/O P0[24] — General purpose digital input/output pin.
I ADC0_IN[1] — A/D converter 0, input 1. When configured
as an ADC input, the digital function of the pin must be
disabled.
I/O I2S_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the
signal WS in the I2S-bus specification.
I T3_CAP1 — Capture input for Timer 3, channel 1.
P0[25] 14 F1 E4 10 7 7 D1 [5] I; PU I/O P0[25] — General purpose digital input/output pin.
I ADC0_IN[2] — A/D converter 0, input 2. When configured
as an ADC input, the digital function of the pin must be
disabled.
I/O I2S_RX_SDA — Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
O U3_TXD — Transmitter output for UART3.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 20 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P0[26] 12 E1 D1 8 6 6 D2 [7] I; PU I/O P0[26] — General purpose digital input/output pin.
I ADC0_IN[3] — A/D converter 0, input 3. When configured
as an ADC input, the digital function of the pin must be
disabled.
O DAC_OUT — D/A converter output. When configured as
the DAC output, the digital function of the pin must be
disabled.
I U3_RXD — Receiver input for UART3.
P0[27] 50 T1 L3 35 25 - - [8] I I/O P0[27] — General purpose digital input/output pin.
I/O I2C0_SDA — I2C0 data input/output. (This pin uses a
specialized I2C pad).
I/O USB_SDA1 — I2C serial data for communication with an
external USB transceiver.
P0[28] 48 R3 M1 34 24 - - [8] I I/O P0[28] — General purpose digital input/output pin.
I/O I2C0_SCL — I2C0 clock input/output (this pin uses a
specialized I2C pad.
I/O USB_SCL1 — I2C serial clock for communication with an
external USB transceiver.
P0[29] 61 U4 K5 42 29 22 J3 [9] I I/O P0[29] — General purpose digital input/output pin.
I/O USB_D+1 — USB port 1 bidirectional D+ line.
I EINT0 — External interrupt 0 input.
P0[30] 62 R6 N4 43 30 23 K3 [9] I I/O P0[30] — General purpose digital input/output pin.
I/O USB_D1 — USB port 1 bidirectional D line.
I EINT1 — External interrupt 1 input.
P0[31] 51 T2 N1 36 - - - [9] I I/O P0[31] — General purpose digital input/output pin.
I/O USB_D+2 — USB port 2 bidirectional D+ line.
P1[0] to P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction
controls for each bit. The operation of port 1 pins depends
upon the pin function selected via the pin connect block
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 21 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[0] 196 A3 B5 136 95 76 A3 [3] I; PU I/O P1[0] — General purpose digital input/output pin.
O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII
interface).
- R — Function reserved.
I T3_CAP1 — Capture input for Timer 3, channel 1.
I/O SSP2_SCK — Serial clock for SSP2.
P1[1] 194 B5 A5 135 94 75 B4 [3] I; PU I/O P1[1] — General purpose digital input/output pin.
O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII
interface).
- R — Function reserved.
O T3_MAT3 — Match output for Timer 3, channel 3.
I/O SSP2_MOSI — Master Out Slave In for SSP2.
P1[2] 185 D9 B7 - - - - [3] I; PU I/O P1[2] — General purpose digital input/output pin.
O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
O SD_CLK — Clock output line for SD card interface.
O PWM0[1] — Pulse Width Modulator 0, output 1.
P1[3] 177 A10 A9 - - - - [3] I; PU I/O P1[3] — General purpose digital input/output pin.
O ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O SD_CMD — Command line for SD card interface.
O PWM0[2] — Pulse Width Modulator 0, output 2.
P1[4] 192 A5 C6 133 93 74 B5 [3] I; PU I/O P1[4] — General purpose digital input/output pin.
O ENET_TX_EN — Ethernet transmit data enable (RMII/MII
interface).
- R — Function reserved.
O T3_MAT2 — Match output for Timer 3, channel 2.
I/O SSP2_MISO — Master In Slave Out for SSP2.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 22 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[5] 156 A17 B13 - - - - [3] I; PU I/O P1[5] — General purpose digital input/output pin.
O ENET_TX_ER — Ethernet Transmit Error (MII interface).
O SD_PWR — Power Supply Enable for external SD card
power supply.
O PWM0[3] — Pulse Width Modulator 0, output 3.
- R — Function reserved.
I CMP1_IN[1] — Comparator 1, input 1.
P1[6] 171 B11 B10 - - - - [3] I; PU I/O P1[6] — General purpose digital input/output pin.
I ENET_TX_CLK — Ethernet Transmit Clock (MII
interface).
I/O SD_DAT[0] — Data line 0 for SD card interface.
O PWM0[4] — Pulse Width Modulator 0, output 4.
- R — Function reserved.
I CMP0_IN[3] — Comparator 0, input 3.
P1[7] 153 D14 C13 - - - - [3] I; PU I/O P1[7] — General purpose digital input/output pin.
I ENET_COL — Ethernet Collision detect (MII interface).
I/O SD_DAT[1] — Data line 1 for SD card interface.
O PWM0[5] — Pulse Width Modulator 0, output 5.
- R — Function reserved.
I CMP1_IN[0] — Comparator 1, input 0.
P1[8] 190 C7 B6 132 92 73 C5 [3] I; PU I/O P1[8] — General purpose digital input/output pin.
I ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense
(MII interface) or Ethernet Carrier Sense/Data Valid (RMII
interface).
- R — Function reserved.
O T3_MAT1 — Match output for Timer 3, channel 1.
I/O SSP2_SSEL — Slave Select for SSP2.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 23 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[9] 188 A6 D7 131 91 72 A4 [3] I; PU I/O P1[9] — General purpose digital input/output pin.
I ENET_RXD0 — Ethernet receive data 0 (RMII/MII
interface).
- R — Function reserved.
O T3_MAT0 — Match output for Timer 3, channel 0.
P1[10] 186 C8 A7 129 90 71 A5 [3] I; PU I/O P1[10] — General purpose digital input/output pin.
I ENET_RXD1 — Ethernet receive data 1 (RMII/MII
interface).
- R — Function reserved.
I T3_CAP0 — Capture input for Timer 3, channel 0.
P1[11] 163 A14 A12 - - - - [3] I; PU I/O P1[11] — General purpose digital input/output pin.
I ENET_RXD2 — Ethernet Receive Data 2 (MII interface).
I/O SD_DAT[2] — Data line 2 for SD card interface.
O PWM0[6] — Pulse Width Modulator 0, output 6.
P1[12] 157 A16 A14 - - - - [3] I; PU I/O P1[12] — General purpose digital input/output pin.
I ENET_RXD3 — Ethernet Receive Data (MII interface).
I/O SD_DAT[3] — Data line 3 for SD card interface.
I PWM0_CAP0 — Capture input for PWM0, channel 0.
- R — Function reserved.
O CMP1_OUT — Comparator 1, output.
P1[13] 147 D16 D14 - - - - [3] I; PU I/O P1[13] — General purpose digital input/output pin.
I ENET_RX_DV — Ethernet Receive Data Valid (MII
interface).
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 24 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[14] 184 A7 D8 128 89 70 C6 [3] I; PU I/O P1[14] — General purpose digital input/output pin.
I ENET_RX_ER — Ethernet receive error (RMII/MII
interface).
- R — Function reserved.
I T2_CAP0 — Capture input for Timer 2, channel 0.
- R — Function reserved.
I CMP0_IN[0] — Comparator 0, input 0.
P1[15] 182 A8 A8 126 88 69 B6 [3] I; PU I/O P1[15] — General purpose digital input/output pin.
I ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).
- R — Function reserved.
I/O I2C2_SDA — I2C2 data input/output (this pin does not use
a specialized I2C pad).
P1[16] 180 D10 B8 125 87 - - [3] I; PU I/O P1[16] — General purpose digital input/output pin.
O ENET_MDC — Ethernet MIIM clock.
O I2S_TX_MCLK — I2S transmit master clock.
- R — Function reserved.
- R — Function reserved.
I CMP0_IN[1] — Comparator 0, input 1.
P1[17] 178 A9 C9 123 86 - - [3] I; PU I/O P1[17] — General purpose digital input/output pin.
I/O ENET_MDIO — Ethernet MIIM data input and output.
O I2S_RX_MCLK — I2S receive master clock.
- R — Function reserved.
- R — Function reserved.
I CMP0_IN[2] — Comparator 0, input 2.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 25 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[18] 66 P7 L5 46 32 25 K4 [3] I; PU I/O P1[18] — General purpose digital input/output pin.
O USB_UP_LED1 — It is LOW when the device is
configured (non-control endpoints enabled), or when the
host is enabled and has detected a device on the bus. It is
HIGH when the device is not configured, or when host is
enabled and has not detected a device on the bus, or
during global suspend. It transitions between LOW and
HIGH (flashes) when the host is enabled and detects
activity on the bus.
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
I T1_CAP0 — Capture input for Timer 1, channel 0.
- R — Function reserved.
I/O SSP1_MISO — Master In Slave Out for SSP1.
P1[19] 68 U6 P5 47 33 26 J4 [3] I; PU I/O P1[19] — General purpose digital input/output pin.
O USB_TX_E1 — Transmit Enable signal for USB port 1
(OTG transceiver).
O USB_PPWR1 — Port Power enable signal for USB port 1.
I T1_CAP1 — Capture input for Timer 1, channel 1.
O MC_0A — Motor control PWM channel 0, output A.
I/O SSP1_SCK — Serial clock for SSP1.
O U2_OE — RS-485/EIA-485 output enable signal for
UART2.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 26 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[20] 70 U7 K6 49 34 27 J5 [3] I; PU I/O P1[20] — General purpose digital input/output pin.
O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG
transceiver).
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I QEI_PHA — Quadrature Encoder Interface PHA input.
I MC_FB0 — Motor control PWM channel 0 feedback input.
I/O SSP0_SCK — Serial clock for SSP0.
O LCD_VD[6] — LCD data.
O LCD_VD[10] — LCD data.
P1[21] 72 R8 N6 50 35 - - [3] I; PU I/O P1[21] — General purpose digital input/output pin.
O USB_TX_DM1 — D transmit data for USB port 1 (OTG
transceiver).
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I/O SSP0_SSEL — Slave Select for SSP0.
I MC_ABORT — Motor control PWM, active low fast abort.
- R — Function reserved.
O LCD_VD[7] — LCD data.
O LCD_VD[11] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 27 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[22] 74 U8 M6 51 36 28 K5 [3] I; PU I/O P1[22] — General purpose digital input/output pin.
I USB_RCV1 — Differential receive data for USB port 1
(OTG transceiver).
I USB_PWRD1 — Power Status for USB port 1 (host power
switch).
O T1_MAT0 — Match output for Timer 1, channel 0.
O MC_0B — Motor control PWM channel 0, output B.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
O LCD_VD[8] — LCD data.
O LCD_VD[12] — LCD data.
P1[23] 76 P9 N7 53 37 29 H5 [3] I; PU I/O P1[23] — General purpose digital input/output pin.
I USB_RX_DP1 — D+ receive data for USB port 1 (OTG
transceiver).
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I QEI_PHB — Quadrature Encoder Interface PHB input.
I MC_FB1 — Motor control PWM channel 1 feedback input.
I/O SSP0_MISO — Master In Slave Out for SSP0.
O LCD_VD[9] — LCD data.
O LCD_VD[13] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 28 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[24] 78 T9 P7 54 38 30 J6 [3] I; PU I/O P1[24] — General purpose digital input/output pin.
I USB_RX_DM1 — D receive data for USB port 1 (OTG
transceiver).
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I QEI_IDX — Quadrature Encoder Interface INDEX input.
I MC_FB2 — Motor control PWM channel 2 feedback input.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
O LCD_VD[10] — LCD data.
O LCD_VD[14] — LCD data.
P1[25] 80 T10 L7 56 39 31 K6 [3] I; PU I/O P1[25] — General purpose digital input/output pin.
O USB_LS1 — Low Speed status for USB port 1 (OTG
transceiver).
O USB_HSTEN1 — Host Enabled status for USB port 1.
O T1_MAT1 — Match output for Timer 1, channel 1.
O MC_1A — Motor control PWM channel 1, output A.
O CLKOUT — Selectable clock output.
O LCD_VD[11] — LCD data.
O LCD_VD[15] — LCD data.
P1[26] 82 R10 P8 57 40 32 H6 [3] I; PU I/O P1[26] — General purpose digital input/output pin.
O USB_SSPND1 — USB port 1 Bus Suspend status (OTG
transceiver).
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
I T0_CAP0 — Capture input for Timer 0, channel 0.
O MC_1B — Motor control PWM channel 1, output B.
I/O SSP1_SSEL — Slave Select for SSP1.
O LCD_VD[12] — LCD data.
O LCD_VD[20] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 29 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[27] 88 T12 M9 61 43 - - [3] I; PU I/O P1[27] — General purpose digital input/output pin.
I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG
transceiver).
I USB_OVRCR1 — USB port 1 Over-Current status.
I T0_CAP1 — Capture input for Timer 0, channel 1.
O CLKOUT — Selectable clock output.
- R — Function reserved.
O LCD_VD[13] — LCD data.
O LCD_VD[21] — LCD data.
P1[28] 90 T13 P10 63 44 35 J8 [3] I; PU I/O P1[28] — General purpose digital input/output pin.
I/O USB_SCL1 — USB port 1 I2C serial clock (OTG
transceiver).
I PWM1_CAP0 — Capture input for PWM1, channel 0.
O T0_MAT0 — Match output for Timer 0, channel 0.
O MC_2A — Motor control PWM channel 2, output A.
I/O SSP0_SSEL — Slave Select for SSP0.
O LCD_VD[14] — LCD data.
O LCD_VD[22] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 30 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P1[29] 92 U14 N10 64 45 36 K8 [3] I; PU I/O P1[29] — General purpose digital input/output pin.
I/O USB_SDA1 — USB port 1 I2C serial data (OTG
transceiver).
I PWM1_CAP1 — Capture input for PWM1, channel 1.
O T0_MAT1 — Match output for Timer 0, channel 1.
O MC_2B — Motor control PWM channel 2, output B.
O U4_TXD — Transmitter output for USART4 (input/output
in smart card mode).
O LCD_VD[15] — LCD data.
O LCD_VD[23] — LCD data.
P1[30] 42 P2 K3 30 21 18 J2 [5] I; PU I/O P1[30] — General purpose digital input/output pin.
I USB_PWRD2 — Power Status for USB port 2.
I USB_VBUS — Monitors the presence of USB bus power.
This signal must be HIGH for USB reset to occur.
I ADC0_IN[4] — A/D converter 0, input 4. When configured
as an ADC input, the digital function of the pin must be
disabled.
I/O I2C0_SDA — I2C0 data input/output (this pin does not use
a specialized I2C pad.
O U3_OE — RS-485/EIA-485 output enable signal for
UART3.
P1[31] 40 P1 K2 28 20 17 H2 [5] I; PU I/O P1[31] — General purpose digital input/output pin.
I USB_OVRCR2 — Over-Current status for USB port 2.
I/O SSP1_SCK — Serial Clock for SSP1.
I ADC0_IN[5] — A/D converter 0, input 5. When configured
as an ADC input, the digital function of the pin must be
disabled.
I/O I2C0_SCL — I2C0 clock input/output (this pin does not
use a specialized I2C pad.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 31 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[0] to P2[31] I/O Port 2: Port 2 is a 32 bit I/O port with individual direction
controls for each bit. The operation of port 1 pins depends
upon the pin function selected via the pin connect block.
P2[0] 154 B17 D12 107 75 60 B10 [3] I; PU I/O P2[0] — General purpose digital input/output pin.
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
O U1_TXD — Transmitter output for UART1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_PWR — LCD panel power enable.
P2[1] 152 E14 C14 106 74 59 B8 [3] I; PU I/O P2[1] — General purpose digital input/output pin.
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I U1_RXD — Receiver input for UART1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_LE — Line end signal.
P2[2] 150 D15 E11 105 73 58 B9 [3] I; PU I/O P2[2] — General purpose digital input/output pin.
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I U1_CTS — Clear to Send input for UART1.
O T2_MAT3 — Match output for Timer 2, channel 3.
- R — Function reserved.
O TRACEDATA[3] — Trace data, bit 3.
- R — Function reserved.
O LCD_DCLK — LCD panel clock.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 32 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[3] 144 E16 E13 100 70 55 C10 [3] I; PU I/O P2[3] — General purpose digital input/output pin.
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I U1_DCD — Data Carrier Detect input for UART1.
O T2_MAT2 — Match output for Timer 2, channel 2.
- R — Function reserved.
O TRACEDATA[2] — Trace data, bit 2.
- R — Function reserved.
O LCD_FP — Frame pulse (STN). Vertical synchronization
pulse (TFT).
P2[4] 142 D17 E14 99 69 54 C9 [3] I; PU I/O P2[4] — General purpose digital input/output pin.
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I U1_DSR — Data Set Ready input for UART1.
O T2_MAT1 — Match output for Timer 2, channel 1.
- R — Function reserved.
O TRACEDATA[1] — Trace data, bit 1.
- R — Function reserved.
O LCD_ENAB_M — STN AC bias drive or TFT data enable
output.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 33 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[5] 140 F16 F12 97 68 53 D10 [3] I; PU I/O P2[5] — General purpose digital input/output pin.
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
O U1_DTR — Data Terminal Ready output for UART1. Can
also be configured to be an RS-485/EIA-485 output enable
signal for UART1.
O T2_MAT0 — Match output for Timer 2, channel 0.
- R — Function reserved.
O TRACEDATA[0] — Trace data, bit 0.
- R — Function reserved.
O LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).
P2[6] 138 E17 F13 96 67 52 E8 [3] I; PU I/O P2[6] — General purpose digital input/output pin.
I PWM1_CAP0 — Capture input for PWM1, channel 0.
I U1_RI — Ring Indicator input for UART1.
I T2_CAP0 — Capture input for Timer 2, channel 0.
O U2_OE — RS-485/EIA-485 output enable signal for
UART2.
O TRACECLK — Trace clock.
O LCD_VD[0] — LCD data.
O LCD_VD[4] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 34 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[7] 136 G16 G11 95 66 51 D9 [3] I; PU I/O P2[7] — General purpose digital input/output pin.
I CAN_RD2 — CAN2 receiver input.
O U1_RTS — Request to Send output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable
signal for UART1.
- R — Function reserved.
- R — Function reserved.
O SPIFI_CS — Chip select output for SPIFI.
O LCD_VD[1] — LCD data.
O LCD_VD[5] — LCD data.
P2[8] 134 H15 G14 93 65 50 E9 [3] I; PU I/O P2[8] — General purpose digital input/output pin.
O CAN_TD2 — CAN2 transmitter output.
O U2_TXD — Transmitter output for UART2.
I U1_CTS — Clear to Send input for UART1.
O ENET_MDC — Ethernet MIIM clock.
- R — Function reserved.
O LCD_VD[2] — LCD data.
O LCD_VD[6] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 35 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[9] 132 H16 H11 92 64 49 E10 [3] I; PU I/O P2[9] — General purpose digital input/output pin.
O USB_CONNECT1 — USB1 SoftConnect control. Signal
used to switch an external 1.5 k resistor under the
software control. Used with the SoftConnect USB feature.
I U2_RXD — Receiver input for UART2.
I U4_RXD — Receiver input for USART4.
I/O ENET_MDIO — Ethernet MIIM data input and output.
- R — Function reserved.
I LCD_VD[3] — LCD data.
I LCD_VD[7] — LCD data.
P2[10] 110 N15 M13 76 53 41 H9 [10] I; PU I/O P2[10] — General purpose digital input/output pin. This
pin includes a 10 ns input glitch filter.
A LOW on this pin while RESET is LOW forces the on-chip
boot loader to take over control of the part after a reset and
go into ISP mode.
I EINT0 — External interrupt 0 input.
I NMI — Non-maskable interrupt input.
P2[11] 108 T17 M12 75 52 - - [10] I; PU I/O P2[11] — General purpose digital input/output pin. This
pin includes a 10 ns input glitch filter.
I EINT1 — External interrupt 1 input.
I/O SD_DAT[1] — Data line 1 for SD card interface.
I/O I2S_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK
in the I2S-bus specification.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_CLKIN — LCD clock.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 36 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[12] 106 N14 N14 73 51 - - [10] I; PU I/O P2[12] — General purpose digital input/output pin. This
pin includes a 10 ns input glitch filter.
I EINT2 — External interrupt 2 input.
I/O SD_DAT[2] — Data line 2 for SD card interface.
I/O I2S_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the
signal WS in the I2S-bus specification.
O LCD_VD[4] — LCD data.
O LCD_VD[3] — LCD data.
O LCD_VD[8] — LCD data.
O LCD_VD[18] — LCD data.
P2[13] 102 T16 M11 71 50 - - [10] I; PU I/O P2[13] — General purpose digital input/output pin. This
pin includes a 10 ns input glitch filter.
I EINT3 — External interrupt 3 input.
I/O SD_DAT[3] — Data line 3 for SD card interface.
I/O I2S_TX_SDA — Transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the
signal SD in the I2S-bus specification.
- R — Function reserved.
O LCD_VD[5] — LCD data.
O LCD_VD[9] — LCD data.
O LCD_VD[19] — LCD data.
P2[14] 91 R12 - - - - - [3] I; PU I/O P2[14] — General purpose digital input/output pin.
O EMC_CS2 — LOW active Chip Select 2 signal.
I/O I2C1_SDA — I2C1 data input/output (this pin does not use
a specialized I2C pad).
I T2_CAP0 — Capture input for Timer 2, channel 0.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 37 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[15] 99 P13 - - - - - [3] I; PU I/O P2[15] — General purpose digital input/output pin.
O EMC_CS3 — LOW active Chip Select 3 signal.
I/O I2C1_SCL — I2C1 clock input/output (this pin does not
use a specialized I2C pad).
I T2_CAP1 — Capture input for Timer 2, channel 1.
P2[16] 87 R11 P9 - - - - [3] I; PU I/O P2[16] — General purpose digital input/output pin.
O EMC_CAS — LOW active SDRAM Column Address
Strobe.
P2[17] 95 R13 P11 - - - - [3] I; PU I/O P2[17] — General purpose digital input/output pin.
O EMC_RAS — LOW active SDRAM Row Address Strobe.
P2[18] 59 U3 P3 - - - - [6] I; PU I/O P2[18] — General purpose digital input/output pin.
O EMC_CLK[0] — SDRAM clock 0.
P2[19] 67 R7 N5 - - - - [6] I; PU I/O P2[19] — General purpose digital input/output pin.
O EMC_CLK[1] — SDRAM clock 1.
P2[20] 73 T8 P6 - - - - [3] I; PU I/O P2[20] — General purpose digital input/output pin.
O EMC_DYCS0 — SDRAM chip select 0.
P2[21] 81 U11 N8 - - - - [3] I; PU I/O P2[21] — General purpose digital input/output pin.
O EMC_DYCS1 — SDRAM chip select 1.
P2[22] 85 U12 - - - - - [3] I; PU I/O P2[22] — General purpose digital input/output pin.
O EMC_DYCS2 — SDRAM chip select 2.
I/O SSP0_SCK — Serial clock for SSP0.
I T3_CAP0 — Capture input for Timer 3, channel 0.
P2[23] 64 U5 - - - - - [3] I; PU I/O P2[23] — General purpose digital input/output pin.
O EMC_DYCS3 — SDRAM chip select 3.
I/O SSP0_SSEL — Slave Select for SSP0.
I T3_CAP1 — Capture input for Timer 3, channel 1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 38 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[24] 53 P5 P1 - - - - [3] I; PU I/O P2[24] — General purpose digital input/output pin.
O EMC_CKE0 — SDRAM clock enable 0.
P2[25] 54 R4 P2 - - - - [3] I; PU I/O P2[25] — General purpose digital input/output pin.
O EMC_CKE1 — SDRAM clock enable 1.
P2[26] 57 T4 - - - - - [3] I; PU I/O P2[26] — General purpose digital input/output pin.
O EMC_CKE2 — SDRAM clock enable 2.
I/O SSP0_MISO — Master In Slave Out for SSP0.
O T3_MAT0 — Match output for Timer 3, channel 0.
P2[27] 47 P3 - - - - - [3] I; PU I/O P2[27] — General purpose digital input/output pin.
O EMC_CKE3 — SDRAM clock enable 3.
I/O SSP0_MOSI — Master Out Slave In for SSP0.
O T3_MAT1 — Match output for Timer 3, channel 1.
P2[28] 49 P4 M2 - - - - [3] I; PU I/O P2[28] — General purpose digital input/output pin.
O EMC_DQM0 — Data mask 0 used with SDRAM and static
devices.
P2[29] 43 N3 L1 - - - - [3] I; PU I/O P2[29] — General purpose digital input/output pin.
O EMC_DQM1 — Data mask 1 used with SDRAM and static
devices.
P2[30] 31 L4 - - - - - [3] I; PU I/O P2[30] — General purpose digital input/output pin.
O EMC_DQM2 — Data mask 2 used with SDRAM and static
devices.
I/O I2C2_SDA — I2C2 data input/output (this pin does not use
a specialized I2C pad).
O T3_MAT2 — Match output for Timer 3, channel 2.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 39 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P2[31] 39 N2 - - - - - [3] I; PU I/O P2[31] — General purpose digital input/output pin.
O EMC_DQM3 — Data mask 3 used with SDRAM and static
devices.
I/O I2C2_SCL — I2C2 clock input/output (this pin does not
use a specialized I2C pad).
O T3_MAT3 — Match output for Timer 3, channel 3.
P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction
controls for each bit. The operation of port 3 pins depends
upon the pin function selected via the pin connect block.
P3[0] 197 B4 D6 137 - - - [3] I; PU I/O P3[0] — General purpose digital input/output pin.
I/O EMC_D[0] — External memory data line 0.
P3[1] 201 B3 E6 140 - - - [3] I; PU I/O P3[1] — General purpose digital input/output pin.
I/O EMC_D[1] — External memory data line 1.
P3[2] 207 B1 A2 144 - - - [3] I; PU I/O P3[2] — General purpose digital input/output pin.
I/O EMC_D[2] — External memory data line 2.
P3[3] 3 E4 G5 2 - - - [3] I; PU I/O P3[3] — General purpose digital input/output pin.
I/O EMC_D[3] — External memory data line 3.
P3[4] 13 F2 D3 9 - - - [3] I; PU I/O P3[4] — General purpose digital input/output pin.
I/O EMC_D[4] — External memory data line 4.
P3[5] 17 G1 E3 12 - - - [3] I; PU I/O P3[5] — General purpose digital input/output pin.
I/O EMC_D[5] — External memory data line 5.
P3[6] 23 J1 F4 16 - - - [3] I; PU I/O P3[6] — General purpose digital input/output pin.
I/O EMC_D[6] — External memory data line 6.
P3[7] 27 L1 G3 19 - - - [3] I; PU I/O P3[7] — General purpose digital input/output pin.
I/O EMC_D[7] — External memory data line 7.
P3[8] 191 D8 A6 - - - - [3] I; PU I/O P3[8] — General purpose digital input/output pin.
I/O EMC_D[8] — External memory data line 8.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 40 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P3[9] 199 C5 A4 - - - - [3] I; PU I/O P3[9] — General purpose digital input/output pin.
I/O EMC_D[9] — External memory data line 9.
P3[10] 205 B2 B3 - - - - [3] I; PU I/O P3[10] — General purpose digital input/output pin.
I/O EMC_D[10] — External memory data line 10.
P3[11] 208 D5 B2 - - - - [3] I; PU I/O P3[11] — General purpose digital input/output pin.
I/O EMC_D[11] — External memory data line 11.
P3[12] 1 D4 A1 - - - - [3] I; PU I/O P3[12] — General purpose digital input/output pin.
I/O EMC_D[12] — External memory data line 12.
P3[13] 7 C1 C1 - - - - [3] I; PU I/O P3[13] — General purpose digital input/output pin.
I/O EMC_D[13] — External memory data line 13.
P3[14] 21 H2 F1 - - - - [3] I; PU I/O P3[14] — General purpose digital input/output pin.
I/O EMC_D[14] — External memory data line 14.
P3[15] 28 M1 G4 - - - - [3] I; PU I/O P3[15] — General purpose digital input/output pin.
I/O EMC_D[15] — External memory data line 15.
P3[16] 137 F17 - - - - - [3] I; PU I/O P3[16] — General purpose digital input/output pin.
I/O EMC_D[16] — External memory data line 16.
O PWM0[1] — Pulse Width Modulator 0, output 1.
O U1_TXD — Transmitter output for UART1.
P3[17] 143 F15 - - - - - [3] I; PU I/O P3[17] — General purpose digital input/output pin.
I/O EMC_D[17] — External memory data line 17.
O PWM0[2] — Pulse Width Modulator 0, output 2.
I U1_RXD — Receiver input for UART1.
P3[18] 151 C15 - - - - - [3] I; PU I/O P3[18] — General purpose digital input/output pin.
I/O EMC_D[18] — External memory data line 18.
O PWM0[3] — Pulse Width Modulator 0, output 3.
I U1_CTS — Clear to Send input for UART1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 41 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P3[19] 161 B14 - - - - - [3] I; PU I/O P3[19] — General purpose digital input/output pin.
I/O EMC_D[19] — External memory data line 19.
O PWM0[4] — Pulse Width Modulator 0, output 4.
I U1_DCD — Data Carrier Detect input for UART1.
P3[20] 167 A13 - - - - - [3] I; PU I/O P3[20] — General purpose digital input/output pin.
I/O EMC_D[20] — External memory data line 20.
O PWM0[5] — Pulse Width Modulator 0, output 5.
I U1_DSR — Data Set Ready input for UART1.
P3[21] 175 C10 - - - - - [3] I; PU I/O P3[21] — General purpose digital input/output pin.
I/O EMC_D[21] — External memory data line 21.
O PWM0[6] — Pulse Width Modulator 0, output 6.
O U1_DTR — Data Terminal Ready output for UART1. Can
also be configured to be an RS-485/EIA-485 output enable
signal for UART1.
P3[22] 195 C6 - - - - - [3] I; PU I/O P3[22] — General purpose digital input/output pin.
I/O EMC_D[22] — External memory data line 22.
I PWM0_CAP0 — Capture input for PWM0, channel 0.
I U1_RI — Ring Indicator input for UART1.
P3[23] 65 T6 M4 45 - - - [3] I; PU I/O P3[23] — General purpose digital input/output pin.
I/O EMC_D[23] — External memory data line 23.
I PWM1_CAP0 — Capture input for PWM1, channel 0.
I T0_CAP0 — Capture input for Timer 0, channel 0.
P3[24] 58 R5 N3 40 - - - [3] I; PU I/O P3[24] — General purpose digital input/output pin.
I/O EMC_D[24] — External memory data line 24.
O PWM1[1] — Pulse Width Modulator 1, output 1.
I T0_CAP1 — Capture input for Timer 0, channel 1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 42 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P3[25] 56 U2 M3 39 27 - - [3] I; PU I/O P3[25] — General purpose digital input/output pin.
I/O EMC_D[25] — External memory data line 25.
O PWM1[2] — Pulse Width Modulator 1, output 2.
O T0_MAT0 — Match output for Timer 0, channel 0.
P3[26] 55 T3 K7 38 26 - - [3] I; PU I/O P3[26] — General purpose digital input/output pin.
I/O EMC_D[26] — External memory data line 26.
O PWM1[3] — Pulse Width Modulator 1, output 3.
O T0_MAT1 — Match output for Timer 0, channel 1.
I STCLK — System tick timer clock input. The maximum
STCLK frequency is 1/4 of the ARM processor clock
frequency CCLK.
P3[27] 203 A1 - - - - - [3] I; PU I/O P3[27] — General purpose digital input/output pin.
I/O EMC_D[27] — External memory data line 27.
O PWM1[4] — Pulse Width Modulator 1, output 4.
I T1_CAP0 — Capture input for Timer 1, channel 0.
P3[28] 5 D2 - - - - - [3] I; PU I/O P3[28] — General purpose digital input/output pin.
I/O EMC_D[28] — External memory data line 28.
O PWM1[5] — Pulse Width Modulator 1, output 5.
I T1_CAP1 — Capture input for Timer 1, channel 1.
P3[29] 11 F3 - - - - - [3] I; PU I/O P3[29] — General purpose digital input/output pin.
I/O EMC_D[29] — External memory data line 29.
O PWM1[6] — Pulse Width Modulator 1, output 6.
O T1_MAT0 — Match output for Timer 1, channel 0.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 43 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P3[30] 19 H3 - - - - - [3] I; PU I/O P3[30] — General purpose digital input/output pin.
I/O EMC_D[30] — External memory data line 30.
O U1_RTS — Request to Send output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable
signal for UART1.
O T1_MAT1 — Match output for Timer 1, channel 1.
P3[31] 25 J3 - - - - - [3] I; PU I/O P3[31] — General purpose digital input/output pin.
I/O EMC_D[31] — External memory data line 31.
- R — Function reserved.
O T1_MAT2 — Match output for Timer 1, channel 2.
P4[0] to P4[31] - I/O Port 4: Port 4 is a 32-bit I/O port with individual direction
controls for each bit. The operation of port 4 pins depends
upon the pin function selected via the pin connect block.
P4[0] 75 U9 L6 52 - - - [3] I; PU I/O P4[0] — General purpose digital input/output pin.
I/O EMC_A[0] — External memory address line 0.
P4[1] 79 U10 M7 55 - - - [3] I; PU I/O P4[1] — General purpose digital input/output pin.
I/O EMC_A[1] — External memory address line 1.
P4[2] 83 T11 M8 58 - - - [3] I; PU I/O P4[2] — General purpose digital input/output pin.
I/O EMC_A[2] — External memory address line 2.
P4[3] 97 U16 K9 68 - - - [3] I; PU I/O P4[3] — General purpose digital input/output pin.
I/O EMC_A[3] — External memory address line 3.
P4[4] 103 R15 P13 72 - - - [3] I; PU I/O P4[4] — General purpose digital input/output pin.
I/O EMC_A[4] — External memory address line 4.
P4[5] 107 R16 H10 74 - - - [3] I; PU I/O P4[5] — General purpose digital input/output pin.
I/O EMC_A[5] — External memory address line 5.
P4[6] 113 M14 K10 78 - - - [3] I; PU I/O P4[6] — General purpose digital input/output pin.
I/O EMC_A[6] — External memory address line 6.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 44 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P4[7] 121 L16 K12 84 - - - [3] I; PU I/O P4[7] — General purpose digital input/output pin.
I/O EMC_A[7] — External memory address line 7.
P4[8] 127 J17 J11 88 - - - [3] I; PU I/O P4[8] — General purpose digital input/output pin.
I/O EMC_A[8] — External memory address line 8.
P4[9] 131 H17 H12 91 - - - [3] I; PU I/O P4[9] — General purpose digital input/output pin.
I/O EMC_A[9] — External memory address line 9.
P4[10] 135 G17 G12 94 - - - [3] I; PU I/O P4[10] — General purpose digital input/output pin.
I/O EMC_A[10] — External memory address line 10.
P4[11] 145 F14 F11 101 - - - [3] I; PU I/O P4[11] — General purpose digital input/output pin.
I/O EMC_A[11] — External memory address line 11.
P4[12] 149 C16 F10 104 - - - [3] I; PU I/O P4[12] — General purpose digital input/output pin.
I/O EMC_A[12] — External memory address line 12.
P4[13] 155 B16 B14 108 - - - [3] I; PU I/O P4[13] — General purpose digital input/output pin.
I/O EMC_A[13] — External memory address line 13.
P4[14] 159 B15 E8 110 - - - [3] I; PU I/O P4[14] — General purpose digital input/output pin.
I/O EMC_A[14] — External memory address line 14.
P4[15] 173 A11 C10 120 - - - [3] I; PU I/O P4[15] — General purpose digital input/output pin.
I/O EMC_A[15] — External memory address line 15.
P4[16] 101 U17 N12 - - - - [3] I; PU I/O P4[16] — General purpose digital input/output pin.
I/O EMC_A[16] — External memory address line 16.
P4[17] 104 P14 N13 - - - - [3] I; PU I/O P4[17] — General purpose digital input/output pin.
I/O EMC_A[17] — External memory address line 17.
P4[18] 105 P15 P14 - - - - [3] I; PU I/O P4[18] — General purpose digital input/output pin.
I/O EMC_A[18] — External memory address line 18.
P4[19] 111 P16 M14 - - - - [3] I; PU I/O P4[19] — General purpose digital input/output pin.
I/O EMC_A[19] — External memory address line 19.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 45 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P4[20] 109 R17 - - - - - [3] I; PU I/O P4[20] — General purpose digital input/output pin.
I/O EMC_A[20] — External memory address line 20.
I/O I2C2_SDA — I2C2 data input/output (this pin does not use
a specialized I2C pad).
I/O SSP1_SCK — Serial Clock for SSP1.
P4[21] 115 M15 - - - - - [3] I; PU I/O P4[21] — General purpose digital input/output pin.
I/O EMC_A[21] — External memory address line 21.
I/O I2C2_SCL — I2C2 clock input/output (this pin does not
use a specialized I2C pad).
I/O SSP1_SSEL — Slave Select for SSP1.
P4[22] 123 K14 - - - - - [3] I; PU I/O P4[22] — General purpose digital input/output pin.
I/O EMC_A[22] — External memory address line 22.
O U2_TXD — Transmitter output for UART2.
I/O SSP1_MISO — Master In Slave Out for SSP1.
P4[23] 129 J15 - - - - - [3] I; PU I/O P4[23] — General purpose digital input/output pin.
I/O EMC_A[23] — External memory address line 23.
I U2_RXD — Receiver input for UART2.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
P4[24] 183 B8 C8 127 - - - [3] I; PU I/O P4[24] — General purpose digital input/output pin.
O EMC_OE — LOW active Output Enable signal.
P4[25] 179 B9 D9 124 - - - [3] I; PU I/O P4[25] — General purpose digital input/output pin.
O EMC_WE — LOW active Write Enable signal.
P4[26] 119 L15 K13 - - - - [3] I; PU I/O P4[26] — General purpose digital input/output pin.
O EMC_BLS0 — LOW active Byte Lane select signal 0.
P4[27] 139 G15 F14 - - - - [3] I; PU I/O P4[27] — General purpose digital input/output pin.
O EMC_BLS1 — LOW active Byte Lane select signal 1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 46 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P4[28] 170 C11 D10 118 82 65 B7 [3] I; PU I/O P4[28] — General purpose digital input/output pin.
O EMC_BLS2 — LOW active Byte Lane select signal 2.
O U3_TXD — Transmitter output for UART3.
O T2_MAT0 — Match output for Timer 2, channel 0.
- R — Function reserved.
O LCD_VD[6] — LCD data.
O LCD_VD[10] — LCD data.
O LCD_VD[2] — LCD data.
P4[29] 176 B10 B9 122 85 68 A6 [3] I; PU I/O P4[29] — General purpose digital input/output pin.
O EMC_BLS3 — LOW active Byte Lane select signal 3.
I U3_RXD — Receiver input for UART3.
O T2_MAT1 — Match output for Timer 2, channel 1.
I/O I2C2_SCL — I2C2 clock input/output (this pin does not
use a specialized I2C pad).
O LCD_VD[7] — LCD data.
O LCD_VD[11] — LCD data.
O LCD_VD[3] — LCD data.
P4[30] 187 B7 C7 130 - - - [3] I; PU I/O P4[30] — General purpose digital input/output pin.
O EMC_CS0 — LOW active Chip Select 0 signal.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O CMP0_OUT — Comparator 0, output.
P4[31] 193 A4 E7 134 - - - [3] I; PU I/O P4[31] — General purpose digital input/output pin.
O EMC_CS1 — LOW active Chip Select 1 signal.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 47 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P5[0] to P5[4] I/O Port 5: Port 5 is a 5-bit I/O port with individual direction
controls for each bit. The operation of port 5 pins depends
upon the pin function selected via the pin connect block.
P5[0] 9 F4 E5 6 - - - [3] I; PU I/O P5[0] — General purpose digital input/output pin.
I/O EMC_A[24] — External memory address line 24.
I/O SSP2_MOSI — Master Out Slave In for SSP2.
O T2_MAT2 — Match output for Timer 2, channel 2.
P5[1] 30 J4 H1 21 - - G1 [3] I; PU I/O P5[1] — General purpose digital input/output pin.
I/O EMC_A[25] — External memory address line 25.
I/O SSP2_MISO — Master In Slave Out for SSP2.
O T2_MAT3 — Match output for Timer 2, channel 3.
P5[2] 117 L14 L12 81 - - - [11] I I/O P5[2] — General purpose digital input/output pin.
- R — Function reserved.
I/O SSP2_SCK — Serial clock for SSP2. When using this pin,
the SSP2 bit rate is limited to 1 MHz.
O T3_MAT2 — Match output for Timer 3, channel 2.
- R — Function reserved.
I/O I2C0_SDA — I2C0 data input/output (this pin uses a
specialized I2C pad that supports I2C Fast Mode Plus).
P5[3] 141 G14 G10 98 - - - [11] I I/O P5[3] — General purpose digital input/output pin.
- R — Function reserved.
I/O SSP2_SSEL — Slave select for SSP2. When using this
pin, the SSP2 bit rate is limited to 1 MHz.
- R — Function reserved.
I U4_RXD — Receiver input for USART4.
I/O I2C0_SCL — I2C0 clock input/output (this pin uses a
specialized I2C pad that supports I2C Fast Mode Plus.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 48 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
P5[4] 206 C3 C4 143 100 - - [3] I; PU I/O P5[4] — General purpose digital input/output pin.
O U0_OE — RS-485/EIA-485 output enable signal for
UART0.
- R — Function reserved.
O T3_MAT3 — Match output for Timer 3, channel 3.
O U4_TXD — Transmitter output for USART4 (input/output
in smart card mode).
JTAG_TDO (SWO) 2 D3 B1 1 1 1 B2 [3] O Test Data Out for JTAG interface. Also used as Serial wire
trace output.
JTAG_TDI 4 C2 C3 3 2 2 B1 [3] I Test Data In for JTAG interface.
JTAG_TMS
(SWDIO)
6 E3 C2 4 3 3 C2 [3] I Test Mode Select for JTAG interface. Also used as Serial
wire debug data input/output.
JTAG_TRST 8 D1 D4 5 4 4 C1 [3] I Test Reset for JTAG interface.
JTAG_TCK
(SWDCLK)
10 E2 D2 7 5 5 D3 [3] I Test Clock for JTAG interface. This clock must be slower
than 1 /6 of the CPU clock (CCLK) for the JTAG interface
to operate. Also used as serial wire clock.
RESET 35 M2 J1 24 17 14 G3 [12] I External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
This pin also serves as the debug select input. LOW level
selects the JTAG boundary scan. HIGH level selects the
ARM SWD debug mode.
RSTOUT 29 K3 H2 20 14 11 F1 [3] O Reset status output. A LOW output on this pin indicates
that the device is in the reset state for any reason. This
reflects the RESET input pin and all internal reset sources.
RTC_ALARM 37 N1 H5 26 - - - [13] O RTC controlled output. This is a 1.8 V pin. It goes HIGH
when a RTC alarm is generated.
RTCX1 34 K2 J2 23 16 13 F2 [14]
[15]
I Input to the RTC 32 kHz ultra-low power oscillator circuit.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 49 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
RTCX2 36 L2 J3 25 18 15 G2 [14]
[15]
O Output from the RTC 32 kHz ultra-low power oscillator
circuit.
USB_D2 52 U1 N2 37 - - - [9] I/O USB port 2 bidirectional D line.
VBAT 38 M3 K1 27 19 16 H1 I RTC power supply: 3.3 V on this pin supplies power to the
RTC.
VDD(REG)(3V3) 26,
86,
174
H4,
P11,
D11
G1,
N9, E9
18,
60,
121
13, 42,
84
34, 67 K7, C7 S 3.3 V regulator supply voltage: This is the power supply for
the on-chip voltage regulator that supplies internal logic.
VDDA 20 G4 F2 14 10 8 E3 S Analog 3.3 V pad supply voltage: This can be connected to
the same supply as VDD(3V3) but should be isolated to
minimize noise and error. This voltage is used to power the
ADC and DAC. Tie this pin to 3.3 V if the ADC and DAC
are not used.
VDD(3V3) 15,
60,
71,
89,
112,
125,
146,
165,
181,
198
G3,
P6,
P8,
U13,
P17,
K16,
C17,
B13,
C9, D7
E2,
L4,
K8,
L11,
J14,
E12,
E10,
C5
41,
62,
77,
102,
114,
138
28, 54,
71, 96
21, 42,
56, 77
K2,
H7,
D8,
C4
S 3.3 V supply voltage: This is the power supply voltage for
I/O other than pins in the VBAT domain.
VREFP 24 K1 G2 17 12 10 E1 S ADC positive reference voltage: This should be the same
voltage as VDDA, but should be isolated to minimize noise
and error. The voltage level on this pin is used as a
reference for ADC and DAC. Tie this pin to 3.3 V if the
ADC and DAC are not used.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 50 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground
or power to minimize power consumption.
[2] I = Input; O = Output; G = Ground; S = Supply.
[3] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. This pad can
be powered by VBAT.
[5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled.
[6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis.
[7] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.
[8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this
pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
VSS 33,
63,
77,
93,
114,
133,
148,
169,
189,
200
L3, T5,
R9,
P12,
N16,
H14,
E15,
A12,
B6, A2
H4,
P4,
L9,
L13,
G13,
D13,
C11,
B4
44,
65,
79,
103,
117,
139
31, 55,
72, 97
24, 43,
57, 78
H4,
G8,
G9,
B3
G Ground: 0 V reference for digital IO pins.
VSSREG 32,
84,
172
D12,
K4,
P10
H3,
L8,
A10
22,
59,
119
15, 41,
83
33, 66 J7, F3 G Ground: 0 V reference for internal logic.
VSSA 22 J2 F3 15 11 9 E2 G Analog ground: 0 V power supply and reference for the
ADC and DAC. This should be the same voltage as VSS,
but should be isolated to minimize noise and error.
XTAL1 44 M4 L2 31 22 19 J1 [14]
[16]
I Input to the oscillator circuit and internal clock generator
circuits.
XTAL2 46 N4 K4 33 23 20 K1 [14]
[16]
O Output from the oscillator amplifier.
DNC - - - - - 12 - Do not connect.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Pin LQFP100
Pin LQFP80
Pin TFBGA80
Reset state[1]
Type[2]
Description
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Product data sheet Rev. 3 — 1 May 2014 51 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
[10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this
pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
[12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[13] This pad can be powered from VBAT.
[14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be used to drive the RTCX1 pin.
[15] If the RTC is not used, these pins can be left floating.
[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to
noise). XTAL2 should be left floating.
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 52 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses are faster than the system bus and
are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for
instruction fetch (I-code) and one bus for data access (D-code). The use of two core
buses allows for simultaneous operations if concurrent operations target different devices.
The LPC408x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
7.2 ARM Cortex-M4 processor
The ARM Cortex-M4 processor is running at frequencies of up to 120 MHz. The processor
executes the Thumb-2 instruction set for optimal performance and code size, including
hardware division, single-cycle multiply, and bit-field manipulation. A Memory Protection
Unit (MPU) supporting eight regions is included.
7.3 ARM Cortex-M4 Floating Point Unit (FPU)
Remark: The FPU is available on parts LP4088/78/76.
The FPU supports single-precision floating-point computation functionality in compliance
with the ANSI/IEEE Standard 754-2008. The FPU provides add, subtract, multiply, divide,
multiply and accumulate, and square root operations. It also performs a variety of
conversions between fixed-point, floating-point, and integer data formats.
7.4 On-chip flash program memory
The LPC408x/7x contain up to 512 kB of on-chip flash program memory. A new two-port
flash accelerator maximizes performance for use with the two fast AHB-Lite buses.
7.5 EEPROM
The LPC408x/7x contains up to 4032 byte of on-chip byte-erasable and
byte-programmable EEPROM data memory.
7.6 On-chip SRAM
The LPC408x/7x contain a total of up to 96 kB on-chip SRAM data memory. This includes
64 kB main SRAM, accessible by the CPU and DMA controller on a higher-speed bus,
and up to two additional 16 kB peripheral SRAM blocks situated on a separate slave port
on the AHB multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
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Product data sheet Rev. 3 — 1 May 2014 53 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
7.7 Memory Protection Unit (MPU)
The LPC408x/7x have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.8 Memory map
Table 4. LPC408x/7x memory usage and details
Address range General Use Address range details and description
0x0000 0000 to
0x1FFF FFFF
On-chip non-volatile
memory
0x0000 0000 to 0x0007 FFFF For devices with 512 kB of flash memory.
0x0000 0000 to 0x0003 FFFF For devices with 256 kB of flash memory.
0x0000 0000 to 0x0001 FFFF For devices with 128 kB of flash memory.
0x0000 0000 to 0x0000 FFFF For devices with 64 kB of flash memory.
On-chip SRAM 0x1000 0000 to 0x1000 FFFF For devices with 64 kB of main SRAM.
0x1000 0000 to 0x1000 7FFF For devices with 32 kB of main SRAM.
0x1000 0000 to 0x1000 3FFF For devices with 16 kB of main SRAM.
Boot ROM 0x1FFF 0000 to 0x1FFF 1FFF 8 kB Boot ROM with flash services.
0x2000 0000 to
0x3FFF FFFF
On-chip SRAM
(typically used for
peripheral data)
0x2000 0000 to 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB)
0x2000 2000 to 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB)
0x2000 4000 to 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB)
AHB peripherals 0x2008 0000 to 0x200B FFFF See Figure 9 for details
0x4000 0000 to
0x7FFF FFFF
APB Peripherals 0x4000 0000 to 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x4008 0000 to 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x8000 0000 to
0xDFFF FFFF
Off-chip Memory via
the External Memory
Controller
Four static memory chip selects:
0x8000 0000 to 0x83FF FFFF Static memory chip select 0 (up to 64 MB)
0x9000 0000 to 0x93FF FFFF Static memory chip select 1 (up to 64 MB)
0x9800 0000 to 0x9BFF FFFF Static memory chip select 2 (up to 64 MB)
0x9C00 0000 to 0x9FFF FFFF Static memory chip select 3 (up to 64 MB)
Four dynamic memory chip selects:
0xA000 0000 to 0xAFFF FFFF Dynamic memory chip select 0 (up to 256 MB)
0xB000 0000 to 0xBFFF FFFF Dynamic memory chip select 1 (up to 256 MB)
0xC000 0000 to 0xCFFF FFFF Dynamic memory chip select 2 (up to 256 MB)
0xD000 0000 to 0xDFFF FFFF Dynamic memory chip select 3 (up to 256 MB)
0xE000 0000 to
0xE00F FFFF
Cortex-M4 Private
Peripheral Bus
0xE000 0000 to 0xE00F FFFF Cortex-M4 related functions, includes the NVIC
and System Tick Timer.
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Product data sheet Rev. 3 — 1 May 2014 54 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
The LPC408x/7x incorporate several distinct memory regions, shown in the following
figures. Figure 9 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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Product data sheet Rev. 3 — 1 May 2014 55 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
(1) Not available on all parts. See Table 2 and Table 4.
Fig 9. LPC408x/7x memory map
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4002 C000
0x4003 4000
0x4003 0000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 C000
0x4006 0000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
APB1 peripherals
0x4008 0000
0x4008 8000
0x4008 C000
0x4009 0000
0x4009 4000
0x4009 8000
0x4009 C000
0x400A 0000
0x400A 4000
0x400A 8000
0x400A C000
0x400B 0000
0x400B 4000
0x400B 8000
0x400B C000
0x400C 0000
0x400F C000
0x4010 0000
SSP0
DAC
timer 2
timer 3
UART2
UART3
USART4(1)
I2C2
1 - 0 reserved
2
3
4
5
6
7
8
9
10
SSP2
I2S
11
12
reserved
motor control PWM
reserved
30 - 17 reserved
13
14
15
16
31 system control
reserved
EMC 4 x static chip select(1)
EMC 4 x dynamic chip select(1)
reserved
private peripheral bus
0 GB
0.5 GB
4 GB
1 GB
0x1FFF 0000
0x2000 0000
0x2000 8000
0x2008 0000
0x2200 0000
0x200A 0000
0x2400 0000
0x2800 0000
0x4000 0000
0x4008 0000
0x4010 0000
0x4200 0000
0x4400 0000
0x8000 0000
0xA000 0000
0xE000 0000
0xE010 0000
0xFFFF FFFF
reserved
reserved
reserved
SPIFI data
reserved
reserved
APB0 peripherals
0xE004 0000
AHB peripherals
APB1 peripherals
peripheral SRAM bit-band
alias addressing
peripheral bit-band alias addressing
0x2000 4000
0x2000 2000
LPC408x/7x
QEI(1)
SD/MMC(1)
APB0 peripherals
WWDT
timer 0
timer 1
UART0
UART1
reserved
reserved
CAN AF RAM
CAN common
CAN1
CAN2
CAN AF registers
PWM0
I2C0
RTC/event recorder
+ backup registers
GPIO interrupts
pin connect
SSP1
ADC
22 - 19 reserved
I2C1
31 - 24 reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
PWM1
8 kB boot ROM
0x0000 0000
0x0000 0400
active interrupt vectors
+ 256 words
I-code/D-code
memory space
002aag736
reserved 0x1FFF 2000
0x2900 0000
reserved
reserved
0x2008 0000
0x2008 4000
0x2008 8000
0x2008 C000
0x200A 0000
0x2009 C000
AHB peripherals
LCD(1)
USB(1)
Ethernet(1)
0 GPDMA controller
1
2
3
CRC engine 0x2009 0000 4
0x2009 4000
5
GPIO 0x2009 8000
EMC registers
6
7
0x0000 0000
0x0001 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x1000 0000
0x1000 4000
0x1000 8000
0x1001 0000
64 kB on- chip flash (LPC4072)
128 kB on- chip flash (LPC4074)
256 kB on-chip flash (LPC4076)
512 kB on-chip flash (LPC4078)
reserved
16 kB main SRAM (LPC4072)
32 kB main SRAM (LPC4074)
64 kB main SRAM (LPC4088/78/76)
16 kB peripheral SRAM1 (LPC4088/78)
8 kB peripheral SRAM0 (LPC4074/72)
16 kB peripheral SRAM0 (LPC4088/78/76)
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Product data sheet Rev. 3 — 1 May 2014 56 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
7.9 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.9.1 Features
• Controls system exceptions and peripheral interrupts.
• On the LPC408x/7x, the NVIC supports 40 vectored interrupts.
• 32 programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.9.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on port 0 and port 2 regardless of the selected function can be programmed to
generate an interrupt on a rising edge, a falling edge, or both.
7.10 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupts being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
7.11 External Memory Controller (EMC)
Remark: The EMC is available for parts LPC4088/78/76. Supported memory size and
type and EMC bus width vary for different packages (see Table 2). The EMC pin
configuration for each part is shown in Table 5.
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Product data sheet Rev. 3 — 1 May 2014 57 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
The LPC408x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral
offering support for asynchronous static memory devices such as RAM, ROM, and flash.
In addition, it can be used as an interface with off-chip memory-mapped devices and
peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
7.11.1 Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16/32 data and 16/20/26 address lines wide static memory support.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
Table 5. External memory controller pin configuration
Parts Data bus pins Address bus
pins
Control pins
SRAM SDRAM
LPC4088FBD208
LPC4088FET208
LPC4078FBD208
LPC4078FET208
EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC4088FET180
LPC4078FET180
LPC4076FET180
EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0],
EMC_CS[1:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[1:0],
EMC_CLK[1:0], EMC_CKE[1:0],
EMC_DQM[1:0]
LPC4088FBD144
LPC4078FBD144
LPC4076FBD144
EMC_D[7:0] EMC_A[15:0] EMC_BLS[3:2],
EMC_CS[1:0],
EMC_OE, EMC_WE
not available
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Product data sheet Rev. 3 — 1 May 2014 58 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
7.12 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the
I2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be
triggered by selected timer match conditions. Memory-to-memory transfers and transfers
to or from GPIO are supported.
7.12.1 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.13 CRC engine
The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
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7.13.1 Features
• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
• Programmable seed number setting.
• Supports CPU PIO or DMA back-to-back transfer.
• Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation
– 16-bit write: 2-cycle operation (8-bit x 2-cycle)
– 32-bit write: 4-cycle operation (8-bit x 4-cycle)
7.14 LCD controller
Remark: The LCD controller is available on parts LPC4088.
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
7.14.1 Features
• AHB master interface to access frame buffer.
• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320 200, 320 240,
640 200, 640 240, 640 480, 800 600, and 1024 768.
• Hardware cursor support for single-panel displays.
• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
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• 16 bpp true-color non-palettized, for color STN and TFT.
• 24 bpp true-color non-palettized, for color TFT.
• Programmable timing for different display panels.
• 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM.
• Frame, line, and pixel clock signals.
• AC bias signal for STN, data enable signal for TFT panels.
• Supports little and big-endian, and Windows CE data formats.
• LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
7.15 Ethernet
Remark: The Ethernet block is available on parts LPC4088/78/76.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M4 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
7.15.1 Features
• Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
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– Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
7.16 USB interface
Remark: The USB Device/Host/OTG controller is available on parts LPC4088/78/76. The
USB Device-only controller is available on part LPC4074/72.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
See Section 13.1 for details on typical USB interfacing solutions.
7.16.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.16.1.1 Features
• Fully compliant with USB 2.0 Specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, the LPC408x/7x can enter one of the reduced
power modes and wake up on USB activity.
• Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.
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• Allows dynamic switching between CPU-controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.16.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the Open Host Controller Interface (OHCI) specification.
7.16.2.1 Features
• OHCI compliant
• Two downstream ports
• Supports per-port power switching
7.16.3 USB OTG controller
USB OTG is a supplement to the USB 2.0 Specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only I2C
interface to implement OTG dual-role device functionality. The dedicated I2C interface
controls an external OTG transceiver.
7.16.3.1 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.17 SD/MMC card interface
Remark: The SD/MMC card interface is available on parts LPC4088/78/76.
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
7.17.1 Features
• The MCI provides all functions specific to the SD/MMC memory card. These include
the clock generation unit, power management control, and command and data
transfer.
• Conforms to Multimedia Card Specification v2.11.
• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
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• Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
• DMA supported through the GPDMA controller.
7.18 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC408x/7x use accelerated GPIO functions:
• GPIO registers are accessed through the AHB multilayer bus so that the fastest
possible I/O timing can be achieved.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.
• Support for Cortex-M4 bit banding.
• Support for use with the GPDMA controller.
Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed
to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is
asynchronous, so it may operate when clocks are not present such as during Power-down
mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.
7.18.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
7.19 12-bit ADC
The LPC408x/7x contain one ADC. It is a single 12-bit successive approximation ADC
with eight channels and DMA support.
7.19.1 Features
• 12-bit successive approximation ADC.
• Input multiplexing among eight pins.
• Power-down mode.
• Measurement range VSS to VREFP.
• 12-bit conversion rate: up to 400 kHz.
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• Individual channels can be selected for conversion.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or Timer Match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
• DMA support.
7.20 10-bit DAC
The LPC408x/7x contain one DAC. The DAC allows to generate a variable analog output.
The maximum output value of the DAC is VREFP.
7.20.1 Features
• 10-bit DAC
• Resistor string architecture
• Buffered output
• Power-down mode
• Selectable output drive
• Dedicated conversion timer
• DMA support
7.21 Comparator
Remark: The comparator is available on parts LPC4088/7876.
Two embedded comparators are available to compare the voltage levels on external pins
or against internal voltages. Up to four voltages on external pins and several internal
reference voltages are selectable on each comparator. Additionally, two of the external
inputs can be selected to drive an input common on both comparators.
7.21.1 Features
• Up to five selectable external sources per comparator; fully configurable on either
positive or negative comparator input channels.
• 0.9 V internal band gap reference voltage selectable as either positive or negative
input on each comparator.
• 32-stage voltage ladder internal reference for selectable voltages on each
comparator; configurable on either positive or negative comparator input.
• Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog
voltage supply.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Relaxation oscillator circuitry output, for a 555 style timer operation.
• Individual comparator outputs can be connected to I/O pins.
• Separate interrupt for each comparator.
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• Edge and level comparator outputs connect to two timers allowing edge counting
while a level match has been asserted or measuring the time between two voltage trip
points.
7.22 UART0/1/2/3 and USART4
Remark: UART0/1/2/3 are available on all parts. USART4 is available on parts
LPC4088/78/76.
The LPC408x/7x contain five UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.22.1 Features
• Maximum UART data bit rate of 7.5 MBit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto-baud capability.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing.
• All UARTs have DMA support for both transmit and receive.
• UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
• USART4 includes an IrDA mode to support infrared communication.
• USART4 supports synchronous mode and a smart card mode conforming to
ISO7816-3.
7.23 SPIFI
The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM
Cortex-M4 processor with little performance penalty compared to parallel flash devices
with higher pin count.
The entire flash content is accessible as normal memory using byte, halfword, and word
accesses by the processor and/or DMA channels.
SPIFI provides sufficient flexibility to be compatible with common flash devices and
includes extensions to help insure compatibility with future devices.
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7.23.1 Features
• Quad SPI Flash Interface (SPIFI) interface to external flash.
• Transfer rates of up to SPIFI_CLK/2 bytes per second.
• Code in the serial flash memory can be executed as if it was in the CPU’s internal
memory space. This is accomplished by mapping the external flash memory directly
into the CPU memory space.
• Supports 1-, 2-, and 4-bit bidirectional serial protocols.
• Half-duplex protocol compatible with various vendors and devices.
• Supported by a driver library available from NXP Semiconductors.
7.24 SSP serial I/O controller
The LPC408x/7x contain three SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.24.1 Features
• Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• DMA transfers supported by GPDMA
7.25 I2C-bus serial I/O controllers
The LPC408x/7x contain three I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.25.1 Features
• All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s
(Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of
up to 400 kbit/s.
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• The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0
using pins P5[2] and P5[3].
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• Both I2C-bus controllers support multiple address recognition and a bus monitor
mode.
7.26 I2S-bus serial I/O controllers
The LPC408x/7x contain one I2S-bus interface. The I2S-bus provides a standard
communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S connection has one master, which is always the
master, and one slave. The I2S interface on the LPC408x/7x provides a separate transmit
and receive channel, each of which can operate as either a master or a slave.
7.26.1 Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
• Configurable word select period in master mode (separately for I2S input and output).
• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S input and I2S output.
7.27 CAN controller and acceptance filters
The LPC408x/7x contain one CAN controller with two channels.
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The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.27.1 Features
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
• FullCAN messages can generate interrupts.
7.28 General purpose 32-bit timers/external event counters
The LPC408x/7x include four 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.28.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
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– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
7.29 Pulse Width Modulator (PWM)
The LPC408x/7x contain two standard PWMs.
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC408x/7x. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
7.29.1 Features
• LPC408x/7x has two PWM blocks with Counter or Timer operation (may use the
peripheral clock or one of the capture inputs as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
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• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler
if the PWM mode is not enabled.
7.30 Motor control PWM
The LPC408x/7x contain one motor control PWM.
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input is also provided that causes the
PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
The maximum PWM speed is determined by the PWM resolution (n) and the operating
frequency f: PWM speed = f/2n (see Table 6).
7.31 Quadrature Encoder Interface (QEI)
Remark: The QEI is available on parts LPC4088/78/76.
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
7.31.1 Features
• Tracks encoder position.
Table 6. PWM speed at operating frequency 120 MHz
PWM resolution PWM speed
6 bit 1.875 MHz
8 bit 0.468 MHz
10 bit 0.117 MHz
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32-bit ARM Cortex-M4 microcontroller
• Increments/decrements depending on direction.
• Programmable for 2 or 4 position counting.
• Velocity capture using built-in timer.
• Velocity compare function with “less than” interrupt.
• Uses 32-bit registers for position and velocity.
• Three position compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
• Connected to APB.
7.32 ARM Cortex-M4 system tick timer
The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval. In the LPC408x/7x, this timer can be
clocked from the internal AHB clock or from a device pin.
7.33 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.33.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is
always running if the watchdog timer is enabled.
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32-bit ARM Cortex-M4 microcontroller
7.34 RTC and backup registers
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. The RTC on the LPC408x/7x is designed to have extremely low power
consumption, i.e. less than 1 A. The RTC will typically run from the main chip power
supply conserving battery power while the rest of the device is powered up. When
operating from a battery, the RTC will continue working down to 2.1 V. Battery power can
be provided from a standard 3 V lithium button cell.
An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion
of the RTC, moving most of the power consumption out of the time counting function.
The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way
that will provide less than 1 second per day error when operated at a constant voltage and
temperature.
The RTC contains a small set of backup registers (20 bytes) for holding data while the
main part of the LPC408x/7x is powered off.
The RTC includes an alarm function that can wake up the LPC408x/7x from all reduced
power modes with a time resolution of 1 s.
7.34.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
• Periodic interrupts can be generated from increments of any field of the time registers.
• Backup registers (20 bytes) powered by VBAT.
• RTC power supply is isolated from the rest of the chip.
7.35 Event monitor/recorder
The event monitor/recorder allows recording of tampering events in sealed product
enclosures. Sensors report any attempt to open the enclosure, or to tamper with the
device in any other way. The event monitor/recorder stores records of such events when
the device is powered only by the backup battery.
7.35.1 Features
• Supports three digital event inputs in the VBAT power domain.
• An event is defined as a level change at the digital event inputs.
• For each event channel, two timestamps mark the first and the last occurrence of an
event. Each channel also has a dedicated counter tracking the total number of events.
Timestamp values are taken from the RTC.
• Runs in VBAT power domain, independent of system power supply. The
event/recorder/monitor can therefore operate in Deep power-down mode.
• Very low power consumption.
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32-bit ARM Cortex-M4 microcontroller
• Interrupt available if system is running.
• A qualified event can be used as a wake-up trigger.
• State of event interrupts accessible by software through GPIO.
7.36 Clocking and power control
7.36.1 Crystal oscillators
The LPC408x/7x include four independent oscillators. These are the main oscillator, the
IRC oscillator, the watchdog oscillator, and the RTC oscillator.
Following reset, the LPC408x/7x will operate from the Internal RC oscillator until switched
by software. This allows systems to operate without any external crystal and the boot
loader code to operate at a known frequency.
See Figure 10 for an overview of the LPC408x/7x clock generation.
Fig 10. LPC408x/7x clock generation block diagram
MAIN PLL0
IRC oscillator
main oscillator
(osc_clk)
CLKSRCSEL
(system clock select)
sysclk
pll_clk
CCLKSEL
(CPU clock select)
002aag737
pll_clk
ALT PLL1
CPU CLOCK
DIVIDER
alt_pll_clk
cclk
PERIPHERAL
CLOCK DIVIDER
pclk
EMC
CLOCK DIVIDER
emc_clk
sysclk
alt_pll_clk
pll_clk
USBCLKSEL
(USB clock select)
USB
CLOCK DIVIDER
usb_clk
sysclk
LPC408x/7x
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32-bit ARM Cortex-M4 microcontroller
7.36.1.1 Internal RC oscillator
The IRC may be used as the clock that drives the PLL and subsequently the CPU. The
nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire
voltage and temperature range.
Upon power-up or any chip reset, the LPC408x/7x use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.36.1.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator also provides the clock source for the alternate PLL1.
The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the main
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 7.36.2 for additional information.
7.36.1.3 RTC oscillator
The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can
be output on the CLKOUT pin in order to allow trimming the RTC oscillator without
interference from a probe.
7.36.1.4 Watchdog oscillator
The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the
Watchdog Timer that is always running if the Watchdog Timer is enabled. The Watchdog
oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency.
In order to allow Watchdog Timer operation with minimum power consumption, which can
be important in reduced power modes, the Watchdog oscillator frequency is not tightly
controlled. The Watchdog oscillator frequency will vary over temperature and power
supply within a particular part, and may vary by processing across different parts. This
variation should be taken into account when determining Watchdog reload values.
Within a particular part, temperature and power supply variations can produce up to a
17 % frequency variation. Frequency variation between devices under the same
operating conditions can be up to 30 %.
7.36.2 Main PLL (PLL0) and Alternate PLL (PLL1)
PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally
identical but have somewhat different input possibilities and output connections. These
possibilities are shown in Figure 10. The Main PLL can receive its input from either the
IRC or the main oscillator and can potentially be used to provide the clocks to nearly
everything on the device. The Alternate PLL receives its input only from the main oscillator
and is intended to be used as an alternate source of clocking to the USB. The USB has
timing needs that may not always be filled by the Main PLL.
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Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the
USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB
clock through that route. The source for each clock must be selected via the CLKSEL
registers and can be further reduced by clock dividers as needed.
PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only
the Main PLL is used, then its output frequency must be an integer multiple of all other
clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring
an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled
Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional
dividers to bring the output down to the desired frequencies. The minimum output divider
value is 2, insuring that the output of the PLLs have a 50 % duty cycle.
If the USB is used, the possibilities for the CPU clock and other clocks will be limited by
the requirements that the frequency be precise and very low jitter, and that the PLL0
output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the
operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in
conjunction with the PLL can meet the precision and jitter specifications for USB. It is due
to these limitations that the Alternate PLL is provided.
The alternate PLL accepts an input clock frequency from the main oscillator in the range
of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied
up to a multiple of 48 MHz (192 MHz or 288 MHz as described above).
7.36.3 Wake-up timer
The LPC408x/7x begin operation at power-up and when awakened from Power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up Timer.
The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code
execution. When power is applied to the chip, or when some event caused the chip to exit
Power-down mode, some time is required for the oscillator to produce a signal of sufficient
amplitude to drive the clock logic. The amount of time depends on many factors, including
the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical
characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g.,
capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
7.36.4 Power control
The LPC408x/7x support a variety of power control features. There are four special
modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode,
and Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
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32-bit ARM Cortex-M4 microcontroller
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, the peripheral power control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all
dynamic power use in any peripherals that are not required for the application. Each of the
peripherals has its own clock divider which provides even better power control.
The integrated PMU (Power Management Unit) automatically adjusts internal regulators
to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep
power-down modes.
The LPC408x/7x also implement a separate power domain to allow turning off power to
the bulk of the device while maintaining operation of the RTC and a small set of registers
for storing data during any of the power-down modes.
7.36.4.1 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence other than re-enabling the clock to the ARM
core.
In Sleep mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
The DMA controller can continue to work in Sleep mode and has access to the peripheral
RAMs and all peripheral registers. The flash memory and the main SRAM are not
available in Sleep mode, they are disabled in order to save power.
Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.
7.36.4.2 Deep-sleep mode
In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.
The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up.
The RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The clock divider
registers are automatically reset to zero.
The Deep-sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power
consumption to a very low value. Power to the flash memory is left on in Deep-sleep
mode, allowing a very quick wake-up.
Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input
pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled.
Wake-up will occur whenever any enabled interrupt occurs.
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On wake-up from Deep-sleep mode, the code execution and peripherals activities will
resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If
the main external oscillator was used, the code execution will resume when 4096 cycles
expire. PLL and clock dividers need to be reconfigured accordingly.
7.36.4.3 Power-down mode
Power-down mode does everything that Deep-sleep mode does but also turns off the
power to the IRC oscillator and the flash memory. This saves more power but requires
waiting for resumption of flash operation before execution of code or data access in the
flash memory can be accomplished.
When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are
stopped. The RTC remains running if it has been enabled and RTC interrupts may be
used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are
automatically turned off and the clock selection multiplexers are set to use the system
clock sysclk (the reset state). The clock divider control registers are automatically reset to
zero. If the Watchdog timer is running, it will continue running in Power-down mode.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 s to start-up. After this four IRC cycles will expire before the
code execution can then be resumed if the code was running from SRAM. In the
meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the
100 s flash start-up time. When it times out, access to the flash will be allowed. Users
need to reconfigure the PLL and clock dividers accordingly.
7.36.4.4 Deep power-down mode
The Deep power-down mode can only be entered from the RTC block. In Deep
power-down mode, power is shut off to the entire chip with the exception of the RTC
module and the RESET pin.
To optimize power conservation, the user has the additional option of turning off or
retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn
off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the
VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before
device operation can be restarted.
The LPC408x/7x can wake up from Deep power-down mode via the RESET pin or an
alarm match event of the RTC.
7.36.4.5 Wake-up Interrupt Controller (WIC)
The WIC allows the CPU to automatically wake up from any enabled priority interrupt that
can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep
power-down modes.
The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When
the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC sends a
mask of the current interrupt situation to the WIC. This mask includes all of the interrupts
that are both enabled and of sufficient priority to be serviced immediately. With this
information, the WIC simply notices when one of the interrupts has occurred and then it
wakes up the CPU.
The WIC eliminates the need to periodically wake up the CPU and poll the interrupts
resulting in additional power savings.
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7.36.5 Peripheral power control
A power control for peripherals feature allows individual peripherals to be turned off if they
are not needed in the application, resulting in additional power savings.
7.36.6 Power domains
The LPC408x/7x provide two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the backup
registers.
On the LPC408x/7x, I/O pads are powered by VDD(3V3), while VDD(REG)(3V3) powers the
on-chip voltage regulator which in turn provides power to the CPU and most of the
peripherals.
Depending on the LPC408x/7x application, a design can use two power options to
manage power consumption.
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly” while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. There is no
power drain from the RTC battery when VDD(REG)(3V3) is available and VDD(REG)(3V3) >
VBAT.
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7.37 System control
7.37.1 Reset
Reset has four sources on the LPC408x/7x: the RESET pin, the Watchdog reset,
Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating
voltage attains a usable level, starts the Wake-up timer (see description in
Section 7.36.3), causing reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the flash controller
has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Fig 11. Power distribution
REAL-TIME CLOCK
BACKUP REGISTERS
REGULATOR
32 kHz
OSCILLATOR
POWER
SELECTOR
ULTRA-LOW
POWER
REGULATOR
RTC POWER DOMAIN
MAIN POWER DOMAIN
002aag738
RTCX1
VBAT
(typical 3.0 V)
VDD(REG)(3V3)
(typical 3.3 V)
RTCX2
VDD(3V3)
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
ADC POWER DOMAIN
VDDA
VREFP
VSSA
LPC408x/7x
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7.37.2 Brownout detection
The LPC408x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this
voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
The second stage of low-voltage detection asserts reset to inactivate the LPC408x/7x
when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V (typical). This reset prevents
alteration of the flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset down below
1 V, at which point the power-on reset circuitry maintains the overall reset.
Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event
loop to sense the condition.
7.37.3 Code security (Code Read Protection - CRP)
This feature of the LPC408x/7x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
7.37.4 APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus
bandwidth and thereby reducing stalls caused by contention between the CPU and the
GPDMA controller.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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7.37.5 AHB multilayer matrix
The LPC408x/7x use an AHB multilayer matrix. This matrix connects the instruction
(I-code) and data (D-code) CPU buses of the ARM Cortex-M4 to the flash memory, the
main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these
memories. Additionally, the matrix connects the CPU system bus and all of the DMA
controllers to the various peripheral functions.
7.37.6 External interrupt inputs
The LPC408x/7x include up to 30 edge sensitive interrupt inputs combined with one level
sensitive external interrupt input as selectable pin function. The external interrupt input
can optionally be used to wake up the processor from Power-down mode.
7.37.7 Memory mapping control
The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC408x/7x is configured for 128 total interrupts.
7.38 Debug control
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watch points.
8. Limiting values
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V
VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V
VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V
Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V
Vi(VREFP) input voltage on pin VREFP 0.5 +4.6 V
VIA analog input voltage on ADC related
pins
0.5 +5.1 V
VI input voltage 5 V tolerant digital
I/O pins;
VDD(3V3) 2.4V
[2] 0.5 +5.5 V
VDD(3V3) 0 V 0.5 +3.6 V
other I/O pins [2][3] 0.5 VDD(3V3) +
0.5
V
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
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32-bit ARM Cortex-M4 microcontroller
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Not to exceed 4.6 V.
[4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on the required shelf lifetime. Please refer to the JEDEC spec for further details.
[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Ilatch I/O latch-up current (0.5VDD(3V3)) < VI
< (1.5VDD(3V3));
Tj < 125 C
- 100 mA
Tstg storage temperature non-operating [4] 65 +150 C
Ptot(pack) total power dissipation (per package) based on package
heat transfer, not
device power
consumption
- 1.5 W
VESD electrostatic discharge voltage human body
model; all pins
[5]- 4000 V
Table 7. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
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9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
Tj = Tamb + PD Rthj – a
Table 8. Thermal characteristics
VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified;
Symbol Parameter Conditions Min Typ Max Unit
Tj(max) maximum junction
temperature
- - 125 C
Table 9. Thermal resistance (LQFP packages)
Tamb = 40 C to +85 C unless otherwise specified.
Thermal resistance value (C/W): ±15 %
LQFP80 LQFP144 LQFP208
ja
JEDEC (4.5 in 4 in)
0 m/s 41 31 27
1 m/s 35 28 25
2.5 m/s 32 26 24
Single-layer (4.5 in 3 in)
0 m/s 61 43 35
1 m/s 47 35 31
2.5 m/s 43 33 29
jc 7.8 9.2 10.5
jb 11.6 13.5 15.2
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Table 10. Thermal resistance value (TFBGA packages)
Tamb = 40 C to +85 C unless otherwise specified.
Thermal resistance value (C/W): ±15 %
TFBGA180 TFBGA208
ja
JEDEC (4.5 in 4 in)
0 m/s 47 43
1 m/s 39 37
2.5 m/s 35 33
8-layer (4.5 in 3 in)
0 m/s 39 37
1 m/s 35 33
2.5 m/s 31 30
jc 8.5 7.4
jb 13 16
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10. Static characteristics
Table 11. Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Supply pins
VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V
VDD(REG)(3V3) regulator supply voltage
(3.3 V)
2.4 3.3 3.6 V
VDDA analog 3.3 V pad supply
voltage
[3] 2.7 3.3 3.6 V
Vi(VBAT) input voltage on pin
VBAT
[4] 2.1 3.0 3.6 V
Vi(VREFP) input voltage on pin
VREFP
[3] 2.7 3.3 VDDA V
IDD(REG)(3V3) regulator supply current
(3.3 V)
active mode; code
while(1){}
executed from flash; all
peripherals disabled
PCLK = CCLK/4
CCLK = 12 MHz; PLL
disabled
[5][6]- 7.5 - mA
CCLK = 120 MHz; PLL
enabled
[5][7]- 56 - mA
active mode; code
while(1){}
executed from flash; all
peripherals enabled;
PCLK = CCLK/4
CCLK = 12 MHz; PLL
disabled
[5][6] 14 -
CCLK = 120 MHz; PLL
enabled
[5][7] 120 - mA
Sleep mode [5][8]- 5.5 - mA
Deep-sleep mode [5][9] - 550 1200 A
Power-down mode [5][9] - 280 600 A
IBAT battery supply current RTC running;
part powered down;
VDD(REG)(3V3) =0 V;
Vi(VBAT) = 3.0 V;
VDD(3V3) = 0 V.
[10] -
1 9 A
part powered;
VDD(REG)(3V3) = 3.3 V;
Vi(VBAT) = 3.0 V
[11] <10 nA
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Standard port pins, RESET
IIL LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
- 0.5 10 nA
IIH HIGH-level input
current
VI = VDD(3V3); on-chip
pull-down resistor
disabled
- 0.5 10 nA
VI input voltage pin configured to provide
a digital function
[15][16]
[17]
0 - 5.0 V
VO output voltage output active 0 - VDD(3V3) V
VIH HIGH-level input
voltage
0.7VDD(3V3)- - V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage
IOH = 4 mA VDD(3V3)
0.45
- - V
VOL LOW-level output
voltage
IOL = 4 mA - - 0.45 V
IOH HIGH-level output
current
VOH = VDD(3V3) 0.4 V 4 - - mA
IOL LOW-level output
current
VOL = 0.4 V 4 - - mA
IOHS HIGH-level short-circuit
output current
VOH = 0 V [18]- - 50 mA
IOLS LOW-level short-circuit
output current
VOL = VDD(3V3) [18]- - 60 mA
Ipd pull-down current VI = 5 V 10 50 150 A
Ipu pull-up current VI = 0 V 15 50 85 A
VDD(3V3) < VI < 5 V 0 0 0 A
I2C-bus pins (P0[27] and P0[28])
VIH HIGH-level input
voltage
0.7VDD(3V3)- - V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage - 0.05
VDD(3V3)
- V
VOL LOW-level output
voltage
IOLS = 3 mA - - 0.4 V
ILI input leakage current VI = VDD(3V3) [19]- 2 4 A
VI = 5 V - 10 22 A
USB pins
IOZ OFF-state output
current
0 V < VI < 3.3 V [20]- - 10 A
VBUS bus supply voltage [20]- - 5.25 V
VDI differential input
sensitivity voltage
(D+) (D) [20] 0.2 - - V
Table 11. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design.
[3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.
[4] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[5] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements.
[6] Boost control bits in the PBOOST register set to 0x0 (see LPC408x/7x User manual).
[7] Boost control bits in the PBOOST register set to 0x3 (see LPC408x/7x User manual).
[8] IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4.
[9] BOD disabled.
[10] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 0; Tamb = 25 C.
[11] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; Tamb = 25 C.
[12] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C.
[13] VDDA = 3.3 V; Tamb = 25 C.
[14] Vi(VREFP) = 3.3 V; Tamb = 25 C.
[15] Including voltage on outputs in 3-state mode.
[16] VDD(3V3) supply voltages must be present.
[17] 3-state outputs go into 3-state mode in Deep power-down mode.
[18] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[19] To VSS.
[20] 3.0 V VDD(3V3) 3.6 V.
VCM differential common
mode voltage range
includes VDI range [20] 0.8 - 2.5 V
Vth(rs)se single-ended receiver
switching threshold
voltage
[20] 0.8 - 2.0 V
VOL LOW-level output
voltage for
low-/full-speed
RL of 1.5 k to 3.6 V [20]- - 0.18 V
VOH HIGH-level output
voltage (driven) for
low-/full-speed
RL of 15 k to GND [20] 2.8 - 3.5 V
Ctrans transceiver capacitance pin to GND [20]- - 20 pF
Oscillator pins (see Section 13.2)
Vi(XTAL1) input voltage on pin
XTAL1
0.5 1.8 1.95 V
Vo(XTAL2) output voltage on pin
XTAL2
0.5 1.8 1.95 V
Vi(RTCX1) input voltage on pin
RTCX1
0.5 - 3.6 V
Vo(RTCX2) output voltage on pin
RTCX2
0.5 - 3.6 V
Table 11. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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10.1 Power consumption
Conditions: BOD disabled.
Fig 12. Deep-sleep mode: Typical regulator supply current IDD(REG)(3V3) versus
temperature
Conditions: BOD disabled.
Fig 13. Power-down mode: Typical regulator supply current IDD(REG)(3V3) versus
temperature
temperature (°C)
-40 -15 10 35 60 85
002aah051
0.7
1.1
1.5
0.3
VDD(REG)(3V3) = 3.6 V
3.3 V
3.0 V
2.4 V
IDD(REG)(3V3)
(mA)
temperature (°C)
-40 -15 10 35 60 85
002aah052
300
600
900
0
VDD(REG)(3V3) = 3.6 V
3.3 V
3.0 V
2.4 V
IDD(REG)(3V3)
(μA)
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Conditions: VDD(REG)(3V3) = VDDA = VDD(3V3) = 0; VBAT = 3.0 V.
Fig 14. Part powered off: Typical battery supply current (IBAT) versus temperature
002aah074
temperature (°C)
-40 -15 10 35 60 85
0.8
1.6
0.4
1.2
2.0
0
IBAT
(μA)
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10.2 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the PCONP register. All
other blocks are disabled and no code is executed. Measured on a typical sample at
Tamb = 25 C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz,
48 MHz, and 120 MHz.
The combined current of several peripherals running at the same time can be less than
the sum of each individual peripheral current measured separately.
Table 12. Power consumption for individual analog and digital blocks
Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4.
Peripheral Conditions Typical supply current in mA
12 MHz[1] 48 MHz[1] 120 MHz[2]
Timer0 0.01 0.06 0.15
Timer1 0.02 0.07 0.16
Timer2 0.02 0.07 0.17
Timer3 0.01 0.07 0.16
Timer0 + Timer1 + Timer2 + Timer3 0.07 0.28 0.67
UART0 0.05 0.19 0.45
UART1 0.06 0.24 0.56
UART2 0.05 0.2 0.47
UART3 0.06 0.23 0.56
USART4 0.07 0.27 0.66
UART0 + UART1 + UART2 + UART3 +
USART4
0.29 1.13 2.74
PWM0 + PWM1 0.08 0.31 0.75
Motor control PWM 0.04 0.15 0.36
I2C0 0.01 0.03 0.08
I2C1 0.01 0.03 0.1
I2C2 0.01 0.03 0.08
I2C0 + I2C1 + I2C2 0.02 0.1 0.26
SSP0 0.03 0.1 0.26
SSP1 0.02 0.11 0.27
DAC 0.3 0.31 0.33
ADC (12 MHz clock) 1.51 1.61 1.7
Comparator 0.01 0.03 0.06
CAN1 0.11 0.44 1.08
CAN2 0.1 0.4 0.98
CAN1 + CAN2 0.15 0.59 1.44
DMA PCLK = CCLK 1.1 4.27 10.27
QEI 0.02 0.11 0.28
GPIO 0.4 1.72 4.16
LCD 0.99 3.84 9.25
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32-bit ARM Cortex-M4 microcontroller
[1] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470).
[2] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470).
I2S 0.04 0.18 0.46
EMC 0.82 3.17 7.63
RTC 0.01 0.01 0.05
USB + PLL1 0.62 0.97 1.67
Ethernet PCENET bit set
to 1 in the
PCONP register
0.54 2.08 5.03
Table 12. Power consumption for individual analog and digital blocks …continued
Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4.
Peripheral Conditions Typical supply current in mA
12 MHz[1] 48 MHz[1] 120 MHz[2]
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10.3 Electrical pin characteristics
Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.
Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
IOH (mA)
0 8 16 24
002aaf112
2.8
2.4
3.2
3.6
VOH
(V)
2.0
T = 85 °C
25 °C
−40 °C
VOL (V)
0 0.2 0.4 0.6
002aaf111
5
10
15
IOL
(mA)
0
T = 85 °C
25 °C
−40 °C
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Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.
Fig 17. Typical pull-up current Ipu versus input voltage VI
Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.
Fig 18. Typical pull-down current Ipd versus input voltage VI
0 1 2 3 4 5
002aaf108
−30
−50
−10
10
Ipu
(μA)
−70
T = 85 °C
25 °C
−40 °C
VI (V)
002aaf109
VI (V)
0 1 2 3 4 5
10
70
50
30
90
Ipd
(μA)
−10
T = 85 °C
25 °C
−40 °C
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11. Dynamic characteristics
11.1 Flash memory
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash
in blocks of 256 bytes.
[1] EEPROM clock frequency = 375 kHz. Programming/erase times increase with decreasing EEPROM clock
frequency.
Table 13. Flash characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Nendu endurance [1] 10000 100000 - cycles
tret retention time powered 10 - - years
unpowered 20 - - years
ter erase time sector or multiple
consecutive sectors
95 100 105 ms
tprog programming
time
[2] 0.95 1 1.05 ms
Table 14. EEPROM characteristics
Tamb = 40 C to +85C; VDD(REG)(3V3) = 2.7 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
fclk clock frequency 200 375 400 kHz
Nendu endurance 100000 500000 - cycles
tret retention time powered 10 - - years
unpowered 10 - - years
ter erase time 64 bytes [1]- 1.8 - ms
tprog programming
time
64 bytes [1]- 1.1 - ms
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11.2 External memory interface
Table 15. Dynamic characteristics: Static external memory interface
CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter[1] Conditions[1] Min Typ Max Unit
Read cycle parameters[2]
tCSLAV CS LOW to address
valid time
RD1 3.3 4.3 6.1 ns
tCSLOEL CS LOW to OE
LOW time
RD2 [3] 2.4 + Tcy(clk)
WAITOEN
3.1 + Tcy(clk)
WAITOEN
4.2 + Tcy(clk)
WAITOEN
ns
tCSLBLSL CS LOW to BLS
LOW time
RD3; PB = 1 [3] 2.7 3.5 4.9 ns
tOELOEH OE LOW to OE
HIGH time
RD4 [3] (WAITRD
WAITOEN + 1)
Tcy(clk) 2.2
(WAITRD
WAITOEN + 1)
Tcy(clk) 2.8
(WAITRD
WAITOEN + 1)
Tcy(clk) 3.8
ns
tam memory access
time
RD5 [4][3] (WAITRD
WAITOEN + 1)
Tcy(clk) 9.6
(WAITRD
WAITOEN + 1)
Tcy(clk) 13.2
(WAITRD
WAITOEN + 1)
Tcy(clk) 20.2
ns
th(D) data input hold time RD6 [5][3] 5.0 7.2 10.7 ns
tCSHBLSH CS HIGH to BLS
HIGH time
PB = 1 2.7 3.4 4.9 ns
tCSHOEH CS HIGH to OE
HIGH time
[3] 2.4 3.1 4.2 ns
tOEHANV OE HIGH to address
invalid time
[3] 0.77 1.2 1.86 ns
tdeact deactivation time RD7 [3] 3.3 4.3 6.1 ns
Write cycle parameters[2]
tCSLAV CS LOW to address
valid time
WR1 3.3 4.3 6.1 ns
tCSLDV CS LOW to data
valid time
WR2 3.4 4.8 6.6 ns
tCSLWEL CS LOW to WE
LOW time
WR3; PB =1 [3] 2.6 + Tcy(clk)
(1 + WAITWEN)
3.3 + Tcy(clk)
(1 + WAITWEN)
4.6 + Tcy(clk)
(1 + WAITWEN)
ns
tCSLBLSL CS LOW to BLS
LOW time
WR4; PB = 1 [3] 2.7 3.5 4.9 ns
tWELWEH WE LOW to WE
HIGH time
WR5; PB =1 [3] (WAITWR
WAITWEN + 1)
Tcy(clk) 2.3
(WAITWR
WAITWEN + 1)
Tcy(clk) 2.8
(WAITWR
WAITWEN + 1)
Tcy(clk) 3.8
ns
tBLSLBLSH BLS LOW to BLS
HIGH time
PB = 1 [3] (WAITWR
WAITWEN + 3)
Tcy(clk) 2.8
(WAITWR
WAITWEN + 3)
Tcy(clk) 3.5
(WAITWR
WAITWEN + 3)
Tcy(clk) 5.0
ns
tWEHDNV WE HIGH to data
invalid time
WR6; PB =1 [3] 3.1 + Tcy(clk) 4.3 + Tcy(clk) 5.8 + Tcy(clk) ns
tWEHEOW WE HIGH to end of
write time
WR7; PB = 1 [6][3] Tcy(clk) 2.6 Tcy(clk) 3.4 Tcy(clk) 4.6 ns
tBLSHDNV BLS HIGH to data
invalid time
PB = 1 3.4 4.8 6.6 ns
tWEHANV WE HIGH to
address invalid time
PB = 1 [3] 3.0 + Tcy(clk) 3.8 + Tcy(clk) 5.3 + Tcy(clk) ns
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[1] Parameters are shown as RDn or WDn in Figure 19 as indicated in the Conditions column.
[2] Parameters specified for 40 % of VDD(3V3) for rising edges and 60 % of VDD(3V3) for falling edges.
[3] Tcy(clk) = 1/EMC_CLK (see LPC408x/7x User manual).
[4] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[5] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[6] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
tdeact deactivation time WR8; PB = 0; PB =
1
[3] 3.3 4.3 6.1 ns
tCSLBLSL CS LOW to BLS
LOW
WR9; PB = 0 [3] 2.7 + Tcy(clk)
(1 + WAITWEN)
3.5 + Tcy(clk)
(1 + WAITWEN)
4.9 + Tcy(clk)
(1 + WAITWEN)
ns
tBLSLBLSH BLS LOW to BLS
HIGH time
WR10; PB = 0 [3] (WAITWR
WAITWEN + 3)
Tcy(clk) 2.8
(WAITWR
WAITWEN + 3)
Tcy(clk) 3.5
(WAITWR
WAITWEN + 3)
Tcy(clk) 5.0
ns
tBLSHEOW BLS HIGH to end of
write time
WR11; PB = 0 [6][3] 3.3 + Tcy(clk) 4.4 + Tcy(clk) 6.1 + Tcy(clk) ns
tBLSHDNV BLS HIGH to data
invalid time
WR12; PB = 0 [3] 3.4 + Tcy(clk) 4.8 + Tcy(clk) 6.6 + Tcy(clk) ns
Table 15. Dynamic characteristics: Static external memory interface …continued
CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter[1] Conditions[1] Min Typ Max Unit
Fig 19. External static memory read/write access (PB = 0)
RD1
RD5
RD2
WR2
WR9
WR12
WR10 WR11
RD5
RD5
RD6
WR8
WR1
EOR EOW
RD7
RD4
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
EMC_Dx
002aag214
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Fig 20. External static memory read/write access (PB =1)
RD1 WR1
EMC_Ax
WR8
WR4
WR8
EMC_CSx
RD2
RD7
RD7
RD4 EMC_OE
EMC_BLSx
EMC_WE
RD5
WR2 WR6
RD5
RD5
RD5
RD6
RD3
EOR EOW
EMC_Dx
WR3 WR5 WR7
002aag215
Fig 21. External static memory burst read cycle
RD5 RD5 RD5 RD5
EMC_Ax
EMC_CSx
EMC_OE
EMC_BLSx
EMC_WE
EMC_Dx
002aag216
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32-bit ARM Cortex-M4 microcontroller
[1] Refers to SDRAM clock signal EMC_CLKx.
[2] CLKDLY = CLKOUTnDLY, where n = 0, 1.
[3] The data input set-up time has to be selected with the following margin:
tsu(D) + delay time of feedback clock SDRAM access time board delay time 0.
[4] The data input hold time has to be selected with the following margin:
th(D) + SDRAM access time board delay time delay time of feedback clock 0.
Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Common to read and write cycles
Tcy(clk) clock cycle time [1] 12.5 - - ns
td(SV) chip select valid delay time [2] (CLKDLY + 1)
0.25 + 2.8
(CLKDLY + 1)
0.25 + 3.5
(CLKDLY + 1)
0.25 + 5.1
ns
th(S) chip select hold time [2] (CLKDLY + 1)
0.25 1.0
(CLKDLY + 1)
0.25 1.1
(CLKDLY + 1)
0.25 1.5
ns
td(RASV) row address strobe valid delay time [2] (CLKDLY + 1)
0.25 + 2.8
(CLKDLY + 1)
0.25 + 3.6
(CLKDLY + 1)
0.25 + 5.1
ns
th(RAS) row address strobe hold time [2] (CLKDLY + 1)
0.25 0.8
(CLKDLY + 1)
0.25 0.9
(CLKDLY + 1)
0.25 1.0
ns
td(CASV) column address strobe valid delay time [2] (CLKDLY + 1)
0.25 + 2.7
(CLKDLY + 1)
0.25 + 3.4
(CLKDLY + 1)
0.25 + 4.9
ns
th(CAS) column address strobe hold time [2] (CLKDLY + 1)
0.25 0.8
(CLKDLY + 1)
0.25 1.0
(CLKDLY + 1)
0.25 1.2
ns
td(WV) write valid delay time [2] (CLKDLY + 1)
0.25 + 3.2
(CLKDLY + 1)
0.25 + 4.1
(CLKDLY + 1)
0.25 + 6.0
ns
th(W) write hold time [2] (CLKDLY + 1)
0.25 0.6
(CLKDLY + 1)
0.25 0.67
(CLKDLY + 1)
0.25 0.7
ns
td(AV) address valid delay time [2] (CLKDLY + 1)
0.25 + 3.4
(CLKDLY + 1)
0.25 + 4.6
(CLKDLY + 1)
0.25 + 6.8
ns
th(A) address hold time [2] (CLKDLY + 1)
0.25 1.1
(CLKDLY + 1)
0.25 1.4
(CLKDLY + 1)
0.25 1.8
ns
Read cycle parameters
tsu(D) data input set-up time [3] (FBCLKDLY +
1) 0.25 + 4.1
(FBCLKDLY +
1) 0.25 + 2.3
(FBCLKDLY +
1) 0.25 0.9
ns
th(D) data input hold time [4] (FBCLKDLY +
1) 0.25 + 4.0
(FBCLKDLY +
1) 0.25 + 4.7
(FBCLKDLY +
1) 0.25 + 5.8
ns
Write cycle parameters
td(QV) data output valid delay time [2] (CLKDLY + 1)
0.25 + 3.9
(CLKDLY + 1)
0.25 + 5.4
(CLKDLY + 1)
0.25 + 7.8
ns
th(Q) data output hold time [2] (CLKDLY + 1)
0.25 1.1
(CLKDLY + 1)
0.25 1.2
(CLKDLY + 1)
0.25 1.4
ns
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32-bit ARM Cortex-M4 microcontroller
[1] Refers to SDRAM clock signal EMC_CLKx.
[2] The data input set-up time has to be selected with the following margin:
tsu(D) + delay time of feedback clock SDRAM access time board delay time 0.
[3] The data input hold time has to be selected with the following margin:
th(D) + SDRAM access time - board delay time - delay time of feedback clock 0.
Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Min Typ Max Unit
Common to read and write cycles
Tcy(clk) clock cycle time [1] 12.5 - - ns
td(SV) chip select valid delay time (CMDDLY + 1)
0.25 + 4.9
(CMDDLY + 1)
0.25 + 6.7
(CMDDLY + 1)
0.25 + 10.4
ns
th(S) chip select hold time (CMDDLY + 1)
0.25 + 1.2
(CMDDLY + 1)
0.25 + 2.1
(CMDDLY + 1)
0.25 + 3.8
ns
td(RASV) row address strobe valid delay time (CMDDLY + 1)
0.25 + 4.9
(CMDDLY + 1)
0.25 + 6.8
(CMDDLY + 1)
0.25 + 10.4
ns
th(RAS) row address strobe hold time (CMDDLY + 1)
0.25 + 1.3
(CMDDLY + 1)
0.25 + 2.3
(CMDDLY + 1)
0.25 + 4.3
ns
td(CASV) column address strobe valid delay
time
(CMDDLY + 1)
0.25 + 4.8
(CMDDLY + 1)
0.25 + 6.7
(CMDDLY + 1)
0.25 + 10.2
ns
th(CAS) column address strobe hold time (CMDDLY + 1)
0.25 + 1.2
(CMDDLY + 1)
0.25 + 2.2
(CMDDLY + 1)
0.25 + 4.1
ns
td(WV) write valid delay time (CMDDLY + 1)
0.25 + 5.1
(CMDDLY + 1)
0.25 + 7.1
(CMDDLY + 1)
0.25 + 10.9
ns
th(W) write hold time (CMDDLY + 1)
0.25 + 1.5
(CMDDLY + 1)
0.25 + 2.6
(CMDDLY + 1)
0.25 + 4.8
ns
td(AV) address valid delay time (CMDDLY + 1)
0.25 + 5.5
(CMDDLY + 1)
0.25 + 7.7
(CMDDLY + 1)
0.25 + 11.9
ns
th(A) address hold time (CMDDLY + 1)
0.25 + 1.0
(CMDDLY + 1)
0.25 + 1.8
(CMDDLY + 1)
0.25 + 3.5
ns
Read cycle parameters
tsu(D) data input set-up time [2] (FBCLKDLY + 1)
0.25 + 4.1
(FBCLKDLY + 1)
0.25 + 2.3
(FBCLKDLY + 1)
0.25 0.9
ns
th(D) data input hold time [3] (FBCLKDLY + 1)
0.25 + 4.0
(FBCLKDLY + 1)
0.25 + 4.7
(FBCLKDLY + 1)
0.25 + 5.8
ns
Write cycle parameters
td(QV) data output valid delay time (CMDDLY + 1)
0.25 + 5.9
(CMDDLY + 1)
0.25 + 8.7
(CMDDLY + 1)
0.25 + 13.1
ns
th(Q) data output hold time (CMDDLY + 1)
0.25 + 1.0
(CMDDLY + 1)
0.25 + 2.0
(CMDDLY + 1)
0.25 + 3.9
ns
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32-bit ARM Cortex-M4 microcontroller
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0. See the LPC408x/7x user
manual for details.
Fig 22. Dynamic external memory interface signal timing
002aah129
EMC_CLKn Tcy(clk)
delay = 0
EMC_DYCSn,
EMC_RAS,
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
th(Q)
tsu(D) th(D)
EMC_D[31:0]
write
EMC_D[31:0]
read
td(QV)
td(xV) th(x)
Table 18. Dynamic characteristics: Dynamic external memory interface programmable
clock delays
CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
td delay time Programmable delay block 0 (CMDDLY
or CLKOUTnDLY bit 0 = 1)
[1] 0.1 0.2 ns
Programmable delay block 1 (CMDDLY
or CLKOUTnDLY bit 1 = 1)
[1] 0.2 0.5 ns
Programmable delay block 2 (CMDDLY
or CLKOUTnDLY bit 2 = 1)
[1] 0.5 1.3 ns
Programmable delay block 3 (CMDDLY
or CLKOUTnDLY bit 3 = 1)
[1] 1.2 2.9 ns
Programmable delay block 4 (CMDDLY
or CLKOUTnDLY bit 4 = 1)
[1] 2.4 6.0 ns
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32-bit ARM Cortex-M4 microcontroller
11.3 External clock
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.4 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.5 I/O pins
[1] Applies to standard port pin. For details, see the LPC408x/7x IBIS model available on the NXP website.
Table 19. Dynamic characteristic: external clock (see Figure 40)
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc oscillator frequency 1 - 25 MHz
Tcy(clk) clock cycle time 40 - 1000 ns
tCHCX clock HIGH time Tcy(clk) 0.4 - - ns
tCLCX clock LOW time Tcy(clk) 0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
Fig 23. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
tCHCL tCLCX
tCHCX
Tcy(clk)
tCLCH
002aaa907
Table 20. Dynamic characteristic: internal oscillators
Tamb = 40 C to +85 C; 2.7 V VDD(3V3) 3.6 V.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc(RC) internal RC oscillator
frequency
- 11.88 12 12.12 MHz
fi(RTC) RTC input frequency - - 32.768 - kHz
Table 21. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.
Symbol Parameter Conditions Min Typ Max Unit
tr rise time pin configured as
output
3.0 - 5.0 ns
tf fall time pin configured as
output
2.5 - 5.0 ns
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32-bit ARM Cortex-M4 microcontroller
11.6 SSP interface
[1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited
by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster
than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain.
The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the
SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register),
and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2] Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V.
[3] Tcy(clk) = 12 Tcy(PCLK). The maximum clock rate in slave mode is 1/12th of the PCLK rate.
[4] Tamb = 25 C; VDD(3V3) = 3.3 V.
Table 22. Dynamic characteristics: SSP pins in SPI mode
CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
SSP master
Tcy(clk) clock cycle time full-duplex
mode
[1] 30 - ns
when only
transmitting
30 - ns
tDS data set-up time in SPI mode [2] 14.8 - ns
tDH data hold time in SPI mode [2] 2 - ns
tv(Q) data output valid time in SPI mode [2] - 6.3 ns
th(Q) data output hold time in SPI mode [2] 2.4 - ns
SSP slave
Tcy(clk) clock cycle time [3] 100 - ns
tDS data set-up time in SPI mode [3][4] 14.8 - ns
tDH data hold time in SPI mode [3][4] 2 - ns
tv(Q) data output valid time in SPI mode [3][4] - 6.3 ns
th(Q) data output hold time in SPI mode [3][4] 2.4 - ns
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32-bit ARM Cortex-M4 microcontroller
Fig 24. SSP master timing in SPI mode
Fig 25. SSP slave timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
SCK (CPOL = 1)
DATA VALID DATA VALID
MOSI
MISO
tDS tDH
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
tv(Q)
CPHA = 1
CPHA = 0
002aae829
SCK (CPOL = 0)
MOSI
MISO
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
SCK (CPOL = 1)
DATA VALID DATA VALID
MOSI
MISO
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
CPHA = 1
CPHA = 0
002aae830
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32-bit ARM Cortex-M4 microcontroller
11.7 I2C-bus
[1] See the I2C-bus specification UM10204 for details.
[2] Parameters are valid over operating temperature range unless otherwise specified.
[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission
and the acknowledge.
[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the
VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA
output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the
SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors
are used, designers should allow for this when considering bus timing.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than
the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if
the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the
data must be valid by the set-up time before it releases the clock.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in
transmission and the acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT =
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
Table 23. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +85 C.[2]
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock
frequency
Standard-mode 0 100 kHz
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tf fall time [4][5][6][7] of both SDA and
SCL signals
Standard-mode
- 300 ns
Fast-mode 20 + 0.1 Cb 300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of
the SCL clock
Standard-mode 4.7 - s
Fast-mode 1.3 - s
Fast-mode Plus 0.5 - s
tHIGH HIGH period of
the SCL clock
Standard-mode 4.0 - s
Fast-mode 0.6 - s
Fast-mode Plus 0.26 - s
tHD;DAT data hold time [3][4][8] Standard-mode 0 - s
Fast-mode 0 - s
Fast-mode Plus 0 - s
tSU;DAT data set-up
time
[9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
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32-bit ARM Cortex-M4 microcontroller
11.8 I2S-bus interface
[1] CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) =
1600 ns, corresponds to the SCK signal in the I2S-bus specification.
Fig 26. I2C-bus pins clock timing
002aaf425
tf
70 %
SDA 30 %
tf
70 %
30 %
S
70 %
30 %
70 %
30 %
tHD;DAT
SCL
1 / fSCL
70 %
30 %
70 %
30 %
tVD;DAT
tHIGH
tLOW
tSU;DAT
Table 24. Dynamic characteristics: I2S-bus interface pins
CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
common to input and output
tr rise time [1] - 6.7 ns
tf fall time [1] - 8.0 ns
tWH pulse width HIGH on pins I2S_TX_SCK and
I2S_RX_SCK
[1] 25 - -
tWL pulse width LOW on pins I2S_TX_SCK and
I2S_RX_SCK
[1] - 25 ns
output
tv(Q) data output valid time on pin I2S_TX_SDA; [1] - 6 ns
input
tsu(D) data input set-up time on pin I2S_RX_SDA [1] 5 - ns
th(D) data input hold time on pin I2S_RX_SDA [1] 2 - ns
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32-bit ARM Cortex-M4 microcontroller
11.9 LCD
Remark: The LCD controller is available on parts LPC4088.
Fig 27. I2S-bus timing (transmit)
Fig 28. I2S-bus timing (receive)
002aag202
I2S_TX_SCK
I2S_TX_SDA
I2S_TX_WS
Tcy(clk) tf tr
tWH tWL
tv(Q)
tv(Q)
002aag203
Tcy(clk) tf tr
tWH
tsu(D) th(D)
tsu(D) tsu(D)
tWL
I2S_RX_SCK
I2S_RX_SDA
I2S_RX_WS
Table 25. Dynamic characteristics: LCD
CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
fclk clock frequency on pin LCD_DCLK - 50 MHz
td(QV) data output valid delay time - 12 ns
th(Q) data output hold time 0.5 - ns
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32-bit ARM Cortex-M4 microcontroller
11.10 SD/MMC
Remark: The SD/MMC card interface is available on parts LPC4088/78/76.
The LCD panel clock is shown with the default polarity. The clock can be inverted via the IPC bit in
the LCD_POL register. Typically, the LCD panel uses the falling edge of the LCD_DCLK to sample
the data.
Fig 29. LCD timing
002aah325
LCD_DCLK
td(QV)
Tcy(clk)
th(Q)
LCD_VD[n]
Table 26. Dynamic characteristics: SD/MMC
CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
fclk clock frequency on pin SD_CLK; data transfer mode - 25 MHz
on pin SD_CLK; identification mode 25 MHz
tsu(D) data input set-up
time
on pins SD_CMD, SD_DAT[3:0] as
inputs
6 - ns
th(D) data input hold time on pins SD_CMD, SD_DAT[3:0] as
inputs
6 - ns
td(QV) data output valid
delay time
on pins SD_CMD, SD_DAT[3:0] as
outputs
- 23 ns
th(Q) data output hold
time
on pins SD_CMD, SD_DAT[3:0] as
outputs
3.5 - ns
Fig 30. SD/MMC timing
002aag204
SD_CLK
SD_DATn (O)
SD_DATn (I)
td(QV)
tsu(D) th(D)
Tcy(clk)
th(Q)
SD_CMD (O)
SD_CMD (I)
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32-bit ARM Cortex-M4 microcontroller
11.11 SPIFI
12. Characteristics of the analog peripherals
12.1 ADC electrical characteristics
Table 27. Dynamic characteristics: SPIFI
Tamb = 40 C to 85 C; 3.0 V VDD(3V3) 3.6 V; CL = 30 pF. Values guaranteed by design.
Symbol Parameter Min Max Unit
Tcy(clk) clock cycle time 11.8 - ns
tDS data set-up time 4.8 - ns
tDH data hold time 0 - ns
tv(Q) data output valid time - 8.8 ns
th(Q) data output hold time 3 - ns
Fig 31. SPIFI timing
SPIFI_SCK
SPIFI data out
SPIFI data in
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
002aah409
Table 28. 12-bit ADC characteristics
VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDDA V
12-bit resolution; 400 kSamples/sec
ED differential linearity
error
[2][3][4] - - 1 LSB
EL(adj) integral non-linearity [2][5] - - 6 LSB
EO offset error [2][6] - - 5 LSB
EG gain error [2][7] - - 5 LSB
ET absolute error [2][8]- - <8 LSB
fclk(ADC) ADC clock frequency - - 12.4 MHz
fc(ADC) ADC conversion
frequency
[9]- - 400 kHz
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32-bit ARM Cortex-M4 microcontroller
[1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.
[2] Conditions: VSSA = 0 V, VDDA = 3.3 V.
[3] The ADC is monotonic, there are no missing codes.
[4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 32.
[5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 32.
[6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 32.
[7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer
curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 32.
[8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer
curve of the non-calibrated ADC and the ideal transfer curve. See Figure 32.
[9] In single-conversion mode.
[10] See Figure 33.
[11] 8-bit resolution is achieved by ignoring the lower four bits of the ADC conversion result.
Cia analog input
capacitance
- - 5 pF
Rvsi voltage source
interface resistance
[10]- - 1 k
8-bit resolution[11]; 1.16 MSamples/sec
ED differential linearity
error
[2][3][4] - 1 - LSB
EL(adj) integral non-linearity [2][5] - 1 - LSB
EO offset error [2][6] - 1 - LSB
EG gain error [2][7] - 1 - LSB
ET absolute error [2][8]- - <1.5 LSB
fclk(ADC) ADC clock frequency - - 36 MHz
fc(ADC) ADC conversion
frequency
[9]- - 1.16 MHz
Cia analog input
capacitance
- - 5 pF
Rvsi voltage source
interface resistance
[10]- - 1 k
Table 28. 12-bit ADC characteristics …continued
VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1]
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 3 — 1 May 2014 110 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 32. 12-bit ADC characteristics
002aaf436
4095
4094
4093
4092
4091
(2)
(1)
1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096
7
6
5
4
3
2
1
0
4090
(5)
(4)
(3)
1 LSB
(ideal)
code
out
VREF P - VSS
4096
offset
error
EO
gain
error
EG
offset error
EO
VIA (LSBideal)
1 LSB =
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Product data sheet Rev. 3 — 1 May 2014 111 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
12.2 DAC electrical characteristics
The values of resistor components Rcmp and Rsw vary with temperature and input voltage and are
process-dependent.
Fig 33. ADC interface to pins ADC0_IN[n]
Table 29. ADC interface components
Component Range Description
Rcmp 90 to 300 Switch-on resistance for the comparator input switch. Varies
with temperature, input voltage, and process.
Rsw 500 to 2 k Switch-on resistance for channel selection switch. Varies with
temperature, input voltage, and process.
C1 110 fF Parasitic capacitance from the ADC block level.
C2 80 fF Parasitic capacitance from the ADC block level.
C3 1.6 pF Sampling capacitor.
LPC408x/7x
AD0[n]
110 fF 80 fF Cia
1.6 pF
Rvsi
Rsw
500 Ω - 2 kΩ
Rcmp
90 Ω - 300 Ω
VSS VEXT
002aah275
ADC
COMPARATOR
BLOCK
C1
C3
C2
Table 30. 10-bit DAC electrical characteristics
VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
ED differential linearity
error
- 1 - LSB
EL(adj) integral non-linearity - 1.5 - LSB
EO offset error - 0.6 - %
EG gain error - 0.6 - %
CL load capacitance - - 200 pF
RL load resistance 1 - - k
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Product data sheet Rev. 3 — 1 May 2014 112 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
12.3 Comparator electrical characteristics
[1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to
+85 C.
[2] Input hysteresis is relative to the reference input channel and is software programmable.
Table 31. Comparator characteristics
VDDA= 3.0 V and Tamb = 25 C unless noted otherwise.
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
IDD supply current - 55 - A
VIC common-mode input voltage 0 - VDDA V
DVO output voltage variation 0 - VDDA V
Voffset offset voltage VIC = 0.1 V - 4 to +4.2 - mV
VIC = 1.5 V - 2 - mV
VIC = 2.8 V - 2.5 mV
Dynamic characteristics
tstartup start-up time nominal process - 4 - s
tPD propagation delay HIGH to LOW; VDDA = 3.3 V;
VIC = 0.1 V; 50 mV overdrive input [1] 122 130 142 ns
VIC = 0.1 V; rail-to-rail input [1] 173 189 233 ns
VIC = 1.5 V; 50 mV overdrive input [1] 101 108 119 ns
VIC = 1.5 V; rail-to-rail input [1] 114 127 162 ns
VIC = 2.9 V; 50 mV overdrive input [1] 123 134 143 ns
VIC = 2.9 V; rail-to-rail input [1] 79 91 120 ns
tPD propagation delay LOW to HIGH; VDDA = 3.3 V;
VIC = 0.1 V; 50 mV overdrive input [1] 221 232 254 ns
VIC = 0.1 V; rail-to-rail input [1] 59 63 68 ns
VIC = 1.5 V; 50 mV overdrive input [1] 183 229 249 ns
VIC = 1.5 V; rail-to-rail input [1] 147 174 213 ns
VIC = 2.9 V; 50 mV overdrive input [1] 171 192 216 ns
VIC = 2.9 V; rail-to-rail input [1] 235 305 450 ns
Vhys hysteresis voltage positive hysteresis; VDDA = 3.0 V;
VIC = 1.5 V
[2] - 5, 10, 20 - mV
Vhys hysteresis voltage negative hysteresis; VDDA = 3.0 V;
VIC = 1.5 V
[2] - 5, 10, 20 - mV
Rlad ladder resistance - - 1.034 - M
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Product data sheet Rev. 3 — 1 May 2014 113 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
[1] Maximum values are derived from worst case simulation (VDDA = 2.6 V; Tamb = 85 C; slow process
models).
[2] Settling time applies to switching between comparator and ADC channels.
[1] Measured on typical silicon samples with a 2 kHz input signal and overdrive < 100 V. Power switched off
to all analog peripherals except the comparator.
Table 32. Comparator voltage ladder dynamic characteristics
Symbol Parameter Conditions Min Typ Max Unit
ts(pu) power-up settling
time
to 99% of voltage
ladder output
value
[1]- - 30 s
ts(sw) switching settling
time
to 99% of voltage
ladder output
value
[1]
[2]
- - 15 s
Table 33. Comparator voltage ladder reference static characteristics
VDDA = 3.3 V; Tamb = -40 C to + 85C.
Symbol Parameter Conditions Min Typ Max[1] Unit
EV(O) output voltage error Internal VDDA supply
decimal code = 00 0 0 0 %
decimal code = 08 0.45 0.5 0.55 %
decimal code = 16 0.99 1.1 1.21 %
decimal code = 24 1.26 1.4 1.54 %
decimal code = 30 1.35 1.5 1.65 %
decimal code = 31 1.35 1.5 1.65 %
EV(O) output voltage error External VDDCMP
supply
decimal code = 00 0 0 0 %
decimal code = 08 0.44 0.4 0.36 %
decimal code = 16 0.18 0.2 0.22 %
decimal code = 24 0.45 0.5 0.55 %
decimal code = 30 0.54 0.6 0.66 %
decimal code = 31 0.45 0.5 0.55 %
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Product data sheet Rev. 3 — 1 May 2014 114 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
13. Application information
13.1 Suggested USB interface solutions
Remark: The USB controller is available as a device/Host/OTG controller on parts
LPC4088 and LPC4078/76 and as device-only controller on parts LPC4074/72.
Fig 34. USB interface on a self-powered device
LPC40xx
USB-B
connector
USB_D+
USB_CONNECT
SoftConnect switch
USB_DVBUS
VSS
VDD(3V3)
R1
1.5 kΩ
RS = 33 Ω
002aah267
RS = 33 Ω
USB_UP_LED
Fig 35. USB interface on a bus-powered device
LPC40xx
VDD(3V3)
R1
1.5 kΩ
R2
USB_UP_LED
002aah268
USB-B
connector
USB_D+
USB_DVBUS
VSS
RS = 33 Ω
RS = 33 Ω
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Product data sheet Rev. 3 — 1 May 2014 115 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 36. USB OTG port configuration: port 1 OTG dual-role device, port 2 host
USB_UP_LED1
USB_D+1
USB_D-1
USB_PWRD2
USB_SDA1
USB_SCL1
RSTOUT
15 kΩ 15 kΩ
LPC408x/7x
USB-A
connector
Mini-AB
connector
33 Ω
33 Ω
33 Ω
33 Ω
VDD
VDD
VDD
USB_UP_LED2
VDD
USB_OVRCR2
LM3526-L
ENA
IN
5 V
OUTA
FLAGA
VDD
D+
DVBUS
USB_PPWR2
USB_D+2
USB_D-2
002aah269
R7
R4 R5 R6
R1 R2 R3 R4
R8
USB_INT1
RESET_N
ADR/PSW
SPEED
SUSPEND
OE_N/INT_N
SCL
SDA
INT_N
VBUS
ID
DP
DM
ISP1302
VSSIO,
VSSCORE
VSSIO,
VSSCORE
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Product data sheet Rev. 3 — 1 May 2014 116 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 37. USB OTG port configuration: VP_VM mode
USB_TX_DP1
USB_TX_DM1
USB_RCV1
USB_RX_DP1
USB_RX_DM1
USB_SCL1
USB_SDA1
SPEED
ADR/PSW
SDA
SCL
RESET_N
INT_N
VP
VM
SUSPEND
OE_N/INT_N
SE0_VM
DAT_VP
RCV
VBUS
ID
DP
DM
LPC408x/7x
ISP1302
USB MINI-AB
connector
33 Ω
33 Ω
002aah270
USB_TX_E1
RSTOUT
VDD
VDD
USB_INT1
USB_UP_LED1
VDD
VSSIO,
VSSCORE
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Product data sheet Rev. 3 — 1 May 2014 117 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 38. USB host port configuration: port 1 and port 2 as hosts
USB_UP_LED1
USB_D+1
USB_D-1
USB_PWRD1
USB_PWRD2
15 kΩ
15 kΩ 15 kΩ
15 kΩ
LPC408x/7x
USB-A
connector
USB-A
connector
33 Ω
33 Ω
33 Ω
33 Ω
002aah271
VDD
USB_UP_LED2
VDD
USB_OVRCR1
USB_OVRCR2
USB_PPWR1
LM3526-L
ENA
ENB
IN
5 V
FLAGA
OUTA
OUTB
FLAGB
VDD
VDD
D+
DD+
DVBUS
VBUS
USB_PPWR2
USB_D+2
USB_D-2
VSSIO,
VSSCORE
VSSIO,
VSSCORE
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Product data sheet Rev. 3 — 1 May 2014 118 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
13.2 Crystal oscillator XTAL input and component selection
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
Fig 39. USB device port configuration: port 1 host and port 2 device
USB_UP_LED1
USB_D+1
USB_D-1
USB_PWRD1
15 kΩ 15 kΩ
LPC408x/7x
USB-A
connector
USB-B
connector
33 Ω
33 Ω
33 Ω
33 Ω
002aah272
VDD
USB_UP_LED2
USB_CONNECT2
VDD
VDD
USB_OVRCR1
USB_PPWR1
LM3526-L
ENA
IN
5 V
FLAGA
OUTA
VDD
D+
DD+
DVBUS
USB_D+2
USB_D-2
VBUS VBUS
VSSIO,
VSSCORE
VSSIO,
VSSCORE
Fig 40. Slave mode operation of the on-chip oscillator
LPC40xx
XTAL1
Ci
100 pF
Cg
002aah273
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Product data sheet Rev. 3 — 1 May 2014 119 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 40), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 41 and in
Table 34 and Table 35. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 41 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
Fig 41. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 34. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1/CX2
1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 300 39 pF, 39 pF
30 pF < 300 57 pF, 57 pF
5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 200 39 pF, 39 pF
30 pF < 100 57 pF, 57 pF
10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 60 39 pF, 39 pF
15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF
002aah274
LPC40xx
XTALIN XTALOUT
CX1 CX2
XTAL
= CL CP
RS
L
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Product data sheet Rev. 3 — 1 May 2014 120 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
13.3 XTAL Printed-Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plane. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen
according to the increase in parasitics of the PCB layout.
13.4 Standard I/O pin configuration
Figure 42 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver: Open-drain mode enabled/disabled
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Analog input
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Table 35. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF
20 pF < 100 39 pF, 39 pF
20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 80 39 pF, 39 pF
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Product data sheet Rev. 3 — 1 May 2014 121 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
13.5 Reset pin configuration
13.6 Reset pin configuration for RTC operation
Under certain circumstances, the RTC may temporarily pause and lose fractions of a
second during the rising and falling edges of the RESET signal.
Fig 42. Standard I/O pin configuration with analog input
PIN
VDD VDD
ESD
VSS
ESD
strong
pull-up
strong
pull-down
VDD
weak
pull-up
weak
pull-down
open-drain enable
output enable
repeater mode
enable
pull-up enable
pull-down enable
data output
data input
analog input
select analog input
002aaf272
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
Fig 43. Reset pin configuration
VSS
reset
002aaf274
VDD
VDD
VDD
Rpu ESD
ESD
20 ns RC
GLITCH FILTER
PIN
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 122 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the
RESET signal, connect an RC filter between the RESET pin and the external reset input.
Fig 44. Reset input with RC filter
002aag552
External
RESET input
10 kΩ
0.1 μF
RESET pin
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 123 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
14. Package outline
Fig 45. Package outline SOT459-1 (LQFP208)
UNIT A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
28.1
27.9 0.5
30.15
29.85
1.43
1.08
7
0
o
1 0.12 0.08 0.08 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT459-1 136E30 MS-026 00-02-06
03-02-20
D(1)
28.1
27.9
HD
30.15
29.85
Z E
1.43
1.08
D
pin 1 index
e bp
θ
E
A A1
Lp
detail X
L
(A 3 )
B
52
c
HD
bp
HE
A2
v M B
D
ZD
A
ZE
e
v M A
X
1
208
157
156
105
104
53
y
w M
w M
0 5 10 mm
scale
LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1
A
max.
1.6
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Product data sheet Rev. 3 — 1 May 2014 124 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 46. Package outline SOT950-1 (TFBGA208)
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT950-1 - - -
SOT950-1
06-06-01
06-06-14
UNIT A
max
mm 1.2 0.4
0.3
0.8
0.6
15.1
14.9
15.1
14.9 0.8 12.8 0.15 0.08 0.1
A1
DIMENSIONS (mm are the original dimensions)
TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm
0 5 10 mm
scale
A2 b
0.5
0.4
D E e e1 e2
12.8
v w y
0.12
y1
C
y1 C y
X
b
ball A1
index area
e2
e1
e
e
∅ v M C A B
∅ w M C
A
B
C
D
E
F
H
K
G
L
J
M
N
P
R
U
T
2 4 6 8 10 12 14 16
1 3 5 7 9 11 13 15 17
ball A1
index area
D B A
E
detail X
A
A2
A1
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 125 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 47. Package outline SOT570-3 (TFBGA180)
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
SOT570-3
SOT570-3
08-07-09
10-04-15
UNIT
mm
max
nom
min
1.20
1.06
0.95
0.40
0.35
0.30
0.50
0.45
0.40
12.1
12.0
11.9
12.1
12.0
11.9
0.8 10.4 0.15 0.12
A
DIMENSIONS (mm are the original dimensions)
TFBGA180: thin fine-pitch ball grid array package; 180 balls
0 5 10 mm
scale
A1 A2
0.80
0.71
0.65
b D E e e1
10.4
e2 v w
0.05
y y1
0.1
ball A1
index area
D B A
E
C
y1 C y
X
A
B
C
D
E
F
H
K
G
L
J
M
N
P
2 4 6 8 10 12 14
1 3 5 7 9 11 13
b
e2
e1
e
e
1/2 e
1/2 e
∅ v M C A B
∅ w M C
ball A1
index area
detail X
A
A2
A1
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 126 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 48. Package outline SOT486-1 (LQFP144)
UNIT A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9 0.5
22.15
21.85
1.4
1.1
7
0
o
1 0.2 0.08 0.08 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT486-1 136E23 MS-026
00-03-14
03-02-20
D(1) (1) (1)
20.1
19.9
HD
22.15
21.85
Z E
1.4
1.1
D
0 5 10 mm
scale
e bp
θ
E
A1
A
Lp
detail X
L
(A 3 )
B
c
bp
HE A2
HD v M B
D
ZD
A
ZE
e
v M A
X
y
w M
w M
A
max.
1.6
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
108
109
pin 1 index
73
72
37
1
144
36
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 127 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 49. Package outline SOT407-1 (LQFP100)
UNIT
A
max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
14.1
13.9
0.5
16.25
15.75
1.15
0.85
7
0
o
1 0.2 0.08 0.08 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT407-1 136E20 MS-026
00-02-01
03-02-20
D(1) (1) (1)
14.1
13.9
HD
16.25
15.75
Z E
1.15
0.85
D
bp
e
θ
E
A1
A
Lp
detail X
L
(A 3 )
B
25
c
HD
bp
HE A2
v M B
D
ZD
A
ZE
e
v M A
X
1
100
76
75 51
50
26
y
pin 1 index
w M
w M
0 5 10 mm
scale
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
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Product data sheet Rev. 3 — 1 May 2014 128 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 50. Package outline SOT315-1 (LQFP80)
UNIT
A
max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.16
0.04
1.5
1.3
0.25
0.27
0.13
0.18
0.12
12.1
11.9
0.5
14.15
13.85
1.45
1.05
7
0
o
1 0.2 0.15 0.1 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.30
SOT315-1 136E15 MS-026
00-01-19
03-02-25
D(1) (1) (1)
12.1
11.9
HD
14.15
13.85
Z E
1.45
1.05
D
bp
e
θ
E
A1
A
Lp
detail X
L
(A 3 )
B
20
c
HD
bp
HE A2
v M B
D
ZD
A
ZE
e
v M A
X
1
80
61
60 41
40
21
y
pin 1 index
w M
w M
0 5 10 mm
scale
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
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Product data sheet Rev. 3 — 1 May 2014 129 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 51. Package outline SOT1328-1 (TFBGA80)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1328-1
sot1328-1_po
12-05-07
12-06-14
Unit
mm
max
nom
min
1.15
1.00
0.90
0.35
0.30
0.25
0.45
0.40
0.35
7.1
7.0
6.9
7.1
7.0
6.9
0.65 5.85 0.15 0.08
A
Dimensions (mm are the original dimensions)
TFBGA80: plastic thin fine-pitch ball grid array package; 80 balls SOT1328-1
A1 A2
0.80
0.70
0.65
b D E e e1
5.85
e2 v w
0.05
y y1
0.1
0 5 mm
scale
ball A1
index area
ball A1
index area
D B A
E
detail X
A
A1
A2
C
y1 C y
X
e2
e
1/2 e
b
e1
e
1/2 e
Ø v C A B
Ø w C
1 2 3 4 5 6 7 8 9 10
K
J
H
G
F
E
D
C
B
A
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Product data sheet Rev. 3 — 1 May 2014 130 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
15. Soldering
Fig 52. Reflow soldering of the LQFP208 package
SOT459-1
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP208 package
Ax
Bx
Gx
Hy Gy
Hx
By Ay
P2 P1
D2 (8×) D1
(0.125)
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
sot459-1_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
0.500 0.560 31.300 31.300 28.300 28.300 1.500 0.280 0.400 28.500 28.500 31.550 31.550
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Product data sheet Rev. 3 — 1 May 2014 131 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 53. Reflow soldering of the TFBGA180 package
DIMENSIONS in mm
P SL SP SR Hx Hy
Hx
Hy
SOT570-3
solder land plus solder paste
occupied area
Footprint information for reflow soldering of TFBGA180 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
Generic footprint pattern
Refer to the package outline drawing for actual layout
detail X
see detail X
sot570-3_fr
0.80 0.400 0.400 0.550 12.575 12.575
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Product data sheet Rev. 3 — 1 May 2014 132 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 54. Reflow soldering of the LQFP144 package
SOT486-1
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP144 package
Ax
Bx
Gx
Hy Gy
Hx
By Ay
P2 P1
D2 (8×) D1
(0.125)
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
sot486-1_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 133 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 55. Reflow soldering of the LQFP100 package
SOT407-1
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP100 package
Ax
Bx
Gx
Hy Gy
Hx
By Ay
P2 P1
D2 (8×) D1
(0.125)
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
sot407-1
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 134 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Fig 56. Reflow soldering of the LQFP80 package
SOT315-1
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP80 package
Ax
Bx
Gx
Hy Gy
Hx
By Ay
P2 P1
D2 (8×) D1
(0.125)
Ax Ay Bx By D1 D2 Gx Gy Hx Hy
15.300 15.300 12.300 12.300
P1
0.500
P2
0.560 0.280
C
1.500 0.400 12.500 12.500 15.550 15.550
sot315-1_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 1 May 2014 135 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
16. Abbreviations
Table 36. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
BOD BrownOut Detection
CAN Controller Area Network
DAC Digital-to-Analog Converter
DMA Direct Memory Access
EOP End Of Packet
ETM Embedded Trace Macrocell
GPIO General Purpose Input/Output
GPS Global Positioning System
HVAC Heating, Venting, and Air Conditioning
IRC Internal RC
IrDA Infrared Data Association
JTAG Joint Test Action Group
MAC Media Access Control
MIIM Media Independent Interface Management
OHCI Open Host Controller Interface
OTG On-The-Go
PHY Physical Layer
PLC Programmable Logic Controller
PLL Phase-Locked Loop
PWM Pulse Width Modulator
RMII Reduced Media Independent Interface
SE0 Single Ended Zero
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TCM Tightly Coupled Memory
TTL Transistor-Transistor Logic
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
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Product data sheet Rev. 3 — 1 May 2014 136 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
17. Revision history
Table 37. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC408X_7X v.3 20140501 Product data sheet - LPC408X_7X v.2
• Added TFBGA80 to features list.
• Added Section 11.11 “SPIFI”.
• Table 3:
– Added function SSP2_SCK to pin P5[2].
– Added function SSP2_SSEL to pin P5[3].
– Updated pin description of STCLK.
– 5 ns glitch filter changed to 10 ns for EINTx pins.
– LQFP80 pin 12 changed from P2[30] to DNC.
• Table 11: Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and
DAC are not used.”.
• Table 28: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and
DAC are not used.”.
• Section 7.37.2 “Brownout detection”: Updated BOD interrupt and reset values.
• Table 15: Added typical specs.
• Table 16:
– Added typical specs
– Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
• Table 17:
– Added typical specs
– Removed “All programmable delays EMCDLYCTL are bypassed” from table title.
• Table note 9 added in Table 28 “12-bit ADC characteristics”.
LPC408X_7X v.2 20130703 Product data sheet - LPC408X_7X v.1.1
• Added LQFP100 and TFBGA80.
• Table 3:
– Removed overbar from NMI.
– Added minimum reset pulse width of 50 ns to RESET pin.
– Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC).
– Added boundary scan information to description for RESET pin.
• Table 11:
– Updated typ numbers for IDD(REG)(3V3) and IBAT.
– Added max values for deep sleep, power down, and deep PD for IBAT.
• Table 15, Table note 3: Changed Tcy(clk) = 1/CCLK to Tcy(clk) = 1/EMC_CLK.
• Table 21: Removed reference to RESET pin from Table note 1.
• Table 22:
– Removed Tcy(PCLK) spec; already given by the maximum chip frequency.
– Changed min clock cyle time for SSP slave from 120 to 100.
– Updated Table note 1 and Table note 3.
• Section 7.24.1 “Features”: Changed max speed for SSP master from 60 to 33.
• Updated EMC timing specs to CL = 30 pF in Table 15, Table 16, Table 17, and Table 18.
• SOT570-2 obsolete; replaced with SOT570-3.
LPC408X_7X v.1.1 20121114 Product data sheet - LPC408X_7X v.1
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Product data sheet Rev. 3 — 1 May 2014 137 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Modifications: • Changed data sheet status to Product.
LPC408X_7X v.1 20120917 Objective data sheet - -
Table 37. Revision history …continued
Document ID Release date Data sheet status Change notice Supersedes
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Product data sheet Rev. 3 — 1 May 2014 138 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
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Product data sheet Rev. 3 — 1 May 2014 139 of 141
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet Rev. 3 — 1 May 2014 140 of 141
continued >>
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 5
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Functional description . . . . . . . . . . . . . . . . . . 52
7.1 Architectural overview . . . . . . . . . . . . . . . . . . 52
7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 52
7.3 ARM Cortex-M4 Floating Point Unit (FPU). . . 52
7.4 On-chip flash program memory . . . . . . . . . . . 52
7.5 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.6 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 52
7.7 Memory Protection Unit (MPU). . . . . . . . . . . . 53
7.8 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.9 Nested Vectored Interrupt Controller (NVIC) . 56
7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.9.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 56
7.10 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 56
7.11 External Memory Controller (EMC). . . . . . . . . 56
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.12 General purpose DMA controller . . . . . . . . . . 58
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.13 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.14 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 59
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.15 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.16 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.16.1 USB device controller . . . . . . . . . . . . . . . . . . . 61
7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.16.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 62
7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.16.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 62
7.16.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.17 SD/MMC card interface . . . . . . . . . . . . . . . . . 62
7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.18 Fast general purpose parallel I/O . . . . . . . . . . 63
7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.19 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.20 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.21 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.22 UART0/1/2/3 and USART4 . . . . . . . . . . . . . . 65
7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.23 SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.24 SSP serial I/O controller. . . . . . . . . . . . . . . . . 66
7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.25 I2C-bus serial I/O controllers . . . . . . . . . . . . . 66
7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.26 I2S-bus serial I/O controllers . . . . . . . . . . . . . 67
7.26.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.27 CAN controller and acceptance filters . . . . . . 67
7.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.28 General purpose 32-bit timers/external event
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.29 Pulse Width Modulator (PWM). . . . . . . . . . . . 69
7.29.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.30 Motor control PWM . . . . . . . . . . . . . . . . . . . . 70
7.31 Quadrature Encoder Interface (QEI) . . . . . . . 70
7.31.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.32 ARM Cortex-M4 system tick timer . . . . . . . . . 71
7.33 Windowed WatchDog Timer (WWDT) . . . . . . 71
7.33.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.34 RTC and backup registers . . . . . . . . . . . . . . . 72
7.34.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.35 Event monitor/recorder . . . . . . . . . . . . . . . . . 72
7.35.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.36 Clocking and power control . . . . . . . . . . . . . . 73
7.36.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 73
7.36.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 74
7.36.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 74
7.36.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 74
7.36.1.4 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 74
7.36.2 Main PLL (PLL0) and Alternate PLL (PLL1) . 74
7.36.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 75
7.36.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.36.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.36.4.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 76
7.36.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 77
7.36.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 77
7.36.4.5 Wake-up Interrupt Controller (WIC) . . . . . . . . 77
7.36.5 Peripheral power control . . . . . . . . . . . . . . . . 78
7.36.6 Power domains . . . . . . . . . . . . . . . . . . . . . . . 78
7.37 System control . . . . . . . . . . . . . . . . . . . . . . . . 79
7.37.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.37.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 80
7.37.3 Code security (Code Read Protection - CRP) 80
NXP Semiconductors LPC408x/7x
32-bit ARM Cortex-M4 microcontroller
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 May 2014
Document identifier: LPC408X_7X
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
7.37.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.37.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 81
7.37.6 External interrupt inputs . . . . . . . . . . . . . . . . . 81
7.37.7 Memory mapping control . . . . . . . . . . . . . . . . 81
7.38 Debug control . . . . . . . . . . . . . . . . . . . . . . . . . 81
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 81
9 Thermal characteristics . . . . . . . . . . . . . . . . . 83
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 85
10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 88
10.2 Peripheral power consumption . . . . . . . . . . . . 90
10.3 Electrical pin characteristics . . . . . . . . . . . . . . 92
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 94
11.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2 External memory interface . . . . . . . . . . . . . . . 95
11.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . 101
11.4 Internal oscillators. . . . . . . . . . . . . . . . . . . . . 101
11.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 102
11.7 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.8 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 105
11.9 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.10 SD/MMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.11 SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12 Characteristics of the analog peripherals . . 108
12.1 ADC electrical characteristics . . . . . . . . . . . . 108
12.2 DAC electrical characteristics . . . . . . . . . . . 111
12.3 Comparator electrical characteristics . . . . . . 112
13 Application information. . . . . . . . . . . . . . . . . 114
13.1 Suggested USB interface solutions . . . . . . . 114
13.2 Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.3 XTAL Printed-Circuit Board (PCB) layout
guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
13.4 Standard I/O pin configuration . . . . . . . . . . . 120
13.5 Reset pin configuration. . . . . . . . . . . . . . . . . 121
13.6 Reset pin configuration for RTC operation . . 121
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . 123
15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 135
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . 136
18 Legal information. . . . . . . . . . . . . . . . . . . . . . 138
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 138
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 138
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 138
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 139
19 Contact information. . . . . . . . . . . . . . . . . . . . 139
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
1. Introduction
This document describes the functionality and electrical specifications of the
transceiver IC PN512.
The PN512 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
1.1 Different available versions
The PN512 is available in three versions:
• PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2
(TFBGA64), hereafter named as version 2.0
• PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),
hereafter named as industrial version, fulfilling the automotive qualification stated in
AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical
stress test qualification for automotive integrated circuits (ICs).
• PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named
as version 1.0
The data sheet describes the functionality for the industrial version and version 2.0. The
differences of the version 1.0 to the version 2.0 are summarized in Section 21. The
industrial version has only differences within the outlined characteristics and limitations.
2. General description
The PN512 transceiver ICs support 4 different operating modes
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Reader/Writer mode supporting ISO/IEC 14443B
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal
transmitter part is able to drive a reader/writer antenna designed to communicate with
ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The
receiver part provides a robust and efficient implementation of a demodulation and
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decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and
transponders. The digital part handles the complete ISO/IEC 14443A framing and error
detection (Parity & CRC).
The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports
contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both
directions.
Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN512 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication
scheme, given correct implementation of additional components, like oscillator, power
supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4
and/or ISO/IEC 14443B anticollision are correctly implemented.
In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer
command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface
scheme. The PN512 generates the digital load modulated signals and in addition with an
external circuit the answer can be sent back to the reader/writer. A complete card
functionality is only possible in combination with a secure IC using the S2C interface.
Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an
NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication
mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092
NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error
detection.
Various host controller interfaces are implemented:
• 8-bit parallel interface1
• SPI interface
• serial UART (similar to RS232 with voltage levels according pad voltage supply)
• I2C interface.
A purchaser of this NXP IC has to take care for appropriate third party patent licenses.
1. 8-bit parallel Interface only available in HVQFN40 package.
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3. Features and benefits
Highly integrated analog circuitry to demodulate and decode responses
Buffered output drivers for connecting an antenna with the minimum number of
external components
Integrated RF Level detector
Integrated data mode detector
Supports ISO/IEC 14443 A/MIFARE
Supports ISO/IEC 14443 B Read/Write modes
Typical operating distance in Read/Write mode up to 50 mm depending on the
antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna
size and tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation
mode of about 100 mm depending on the antenna size and tuning and the external
field strength
Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode
ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
Contactless communication according to the FeliCa scheme at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
S2C interface
Additional power supply to directly supply the smart card IC connected via S2C
Supported host interfaces
SPI up to 10 Mbit/s
I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin
voltage supply
8-bit parallel interface with and without Address Latch Enable
FIFO buffer handles 64 byte send and receive
Flexible interrupt modes
Hard reset with low power function
Power-down mode per software
Programmable timer
Internal oscillator for connection to 27.12 MHz quartz crystal
2.5 V to 3.6 V power supply
CRC coprocessor
Programmable I/O pins
Internal self-test
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4. Quick reference data
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
[4] Ipd is the total current for all supplies.
[5] IDD(PVDD) depends on the overall load at the digital pins.
[6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[7] During typical circuit operation, the overall current is below 100 mA.
[8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2] 2.5 - 3.6 V
VDDD digital supply voltage
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage [3] 1.6 - 3.6 V
VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V
Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V
hard power-down; pin NRSTPD set LOW [4]- - 5 A
soft power-down; RF level detector on [4]- - 10 A
IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9 mA
IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s
RcvOff bit = 0
- 7 10 mA
pin AVDD; receiver switched off; VDDA = 3 V,
CommandReg register’s RcvOff bit = 1
- 3 5 mA
IDD(PVDD) PVDD supply current pin PVDD [5]- - 40 mA
IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8]- 60 100 mA
Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 +85 C
lndustrial version:
Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V
hard power-down; pin NRSTPD set LOW [4]- - 15 A
soft power-down; RF level detector on [4]- - 30 A
Tamb ambient temperature HVQFN32 40 - +90 C
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5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-1
PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-1
PN5120A0ET/C2 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT1336-1
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6. Block diagram
The analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare
the internal receiver to demodulate signals, which are sent to the PN512.
The communication (S2C) interface provides digital signals to support communication for
transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
Various host interfaces are implemented to meet different customer requirements.
Fig 1. Simplified block diagram of the PN512
001aaj627
HOST
ANTENNA FIFO
BUFFER
ANALOG
INTERFACE
CONTACTLESS
UART SERIAL UART
SPI
I2C-BUS
REGISTER BANK
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Fig 2. Detailed block diagram of the PN512
001aak602
DVDD
NRSTPD
IRQ
MFIN
MFOUT
SVDD
OSCIN
OSCOUT
VMID AUX1 AUX2 RX TVSS TX1 TX2 TVDD
16 19 20 17 10, 14 11 13 12
DVSS
AVDD
SDA/NSS/RX EA I2C PVDD PVSS
24 32 1 2 5
D1/ADR_5
25
D2/ADR_4
26
D3/ADR_3
27
D4/ADR_2
28
D5/ADR_1/
SCK/DTRQ
29
D6/ADR_0/
MOSI/MX
30
D7/SCL/
MISO/TX
31
AVSS
3
6
23
7
8
9
21
22
4
15
18
FIFO CONTROL
MIFARE CLASSIC UNIT
STATE MACHINE
COMMAND REGISTER
PROGRAMABLE TIMER
INTERRUPT CONTROL
CRC16
GENERATION AND CHECK
PARALLEL/SERIAL
CONVERTER
SERIAL DATA SWITCH
TRANSMITTER CONTROL
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING BIT ENCODING
RANDOM NUMBER
GENERATOR
ANALOG TO DIGITAL
CONVERTER
I-CHANNEL
AMPLIFIER
ANALOG TEST
MULTIPLEXOR
AND
DIGITAL TO
ANALOG
CONVERTER
I-CHANNEL
DEMODULATOR
Q-CHANNEL
AMPLIFIER
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
Q-CLOCK
GENERATION
OSCILLATOR
TEMPERATURE
SENSOR
Q-CHANNEL
DEMODULATOR
AMPLITUDE
RATING
REFERENCE
VOLTAGE
64-BYTE FIFO
BUFFER
CONTROL REGISTER
BANK
SPI, UART, I2C-BUS INTERFACE CONTROL
VOLTAGE
MONITOR
AND
POWER ON
DETECT
RESET
CONTROL
POWER-DOWN
CONTROL
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7. Pinning information
7.1 Pinning
Fig 3. Pinning configuration HVQFN32 (SOT617-1)
Fig 4. Pinning configuration HVQFN40 (SOT618-1)
001aan212
PN512
Transparent top view
RX
SIGIN
SIGOUT
AVSS
NRSTPD AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
A1 ALE
SVDD
TVSS
TX1
TVDD
TX2
TVSS
AVDD
VMID
A0
D7
D6
D5
D4
D3
D2
D1
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
001aan213
PN512
AVSS
NRSTPD
SIGIN
AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
A5 NWR
A4 NRD
A3 ALE
A2 NCS
SIGOUT
SVDD
TVSS
TX1
TVDD
TX2
TVSS
AVDD
VMID
RX
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
terminal 1
index area
Transparent top view
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Fig 5. Pin configuration TFBGA64 (SOT1336-1)
aaa-005873
TFBGA64
Transparent top view
ball A1
index area
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8
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7.2 Pin description
Table 3. Pin description HVQFN32
Pin Symbol Type Description
1 A1 I Address Line
2 PVDD PWR Pad power supply
3 DVDD PWR Digital Power Supply
4 DVSS PWR Digital Ground
5 PVSS PWR Pad power supply ground
6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
7 SIGIN I Communication Interface Input: accepts a digital, serial data stream
8 SIGOUT O Communication Interface Output: delivers a serial data stream
9 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
15 AVDD PWR Analog Power Supply
16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
17 RX I Receiver Input
18 AVSS PWR Analog Ground
19 AUX1 O Auxiliary Outputs: These pins are used for testing.
20 AUX2 O
21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
23 IRQ O Interrupt Request: output to signal an interrupt event
24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: An 8-bit parallel interface is not available.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
32 A0 I Address Line
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Table 4. Pin description HVQFN40
Pin Symbol Type Description
1 to 4 A2 to A5 I Address Line
5 PVDD PWR Pad power supply
6 DVDD PWR Digital Power Supply
7 DVSS PWR Digital Ground
8 PVSS PWR Pad power supply ground
9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
10 SIGIN I Communication Interface Input: accepts a digital, serial data stream
11 SIGOUT O Communication Interface Output: delivers a serial data stream
12 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
18 AVDD PWR Analog Power Supply
19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
20 RX I Receiver Input
21 AVSS PWR Analog Ground
22 AUX1 O Auxiliary Outputs: These pins are used for testing.
23 AUX2 O
24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
26 IRQ O Interrupt Request: output to signal an interrupt event
27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register
28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7)
29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512
31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
39 to 40 A0 to A1 I Address Line
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Table 5. Pin description TFBGA64
Pin Symbol Type Description
A1 to A5, A8,
B3, B4, B8, E1
PVSS PWR Pad power supply ground
A6 D4 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
A7 D2 I/O
B1 PVDD PWR Pad power supply
B2 A0 I Address Line
B5 D5 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
B6 D3 I/O
B7 D1 I/O
C1 DVDD PWR Digital Power Supply
C2 A1 I Address Line
C3 D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
C4 D6 I/O
C5 IRQ O Interrupt Request: output to signal an interrupt event
C6 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
C7, C8, D6, D8,
E6, E8, F7, G8,
H8
AVSS PWR Analog Ground
D1 DVSS PWR Digital Ground
D2 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off,
the oscillator is inhibited, and the input pads are disconnected from the outside
world. With a positive edge on this pin the internal reset phase starts.
D3 to D5, E3 to
E5, F3, F4,
G1 to G6,
H1, H2, H6
TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
D7 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
E2 SIGIN I Communication Interface Input: accepts a digital, serial data stream
E7 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin
is also the input for an externally generated clock (fosc = 27.12MHz).
F1 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
F2 SIGOUT O Communication Interface Output: delivers a serial data stream
F5 AUX1 O Auxiliary Outputs: These pins are used for testing.
F6 AUX2 O
F8 RX I Receiver Input
G7 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
H3 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
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H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
H7 AVDD PWR Analog Power Supply
Table 5. Pin description TFBGA64
Pin Symbol Type Description
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8. Functional description
The PN512 transmission module supports the Read/Write mode for
ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and
modulation protocols.
PN512 transceiver IC supports the following operating modes:
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
The modes support different transfer speeds and modulation schemes. The following
chapters will explain the different modes in detail.
Note: All indicated modulation indices and modes in this chapter are system parameters.
This means that beside the IC settings a suitable antenna tuning is required to achieve the
optimum performance.
8.1 ISO/IEC 14443 A/MIFARE functionality
The physical level communication is shown in Figure 7.
The physical parameters are described in Table 4.
Fig 6. PN512 Read/Write mode
001aan218
BATTERY
reader/writer
contactless card
MICROCONTROLLER
PN512 ISO/IEC 14443 A CARD
Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram
Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer
Communication
direction
Signal type Transfer speed
106 kBd 212 kBd 424 kBd
Reader to card (send
data from the PN512
to a card)
reader side
modulation
100 % ASK 100 % ASK 100 % ASK
bit encoding modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s)
(1)
(2)
001aan219
PN512
ISO/IEC 14443 A CARD
ISO/IEC 14443 A
READER
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The PN512’s contactless UART and dedicated external host must manage the complete
ISO/IEC 14443 A/MIFARE protocol. Figure 8 shows the data coding and framing
according to ISO/IEC 14443 A/MIFARE.
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed. Automatic
parity generation can be switched off using the ManualRCVReg register’s ParityDisable
bit.
8.2 ISO/IEC 14443 B functionality
The PN512 reader IC fully supports international standard ISO 14443 which includes
communication schemes ISO 14443 A and ISO 14443 B.
Refer to the ISO 14443 reference documents Identification cards - Contactless integrated
circuit cards - Proximity cards (parts 1 to 4).
Remark: NXP Semiconductors does not offer a software library to enable design-in of the
ISO 14443 B protocol.
Card to reader
(PN512 receives data
from a card)
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
bit encoding Manchester
encoding
BPSK BPSK
Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued
Communication
direction
Signal type Transfer speed
106 kBd 212 kBd 424 kBd
Fig 8. Data coding and framing according to ISO/IEC 14443 A
001aak585
ISO/IEC 14443 A framing at 106 kBd
8-bit data 8-bit data 8-bit data
odd
parity
odd
parity
start
odd
start bit is 1 parity
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
8-bit data 8-bit data 8-bit data
odd
parity
odd
parity
start
even
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the frame
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8.3 FeliCa reader/writer functionality
The FeliCa mode is the general reader/writer to card communication scheme according to
the FeliCa specification. The following diagram describes the communication on a
physical level, the communication overview describes the physical parameters.
The contactless UART of PN512 and a dedicated external host controller are required to
handle the complete FeliCa protocol.
8.3.1 FeliCa framing and coding
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and databytes
to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the
PN512 automatically and must not be written to the FIFO by the host controller. The
PN512 performs internally the CRC calculation and adds the result to the data frame.
Example for FeliCa CRC Calculation:
Fig 9. FeliCa reader/writer communication diagram
Table 7. Communication overview for FeliCa reader/writer
Communication
direction
FeliCa FeliCa Higher
transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
PN512 card Modulation on reader side 8-30 % ASK 8-30 % ASK
bit coding Manchester Coding Manchester Coding
Bitlength (64/13.56) s (32/13.56) s
card PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK
bit coding Manchester coding Manchester coding
2. PICC to PCD, > 12 % ASK loadmodulation
Manchester coded, baudrate 212 to 424 kbaud
1. PCD to PICC, 8-30 % ASK
Manchester coded, baudrate 212 to 424 kbaud
001aan214
PN512
FeliCa CARD
(PICC)
Felica READER
(PCD)
Table 8. FeliCa framing and coding
Preamble Sync Len n-Data CRC
00h 00h 00h 00h 00h 00h B2h 4Dh
Table 9. Start value for the CRC Polynomial: (00h), (00h)
Preamble Sync Len 2 Data Bytes CRC
00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35h
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8.4 NFCIP-1 mode
The NFCIP-1 communication differentiates between an active and a Passive
Communication mode.
• Active Communication mode means both the initiator and the target are using their
own RF field to transmit data.
• Passive Communication mode means that the target answers to an initiator command
in a load modulation scheme. The initiator is active in terms of generating the RF field.
• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication
• Target: responds to initiator command either in a load modulation scheme in Passive
Communication mode or using a self generated and self modulated RF field for Active
Communication mode.
In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive
Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
Fig 10. NFCIP-1 mode
001aan215
BATTERY
initiator: active target:
passive or active
MICROCONTROLLER
PN512
BATTERY
MICROCONTROLLER
PN512
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8.4.1 Active communication mode
Active communication mode means both the initiator and the target are using their own
RF field to transmit data.
The contactless UART of PN512 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN512 supports these transfer speeds only with dedicated external circuits.
Fig 11. Active communication mode
Table 10. Communication overview for Active communication mode
Communication
direction
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,
3.39 Mbit/s
Initiator Target According to
ISO/IEC 14443A
100 % ASK,
Modified
Miller Coded
According to FeliCa, 8-30 %
ASK Manchester Coded
digital capability to handle
Target Initiator this communication
host
NFC INITIATOR
powered to
generate RF field
1. initiator starts communication at
selected transfer speed
Initial command
response
2. target answers at
the same transfer speed
host NFC INITIATOR
powered for digital
processing
host
host
NFC TARGET
NFC TARGET
powered for
digital processing
powered to
generate RF field
001aan216
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8.4.2 Passive communication mode
Passive Communication mode means that the target answers to an initiator command in a
load modulation scheme. The initiator is active meaning generating the RF field.
The contactless UART of PN512 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN512 supports these transfer speeds only with dedicated external circuits.
Fig 12. Passive communication mode
Table 11. Communication overview for Passive communication mode
Communication
direction
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,
3.39 Mbit/s
Initiator Target According to
ISO/IEC 14443A
100 % ASK,
Modified
Miller Coded
According to FeliCa, 8-30
% ASK Manchester Coded
digital capability to handle
this communication
Target Initiator According to
ISO/IEC 14443A
subcarrier load
modulation,
Manchester Coded
According to FeliCa, > 12 %
ASK Manchester Coded
host
NFC INITIATOR
powered to
generate RF field
1. initiator starts communication
at selected transfer speed
2. targets answers using
load modulated data
at the same transfer speed
host
NFC TARGET
powered for
digital processing
001aan217
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8.4.3 NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive Communication mode is defined
in the NFCIP-1 standard.
8.4.4 NFCIP-1 protocol support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is
according to the following policy:
• Speed shall not be changed while continuum data exchange in a transaction.
• Transaction includes initialization and anticollision methods and data exchange (in
continuous way, meaning no interruption by another transaction).
In order not to disturb current infrastructure based on 13.56 MHz general rules to start
NFCIP-1 communication are defined in the following way.
1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off.
2. The RF level detector is active.
3. Only if application requires the NFCIP-1 device shall switch to Initiator mode.
4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level
detector during a time of TIDT.
5. The initiator performs initialization according to the selected mode.
8.4.5 MIFARE Card operation mode
Table 12. Framing and coding overview
Transfer speed Framing and Coding
106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme
212 kbit/s According to the FeliCa scheme
424 kbit/s According to the FeliCa scheme
Table 13. MIFARE Card operation mode
Communication
direction
ISO/IEC 14443A/
MIFARE
MIFARE Higher transfer speeds
transfer speed 106 kbit/s 212 kbit/s 424 kbit/s
reader/writer
PN512
Modulation on
reader side
100 % ASK 100 % ASK 100 % ASK
bit coding Modified Miller Modified Miller Modified Miller
Bitlength (128/13.56) s (64/13.56) s (32/13.56) s
PN512 reader/
writer
Modulation on
PN512 side
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
bit coding Manchester coding BPSK BPSK
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8.4.6 FeliCa Card operation mode
9. PN512 register SET
9.1 PN512 registers overview
Table 14. FeliCa Card operation mode
Communication
direction
FeliCa FeliCa Higher
transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
reader/writer
PN512
Modulation on reader side 8-30 % ASK 8-30 % ASK
bit coding Manchester Coding Manchester Coding
Bitlength (64/13.56) s (32/13.56) s
PN512 reader/
writer
Load modulation on PN512
side
> 12 % ASK load
modulation
> 12 % ASK load
modulation
bit coding Manchester coding Manchester coding
Table 15. PN512 registers overview
Addr
(hex)
Register Name Function
Page 0: Command and Status
0 PageReg Selects the register page
1 CommandReg Starts and stops command execution
2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests
3 DivlEnReg Controls bits to enable and disable the passing of Interrupt Requests
4 ComIrqReg Contains Interrupt Request bits
5 DivIrqReg Contains Interrupt Request bits
6 ErrorReg Error bits showing the error status of the last command executed
7 Status1Reg Contains status bits for communication
8 Status2Reg Contains status bits of the receiver and transmitter
9 FIFODataReg In- and output of 64 byte FIFO-buffer
A FIFOLevelReg Indicates the number of bytes stored in the FIFO
B WaterLevelReg Defines the level for FIFO under- and overflow warning
C ControlReg Contains miscellaneous Control Registers
D BitFramingReg Adjustments for bit oriented frames
E CollReg Bit position of the first bit collision detected on the RF-interface
F RFU Reserved for future use
Page 1: Command
0 PageReg Selects the register page
1 ModeReg Defines general modes for transmitting and receiving
2 TxModeReg Defines the data rate and framing during transmission
3 RxModeReg Defines the data rate and framing during receiving
4 TxControlReg Controls the logical behavior of the antenna driver pins TX1 and TX2
5 TxAutoReg Controls the setting of the antenna drivers
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6 TxSelReg Selects the internal sources for the antenna driver
7 RxSelReg Selects internal receiver settings
8 RxThresholdReg Selects thresholds for the bit decoder
9 DemodReg Defines demodulator settings
A FelNFC1Reg Defines the length of the valid range for the receive package
B FelNFC2Reg Defines the length of the valid range for the receive package
C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC
target mode at 106 kbit
D ManualRCVReg Allows manual fine tuning of the internal receiver
E TypeBReg Configure the ISO/IEC 14443 type B
F SerialSpeedReg Selects the speed of the serial UART interface
Page 2: CFG
0 PageReg Selects the register page
1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation
2
3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation, when the driver is switched off
4 ModWidthReg Controls the setting of the ModWidth
5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit
6 RFCfgReg Configures the receiver gain and RF level
7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation when the drivers are switched on
8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during times of no modulation
9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during modulation
A TModeReg
TPrescalerReg
Defines settings for the internal timer
B
C TReloadReg Describes the 16-bit timer reload value
D
E TCounterValReg Shows the 16-bit actual timer value
F
Page 3: TestRegister
0 PageReg selects the register page
1 TestSel1Reg General test signal configuration
2 TestSel2Reg General test signal configuration and PRBS control
3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial
interfaces only)
4 TestPin
ValueReg
Defines the values for the 8-bit parallel bus when it is used as I/O bus
5 TestBusReg Shows the status of the internal testbus
6 AutoTestReg Controls the digital selftest
Table 15. PN512 registers overview …continued
Addr
(hex)
Register Name Function
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9.1.1 Register bit behavior
Depending on the functionality of a register, the access conditions to the register can vary.
In principle bits with same behavior are grouped in common registers. In Table 16 the
access conditions are described.
7 VersionReg Shows the version
8 AnalogTestReg Controls the pins AUX1 and AUX2
9 TestDAC1Reg Defines the test value for the TestDAC1
A TestDAC2Reg Defines the test value for the TestDAC2
B TestADCReg Shows the actual value of ADC I and Q
C-F RFT Reserved for production tests
Table 15. PN512 registers overview …continued
Addr
(hex)
Register Name Function
Table 16. Behavior of register bits and its designation
Abbreviation Behavior Description
r/w read and write These bits can be written and read by the -Controller. Since they
are used only for control means, there content is not influenced by
internal state machines, e.g. the PageSelect-Register may be
written and read by the -Controller. It will also be read by internal
state machines, but never changed by them.
dy dynamic These bits can be written and read by the -Controller.
Nevertheless, they may also be written automatically by internal
state machines, e.g. the Command-Register changes its value
automatically after the execution of the actual command.
r read only These registers hold bits, which value is determined by internal
states only, e.g. the CRCReady bit can not be written from
external but shows internal states.
w write only Reading these registers returns always ZERO.
RFU - These registers are reserved for future use.
In case of a PN512 Version version 2.0 (VersionReg = 82h) a
read access to these registers returns always the value “0”.
Nevertheless this is not guaranteed for future chips versions
where the value is undefined. In case of a write access, it is
recommended to write always the value “0”.
RFT - These registers are reserved for production tests and shall not be
changed.
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9.2 Register description
9.2.1 Page 0: Command and status
9.2.1.1 PageReg
Selects the register page.
9.2.1.2 CommandReg
Starts and stops command execution.
Table 17. PageReg register (address 00h); reset value: 00h, 0000000b
7 6 5 4 3 2 1 0
UsePage Select 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
Table 18. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).
Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 RcvOff Power Down Command
Access
Rights
RFU RFU r/w dy dy dy dy dy
Table 20. Description of CommandReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 RcvOff Set to logic 1, the analog part of the receiver is switched off.
4 PowerDown Set to logic 1, Soft Power-down mode is entered.
Set to logic 0, the PN512 starts the wake up procedure. During this
procedure this bit still shows a 1. A 0 indicates that the PN512 is ready
for operations; see Section 16.2 “Soft power-down mode”.
Note: The bit Power Down cannot be set, when the command
SoftReset has been activated.
3 to 0 Command Activates a command according to the Command Code. Reading this
register shows, which command is actually executed (see Section 19.3
“PN512 command overview”).
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9.2.1.3 CommIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 22. Description of CommIEnReg bits
Bit Symbol Description
7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the
register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq.
In combination with bit IRqPushPull in register DivIEnReg, the default value
of 1 ensures, that the output level on pin IRQ is 3-state.
6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be
propagated to pin IRQ.
5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be
propagated to pin IRQ.
4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to
pin IRQ.
3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be
propagated to pin IRQ.
2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be
propagated to pin IRQ.
1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated
to pin IRQ.
0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be
propagated to pin IRQ.
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9.2.1.4 DivIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn
Access
Rights
r/w RFU RFU r/w r/w r/w r/w r/w
Table 24. Description of DivIEnReg bits
Bit Symbol Description
7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
6 to 5 - Reserved for future use.
4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ.
3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be
propagated to pin IRQ.
2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to
be propagated to pin IRQ.
0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to
be propagated to pin IRQ.
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9.2.1.5 CommIRqReg
Contains Interrupt Request bits.
Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b
7 6 5 4 3 2 1 0
Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Access
Rights
w dy dy dy dy dy dy dy
Table 26. Description of CommIRqReg bits
All bits in the register CommIRqReg shall be cleared by software.
Bit Symbol Description
7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out.
5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream.
If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
-Controller does not set bit IdleIRq.
3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to
LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit
Set1.
1 ErrIRq Set to logic 1 if any error bit in the Error Register is set.
0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.
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9.2.1.6 DivIRqReg
Contains Interrupt Request bits
Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb
7 6 5 4 3 2 1 0
Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq
Access
Rights
w RFU RFU dy dy dy dy dy
Table 28. Description of DivIRqReg bits
All bits in the register DivIRqReg shall be cleared by software.
Bit Symbol Description
7 Set2 Set to logic 1, Set2 defines that the marked bits in the register
DivIRqReg are set.
Set to logic 0, Set2 defines, that the marked bits in the register
DivIRqReg are cleared
6 to 5 - Reserved for future use.
4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “S2C interface
support”. This interrupt is set when either a rising or falling signal edge
is detected.
3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode
detector.
Note: The Data mode detector can only be activated by the AutoColl
command and is terminated automatically having detected the
Communication mode.
Note: The Data mode detector is automatically restarted after each RF
Reset.
2 CRCIRq Set to logic 1, when the CRC command is active and all data are
processed.
1 RFOnIRq Set to logic 1, when an external RF field is detected.
0 RFOffIRq Set to logic 1, when a present external RF field is switched off.
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9.2.1.7 ErrorReg
Error bit register showing the error status of the last command executed.
[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.
Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Access
Rights
r r r r r r r r
Table 30. Description of ErrorReg bits
Bit Symbol Description
7 WrErr Set to logic 1, when data is written into FIFO by the host controller
during the AutoColl command or MFAuthent command or if data is
written into FIFO by the host controller during the time between
sending the last bit on the RF interface and receiving the last bit on the
RF interface.
6 TempErr[1] Set to logic 1, if the internal temperature sensor detects overheating.
In this case, the antenna drivers are switched off automatically.
5 RFErr Set to logic 1, if in Active Communication mode the counterpart does
not switch on the RF field in time as defined in NFCIP-1 standard.
Note: RFErr is only used in Active Communication mode. The bits
RxFraming or the bits TxFraming has to be set to 01 to enable this
functionality.
4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine
(e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer
although the FIFO-buffer is already full.
3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at
receiver start-up phase. This bit is only valid during the bitwise
anticollision at 106 kbit. During communication schemes at 212 and
424 kbit this bit is always set to logic 1.
2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the
CRC calculation fails. It is cleared to 0 automatically at receiver
start-up phase.
1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or
NFCIP-1 communication at 106 kbit.
0 ProtocolErr Set to logic 1, if one out of the following cases occur:
• Set to logic 1 if the SOF is incorrect. It is cleared automatically at
receiver start-up phase. The bit is only valid for 106 kbit in Active
and Passive Communication mode.
• If bit DetectSync in register ModeReg is set to logic 1 during
FeliCa communication or active communication with transfer
speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in
case of a byte length violation.
• During the AutoColl command, bit ProtocolErr is set to logic 1, if
the bit Initiator in register ControlReg is set to logic 1.
• During the MFAuthent Command, bit ProtocolErr is set to logic 1,
if the number of bytes received in one data stream is incorrect.
• Set to logic 1, if the Miller Decoder detects 2 pulses below the
minimum time according to the ISO/IEC 14443A definitions.
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9.2.1.8 Status1Reg
Contains status bits of the CRC, Interrupt and FIFO-buffer.
Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb
7 6 5 4 3 2 1 0
RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert
Access
Rights
r r r r r r r r
Table 32. Description of Status1Reg bits
Bit Symbol Description
7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of
13.56 MHz.
Set to logic 1, if the frequency at the RX pin is in the range
12 MHz < RX pin frequency < 15 MHz.
Note: The value of RFFreqOK is not defined if the external RF
frequency is in the range from 9 to 12 MHz or in the range from
15 to 19 MHz.
6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and
reception the bit CRCOk is undefined (use CRCErr in register
ErrorReg). CRCOk indicates the status of the CRC co-processor,
during calculation the value changes to ZERO, when the calculation is
done correctly, the value changes to ONE.
5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only
valid for the CRC co-processor calculation using the command
CalcCRC.
4 IRq This bit shows, if any interrupt source requests attention (with respect
to the setting of the interrupt enable bits, see register CommIEnReg
and DivIEnReg).
3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will
decrement the TCounterValReg with the next timer clock.
Note: In the gated mode the bit TRunning is set to logic 1, when the
timer is enabled by the register bits. This bit is not influenced by the
gated signal.
2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store
the state of the RF field.
1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
FIFOLength = 60, WaterLevel = 4 HiAlert = 1
FIFOLength = 59, WaterLevel = 4 HiAlert = 0
0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
FIFOLength = 4, WaterLevel = 4 LoAlert = 1
FIFOLength = 5, WaterLevel = 4 LoAlert = 0
HiAlert = 64 – FIFOLength WaterLevel
LoAlert = FIFOLength WaterLevel
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9.2.1.9 Status2Reg
Contains status bits of the Receiver, Transmitter and Data mode detector.
Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TempSensClear I2CForceHS 0 TargetActivated MFCrypto1On Modem State
Access
Rights
r/w r/w RFU dy dy r r r
Table 34. Description of Status2Reg bits
Bit Symbol Description
7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature
is below the alarm limit of 125 C.
6 I2CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the
High-speed mode independent of the I2C protocol. Set to logic 0, the
I2C input filter is set to the used I2C protocol.
5 - Reserved for future use.
4 TargetActivated Set to logic 1 if the Select command or if the Polling command was
answered. Note: This bit can only be set during the AutoColl
command in Passive Communication mode.
Note: This bit is cleared automatically by switching off the external
RF field.
3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and
therefore all data communication with the card is encrypted.
This bit can only be set to logic 1 by a successful execution of the
MFAuthent Command. This bit is only valid in Reader/Writer mode
for MIFARE cards. This bit shall be cleared by software.
2 to 0 Modem State ModemState shows the state of the transmitter and receiver state
machines.
Value Description
000 IDLE
001 Wait for StartSend in register BitFramingReg
010 TxWait: Wait until RF field is present, if the bit TxWaitRF is
set to logic 1. The minimum time for TxWait is defined by the
TxWaitReg register.
011 Sending
100 RxWait: Wait until RF field is present, if the bit RxWaitRF is
set to logic 1. The minimum time for RxWait is defined by the
RxWaitReg register.
101 Wait for data
110 Receiving
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9.2.1.10 FIFODataReg
In- and output of 64 byte FIFO-buffer.
9.2.1.11 FIFOLevelReg
Indicates the number of bytes stored in the FIFO.
Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
FIFOData
Access
Rights
dy dy dy dy dy dy dy dy
Table 36. Description of FIFODataReg bits
Bit Symbol Description
7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The
FIFO-buffer acts as parallel in/parallel out converter for all serial data
stream in- and outputs.
Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FlushBuffer FIFOLevel
Access
Rights
w r r r r r r r
Table 38. Description of FIFOLevelReg bits
Bit Symbol Description
7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the register ErrReg immediately.
Reading this bit will always return 0.
6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the
FIFODataReg increments, reading decrements the FIFOLevel.
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9.2.1.12 WaterLevelReg
Defines the level for FIFO under- and overflow warning.
9.2.1.13 ControlReg
Miscellaneous control bits.
Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b
7 6 5 4 3 2 1 0
0 0 WaterLevel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 40. Description of WaterLevelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or
underflow:
The bit HiAlert in Status1Reg is set to logic 1, if the remaining number
of bytes in the FIFO-buffer space is equal or less than the defined
number of WaterLevel bytes.
The bit LoAlert in Status1Reg is set to logic 1, if equal or less than
WaterLevel bytes are in the FIFO.
Note: For the calculation of HiAlert and LoAlert see Table 31
Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits
Access
Rights
w w dy r/w RFU r r r
Table 42. Description of ControlReg bits
Bit Symbol Description
7 TStopNow Set to logic 1, the timer stops immediately.
Reading this bit will always return 0.
6 TStartNow Set to logic 1 starts the timer immediately.
Reading this bit will always return 0.
5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the
FIFO.
Afterwards the bit is cleared automatically
4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target
3 - Reserved for future use.
2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the
whole byte is valid.
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9.2.1.14 BitFramingReg
Adjustments for bit oriented frames.
Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
StartSend RxAlign 0 TxLastBits
Access
Rights
w r/w r/w r/w RFU r/w r/w r/w
Table 44. Description of BitFramingReg bits
Bit Symbol Description
7 StartSend Set to logic 1, the transmission of data starts.
This bit is only valid in combination with the Transceive command.
6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position
for the first bit received to be stored in the FIFO. Further received bits are
stored at the following bit positions.
Example:
RxAlign = 0: the LSB of the received bit is stored at bit 0, the second
received bit is stored at bit position 1.
RxAlign = 1: the LSB of the received bit is stored at bit 1, the second
received bit is stored at bit position 2.
RxAlign = 7: the LSB of the received bit is stored at bit 7, the second
received bit is stored in the following byte at bit position 0.
This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive
Communication mode. In all other modes it shall be set to logic 0.
3 - Reserved for future use.
2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the
number of bits of the last byte that shall be transmitted. A 000 indicates
that all bits of the last byte shall be transmitted.
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9.2.1.15 CollReg
Defines the first bit collision detected on the RF interface.
Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb
7 6 5 4 3 2 1 0
Values
AfterColl
0 CollPos
NotValid
CollPos
Access
Rights
r/w RFU r r r r r r
Table 46. Description of CollReg bits
Bit Symbol Description
7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a
collision. This bit shall only be used during bitwise anticollision at
106 kbit, otherwise it shall be set to logic 1.
6 - Reserved for future use.
5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the
Collision is out of the range of bits CollPos. This bit shall only be
interpreted in Passive Communication mode at 106 kbit or
ISO/IEC 14443A/MIFARE Reader/Writer mode.
4 to 0 CollPos These bits show the bit position of the first detected collision in a
received frame, only data bits are interpreted.
Example:
00h indicates a bit collision in the 32th bit
01h indicates a bit collision in the 1st bit
08h indicates a bit collision in the 8th bit
These bits shall only be interpreted in Passive Communication mode
at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit
CollPosNotValid is set to logic 0.
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9.2.2 Page 1: Communication
9.2.2.1 PageReg
Selects the register page.
Table 47. PageReg register (address 10h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePage Select 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
Table 48. Description of PageReg bits
Bit Symbol Description
7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).
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9.2.2.2 ModeReg
Defines general mode settings for transmitting and receiving.
Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b
7 6 5 4 3 2 1 0
MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 50. Description of ModeReg bits
Bit Symbol Description
7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB
first and the CRCResultMSB and the CRCResultLSB in the
CRCResultReg register are bit reversed.
Note: During RF communication this bit is ignored.
6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before
the receiver is activated and F0h is added as a Sync-byte for
transmission.
This bit is only valid for 106 kbit during NFCIP-1 data exchange
protocol.
In all other modes it shall be set to logic 0.
5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for
NFCIP-1 can only be started, if an RF field is generated.
4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field
is detected in Target mode for NFCIP-1 or in Card Communication
mode.
3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the
polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN
pin is active low.
Note: The internal envelope signal is coded active low.
Note: Changing this bit will generate a SiginActIRq event.
2 ModeDetOff Set to logic 1, the internal mode detector is switched off.
Note: The mode detector is only active during the AutoColl command.
1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command
CalCRC.
Note: During any communication, the preset values is selected
automatically according to the definition in the bits RxMode and
TxMode.
Value Description
00 0000
01 6363
10 A671
11 FFFF
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9.2.2.3 TxModeReg
Defines the data rate and framing during transmission.
Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TxCRCEn TxSpeed InvMod TxMix TxFraming
Access
Rights
r/w dy dy dy r/w r/w dy dy
Table 52. Description of TxModeReg bits
Bit Symbol Description
7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data
transmission.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 TxSpeed Defines the bit rate while data transmission.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 InvMod Set to logic 1, the modulation for transmitting data is inverted.
2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder
(see Section 12.6 “S2C interface support”).
1 to 0 TxFraming Defines the framing used for data transmission.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication mode
106 kbit
01 Active Communication mode
10 FeliCa and Passive communication mode 212 and 424 kbit
11 ISO/IEC 14443B
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9.2.2.4 RxModeReg
Defines the data rate and framing during reception.
Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming
Access
Rights
r/w dy dy dy r/w r/w dy dy
Table 54. Description of RxModeReg bits
Bit Symbol Description
7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 RxSpeed Defines the bit rate while data transmission.
The PN512’s analog part handles only transfer speeds up to 424 kbit
internally, the digital UART handles the higher transfer speeds as well.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits
received) will be ignored. The receiver will remain active.
For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non
valid datastream.
2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame.
Set to logic 1, it is possible to receive more than one data frame. Having
set this bit, the receive and transceive commands will not terminate
automatically. In this case the multiple receiving can only be deactivated
by writing any command (except the Receive command) to the
CommandReg register or by clearing the bit by the host controller.
At the end of a received data stream an error byte is added to the FIFO.
The error byte is a copy of the ErrorReg register.
The behaviour for version 1.0 is described in Section 21 “Errata sheet”
on page 109.
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9.2.2.5 TxControlReg
Controls the logical behavior of the antenna driver pins Tx1 and Tx2.
1 to 0 RxFraming Defines the expected framing for data reception.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication
mode 106 kbit
01 Active Communication mode
10 FeliCa and Passive Communication mode 212 and 424 kbit
11 ISO/IEC 14443B
Table 54. Description of RxModeReg bits
Bit Symbol Description
Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
InvTx2RF
On
InvTx1RF
On
InvTx2RF
Off
InvTx1RF
Off
Tx2CW CheckRF Tx2RF
En
Tx1RF
En
Access
Rights
r/w r/w r/w r/w r/w w r/w r/w
Table 56. Description of TxControlReg bits
Bit Symbol Description
7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2
is enabled.
6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1
is enabled.
5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2
is disabled.
4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1
is disabled.
3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the
un-modulated 13.56 MHz energy carrier.
Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy
carrier.
2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF
field is detected. Only valid when using in combination with bit
Tx2RFEn or Tx1RFEn
1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz
energy carrier modulated by the transmission data.
0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz
energy carrier modulated by the transmission data.
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9.2.2.6 TxAutoReg
Controls the settings of the antenna driver.
Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
AutoRF
OFF
Force100
ASK
Auto
WakeUp
0 CAOn InitialRF
On
Tx2RFAut
oEn
Tx1RFAuto
En
Access
Rights
r/w r/w r/w RFU r/w r/w r/w r/w
Table 58. Description of TxAutoReg bits
Bit Symbol Description
7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last
data bit has been transmitted as defined in the NFCIP-1.
6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation
independent of the setting in register ModGsPReg.
5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by
the RF level detector.
4 - Reserved for future use.
3 CAOn Set to logic 1, the collision avoidance is activated and internally the
value n is set in accordance to the NFCIP-1 Standard.
2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit
InitialRFOn is cleared automatically, if the RF is switched on.
Note: The driver, which should be switched on, has to be enabled by
bit Tx2RFAutoEn or bit Tx1RFAutoEn.
1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field
is switched off according to the time TADT. If the bits InitialRFOn and
Tx2RFAutoEn are set to logic 1, Tx2 is switched on if no external RF
field is detected during the time TIDT.
Note: The times TADT and TIDT are defined in the NFC IP-1 standard
(ISO/IEC 18092).
0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field
is switched off according to the time TADT. If the bit InitialRFOn and
Tx1RFAutoEn are set to logic 1, Tx1 is switched on if no external RF
field is detected during the time TIDT.
Note: The times TADT and TIDT are defined in the NFC IP-1 standard
(ISO/IEC 18092).
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9.2.2.7 TxSelReg
Selects the sources for the analog part.
Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b
7 6 5 4 3 2 1 0
0 0 DriverSel SigOutSel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 60. Description of TxSelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 4 DriverSel Selects the input of driver Tx1 and Tx2.
Value Description
00 Tristate
Note: In soft power down the drivers are only in Tristate mode
if DriverSel is set to Tristate mode.
01 Modulation signal (envelope) from the internal coder
10 Modulation signal (envelope) from SIGIN
11 HIGH
Note: The HIGH level depends on the setting of InvTx1RFOn/
InvTx1RFOff and InvTx2RFOn/InvTx2RFOff.
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3 to 0 SigOutSel Selects the input for the SIGOUT Pin.
Value Description
0000 Tristate
0001 Low
0010 High
0011 TestBus signal as defined by bit TestBusBitSel in register
TestSel1Reg.
0100 Modulation signal (envelope) from the internal coder
0101 Serial data stream to be transmitted
0110 Output signal of the receiver circuit (card modulation signal
regenerated and delayed). This signal is used as data output
signal for SAM interface connection using 3 lines.
Note: To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
Note: Do not use this setting in MIFARE mode. Manchester
coding as data collisions will not be transmitted on the
SIGOUT line.
0111 Serial data stream received.
Note: Do not use this setting in MIFARE mode. Miller coding
parameters as the bit length can vary.
1000-1011 FeliCa Sam modulation
1000 RX*
1001 TX
1010 Demodulator comparator output
1011 RFU
Note: * To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
1100-1111 MIFARE Sam modulation
1100 RX* with RF carrier
1101 TX with RF carrier
1110 RX with RF carrier un-filtered
1111 RX envelope un-filtered
Note: *To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
Table 60. Description of TxSelReg bits …continued
Bit Symbol Description
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9.2.2.8 RxSelReg
Selects internal receiver settings.
9.2.2.9 RxThresholdReg
Selects thresholds for the bit decoder.
Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b
7 6 5 4 3 2 1 0
UartSel RxWait
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 62. Description of RxSelReg bits
Bit Symbol Description
7 to 6 UartSel Selects the input of the contactless UART
Value Description
00 Constant Low
01 Envelope signal at SIGIN
10 Modulation signal from the internal analog part
11 Modulation signal from SIGIN pin. Only valid for transfer
speeds above 424 kbit
5 to 0 RxWait After data transmission, the activation of the receiver is delayed for
RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX
is ignored. This parameter is ignored by the Receive command. All
other commands (e.g. Transceive, Autocoll, MFAuthent) use this
parameter. Depending on the mode of the PN512, the counter starts
different. In Passive Communication mode the counter starts with the
last modulation pulse of the transmitted data stream. In Active
Communication mode the counter starts immediately after the external
RF field is switched on.
Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b
7 6 5 4 3 2 1 0
MinLevel 0 CollLevel
Access
Rights
r/w r/w r/w r/w RFU r/w r/w r/w
Table 64. Description of RxThresholdReg bits
Bit Symbol Description
7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be
accepted. If the signal strength is below this level, it is not evaluated.
3 - Reserved for future use.
2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be
reached by the weaker half-bit of the Manchester-coded signal to
generate a bit-collision relatively to the amplitude of the stronger half-bit.
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9.2.2.10 DemodReg
Defines demodulator settings.
Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b
7 6 5 4 3 2 1 0
AddIQ FixIQ TPrescal
Even
TauRcv TauSync
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 66. Description of DemodReg bits
Bit Symbol Description
7 to 6 AddIQ Defines the use of I and Q channel during reception
Note: FixIQ has to be set to logic 0 to
enable the following settings.
Value Description
00 Select the stronger channel
01 Select the stronger and freeze the selected during communication
10 combines the I and Q channel
11 Reserved
5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to
I channel.
If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to
Q channel.
NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ
set to X0 is rewired.
4 TPrescalE
ven
If set to logic 0 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 1).
If set to logic 1 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 2).
(Default TPrescalEven is logic 0)
The behaviour for the version 1.0 is described in Section 21 “Errata
sheet” on page 109.
3 to 2 TauRcv Changes the time constant of the internal during data reception.
Note: If set to 00, the PLL is frozen during data reception.
1 to 0 TauSync Changes the time constant of the internal PLL during burst.
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9.2.2.11 FelNFC1Reg
Defines the length of the FeliCa Sync bytes and the minimum length of the received
packet.
Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FelSyncLen DataLenMin
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 68. Description of FelNFC1Reg bits
Bit Symbol Description
7 to 6 FelSyncLen Defines the length of the Sync bytes.
Value Sync- bytes in hex
00 B2 4D
01 00 B2 4D
10 00 00 B2 4D
11 00 00 00 B2 4D
5 to 0 DataLenMin These bits define the minimum length of the accepted packet length:
DataLenMin * 4 data packet length
This parameter is ignored at 106 kbit if the bit DetectSync in register
ModeReg is set to logic 0. If a received data packet is shorter than the
defined DataLenMin value, the data packet will be ignored.
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9.2.2.12 FelNFC2Reg
Defines the maximum length of the received packet.
Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
WaitForSelected ShortTimeSlot DataLenMax
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 70. Description of FelNFC2Reg bits
Bit Symbol Description
7 WaitForSelected Set to logic 1, the AutoColl command is only terminated
automatically when:
1. A valid command has been received after performing a valid
Select procedure according ISO/IEC 14443A.
2. A valid command has been received after performing a valid
Polling procedure according to the FeliCa specification.
Note: If this bit is set, no active communication is possible.
Note: Setting this bit reduces the host controller interaction in case
of a communication to another device in the same RF field during
Passive Communication mode.
6 ShortTimeSlot Defines the time slot length for Passive Communication mode at
424 kbit. Set to logic 1 a short time slot is used (half of the timeslot
at 212 kbit). Set to logic 0 a long timeslot is used (equal to the
timeslot for 212 kbit).
5 to 0 DataLenMax These bits define the maximum length of the accepted packet
length: DataLenMax * 4 data packet length
Note: If set to logic 0 the maximum data length is 256 bytes.
This parameter is ignored at 106 kbit if the bit DetectSync in
register ModeReg is set to logic 0. If a received packet is larger
than the defined DataLenMax value, the packet will be ignored.
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9.2.2.13 MifNFCReg
Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating
mode.
Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b
7 6 5 4 3 2 1 0
SensMiller TauMiller MFHalted TxWait
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 72. Description of MifNFCReg bits
Bit Symbol Description
7 to 5 SensMiller These bits define the sensitivity of the Miller decoder.
4 to 3 TauMiller These bits define the time constant of the Miller decoder.
2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in
Card Operation mode at 106 kbit. This bit is either set by the host
controller or by the internal state machine and indicates that only the
code 52h is accepted as a request command. This bit is cleared
automatically by a RF reset.
1 to 0 TxWait These bits define the minimum response time between receive and
transmit in number of data bits + 7 data bits.
The shortest possible minimum response time is 7 data bits.
(TxWait=0). The minimum response time can be increased by the
number of bits defined in TxWait. The longest minimum response time
is 10 data bits (TxWait = 3).
If a transmission of a frame is started before the minimum response
time is over, the PN512 waits before transmitting the data until the
minimum response time is over.
If a transmission of a frame is started after the minimum response time
is over, the frame is started immediately if the data bit synchronization
is correct. (adjustable with TxBitPhase).
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9.2.2.14 ManualRCVReg
Allows manual fine tuning of the internal receiver.
Remark: For standard applications it is not recommended to change this register settings.
Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
0 FastFilt
MF_SO
Delay
MF_SO
Parity
Disable
LargeBW
PLL
Manual
HPCF
HPFC
Access
Rights
RFU r/w r/w r/w r/w r/w r/w r/w
Table 74. Description of ManualRCVReg bits
Bit Symbol Description
7 - Reserved for future use.
6 FastFilt
MF_SO
If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is
set to Fast mode.
Note: This bit should only set to logic 1, if Millerpulses of less than
400 ns Pulse length are expected. At 106 kBaud the typical value is
3 us.
5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that
in SAM mode the Signal at SIGIN must be 128/fc faster compared to
the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the
RF-Field.
Note: This delay shall only be activated for setting bits SigOutSel to
(1110b) or (1111b) in register TxSelReg.
4 Parity Disable If this bit is set to logic 1, the generation of the Parity bit for
transmission and the Parity-Check for receiving is switched off. The
received Parity bit is handled like a data bit.
3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock
recovery is extended.
2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are
adapted automatically to the receiving mode. Set to logic 1, values of
HPCF are valid.
1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the
internal receiver chain
00 For signals with frequency spectrum down to 106 kHz.
01 For signals with frequency spectrum down to 212 kHz.
10 For signals with frequency spectrum down to 424 kHz.
11 For signals with frequency spectrum down to 848 kHz
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9.2.2.15 TypeBReg
9.2.2.16 SerialSpeedReg
Selects the speed of the serial UART interface.
Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
RxSOF
Req
RxEOF
Req
0 EOFSO
FWidth
NoTxSOF NoTxEOF TxEGT
Access
Rights
r/w r/w RFU r/w r/w r/w r/w r/w
Table 76. Description of TypeBReg bits
Bit Symbol Description
7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting
without SOF is ignored.
If this bit is cleared, a datastream with and without SOF is accepted.
The SOF will be removed and not written into the FIFO.
6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending
without EOF will generate a Protocol-Error. If this bit is cleared, a
datastream with and without EOF is accepted. The EOF will be
removed and not written into the FIFO.
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
5 - Reserved for future use.
4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF
and EOF will have the maximum length defined in ISO/IEC 14443B.
If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and
EOF will have the minimum length defined in ISO/IEC 14443B.
If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in
SOF low = (11etu 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu 8 cycles)/fc
If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in
an incorrect system behavior in respect to ISO specification.
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed.
2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed.
1 to 0 TxEGT These bits define the length of the EGT.
Value Description
00 0 bit
01 1 bit
10 2 bits
11 3 bits
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Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b
7 6 5 4 3 2 1 0
BR_T0 BR_T1
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 78. Description of SerialSpeedReg bits
Bit Symbol Description
7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section
10.3.2 “Selectable UART transfer speeds”.
3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section
10.3.2 “Selectable UART transfer speeds”.
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9.2.3 Page 2: Configuration
9.2.3.1 PageReg
Selects the register page.
9.2.3.2 CRCResultReg
Shows the actual MSB and LSB values of the CRC calculation.
Note: The CRC is split into two 8-bit register.
Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is
not changed.
Table 79. PageReg register (address 20h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePageSelect 0 0 0 0 0 PageSelect
Access Rights r/w RFU RFU RFU RFU RFU r/w r/w
Table 80. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4of the register address).
Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
CRCResultMSB
Access Rights r r r r r r r r
Table 82. Description of CRCResultReg bits
Bit Symbol Description
7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of
the CRCResultReg register. It is valid only if bit CRCReady in
register Status1Reg is set to logic 1.
Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
CRCResultLSB
Access Rights r r r r r r r r
Table 84. Description of CRCResultReg bits
Bit Symbol Description
7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of
the CRCResult register. It is valid only if bit CRCReady in register
Status1Reg is set to logic 1.
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9.2.3.3 GsNOffReg
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the
driver is switched off.
Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b
7 6 5 4 3 2 1 0
CWGsNOff ModGsNOff
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 86. Description of GsNOffReg bits
Bit Symbol Description
7 to 4 CWGsNOff The value of this register defines the conductance of the output
N-driver during times of no modulation.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: The value of the register is only used if the driver is switched
off. Otherwise the bit value CWGsNOn of register GsNOnReg is
used.
Note: This value is used for LoadModulation.
3 to 0 ModGsNOff The value of this register defines the conductance of the output
N-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: The value of the register is only used if the driver is switched
off. Otherwise the bit value ModGsNOn of register GsNOnReg is
used
Note: This value is used for LoadModulation.
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9.2.3.4 ModWidthReg
Controls the modulation width settings.
9.2.3.5 TxBitPhaseReg
Adjust the bitphase at 106 kbit during transmission.
Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b
7 6 5 4 3 2 1 0
ModWidth
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 88. Description of ModWidthReg bits
Bit Symbol Description
7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active
and Passive Communication mode as multiples of the carrier
frequency (ModWidth + 1/fc). The maximum value is half the bit
period.
Acting as a target in Passive Communication mode at 106 kbit or in
Card Operating mode for ISO/IEC 14443A/MIFARE these bits are
used to change the duty cycle of the subcarrier frequency.
The resulting number of carrier periods are calculated according to the
following formulas:
LOW value: #clocksLOW = (ModWidth modulo 8) + 1.
HIGH value: #clocksHIGH = 16-#clocksLOW.
Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b
7 6 5 4 3 2 1 0
RcvClkChange TxBitPhase
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 90. Description of TxBitPhaseReg bits
Bit Symbol Description
7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF
field.
6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock
cycles, which are added to the waiting period before transmitting
data in all communication modes. TXBitPhase is used to adjust the
TX bit synchronization during passive NFCIP-1 communication mode
at 106 kbit and in ISO/IEC 14443A/MIFARE card mode.
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9.2.3.6 RFCfgReg
Configures the receiver gain and RF level detector sensitivity.
Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b
7 6 5 4 3 2 1 0
RFLevelAmp RxGain RFLevel
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 92. Description of RFCfgReg bits
Bit Symbol Description
7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier.
6 to 4 RxGain This register defines the receivers signal voltage gain factor:
Value Description
000 18 dB
001 23 dB
010 18 dB
011 23 dB
100 33 dB
101 38 dB
110 43 dB
111 48 dB
3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see
Section 12.3 “RF level detector”.
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9.2.3.7 GsNOnReg
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the
driver is switched on.
9.2.3.8 CWGsPReg
Defines the conductance of the P-driver during times of no modulation
Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b
7 6 5 4 3 2 1 0
CWGsNOn ModGsNOn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 94. Description of GsNOnReg bits
Bit Symbol Description
7 to 4 CWGsNOn The value of this register defines the conductance of the output
N-driver during times of no modulation. This may be used to regulate
the output power and subsequently current consumption and
operating distance.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: This value is only used if the driver TX1 or TX2 are switched on.
Otherwise the value of the bits CWGsNOff of register GsNOffReg is
used.
3 to 0 ModGsNOn The value of this register defines the conductance of the output
N-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: This value is only used if the driver TX1 or Tx2 are switched on.
Otherwise the value of the bits ModsNOff of register GsNOffReg is
used.
Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 CWGsP
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 96. Description of CWGsPReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 CWGsP The value of this register defines the conductance of the output
P-driver. This may be used to regulate the output power and
subsequently current consumption and operating distance.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
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9.2.3.9 ModGsPReg
Defines the driver P-output conductance during modulation.
[1] If Force100ASK is set to logic 1, the value of ModGsP has no effect.
9.2.3.10 TMode Register, TPrescaler Register
Defines settings for the timer.
Note: The Prescaler value is split into two 8-bit registers
Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 ModGsP
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 98. Description of ModGsPReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 ModGsP[1] The value of this register defines the conductance of the output
P-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TAuto TGated TAutoRestart TPrescaler_Hi
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 100. Description of TModeReg bits
Bit Symbol Description
7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission
in all communication modes at all speeds or when bit InitialRFOn is set to
logic 1 and the RF field is switched on.
In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th
bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is
not set. In all other modes, the timer stops after the 4th bit if the bit
RxMultiple the register RxModeReg is not set.
If RxMultiple is set to logic 1, the timer never stops. In this case the timer
can be stopped by setting the bit TStopNow in register ControlReg to 1.
Set to logic 0 indicates, that the timer is not influenced by the protocol.
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6 to 5 TGated The internal timer is running in gated mode.
Note: In the gated mode, the bit TRunning is 1 when the timer is enabled
by the register bits. This bit does not influence the gating signal.
Value Description
00 Non gated mode
01 Gated by SIGIN
10 Gated by AUX1
11 Gated by A3
4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from
TReloadValue, instead of counting down to zero.
Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set
to logic 1.
3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler.
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 0:
fTimer = 13.56 MHz/(2*TPreScaler+1).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits) (Default TPrescalEven is logic 0)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
fTimer = 13.56 MHz/(2*TPreScaler+2).
For detailed description see Section 15 “Timer unit”. For the behaviour
within version 1.0, see Section 21 “Errata sheet” on page 109.
Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TPrescaler_Lo
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 102. Description of TPrescalerReg bits
Bit Symbol Description
7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler.
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 0:
fTimer = 13.56 MHz/(2*TPreScaler+1).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
fTimer = 13.56 MHz/(2*TPreScaler+2).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
For detailed description see Section 15 “Timer unit”.
Table 100. Description of TModeReg bits …continued
Bit Symbol Description
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9.2.3.11 TReloadReg
Describes the 16-bit long timer reload value.
Note: The Reload value is split into two 8-bit registers.
Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TReloadVal_Hi
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 104. Description of the higher TReloadReg bits
Bit Symbol Description
7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg.
With a start event the timer loads the TReloadVal. Changing this
register affects the timer only at the next start event.
Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TReloadVal_Lo
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 106. Description of lower TReloadReg bits
Bit Symbol Description
7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg.
With a start event the timer loads the TReloadVal. Changing this
register affects the timer only at the next start event.
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9.2.3.12 TCounterValReg
Contains the current value of the timer.
Note: The Counter value is split into two 8-bit register.
9.2.4 Page 3: Test
9.2.4.1 PageReg
Selects the register page.
Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh,
XXXXXXXXb
7 6 5 4 3 2 1 0
TCounterVal_Hi
Access
Rights
r r r r r r r r
Table 108. Description of the higher TCounterValReg bits
Bit Symbol Description
7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits.
Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh,
XXXXXXXXb
7 6 5 4 3 2 1 0
TCounterVal_Lo
Access
Rights
r r r r r r r r
Table 110. Description of lower TCounterValReg bits
Bit Symbol Description
7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits.
Table 111. PageReg register (address 30h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePageSelect 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
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Table 112. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address
A5 and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4 of the register address).
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9.2.4.2 TestSel1Reg
General test signal configuration.
9.2.4.3 TestSel2Reg
General test signal configuration and PRBS control
Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
- - SAMClockSel SAMClkD1 TstBusBitSel
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 114. Description of TestSel1Reg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock
Value Description
00 GND- Sam Clock switched off
01 clock derived by the internal oscillator
10 internal UART clock
11 clock derived by the RF field
3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1.
Note: Only possible if the 8bit parallel interface is not used.
2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT.
Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TstBusFlip PRBS9 PRBS15 TestBusSel
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 116. Description of TestSel2Reg bits
Bit Symbol Description
7 TstBusFlip If set to logic 1, the testbus is mapped to the parallel port by the
following order:
D4, D3, D2, D6, D5, D0, D1. See Section 20 “Testsignals”.
6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS9 mode.
Note: The data transmission of the defined sequence is started by the
send command.
5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS15 mode.
Note: The data transmission of the defined sequence is started by the
send command.
4 to 0 TestBusSel Selects the testbus. See Section 20 “Testsignals”
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9.2.4.4 TestPinEnReg
Enables the pin output driver on the 8-bit parallel bus.
9.2.4.5 TestPinValueReg
Defines the values for the 7-bit parallel port when it is used as I/O.
Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
RS232LineEn TestPinEn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 118. Description of TestPinEnReg bits
Bit Symbol Description
7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are
disabled.
6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface.
Example:
Setting bit 0 to 1 enables D0
Setting bit 5 to 1 enables D5
Note: Only valid if one of serial interfaces is used.
If the SPI interface is used only D0 to D4 can be used. If the serial
UART interface is used and RS232LineEn is set to logic 1 only D0 to
D4 can be used.
Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UseIO TestPinValue
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 120. Description of TestPinValueReg bits
Bit Symbol Description
7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel
port in case one of the serial interfaces is used. The input/output
behavior is defined by TestPinEn in register TestPinEnReg. The value
for the output behavior is defined in the bits TestPinVal.
Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O.
6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each
output has to be enabled by the TestPinEn bits in register
TestPinEnReg.
Note: Reading the register indicates the actual status of the pins D6 -
D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the
register TestPinValueReg is read back.
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9.2.4.6 TestBusReg
Shows the status of the internal testbus.
9.2.4.7 AutoTestReg
Controls the digital selftest.
9.2.4.8 VersionReg
Shows the version.
Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
TestBus
Access Rights r r r r r r r r
Table 122. Description of TestBusReg bits
Bit Symbol Description
7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the
register TestSel2Reg. See Section 20 “Testsignals”.
Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b
7 6 5 4 3 2 1 0
0 AmpRcv EOFSO
FAdjust
- SelfTest
Access Rights RFT r/w RFU RFU r/w r/w r/w r/w
Table 124. Description of bits
Bit Symbol Description
7 - Reserved for production tests.
6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is
performed non-linear. This increases the operating distance in
communication modes at 106 kbit.
Note: Due to the non linearity the effect of the bits MinLevel and
CollLevel in the register RxThreshholdReg are as well non linear.
5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the
Maximum length of SOF and EOF according to ISO/IEC14443B
If set to logic 0 and the EOFSOFwidth is set to 0 will result in the
Minimum length of SOF and EOF according to ISO/IEC14443B
If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in
SOF low = (11 etu 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu 8 cycles)/fc
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
4 - Reserved for future use.
3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest
command in the command register. The selftest is enabled by 1001.
Note: For default operation the selftest has to be disabled by 0000.
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Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
Version
Access Rights r r r r r r r r
Table 126. Description of VersionReg bits
Bit Symbol Description
7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are
described within Section 21 “Errata sheet” on page 109.
82h indicates PN512 version 2.0, which covers also the industrial
version.
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9.2.4.9 AnalogTestReg
Controls the pins AUX1 and AUX2
Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
AnalogSelAux1 AnalogSelAux2
Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Table 128. Description of AnalogTestReg bits
Bit Symbol Description
7 to 4
3 to 0
AnalogSelAux1
AnalogSelAux2
Controls the AUX pin.
Note: All test signals are described in Section 20 “Testsignals”.
Value Description
0000 Tristate
0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2)
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0010 Testsignal Corr1
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0011 Testsignal Corr2
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0100 Testsignal MinLevel
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0101 Testsignal ADC channel I
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0110 Testsignal ADC channel Q
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0111 Testsignal ADC channel I combined with Q
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
1000 Testsignal for production test
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
1001 SAM clock (13.56 MHz)
1010 HIGH
1011 LOW
1100 TxActive
At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High
during Preamble, Sync, Data and CRC.
1101 RxActive
At 106 kbit: High during databit, Parity and CRC.
At 212 and 424 kbit: High during data and CRC.
1110 Subcarrier detected
106 kbit: not applicable
212 and 424 kbit: High during last part of Preamble, Sync data and CRC
1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg.
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9.2.4.10 TestDAC1Reg
Defines the testvalues for TestDAC1.
9.2.4.11 TestDAC2Reg
Defines the testvalue for TestDAC2.
9.2.4.12 TestADCReg
Shows the actual value of ADC I and Q channel.
Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb
7 6 5 4 3 2 1 0
0 0 TestDAC1
Access
Rights
RFT RFU r/w r/w r/w r/w r/w r/w
Table 130. Description of TestDAC1Reg bits
Bit Symbol Description
7 - Reserved for production tests.
6 - Reserved for future use.
5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be
switched to AUX1 by setting AnalogSelAux1 to 0001 in register
AnalogTestReg.
Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb
7 6 5 4 3 2 1 0
0 0 TestDAC2
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 132. Description ofTestDAC2Reg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be
switched to AUX2 by setting AnalogSelAux2 to 0001 in register
AnalogTestReg.
Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
ADC_I ADC_Q
Access
Rights
Table 134. Description of TestADCReg bits
Bit Symbol Description
7 to 4 ADC_I Shows the actual value of ADC I channel.
3 to 0 ADC_Q Shows the actual value of ADC Q channel.
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9.2.4.13 RFTReg
10. Digital interfaces
10.1 Automatic microcontroller interface detection
The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART
interfaces. The PN512 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset. The PN512 identifies the host
interface by sensing the logic levels on the control pins after the reset phase. This is done
using a combination of fixed pin connections. Table 141 shows the different connection
configurations.
Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 136. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 138. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 140. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
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[1] only available in HVQFN 40.
Table 141. Connection protocol for detecting different interface types
Pin Interface type
UART (input) SPI (output) I2C-bus (I/O)
SDA RX NSS SDA
I2C 0 0 1
EA 0 1 EA
D7 TX MISO SCL
D6 MX MOSI ADR_0
D5 DTRQ SCK ADR_1
D4 - - ADR_2
D3 - - ADR_3
D2 - - ADR_4
D1 - - ADR_5
Table 142. Connection scheme for detecting the different interface types
PN512 Parallel Interface Type Serial Interface Types
Separated Read/Write Strobe Common Read/Write Strobe
Pin Dedicated
Address Bus
Multiplexed
Address Bus
Dedicated
Address Bus
Multiplexed
Address Bus
UART SPI I2C
ALE 1 ALE 1 AS RX NSS SDA
A5[1] A5 0 A5 0 0 0 0
A4[1] A4 0 A4 0 0 0 0
A3[1] A3 0 A3 0 0 0 0
A2[1] A2 1 A2 1 0 0 0
A1 A1 1 A1 1 0 0 1
A0 A0 1 A0 0 0 1 EA
NRD[1] NRD NRD NDS NDS 1 1 1
NWR[1] NWR NWR RD/NWR RD/NWR 1 1 1
NCS[1] NCS NCS NCS NCS NCS NCS NCS
D7 D7 D7 D7 D7 TX MISO SCL
D6 D6 D6 D6 D6 MX MOSI ADR_0
D5 D5 AD5 D5 AD5 DTRQ SCK ADR_1
D4 D4 AD4 D4 AD4 - - ADR_2
D3 D3 AD3 D3 AD3 - - ADR_3
D2 D2 AD2 D2 AD2 - - ADR_4
D1 D1 AD1 D1 AD1 - - ADR_5
D0 D0 AD0 D0 AD0 - - ADR_6
Remark: Overview on the pin behavior
Pin behavior Input Output In/Out
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10.2 Serial Peripheral Interface
A serial peripheral interface (SPI compatible) is supported to enable high-speed
communication to the host. The interface can handle data speeds up to 10 Mbit/s. When
communicating with a host, the PN512 acts as a slave, receiving data from the external
host for register settings, sending and receiving data relevant for RF interface
communication.
An interface compatible with SPI enables high-speed serial communication between the
PN512 and a microcontroller. The implemented interface is in accordance with the SPI
standard.
The timing specification is given in Section 26.1 on page 117.
The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be
generated by the master. Data communication from the master to the slave uses the
MOSI line. The MISO line is used to send data from the PN512 to the master.
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI
and MISO lines must be stable on the rising edge of the clock and can be changed on the
falling edge. Data is provided by the PN512 on the falling clock edge and is stable during
the rising clock edge.
10.2.1 SPI read data
Reading data using SPI requires the byte order shown in Table 143 to be used. It is
possible to read out up to n-data bytes.
The first byte sent defines both the mode and the address.
[1] X = Do not care.
Remark: The MSB must be sent first.
10.2.2 SPI write data
To write data to the PN512 using SPI requires the byte order shown in Table 144. It is
possible to write up to n data bytes by only sending one address byte.
Fig 13. SPI connection to host
001aan220
PN512
SCK
SCK
MOSI
MOSI
MISO
MISO
NSS
NSS
Table 143. MOSI and MISO byte order
Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1
MOSI address 0 address 1 address 2 ... address n 00
MISO X[1] data 0 data 1 ... data n 1 data n
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The first send byte defines both the mode and the address byte.
[1] X = Do not care.
Remark: The MSB must be sent first.
10.2.3 SPI address byte
The address byte has to meet the following format.
The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is
set to logic 1. To write data to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define
the address and the LSB is set to logic 0.
10.3 UART interface
10.3.1 Connection to a host
Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s
RS232LineEn bit.
10.3.2 Selectable UART transfer speeds
The internal UART interface is compatible with an RS232 serial interface.
The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller
must write a value for the new transfer speed to the SerialSpeedReg register. Bits
BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the
SerialSpeedReg register.
The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different
transfer speeds and the relevant register settings are given in Table 11.
Table 144. MOSI and MISO byte order
Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1
MOSI address 0 data 0 data 1 ... data n 1 data n
MISO X[1] X[1] X[1] ... X[1] X[1]
Table 145. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read
0 = write
address 0
Fig 14. UART connection to microcontrollers
001aan221
PN512
RX
RX
TX
TX
DTRQ
DTRQ
MX
MX
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[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.
The selectable transfer speeds shown in Table 11 are calculated according to the
following equations:
If BR_T0[2:0] = 0:
(1)
If BR_T0[2:0] > 0:
(2)
Remark: Transfer speeds above 1228.8 kBd are not supported.
10.3.3 UART framing
Table 146. BR_T0 and BR_T1 settings
BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
BR_T0 factor 1 1 2 4 8 16 32 64
BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
Table 147. Selectable UART transfer speeds
Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1]
Decimal Hexadecimal
7.2 250 FAh 0.25
9.6 235 EBh 0.32
14.4 218 DAh 0.25
19.2 203 CBh 0.32
38.4 171 ABh 0.32
57.6 154 9Ah 0.25
115.2 122 7Ah 0.25
128 116 74h 0.06
230.4 90 5Ah 0.25
460.8 58 3Ah 0.25
921.6 28 1Ch 1.45
1228.8 21 15h 0.32
transfer speed 27.12 106
BR_T0 + 1 = -------------------------------
transfer speed 27.12 106
BR_T1 + 33
2BR_T0 – 1 -----------------------------------
-----------------------------------
=
Table 148. UART framing
Bit Length Value
Start 1-bit 0
Data 8 bits data
Stop 1-bit 1
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Remark: The LSB for data and address bytes must be sent first. No parity bit is used
during transmission.
Read data: To read data using the UART interface, the flow shown in Table 149 must be
used. The first byte sent defines both the mode and the address.
Write data: To write data to the PN512 using the UART interface, the structure shown in
Table 150 must be used.
The first byte sent defines both the mode and the address.
Table 149. Read data byte order
Pin Byte 0 Byte 1
RX (pin 24) address -
TX (pin 31) - data 0
(1) Reserved.
Fig 15. UART read data timing diagram
001aak588
SA
ADDRESS
RX
TX
MX
DTRQ
A0 A1 A2 A3 A4 A5 (1) SO
SA D0 D1 D2 D3 D4 D5 D6 D7 SO
DATA
R/W
Table 150. Write data byte order
Pin Byte 0 Byte 1
RX (pin 24) address 0 data 0
TX (pin 31) - address 0
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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Remark: The data byte can be sent directly after the address byte on pin RX.
Address byte: The address byte has to meet the following format:
(1) Reserved.
Fig 16. UART write data timing diagram
001aak589
SA
ADDRESS
RX
TX
MX
DTRQ
A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO
SA A0 A1 A2 A3 A4 A5 (1) SO
DATA
ADDRESS
R/W
R/W
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The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is
set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for
future use, and bits 5 to 0 define the address; see Table 151.
10.4 I2C Bus Interface
An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus
interface to the host. The I2C-bus interface is implemented according to
NXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. The
interface can only act in Slave mode. Therefore the PN512 does not implement clock
generation or access arbitration.
The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast
mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
PN512 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus
can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast
mode or up to 3.4 Mbit/s in High-speed mode.
If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA
as defined in the I2C-bus interface specification.
See Table 171 on page 117 for timing requirements.
Table 151. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read
0 = write
reserved address
Fig 17. I2C-bus interface
001aan222
PN512
SDA
SCL
I2C
EA
ADR_[5:0]
PULL-UP
NETWORK
CONFIGURATION
WIRING
PULL-UP
NETWORK
MICROCONTROLLER
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10.4.1 Data validity
Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW
state of the data line must only change when the clock signal on SCL is LOW.
10.4.2 START and STOP conditions
To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
• A START condition is defined with a HIGH-to-LOW transition on the SDA line while
SCL is HIGH.
• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while
SCL is HIGH.
The I2C-bus master always generates the START and STOP conditions. The bus is busy
after the START condition. The bus is free again a certain time after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,
S is used as a generic term to represent both the START (S) and repeated START (Sr)
conditions.
10.4.3 Byte format
Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;
see Figure 22. The number of transmitted bytes during one data transfer is unrestricted
but must meet the read/write cycle format.
Fig 18. Bit transfer on the I2C-bus
mbc621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 19. START and STOP conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
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10.4.4 Acknowledge
An acknowledge must be sent at the end of one data byte. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer or a
repeated START (Sr) condition to start a new transfer.
A master-receiver indicates the end of data to the slave-transmitter by not generating an
acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
releases the data line to allow the master to generate a STOP (P) or repeated START (Sr)
condition.
Fig 20. Acknowledge on the I2C-bus
mbc602
S
START
condition
1 2 8 9
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
Fig 21. Data transfer on the I2C-bus
msc608
Sr
or
P
SDA
Sr
P
SCL
STOP or
repeated START
condition
S
or
Sr
START or
repeated START
condition
1 2 3 - 8 9
ACK
9
ACK
1 2 7 8
MSB acknowledgement
signal from slave
byte complete,
interrupt within slave
clock line held LOW while
interrupts are serviced
acknowledgement
signal from receiver
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10.4.5 7-Bit addressing
During the I2C-bus address procedure, the first byte after the START condition is used to
determine which slave will be selected by the master.
Several address numbers are reserved. During device configuration, the designer must
ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus
specification for a complete list of reserved addresses.
The I2C-bus address specification is dependent on the definition of pin EA. Immediately
after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus
address according to pin EA.
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by
NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer
to prevent collisions with other I2C-bus devices.
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins
according to Table 141 on page 69. ADR_6 is always set to logic 0.
In both modes, the external address coding is latched immediately after releasing the
reset condition. Further changes at the used pins are not taken into consideration.
Depending on the external wiring, the I2C-bus address pins can be used for test signal
outputs.
10.4.6 Register write access
To write data from the host controller using the I2C-bus to a specific register in the PN512
the following frame format must be used.
• The first byte of a frame indicates the device address according to the I2C-bus rules.
• The second byte indicates the register address followed by up to n-data bytes.
In one frame all data bytes are written to the same register address. This enables fast
FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.
Fig 22. First byte following the START procedure
slave address 001aak591
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
MSB LSB
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10.4.7 Register read access
To read out data from a specific register address in the PN512, the host controller must
use the following procedure:
• Firstly, a write access to the specific register address must be performed as indicated
in the frame that follows
• The first byte of a frame indicates the device address according to the I2C-bus rules
• The second byte indicates the register address. No data bytes are added
• The Read/Write bit is 0
After the write access, read access can start. The host sends the device address of the
PN512. In response, the PN512 sends the content of the read access register. In one
frame all data bytes can be read from the same register address. This enables fast FIFO
buffer access or register polling.
The Read/Write (R/W) bit is set to logic 1.
Fig 23. Register read and write access
001aak592
S A 0 0
I2C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
write cycle
0
(W) A DATA
[7:0]
[0:n]
[0:n]
[0:n]
A
P
S A 0 0
I2C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
read cycle
optional, if the previous access was on the same register address
0
(W) A P
P
S
S start condition
P stop condition
A acknowledge
A not acknowledge
W write cycle
R read cycle
A
I2C-BUS
SLAVE ADDRESS
[A7:A0]
sent by master
sent by slave
DATA
[7:0]
1
(R) A
DATA
[7:0]
A
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10.4.8 High-speed mode
In High-speed mode (HS mode), the device can transfer information at data rates of up to
3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode
(F/S mode) for bidirectional communication in a mixed-speed bus system.
10.4.9 High-speed transfer
To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to
I2C-bus operation.
• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger
on the SDA and SCL inputs and different timing constants when compared to
F/S mode
• The output buffers of the device in HS mode incorporate slope control of the falling
edges of the SDA and SCL signals with different fall times compared to F/S mode
10.4.10 Serial data transfer format in HS mode
The HS mode serial data transfer format meets the Standard mode I2C-bus specification.
HS mode can only start after all of the following conditions (all of which are in F/S mode):
1. START condition (S)
2. 8-bit master code (00001XXXb)
3. Not-acknowledge bit (A)
When HS mode starts, the active master sends a repeated START condition (Sr) followed
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from
the selected PN512.
Data transfer continues in HS mode after the next repeated START (Sr), only switching
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,
a master links a number of HS mode transfers, separated by repeated START conditions
(Sr).
Fig 24. I2C-bus HS mode protocol switch
F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode
001aak749
A A DATA A/A
(n-bytes + A)
S MASTER CODE Sr SLAVE ADDRESS R/W
HS mode continues
Sr SLAVE ADDRESS
P
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Fig 25. I2C-bus HS mode protocol frame
msc618
8-bit master code 0000 1xxx A
tH
t1
S
F/S mode
HS mode
If P then
F/S mode
If Sr (dotted lines)
then HS mode
1 6 7 8 9 1 6 7 8 9
1 2 to 5
2 to 5 2 to 5
6 7 8 9
SDA high
SCL high
SDA high
SCL high
tH
tFS
Sr Sr P
7-bit SLA R/W A n + (8-bit data + A/A)
= Master current source pull-up
= Resistor pull-up
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10.4.11 Switching between F/S mode and HS mode
After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as
Fast mode is downward-compatible with Standard mode). The connected PN512
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast
mode setting to the HS mode setting.
The following actions are taken:
1. Adapt the SDA and SCL input filters according to the spike suppression requirement
in HS mode.
2. Adapt the slope control of the SDA output stages.
It is possible for system configurations that do not have other I2C-bus devices involved in
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines
must be avoided because of the reduced spike suppression.
10.4.12 PN512 at lower speed modes
PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus
system. The device stays in F/S mode and communicates at F/S mode speeds because a
master code is not transmitted in this configuration.
11. 8-bit parallel interface
The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola
compatible modes.
11.1 Overview of supported host controller interfaces
The PN512 supports direct interfacing to various -Controllers. The following table shows
the parallel interface types supported by the PN512.
Table 152. Supported interface types
Supported interface types Bus Separated Address and
Data Bus
Multiplexed Address
and Data Bus
Separated Read and Write
Strobes (INTEL compatible)
control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0 … A3 [..A5*] AD0 … AD7
data D0 … D7 AD0 … AD7
Multiplexed Read and Write
Strobe (Motorola compatible)
control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0 … A3 [..A5*] AD0 … AD7
data D0 … D7 AD0 … AD7
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11.2 Separated Read/Write strobe
For timing requirements refer to Section 26.2 “8-bit parallel interface timing”.
11.3 Common Read/Write strobe
For timing requirements refer to Section 26.2 “8-bit parallel interface timing”
Fig 26. Connection to host controller with separated Read/Write strobes
001aan223
PN512
NCS
A0...A3[A5*]
D0...D7
A0
A1
A2
A3
A4*
A5*
address bus (A0...A3[A5*])
ALE
NRD
NWR
ADDRESS
DECODER
data bus (D0...D7)
high
not data strobe (NRD)
not write (NWR)
address bus
remark: *depending on the package type.
multiplexed address/data AD0...AD7)
PN512
NCS
D0...D7
ALE
NRD
NWR
ADDRESS
DECODER
low
low
high
high
high
low
address latch enable (ALE)
not read strobe (NRD)
not write (NWR)
non multiplexed
address
Fig 27. Connection to host controller with common Read/Write strobes
001aan224
PN512
NCS
A0...A3[A5*]
D0...D7
A0
A1
A2
A3
A4*
A5*
address bus (A0...A3[A5*])
ALE
NRD
NWR
ADDRESS
DECODER
Data bus (D0...D7)
high
not data strobe (NDS)
read not write (RD/NWR)
address bus
remark: *depending on the package type.
multiplexed address/data AD0...AD7)
PN512
NCS
D0...D7
ALE
NRD
NWR
ADDRESS
DECODER
low
low
high
high
low
low
address strobe (AS)
not data strobe (NDS)
read not write (RD/NWR)
non multiplexed
address
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12. Analog interface and contactless UART
12.1 General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kBd. An external circuit can be connected
to the communication interface pins MFIN and MFOUT to modulate and demodulate the
data.
The contactless UART handles the protocol requirements for the communication
protocols in cooperation with the host. Protocol handling generates bit and byte-oriented
framing. In addition, it handles error detection such as parity and CRC, based on the
various supported contactless communication protocols.
Remark: The size and tuning of the antenna and the power supply voltage have an
important impact on the achievable operating distance.
12.2 TX driver
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly using a few passive
components for matching and filtering; see Section 15 on page 96. The signal on pins TX1
and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on
page 40.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured using registers CWGsPReg and
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg
register. The modulation index also depends on the antenna design and tuning.
The TxModeReg and TxSelReg registers control the data rate and framing during
transmission and the antenna driver setting to support the different requirements at the
different modes and transfer speeds.
[1] X = Do not care.
Table 153. Register and bit settings controlling the signal on pin TX1
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
InvTx1RFOn
Bit
InvTx1RFOff
Envelope Pin
TX1
GSPMos GSNMos Remarks
0 X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is
switched off
1 0 0 X[1] 0 RF pMod nMod 100 % ASK: pin TX1
pulled to logic 0,
independent of the
InvTx1RFOff bit
1 RF pCW nCW
0 1 X[1] 0 RF pMod nMod
1 RF pCW nCW
1 1 X[1] 0 0 pMod nMod
1 RF_n pCW nCW
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[1] X = Do not care.
The following abbreviations have been used in Table 153 and Table 154:
• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2
• RF_n: inverted 13.56 MHz clock
• GSPMos: conductance, configuration of the PMOS array
• GSNMos: conductance, configuration of the NMOS array
• pCW: PMOS conductance value for continuous wave defined by the CWGsPReg
register
• pMod: PMOS conductance value for modulation defined by the ModGsPReg register
• nCW: NMOS conductance value for continuous wave defined by the GsNReg
register’s CWGsN[3:0] bits
• nMod: NMOS conductance value for modulation defined by the GsNReg register’s
ModGsN[3:0] bits
• X = do not care.
Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and
GsNReg registers are used for both drivers.
12.3 RF level detector
The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF
collision avoidance). Furthermore the RF level detector can be used to wake up the
PN512 and to generate an interrupt.
Table 154. Register and bit settings controlling the signal on pin TX2
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
Tx2CW
Bit
InvTx2RFOn
Bit
InvTx2RFOff
Envelope
Pin
TX2
GSPMos GSNMos Remarks
0 X[1] X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if
RF is switched
off
1 0 0 0 X[1] 0 RF pMod nMod -
1 RF pCW nCW
1 X[1] 0 RF_n pMod nMod
1 RF_n pCW nCW
1 0 X[1] X[1] RF pCW nCW conductance
always CW for
the Tx2CW bit
1 X[1] X[1] RF_n pCW nCW
1 0 0 X[1] 0 0 pMod nMod 100 % ASK: pin
TX2 pulled
to logic 0
(independent of
the
InvTx2RFOn/In
vTx2RFOff bits)
1 RF pCW nCW
1 X[1] 0 0 pMod nMod
1 RF_n pCW nCW
1 0 X[1] X[1] RF pCW nCW
1 X[1] X[1] RF_n pCW nCW
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The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel
in register RFCfgReg. The sensitivity itself depends on the antenna configuration and
tuning.
Possible sensitivity levels at the RX pin are listed in the Table 154.
To increase the sensitivity of the RF level detector an amplifier can be activated by setting
the bit RFLevelAmp in register RFCfgReg to 1.
Remark: During soft Power-down mode the RF level detector amplifier is automatically
switched off to ensure that the power consumption is less than 10 A at 3 V.
Remark: With typical antennas lower sensitivity levels can provoke misleading results
because of intrinsic noise in the environment.
Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings.
12.4 Data mode detector
The Data mode detector gives the possibility to detect received signals according to the
ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds
for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and
convenient way for further data processing.
The Data mode detector can only be activated by the AutoColl command. The mode
detector resets, when no external RF field is detected by the RF level detector. The Data
mode detector could be switched off during the AutoColl command by setting bit
ModeDetOff in register ModeReg to 1.
Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated)
V~Rx [Vpp] RFLevel
~2 1111
~1.4 1110
~0.99 1101
~0.69 1100
~0.49 1011
~0.35 1010
~0.24 1001
~0.17 1000
~0.12 0111
~0.083 0110
~0.058 0101
~0.041 0100
~0.029 0011
~0.020 0010
~0.014 0001
~0.010 0000
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Fig 28. Data mode detector
001aan225
HOST INTERFACES
RECEIVER
I/Q DEMODULATOR
REGISTERS
REGISTERSETTING
FOR THE
DETECTED MODE
DATA MODE DETECTOR
PN512 RX
NFC @ 106 kbit/s
NFC @ 212 kbit/s
NFC @ 424 kbit/s
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12.5 Serial data switch
Two main blocks are implemented in the PN512. The digital block comprises the state
machines, encoder/decoder logic. The analog block comprises the modulator and
antenna drivers, the receiver and amplifiers. The interface between these two blocks can
be configured in the way, that the interfacing signals may be routed to the pins SIGIN and
SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above
424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional
external circuit to generate transfer speeds above 424 kbit (including 106, 212 and
424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S2C interface in the
card SAM mode to emulate a card functionality with the PN512 and a secure IC. A secure
IC can be the SmartMX smart card controller IC.
This topology allows the analog block of the PN512 to be connected to the digital block of
another device.
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.
Figure 29 shows the serial data switch for TX1 and TX2.
12.6 S2C interface support
The S2C provides the possibility to directly connect a secure IC to the PN512 in order act
as a contactless smart card IC via the PN512. The interfacing signals can be routed to the
pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized
ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital
signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC
provided by NXP Semiconductors.
The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and
SIGOUT pads.
Figure 31 outlines possible ways of communications via the PN512 to the secure IC.
Fig 29. Serial data switch for TX1 and TX2
001aak593
INTERNAL
CODER
INVERT IF
InvMod = 1
DriverSel[1:0]
00
01
10
11
3-state
to driver TX1 and TX2
0 = impedance = modulated
1 = impedance = CW
1
INVERT IF
PolMFin = 0
MFIN
envelope
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Configured in the Secure Access Mode the host controller can directly communicate to
the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and
performs the communication on the SIGOUT line. To enable the Secure Access module
mode the clock has to be derived by the internal oscillator of the PN512, see bits
SAMClockSel in register TestSel1Reg.
Configured in Contactless Card mode the secure IC can act as contactless smart card IC
via the PN512. In this mode the signal on the SIGOUT line is provided by the external RF
field of the external reader/writer. To enable the Contactless Card mode the clock derived
by the external RF field has to be used.
The configuration of the S2C interface differs for the FeliCa and MIFARE scheme as
outlined in the following chapters.
Fig 30. Communication flows using the S2C interface
001aan226
CONTACTLESS UART
SERIAL SIGNAL SWITCH
FIFO AND STATE MACHINE
SPI, I2C, SERIAL UART
HOST CONTROLLER
PN512
SECURE CORE IC
SIGOUT
SIGIN
2. contactless
card mode
1. secure access
module (SAM) mode
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12.6.1 Signal shape for Felica S2C interface support
The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN.
The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized
demodulated signal. The clock and the demodulated signal is combined by using the
logical function exclusive or.
To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
The time delay for that digital filtering is in the range of one bit length. The demodulated
signal changes only at a positive edge of the clock.
The register TxSelReg controls the setting at SIGOUT.
The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver.
The modulation is done according to the register settings of the antenna drivers.
The clock is switched to AUX1 or AUX2 (see AnalogSelAux).
Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at
SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock
output if a serial interface is used. The HIGH level at D0 is the same as PVDD.
Note: The signal on the antenna is shown in principle only. In reality the waveform is
sinusoidal.
Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode
Fig 32. Signal shape for SIGIN in SAM mode
001aan227
clock
signal on
SIGIN
signal on
antenna
001aan228
clock
demodulated
signal
signal on
SIGOUT
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12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support
The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and
SIGIN.
The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels
between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of
the Contactless Card mode or internally generated in terms of Secure Access mode.
The register TxSelReg controls the setting at SIGOUT.
Note: The clock settings for the Secure Access mode and the Contactless Card mode
differ, refer to the description of the bits SAMClockSel in register TestSel1Reg.
The signal at SIGIN is a digital Manchester coded signal according to the requirements of
the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure
IC.
Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode
Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode
001aan229
1
0
bit
value RF
signal on
antenna
signal on
SIGOUT
0 1 0 0 1
001aan230
0
1
0
1 0 0 1
bit
value
signal on
antenna
signal on
SIGIN
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12.7 Hardware support for FeliCa and NFC polling
12.7.1 Polling sequence functionality for initiator
1. Timer: The PN512 has a timer, which can be programmed in a way that it generates
an interrupt at the end of each timeslot, or if required an interrupt is generated at the
end of the last timeslot.
2. The receiver can be configured in a way to receive continuously. In this mode it can
receive any number of packets. The receiver is ready to receive the next packet
directly after the last packet has been received. This mode is active by setting the bit
RxMultiple in register RxModeReg to 1 and has to be stopped by software.
3. The internal UART adds one byte to the end of every received packet, before it is
transferred into the FIFO-buffer. This byte indicates if the received byte packet is
correct (see register ErrReg). The first byte of each packet contains the length byte of
the packet.
4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a
length of 64 bytes. This means three packets can be stored in the FIFO at the same
time. If more than three packets are expected, the host controller has to empty the
FIFO, before the FIFO is filled completely. In case of a FIFO-overflow data is lost (See
bit BufferOvfl in register ErrorReg).
12.7.2 Polling sequence functionality for target
1. The host controller has to configure the PN512 with the correct polling response
parameters for the polling command.
2. To activate the automatic polling in Target mode, the AutoColl Command has to be
activated.
3. The PN512 receives the polling command send out by an initiator and answers with
the polling response. The timeslot is selected automatically (The timeslot itself is
randomly generated, but in the range 0 to TSN, which is defined by the Polling
command). The PN512 compares the system code, stored in byte 17 and 18 of the
Config Command with the system code received by the polling command of an
initiator. If the system code is equal, the PN512 answers according to the configured
polling response. The system code FF (hex) acts as a wildcard for the system code
bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with
one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex).
If the system code does not match no answer is sent back by the PN512.
If a valid command is received by the PN512, which is not a Polling command, no
answer is sent back and the command AutoColl is stopped. The received packet is
stored in the FIFO.
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12.7.3 Additional hardware support for FeliCa and NFC
Additionally to the polling sequence support for the Felica mode, the PN512 supports the
check of the Len-byte.
The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg:
DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet
length. This register is six bit long. Each bit represents a length of four bytes.
DataLenMax in register FelNFC2Reg defines the maximum length of the accepted
package. This register is six bit long. Each bit represents a length of four bytes. If set to
logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not
transferred to the FIFO and receiving is kept active.
Example 1:
• DataLenMin = 4
– The length shall be greater or equal 16.
• DataLenMax = 5
– The length shall be smaller than 20. Valid area: 16, 17, 18, 19
Example 2:
• DataLenMin = 9
– The length shall be greater or equal 36.
• DataLenMax = 0
– The length shall be smaller than 256. Valid area: 36 to 255
12.7.4 CRC coprocessor
The following CRC coprocessor parameters can be configured:
• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
• The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1
• The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB
first.
Table 156. CRC coprocessor parameters
Parameter Value
CRC register length 16-bit CRC
CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T
CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the
ModeReg register’s CRCPreset[1:0] bits
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13. FIFO buffer
An 8 64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream
between the host and the PN512’s internal state machine. This makes it possible to
manage data streams up to 64 bytes long without the need to take timing constraints into
account.
13.1 Accessing the FIFO buffer
The FIFO buffer input and output data bus is connected to the FIFODataReg register.
Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO
buffer write pointer. Reading from this register shows the FIFO buffer contents stored in
the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance
between the write and read pointer can be obtained by reading the FIFOLevelReg
register.
When the microcontroller starts a command, the PN512 can, while the command is in
progress, access the FIFO buffer according to that command. Only one FIFO buffer has
been implemented which can be used for input and output. The microcontroller must
ensure that there are not any unintentional FIFO buffer accesses.
13.2 Controlling the FIFO buffer
The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit
to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg
register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer
accessible allowing the FIFO buffer to be filled with another 64 bytes.
13.3 FIFO buffer status information
The host can get the following FIFO buffer status information:
• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]
• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit
• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit
• FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit
can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.
The PN512 can generate an interrupt signal when:
• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to
Equation 3:
HiAlert = 64 – FIFOLength WaterLevel (3)
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If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4:
(4)
14. Interrupt request system
The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
14.1 Interrupt sources overview
Table 157 shows the available interrupt bits, the corresponding source and the condition
for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set
by the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on
page 101).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
LoAlert = FIFOLength WaterLevel
Table 157. Interrupt sources
Interrupt flag Interrupt source Trigger action
TimerIRq timer unit the timer counts from 1 to 0
TxIRq transmitter a transmitted data stream ends
CRCIRq CRC coprocessor all data from the FIFO buffer has been processed
RxIRq receiver a received data stream ends
IdleIRq ComIrqReg register command execution finishes
HiAlertIRq FIFO buffer the FIFO buffer is almost full
LoAlertIRq FIFO buffer the FIFO buffer is almost empty
ErrIRq contactless UART an error is detected
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15. Timer unit
A timer unit is implemented in the PN512. The external host controller may use this timer
to manage timing relevant tasks. The timer unit may be used in one of the following
configurations:
• Time-out counter
• Watch-dog counter
• Stop watch
• Programmable one-shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
which will be explained in the following, but the timer itself does not influence any internal
event (e.g. A time-out during data reception does not influence the reception process
automatically). Furthermore, several timer related bits are set and these bits can be used
to generate an interrupt.
Timer
The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer
consists of two stages: 1 prescaler and 1 counter.
The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between
0 and 4095 in register TModeReg and TPrescalerReg.
The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the
register TReloadReg.
The current value of the timer is indicated by the register TCounterValReg.
If the counter reaches 0 an interrupt will be generated automatically indicated by setting
the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on
the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on
the configuration the timer will stop at 0 or restart with the value from register
TReloadReg.
The status of the timer is indicated by bit TRunning in register Status1Reg.
The timer can be manually started by TStartNow in register ControlReg or manually
stopped by TStopNow in register ControlReg.
Furthermore the timer can be activated automatically by setting the bit TAuto in the
register TModeReg to fulfill dedicated protocol requirements automatically.
The time delay of a timer stage is the reload value +1.
The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if
TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz
Maximum time: TPrescaler = 4095,TReloadVal = 65535
=> (2*4095 +2)*65536/13.56 MHz = 39.59 s
Example:
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To indicate 25 us it is required to count 339 clock cycles. This means the value for
TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us.
The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version
1.0, see Section 21 “Errata sheet” on page 109.
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16. Power reduction modes
16.1 Hard power-down
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
16.2 Soft power-down mode
Soft Power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited.
Remark: If the internal oscillator is used, you must take into account that it is supplied by
pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock
cycles can be detected by the internal logic. It is recommended for the serial UART, to first
send the value 55h to the PN512. The oscillator must be stable for further access to the
registers. To ensure this, perform a read access to address 0 until the PN512 answers to
the last read command with the register content of address 0. This indicates that the
PN512 is ready.
16.3 Transmitter power-down mode
The Transmitter Power-down mode switches off the internal antenna drivers thereby,
turning off the RF field. Transmitter power-down mode is entered by setting either the
TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.
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17. Oscillator circuitry
The clock applied to the PN512 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency, therefore, is an important factor
for correct operation. To obtain optimum performance, clock jitter must be reduced as
much as possible. This is best achieved using the internal oscillator buffer with the
recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, special care must be taken with the clock duty cycle and clock jitter and the clock
quality must be verified.
18. Reset and oscillator start-up time
18.1 Reset timing requirements
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,
the signal must be LOW for at least 100 ns.
18.2 Oscillator start-up time
If the PN512 has been set to a Power-down mode or is powered by a VDDX supply, the
start-up time for the PN512 depends on the oscillator used and is shown in Figure 36.
The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator
start-up time is defined by the crystal.
The time (td) is the internal delay time of the PN512 when the clock signal is stable before
the PN512 can be addressed.
The delay time is calculated by:
(5)
The time (tosc) is the sum of td and tstartup.
Fig 35. Quartz crystal connection
001aan231
PN512
27.12 MHz
OSCOUT OSCIN
td
1024
27 s
= -------------- = 37.74 s
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19. PN512 command set
The PN512 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 158) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
19.1 General description
The PN512 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 158) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
19.2 General behavior
• Each command that needs a data bit stream (or data byte stream) as an input
immediately processes any data in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command, transmission is started with the
BitFramingReg register’s StartSend bit.
• Each command that needs a certain number of arguments, starts processing only
when it has received the correct number of arguments from the FIFO buffer.
• The FIFO buffer is not automatically cleared when commands start. This makes it
possible to write command arguments and/or the data bytes to the FIFO buffer and
then start the command.
• Each command can be interrupted by the host writing a new command code to the
CommandReg register, for example, the Idle command.
Fig 36. Oscillator start-up time
001aak596
tstartup td
tosc
t
device activation
oscillator
clock stable
clock ready
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19.3 PN512 command overview
19.3.1 PN512 command descriptions
19.3.1.1 Idle
Places the PN512 in Idle mode. The Idle command also terminates itself.
19.3.1.2 Config command
To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for
these transactions has to be stored internally. All the following data have to be written to
the FIFO in this order:
SENS_RES (2 bytes); in order byte 0, byte 1
NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h and
the check byte is calculated automatically.
SEL_RES (1 Byte)
polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes
system code)
NFCID3 (1 byte)
In total 25 bytes are transferred into an internal buffer.
The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2
bytes and the one NFCID3 byte which are listed above.
To read out this configuration the command Config with an empty FIFO-buffer has to be
started. In this case the 25 bytes are transferred from the internal buffer to the FIFO.
Table 158. Command overview
Command Command
code
Action
Idle 0000 no action, cancels current command execution
Configure 0001 Configures the PN512 for FeliCa, MIFARE and NFCIP-1
communication
Generate RandomID 0010 generates a 10-byte random ID number
CalcCRC 0011 activates the CRC coprocessor or performs a self test
Transmit 0100 transmits data from the FIFO buffer
NoCmdChange 0111 no command change, can be used to modify the
CommandReg register bits without affecting the command,
for example, the PowerDown bit
Receive 1000 activates the receiver circuits
Transceive 1100 transmits data from FIFO buffer to antenna and automatically
activates the receiver after transmission
AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and
MIFARE anticollision (Card Operation mode only)
MFAuthent 1110 performs the MIFARE standard authentication as a reader
SoftReset 1111 resets the PN512
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The PN512 has to be configured after each power up, before using the automatic
Anticollision/Polling function (AutoColl command). During a hard power down (reset pin)
this configuration remains unchanged.
This command terminates automatically when finished and the active command is idle.
19.3.1.3 Generate RandomID
This command generates a 10-byte random number which is initially stored in the internal
buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command
automatically terminates when finished and the PN512 returns to Idle mode.
19.3.1.4 CalcCRC
The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is
started. The calculation result is stored in the CRCResultReg register. The CRC
calculation is not limited to a dedicated number of bytes. The calculation is not stopped
when the FIFO buffer is empty during the data stream. The next byte written to the FIFO
buffer is added to the calculation.
The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The
value is loaded in to the CRC coprocessor when the command starts.
This command must be terminated by writing a command to the CommandReg register,
such as, the Idle command.
If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self
Test mode. Starting the CalcCRC command initiates a digital self test. The result of the
self test is written to the FIFO buffer.
19.3.1.5 Transmit
The FIFO buffer content is immediately transmitted after starting this command. Before
transmitting the FIFO buffer content, all relevant registers must be set for data
transmission.
This command automatically terminates when the FIFO buffer is empty. It can be
terminated by another command written to the CommandReg register.
19.3.1.6 NoCmdChange
This command does not influence any running command in the CommandReg register. It
can be used to manipulate any bit except the CommandReg register Command[3:0] bits,
for example, the RcvOff bit or the PowerDown bit.
19.3.1.7 Receive
The PN512 activates the receiver path and waits for a data stream to be received. The
correct settings must be chosen before starting this command.
This command automatically terminates when the data stream ends. This is indicated
either by the end of frame pattern or by the length byte depending on the selected frame
type and speed.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive
command will not automatically terminate. It must be terminated by starting another
command in the CommandReg register.
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19.3.1.8 Transceive
This command continuously repeats the transmission of data from the FIFO buffer and the
reception of data from the RF field. The first action is transmit and after transmission the
command is changed to receive a data stream.
Each transmit process must be started by setting the BitFramingReg register’s StartSend
bit to logic 1. This command must be cleared by writing any command to the
CommandReg register.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive
command never leaves the receive state because this state cannot be cancelled
automatically.
19.3.1.9 AutoColl
This command automatically handles the MIFARE activation and the FeliCa polling in the
Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0
for correct operation. During this command also the mode detector is active if not
deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode
detector detects a mode, all the mode dependent registers are set according to the
received data. In case of no external RF field the command resets the internal state
machine and returns to the initial state but it will not be terminated. When the command
terminates the transceive command gets active.
During protocol processing the IRQ bits are not supported. Only the last received frame
will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the
protocol. During ISO/IEC 14443A activation the enable bits are defined by the command
AutoColl. The changes cannot be observed at the register TXModeReg and RXModeReg.
After the Transceive command is active, the value of the register bit is relevant.
The FIFO will also receive the two CRC check bytes of the last command even if they
already checked and correct, if the state machine (Anticollision and Select routine) has to
not been executed and 106 kbit is detected.
During Felica activation the register bit is always relevant and is not overruled by the
command settings. This command can be cleared by software by writing any other
command to the CommandReg register, e.g. the idle command. Writing the same content
again to the CommandReg register resets the state machine.
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NFCIP-1 106 kbps Passive Communication mode:
The MIFARE anticollision is finished and the command has automatically changed to
Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit
TargetActivated in the Status2Reg register is set to logic 1.
NFCIP-1 212/424 kbps Passive Communication mode:
The FeliCa polling command is finished and the command has automatically changed to
Transceive. The FIFO contains the ATR_REQ. The bit TargetActivated in the Status2Reg
register is set to logic 1.
NFCIP-1 106/212/424 kbps Active Communication mode:
This command is changing the automatically to the command Transceive. The FIFO
contains the ATR REQ The bit TargetActivated in the Status2Reg register is set to logic 0.
For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC is
added to the FIFO.
Fig 37. Autocoll Command
NFCIP-1 106 kB aud
ISO14443-3
NPCIP-1 > 106 kB aud
FELICA
IDLE MODEO
MODE
detection
RXF
raming
MFHalted = 1
HALT
AC
nAC
SELECT
nSELECT
HLTA
AC
polling,
polling response
next frame
received
next frame
received
REQA, WUPA
READY
ACTIVE
WUPA
SELECT SELECT
READY*
ACTIVE*
TRANSCEIVE
wait for
transmit
next frame
received
J N
HLTA
REQA,
WUPA,
AC,
nAC,
SELECT,
nSELECT,
error
REQA,
AC,
nAC,
SELECT,
nSELECT,
HLTA
REQA,
WUPA,
nAC,
nSELECT,
HLTA,
error
REQA,
WUPA,
nAC,
nSELECT,
HLTA,
error
REQA,
WUPA,
AC,
SELECT,
nSELECT,
error
00 10
AC
aaa-001826
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MIFARE (Card Operation mode):
The MIFARE anticollision is finished and the command has automatically changed to
transceive. The FIFO contains the first command after the Select. The bit TargetActivated
in the Status2Reg register is set to logic 1.
Felica (Card Operation mode):
The FeliCa polling command is finished and the command has automatically changed to
transceive. The FIFO contains the first command followed after the Poling by the FeliCa
protocol. The bit TargetActivated in the Status2Reg register is set to logic 1.
19.3.1.10 MFAuthent
This command manages MIFARE authentication to enable a secure communication to
any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the
FIFO buffer before the command can be activated:
• Authentication command code (60h, 61h)
• Block address
• Sector key byte 0
• Sector key byte 1
• Sector key byte 2
• Sector key byte 3
• Sector key byte 4
• Sector key byte 5
• Card serial number byte 0
• Card serial number byte 1
• Card serial number byte 2
• Card serial number byte 3
In total 12 bytes are written to the FIFO.
Remark: When the MFAuthent command is active all access to the FIFO buffer is
blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is
set.
This command automatically terminates when the MIFARE card is authenticated and the
Status2Reg register’s MFCrypto1On bit is set to logic 1.
This command does not terminate automatically if the card does not answer, so the timer
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the
TimerIRq bit can be used as the termination criteria. During authentication processing, the
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of
the MFAuthent command, either after processing the protocol or writing Idle to the
CommandReg register.
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.
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19.3.1.11 SoftReset
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command automatically
terminates when finished.
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.
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20. Testsignals
20.1 Selftest
The PN512 has the capability to perform a digital selftest. To start the selftest the following
procedure has to be performed:
1. Perform a soft reset.
2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command.
3. Enable the Selftest by writing the value 09h to the register AutoTestReg.
4. Write 00h to the FIFO.
5. Start the Selftest with the CalcCRC Command.
6. The Selftest will be performed.
7. When the Selftest is finished, the FIFO contains the following bytes:
Version 1.0 has a different Selftest answer, explained in Section 21.
Correct answer for VersionReg equal to 82h:
00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh,
9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h,
49h, 7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h,
21h, A9h, 86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh,
95h, 3Bh, 2Fh
20.2 Testbus
The testbus is implemented for production test purposes. The following configuration can
be used to improve the design of a system using the PN512. The testbus allows to route
internal signals to the digital interface. The testbus signals are selected by accessing
TestBusSel in register TestSel2Reg.
Table 159. Testsignal routing (TestSel2Reg = 07h)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal sdata scoll svalid sover RCV_reset RFon,
filtered
Envelope
Table 160. Description of Testsignals
Pins Testsignal Description
D6 sdata shows the actual received data stream.
D5 scoll shows if in the actual bit a collision has been detected (106 kbit only)
D4 svalid shows if sdata and scoll are valid
D3 sover shows that the receiver has detected a stop condition
(ISO/IEC 14443A/ MIFARE mode only).
D2 RCV_reset shows if the receiver is reset
D1 RFon, filtered shows the value of the internal RF level detector
D0 Envelope shows the output of the internal coder
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20.3 Testsignals at pin AUX
Table 161. Testsignal routing (TestSel2Reg = 0Dh)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf
Table 162. Description of Testsignals
Pins Testsignal Description
D6 clkstable shows if the oscillator delivers a stable signal.
D5 clk27/8 shows the output signal of the oscillator divided by 8
D4 clk27rf/8 shows the clk27rf signal divided by 8
D3 clkrf13/4 shows the clk13rf divided by 4.
D2 clk27 shows the output signal of the oscillator
D1 clk27rf shows the RF clock multiplied by 2.
D0 clk13rf shows the RF clock of 13.56 MHz
Table 163. Testsignal routing (TestSel2Reg = 19h)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal - TRunning - - - - -
Table 164. Description of Testsignals
Pins Testsignal Description
D6 - -
D5 TRunning TRunning stops 1 clockcycle after TimerIRQ is raised
D4 - -
D3 - -
D2 - -
D1 - -
D0 - -
Table 165. Testsignals description
SelAux Description for Aux1 / Aux2
0000 Tristate
0001 DAC: register TestDAC 1/2
0010 DAC: testsignal corr1
0011 DAC: testsignal corr2
0100 DAC: testsignal MinLevel
0101 DAC: ADC_I
0110 DAC: ADC_Q
0111 DAC: testsignal ADC_I combined with ADC_Q
1000 Testsignal for production test
1001 SAM clock
1010 High
1011 low
1100 TxActive
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Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the
register AnalogTestReg.
Note: The DAC has a current output, it is recommended to use a 1 k pull-down
resistance at pins AUX1/AUX2.
20.4 PRBS
Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the
transmission of the defined datastream the command send has to be activated. The
preamble/Sync byte/start bit/parity bit are generated automatically depending on the
selected mode.
Note: All relevant register to transmit data have to be configured before entering PRBS
mode according ITU-TO150.
21. Errata sheet
This data sheet is describing the functionality for version 2.0 and the industrial version.
This chapter lists all differences from version 1.0 to version 2.0:
The value of the version in Section 9.2.4.8 is set to80h.
The behaviour ‘RFU’ for the register is undefined.
The answer to the Selftest (see Section 20.1) for version 1.0 (VersionReg equal to 80h):
00h, AAh, E3h, 29h, 0Ch, 10h, 29zhh, 6Bh,
76h, 8Dh, AFh, 4Bh, A2h, DAh, 76h, 99h
C7h, 5Eh, 24h, 69h, D2h, BAh, FAh, BCh
3Eh, DAh, 96h, B5h, F5h, 94h, B0h, 3Ah
4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh
38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh
4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh
38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh
FBh, F4h, 19h, 94h, 82h, 5Ah, 72h, 9Dh
BAh, 0Dh, 1Fh, 17h, 56h, 22h, B9h, 08h
Only the default setting for the prescaler (see Section 15 “Timer unit” on page 96): t =
((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula fTimer =
13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in Table 100 “Description
of TModeReg bits” on page 57 and TPrescalerLo in Table 101 “TPrescalerReg register
(address 2Bh); reset value: 00h, 00000000b” on page 58. As there is no option for the
prescaler available, also the TPrescalEven is not available Section 9.2.2.10 on page 45.
This bit is set to ‘RFU’.
1101 RxActive
1110 Subcarrier detected
1111 TstBusBit
Table 165. Testsignals description
SelAux Description for Aux1 / Aux2
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Especially when using time slot protocols, it is needed that the error flag is copied into the
status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4
on page 39) within version 1.0 the protocol error flag is not included in the status
information for the frame. In addition the CRCOk is copied instead of the CRCErr. This
can be a problem in frames without length information e.g. ISO/IEC 14443-B.
The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits,
as such the configuration within Section 9.2.2.15 “TypeBReg” on page 50 bit 4 for
RxEOFReq does not exist. In addition the IC only has the possibility to select the
minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As
such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section
9.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only
setting minimum and maximum length according ISO/IEC 14443-B, see Section 9.2.2.15
“TypeBReg” on page 50, bit 4.
22. Application design-in information
The figure below shows a typical circuit diagram, using a complementary antenna
connection to the PN512.
The antenna tuning and RF part matching is described in the application note “NFC
Transmission Module Antenna and RF Design Guide”.
Fig 38. Typical circuit diagram
AVDD TVDD
RX
VMID
supply
TX1
TVSS
TX2
DVSS
DVDD
DVDD
PVDD
SVDD
AVSS
IRQ
NRSTPD
R1
R2
L0
C0
C0
C2
C1
CRX
RQ
C1 RQ
C2
L0
Cvmid
001aan232
27.12 MHz
OSCIN OSCOUT
HOST
CONTROLLER
interface
PN512
antenna
Lant
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23. Limiting values
24. Recommended operating conditions
Table 166. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDDA analog supply voltage 0.5 +4.0 V
VDDD digital supply voltage 0.5 +4.0 V
VDD(PVDD) PVDD supply voltage 0.5 +4.0 V
VDD(TVDD) TVDD supply voltage 0.5 +4.0 V
VDD(SVDD) SVDD supply voltage 0.5 +4.0 V
VI input voltage all input pins except pins SIGIN and
RX
VSS(PVSS) 0.5 VDD(PVDD) + 0.5 V
pin MFIN VSS(PVSS) 0.5 VDD(SVDD) + 0.5 V
Ptot total power dissipation per package; and VDDD in shortcut
mode
- 200 mW
Tj junction temperature - 125 C
VESD electrostatic discharge
voltage
HBM; 1500 , 100 pF;
JESD22-A114-B
- 2000 V
MM; 0.75 H, 200 pF;
JESD22-A114-A
- 200 V
Charged device model;
JESD22-C101-A
on all pins - 200 V
on all pins except SVDD in
TFBGA64 package
- 500 V
Industrial version:
VESD electrostatic discharge
voltage
HBM; 1500 , 100 pF;
JESD22-A114-B
- 2000 V
MM; 0.75 H, 200 pF;
JESD22-A114-A
- 200 V
Charged device model;
AEC-Q100-011
on all pins - 200 V
on all pins except SVDD - 500 V
Table 167. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2] 2.5 - 3.6 V
VDDD digital supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2] 2.5 - 3.6 V
VDD(TVDD) TVDD supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[1][2] 2.5 - 3.6 V
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[1] Supply voltages below 3 V reduce the performance (the achievable operating distance).
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
25. Thermal characteristics
26. Characteristics
VDD(PVDD) PVDD supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
[3] 1.6 - 3.6 V
VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V
Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 - +85 C
Industrial version:
Tamb ambient temperature HVQFN32 40 - +90 C
Table 167. Operating conditions …continued
Symbol Parameter Conditions Min Typ Max Unit
Table 168. Thermal characteristics
Symbol Parameter Conditions Package Typ Unit
Rthj-a Thermal resistance from
junction to ambient
In still air with exposed pad
soldered on a 4 layer Jedec PCB
In still air
HVQFN32 40 K/W
HVQFN40 35 K/W
TFBGA64 <0100 0000> <0100 0000>