LPC408x/7x 32-bit ARM Cortex-M4 MCU; up to 512 ... - NXP - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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1. General description The LPC408x/7x is an ARM Cortex-M4 based digital signal controller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex-M4 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated in the core for several versions of the part. The LPC408x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC408x/7x is targeted to operate at up to 120 MHz CPU frequency. The peripheral complement of the LPC408x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory controller (EMC), LCD, Ethernet, USB Device/Host/OTG, an SPI Flash Interface (SPIFI), a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine and up to 165 general purpose I/O pins. The analog peripherals include one eight-channel 12-bit ADC, two analog comparators, and a DAC. The pinout of LPC408x/7x is intended to allow pin function compatibility with the LPC24xx/23xx as well as the LPC178x/7x families. 2. Features and benefits  Functional replacement for LPC23xx/24xx and LPC178x/7x family devices.  ARM Cortex-M4 core:  ARM Cortex-M4 processor, running at frequencies of up to 120 MHz.  ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.  ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).  Hardware floating-point unit (not all versions).  Non-maskable Interrupt (NMI) input. LPC408x/7x 32-bit ARM Cortex-M4 MCU; up to 512 kB flash, 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC; SPIFI Rev. 3 — 1 May 2014 Product data sheet LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 2 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller  JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.  System tick timer.  System:  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time.  Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy.  Embedded Trace Macrocell (ETM) module supports real-time trace.  Boundary scan for simplified board testing.  Memory:  512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash.  Up to 96 kB on-chip SRAM includes: 64 kB of main SRAM on the CPU with local code/data bus for high-performance CPU access. Two 16 kB peripheral SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for DMA memory as well as for general purpose instruction and data storage.  Up to 4032 byte on-chip EEPROM.  LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays.  Dedicated DMA controller.  Selectable display resolution (up to 1024  768 pixels).  Supports up to 24-bit true-color mode.  External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM.  Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, GPIO, and for memory-to-memory transfers.  Serial interfaces:  Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.  Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB.  USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller.  Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one UART (USART4) supports IrDA, synchronous mode, and a smart card mode conforming to ISO7816-3. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 3 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller  Three SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.  Three enhanced I2C-bus interfaces, one with a true open-drain output supporting the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA.  CAN controller with two channels.  Digital peripherals:  SD/MMC memory card interface.  Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, with configurable pull-up/down resistors, open-drain mode, and repeater mode. All GPIOs are located on an AHB bus for fast access and support Cortex-M4 bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any pin of ports 0 and 2 can be used to generate an interrupt.  Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources.  Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.  Quadrature encoder interface that can monitor one external quadrature encoder.  Two standard PWM/timer blocks with external count input option.  One motor control PWM with support for three-phase motor control.  Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. Battery power can be supplied from a standard 3 V lithium button cell. The RTC will continue working when the battery voltage drops to as low as 2.1 V. An RTC interrupt can wake up the CPU from any reduced power mode.  Event Recorder that can capture the clock value when an event occurs on any of three inputs. The event identification and the time it occurred are stored in registers. The Event Recorder is located in the RTC power domain and can therefore operate as long as there is RTC power.  Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal oscillator, watchdog warning interrupt, and safety features.  CRC Engine block can calculate a CRC on supplied data using one of three standard polynomials. The CRC engine can be used in conjunction with the DMA controller to generate a CRC without CPU involvement in the data transfer.  Analog peripherals:  12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.  10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support.  Two analog comparators. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 4 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller  Power control:  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2 pin interrupt, and NMI).  Brownout detect with separate threshold for interrupt and forced reset.  On-chip Power-On Reset (POR).  Clock generation:  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, USB clock, or the watchdog timer clock.  On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.  12 MHz Internal RC oscillator (IRC) trimmed to 1 % accuracy that can optionally be used as a system clock.  An on-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator or the internal RC oscillator.  A second, dedicated PLL may be used for USB interface in order to allow added flexibility for the Main PLL settings.  Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions.  Unique device serial number for identification purposes.  Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C.  Available as LQFP208, TFBGA208, TFBGA180, LQFP144, TFBGA80, and LQFP80 package. 3. Applications  Communications:  Point-of-sale terminals, web servers, multi-protocol bridges  Industrial/Medical:  Automation controllers, application control, robotics control, HVAC, PLC, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom  Consumer/Appliance:  Audio, MP3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment  Automotive:  After-market, car alarms, GPS/fleet monitors LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 5 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC4088 LPC4088FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC4088FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm SOT950-1 LPC4088FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3 LPC4088FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1 LPC4078 LPC4078FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1 LPC4078FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15  15  0.7 mm SOT950-1 LPC4078FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3 LPC4078FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1 LPC4078FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12  12  1.4 mm SOT315-1 LPC4078FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC4076 LPC4076FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls SOT570-3 LPC4076FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1 LPC4074 LPC4074FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20  20  1.4 mm SOT486-1 LPC4074FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12  12  1.4 mm SOT315-1 LPC4072 LPC4072FET80 TFBGA80 plastic thin fine-pitch ball grid array package; 80 balls SOT1328-1 LPC4072FBD80 LQFP80 plastic low-profile quad package; 80 leads; body 12  12  1.4 mm SOT315-1 Table 2. Ordering options Type number Flash (kB) SRAM (kB) EEPROM (B) EMC bus width (bit) LCD Ethernet USB UART QEI SD/MMC Comparator FPU Package LPC4088 LPC4088FBD208 512 96 4032 32 yes yes H/O/D 5 yes yes yes yes LQFP208 LPC4088FET208 512 96 4032 32 yes yes H/O/D 5 yes yes yes yes TFBGA208 LPC4088FET180 512 96 4032 16 yes yes H/O/D 5 yes yes yes yes TFBGA180 LPC4088FBD144 512 96 4032 8 yes yes H/O/D 5 yes yes yes yes LQFP144 LPC4078 LPC4078FBD208 512 96 4032 32 no yes H/O/D 5 yes yes yes yes LQFP208 LPC4078FET208 512 96 4032 32 no yes H/O/D 5 yes yes yes yes TFBGA208 LPC4078FET180 512 96 4032 16 no yes H/O/D 5 yes yes yes yes TFBGA180 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 6 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller LPC4078FBD144 512 96 4032 8 no yes H/O/D 5 yes yes yes yes LQFP144 LPC4078FBD100 512 96 4032 - no yes H/O/D 5 yes yes yes yes LQFP100 LPC4078FBD80 512 96 4032 - no yes H/O/D 5 yes yes yes yes LQFP80 LPC4076 LPC4076FET180 256 80 2048 16 no yes H/O/D 5 yes yes yes yes TFBGA180 LPC4076FBD144 256 80 2048 8 no yes H/O/D 5 yes yes yes yes LQFP144 LPC4074 LPC4074FBD144 128 40 2048 - no no D 4 no no no no LQFP144 LPC4074FBD80 128 40 2048 - no no D 4 no no no no LQFP80 LPC4072 LPC4072FET80 64 24 2048 - no no D 4 no no no no TFBGA80 LPC4072FBD80 64 24 2048 - no no D 4 no no no no LQFP80 Table 2. Ordering options …continued Type number Flash (kB) SRAM (kB) EEPROM (B) EMC bus width (bit) LCD Ethernet USB UART QEI SD/MMC Comparator FPU Package LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 7 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 5. Block diagram (1) Not available on all parts. Fig 1. Block diagram SRAM 96/80/ 40/24 kB ARM CORTEX-M4 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128/64 kB GPDMA CONTROLLER I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 4032 B/ 2048 B EEPROM CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls JTAG interface debug port SSP0/2 USART4(1) UART2/3 SYSTEM CONTROL 2 x ANALOG COMPARATOR(1) SSP1 UART0/1 I2C0/1 CAN 0/1 TIMER 0/1 WINDOWED WDT 12-bit ADC PWM0/1 PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS EVENT RECORDER 32 kHz OSCILLATOR APB slave group 1 APB slave group 0 RTC POWER DOMAIN LPC408x/7x master ETHERNET(1) master USB DEVICE/ HOST(1)/OTG(1) master 002aag491 slave slave CRC slave SPIFI slave slave slave slave EMC(1) ROM slave slave LCD(1) slave MULTILAYER AHB MATRIX I2C2 TIMER2/3 DAC I2S QUADRATURE ENCODER(1) MOTOR CONTROL PWM MPU FPU(1) SD/MMC(1) = connected to GPDMA LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 8 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 6. Pinning information 6.1 Pinning Fig 2. Pin configuration (LQFP208) Fig 3. Pin configuration (LQFP144) Fig 4. Pin configuration (LQFP100) LPC408x/7x 156 53 104 208 157 105 1 52 002aag732 LPC408x/7x 108 37 72 144 109 73 1 36 002aag735 LPC407x 50 1 25 75 51 26 76 100 002aah638 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 9 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 5. Pin configuration (LQFP80) Fig 6. Pin configuration (TFBGA208) 40 1 20 60 41 21 61 80 002aag865 LPC408x/7x 002aag733 LPC408x/7x Transparent top view ball A1 index area U T R P N M K H L J G F E D C A B 2 4 6 8 10 12 13 14 15 17 16 1 3 5 7 9 11 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 10 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 6.2 Pin description I/O pins on the LPC408x/7x are 5 V tolerant and have input hysteresis unless otherwise indicated in the table below. Crystal pins, power pins, and reference voltage pins are not 5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5 V tolerant and the input voltage must be limited to the voltage at the ADC positive reference pin (VREFP). All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 in the order defined by the FUNC bits of the corresponding IOCON register up to the highest used function number. Each port pin can support up to eight multiplexed functions. IOCON register FUNC values which are reserved are noted as “R” in the pin configuration table. Fig 7. Pin configuration (TFBGA180) Fig 8. Pin configuration (TFBGA80) 002aag734 LPC408x/7x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ball A1 index area P N M L K J G E H F D C B A Transparent top view 002aah684 LPC4072FET80 Transparent top view 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K ball A1 index area xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 11 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Table 3. Pin description Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. P0[0] 94 U15 M10 66 46 37 J9 [3] I; PU I/O P0[0] — General purpose digital input/output pin. I CAN_RD1 — CAN1 receiver input. O U3_TXD — Transmitter output for UART3. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). O U0_TXD — Transmitter output for UART0. P0[1] 96 T14 N11 67 47 38 J10 [3] I; PU I/O P0[1] — General purpose digital input/output pin. O CAN_TD1 — CAN1 transmitter output. I U3_RXD — Receiver input for UART3. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). I U0_RXD — Receiver input for UART0. P0[2] 202 C4 D5 141 98 79 A2 [3] I; PU I/O P0[2] — General purpose digital input/output pin. O U0_TXD — Transmitter output for UART0. O U3_TXD — Transmitter output for UART3. P0[3] 204 D6 A3 142 99 80 A1 [3] I; PU I/O P0[3] — General purpose digital input/output pin. I U0_RXD — Receiver input for UART0. I U3_RXD — Receiver input for UART3. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 12 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[4] 168 B12 A11 116 81 - - [3] I; PU I/O P0[4] — General purpose digital input/output pin. I/O I2S_RX_SCK — I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I CAN_RD2 — CAN2 receiver input. I T2_CAP0 — Capture input for Timer 2, channel 0. - R — Function reserved. I/O CMP_ROSC — Comparator relaxation oscillator for 555 timer applications. - R — Function reserved. O LCD_VD[0] — LCD data. P0[5] 166 C12 B11 115 80 - - [3] I; PU I/O P0[5] — General purpose digital input/output pin. I/O I2S_RX_WS — I2S Receive word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O CAN_TD2 — CAN2 transmitter output. I T2_CAP1 — Capture input for Timer 2, channel 1. - R — Function reserved. I CMP_RESET — Comparator reset. - R — Function reserved. O LCD_VD[1] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 13 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[6] 164 D13 D11 113 79 64 A7 [3] I; PU I/O P0[6] — General purpose digital input/output pin. I/O I2S_RX_SDA — I2S Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SSP1_SSEL — Slave Select for SSP1. O T2_MAT0 — Match output for Timer 2, channel 0. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O CMP_ROSC — Comparator relaxation oscillator for 555 timer applications. - R — Function reserved. O LCD_VD[8] — LCD data. P0[7] 162 C13 B12 112 78 63 A8 [4] I; IA I/O P0[7] — General purpose digital input/output pin. I/O I2S_TX_SCK — I2S transmit clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O SSP1_SCK — Serial Clock for SSP1. O T2_MAT1 — Match output for Timer 2, channel 1. I RTC_EV0 — Event input 0 to Event Monitor/Recorder. I CMP_VREF — Comparator reference voltage. - R — Function reserved. O LCD_VD[9] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 14 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[8] 160 A15 C12 111 77 62 A10 [4] I; IA I/O P0[8] — General purpose digital input/output pin. I/O I2S_TX_WS — I2S Transmit word select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O SSP1_MISO — Master In Slave Out for SSP1. O T2_MAT2 — Match output for Timer 2, channel 2. I RTC_EV1 — Event input 1 to Event Monitor/Recorder. I CMP1_IN[3] — Comparator 1, input 3. - R — Function reserved. O LCD_VD[16] — LCD data. P0[9] 158 C14 A13 109 76 61 A9 [4] I; IA I/O P0[9] — General purpose digital input/output pin. I/O I2S_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SSP1_MOSI — Master Out Slave In for SSP1. O T2_MAT3 — Match output for Timer 2, channel 3. I RTC_EV2 — Event input 2 to Event Monitor/Recorder. I CMP1_IN[2] — Comparator 1, input 2. - R — Function reserved. O LCD_VD[17] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 15 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[10] 98 T15 L10 69 48 39 K9 [3] I; PU I/O P0[10] — General purpose digital input/output pin. O U2_TXD — Transmitter output for UART2. I/O I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). O T3_MAT0 — Match output for Timer 3, channel 0. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[5] — LCD data. P0[11] 100 R14 P12 70 49 40 K10 [3] I; PU I/O P0[11] — General purpose digital input/output pin. I U2_RXD — Receiver input for UART2. I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). O T3_MAT1 — Match output for Timer 3, channel 1. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[10] — LCD data. P0[12] 41 R1 J4 29 - - - [5] I; PU I/O P0[12] — General purpose digital input/output pin. O USB_PPWR2 — Port Power enable signal for USB port 2. I/O SSP1_MISO — Master In Slave Out for SSP1. I ADC0_IN[6] — A/D converter 0, input 6. When configured as an ADC input, the digital function of the pin must be disabled. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 16 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[13] 45 R2 J5 32 - - - [5] I; PU I/O P0[13] — General purpose digital input/output pin. O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. I/O SSP1_MOSI — Master Out Slave In for SSP1. I ADC0_IN[7] — A/D converter 0, input 7. When configured as an ADC input, the digital function of the pin must be disabled. P0[14] 69 T7 M5 48 - - - [3] I; PU I/O P0[14] — General purpose digital input/output pin. O USB_HSTEN2 — Host Enabled status for USB port 2. I/O SSP1_SSEL — Slave Select for SSP1. O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. P0[15] 128 J16 H13 89 62 47 F9 [3] I; PU I/O P0[15] — General purpose digital input/output pin. O U1_TXD — Transmitter output for UART1. I/O SSP0_SCK — Serial clock for SSP0. - R — Function reserved. - R — Function reserved. I/O SPIFI_IO[2] — Data bit 0 for SPIFI. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 17 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[16] 130 J14 H14 90 63 48 F8 [3] I; PU I/O P0[16] — General purpose digital input/output pin. I U1_RXD — Receiver input for UART1. I/O SSP0_SSEL — Slave Select for SSP0. - R — Function reserved. - R — Function reserved. I/O SPIFI_IO[3] — Data bit 0 for SPIFI. P0[17] 126 K17 J12 87 61 46 F10 [3] I; PU I/O P0[17] — General purpose digital input/output pin. I U1_CTS — Clear to Send input for UART1. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved. - R — Function reserved. I/O SPIFI_IO[1] — Data bit 0 for SPIFI. P0[18] 124 K15 J13 86 60 45 G10 [3] I; PU I/O P0[18] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1. I/O SSP0_MOSI — Master Out Slave In for SSP0. - R — Function reserved. - R — Function reserved. I/O SPIFI_IO[0] — Data bit 0 for SPIFI. P0[19] 122 L17 J10 85 59 - - [3] I; PU I/O P0[19] — General purpose digital input/output pin. I U1_DSR — Data Set Ready input for UART1. O SD_CLK — Clock output line for SD card interface. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[13] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 18 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[20] 120 M17 K14 83 58 - - [3] I; PU I/O P0[20] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O SD_CMD — Command line for SD card interface. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_VD[14] — LCD data. P0[21] 118 M16 K11 82 57 - - [3] I; PU I/O P0[21] — General purpose digital input/output pin. I U1_RI — Ring Indicator input for UART1. O SD_PWR — Power Supply Enable for external SD card power supply. O U4_OE — RS-485/EIA-485 output enable signal for UART4. I CAN_RD1 — CAN1 receiver input. I/O U4_SCLK — USART 4 clock input or output in synchronous mode. P0[22] 116 N17 L14 80 56 44 H10 [6] I; PU I/O P0[22] — General purpose digital input/output pin. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. I/O SD_DAT[0] — Data line 0 for SD card interface. O U4_TXD — Transmitter output for USART4 (input/output in smart card mode). O CAN_TD1 — CAN1 transmitter output. O SPIFI_CLK — Clock output for SPIFI. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 19 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[23] 18 H1 F5 13 9 - - [5] I; PU I/O P0[23] — General purpose digital input/output pin. I ADC0_IN[0] — A/D converter 0, input 0. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SCK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I T3_CAP0 — Capture input for Timer 3, channel 0. P0[24] 16 G2 E1 11 8 - - [5] I; PU I/O P0[24] — General purpose digital input/output pin. I ADC0_IN[1] — A/D converter 0, input 1. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I T3_CAP1 — Capture input for Timer 3, channel 1. P0[25] 14 F1 E4 10 7 7 D1 [5] I; PU I/O P0[25] — General purpose digital input/output pin. I ADC0_IN[2] — A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O U3_TXD — Transmitter output for UART3. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 20 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P0[26] 12 E1 D1 8 6 6 D2 [7] I; PU I/O P0[26] — General purpose digital input/output pin. I ADC0_IN[3] — A/D converter 0, input 3. When configured as an ADC input, the digital function of the pin must be disabled. O DAC_OUT — D/A converter output. When configured as the DAC output, the digital function of the pin must be disabled. I U3_RXD — Receiver input for UART3. P0[27] 50 T1 L3 35 25 - - [8] I I/O P0[27] — General purpose digital input/output pin. I/O I2C0_SDA — I2C0 data input/output. (This pin uses a specialized I2C pad). I/O USB_SDA1 — I2C serial data for communication with an external USB transceiver. P0[28] 48 R3 M1 34 24 - - [8] I I/O P0[28] — General purpose digital input/output pin. I/O I2C0_SCL — I2C0 clock input/output (this pin uses a specialized I2C pad. I/O USB_SCL1 — I2C serial clock for communication with an external USB transceiver. P0[29] 61 U4 K5 42 29 22 J3 [9] I I/O P0[29] — General purpose digital input/output pin. I/O USB_D+1 — USB port 1 bidirectional D+ line. I EINT0 — External interrupt 0 input. P0[30] 62 R6 N4 43 30 23 K3 [9] I I/O P0[30] — General purpose digital input/output pin. I/O USB_D1 — USB port 1 bidirectional D line. I EINT1 — External interrupt 1 input. P0[31] 51 T2 N1 36 - - - [9] I I/O P0[31] — General purpose digital input/output pin. I/O USB_D+2 — USB port 2 bidirectional D+ line. P1[0] to P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 21 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[0] 196 A3 B5 136 95 76 A3 [3] I; PU I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). - R — Function reserved. I T3_CAP1 — Capture input for Timer 3, channel 1. I/O SSP2_SCK — Serial clock for SSP2. P1[1] 194 B5 A5 135 94 75 B4 [3] I; PU I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). - R — Function reserved. O T3_MAT3 — Match output for Timer 3, channel 3. I/O SSP2_MOSI — Master Out Slave In for SSP2. P1[2] 185 D9 B7 - - - - [3] I; PU I/O P1[2] — General purpose digital input/output pin. O ENET_TXD2 — Ethernet transmit data 2 (MII interface). O SD_CLK — Clock output line for SD card interface. O PWM0[1] — Pulse Width Modulator 0, output 1. P1[3] 177 A10 A9 - - - - [3] I; PU I/O P1[3] — General purpose digital input/output pin. O ENET_TXD3 — Ethernet transmit data 3 (MII interface). I/O SD_CMD — Command line for SD card interface. O PWM0[2] — Pulse Width Modulator 0, output 2. P1[4] 192 A5 C6 133 93 74 B5 [3] I; PU I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface). - R — Function reserved. O T3_MAT2 — Match output for Timer 3, channel 2. I/O SSP2_MISO — Master In Slave Out for SSP2. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 22 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[5] 156 A17 B13 - - - - [3] I; PU I/O P1[5] — General purpose digital input/output pin. O ENET_TX_ER — Ethernet Transmit Error (MII interface). O SD_PWR — Power Supply Enable for external SD card power supply. O PWM0[3] — Pulse Width Modulator 0, output 3. - R — Function reserved. I CMP1_IN[1] — Comparator 1, input 1. P1[6] 171 B11 B10 - - - - [3] I; PU I/O P1[6] — General purpose digital input/output pin. I ENET_TX_CLK — Ethernet Transmit Clock (MII interface). I/O SD_DAT[0] — Data line 0 for SD card interface. O PWM0[4] — Pulse Width Modulator 0, output 4. - R — Function reserved. I CMP0_IN[3] — Comparator 0, input 3. P1[7] 153 D14 C13 - - - - [3] I; PU I/O P1[7] — General purpose digital input/output pin. I ENET_COL — Ethernet Collision detect (MII interface). I/O SD_DAT[1] — Data line 1 for SD card interface. O PWM0[5] — Pulse Width Modulator 0, output 5. - R — Function reserved. I CMP1_IN[0] — Comparator 1, input 0. P1[8] 190 C7 B6 132 92 73 C5 [3] I; PU I/O P1[8] — General purpose digital input/output pin. I ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII interface) or Ethernet Carrier Sense/Data Valid (RMII interface). - R — Function reserved. O T3_MAT1 — Match output for Timer 3, channel 1. I/O SSP2_SSEL — Slave Select for SSP2. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 23 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[9] 188 A6 D7 131 91 72 A4 [3] I; PU I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). - R — Function reserved. O T3_MAT0 — Match output for Timer 3, channel 0. P1[10] 186 C8 A7 129 90 71 A5 [3] I; PU I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). - R — Function reserved. I T3_CAP0 — Capture input for Timer 3, channel 0. P1[11] 163 A14 A12 - - - - [3] I; PU I/O P1[11] — General purpose digital input/output pin. I ENET_RXD2 — Ethernet Receive Data 2 (MII interface). I/O SD_DAT[2] — Data line 2 for SD card interface. O PWM0[6] — Pulse Width Modulator 0, output 6. P1[12] 157 A16 A14 - - - - [3] I; PU I/O P1[12] — General purpose digital input/output pin. I ENET_RXD3 — Ethernet Receive Data (MII interface). I/O SD_DAT[3] — Data line 3 for SD card interface. I PWM0_CAP0 — Capture input for PWM0, channel 0. - R — Function reserved. O CMP1_OUT — Comparator 1, output. P1[13] 147 D16 D14 - - - - [3] I; PU I/O P1[13] — General purpose digital input/output pin. I ENET_RX_DV — Ethernet Receive Data Valid (MII interface). Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 24 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[14] 184 A7 D8 128 89 70 C6 [3] I; PU I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error (RMII/MII interface). - R — Function reserved. I T2_CAP0 — Capture input for Timer 2, channel 0. - R — Function reserved. I CMP0_IN[0] — Comparator 0, input 0. P1[15] 182 A8 A8 126 88 69 B6 [3] I; PU I/O P1[15] — General purpose digital input/output pin. I ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock (MII interface) or Ethernet Reference Clock (RMII interface). - R — Function reserved. I/O I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). P1[16] 180 D10 B8 125 87 - - [3] I; PU I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock. O I2S_TX_MCLK — I2S transmit master clock. - R — Function reserved. - R — Function reserved. I CMP0_IN[1] — Comparator 0, input 1. P1[17] 178 A9 C9 123 86 - - [3] I; PU I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. O I2S_RX_MCLK — I2S receive master clock. - R — Function reserved. - R — Function reserved. I CMP0_IN[2] — Comparator 0, input 2. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 25 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[18] 66 P7 L5 46 32 25 K4 [3] I; PU I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED1 — It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I T1_CAP0 — Capture input for Timer 1, channel 0. - R — Function reserved. I/O SSP1_MISO — Master In Slave Out for SSP1. P1[19] 68 U6 P5 47 33 26 J4 [3] I; PU I/O P1[19] — General purpose digital input/output pin. O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). O USB_PPWR1 — Port Power enable signal for USB port 1. I T1_CAP1 — Capture input for Timer 1, channel 1. O MC_0A — Motor control PWM channel 0, output A. I/O SSP1_SCK — Serial clock for SSP1. O U2_OE — RS-485/EIA-485 output enable signal for UART2. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 26 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[20] 70 U7 K6 49 34 27 J5 [3] I; PU I/O P1[20] — General purpose digital input/output pin. O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver). O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I QEI_PHA — Quadrature Encoder Interface PHA input. I MC_FB0 — Motor control PWM channel 0 feedback input. I/O SSP0_SCK — Serial clock for SSP0. O LCD_VD[6] — LCD data. O LCD_VD[10] — LCD data. P1[21] 72 R8 N6 50 35 - - [3] I; PU I/O P1[21] — General purpose digital input/output pin. O USB_TX_DM1 — D transmit data for USB port 1 (OTG transceiver). O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSP0_SSEL — Slave Select for SSP0. I MC_ABORT — Motor control PWM, active low fast abort. - R — Function reserved. O LCD_VD[7] — LCD data. O LCD_VD[11] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 27 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[22] 74 U8 M6 51 36 28 K5 [3] I; PU I/O P1[22] — General purpose digital input/output pin. I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver). I USB_PWRD1 — Power Status for USB port 1 (host power switch). O T1_MAT0 — Match output for Timer 1, channel 0. O MC_0B — Motor control PWM channel 0, output B. I/O SSP1_MOSI — Master Out Slave In for SSP1. O LCD_VD[8] — LCD data. O LCD_VD[12] — LCD data. P1[23] 76 P9 N7 53 37 29 H5 [3] I; PU I/O P1[23] — General purpose digital input/output pin. I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver). O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I QEI_PHB — Quadrature Encoder Interface PHB input. I MC_FB1 — Motor control PWM channel 1 feedback input. I/O SSP0_MISO — Master In Slave Out for SSP0. O LCD_VD[9] — LCD data. O LCD_VD[13] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 28 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[24] 78 T9 P7 54 38 30 J6 [3] I; PU I/O P1[24] — General purpose digital input/output pin. I USB_RX_DM1 — D receive data for USB port 1 (OTG transceiver). O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I QEI_IDX — Quadrature Encoder Interface INDEX input. I MC_FB2 — Motor control PWM channel 2 feedback input. I/O SSP0_MOSI — Master Out Slave in for SSP0. O LCD_VD[10] — LCD data. O LCD_VD[14] — LCD data. P1[25] 80 T10 L7 56 39 31 K6 [3] I; PU I/O P1[25] — General purpose digital input/output pin. O USB_LS1 — Low Speed status for USB port 1 (OTG transceiver). O USB_HSTEN1 — Host Enabled status for USB port 1. O T1_MAT1 — Match output for Timer 1, channel 1. O MC_1A — Motor control PWM channel 1, output A. O CLKOUT — Selectable clock output. O LCD_VD[11] — LCD data. O LCD_VD[15] — LCD data. P1[26] 82 R10 P8 57 40 32 H6 [3] I; PU I/O P1[26] — General purpose digital input/output pin. O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I T0_CAP0 — Capture input for Timer 0, channel 0. O MC_1B — Motor control PWM channel 1, output B. I/O SSP1_SSEL — Slave Select for SSP1. O LCD_VD[12] — LCD data. O LCD_VD[20] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 29 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[27] 88 T12 M9 61 43 - - [3] I; PU I/O P1[27] — General purpose digital input/output pin. I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver). I USB_OVRCR1 — USB port 1 Over-Current status. I T0_CAP1 — Capture input for Timer 0, channel 1. O CLKOUT — Selectable clock output. - R — Function reserved. O LCD_VD[13] — LCD data. O LCD_VD[21] — LCD data. P1[28] 90 T13 P10 63 44 35 J8 [3] I; PU I/O P1[28] — General purpose digital input/output pin. I/O USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver). I PWM1_CAP0 — Capture input for PWM1, channel 0. O T0_MAT0 — Match output for Timer 0, channel 0. O MC_2A — Motor control PWM channel 2, output A. I/O SSP0_SSEL — Slave Select for SSP0. O LCD_VD[14] — LCD data. O LCD_VD[22] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 30 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P1[29] 92 U14 N10 64 45 36 K8 [3] I; PU I/O P1[29] — General purpose digital input/output pin. I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver). I PWM1_CAP1 — Capture input for PWM1, channel 1. O T0_MAT1 — Match output for Timer 0, channel 1. O MC_2B — Motor control PWM channel 2, output B. O U4_TXD — Transmitter output for USART4 (input/output in smart card mode). O LCD_VD[15] — LCD data. O LCD_VD[23] — LCD data. P1[30] 42 P2 K3 30 21 18 J2 [5] I; PU I/O P1[30] — General purpose digital input/output pin. I USB_PWRD2 — Power Status for USB port 2. I USB_VBUS — Monitors the presence of USB bus power. This signal must be HIGH for USB reset to occur. I ADC0_IN[4] — A/D converter 0, input 4. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2C0_SDA — I2C0 data input/output (this pin does not use a specialized I2C pad. O U3_OE — RS-485/EIA-485 output enable signal for UART3. P1[31] 40 P1 K2 28 20 17 H2 [5] I; PU I/O P1[31] — General purpose digital input/output pin. I USB_OVRCR2 — Over-Current status for USB port 2. I/O SSP1_SCK — Serial Clock for SSP1. I ADC0_IN[5] — A/D converter 0, input 5. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2C0_SCL — I2C0 clock input/output (this pin does not use a specialized I2C pad. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 31 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[0] to P2[31] I/O Port 2: Port 2 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. P2[0] 154 B17 D12 107 75 60 B10 [3] I; PU I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O U1_TXD — Transmitter output for UART1. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_PWR — LCD panel power enable. P2[1] 152 E14 C14 106 74 59 B8 [3] I; PU I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I U1_RXD — Receiver input for UART1. - R — Function reserved. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_LE — Line end signal. P2[2] 150 D15 E11 105 73 58 B9 [3] I; PU I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I U1_CTS — Clear to Send input for UART1. O T2_MAT3 — Match output for Timer 2, channel 3. - R — Function reserved. O TRACEDATA[3] — Trace data, bit 3. - R — Function reserved. O LCD_DCLK — LCD panel clock. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 32 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[3] 144 E16 E13 100 70 55 C10 [3] I; PU I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I U1_DCD — Data Carrier Detect input for UART1. O T2_MAT2 — Match output for Timer 2, channel 2. - R — Function reserved. O TRACEDATA[2] — Trace data, bit 2. - R — Function reserved. O LCD_FP — Frame pulse (STN). Vertical synchronization pulse (TFT). P2[4] 142 D17 E14 99 69 54 C9 [3] I; PU I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I U1_DSR — Data Set Ready input for UART1. O T2_MAT1 — Match output for Timer 2, channel 1. - R — Function reserved. O TRACEDATA[1] — Trace data, bit 1. - R — Function reserved. O LCD_ENAB_M — STN AC bias drive or TFT data enable output. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 33 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[5] 140 F16 F12 97 68 53 D10 [3] I; PU I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. O T2_MAT0 — Match output for Timer 2, channel 0. - R — Function reserved. O TRACEDATA[0] — Trace data, bit 0. - R — Function reserved. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT). P2[6] 138 E17 F13 96 67 52 E8 [3] I; PU I/O P2[6] — General purpose digital input/output pin. I PWM1_CAP0 — Capture input for PWM1, channel 0. I U1_RI — Ring Indicator input for UART1. I T2_CAP0 — Capture input for Timer 2, channel 0. O U2_OE — RS-485/EIA-485 output enable signal for UART2. O TRACECLK — Trace clock. O LCD_VD[0] — LCD data. O LCD_VD[4] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 34 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[7] 136 G16 G11 95 66 51 D9 [3] I; PU I/O P2[7] — General purpose digital input/output pin. I CAN_RD2 — CAN2 receiver input. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. - R — Function reserved. - R — Function reserved. O SPIFI_CS — Chip select output for SPIFI. O LCD_VD[1] — LCD data. O LCD_VD[5] — LCD data. P2[8] 134 H15 G14 93 65 50 E9 [3] I; PU I/O P2[8] — General purpose digital input/output pin. O CAN_TD2 — CAN2 transmitter output. O U2_TXD — Transmitter output for UART2. I U1_CTS — Clear to Send input for UART1. O ENET_MDC — Ethernet MIIM clock. - R — Function reserved. O LCD_VD[2] — LCD data. O LCD_VD[6] — LCD data. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 35 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[9] 132 H16 H11 92 64 49 E10 [3] I; PU I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch an external 1.5 k resistor under the software control. Used with the SoftConnect USB feature. I U2_RXD — Receiver input for UART2. I U4_RXD — Receiver input for USART4. I/O ENET_MDIO — Ethernet MIIM data input and output. - R — Function reserved. I LCD_VD[3] — LCD data. I LCD_VD[7] — LCD data. P2[10] 110 N15 M13 76 53 41 H9 [10] I; PU I/O P2[10] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. A LOW on this pin while RESET is LOW forces the on-chip boot loader to take over control of the part after a reset and go into ISP mode. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. P2[11] 108 T17 M12 75 52 - - [10] I; PU I/O P2[11] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT1 — External interrupt 1 input. I/O SD_DAT[1] — Data line 1 for SD card interface. I/O I2S_TX_SCK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. - R — Function reserved. - R — Function reserved. - R — Function reserved. O LCD_CLKIN — LCD clock. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 36 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[12] 106 N14 N14 73 51 - - [10] I; PU I/O P2[12] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT2 — External interrupt 2 input. I/O SD_DAT[2] — Data line 2 for SD card interface. I/O I2S_TX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. O LCD_VD[4] — LCD data. O LCD_VD[3] — LCD data. O LCD_VD[8] — LCD data. O LCD_VD[18] — LCD data. P2[13] 102 T16 M11 71 50 - - [10] I; PU I/O P2[13] — General purpose digital input/output pin. This pin includes a 10 ns input glitch filter. I EINT3 — External interrupt 3 input. I/O SD_DAT[3] — Data line 3 for SD card interface. I/O I2S_TX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. - R — Function reserved. O LCD_VD[5] — LCD data. O LCD_VD[9] — LCD data. O LCD_VD[19] — LCD data. P2[14] 91 R12 - - - - - [3] I; PU I/O P2[14] — General purpose digital input/output pin. O EMC_CS2 — LOW active Chip Select 2 signal. I/O I2C1_SDA — I2C1 data input/output (this pin does not use a specialized I2C pad). I T2_CAP0 — Capture input for Timer 2, channel 0. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 37 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[15] 99 P13 - - - - - [3] I; PU I/O P2[15] — General purpose digital input/output pin. O EMC_CS3 — LOW active Chip Select 3 signal. I/O I2C1_SCL — I2C1 clock input/output (this pin does not use a specialized I2C pad). I T2_CAP1 — Capture input for Timer 2, channel 1. P2[16] 87 R11 P9 - - - - [3] I; PU I/O P2[16] — General purpose digital input/output pin. O EMC_CAS — LOW active SDRAM Column Address Strobe. P2[17] 95 R13 P11 - - - - [3] I; PU I/O P2[17] — General purpose digital input/output pin. O EMC_RAS — LOW active SDRAM Row Address Strobe. P2[18] 59 U3 P3 - - - - [6] I; PU I/O P2[18] — General purpose digital input/output pin. O EMC_CLK[0] — SDRAM clock 0. P2[19] 67 R7 N5 - - - - [6] I; PU I/O P2[19] — General purpose digital input/output pin. O EMC_CLK[1] — SDRAM clock 1. P2[20] 73 T8 P6 - - - - [3] I; PU I/O P2[20] — General purpose digital input/output pin. O EMC_DYCS0 — SDRAM chip select 0. P2[21] 81 U11 N8 - - - - [3] I; PU I/O P2[21] — General purpose digital input/output pin. O EMC_DYCS1 — SDRAM chip select 1. P2[22] 85 U12 - - - - - [3] I; PU I/O P2[22] — General purpose digital input/output pin. O EMC_DYCS2 — SDRAM chip select 2. I/O SSP0_SCK — Serial clock for SSP0. I T3_CAP0 — Capture input for Timer 3, channel 0. P2[23] 64 U5 - - - - - [3] I; PU I/O P2[23] — General purpose digital input/output pin. O EMC_DYCS3 — SDRAM chip select 3. I/O SSP0_SSEL — Slave Select for SSP0. I T3_CAP1 — Capture input for Timer 3, channel 1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 38 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[24] 53 P5 P1 - - - - [3] I; PU I/O P2[24] — General purpose digital input/output pin. O EMC_CKE0 — SDRAM clock enable 0. P2[25] 54 R4 P2 - - - - [3] I; PU I/O P2[25] — General purpose digital input/output pin. O EMC_CKE1 — SDRAM clock enable 1. P2[26] 57 T4 - - - - - [3] I; PU I/O P2[26] — General purpose digital input/output pin. O EMC_CKE2 — SDRAM clock enable 2. I/O SSP0_MISO — Master In Slave Out for SSP0. O T3_MAT0 — Match output for Timer 3, channel 0. P2[27] 47 P3 - - - - - [3] I; PU I/O P2[27] — General purpose digital input/output pin. O EMC_CKE3 — SDRAM clock enable 3. I/O SSP0_MOSI — Master Out Slave In for SSP0. O T3_MAT1 — Match output for Timer 3, channel 1. P2[28] 49 P4 M2 - - - - [3] I; PU I/O P2[28] — General purpose digital input/output pin. O EMC_DQM0 — Data mask 0 used with SDRAM and static devices. P2[29] 43 N3 L1 - - - - [3] I; PU I/O P2[29] — General purpose digital input/output pin. O EMC_DQM1 — Data mask 1 used with SDRAM and static devices. P2[30] 31 L4 - - - - - [3] I; PU I/O P2[30] — General purpose digital input/output pin. O EMC_DQM2 — Data mask 2 used with SDRAM and static devices. I/O I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). O T3_MAT2 — Match output for Timer 3, channel 2. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 39 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P2[31] 39 N2 - - - - - [3] I; PU I/O P2[31] — General purpose digital input/output pin. O EMC_DQM3 — Data mask 3 used with SDRAM and static devices. I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). O T3_MAT3 — Match output for Timer 3, channel 3. P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. P3[0] 197 B4 D6 137 - - - [3] I; PU I/O P3[0] — General purpose digital input/output pin. I/O EMC_D[0] — External memory data line 0. P3[1] 201 B3 E6 140 - - - [3] I; PU I/O P3[1] — General purpose digital input/output pin. I/O EMC_D[1] — External memory data line 1. P3[2] 207 B1 A2 144 - - - [3] I; PU I/O P3[2] — General purpose digital input/output pin. I/O EMC_D[2] — External memory data line 2. P3[3] 3 E4 G5 2 - - - [3] I; PU I/O P3[3] — General purpose digital input/output pin. I/O EMC_D[3] — External memory data line 3. P3[4] 13 F2 D3 9 - - - [3] I; PU I/O P3[4] — General purpose digital input/output pin. I/O EMC_D[4] — External memory data line 4. P3[5] 17 G1 E3 12 - - - [3] I; PU I/O P3[5] — General purpose digital input/output pin. I/O EMC_D[5] — External memory data line 5. P3[6] 23 J1 F4 16 - - - [3] I; PU I/O P3[6] — General purpose digital input/output pin. I/O EMC_D[6] — External memory data line 6. P3[7] 27 L1 G3 19 - - - [3] I; PU I/O P3[7] — General purpose digital input/output pin. I/O EMC_D[7] — External memory data line 7. P3[8] 191 D8 A6 - - - - [3] I; PU I/O P3[8] — General purpose digital input/output pin. I/O EMC_D[8] — External memory data line 8. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 40 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P3[9] 199 C5 A4 - - - - [3] I; PU I/O P3[9] — General purpose digital input/output pin. I/O EMC_D[9] — External memory data line 9. P3[10] 205 B2 B3 - - - - [3] I; PU I/O P3[10] — General purpose digital input/output pin. I/O EMC_D[10] — External memory data line 10. P3[11] 208 D5 B2 - - - - [3] I; PU I/O P3[11] — General purpose digital input/output pin. I/O EMC_D[11] — External memory data line 11. P3[12] 1 D4 A1 - - - - [3] I; PU I/O P3[12] — General purpose digital input/output pin. I/O EMC_D[12] — External memory data line 12. P3[13] 7 C1 C1 - - - - [3] I; PU I/O P3[13] — General purpose digital input/output pin. I/O EMC_D[13] — External memory data line 13. P3[14] 21 H2 F1 - - - - [3] I; PU I/O P3[14] — General purpose digital input/output pin. I/O EMC_D[14] — External memory data line 14. P3[15] 28 M1 G4 - - - - [3] I; PU I/O P3[15] — General purpose digital input/output pin. I/O EMC_D[15] — External memory data line 15. P3[16] 137 F17 - - - - - [3] I; PU I/O P3[16] — General purpose digital input/output pin. I/O EMC_D[16] — External memory data line 16. O PWM0[1] — Pulse Width Modulator 0, output 1. O U1_TXD — Transmitter output for UART1. P3[17] 143 F15 - - - - - [3] I; PU I/O P3[17] — General purpose digital input/output pin. I/O EMC_D[17] — External memory data line 17. O PWM0[2] — Pulse Width Modulator 0, output 2. I U1_RXD — Receiver input for UART1. P3[18] 151 C15 - - - - - [3] I; PU I/O P3[18] — General purpose digital input/output pin. I/O EMC_D[18] — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I U1_CTS — Clear to Send input for UART1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 41 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P3[19] 161 B14 - - - - - [3] I; PU I/O P3[19] — General purpose digital input/output pin. I/O EMC_D[19] — External memory data line 19. O PWM0[4] — Pulse Width Modulator 0, output 4. I U1_DCD — Data Carrier Detect input for UART1. P3[20] 167 A13 - - - - - [3] I; PU I/O P3[20] — General purpose digital input/output pin. I/O EMC_D[20] — External memory data line 20. O PWM0[5] — Pulse Width Modulator 0, output 5. I U1_DSR — Data Set Ready input for UART1. P3[21] 175 C10 - - - - - [3] I; PU I/O P3[21] — General purpose digital input/output pin. I/O EMC_D[21] — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. P3[22] 195 C6 - - - - - [3] I; PU I/O P3[22] — General purpose digital input/output pin. I/O EMC_D[22] — External memory data line 22. I PWM0_CAP0 — Capture input for PWM0, channel 0. I U1_RI — Ring Indicator input for UART1. P3[23] 65 T6 M4 45 - - - [3] I; PU I/O P3[23] — General purpose digital input/output pin. I/O EMC_D[23] — External memory data line 23. I PWM1_CAP0 — Capture input for PWM1, channel 0. I T0_CAP0 — Capture input for Timer 0, channel 0. P3[24] 58 R5 N3 40 - - - [3] I; PU I/O P3[24] — General purpose digital input/output pin. I/O EMC_D[24] — External memory data line 24. O PWM1[1] — Pulse Width Modulator 1, output 1. I T0_CAP1 — Capture input for Timer 0, channel 1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 42 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P3[25] 56 U2 M3 39 27 - - [3] I; PU I/O P3[25] — General purpose digital input/output pin. I/O EMC_D[25] — External memory data line 25. O PWM1[2] — Pulse Width Modulator 1, output 2. O T0_MAT0 — Match output for Timer 0, channel 0. P3[26] 55 T3 K7 38 26 - - [3] I; PU I/O P3[26] — General purpose digital input/output pin. I/O EMC_D[26] — External memory data line 26. O PWM1[3] — Pulse Width Modulator 1, output 3. O T0_MAT1 — Match output for Timer 0, channel 1. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. P3[27] 203 A1 - - - - - [3] I; PU I/O P3[27] — General purpose digital input/output pin. I/O EMC_D[27] — External memory data line 27. O PWM1[4] — Pulse Width Modulator 1, output 4. I T1_CAP0 — Capture input for Timer 1, channel 0. P3[28] 5 D2 - - - - - [3] I; PU I/O P3[28] — General purpose digital input/output pin. I/O EMC_D[28] — External memory data line 28. O PWM1[5] — Pulse Width Modulator 1, output 5. I T1_CAP1 — Capture input for Timer 1, channel 1. P3[29] 11 F3 - - - - - [3] I; PU I/O P3[29] — General purpose digital input/output pin. I/O EMC_D[29] — External memory data line 29. O PWM1[6] — Pulse Width Modulator 1, output 6. O T1_MAT0 — Match output for Timer 1, channel 0. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 43 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P3[30] 19 H3 - - - - - [3] I; PU I/O P3[30] — General purpose digital input/output pin. I/O EMC_D[30] — External memory data line 30. O U1_RTS — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal for UART1. O T1_MAT1 — Match output for Timer 1, channel 1. P3[31] 25 J3 - - - - - [3] I; PU I/O P3[31] — General purpose digital input/output pin. I/O EMC_D[31] — External memory data line 31. - R — Function reserved. O T1_MAT2 — Match output for Timer 1, channel 2. P4[0] to P4[31] - I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. P4[0] 75 U9 L6 52 - - - [3] I; PU I/O P4[0] — General purpose digital input/output pin. I/O EMC_A[0] — External memory address line 0. P4[1] 79 U10 M7 55 - - - [3] I; PU I/O P4[1] — General purpose digital input/output pin. I/O EMC_A[1] — External memory address line 1. P4[2] 83 T11 M8 58 - - - [3] I; PU I/O P4[2] — General purpose digital input/output pin. I/O EMC_A[2] — External memory address line 2. P4[3] 97 U16 K9 68 - - - [3] I; PU I/O P4[3] — General purpose digital input/output pin. I/O EMC_A[3] — External memory address line 3. P4[4] 103 R15 P13 72 - - - [3] I; PU I/O P4[4] — General purpose digital input/output pin. I/O EMC_A[4] — External memory address line 4. P4[5] 107 R16 H10 74 - - - [3] I; PU I/O P4[5] — General purpose digital input/output pin. I/O EMC_A[5] — External memory address line 5. P4[6] 113 M14 K10 78 - - - [3] I; PU I/O P4[6] — General purpose digital input/output pin. I/O EMC_A[6] — External memory address line 6. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 44 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P4[7] 121 L16 K12 84 - - - [3] I; PU I/O P4[7] — General purpose digital input/output pin. I/O EMC_A[7] — External memory address line 7. P4[8] 127 J17 J11 88 - - - [3] I; PU I/O P4[8] — General purpose digital input/output pin. I/O EMC_A[8] — External memory address line 8. P4[9] 131 H17 H12 91 - - - [3] I; PU I/O P4[9] — General purpose digital input/output pin. I/O EMC_A[9] — External memory address line 9. P4[10] 135 G17 G12 94 - - - [3] I; PU I/O P4[10] — General purpose digital input/output pin. I/O EMC_A[10] — External memory address line 10. P4[11] 145 F14 F11 101 - - - [3] I; PU I/O P4[11] — General purpose digital input/output pin. I/O EMC_A[11] — External memory address line 11. P4[12] 149 C16 F10 104 - - - [3] I; PU I/O P4[12] — General purpose digital input/output pin. I/O EMC_A[12] — External memory address line 12. P4[13] 155 B16 B14 108 - - - [3] I; PU I/O P4[13] — General purpose digital input/output pin. I/O EMC_A[13] — External memory address line 13. P4[14] 159 B15 E8 110 - - - [3] I; PU I/O P4[14] — General purpose digital input/output pin. I/O EMC_A[14] — External memory address line 14. P4[15] 173 A11 C10 120 - - - [3] I; PU I/O P4[15] — General purpose digital input/output pin. I/O EMC_A[15] — External memory address line 15. P4[16] 101 U17 N12 - - - - [3] I; PU I/O P4[16] — General purpose digital input/output pin. I/O EMC_A[16] — External memory address line 16. P4[17] 104 P14 N13 - - - - [3] I; PU I/O P4[17] — General purpose digital input/output pin. I/O EMC_A[17] — External memory address line 17. P4[18] 105 P15 P14 - - - - [3] I; PU I/O P4[18] — General purpose digital input/output pin. I/O EMC_A[18] — External memory address line 18. P4[19] 111 P16 M14 - - - - [3] I; PU I/O P4[19] — General purpose digital input/output pin. I/O EMC_A[19] — External memory address line 19. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 45 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P4[20] 109 R17 - - - - - [3] I; PU I/O P4[20] — General purpose digital input/output pin. I/O EMC_A[20] — External memory address line 20. I/O I2C2_SDA — I2C2 data input/output (this pin does not use a specialized I2C pad). I/O SSP1_SCK — Serial Clock for SSP1. P4[21] 115 M15 - - - - - [3] I; PU I/O P4[21] — General purpose digital input/output pin. I/O EMC_A[21] — External memory address line 21. I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). I/O SSP1_SSEL — Slave Select for SSP1. P4[22] 123 K14 - - - - - [3] I; PU I/O P4[22] — General purpose digital input/output pin. I/O EMC_A[22] — External memory address line 22. O U2_TXD — Transmitter output for UART2. I/O SSP1_MISO — Master In Slave Out for SSP1. P4[23] 129 J15 - - - - - [3] I; PU I/O P4[23] — General purpose digital input/output pin. I/O EMC_A[23] — External memory address line 23. I U2_RXD — Receiver input for UART2. I/O SSP1_MOSI — Master Out Slave In for SSP1. P4[24] 183 B8 C8 127 - - - [3] I; PU I/O P4[24] — General purpose digital input/output pin. O EMC_OE — LOW active Output Enable signal. P4[25] 179 B9 D9 124 - - - [3] I; PU I/O P4[25] — General purpose digital input/output pin. O EMC_WE — LOW active Write Enable signal. P4[26] 119 L15 K13 - - - - [3] I; PU I/O P4[26] — General purpose digital input/output pin. O EMC_BLS0 — LOW active Byte Lane select signal 0. P4[27] 139 G15 F14 - - - - [3] I; PU I/O P4[27] — General purpose digital input/output pin. O EMC_BLS1 — LOW active Byte Lane select signal 1. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 46 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P4[28] 170 C11 D10 118 82 65 B7 [3] I; PU I/O P4[28] — General purpose digital input/output pin. O EMC_BLS2 — LOW active Byte Lane select signal 2. O U3_TXD — Transmitter output for UART3. O T2_MAT0 — Match output for Timer 2, channel 0. - R — Function reserved. O LCD_VD[6] — LCD data. O LCD_VD[10] — LCD data. O LCD_VD[2] — LCD data. P4[29] 176 B10 B9 122 85 68 A6 [3] I; PU I/O P4[29] — General purpose digital input/output pin. O EMC_BLS3 — LOW active Byte Lane select signal 3. I U3_RXD — Receiver input for UART3. O T2_MAT1 — Match output for Timer 2, channel 1. I/O I2C2_SCL — I2C2 clock input/output (this pin does not use a specialized I2C pad). O LCD_VD[7] — LCD data. O LCD_VD[11] — LCD data. O LCD_VD[3] — LCD data. P4[30] 187 B7 C7 130 - - - [3] I; PU I/O P4[30] — General purpose digital input/output pin. O EMC_CS0 — LOW active Chip Select 0 signal. - R — Function reserved. - R — Function reserved. - R — Function reserved. O CMP0_OUT — Comparator 0, output. P4[31] 193 A4 E7 134 - - - [3] I; PU I/O P4[31] — General purpose digital input/output pin. O EMC_CS1 — LOW active Chip Select 1 signal. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 47 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P5[0] to P5[4] I/O Port 5: Port 5 is a 5-bit I/O port with individual direction controls for each bit. The operation of port 5 pins depends upon the pin function selected via the pin connect block. P5[0] 9 F4 E5 6 - - - [3] I; PU I/O P5[0] — General purpose digital input/output pin. I/O EMC_A[24] — External memory address line 24. I/O SSP2_MOSI — Master Out Slave In for SSP2. O T2_MAT2 — Match output for Timer 2, channel 2. P5[1] 30 J4 H1 21 - - G1 [3] I; PU I/O P5[1] — General purpose digital input/output pin. I/O EMC_A[25] — External memory address line 25. I/O SSP2_MISO — Master In Slave Out for SSP2. O T2_MAT3 — Match output for Timer 2, channel 3. P5[2] 117 L14 L12 81 - - - [11] I I/O P5[2] — General purpose digital input/output pin. - R — Function reserved. I/O SSP2_SCK — Serial clock for SSP2. When using this pin, the SSP2 bit rate is limited to 1 MHz. O T3_MAT2 — Match output for Timer 3, channel 2. - R — Function reserved. I/O I2C0_SDA — I2C0 data input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus). P5[3] 141 G14 G10 98 - - - [11] I I/O P5[3] — General purpose digital input/output pin. - R — Function reserved. I/O SSP2_SSEL — Slave select for SSP2. When using this pin, the SSP2 bit rate is limited to 1 MHz. - R — Function reserved. I U4_RXD — Receiver input for USART4. I/O I2C0_SCL — I2C0 clock input/output (this pin uses a specialized I2C pad that supports I2C Fast Mode Plus. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 48 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller P5[4] 206 C3 C4 143 100 - - [3] I; PU I/O P5[4] — General purpose digital input/output pin. O U0_OE — RS-485/EIA-485 output enable signal for UART0. - R — Function reserved. O T3_MAT3 — Match output for Timer 3, channel 3. O U4_TXD — Transmitter output for USART4 (input/output in smart card mode). JTAG_TDO (SWO) 2 D3 B1 1 1 1 B2 [3] O Test Data Out for JTAG interface. Also used as Serial wire trace output. JTAG_TDI 4 C2 C3 3 2 2 B1 [3] I Test Data In for JTAG interface. JTAG_TMS (SWDIO) 6 E3 C2 4 3 3 C2 [3] I Test Mode Select for JTAG interface. Also used as Serial wire debug data input/output. JTAG_TRST 8 D1 D4 5 4 4 C1 [3] I Test Reset for JTAG interface. JTAG_TCK (SWDCLK) 10 E2 D2 7 5 5 D3 [3] I Test Clock for JTAG interface. This clock must be slower than 1 /6 of the CPU clock (CCLK) for the JTAG interface to operate. Also used as serial wire clock. RESET 35 M2 J1 24 17 14 G3 [12] I External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin also serves as the debug select input. LOW level selects the JTAG boundary scan. HIGH level selects the ARM SWD debug mode. RSTOUT 29 K3 H2 20 14 11 F1 [3] O Reset status output. A LOW output on this pin indicates that the device is in the reset state for any reason. This reflects the RESET input pin and all internal reset sources. RTC_ALARM 37 N1 H5 26 - - - [13] O RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. RTCX1 34 K2 J2 23 16 13 F2 [14] [15] I Input to the RTC 32 kHz ultra-low power oscillator circuit. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 49 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller RTCX2 36 L2 J3 25 18 15 G2 [14] [15] O Output from the RTC 32 kHz ultra-low power oscillator circuit. USB_D2 52 U1 N2 37 - - - [9] I/O USB port 2 bidirectional D line. VBAT 38 M3 K1 27 19 16 H1 I RTC power supply: 3.3 V on this pin supplies power to the RTC. VDD(REG)(3V3) 26, 86, 174 H4, P11, D11 G1, N9, E9 18, 60, 121 13, 42, 84 34, 67 K7, C7 S 3.3 V regulator supply voltage: This is the power supply for the on-chip voltage regulator that supplies internal logic. VDDA 20 G4 F2 14 10 8 E3 S Analog 3.3 V pad supply voltage: This can be connected to the same supply as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Tie this pin to 3.3 V if the ADC and DAC are not used. VDD(3V3) 15, 60, 71, 89, 112, 125, 146, 165, 181, 198 G3, P6, P8, U13, P17, K16, C17, B13, C9, D7 E2, L4, K8, L11, J14, E12, E10, C5 41, 62, 77, 102, 114, 138 28, 54, 71, 96 21, 42, 56, 77 K2, H7, D8, C4 S 3.3 V supply voltage: This is the power supply voltage for I/O other than pins in the VBAT domain. VREFP 24 K1 G2 17 12 10 E1 S ADC positive reference voltage: This should be the same voltage as VDDA, but should be isolated to minimize noise and error. The voltage level on this pin is used as a reference for ADC and DAC. Tie this pin to 3.3 V if the ADC and DAC are not used. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 50 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption. [2] I = Input; O = Output; G = Ground; S = Supply. [3] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. This pad can be powered by VBAT. [5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the pad is disabled. [6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL levels and hysteresis. [7] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. VSS 33, 63, 77, 93, 114, 133, 148, 169, 189, 200 L3, T5, R9, P12, N16, H14, E15, A12, B6, A2 H4, P4, L9, L13, G13, D13, C11, B4 44, 65, 79, 103, 117, 139 31, 55, 72, 97 24, 43, 57, 78 H4, G8, G9, B3 G Ground: 0 V reference for digital IO pins. VSSREG 32, 84, 172 D12, K4, P10 H3, L8, A10 22, 59, 119 15, 41, 83 33, 66 J7, F3 G Ground: 0 V reference for internal logic. VSSA 22 J2 F3 15 11 9 E2 G Analog ground: 0 V power supply and reference for the ADC and DAC. This should be the same voltage as VSS, but should be isolated to minimize noise and error. XTAL1 44 M4 L2 31 22 19 J1 [14] [16] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 46 N4 K4 33 23 20 K1 [14] [16] O Output from the oscillator amplifier. DNC - - - - - 12 - Do not connect. Table 3. Pin description …continued Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, comparator pins) and Table 5 (EMC pins). Symbol Pin LQFP208 Ball TFBGA208 Ball TFBGA180 Pin LQFP144 Pin LQFP100 Pin LQFP80 Pin TFBGA80 Reset state[1] Type[2] Description xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 51 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [10] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [13] This pad can be powered from VBAT. [14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be used to drive the RTCX1 pin. [15] If the RTC is not used, these pins can be left floating. [16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 52 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC408x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 7.2 ARM Cortex-M4 processor The ARM Cortex-M4 processor is running at frequencies of up to 120 MHz. The processor executes the Thumb-2 instruction set for optimal performance and code size, including hardware division, single-cycle multiply, and bit-field manipulation. A Memory Protection Unit (MPU) supporting eight regions is included. 7.3 ARM Cortex-M4 Floating Point Unit (FPU) Remark: The FPU is available on parts LP4088/78/76. The FPU supports single-precision floating-point computation functionality in compliance with the ANSI/IEEE Standard 754-2008. The FPU provides add, subtract, multiply, divide, multiply and accumulate, and square root operations. It also performs a variety of conversions between fixed-point, floating-point, and integer data formats. 7.4 On-chip flash program memory The LPC408x/7x contain up to 512 kB of on-chip flash program memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 7.5 EEPROM The LPC408x/7x contains up to 4032 byte of on-chip byte-erasable and byte-programmable EEPROM data memory. 7.6 On-chip SRAM The LPC408x/7x contain a total of up to 96 kB on-chip SRAM data memory. This includes 64 kB main SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB peripheral SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 53 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.7 Memory Protection Unit (MPU) The LPC408x/7x have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to eight regions each of which can be divided into eight subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 7.8 Memory map Table 4. LPC408x/7x memory usage and details Address range General Use Address range details and description 0x0000 0000 to 0x1FFF FFFF On-chip non-volatile memory 0x0000 0000 to 0x0007 FFFF For devices with 512 kB of flash memory. 0x0000 0000 to 0x0003 FFFF For devices with 256 kB of flash memory. 0x0000 0000 to 0x0001 FFFF For devices with 128 kB of flash memory. 0x0000 0000 to 0x0000 FFFF For devices with 64 kB of flash memory. On-chip SRAM 0x1000 0000 to 0x1000 FFFF For devices with 64 kB of main SRAM. 0x1000 0000 to 0x1000 7FFF For devices with 32 kB of main SRAM. 0x1000 0000 to 0x1000 3FFF For devices with 16 kB of main SRAM. Boot ROM 0x1FFF 0000 to 0x1FFF 1FFF 8 kB Boot ROM with flash services. 0x2000 0000 to 0x3FFF FFFF On-chip SRAM (typically used for peripheral data) 0x2000 0000 to 0x2000 1FFF Peripheral SRAM - bank 0 (first 8 kB) 0x2000 2000 to 0x2000 3FFF Peripheral SRAM - bank 0 (second 8 kB) 0x2000 4000 to 0x2000 7FFF Peripheral SRAM - bank 1 (16 kB) AHB peripherals 0x2008 0000 to 0x200B FFFF See Figure 9 for details 0x4000 0000 to 0x7FFF FFFF APB Peripherals 0x4000 0000 to 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of 16 kB each. 0x4008 0000 to 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of 16 kB each. 0x8000 0000 to 0xDFFF FFFF Off-chip Memory via the External Memory Controller Four static memory chip selects: 0x8000 0000 to 0x83FF FFFF Static memory chip select 0 (up to 64 MB) 0x9000 0000 to 0x93FF FFFF Static memory chip select 1 (up to 64 MB) 0x9800 0000 to 0x9BFF FFFF Static memory chip select 2 (up to 64 MB) 0x9C00 0000 to 0x9FFF FFFF Static memory chip select 3 (up to 64 MB) Four dynamic memory chip selects: 0xA000 0000 to 0xAFFF FFFF Dynamic memory chip select 0 (up to 256 MB) 0xB000 0000 to 0xBFFF FFFF Dynamic memory chip select 1 (up to 256 MB) 0xC000 0000 to 0xCFFF FFFF Dynamic memory chip select 2 (up to 256 MB) 0xD000 0000 to 0xDFFF FFFF Dynamic memory chip select 3 (up to 256 MB) 0xE000 0000 to 0xE00F FFFF Cortex-M4 Private Peripheral Bus 0xE000 0000 to 0xE00F FFFF Cortex-M4 related functions, includes the NVIC and System Tick Timer. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 54 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller The LPC408x/7x incorporate several distinct memory regions, shown in the following figures. Figure 9 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 55 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller (1) Not available on all parts. See Table 2 and Table 4. Fig 9. LPC408x/7x memory map 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 0x4000 0000 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC timer 2 timer 3 UART2 UART3 USART4(1) I2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 SSP2 I2S 11 12 reserved motor control PWM reserved 30 - 17 reserved 13 14 15 16 31 system control reserved EMC 4 x static chip select(1) EMC 4 x dynamic chip select(1) reserved private peripheral bus 0 GB 0.5 GB 4 GB 1 GB 0x1FFF 0000 0x2000 0000 0x2000 8000 0x2008 0000 0x2200 0000 0x200A 0000 0x2400 0000 0x2800 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x8000 0000 0xA000 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved reserved SPIFI data reserved reserved APB0 peripherals 0xE004 0000 AHB peripherals APB1 peripherals peripheral SRAM bit-band alias addressing peripheral bit-band alias addressing 0x2000 4000 0x2000 2000 LPC408x/7x QEI(1) SD/MMC(1) APB0 peripherals WWDT timer 0 timer 1 UART0 UART1 reserved reserved CAN AF RAM CAN common CAN1 CAN2 CAN AF registers PWM0 I2C0 RTC/event recorder + backup registers GPIO interrupts pin connect SSP1 ADC 22 - 19 reserved I2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aag736 reserved 0x1FFF 2000 0x2900 0000 reserved reserved 0x2008 0000 0x2008 4000 0x2008 8000 0x2008 C000 0x200A 0000 0x2009 C000 AHB peripherals LCD(1) USB(1) Ethernet(1) 0 GPDMA controller 1 2 3 CRC engine 0x2009 0000 4 0x2009 4000 5 GPIO 0x2009 8000 EMC registers 6 7 0x0000 0000 0x0001 0000 0x0002 0000 0x0004 0000 0x0008 0000 0x1000 0000 0x1000 4000 0x1000 8000 0x1001 0000 64 kB on- chip flash (LPC4072) 128 kB on- chip flash (LPC4074) 256 kB on-chip flash (LPC4076) 512 kB on-chip flash (LPC4078) reserved 16 kB main SRAM (LPC4072) 32 kB main SRAM (LPC4074) 64 kB main SRAM (LPC4088/78/76) 16 kB peripheral SRAM1 (LPC4088/78) 8 kB peripheral SRAM0 (LPC4074/72) 16 kB peripheral SRAM0 (LPC4088/78/76) LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 56 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.9 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.9.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC408x/7x, the NVIC supports 40 vectored interrupts. • 32 programmable interrupt priority levels, with hardware priority level masking. • Relocatable vector table. • Non-Maskable Interrupt (NMI). • Software interrupt generation. 7.9.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 7.10 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupts being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 7.11 External Memory Controller (EMC) Remark: The EMC is available for parts LPC4088/78/76. Supported memory size and type and EMC bus width vary for different packages (see Table 2). The EMC pin configuration for each part is shown in Table 5. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 57 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller The LPC408x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. 7.11.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • 8/16/32 data and 16/20/26 address lines wide static memory support. • 16 bit and 32 bit wide chip select SDRAM memory support. • Static memory features include: – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. Table 5. External memory controller pin configuration Parts Data bus pins Address bus pins Control pins SRAM SDRAM LPC4088FBD208 LPC4088FET208 LPC4078FBD208 LPC4078FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0], EMC_CS[3:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[3:0], EMC_CLK[1:0], EMC_CKE[3:0], EMC_DQM[3:0] LPC4088FET180 LPC4078FET180 LPC4076FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0], EMC_CS[1:0], EMC_OE, EMC_WE EMC_RAS, EMC_CAS, EMC_DYCS[1:0], EMC_CLK[1:0], EMC_CKE[1:0], EMC_DQM[1:0] LPC4088FBD144 LPC4078FBD144 LPC4076FBD144 EMC_D[7:0] EMC_A[15:0] EMC_BLS[3:2], EMC_CS[1:0], EMC_OE, EMC_WE not available LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 58 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.12 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master. The GPDMA controller allows data transfers between the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the I2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be triggered by selected timer match conditions. Memory-to-memory transfers and transfers to or from GPIO are supported. 7.12.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.13 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 59 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.13.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO or DMA back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation – 16-bit write: 2-cycle operation (8-bit x 2-cycle) – 32-bit write: 4-cycle operation (8-bit x 4-cycle) 7.14 LCD controller Remark: The LCD controller is available on parts LPC4088. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.14.1 Features • AHB master interface to access frame buffer. • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. • Hardware cursor support for single-panel displays. • 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. • 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. • 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 60 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • 16 bpp true-color non-palettized, for color STN and TFT. • 24 bpp true-color non-palettized, for color TFT. • Programmable timing for different display panels. • 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. • LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.15 Ethernet Remark: The Ethernet block is available on parts LPC4088/78/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M4 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.15.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 61 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.16 USB interface Remark: The USB Device/Host/OTG controller is available on parts LPC4088/78/76. The USB Device-only controller is available on part LPC4074/72. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. See Section 13.1 for details on typical USB interfacing solutions. 7.16.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM. 7.16.1.1 Features • Fully compliant with USB 2.0 Specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the LPC408x/7x can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 62 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.16.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the Open Host Controller Interface (OHCI) specification. 7.16.2.1 Features • OHCI compliant • Two downstream ports • Supports per-port power switching 7.16.3 USB OTG controller USB OTG is a supplement to the USB 2.0 Specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.16.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 7.17 SD/MMC card interface Remark: The SD/MMC card interface is available on parts LPC4088/78/76. The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.17.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 63 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.18 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC408x/7x use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M4 bit banding. • Support for use with the GPDMA controller. Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.18.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 7.19 12-bit ADC The LPC408x/7x contain one ADC. It is a single 12-bit successive approximation ADC with eight channels and DMA support. 7.19.1 Features • 12-bit successive approximation ADC. • Input multiplexing among eight pins. • Power-down mode. • Measurement range VSS to VREFP. • 12-bit conversion rate: up to 400 kHz. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 64 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 7.20 10-bit DAC The LPC408x/7x contain one DAC. The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. 7.20.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA support 7.21 Comparator Remark: The comparator is available on parts LPC4088/7876. Two embedded comparators are available to compare the voltage levels on external pins or against internal voltages. Up to four voltages on external pins and several internal reference voltages are selectable on each comparator. Additionally, two of the external inputs can be selected to drive an input common on both comparators. 7.21.1 Features • Up to five selectable external sources per comparator; fully configurable on either positive or negative comparator input channels. • 0.9 V internal band gap reference voltage selectable as either positive or negative input on each comparator. • 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either positive or negative comparator input. • Voltage ladder source voltage is selectable from an external pin or the 3.3 V analog voltage supply. • Voltage ladder can be separately powered down for applications only requiring the comparator function. • Relaxation oscillator circuitry output, for a 555 style timer operation. • Individual comparator outputs can be connected to I/O pins. • Separate interrupt for each comparator. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 65 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Edge and level comparator outputs connect to two timers allowing edge counting while a level match has been asserted or measuring the time between two voltage trip points. 7.22 UART0/1/2/3 and USART4 Remark: UART0/1/2/3 are available on all parts. USART4 is available on parts LPC4088/78/76. The LPC408x/7x contain five UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.22.1 Features • Maximum UART data bit rate of 7.5 MBit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto-baud capability. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing. • All UARTs have DMA support for both transmit and receive. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • USART4 includes an IrDA mode to support infrared communication. • USART4 supports synchronous mode and a smart card mode conforming to ISO7816-3. 7.23 SPIFI The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM Cortex-M4 processor with little performance penalty compared to parallel flash devices with higher pin count. The entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 66 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.23.1 Features • Quad SPI Flash Interface (SPIFI) interface to external flash. • Transfer rates of up to SPIFI_CLK/2 bytes per second. • Code in the serial flash memory can be executed as if it was in the CPU’s internal memory space. This is accomplished by mapping the external flash memory directly into the CPU memory space. • Supports 1-, 2-, and 4-bit bidirectional serial protocols. • Half-duplex protocol compatible with various vendors and devices. • Supported by a driver library available from NXP Semiconductors. 7.24 SSP serial I/O controller The LPC408x/7x contain three SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.24.1 Features • Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 7.25 I2C-bus serial I/O controllers The LPC408x/7x contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.25.1 Features • All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s (Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of up to 400 kbit/s. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 67 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0 using pins P5[2] and P5[3]. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • Both I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.26 I2S-bus serial I/O controllers The LPC408x/7x contain one I2S-bus interface. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC408x/7x provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.26.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • Configurable word select period in master mode (separately for I2S input and output). • Two 8 word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. 7.27 CAN controller and acceptance filters The LPC408x/7x contain one CAN controller with two channels. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 68 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.27.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 7.28 General purpose 32-bit timers/external event counters The LPC408x/7x include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.28.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 69 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 7.29 Pulse Width Modulator (PWM) The LPC408x/7x contain two standard PWMs. The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC408x/7x. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.29.1 Features • LPC408x/7x has two PWM blocks with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 70 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 7.30 Motor control PWM The LPC408x/7x contain one motor control PWM. The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2n (see Table 6). 7.31 Quadrature Encoder Interface (QEI) Remark: The QEI is available on parts LPC4088/78/76. A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 7.31.1 Features • Tracks encoder position. Table 6. PWM speed at operating frequency 120 MHz PWM resolution PWM speed 6 bit 1.875 MHz 8 bit 0.468 MHz 10 bit 0.117 MHz LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 71 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 7.32 ARM Cortex-M4 system tick timer The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC408x/7x, this timer can be clocked from the internal AHB clock or from a device pin. 7.33 Windowed WatchDog Timer (WWDT) The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.33.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect feed sequence causes reset or interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is always running if the watchdog timer is enabled. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 72 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.34 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC408x/7x is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC408x/7x is powered off. The RTC includes an alarm function that can wake up the LPC408x/7x from all reduced power modes with a time resolution of 1 s. 7.34.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 7.35 Event monitor/recorder The event monitor/recorder allows recording of tampering events in sealed product enclosures. Sensors report any attempt to open the enclosure, or to tamper with the device in any other way. The event monitor/recorder stores records of such events when the device is powered only by the backup battery. 7.35.1 Features • Supports three digital event inputs in the VBAT power domain. • An event is defined as a level change at the digital event inputs. • For each event channel, two timestamps mark the first and the last occurrence of an event. Each channel also has a dedicated counter tracking the total number of events. Timestamp values are taken from the RTC. • Runs in VBAT power domain, independent of system power supply. The event/recorder/monitor can therefore operate in Deep power-down mode. • Very low power consumption. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 73 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller • Interrupt available if system is running. • A qualified event can be used as a wake-up trigger. • State of event interrupts accessible by software through GPIO. 7.36 Clocking and power control 7.36.1 Crystal oscillators The LPC408x/7x include four independent oscillators. These are the main oscillator, the IRC oscillator, the watchdog oscillator, and the RTC oscillator. Following reset, the LPC408x/7x will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency. See Figure 10 for an overview of the LPC408x/7x clock generation. Fig 10. LPC408x/7x clock generation block diagram MAIN PLL0 IRC oscillator main oscillator (osc_clk) CLKSRCSEL (system clock select) sysclk pll_clk CCLKSEL (CPU clock select) 002aag737 pll_clk ALT PLL1 CPU CLOCK DIVIDER alt_pll_clk cclk PERIPHERAL CLOCK DIVIDER pclk EMC CLOCK DIVIDER emc_clk sysclk alt_pll_clk pll_clk USBCLKSEL (USB clock select) USB CLOCK DIVIDER usb_clk sysclk LPC408x/7x LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 74 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.36.1.1 Internal RC oscillator The IRC may be used as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC408x/7x use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.36.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the alternate PLL1. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.36.2 for additional information. 7.36.1.3 RTC oscillator The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can be output on the CLKOUT pin in order to allow trimming the RTC oscillator without interference from a probe. 7.36.1.4 Watchdog oscillator The Watchdog Timer has a dedicated oscillator that provides a 500 kHz clock to the Watchdog Timer that is always running if the Watchdog Timer is enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to allow observe its frequency. In order to allow Watchdog Timer operation with minimum power consumption, which can be important in reduced power modes, the Watchdog oscillator frequency is not tightly controlled. The Watchdog oscillator frequency will vary over temperature and power supply within a particular part, and may vary by processing across different parts. This variation should be taken into account when determining Watchdog reload values. Within a particular part, temperature and power supply variations can produce up to a 17 % frequency variation. Frequency variation between devices under the same operating conditions can be up to 30 %. 7.36.2 Main PLL (PLL0) and Alternate PLL (PLL1) PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally identical but have somewhat different input possibilities and output connections. These possibilities are shown in Figure 10. The Main PLL can receive its input from either the IRC or the main oscillator and can potentially be used to provide the clocks to nearly everything on the device. The Alternate PLL receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the USB. The USB has timing needs that may not always be filled by the Main PLL. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 75 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB clock through that route. The source for each clock must be selected via the CLKSEL registers and can be further reduced by clock dividers as needed. PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only the Main PLL is used, then its output frequency must be an integer multiple of all other clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional dividers to bring the output down to the desired frequencies. The minimum output divider value is 2, insuring that the output of the PLLs have a 50 % duty cycle. If the USB is used, the possibilities for the CPU clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the PLL0 output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in conjunction with the PLL can meet the precision and jitter specifications for USB. It is due to these limitations that the Alternate PLL is provided. The alternate PLL accepts an input clock frequency from the main oscillator in the range of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied up to a multiple of 48 MHz (192 MHz or 288 MHz as described above). 7.36.3 Wake-up timer The LPC408x/7x begin operation at power-up and when awakened from Power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.36.4 Power control The LPC408x/7x support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 76 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller value. This allows a trade-off of power versus processing speed based on application requirements. In addition, the peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. The LPC408x/7x also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 7.36.4.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence other than re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The DMA controller can continue to work in Sleep mode and has access to the peripheral RAMs and all peripheral registers. The flash memory and the main SRAM are not available in Sleep mode, they are disabled in order to save power. Wake-up from Sleep mode will occur whenever any enabled interrupt occurs. 7.36.4.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The clock divider registers are automatically reset to zero. The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0 through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect, an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled. Wake-up will occur whenever any enabled interrupt occurs. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 77 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 7.36.4.3 Power-down mode Power-down mode does everything that Deep-sleep mode does but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are stopped. The RTC remains running if it has been enabled and RTC interrupts may be used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are automatically turned off and the clock selection multiplexers are set to use the system clock sysclk (the reset state). The clock divider control registers are automatically reset to zero. If the Watchdog timer is running, it will continue running in Power-down mode. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this four IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 7.36.4.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before device operation can be restarted. The LPC408x/7x can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.36.4.5 Wake-up Interrupt Controller (WIC) The WIC allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC. This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 78 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.36.5 Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.36.6 Power domains The LPC408x/7x provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup registers. On the LPC408x/7x, I/O pads are powered by VDD(3V3), while VDD(REG)(3V3) powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC408x/7x application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly” while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. There is no power drain from the RTC battery when VDD(REG)(3V3) is available and VDD(REG)(3V3) > VBAT. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 79 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.37 System control 7.37.1 Reset Reset has four sources on the LPC408x/7x: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.36.3), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 11. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR POWER SELECTOR ULTRA-LOW POWER REGULATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aag738 RTCX1 VBAT (typical 3.0 V) VDD(REG)(3V3) (typical 3.3 V) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VSSA LPC408x/7x LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 80 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.37.2 Brownout detection The LPC408x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC408x/7x when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V (typical). This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.37.3 Code security (Code Read Protection - CRP) This feature of the LPC408x/7x allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. 7.37.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 81 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 7.37.5 AHB multilayer matrix The LPC408x/7x use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M4 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 7.37.6 External interrupt inputs The LPC408x/7x include up to 30 edge sensitive interrupt inputs combined with one level sensitive external interrupt input as selectable pin function. The external interrupt input can optionally be used to wake up the processor from Power-down mode. 7.37.7 Memory mapping control The Cortex-M4 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M4 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC408x/7x is configured for 128 total interrupts. 7.38 Debug control Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four watch points. 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP 0.5 +4.6 V VIA analog input voltage on ADC related pins 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD(3V3)  2.4V [2] 0.5 +5.5 V VDD(3V3)  0 V 0.5 +3.6 V other I/O pins [2][3] 0.5 VDD(3V3) + 0.5 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 82 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on the required shelf lifetime. Please refer to the JEDEC spec for further details. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature non-operating [4] 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [5]- 4000 V Table 7. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 83 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation Tj = Tamb + PD  Rthj – a Table 8. Thermal characteristics VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Parameter Conditions Min Typ Max Unit Tj(max) maximum junction temperature - - 125 C Table 9. Thermal resistance (LQFP packages) Tamb = 40 C to +85 C unless otherwise specified. Thermal resistance value (C/W): ±15 % LQFP80 LQFP144 LQFP208 ja JEDEC (4.5 in  4 in) 0 m/s 41 31 27 1 m/s 35 28 25 2.5 m/s 32 26 24 Single-layer (4.5 in  3 in) 0 m/s 61 43 35 1 m/s 47 35 31 2.5 m/s 43 33 29 jc 7.8 9.2 10.5 jb 11.6 13.5 15.2 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 84 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Table 10. Thermal resistance value (TFBGA packages) Tamb = 40 C to +85 C unless otherwise specified. Thermal resistance value (C/W): ±15 % TFBGA180 TFBGA208 ja JEDEC (4.5 in  4 in) 0 m/s 47 43 1 m/s 39 37 2.5 m/s 35 33 8-layer (4.5 in  3 in) 0 m/s 39 37 1 m/s 35 33 2.5 m/s 31 30 jc 8.5 7.4 jb 13 16 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 85 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3] 2.7 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [4] 2.1 3.0 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.7 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled [5][6]- 7.5 - mA CCLK = 120 MHz; PLL enabled [5][7]- 56 - mA active mode; code while(1){} executed from flash; all peripherals enabled; PCLK = CCLK/4 CCLK = 12 MHz; PLL disabled [5][6] 14 - CCLK = 120 MHz; PLL enabled [5][7] 120 - mA Sleep mode [5][8]- 5.5 - mA Deep-sleep mode [5][9] - 550 1200 A Power-down mode [5][9] - 280 600 A IBAT battery supply current RTC running; part powered down; VDD(REG)(3V3) =0 V; Vi(VBAT) = 3.0 V; VDD(3V3) = 0 V. [10] - 1 9 A part powered; VDD(REG)(3V3) = 3.3 V; Vi(VBAT) = 3.0 V [11] <10 nA LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 86 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [15][16] [17] 0 - 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3)  0.45 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.45 V IOH HIGH-level output current VOH = VDD(3V3)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [18]- - 50 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [18]- - 60 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A VDD(3V3) < VI < 5 V 0 0 0 A I2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05  VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA - - 0.4 V ILI input leakage current VI = VDD(3V3) [19]- 2 4 A VI = 5 V - 10 22 A USB pins IOZ OFF-state output current 0 V < VI < 3.3 V [20]- - 10 A VBUS bus supply voltage [20]- - 5.25 V VDI differential input sensitivity voltage (D+)  (D) [20] 0.2 - - V Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 87 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  VDD((3V3)  3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [5] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. [6] Boost control bits in the PBOOST register set to 0x0 (see LPC408x/7x User manual). [7] Boost control bits in the PBOOST register set to 0x3 (see LPC408x/7x User manual). [8] IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4. [9] BOD disabled. [10] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 0; Tamb = 25 C. [11] On pin VBAT; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; Tamb = 25 C. [12] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. [13] VDDA = 3.3 V; Tamb = 25 C. [14] Vi(VREFP) = 3.3 V; Tamb = 25 C. [15] Including voltage on outputs in 3-state mode. [16] VDD(3V3) supply voltages must be present. [17] 3-state outputs go into 3-state mode in Deep power-down mode. [18] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [19] To VSS. [20] 3.0 V  VDD(3V3)  3.6 V. VCM differential common mode voltage range includes VDI range [20] 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage [20] 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V [20]- - 0.18 V VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND [20] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [20]- - 20 pF Oscillator pins (see Section 13.2) Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V Table 11. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 88 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 10.1 Power consumption Conditions: BOD disabled. Fig 12. Deep-sleep mode: Typical regulator supply current IDD(REG)(3V3) versus temperature Conditions: BOD disabled. Fig 13. Power-down mode: Typical regulator supply current IDD(REG)(3V3) versus temperature temperature (°C) -40 -15 10 35 60 85 002aah051 0.7 1.1 1.5 0.3 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V IDD(REG)(3V3) (mA) temperature (°C) -40 -15 10 35 60 85 002aah052 300 600 900 0 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.4 V IDD(REG)(3V3) (μA) LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 89 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Conditions: VDD(REG)(3V3) = VDDA = VDD(3V3) = 0; VBAT = 3.0 V. Fig 14. Part powered off: Typical battery supply current (IBAT) versus temperature 002aah074 temperature (°C) -40 -15 10 35 60 85 0.8 1.6 0.4 1.2 2.0 0 IBAT (μA) LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 90 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 10.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz, 48 MHz, and 120 MHz. The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. Table 12. Power consumption for individual analog and digital blocks Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz[1] 48 MHz[1] 120 MHz[2] Timer0 0.01 0.06 0.15 Timer1 0.02 0.07 0.16 Timer2 0.02 0.07 0.17 Timer3 0.01 0.07 0.16 Timer0 + Timer1 + Timer2 + Timer3 0.07 0.28 0.67 UART0 0.05 0.19 0.45 UART1 0.06 0.24 0.56 UART2 0.05 0.2 0.47 UART3 0.06 0.23 0.56 USART4 0.07 0.27 0.66 UART0 + UART1 + UART2 + UART3 + USART4 0.29 1.13 2.74 PWM0 + PWM1 0.08 0.31 0.75 Motor control PWM 0.04 0.15 0.36 I2C0 0.01 0.03 0.08 I2C1 0.01 0.03 0.1 I2C2 0.01 0.03 0.08 I2C0 + I2C1 + I2C2 0.02 0.1 0.26 SSP0 0.03 0.1 0.26 SSP1 0.02 0.11 0.27 DAC 0.3 0.31 0.33 ADC (12 MHz clock) 1.51 1.61 1.7 Comparator 0.01 0.03 0.06 CAN1 0.11 0.44 1.08 CAN2 0.1 0.4 0.98 CAN1 + CAN2 0.15 0.59 1.44 DMA PCLK = CCLK 1.1 4.27 10.27 QEI 0.02 0.11 0.28 GPIO 0.4 1.72 4.16 LCD 0.99 3.84 9.25 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 91 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] Boost control bits in the PBOOST register set to 0x0 (see LPC178x/7x User manual UM10470). [2] Boost control bits in the PBOOST register set to 0x3 (see LPC178x/7x User manual UM10470). I2S 0.04 0.18 0.46 EMC 0.82 3.17 7.63 RTC 0.01 0.01 0.05 USB + PLL1 0.62 0.97 1.67 Ethernet PCENET bit set to 1 in the PCONP register 0.54 2.08 5.03 Table 12. Power consumption for individual analog and digital blocks …continued Tamb = 25 C; VDD(REG)(3V3) = VDD(3V3) = VDDA = 3.3 V; PCLK = CCLK/4. Peripheral Conditions Typical supply current in mA 12 MHz[1] 48 MHz[1] 120 MHz[2] LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 92 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 10.3 Electrical pin characteristics Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL IOH (mA) 0 8 16 24 002aaf112 2.8 2.4 3.2 3.6 VOH (V) 2.0 T = 85 °C 25 °C −40 °C VOL (V) 0 0.2 0.4 0.6 002aaf111 5 10 15 IOL (mA) 0 T = 85 °C 25 °C −40 °C LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 93 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 17. Typical pull-up current Ipu versus input voltage VI Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 18. Typical pull-down current Ipd versus input voltage VI 0 1 2 3 4 5 002aaf108 −30 −50 −10 10 Ipu (μA) −70 T = 85 °C 25 °C −40 °C VI (V) 002aaf109 VI (V) 0 1 2 3 4 5 10 70 50 30 90 Ipd (μA) −10 T = 85 °C 25 °C −40 °C LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 94 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11. Dynamic characteristics 11.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. [1] EEPROM clock frequency = 375 kHz. Programming/erase times increase with decreasing EEPROM clock frequency. Table 13. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 14. EEPROM characteristics Tamb = 40 C to +85C; VDD(REG)(3V3) = 2.7 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency 200 375 400 kHz Nendu endurance 100000 500000 - cycles tret retention time powered 10 - - years unpowered 10 - - years ter erase time 64 bytes [1]- 1.8 - ms tprog programming time 64 bytes [1]- 1.1 - ms LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 95 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.2 External memory interface Table 15. Dynamic characteristics: Static external memory interface CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Conditions[1] Min Typ Max Unit Read cycle parameters[2] tCSLAV CS LOW to address valid time RD1 3.3 4.3 6.1 ns tCSLOEL CS LOW to OE LOW time RD2 [3] 2.4 + Tcy(clk)  WAITOEN 3.1 + Tcy(clk)  WAITOEN 4.2 + Tcy(clk)  WAITOEN ns tCSLBLSL CS LOW to BLS LOW time RD3; PB = 1 [3] 2.7 3.5 4.9 ns tOELOEH OE LOW to OE HIGH time RD4 [3] (WAITRD  WAITOEN + 1)  Tcy(clk)  2.2 (WAITRD  WAITOEN + 1)  Tcy(clk)  2.8 (WAITRD  WAITOEN + 1)  Tcy(clk)  3.8 ns tam memory access time RD5 [4][3] (WAITRD  WAITOEN + 1)  Tcy(clk)  9.6 (WAITRD  WAITOEN + 1)  Tcy(clk)  13.2 (WAITRD  WAITOEN + 1)  Tcy(clk)  20.2 ns th(D) data input hold time RD6 [5][3] 5.0 7.2 10.7 ns tCSHBLSH CS HIGH to BLS HIGH time PB = 1 2.7 3.4 4.9 ns tCSHOEH CS HIGH to OE HIGH time [3] 2.4 3.1 4.2 ns tOEHANV OE HIGH to address invalid time [3] 0.77 1.2 1.86 ns tdeact deactivation time RD7 [3] 3.3 4.3 6.1 ns Write cycle parameters[2] tCSLAV CS LOW to address valid time WR1 3.3 4.3 6.1 ns tCSLDV CS LOW to data valid time WR2 3.4 4.8 6.6 ns tCSLWEL CS LOW to WE LOW time WR3; PB =1 [3] 2.6 + Tcy(clk)  (1 + WAITWEN) 3.3 + Tcy(clk)  (1 + WAITWEN) 4.6 + Tcy(clk)  (1 + WAITWEN) ns tCSLBLSL CS LOW to BLS LOW time WR4; PB = 1 [3] 2.7 3.5 4.9 ns tWELWEH WE LOW to WE HIGH time WR5; PB =1 [3] (WAITWR  WAITWEN + 1)  Tcy(clk)  2.3 (WAITWR  WAITWEN + 1)  Tcy(clk)  2.8 (WAITWR  WAITWEN + 1)  Tcy(clk)  3.8 ns tBLSLBLSH BLS LOW to BLS HIGH time PB = 1 [3] (WAITWR  WAITWEN + 3)  Tcy(clk)  2.8 (WAITWR  WAITWEN + 3)  Tcy(clk)  3.5 (WAITWR  WAITWEN + 3)  Tcy(clk)  5.0 ns tWEHDNV WE HIGH to data invalid time WR6; PB =1 [3] 3.1 + Tcy(clk) 4.3 + Tcy(clk) 5.8 + Tcy(clk) ns tWEHEOW WE HIGH to end of write time WR7; PB = 1 [6][3] Tcy(clk)  2.6 Tcy(clk)  3.4 Tcy(clk)  4.6 ns tBLSHDNV BLS HIGH to data invalid time PB = 1 3.4 4.8 6.6 ns tWEHANV WE HIGH to address invalid time PB = 1 [3] 3.0 + Tcy(clk) 3.8 + Tcy(clk) 5.3 + Tcy(clk) ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 96 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] Parameters are shown as RDn or WDn in Figure 19 as indicated in the Conditions column. [2] Parameters specified for 40 % of VDD(3V3) for rising edges and 60 % of VDD(3V3) for falling edges. [3] Tcy(clk) = 1/EMC_CLK (see LPC408x/7x User manual). [4] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1). [5] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid. [6] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1). tdeact deactivation time WR8; PB = 0; PB = 1 [3] 3.3 4.3 6.1 ns tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [3] 2.7 + Tcy(clk)  (1 + WAITWEN) 3.5 + Tcy(clk)  (1 + WAITWEN) 4.9 + Tcy(clk)  (1 + WAITWEN) ns tBLSLBLSH BLS LOW to BLS HIGH time WR10; PB = 0 [3] (WAITWR  WAITWEN + 3)  Tcy(clk)  2.8 (WAITWR  WAITWEN + 3)  Tcy(clk) 3.5 (WAITWR  WAITWEN + 3)  Tcy(clk)  5.0 ns tBLSHEOW BLS HIGH to end of write time WR11; PB = 0 [6][3] 3.3 + Tcy(clk) 4.4 + Tcy(clk) 6.1 + Tcy(clk) ns tBLSHDNV BLS HIGH to data invalid time WR12; PB = 0 [3] 3.4 + Tcy(clk) 4.8 + Tcy(clk) 6.6 + Tcy(clk) ns Table 15. Dynamic characteristics: Static external memory interface …continued CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter[1] Conditions[1] Min Typ Max Unit Fig 19. External static memory read/write access (PB = 0) RD1 RD5 RD2 WR2 WR9 WR12 WR10 WR11 RD5 RD5 RD6 WR8 WR1 EOR EOW RD7 RD4 EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx 002aag214 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 97 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 20. External static memory read/write access (PB =1) RD1 WR1 EMC_Ax WR8 WR4 WR8 EMC_CSx RD2 RD7 RD7 RD4 EMC_OE EMC_BLSx EMC_WE RD5 WR2 WR6 RD5 RD5 RD5 RD6 RD3 EOR EOW EMC_Dx WR3 WR5 WR7 002aag215 Fig 21. External static memory burst read cycle RD5 RD5 RD5 RD5 EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx 002aag216 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 98 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] Refers to SDRAM clock signal EMC_CLKx. [2] CLKDLY = CLKOUTnDLY, where n = 0, 1. [3] The data input set-up time has to be selected with the following margin: tsu(D) + delay time of feedback clock  SDRAM access time  board delay time  0. [4] The data input hold time has to be selected with the following margin: th(D) + SDRAM access time  board delay time  delay time of feedback clock  0. Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Common to read and write cycles Tcy(clk) clock cycle time [1] 12.5 - - ns td(SV) chip select valid delay time [2] (CLKDLY + 1)  0.25 + 2.8 (CLKDLY + 1)  0.25 + 3.5 (CLKDLY + 1)  0.25 + 5.1 ns th(S) chip select hold time [2] (CLKDLY + 1)  0.25  1.0 (CLKDLY + 1)  0.25  1.1 (CLKDLY + 1)  0.25  1.5 ns td(RASV) row address strobe valid delay time [2] (CLKDLY + 1)  0.25 + 2.8 (CLKDLY + 1)  0.25 + 3.6 (CLKDLY + 1)  0.25 + 5.1 ns th(RAS) row address strobe hold time [2] (CLKDLY + 1)  0.25 0.8 (CLKDLY + 1)  0.25 0.9 (CLKDLY + 1)  0.25  1.0 ns td(CASV) column address strobe valid delay time [2] (CLKDLY + 1)  0.25 + 2.7 (CLKDLY + 1)  0.25 + 3.4 (CLKDLY + 1)  0.25 + 4.9 ns th(CAS) column address strobe hold time [2] (CLKDLY + 1)  0.25  0.8 (CLKDLY + 1)  0.25  1.0 (CLKDLY + 1)  0.25  1.2 ns td(WV) write valid delay time [2] (CLKDLY + 1)  0.25 + 3.2 (CLKDLY + 1)  0.25 + 4.1 (CLKDLY + 1)  0.25 + 6.0 ns th(W) write hold time [2] (CLKDLY + 1)  0.25  0.6 (CLKDLY + 1)  0.25  0.67 (CLKDLY + 1)  0.25  0.7 ns td(AV) address valid delay time [2] (CLKDLY + 1)  0.25 + 3.4 (CLKDLY + 1)  0.25 + 4.6 (CLKDLY + 1)  0.25 + 6.8 ns th(A) address hold time [2] (CLKDLY + 1)  0.25  1.1 (CLKDLY + 1)  0.25  1.4 (CLKDLY + 1)  0.25  1.8 ns Read cycle parameters tsu(D) data input set-up time [3] (FBCLKDLY + 1)  0.25 + 4.1 (FBCLKDLY + 1)  0.25 + 2.3 (FBCLKDLY + 1)  0.25  0.9 ns th(D) data input hold time [4] (FBCLKDLY + 1)  0.25 + 4.0 (FBCLKDLY + 1)  0.25 + 4.7 (FBCLKDLY + 1)  0.25 + 5.8 ns Write cycle parameters td(QV) data output valid delay time [2] (CLKDLY + 1)  0.25 + 3.9 (CLKDLY + 1)  0.25 + 5.4 (CLKDLY + 1)  0.25 + 7.8 ns th(Q) data output hold time [2] (CLKDLY + 1)  0.25  1.1 (CLKDLY + 1)  0.25  1.2 (CLKDLY + 1)  0.25  1.4 ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 99 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] Refers to SDRAM clock signal EMC_CLKx. [2] The data input set-up time has to be selected with the following margin: tsu(D) + delay time of feedback clock  SDRAM access time  board delay time  0. [3] The data input hold time has to be selected with the following margin: th(D) + SDRAM access time - board delay time - delay time of feedback clock  0. Table 17. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Min Typ Max Unit Common to read and write cycles Tcy(clk) clock cycle time [1] 12.5 - - ns td(SV) chip select valid delay time (CMDDLY + 1)  0.25 + 4.9 (CMDDLY + 1)  0.25 + 6.7 (CMDDLY + 1)  0.25 + 10.4 ns th(S) chip select hold time (CMDDLY + 1)  0.25 + 1.2 (CMDDLY + 1)  0.25 + 2.1 (CMDDLY + 1)  0.25 + 3.8 ns td(RASV) row address strobe valid delay time (CMDDLY + 1)  0.25 + 4.9 (CMDDLY + 1)  0.25 + 6.8 (CMDDLY + 1)  0.25 + 10.4 ns th(RAS) row address strobe hold time (CMDDLY + 1)  0.25 + 1.3 (CMDDLY + 1)  0.25 + 2.3 (CMDDLY + 1)  0.25 + 4.3 ns td(CASV) column address strobe valid delay time (CMDDLY + 1)  0.25 + 4.8 (CMDDLY + 1)  0.25 + 6.7 (CMDDLY + 1)  0.25 + 10.2 ns th(CAS) column address strobe hold time (CMDDLY + 1)  0.25 + 1.2 (CMDDLY + 1)  0.25 + 2.2 (CMDDLY + 1)  0.25 + 4.1 ns td(WV) write valid delay time (CMDDLY + 1)  0.25 + 5.1 (CMDDLY + 1)  0.25 + 7.1 (CMDDLY + 1)  0.25 + 10.9 ns th(W) write hold time (CMDDLY + 1)  0.25 + 1.5 (CMDDLY + 1)  0.25 + 2.6 (CMDDLY + 1)  0.25 + 4.8 ns td(AV) address valid delay time (CMDDLY + 1)  0.25 + 5.5 (CMDDLY + 1)  0.25 + 7.7 (CMDDLY + 1)  0.25 + 11.9 ns th(A) address hold time (CMDDLY + 1)  0.25 + 1.0 (CMDDLY + 1)  0.25 + 1.8 (CMDDLY + 1)  0.25 + 3.5 ns Read cycle parameters tsu(D) data input set-up time [2] (FBCLKDLY + 1)  0.25 + 4.1 (FBCLKDLY + 1)  0.25 + 2.3 (FBCLKDLY + 1)  0.25  0.9 ns th(D) data input hold time [3] (FBCLKDLY + 1)  0.25 + 4.0 (FBCLKDLY + 1)  0.25 + 4.7 (FBCLKDLY + 1)  0.25 + 5.8 ns Write cycle parameters td(QV) data output valid delay time (CMDDLY + 1)  0.25 + 5.9 (CMDDLY + 1)  0.25 + 8.7 (CMDDLY + 1)  0.25 + 13.1 ns th(Q) data output hold time (CMDDLY + 1)  0.25 + 1.0 (CMDDLY + 1)  0.25 + 2.0 (CMDDLY + 1)  0.25 + 3.9 ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 100 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All delay times are incremental delays for each element starting from delay block 0. See the LPC408x/7x user manual for details. Fig 22. Dynamic external memory interface signal timing 002aah129 EMC_CLKn Tcy(clk) delay = 0 EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn th(Q) tsu(D) th(D) EMC_D[31:0] write EMC_D[31:0] read td(QV) td(xV) th(x) Table 18. Dynamic characteristics: Dynamic external memory interface programmable clock delays CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design. Symbol Parameter Conditions Min Max Unit td delay time Programmable delay block 0 (CMDDLY or CLKOUTnDLY bit 0 = 1) [1] 0.1 0.2 ns Programmable delay block 1 (CMDDLY or CLKOUTnDLY bit 1 = 1) [1] 0.2 0.5 ns Programmable delay block 2 (CMDDLY or CLKOUTnDLY bit 2 = 1) [1] 0.5 1.3 ns Programmable delay block 3 (CMDDLY or CLKOUTnDLY bit 3 = 1) [1] 1.2 2.9 ns Programmable delay block 4 (CMDDLY or CLKOUTnDLY bit 4 = 1) [1] 2.4 6.0 ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 101 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.3 External clock [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.4 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 11.5 I/O pins [1] Applies to standard port pin. For details, see the LPC408x/7x IBIS model available on the NXP website. Table 19. Dynamic characteristic: external clock (see Figure 40) Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) 0.4 - - ns tCLCX clock LOW time Tcy(clk) 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Fig 23. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Table 20. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Table 21. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 102 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.6 SSP interface [1] The minimum clock cycle time, and therefore the maximum frequency of the SSP in master mode, is limited by the pin electronics to the value given. The SSP block should not be configured to generate a clock faster than that. At and below the maximum frequency, Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register). [2] Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V. [3] Tcy(clk) = 12  Tcy(PCLK). The maximum clock rate in slave mode is 1/12th of the PCLK rate. [4] Tamb = 25 C; VDD(3V3) = 3.3 V. Table 22. Dynamic characteristics: SSP pins in SPI mode CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit SSP master Tcy(clk) clock cycle time full-duplex mode [1] 30 - ns when only transmitting 30 - ns tDS data set-up time in SPI mode [2] 14.8 - ns tDH data hold time in SPI mode [2] 2 - ns tv(Q) data output valid time in SPI mode [2] - 6.3 ns th(Q) data output hold time in SPI mode [2] 2.4 - ns SSP slave Tcy(clk) clock cycle time [3] 100 - ns tDS data set-up time in SPI mode [3][4] 14.8 - ns tDH data hold time in SPI mode [3][4] 2 - ns tv(Q) data output valid time in SPI mode [3][4] - 6.3 ns th(Q) data output hold time in SPI mode [3][4] 2.4 - ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 103 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 24. SSP master timing in SPI mode Fig 25. SSP slave timing in SPI mode SCK (CPOL = 0) MOSI MISO Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH DATA VALID DATA VALID th(Q) DATA VALID DATA VALID tv(Q) CPHA = 1 CPHA = 0 002aae829 SCK (CPOL = 0) MOSI MISO Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH tv(Q) DATA VALID DATA VALID th(Q) DATA VALID DATA VALID CPHA = 1 CPHA = 0 002aae830 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 104 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.7 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Table 23. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [4][5][6][7] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s tHD;DAT data hold time [3][4][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 105 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.8 I2S-bus interface [1] CCLK = 100 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK / 4. I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. Fig 26. I2C-bus pins clock timing 002aaf425 tf 70 % SDA 30 % tf 70 % 30 % S 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 70 % 30 % 70 % 30 % tVD;DAT tHIGH tLOW tSU;DAT Table 24. Dynamic characteristics: I2S-bus interface pins CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit common to input and output tr rise time [1] - 6.7 ns tf fall time [1] - 8.0 ns tWH pulse width HIGH on pins I2S_TX_SCK and I2S_RX_SCK [1] 25 - - tWL pulse width LOW on pins I2S_TX_SCK and I2S_RX_SCK [1] - 25 ns output tv(Q) data output valid time on pin I2S_TX_SDA; [1] - 6 ns input tsu(D) data input set-up time on pin I2S_RX_SDA [1] 5 - ns th(D) data input hold time on pin I2S_RX_SDA [1] 2 - ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 106 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.9 LCD Remark: The LCD controller is available on parts LPC4088. Fig 27. I2S-bus timing (transmit) Fig 28. I2S-bus timing (receive) 002aag202 I2S_TX_SCK I2S_TX_SDA I2S_TX_WS Tcy(clk) tf tr tWH tWL tv(Q) tv(Q) 002aag203 Tcy(clk) tf tr tWH tsu(D) th(D) tsu(D) tsu(D) tWL I2S_RX_SCK I2S_RX_SDA I2S_RX_WS Table 25. Dynamic characteristics: LCD CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit fclk clock frequency on pin LCD_DCLK - 50 MHz td(QV) data output valid delay time - 12 ns th(Q) data output hold time 0.5 - ns LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 107 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.10 SD/MMC Remark: The SD/MMC card interface is available on parts LPC4088/78/76. The LCD panel clock is shown with the default polarity. The clock can be inverted via the IPC bit in the LCD_POL register. Typically, the LCD panel uses the falling edge of the LCD_DCLK to sample the data. Fig 29. LCD timing 002aah325 LCD_DCLK td(QV) Tcy(clk) th(Q) LCD_VD[n] Table 26. Dynamic characteristics: SD/MMC CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. Symbol Parameter Conditions Min Max Unit fclk clock frequency on pin SD_CLK; data transfer mode - 25 MHz on pin SD_CLK; identification mode 25 MHz tsu(D) data input set-up time on pins SD_CMD, SD_DAT[3:0] as inputs 6 - ns th(D) data input hold time on pins SD_CMD, SD_DAT[3:0] as inputs 6 - ns td(QV) data output valid delay time on pins SD_CMD, SD_DAT[3:0] as outputs - 23 ns th(Q) data output hold time on pins SD_CMD, SD_DAT[3:0] as outputs 3.5 - ns Fig 30. SD/MMC timing 002aag204 SD_CLK SD_DATn (O) SD_DATn (I) td(QV) tsu(D) th(D) Tcy(clk) th(Q) SD_CMD (O) SD_CMD (I) LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 108 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 11.11 SPIFI 12. Characteristics of the analog peripherals 12.1 ADC electrical characteristics Table 27. Dynamic characteristics: SPIFI Tamb = 40 C to 85 C; 3.0 V  VDD(3V3)  3.6 V; CL = 30 pF. Values guaranteed by design. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 11.8 - ns tDS data set-up time 4.8 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 8.8 ns th(Q) data output hold time 3 - ns Fig 31. SPIFI timing SPIFI_SCK SPIFI data out SPIFI data in Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) DATA VALID DATA VALID 002aah409 Table 28. 12-bit ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA V 12-bit resolution; 400 kSamples/sec ED differential linearity error [2][3][4] - - 1 LSB EL(adj) integral non-linearity [2][5] - - 6 LSB EO offset error [2][6] - - 5 LSB EG gain error [2][7] - - 5 LSB ET absolute error [2][8]- - <8 LSB fclk(ADC) ADC clock frequency - - 12.4 MHz fc(ADC) ADC conversion frequency [9]- - 400 kHz LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 109 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] Conditions: VSSA = 0 V, VDDA = 3.3 V. [3] The ADC is monotonic, there are no missing codes. [4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 32. [5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 32. [6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 32. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 32. [8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 32. [9] In single-conversion mode. [10] See Figure 33. [11] 8-bit resolution is achieved by ignoring the lower four bits of the ADC conversion result. Cia analog input capacitance - - 5 pF Rvsi voltage source interface resistance [10]- - 1 k 8-bit resolution[11]; 1.16 MSamples/sec ED differential linearity error [2][3][4] - 1 - LSB EL(adj) integral non-linearity [2][5] - 1 - LSB EO offset error [2][6] - 1 - LSB EG gain error [2][7] - 1 - LSB ET absolute error [2][8]- - <1.5 LSB fclk(ADC) ADC clock frequency - - 36 MHz fc(ADC) ADC conversion frequency [9]- - 1.16 MHz Cia analog input capacitance - - 5 pF Rvsi voltage source interface resistance [10]- - 1 k Table 28. 12-bit ADC characteristics …continued VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 110 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 32. 12-bit ADC characteristics 002aaf436 4095 4094 4093 4092 4091 (2) (1) 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 LSB (ideal) code out VREF P - VSS 4096 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 111 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 12.2 DAC electrical characteristics The values of resistor components Rcmp and Rsw vary with temperature and input voltage and are process-dependent. Fig 33. ADC interface to pins ADC0_IN[n] Table 29. ADC interface components Component Range Description Rcmp 90  to 300  Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. Rsw 500  to 2 k Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. C1 110 fF Parasitic capacitance from the ADC block level. C2 80 fF Parasitic capacitance from the ADC block level. C3 1.6 pF Sampling capacitor. LPC408x/7x AD0[n] 110 fF 80 fF Cia 1.6 pF Rvsi Rsw 500 Ω - 2 kΩ Rcmp 90 Ω - 300 Ω VSS VEXT 002aah275 ADC COMPARATOR BLOCK C1 C3 C2 Table 30. 10-bit DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.6 - % CL load capacitance - - 200 pF RL load resistance 1 - - k LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 112 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 12.3 Comparator electrical characteristics [1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = -40 C to +85 C. [2] Input hysteresis is relative to the reference input channel and is software programmable. Table 31. Comparator characteristics VDDA= 3.0 V and Tamb = 25 C unless noted otherwise. Symbol Parameter Conditions Min Typ Max Unit Static characteristics IDD supply current - 55 - A VIC common-mode input voltage 0 - VDDA V DVO output voltage variation 0 - VDDA V Voffset offset voltage VIC = 0.1 V - 4 to +4.2 - mV VIC = 1.5 V - 2 - mV VIC = 2.8 V - 2.5 mV Dynamic characteristics tstartup start-up time nominal process - 4 - s tPD propagation delay HIGH to LOW; VDDA = 3.3 V; VIC = 0.1 V; 50 mV overdrive input [1] 122 130 142 ns VIC = 0.1 V; rail-to-rail input [1] 173 189 233 ns VIC = 1.5 V; 50 mV overdrive input [1] 101 108 119 ns VIC = 1.5 V; rail-to-rail input [1] 114 127 162 ns VIC = 2.9 V; 50 mV overdrive input [1] 123 134 143 ns VIC = 2.9 V; rail-to-rail input [1] 79 91 120 ns tPD propagation delay LOW to HIGH; VDDA = 3.3 V; VIC = 0.1 V; 50 mV overdrive input [1] 221 232 254 ns VIC = 0.1 V; rail-to-rail input [1] 59 63 68 ns VIC = 1.5 V; 50 mV overdrive input [1] 183 229 249 ns VIC = 1.5 V; rail-to-rail input [1] 147 174 213 ns VIC = 2.9 V; 50 mV overdrive input [1] 171 192 216 ns VIC = 2.9 V; rail-to-rail input [1] 235 305 450 ns Vhys hysteresis voltage positive hysteresis; VDDA = 3.0 V; VIC = 1.5 V [2] - 5, 10, 20 - mV Vhys hysteresis voltage negative hysteresis; VDDA = 3.0 V; VIC = 1.5 V [2] - 5, 10, 20 - mV Rlad ladder resistance - - 1.034 - M LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 113 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller [1] Maximum values are derived from worst case simulation (VDDA = 2.6 V; Tamb = 85 C; slow process models). [2] Settling time applies to switching between comparator and ADC channels. [1] Measured on typical silicon samples with a 2 kHz input signal and overdrive < 100 V. Power switched off to all analog peripherals except the comparator. Table 32. Comparator voltage ladder dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit ts(pu) power-up settling time to 99% of voltage ladder output value [1]- - 30 s ts(sw) switching settling time to 99% of voltage ladder output value [1] [2] - - 15 s Table 33. Comparator voltage ladder reference static characteristics VDDA = 3.3 V; Tamb = -40 C to + 85C. Symbol Parameter Conditions Min Typ Max[1] Unit EV(O) output voltage error Internal VDDA supply decimal code = 00 0 0 0 % decimal code = 08 0.45 0.5 0.55 % decimal code = 16 0.99 1.1 1.21 % decimal code = 24 1.26 1.4 1.54 % decimal code = 30 1.35 1.5 1.65 % decimal code = 31 1.35 1.5 1.65 % EV(O) output voltage error External VDDCMP supply decimal code = 00 0 0 0 % decimal code = 08 0.44 0.4 0.36 % decimal code = 16 0.18 0.2 0.22 % decimal code = 24 0.45 0.5 0.55 % decimal code = 30 0.54 0.6 0.66 % decimal code = 31 0.45 0.5 0.55 % LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 114 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 13. Application information 13.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC4088 and LPC4078/76 and as device-only controller on parts LPC4074/72. Fig 34. USB interface on a self-powered device LPC40xx USB-B connector USB_D+ USB_CONNECT SoftConnect switch USB_DVBUS VSS VDD(3V3) R1 1.5 kΩ RS = 33 Ω 002aah267 RS = 33 Ω USB_UP_LED Fig 35. USB interface on a bus-powered device LPC40xx VDD(3V3) R1 1.5 kΩ R2 USB_UP_LED 002aah268 USB-B connector USB_D+ USB_DVBUS VSS RS = 33 Ω RS = 33 Ω LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 115 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 36. USB OTG port configuration: port 1 OTG dual-role device, port 2 host USB_UP_LED1 USB_D+1 USB_D-1 USB_PWRD2 USB_SDA1 USB_SCL1 RSTOUT 15 kΩ 15 kΩ LPC408x/7x USB-A connector Mini-AB connector 33 Ω 33 Ω 33 Ω 33 Ω VDD VDD VDD USB_UP_LED2 VDD USB_OVRCR2 LM3526-L ENA IN 5 V OUTA FLAGA VDD D+ DVBUS USB_PPWR2 USB_D+2 USB_D-2 002aah269 R7 R4 R5 R6 R1 R2 R3 R4 R8 USB_INT1 RESET_N ADR/PSW SPEED SUSPEND OE_N/INT_N SCL SDA INT_N VBUS ID DP DM ISP1302 VSSIO, VSSCORE VSSIO, VSSCORE LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 116 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 37. USB OTG port configuration: VP_VM mode USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 USB_SCL1 USB_SDA1 SPEED ADR/PSW SDA SCL RESET_N INT_N VP VM SUSPEND OE_N/INT_N SE0_VM DAT_VP RCV VBUS ID DP DM LPC408x/7x ISP1302 USB MINI-AB connector 33 Ω 33 Ω 002aah270 USB_TX_E1 RSTOUT VDD VDD USB_INT1 USB_UP_LED1 VDD VSSIO, VSSCORE LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 117 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 38. USB host port configuration: port 1 and port 2 as hosts USB_UP_LED1 USB_D+1 USB_D-1 USB_PWRD1 USB_PWRD2 15 kΩ 15 kΩ 15 kΩ 15 kΩ LPC408x/7x USB-A connector USB-A connector 33 Ω 33 Ω 33 Ω 33 Ω 002aah271 VDD USB_UP_LED2 VDD USB_OVRCR1 USB_OVRCR2 USB_PPWR1 LM3526-L ENA ENB IN 5 V FLAGA OUTA OUTB FLAGB VDD VDD D+ DD+ DVBUS VBUS USB_PPWR2 USB_D+2 USB_D-2 VSSIO, VSSCORE VSSIO, VSSCORE LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 118 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 13.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. Fig 39. USB device port configuration: port 1 host and port 2 device USB_UP_LED1 USB_D+1 USB_D-1 USB_PWRD1 15 kΩ 15 kΩ LPC408x/7x USB-A connector USB-B connector 33 Ω 33 Ω 33 Ω 33 Ω 002aah272 VDD USB_UP_LED2 USB_CONNECT2 VDD VDD USB_OVRCR1 USB_PPWR1 LM3526-L ENA IN 5 V FLAGA OUTA VDD D+ DD+ DVBUS USB_D+2 USB_D-2 VBUS VBUS VSSIO, VSSCORE VSSIO, VSSCORE Fig 40. Slave mode operation of the on-chip oscillator LPC40xx XTAL1 Ci 100 pF Cg 002aah273 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 119 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 40), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 41 and in Table 34 and Table 35. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 41 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. Fig 41. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 34. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1/CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF 002aah274 LPC40xx XTALIN XTALOUT CX1 CX2 XTAL = CL CP RS L LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 120 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 13.3 XTAL Printed-Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plane. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Smaller values of Cx1 and Cx2 should be chosen according to the increase in parasitics of the PCB layout. 13.4 Standard I/O pin configuration Figure 42 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver: Open-drain mode enabled/disabled • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. Table 35. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 121 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 13.5 Reset pin configuration 13.6 Reset pin configuration for RTC operation Under certain circumstances, the RTC may temporarily pause and lose fractions of a second during the rising and falling edges of the RESET signal. Fig 42. Standard I/O pin configuration with analog input PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aaf272 pin configured as digital output driver pin configured as digital input pin configured as analog input Fig 43. Reset pin configuration VSS reset 002aaf274 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 122 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller To eliminate the loss of time counts in the RTC due to voltage swing or ramp rate of the RESET signal, connect an RC filter between the RESET pin and the external reset input. Fig 44. Reset input with RC filter 002aag552 External RESET input 10 kΩ 0.1 μF RESET pin LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 123 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 14. Package outline Fig 45. Package outline SOT459-1 (LQFP208) UNIT A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 0.5 30.15 29.85 1.43 1.08 7 0 o 1 0.12 0.08 0.08 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT459-1 136E30 MS-026 00-02-06 03-02-20 D(1) 28.1 27.9 HD 30.15 29.85 Z E 1.43 1.08 D pin 1 index e bp θ E A A1 Lp detail X L (A 3 ) B 52 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 208 157 156 105 104 53 y w M w M 0 5 10 mm scale LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 A max. 1.6 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 124 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 46. Package outline SOT950-1 (TFBGA208) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT950-1 - - - SOT950-1 06-06-01 06-06-14 UNIT A max mm 1.2 0.4 0.3 0.8 0.6 15.1 14.9 15.1 14.9 0.8 12.8 0.15 0.08 0.1 A1 DIMENSIONS (mm are the original dimensions) TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm 0 5 10 mm scale A2 b 0.5 0.4 D E e e1 e2 12.8 v w y 0.12 y1 C y1 C y X b ball A1 index area e2 e1 e e ∅ v M C A B ∅ w M C A B C D E F H K G L J M N P R U T 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 17 ball A1 index area D B A E detail X A A2 A1 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 125 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 47. Package outline SOT570-3 (TFBGA180) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT570-3 SOT570-3 08-07-09 10-04-15 UNIT mm max nom min 1.20 1.06 0.95 0.40 0.35 0.30 0.50 0.45 0.40 12.1 12.0 11.9 12.1 12.0 11.9 0.8 10.4 0.15 0.12 A DIMENSIONS (mm are the original dimensions) TFBGA180: thin fine-pitch ball grid array package; 180 balls 0 5 10 mm scale A1 A2 0.80 0.71 0.65 b D E e e1 10.4 e2 v w 0.05 y y1 0.1 ball A1 index area D B A E C y1 C y X A B C D E F H K G L J M N P 2 4 6 8 10 12 14 1 3 5 7 9 11 13 b e2 e1 e e 1/2 e 1/2 e ∅ v M C A B ∅ w M C ball A1 index area detail X A A2 A1 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 126 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 48. Package outline SOT486-1 (LQFP144) UNIT A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.5 22.15 21.85 1.4 1.1 7 0 o 1 0.2 0.08 0.08 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT486-1 136E23 MS-026 00-03-14 03-02-20 D(1) (1) (1) 20.1 19.9 HD 22.15 21.85 Z E 1.4 1.1 D 0 5 10 mm scale e bp θ E A1 A Lp detail X L (A 3 ) B c bp HE A2 HD v M B D ZD A ZE e v M A X y w M w M A max. 1.6 LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 108 109 pin 1 index 73 72 37 1 144 36 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 127 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 49. Package outline SOT407-1 (LQFP100) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o 1 0.2 0.08 0.08 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT407-1 136E20 MS-026 00-02-01 03-02-20 D(1) (1) (1) 14.1 13.9 HD 16.25 15.75 Z E 1.15 0.85 D bp e θ E A1 A Lp detail X L (A 3 ) B 25 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 100 76 75 51 50 26 y pin 1 index w M w M 0 5 10 mm scale LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 128 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 50. Package outline SOT315-1 (LQFP80) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 0.5 14.15 13.85 1.45 1.05 7 0 o 1 0.2 0.15 0.1 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.30 SOT315-1 136E15 MS-026 00-01-19 03-02-25 D(1) (1) (1) 12.1 11.9 HD 14.15 13.85 Z E 1.45 1.05 D bp e θ E A1 A Lp detail X L (A 3 ) B 20 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 80 61 60 41 40 21 y pin 1 index w M w M 0 5 10 mm scale LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 129 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 51. Package outline SOT1328-1 (TFBGA80) Outline References version European projection Issue date IEC JEDEC JEITA SOT1328-1 sot1328-1_po 12-05-07 12-06-14 Unit mm max nom min 1.15 1.00 0.90 0.35 0.30 0.25 0.45 0.40 0.35 7.1 7.0 6.9 7.1 7.0 6.9 0.65 5.85 0.15 0.08 A Dimensions (mm are the original dimensions) TFBGA80: plastic thin fine-pitch ball grid array package; 80 balls SOT1328-1 A1 A2 0.80 0.70 0.65 b D E e e1 5.85 e2 v w 0.05 y y1 0.1 0 5 mm scale ball A1 index area ball A1 index area D B A E detail X A A1 A2 C y1 C y X e2 e 1/2 e b e1 e 1/2 e Ø v C A B Ø w C 1 2 3 4 5 6 7 8 9 10 K J H G F E D C B A LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 130 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 15. Soldering Fig 52. Reflow soldering of the LQFP208 package SOT459-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP208 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy sot459-1_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout 0.500 0.560 31.300 31.300 28.300 28.300 1.500 0.280 0.400 28.500 28.500 31.550 31.550 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 131 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 53. Reflow soldering of the TFBGA180 package DIMENSIONS in mm P SL SP SR Hx Hy Hx Hy SOT570-3 solder land plus solder paste occupied area Footprint information for reflow soldering of TFBGA180 package solder land solder paste deposit solder resist P P SL SP SR Generic footprint pattern Refer to the package outline drawing for actual layout detail X see detail X sot570-3_fr 0.80 0.400 0.400 0.550 12.575 12.575 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 132 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 54. Reflow soldering of the LQFP144 package SOT486-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP144 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy sot486-1_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout 0.500 0.560 23.300 23.300 20.300 20.300 1.500 0.280 0.400 20.500 20.500 23.550 23.550 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 133 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 55. Reflow soldering of the LQFP100 package SOT407-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP100 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy sot407-1 solder land C Generic footprint pattern Refer to the package outline drawing for actual layout 0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 134 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Fig 56. Reflow soldering of the LQFP80 package SOT315-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP80 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 15.300 15.300 12.300 12.300 P1 0.500 P2 0.560 0.280 C 1.500 0.400 12.500 12.500 15.550 15.550 sot315-1_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 135 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 16. Abbreviations Table 36. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DMA Direct Memory Access EOP End Of Packet ETM Embedded Trace Macrocell GPIO General Purpose Input/Output GPS Global Positioning System HVAC Heating, Venting, and Air Conditioning IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLC Programmable Logic Controller PLL Phase-Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCM Tightly Coupled Memory TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 136 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 17. Revision history Table 37. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC408X_7X v.3 20140501 Product data sheet - LPC408X_7X v.2 • Added TFBGA80 to features list. • Added Section 11.11 “SPIFI”. • Table 3: – Added function SSP2_SCK to pin P5[2]. – Added function SSP2_SSEL to pin P5[3]. – Updated pin description of STCLK. – 5 ns glitch filter changed to 10 ns for EINTx pins. – LQFP80 pin 12 changed from P2[30] to DNC. • Table 11: Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.”. • Table 28: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.”. • Section 7.37.2 “Brownout detection”: Updated BOD interrupt and reset values. • Table 15: Added typical specs. • Table 16: – Added typical specs – Removed “All programmable delays EMCDLYCTL are bypassed” from table title. • Table 17: – Added typical specs – Removed “All programmable delays EMCDLYCTL are bypassed” from table title. • Table note 9 added in Table 28 “12-bit ADC characteristics”. LPC408X_7X v.2 20130703 Product data sheet - LPC408X_7X v.1.1 • Added LQFP100 and TFBGA80. • Table 3: – Removed overbar from NMI. – Added minimum reset pulse width of 50 ns to RESET pin. – Updated Table note 14 for RTCX pins (32 kHz crystal must be used to operate RTC). – Added boundary scan information to description for RESET pin. • Table 11: – Updated typ numbers for IDD(REG)(3V3) and IBAT. – Added max values for deep sleep, power down, and deep PD for IBAT. • Table 15, Table note 3: Changed Tcy(clk) = 1/CCLK to Tcy(clk) = 1/EMC_CLK. • Table 21: Removed reference to RESET pin from Table note 1. • Table 22: – Removed Tcy(PCLK) spec; already given by the maximum chip frequency. – Changed min clock cyle time for SSP slave from 120 to 100. – Updated Table note 1 and Table note 3. • Section 7.24.1 “Features”: Changed max speed for SSP master from 60 to 33. • Updated EMC timing specs to CL = 30 pF in Table 15, Table 16, Table 17, and Table 18. • SOT570-2 obsolete; replaced with SOT570-3. LPC408X_7X v.1.1 20121114 Product data sheet - LPC408X_7X v.1 LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 137 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Modifications: • Changed data sheet status to Product. LPC408X_7X v.1 20120917 Objective data sheet - - Table 37. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 138 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 139 of 141 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC408X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 3 — 1 May 2014 140 of 141 continued >> NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 52 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 52 7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 52 7.3 ARM Cortex-M4 Floating Point Unit (FPU). . . 52 7.4 On-chip flash program memory . . . . . . . . . . . 52 7.5 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.6 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 52 7.7 Memory Protection Unit (MPU). . . . . . . . . . . . 53 7.8 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.9 Nested Vectored Interrupt Controller (NVIC) . 56 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.9.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 56 7.10 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 56 7.11 External Memory Controller (EMC). . . . . . . . . 56 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.12 General purpose DMA controller . . . . . . . . . . 58 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.13 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.14 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 59 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.15 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.16 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.16.1 USB device controller . . . . . . . . . . . . . . . . . . . 61 7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.16.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 62 7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.16.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 62 7.16.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.17 SD/MMC card interface . . . . . . . . . . . . . . . . . 62 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.18 Fast general purpose parallel I/O . . . . . . . . . . 63 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.19 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.20 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.21 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.22 UART0/1/2/3 and USART4 . . . . . . . . . . . . . . 65 7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.23 SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.24 SSP serial I/O controller. . . . . . . . . . . . . . . . . 66 7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.25 I2C-bus serial I/O controllers . . . . . . . . . . . . . 66 7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.26 I2S-bus serial I/O controllers . . . . . . . . . . . . . 67 7.26.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.27 CAN controller and acceptance filters . . . . . . 67 7.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.28 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.29 Pulse Width Modulator (PWM). . . . . . . . . . . . 69 7.29.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.30 Motor control PWM . . . . . . . . . . . . . . . . . . . . 70 7.31 Quadrature Encoder Interface (QEI) . . . . . . . 70 7.31.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.32 ARM Cortex-M4 system tick timer . . . . . . . . . 71 7.33 Windowed WatchDog Timer (WWDT) . . . . . . 71 7.33.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.34 RTC and backup registers . . . . . . . . . . . . . . . 72 7.34.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.35 Event monitor/recorder . . . . . . . . . . . . . . . . . 72 7.35.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.36 Clocking and power control . . . . . . . . . . . . . . 73 7.36.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 73 7.36.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 74 7.36.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 74 7.36.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 74 7.36.1.4 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 74 7.36.2 Main PLL (PLL0) and Alternate PLL (PLL1) . 74 7.36.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 75 7.36.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.36.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.36.4.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 76 7.36.4.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 77 7.36.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 77 7.36.4.5 Wake-up Interrupt Controller (WIC) . . . . . . . . 77 7.36.5 Peripheral power control . . . . . . . . . . . . . . . . 78 7.36.6 Power domains . . . . . . . . . . . . . . . . . . . . . . . 78 7.37 System control . . . . . . . . . . . . . . . . . . . . . . . . 79 7.37.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.37.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 80 7.37.3 Code security (Code Read Protection - CRP) 80 NXP Semiconductors LPC408x/7x 32-bit ARM Cortex-M4 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 May 2014 Document identifier: LPC408X_7X Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 7.37.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.37.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 81 7.37.6 External interrupt inputs . . . . . . . . . . . . . . . . . 81 7.37.7 Memory mapping control . . . . . . . . . . . . . . . . 81 7.38 Debug control . . . . . . . . . . . . . . . . . . . . . . . . . 81 8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 81 9 Thermal characteristics . . . . . . . . . . . . . . . . . 83 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 85 10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 88 10.2 Peripheral power consumption . . . . . . . . . . . . 90 10.3 Electrical pin characteristics . . . . . . . . . . . . . . 92 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 94 11.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 94 11.2 External memory interface . . . . . . . . . . . . . . . 95 11.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . 101 11.4 Internal oscillators. . . . . . . . . . . . . . . . . . . . . 101 11.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 102 11.7 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.8 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 105 11.9 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.10 SD/MMC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.11 SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12 Characteristics of the analog peripherals . . 108 12.1 ADC electrical characteristics . . . . . . . . . . . . 108 12.2 DAC electrical characteristics . . . . . . . . . . . 111 12.3 Comparator electrical characteristics . . . . . . 112 13 Application information. . . . . . . . . . . . . . . . . 114 13.1 Suggested USB interface solutions . . . . . . . 114 13.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.3 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.4 Standard I/O pin configuration . . . . . . . . . . . 120 13.5 Reset pin configuration. . . . . . . . . . . . . . . . . 121 13.6 Reset pin configuration for RTC operation . . 121 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . 123 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 135 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . 136 18 Legal information. . . . . . . . . . . . . . . . . . . . . . 138 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 138 18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 138 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 138 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 139 19 Contact information. . . . . . . . . . . . . . . . . . . . 139 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 1. Introduction This document describes the functionality and electrical specifications of the transceiver IC PN512. The PN512 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. 1.1 Different available versions The PN512 is available in three versions: • PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2 (TFBGA64), hereafter named as version 2.0 • PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In), hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs). • PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named as version 1.0 The data sheet describes the functionality for the industrial version and version 2.0. The differences of the version 1.0 to the version 2.0 are summarized in Section 21. The industrial version has only differences within the outlined characteristics and limitations. 2. General description The PN512 transceiver ICs support 4 different operating modes • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Reader/Writer mode supporting ISO/IEC 14443B • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and PN512 Full NFC Forum compliant solution Rev. 4.5 — 17 December 2013 111345 Product data sheet COMPANY PUBLIC PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 2 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC). The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both directions. Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented. In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card functionality is only possible in combination with a secure IC using the S2C interface. Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection. Various host controller interfaces are implemented: • 8-bit parallel interface1 • SPI interface • serial UART (similar to RS232 with voltage levels according pad voltage supply) • I2C interface. A purchaser of this NXP IC has to take care for appropriate third party patent licenses. 1. 8-bit parallel Interface only available in HVQFN40 package. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 3 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 3. Features and benefits  Highly integrated analog circuitry to demodulate and decode responses  Buffered output drivers for connecting an antenna with the minimum number of external components  Integrated RF Level detector  Integrated data mode detector  Supports ISO/IEC 14443 A/MIFARE  Supports ISO/IEC 14443 B Read/Write modes  Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning  Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna size and tuning and power supply  Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation mode of about 100 mm depending on the antenna size and tuning and the external field strength  Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode  ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s  Contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s  Integrated RF interface for NFCIP-1 up to 424 kbit/s  S2C interface  Additional power supply to directly supply the smart card IC connected via S2C  Supported host interfaces  SPI up to 10 Mbit/s  I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode  RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply  8-bit parallel interface with and without Address Latch Enable  FIFO buffer handles 64 byte send and receive  Flexible interrupt modes  Hard reset with low power function  Power-down mode per software  Programmable timer  Internal oscillator for connection to 27.12 MHz quartz crystal  2.5 V to 3.6 V power supply  CRC coprocessor  Programmable I/O pins  Internal self-test PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 4 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 4. Quick reference data [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. [4] Ipd is the total current for all supplies. [5] IDD(PVDD) depends on the overall load at the digital pins. [6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz. Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V VDDD digital supply voltage VDD(TVDD) TVDD supply voltage VDD(PVDD) PVDD supply voltage [3] 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [4]- - 5 A soft power-down; RF level detector on [4]- - 10 A IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register’s RcvOff bit = 1 - 3 5 mA IDD(PVDD) PVDD supply current pin PVDD [5]- - 40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8]- 60 100 mA Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 +85 C lndustrial version: Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [4]- - 15 A soft power-down; RF level detector on [4]- - 30 A Tamb ambient temperature HVQFN32 40 - +90 C PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 5 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 5. Ordering information Table 2. Ordering information Type number Package Name Description Version PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-1 PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-1 PN5120A0ET/C2 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT1336-1 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 6 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN512. The communication (S2C) interface provides digital signals to support communication for transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC. The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa. Various host interfaces are implemented to meet different customer requirements. Fig 1. Simplified block diagram of the PN512 001aaj627 HOST ANTENNA FIFO BUFFER ANALOG INTERFACE CONTACTLESS UART SERIAL UART SPI I2C-BUS REGISTER BANK PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 7 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 2. Detailed block diagram of the PN512 001aak602 DVDD NRSTPD IRQ MFIN MFOUT SVDD OSCIN OSCOUT VMID AUX1 AUX2 RX TVSS TX1 TX2 TVDD 16 19 20 17 10, 14 11 13 12 DVSS AVDD SDA/NSS/RX EA I2C PVDD PVSS 24 32 1 2 5 D1/ADR_5 25 D2/ADR_4 26 D3/ADR_3 27 D4/ADR_2 28 D5/ADR_1/ SCK/DTRQ 29 D6/ADR_0/ MOSI/MX 30 D7/SCL/ MISO/TX 31 AVSS 3 6 23 7 8 9 21 22 4 15 18 FIFO CONTROL MIFARE CLASSIC UNIT STATE MACHINE COMMAND REGISTER PROGRAMABLE TIMER INTERRUPT CONTROL CRC16 GENERATION AND CHECK PARALLEL/SERIAL CONVERTER SERIAL DATA SWITCH TRANSMITTER CONTROL BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK BIT DECODING BIT ENCODING RANDOM NUMBER GENERATOR ANALOG TO DIGITAL CONVERTER I-CHANNEL AMPLIFIER ANALOG TEST MULTIPLEXOR AND DIGITAL TO ANALOG CONVERTER I-CHANNEL DEMODULATOR Q-CHANNEL AMPLIFIER CLOCK GENERATION, FILTERING AND DISTRIBUTION Q-CLOCK GENERATION OSCILLATOR TEMPERATURE SENSOR Q-CHANNEL DEMODULATOR AMPLITUDE RATING REFERENCE VOLTAGE 64-BYTE FIFO BUFFER CONTROL REGISTER BANK SPI, UART, I2C-BUS INTERFACE CONTROL VOLTAGE MONITOR AND POWER ON DETECT RESET CONTROL POWER-DOWN CONTROL PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 8 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1) Fig 4. Pinning configuration HVQFN40 (SOT618-1) 001aan212 PN512 Transparent top view RX SIGIN SIGOUT AVSS NRSTPD AUX1 PVSS AUX2 DVSS OSCIN DVDD OSCOUT PVDD IRQ A1 ALE SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID A0 D7 D6 D5 D4 D3 D2 D1 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 001aan213 PN512 AVSS NRSTPD SIGIN AUX1 PVSS AUX2 DVSS OSCIN DVDD OSCOUT PVDD IRQ A5 NWR A4 NRD A3 ALE A2 NCS SIGOUT SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID RX A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 terminal 1 index area Transparent top view PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 9 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 5. Pin configuration TFBGA64 (SOT1336-1) aaa-005873 TFBGA64 Transparent top view ball A1 index area H G F E D C B A 1 2 3 4 5 6 7 8 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 10 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 7.2 Pin description Table 3. Pin description HVQFN32 Pin Symbol Type Description 1 A1 I Address Line 2 PVDD PWR Pad power supply 3 DVDD PWR Digital Power Supply 4 DVSS PWR Digital Ground 5 PVSS PWR Pad power supply ground 6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. 7 SIGIN I Communication Interface Input: accepts a digital, serial data stream 8 SIGOUT O Communication Interface Output: delivers a serial data stream 9 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads 10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 15 AVDD PWR Analog Power Supply 16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 17 RX I Receiver Input 18 AVSS PWR Analog Ground 19 AUX1 O Auxiliary Outputs: These pins are used for testing. 20 AUX2 O 21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). 22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 23 IRQ O Interrupt Request: output to signal an interrupt event 24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus. Remark: An 8-bit parallel interface is not available. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. Remark: For serial interfaces this pins can be used for test signals or I/Os. 32 A0 I Address Line PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 11 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 4. Pin description HVQFN40 Pin Symbol Type Description 1 to 4 A2 to A5 I Address Line 5 PVDD PWR Pad power supply 6 DVDD PWR Digital Power Supply 7 DVSS PWR Digital Ground 8 PVSS PWR Pad power supply ground 9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. 10 SIGIN I Communication Interface Input: accepts a digital, serial data stream 11 SIGOUT O Communication Interface Output: delivers a serial data stream 12 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads 13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 18 AVDD PWR Analog Power Supply 19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 20 RX I Receiver Input 21 AVSS PWR Analog Ground 22 AUX1 O Auxiliary Outputs: These pins are used for testing. 23 AUX2 O 24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). 25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 26 IRQ O Interrupt Request: output to signal an interrupt event 27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register 28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7) 29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512 31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. 39 to 40 A0 to A1 I Address Line PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 12 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 5. Pin description TFBGA64 Pin Symbol Type Description A1 to A5, A8, B3, B4, B8, E1 PVSS PWR Pad power supply ground A6 D4 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. A7 D2 I/O B1 PVDD PWR Pad power supply B2 A0 I Address Line B5 D5 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. B6 D3 I/O B7 D1 I/O C1 DVDD PWR Digital Power Supply C2 A1 I Address Line C3 D7 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. C4 D6 I/O C5 IRQ O Interrupt Request: output to signal an interrupt event C6 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. C7, C8, D6, D8, E6, E8, F7, G8, H8 AVSS PWR Analog Ground D1 DVSS PWR Digital Ground D2 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. D3 to D5, E3 to E5, F3, F4, G1 to G6, H1, H2, H6 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 D7 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. E2 SIGIN I Communication Interface Input: accepts a digital, serial data stream E7 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12MHz). F1 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads F2 SIGOUT O Communication Interface Output: delivers a serial data stream F5 AUX1 O Auxiliary Outputs: These pins are used for testing. F6 AUX2 O F8 RX I Receiver Input G7 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. H3 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 13 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier H7 AVDD PWR Analog Power Supply Table 5. Pin description TFBGA64 Pin Symbol Type Description PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 14 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8. Functional description The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols. PN512 transceiver IC supports the following operating modes: • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail. Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance. 8.1 ISO/IEC 14443 A/MIFARE functionality The physical level communication is shown in Figure 7. The physical parameters are described in Table 4. Fig 6. PN512 Read/Write mode 001aan218 BATTERY reader/writer contactless card MICROCONTROLLER PN512 ISO/IEC 14443 A CARD Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer Communication direction Signal type Transfer speed 106 kBd 212 kBd 424 kBd Reader to card (send data from the PN512 to a card) reader side modulation 100 % ASK 100 % ASK 100 % ASK bit encoding modified Miller encoding modified Miller encoding modified Miller encoding bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s) (1) (2) 001aan219 PN512 ISO/IEC 14443 A CARD ISO/IEC 14443 A READER PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 15 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The PN512’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol. Figure 8 shows the data coding and framing according to ISO/IEC 14443 A/MIFARE. The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the ManualRCVReg register’s ParityDisable bit. 8.2 ISO/IEC 14443 B functionality The PN512 reader IC fully supports international standard ISO 14443 which includes communication schemes ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. Card to reader (PN512 receives data from a card) card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit encoding Manchester encoding BPSK BPSK Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued Communication direction Signal type Transfer speed 106 kBd 212 kBd 424 kBd Fig 8. Data coding and framing according to ISO/IEC 14443 A 001aak585 ISO/IEC 14443 A framing at 106 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start odd start bit is 1 parity ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start even parity start bit is 0 burst of 32 subcarrier clocks even parity at the end of the frame PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 16 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.3 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. The contactless UART of PN512 and a dedicated external host controller are required to handle the complete FeliCa protocol. 8.3.1 FeliCa framing and coding To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver. The following Len byte indicates the length of the sent data bytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first. To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the PN512 automatically and must not be written to the FIFO by the host controller. The PN512 performs internally the CRC calculation and adds the result to the data frame. Example for FeliCa CRC Calculation: Fig 9. FeliCa reader/writer communication diagram Table 7. Communication overview for FeliCa reader/writer Communication direction FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s PN512  card Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s card  PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK bit coding Manchester coding Manchester coding 2. PICC to PCD, > 12 % ASK loadmodulation Manchester coded, baudrate 212 to 424 kbaud 1. PCD to PICC, 8-30 % ASK Manchester coded, baudrate 212 to 424 kbaud 001aan214 PN512 FeliCa CARD (PICC) Felica READER (PCD) Table 8. FeliCa framing and coding Preamble Sync Len n-Data CRC 00h 00h 00h 00h 00h 00h B2h 4Dh Table 9. Start value for the CRC Polynomial: (00h), (00h) Preamble Sync Len 2 Data Bytes CRC 00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35h PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 17 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4 NFCIP-1 mode The NFCIP-1 communication differentiates between an active and a Passive Communication mode. • Active Communication mode means both the initiator and the target are using their own RF field to transmit data. • Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active in terms of generating the RF field. • Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication • Target: responds to initiator command either in a load modulation scheme in Passive Communication mode or using a self generated and self modulated RF field for Active Communication mode. In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. Fig 10. NFCIP-1 mode 001aan215 BATTERY initiator: active target: passive or active MICROCONTROLLER PN512 BATTERY MICROCONTROLLER PN512 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 18 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated external circuits. Fig 11. Active communication mode Table 10. Communication overview for Active communication mode Communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s Initiator  Target According to ISO/IEC 14443A 100 % ASK, Modified Miller Coded According to FeliCa, 8-30 % ASK Manchester Coded digital capability to handle Target  Initiator this communication host NFC INITIATOR powered to generate RF field 1. initiator starts communication at selected transfer speed Initial command response 2. target answers at the same transfer speed host NFC INITIATOR powered for digital processing host host NFC TARGET NFC TARGET powered for digital processing powered to generate RF field 001aan216 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 19 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated external circuits. Fig 12. Passive communication mode Table 11. Communication overview for Passive communication mode Communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s Initiator  Target According to ISO/IEC 14443A 100 % ASK, Modified Miller Coded According to FeliCa, 8-30 % ASK Manchester Coded digital capability to handle this communication Target  Initiator According to ISO/IEC 14443A subcarrier load modulation, Manchester Coded According to FeliCa, > 12 % ASK Manchester Coded host NFC INITIATOR powered to generate RF field 1. initiator starts communication at selected transfer speed 2. targets answers using load modulated data at the same transfer speed host NFC TARGET powered for digital processing 001aan217 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 20 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. 8.4.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is according to the following policy: • Speed shall not be changed while continuum data exchange in a transaction. • Transaction includes initialization and anticollision methods and data exchange (in continuous way, meaning no interruption by another transaction). In order not to disturb current infrastructure based on 13.56 MHz general rules to start NFCIP-1 communication are defined in the following way. 1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off. 2. The RF level detector is active. 3. Only if application requires the NFCIP-1 device shall switch to Initiator mode. 4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level detector during a time of TIDT. 5. The initiator performs initialization according to the selected mode. 8.4.5 MIFARE Card operation mode Table 12. Framing and coding overview Transfer speed Framing and Coding 106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme Table 13. MIFARE Card operation mode Communication direction ISO/IEC 14443A/ MIFARE MIFARE Higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s reader/writer  PN512 Modulation on reader side 100 % ASK 100 % ASK 100 % ASK bit coding Modified Miller Modified Miller Modified Miller Bitlength (128/13.56) s (64/13.56) s (32/13.56) s PN512  reader/ writer Modulation on PN512 side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding Manchester coding BPSK BPSK PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 21 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.6 FeliCa Card operation mode 9. PN512 register SET 9.1 PN512 registers overview Table 14. FeliCa Card operation mode Communication direction FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s reader/writer  PN512 Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s PN512  reader/ writer Load modulation on PN512 side > 12 % ASK load modulation > 12 % ASK load modulation bit coding Manchester coding Manchester coding Table 15. PN512 registers overview Addr (hex) Register Name Function Page 0: Command and Status 0 PageReg Selects the register page 1 CommandReg Starts and stops command execution 2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests 3 DivlEnReg Controls bits to enable and disable the passing of Interrupt Requests 4 ComIrqReg Contains Interrupt Request bits 5 DivIrqReg Contains Interrupt Request bits 6 ErrorReg Error bits showing the error status of the last command executed 7 Status1Reg Contains status bits for communication 8 Status2Reg Contains status bits of the receiver and transmitter 9 FIFODataReg In- and output of 64 byte FIFO-buffer A FIFOLevelReg Indicates the number of bytes stored in the FIFO B WaterLevelReg Defines the level for FIFO under- and overflow warning C ControlReg Contains miscellaneous Control Registers D BitFramingReg Adjustments for bit oriented frames E CollReg Bit position of the first bit collision detected on the RF-interface F RFU Reserved for future use Page 1: Command 0 PageReg Selects the register page 1 ModeReg Defines general modes for transmitting and receiving 2 TxModeReg Defines the data rate and framing during transmission 3 RxModeReg Defines the data rate and framing during receiving 4 TxControlReg Controls the logical behavior of the antenna driver pins TX1 and TX2 5 TxAutoReg Controls the setting of the antenna drivers PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 22 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6 TxSelReg Selects the internal sources for the antenna driver 7 RxSelReg Selects internal receiver settings 8 RxThresholdReg Selects thresholds for the bit decoder 9 DemodReg Defines demodulator settings A FelNFC1Reg Defines the length of the valid range for the receive package B FelNFC2Reg Defines the length of the valid range for the receive package C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit D ManualRCVReg Allows manual fine tuning of the internal receiver E TypeBReg Configure the ISO/IEC 14443 type B F SerialSpeedReg Selects the speed of the serial UART interface Page 2: CFG 0 PageReg Selects the register page 1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation 2 3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when the driver is switched off 4 ModWidthReg Controls the setting of the ModWidth 5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit 6 RFCfgReg Configures the receiver gain and RF level 7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation when the drivers are switched on 8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during times of no modulation 9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during modulation A TModeReg TPrescalerReg Defines settings for the internal timer B C TReloadReg Describes the 16-bit timer reload value D E TCounterValReg Shows the 16-bit actual timer value F Page 3: TestRegister 0 PageReg selects the register page 1 TestSel1Reg General test signal configuration 2 TestSel2Reg General test signal configuration and PRBS control 3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial interfaces only) 4 TestPin ValueReg Defines the values for the 8-bit parallel bus when it is used as I/O bus 5 TestBusReg Shows the status of the internal testbus 6 AutoTestReg Controls the digital selftest Table 15. PN512 registers overview …continued Addr (hex) Register Name Function PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 23 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.1.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In Table 16 the access conditions are described. 7 VersionReg Shows the version 8 AnalogTestReg Controls the pins AUX1 and AUX2 9 TestDAC1Reg Defines the test value for the TestDAC1 A TestDAC2Reg Defines the test value for the TestDAC2 B TestADCReg Shows the actual value of ADC I and Q C-F RFT Reserved for production tests Table 15. PN512 registers overview …continued Addr (hex) Register Name Function Table 16. Behavior of register bits and its designation Abbreviation Behavior Description r/w read and write These bits can be written and read by the -Controller. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the PageSelect-Register may be written and read by the -Controller. It will also be read by internal state machines, but never changed by them. dy dynamic These bits can be written and read by the -Controller. Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command. r read only These registers hold bits, which value is determined by internal states only, e.g. the CRCReady bit can not be written from external but shows internal states. w write only Reading these registers returns always ZERO. RFU - These registers are reserved for future use. In case of a PN512 Version version 2.0 (VersionReg = 82h) a read access to these registers returns always the value “0”. Nevertheless this is not guaranteed for future chips versions where the value is undefined. In case of a write access, it is recommended to write always the value “0”. RFT - These registers are reserved for production tests and shall not be changed. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 24 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2 Register description 9.2.1 Page 0: Command and status 9.2.1.1 PageReg Selects the register page. 9.2.1.2 CommandReg Starts and stops command execution. Table 17. PageReg register (address 00h); reset value: 00h, 0000000b 7 6 5 4 3 2 1 0 UsePage Select 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 18. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case it specifies the register page (which is A5 and A4 of the register address). Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 RcvOff Power Down Command Access Rights RFU RFU r/w dy dy dy dy dy Table 20. Description of CommandReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 RcvOff Set to logic 1, the analog part of the receiver is switched off. 4 PowerDown Set to logic 1, Soft Power-down mode is entered. Set to logic 0, the PN512 starts the wake up procedure. During this procedure this bit still shows a 1. A 0 indicates that the PN512 is ready for operations; see Section 16.2 “Soft power-down mode”. Note: The bit Power Down cannot be set, when the command SoftReset has been activated. 3 to 0 Command Activates a command according to the Command Code. Reading this register shows, which command is actually executed (see Section 19.3 “PN512 command overview”). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 25 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 22. Description of CommIEnReg bits Bit Symbol Description 7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of 1 ensures, that the output level on pin IRQ is 3-state. 6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. 5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. 4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. 3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. 2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. 1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated to pin IRQ. 0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 26 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn Access Rights r/w RFU RFU r/w r/w r/w r/w r/w Table 24. Description of DivIEnReg bits Bit Symbol Description 7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad. Set to logic 0, the pin IRQ works as open drain output pad. 6 to 5 - Reserved for future use. 4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ. 3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be propagated to pin IRQ. 2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be propagated to pin IRQ. 1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to be propagated to pin IRQ. 0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to be propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 27 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b 7 6 5 4 3 2 1 0 Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq Access Rights w dy dy dy dy dy dy dy Table 26. Description of CommIRqReg bits All bits in the register CommIRqReg shall be cleared by software. Bit Symbol Description 7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg are cleared. 6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out. 5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream. If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set to logic 1 when data bytes are available in the FIFO. 4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq. 3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1. 2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1. 1 ErrIRq Set to logic 1 if any error bit in the Error Register is set. 0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 28 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb 7 6 5 4 3 2 1 0 Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq Access Rights w RFU RFU dy dy dy dy dy Table 28. Description of DivIRqReg bits All bits in the register DivIRqReg shall be cleared by software. Bit Symbol Description 7 Set2 Set to logic 1, Set2 defines that the marked bits in the register DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register DivIRqReg are cleared 6 to 5 - Reserved for future use. 4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “S2C interface support”. This interrupt is set when either a rising or falling signal edge is detected. 3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode detector. Note: The Data mode detector can only be activated by the AutoColl command and is terminated automatically having detected the Communication mode. Note: The Data mode detector is automatically restarted after each RF Reset. 2 CRCIRq Set to logic 1, when the CRC command is active and all data are processed. 1 RFOnIRq Set to logic 1, when an external RF field is detected. 0 RFOffIRq Set to logic 1, when a present external RF field is switched off. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 29 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. [1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr Access Rights r r r r r r r r Table 30. Description of ErrorReg bits Bit Symbol Description 7 WrErr Set to logic 1, when data is written into FIFO by the host controller during the AutoColl command or MFAuthent command or if data is written into FIFO by the host controller during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface. 6 TempErr[1] Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically. 5 RFErr Set to logic 1, if in Active Communication mode the counterpart does not switch on the RF field in time as defined in NFCIP-1 standard. Note: RFErr is only used in Active Communication mode. The bits RxFraming or the bits TxFraming has to be set to 01 to enable this functionality. 4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine (e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer although the FIFO-buffer is already full. 3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit. During communication schemes at 212 and 424 kbit this bit is always set to logic 1. 2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the CRC calculation fails. It is cleared to 0 automatically at receiver start-up phase. 1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or NFCIP-1 communication at 106 kbit. 0 ProtocolErr Set to logic 1, if one out of the following cases occur: • Set to logic 1 if the SOF is incorrect. It is cleared automatically at receiver start-up phase. The bit is only valid for 106 kbit in Active and Passive Communication mode. • If bit DetectSync in register ModeReg is set to logic 1 during FeliCa communication or active communication with transfer speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in case of a byte length violation. • During the AutoColl command, bit ProtocolErr is set to logic 1, if the bit Initiator in register ControlReg is set to logic 1. • During the MFAuthent Command, bit ProtocolErr is set to logic 1, if the number of bytes received in one data stream is incorrect. • Set to logic 1, if the Miller Decoder detects 2 pulses below the minimum time according to the ISO/IEC 14443A definitions. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 30 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb 7 6 5 4 3 2 1 0 RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert Access Rights r r r r r r r r Table 32. Description of Status1Reg bits Bit Symbol Description 7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of 13.56 MHz. Set to logic 1, if the frequency at the RX pin is in the range 12 MHz < RX pin frequency < 15 MHz. Note: The value of RFFreqOK is not defined if the external RF frequency is in the range from 9 to 12 MHz or in the range from 15 to 19 MHz. 6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC co-processor, during calculation the value changes to ZERO, when the calculation is done correctly, the value changes to ONE. 5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only valid for the CRC co-processor calculation using the command CalcCRC. 4 IRq This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg). 3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will decrement the TCounterValReg with the next timer clock. Note: In the gated mode the bit TRunning is set to logic 1, when the timer is enabled by the register bits. This bit is not influenced by the gated signal. 2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store the state of the RF field. 1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer fulfills the following equation: Example: FIFOLength = 60, WaterLevel = 4  HiAlert = 1 FIFOLength = 59, WaterLevel = 4  HiAlert = 0 0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer fulfills the following equation: Example: FIFOLength = 4, WaterLevel = 4  LoAlert = 1 FIFOLength = 5, WaterLevel = 4  LoAlert = 0 HiAlert = 64 – FIFOLength   WaterLevel LoAlert = FIFOLength  WaterLevel PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 31 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TempSensClear I2CForceHS 0 TargetActivated MFCrypto1On Modem State Access Rights r/w r/w RFU dy dy r r r Table 34. Description of Status2Reg bits Bit Symbol Description 7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature is below the alarm limit of 125 C. 6 I2CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the High-speed mode independent of the I2C protocol. Set to logic 0, the I2C input filter is set to the used I2C protocol. 5 - Reserved for future use. 4 TargetActivated Set to logic 1 if the Select command or if the Polling command was answered. Note: This bit can only be set during the AutoColl command in Passive Communication mode. Note: This bit is cleared automatically by switching off the external RF field. 3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and therefore all data communication with the card is encrypted. This bit can only be set to logic 1 by a successful execution of the MFAuthent Command. This bit is only valid in Reader/Writer mode for MIFARE cards. This bit shall be cleared by software. 2 to 0 Modem State ModemState shows the state of the transmitter and receiver state machines. Value Description 000 IDLE 001 Wait for StartSend in register BitFramingReg 010 TxWait: Wait until RF field is present, if the bit TxWaitRF is set to logic 1. The minimum time for TxWait is defined by the TxWaitReg register. 011 Sending 100 RxWait: Wait until RF field is present, if the bit RxWaitRF is set to logic 1. The minimum time for RxWait is defined by the RxWaitReg register. 101 Wait for data 110 Receiving PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 32 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. 9.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 FIFOData Access Rights dy dy dy dy dy dy dy dy Table 36. Description of FIFODataReg bits Bit Symbol Description 7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The FIFO-buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs. Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 FlushBuffer FIFOLevel Access Rights w r r r r r r r Table 38. Description of FIFOLevelReg bits Bit Symbol Description 7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0. 6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the FIFODataReg increments, reading decrements the FIFOLevel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 33 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. 9.2.1.13 ControlReg Miscellaneous control bits. Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b 7 6 5 4 3 2 1 0 0 0 WaterLevel Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 40. Description of WaterLevelReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or underflow: The bit HiAlert in Status1Reg is set to logic 1, if the remaining number of bytes in the FIFO-buffer space is equal or less than the defined number of WaterLevel bytes. The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO. Note: For the calculation of HiAlert and LoAlert see Table 31 Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits Access Rights w w dy r/w RFU r r r Table 42. Description of ControlReg bits Bit Symbol Description 7 TStopNow Set to logic 1, the timer stops immediately. Reading this bit will always return 0. 6 TStartNow Set to logic 1 starts the timer immediately. Reading this bit will always return 0. 5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the FIFO. Afterwards the bit is cleared automatically 4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target 3 - Reserved for future use. 2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the whole byte is valid. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 34 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 StartSend RxAlign 0 TxLastBits Access Rights w r/w r/w r/w RFU r/w r/w r/w Table 44. Description of BitFramingReg bits Bit Symbol Description 7 StartSend Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command. 6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position for the first bit received to be stored in the FIFO. Further received bits are stored at the following bit positions. Example: RxAlign = 0: the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1. RxAlign = 1: the LSB of the received bit is stored at bit 1, the second received bit is stored at bit position 2. RxAlign = 7: the LSB of the received bit is stored at bit 7, the second received bit is stored in the following byte at bit position 0. This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive Communication mode. In all other modes it shall be set to logic 0. 3 - Reserved for future use. 2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 35 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb 7 6 5 4 3 2 1 0 Values AfterColl 0 CollPos NotValid CollPos Access Rights r/w RFU r r r r r r Table 46. Description of CollReg bits Bit Symbol Description 7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a collision. This bit shall only be used during bitwise anticollision at 106 kbit, otherwise it shall be set to logic 1. 6 - Reserved for future use. 5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the Collision is out of the range of bits CollPos. This bit shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode. 4 to 0 CollPos These bits show the bit position of the first detected collision in a received frame, only data bits are interpreted. Example: 00h indicates a bit collision in the 32th bit 01h indicates a bit collision in the 1st bit 08h indicates a bit collision in the 8th bit These bits shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit CollPosNotValid is set to logic 0. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 36 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2 Page 1: Communication 9.2.2.1 PageReg Selects the register page. Table 47. PageReg register (address 10h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePage Select 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 48. Description of PageReg bits Bit Symbol Description 7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to logic 1. In this case it specifies the register page (which is A5 and A4 of the register address). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 37 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b 7 6 5 4 3 2 1 0 MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 50. Description of ModeReg bits Bit Symbol Description 7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB first and the CRCResultMSB and the CRCResultLSB in the CRCResultReg register are bit reversed. Note: During RF communication this bit is ignored. 6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before the receiver is activated and F0h is added as a Sync-byte for transmission. This bit is only valid for 106 kbit during NFCIP-1 data exchange protocol. In all other modes it shall be set to logic 0. 5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for NFCIP-1 can only be started, if an RF field is generated. 4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field is detected in Target mode for NFCIP-1 or in Card Communication mode. 3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN pin is active low. Note: The internal envelope signal is coded active low. Note: Changing this bit will generate a SiginActIRq event. 2 ModeDetOff Set to logic 1, the internal mode detector is switched off. Note: The mode detector is only active during the AutoColl command. 1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command CalCRC. Note: During any communication, the preset values is selected automatically according to the definition in the bits RxMode and TxMode. Value Description 00 0000 01 6363 10 A671 11 FFFF PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 38 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TxCRCEn TxSpeed InvMod TxMix TxFraming Access Rights r/w dy dy dy r/w r/w dy dy Table 52. Description of TxModeReg bits Bit Symbol Description 7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data transmission. Note: This bit shall only be set to logic 0 at 106 kbit. 6 to 4 TxSpeed Defines the bit rate while data transmission. Value Description 000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to the bit coding of Active Communication mode 424 kbit (Ecma 340). 3 InvMod Set to logic 1, the modulation for transmitting data is inverted. 2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder (see Section 12.6 “S2C interface support”). 1 to 0 TxFraming Defines the framing used for data transmission. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive communication mode 212 and 424 kbit 11 ISO/IEC 14443B PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 39 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming Access Rights r/w dy dy dy r/w r/w dy dy Table 54. Description of RxModeReg bits Bit Symbol Description 7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception. Note: This bit shall only be set to logic 0 at 106 kbit. 6 to 4 RxSpeed Defines the bit rate while data transmission. The PN512’s analog part handles only transfer speeds up to 424 kbit internally, the digital UART handles the higher transfer speeds as well. Value Description 000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to the bit coding of Active Communication mode 424 kbit (Ecma 340). 3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits received) will be ignored. The receiver will remain active. For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non valid datastream. 2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame. Set to logic 1, it is possible to receive more than one data frame. Having set this bit, the receive and transceive commands will not terminate automatically. In this case the multiple receiving can only be deactivated by writing any command (except the Receive command) to the CommandReg register or by clearing the bit by the host controller. At the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the ErrorReg register. The behaviour for version 1.0 is described in Section 21 “Errata sheet” on page 109. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 40 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. 1 to 0 RxFraming Defines the expected framing for data reception. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive Communication mode 212 and 424 kbit 11 ISO/IEC 14443B Table 54. Description of RxModeReg bits Bit Symbol Description Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 InvTx2RF On InvTx1RF On InvTx2RF Off InvTx1RF Off Tx2CW CheckRF Tx2RF En Tx1RF En Access Rights r/w r/w r/w r/w r/w w r/w r/w Table 56. Description of TxControlReg bits Bit Symbol Description 7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is enabled. 6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is enabled. 5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is disabled. 4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is disabled. 3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz energy carrier. Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy carrier. 2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF field is detected. Only valid when using in combination with bit Tx2RFEn or Tx1RFEn 1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier modulated by the transmission data. 0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier modulated by the transmission data. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 41 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 AutoRF OFF Force100 ASK Auto WakeUp 0 CAOn InitialRF On Tx2RFAut oEn Tx1RFAuto En Access Rights r/w r/w r/w RFU r/w r/w r/w r/w Table 58. Description of TxAutoReg bits Bit Symbol Description 7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last data bit has been transmitted as defined in the NFCIP-1. 6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation independent of the setting in register ModGsPReg. 5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by the RF level detector. 4 - Reserved for future use. 3 CAOn Set to logic 1, the collision avoidance is activated and internally the value n is set in accordance to the NFCIP-1 Standard. 2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit InitialRFOn is cleared automatically, if the RF is switched on. Note: The driver, which should be switched on, has to be enabled by bit Tx2RFAutoEn or bit Tx1RFAutoEn. 1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field is switched off according to the time TADT. If the bits InitialRFOn and Tx2RFAutoEn are set to logic 1, Tx2 is switched on if no external RF field is detected during the time TIDT. Note: The times TADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092). 0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field is switched off according to the time TADT. If the bit InitialRFOn and Tx1RFAutoEn are set to logic 1, Tx1 is switched on if no external RF field is detected during the time TIDT. Note: The times TADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 42 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.7 TxSelReg Selects the sources for the analog part. Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b 7 6 5 4 3 2 1 0 0 0 DriverSel SigOutSel Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 60. Description of TxSelReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 DriverSel Selects the input of driver Tx1 and Tx2. Value Description 00 Tristate Note: In soft power down the drivers are only in Tristate mode if DriverSel is set to Tristate mode. 01 Modulation signal (envelope) from the internal coder 10 Modulation signal (envelope) from SIGIN 11 HIGH Note: The HIGH level depends on the setting of InvTx1RFOn/ InvTx1RFOff and InvTx2RFOn/InvTx2RFOff. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 43 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 3 to 0 SigOutSel Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. 0100 Modulation signal (envelope) from the internal coder 0101 Serial data stream to be transmitted 0110 Output signal of the receiver circuit (card modulation signal regenerated and delayed). This signal is used as data output signal for SAM interface connection using 3 lines. Note: To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. Note: Do not use this setting in MIFARE mode. Manchester coding as data collisions will not be transmitted on the SIGOUT line. 0111 Serial data stream received. Note: Do not use this setting in MIFARE mode. Miller coding parameters as the bit length can vary. 1000-1011 FeliCa Sam modulation 1000 RX* 1001 TX 1010 Demodulator comparator output 1011 RFU Note: * To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. 1100-1111 MIFARE Sam modulation 1100 RX* with RF carrier 1101 TX with RF carrier 1110 RX with RF carrier un-filtered 1111 RX envelope un-filtered Note: *To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. Table 60. Description of TxSelReg bits …continued Bit Symbol Description PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 44 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.8 RxSelReg Selects internal receiver settings. 9.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b 7 6 5 4 3 2 1 0 UartSel RxWait Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 62. Description of RxSelReg bits Bit Symbol Description 7 to 6 UartSel Selects the input of the contactless UART Value Description 00 Constant Low 01 Envelope signal at SIGIN 10 Modulation signal from the internal analog part 11 Modulation signal from SIGIN pin. Only valid for transfer speeds above 424 kbit 5 to 0 RxWait After data transmission, the activation of the receiver is delayed for RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX is ignored. This parameter is ignored by the Receive command. All other commands (e.g. Transceive, Autocoll, MFAuthent) use this parameter. Depending on the mode of the PN512, the counter starts different. In Passive Communication mode the counter starts with the last modulation pulse of the transmitted data stream. In Active Communication mode the counter starts immediately after the external RF field is switched on. Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b 7 6 5 4 3 2 1 0 MinLevel 0 CollLevel Access Rights r/w r/w r/w r/w RFU r/w r/w r/w Table 64. Description of RxThresholdReg bits Bit Symbol Description 7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. 3 - Reserved for future use. 2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 45 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.10 DemodReg Defines demodulator settings. Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b 7 6 5 4 3 2 1 0 AddIQ FixIQ TPrescal Even TauRcv TauSync Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 66. Description of DemodReg bits Bit Symbol Description 7 to 6 AddIQ Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings. Value Description 00 Select the stronger channel 01 Select the stronger and freeze the selected during communication 10 combines the I and Q channel 11 Reserved 5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to I channel. If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to Q channel. NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ set to X0 is rewired. 4 TPrescalE ven If set to logic 0 the following formula is used to calculate fTimer of the prescaler: fTimer = 13.56 MHz / (2 * TPreScaler + 1). If set to logic 1 the following formula is used to calculate fTimer of the prescaler: fTimer = 13.56 MHz / (2 * TPreScaler + 2). (Default TPrescalEven is logic 0) The behaviour for the version 1.0 is described in Section 21 “Errata sheet” on page 109. 3 to 2 TauRcv Changes the time constant of the internal during data reception. Note: If set to 00, the PLL is frozen during data reception. 1 to 0 TauSync Changes the time constant of the internal PLL during burst. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 46 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 FelSyncLen DataLenMin Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 68. Description of FelNFC1Reg bits Bit Symbol Description 7 to 6 FelSyncLen Defines the length of the Sync bytes. Value Sync- bytes in hex 00 B2 4D 01 00 B2 4D 10 00 00 B2 4D 11 00 00 00 B2 4D 5 to 0 DataLenMin These bits define the minimum length of the accepted packet length: DataLenMin * 4  data packet length This parameter is ignored at 106 kbit if the bit DetectSync in register ModeReg is set to logic 0. If a received data packet is shorter than the defined DataLenMin value, the data packet will be ignored. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 47 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WaitForSelected ShortTimeSlot DataLenMax Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 70. Description of FelNFC2Reg bits Bit Symbol Description 7 WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1. A valid command has been received after performing a valid Select procedure according ISO/IEC 14443A. 2. A valid command has been received after performing a valid Polling procedure according to the FeliCa specification. Note: If this bit is set, no active communication is possible. Note: Setting this bit reduces the host controller interaction in case of a communication to another device in the same RF field during Passive Communication mode. 6 ShortTimeSlot Defines the time slot length for Passive Communication mode at 424 kbit. Set to logic 1 a short time slot is used (half of the timeslot at 212 kbit). Set to logic 0 a long timeslot is used (equal to the timeslot for 212 kbit). 5 to 0 DataLenMax These bits define the maximum length of the accepted packet length: DataLenMax * 4  data packet length Note: If set to logic 0 the maximum data length is 256 bytes. This parameter is ignored at 106 kbit if the bit DetectSync in register ModeReg is set to logic 0. If a received packet is larger than the defined DataLenMax value, the packet will be ignored. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 48 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b 7 6 5 4 3 2 1 0 SensMiller TauMiller MFHalted TxWait Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 72. Description of MifNFCReg bits Bit Symbol Description 7 to 5 SensMiller These bits define the sensitivity of the Miller decoder. 4 to 3 TauMiller These bits define the time constant of the Miller decoder. 2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in Card Operation mode at 106 kbit. This bit is either set by the host controller or by the internal state machine and indicates that only the code 52h is accepted as a request command. This bit is cleared automatically by a RF reset. 1 to 0 TxWait These bits define the minimum response time between receive and transmit in number of data bits + 7 data bits. The shortest possible minimum response time is 7 data bits. (TxWait=0). The minimum response time can be increased by the number of bits defined in TxWait. The longest minimum response time is 10 data bits (TxWait = 3). If a transmission of a frame is started before the minimum response time is over, the PN512 waits before transmitting the data until the minimum response time is over. If a transmission of a frame is started after the minimum response time is over, the frame is started immediately if the data bit synchronization is correct. (adjustable with TxBitPhase). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 49 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 0 FastFilt MF_SO Delay MF_SO Parity Disable LargeBW PLL Manual HPCF HPFC Access Rights RFU r/w r/w r/w r/w r/w r/w r/w Table 74. Description of ManualRCVReg bits Bit Symbol Description 7 - Reserved for future use. 6 FastFilt MF_SO If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is set to Fast mode. Note: This bit should only set to logic 1, if Millerpulses of less than 400 ns Pulse length are expected. At 106 kBaud the typical value is 3 us. 5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that in SAM mode the Signal at SIGIN must be 128/fc faster compared to the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the RF-Field. Note: This delay shall only be activated for setting bits SigOutSel to (1110b) or (1111b) in register TxSelReg. 4 Parity Disable If this bit is set to logic 1, the generation of the Parity bit for transmission and the Parity-Check for receiving is switched off. The received Parity bit is handled like a data bit. 3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock recovery is extended. 2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are adapted automatically to the receiving mode. Set to logic 1, values of HPCF are valid. 1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the internal receiver chain 00 For signals with frequency spectrum down to 106 kHz. 01 For signals with frequency spectrum down to 212 kHz. 10 For signals with frequency spectrum down to 424 kHz. 11 For signals with frequency spectrum down to 848 kHz PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 50 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.15 TypeBReg 9.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 RxSOF Req RxEOF Req 0 EOFSO FWidth NoTxSOF NoTxEOF TxEGT Access Rights r/w r/w RFU r/w r/w r/w r/w r/w Table 76. Description of TypeBReg bits Bit Symbol Description 7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting without SOF is ignored. If this bit is cleared, a datastream with and without SOF is accepted. The SOF will be removed and not written into the FIFO. 6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending without EOF will generate a Protocol-Error. If this bit is cleared, a datastream with and without EOF is accepted. The EOF will be removed and not written into the FIFO. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 5 - Reserved for future use. 4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF and EOF will have the maximum length defined in ISO/IEC 14443B. If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and EOF will have the minimum length defined in ISO/IEC 14443B. If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in SOF low = (11etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in an incorrect system behavior in respect to ISO specification. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed. 2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed. 1 to 0 TxEGT These bits define the length of the EGT. Value Description 00 0 bit 01 1 bit 10 2 bits 11 3 bits PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 51 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b 7 6 5 4 3 2 1 0 BR_T0 BR_T1 Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 78. Description of SerialSpeedReg bits Bit Symbol Description 7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”. 3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 52 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3 Page 2: Configuration 9.2.3.1 PageReg Selects the register page. 9.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Note: The CRC is split into two 8-bit register. Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is not changed. Table 79. PageReg register (address 20h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePageSelect 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 80. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case, it specifies the register page (which is A5 and A4of the register address). Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 CRCResultMSB Access Rights r r r r r r r r Table 82. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of the CRCResultReg register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 CRCResultLSB Access Rights r r r r r r r r Table 84. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 53 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.3 GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b 7 6 5 4 3 2 1 0 CWGsNOff ModGsNOff Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 86. Description of GsNOffReg bits Bit Symbol Description 7 to 4 CWGsNOff The value of this register defines the conductance of the output N-driver during times of no modulation. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched off. Otherwise the bit value CWGsNOn of register GsNOnReg is used. Note: This value is used for LoadModulation. 3 to 0 ModGsNOff The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched off. Otherwise the bit value ModGsNOn of register GsNOnReg is used Note: This value is used for LoadModulation. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 54 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.4 ModWidthReg Controls the modulation width settings. 9.2.3.5 TxBitPhaseReg Adjust the bitphase at 106 kbit during transmission. Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b 7 6 5 4 3 2 1 0 ModWidth Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 88. Description of ModWidthReg bits Bit Symbol Description 7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active and Passive Communication mode as multiples of the carrier frequency (ModWidth + 1/fc). The maximum value is half the bit period. Acting as a target in Passive Communication mode at 106 kbit or in Card Operating mode for ISO/IEC 14443A/MIFARE these bits are used to change the duty cycle of the subcarrier frequency. The resulting number of carrier periods are calculated according to the following formulas: LOW value: #clocksLOW = (ModWidth modulo 8) + 1. HIGH value: #clocksHIGH = 16-#clocksLOW. Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b 7 6 5 4 3 2 1 0 RcvClkChange TxBitPhase Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 90. Description of TxBitPhaseReg bits Bit Symbol Description 7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF field. 6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock cycles, which are added to the waiting period before transmitting data in all communication modes. TXBitPhase is used to adjust the TX bit synchronization during passive NFCIP-1 communication mode at 106 kbit and in ISO/IEC 14443A/MIFARE card mode. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 55 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b 7 6 5 4 3 2 1 0 RFLevelAmp RxGain RFLevel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 92. Description of RFCfgReg bits Bit Symbol Description 7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier. 6 to 4 RxGain This register defines the receivers signal voltage gain factor: Value Description 000 18 dB 001 23 dB 010 18 dB 011 23 dB 100 33 dB 101 38 dB 110 43 dB 111 48 dB 3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see Section 12.3 “RF level detector”. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 56 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. 9.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b 7 6 5 4 3 2 1 0 CWGsNOn ModGsNOn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 94. Description of GsNOnReg bits Bit Symbol Description 7 to 4 CWGsNOn The value of this register defines the conductance of the output N-driver during times of no modulation. This may be used to regulate the output power and subsequently current consumption and operating distance. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or TX2 are switched on. Otherwise the value of the bits CWGsNOff of register GsNOffReg is used. 3 to 0 ModGsNOn The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or Tx2 are switched on. Otherwise the value of the bits ModsNOff of register GsNOffReg is used. Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 CWGsP Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 96. Description of CWGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 CWGsP The value of this register defines the conductance of the output P-driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 57 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. [1] If Force100ASK is set to logic 1, the value of ModGsP has no effect. 9.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Note: The Prescaler value is split into two 8-bit registers Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 ModGsP Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 98. Description of ModGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 ModGsP[1] The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TAuto TGated TAutoRestart TPrescaler_Hi Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 100. Description of TModeReg bits Bit Symbol Description 7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission in all communication modes at all speeds or when bit InitialRFOn is set to logic 1 and the RF field is switched on. In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is not set. In all other modes, the timer stops after the 4th bit if the bit RxMultiple the register RxModeReg is not set. If RxMultiple is set to logic 1, the timer never stops. In this case the timer can be stopped by setting the bit TStopNow in register ControlReg to 1. Set to logic 0 indicates, that the timer is not influenced by the protocol. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 58 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6 to 5 TGated The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits. This bit does not influence the gating signal. Value Description 00 Non gated mode 01 Gated by SIGIN 10 Gated by AUX1 11 Gated by A3 4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from TReloadValue, instead of counting down to zero. Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set to logic 1. 3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler. The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 0: fTimer = 13.56 MHz/(2*TPreScaler+1). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) (Default TPrescalEven is logic 0) The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1: fTimer = 13.56 MHz/(2*TPreScaler+2). For detailed description see Section 15 “Timer unit”. For the behaviour within version 1.0, see Section 21 “Errata sheet” on page 109. Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TPrescaler_Lo Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 102. Description of TPrescalerReg bits Bit Symbol Description 7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler. The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 0: fTimer = 13.56 MHz/(2*TPreScaler+1). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1: fTimer = 13.56 MHz/(2*TPreScaler+2). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) For detailed description see Section 15 “Timer unit”. Table 100. Description of TModeReg bits …continued Bit Symbol Description PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 59 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TReloadVal_Hi Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 104. Description of the higher TReloadReg bits Bit Symbol Description 7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TReloadVal_Lo Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 106. Description of lower TReloadReg bits Bit Symbol Description 7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 60 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. 9.2.4 Page 3: Test 9.2.4.1 PageReg Selects the register page. Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TCounterVal_Hi Access Rights r r r r r r r r Table 108. Description of the higher TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits. Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TCounterVal_Lo Access Rights r r r r r r r r Table 110. Description of lower TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits. Table 111. PageReg register (address 30h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePageSelect 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 61 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 112. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case, it specifies the register page (which is A5 and A4 of the register address). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 62 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.2 TestSel1Reg General test signal configuration. 9.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 - - SAMClockSel SAMClkD1 TstBusBitSel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 114. Description of TestSel1Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock Value Description 00 GND- Sam Clock switched off 01 clock derived by the internal oscillator 10 internal UART clock 11 clock derived by the RF field 3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1. Note: Only possible if the 8bit parallel interface is not used. 2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT. Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TstBusFlip PRBS9 PRBS15 TestBusSel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 116. Description of TestSel2Reg bits Bit Symbol Description 7 TstBusFlip If set to logic 1, the testbus is mapped to the parallel port by the following order: D4, D3, D2, D6, D5, D0, D1. See Section 20 “Testsignals”. 6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150. Note: All relevant registers to transmit data have to be configured before entering PRBS9 mode. Note: The data transmission of the defined sequence is started by the send command. 5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150. Note: All relevant registers to transmit data have to be configured before entering PRBS15 mode. Note: The data transmission of the defined sequence is started by the send command. 4 to 0 TestBusSel Selects the testbus. See Section 20 “Testsignals” PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 63 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. 9.2.4.5 TestPinValueReg Defines the values for the 7-bit parallel port when it is used as I/O. Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 RS232LineEn TestPinEn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 118. Description of TestPinEnReg bits Bit Symbol Description 7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are disabled. 6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface. Example: Setting bit 0 to 1 enables D0 Setting bit 5 to 1 enables D5 Note: Only valid if one of serial interfaces is used. If the SPI interface is used only D0 to D4 can be used. If the serial UART interface is used and RS232LineEn is set to logic 1 only D0 to D4 can be used. Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UseIO TestPinValue Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 120. Description of TestPinValueReg bits Bit Symbol Description 7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel port in case one of the serial interfaces is used. The input/output behavior is defined by TestPinEn in register TestPinEnReg. The value for the output behavior is defined in the bits TestPinVal. Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O. 6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each output has to be enabled by the TestPinEn bits in register TestPinEnReg. Note: Reading the register indicates the actual status of the pins D6 - D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the register TestPinValueReg is read back. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 64 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.6 TestBusReg Shows the status of the internal testbus. 9.2.4.7 AutoTestReg Controls the digital selftest. 9.2.4.8 VersionReg Shows the version. Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TestBus Access Rights r r r r r r r r Table 122. Description of TestBusReg bits Bit Symbol Description 7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the register TestSel2Reg. See Section 20 “Testsignals”. Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b 7 6 5 4 3 2 1 0 0 AmpRcv EOFSO FAdjust - SelfTest Access Rights RFT r/w RFU RFU r/w r/w r/w r/w Table 124. Description of bits Bit Symbol Description 7 - Reserved for production tests. 6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is performed non-linear. This increases the operating distance in communication modes at 106 kbit. Note: Due to the non linearity the effect of the bits MinLevel and CollLevel in the register RxThreshholdReg are as well non linear. 5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the Maximum length of SOF and EOF according to ISO/IEC14443B If set to logic 0 and the EOFSOFwidth is set to 0 will result in the Minimum length of SOF and EOF according to ISO/IEC14443B If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in SOF low = (11 etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 4 - Reserved for future use. 3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest command in the command register. The selftest is enabled by 1001. Note: For default operation the selftest has to be disabled by 0000. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 65 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 Version Access Rights r r r r r r r r Table 126. Description of VersionReg bits Bit Symbol Description 7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are described within Section 21 “Errata sheet” on page 109. 82h indicates PN512 version 2.0, which covers also the industrial version. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 66 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 AnalogSelAux1 AnalogSelAux2 Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 128. Description of AnalogTestReg bits Bit Symbol Description 7 to 4 3 to 0 AnalogSelAux1 AnalogSelAux2 Controls the AUX pin. Note: All test signals are described in Section 20 “Testsignals”. Value Description 0000 Tristate 0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2) Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0010 Testsignal Corr1 Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0011 Testsignal Corr2 Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0100 Testsignal MinLevel Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0101 Testsignal ADC channel I Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0110 Testsignal ADC channel Q Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0111 Testsignal ADC channel I combined with Q Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1000 Testsignal for production test Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1001 SAM clock (13.56 MHz) 1010 HIGH 1011 LOW 1100 TxActive At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High during Preamble, Sync, Data and CRC. 1101 RxActive At 106 kbit: High during databit, Parity and CRC. At 212 and 424 kbit: High during data and CRC. 1110 Subcarrier detected 106 kbit: not applicable 212 and 424 kbit: High during last part of Preamble, Sync data and CRC 1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 67 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. 9.2.4.11 TestDAC2Reg Defines the testvalue for TestDAC2. 9.2.4.12 TestADCReg Shows the actual value of ADC I and Q channel. Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb 7 6 5 4 3 2 1 0 0 0 TestDAC1 Access Rights RFT RFU r/w r/w r/w r/w r/w r/w Table 130. Description of TestDAC1Reg bits Bit Symbol Description 7 - Reserved for production tests. 6 - Reserved for future use. 5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be switched to AUX1 by setting AnalogSelAux1 to 0001 in register AnalogTestReg. Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb 7 6 5 4 3 2 1 0 0 0 TestDAC2 Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 132. Description ofTestDAC2Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be switched to AUX2 by setting AnalogSelAux2 to 0001 in register AnalogTestReg. Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 ADC_I ADC_Q Access Rights Table 134. Description of TestADCReg bits Bit Symbol Description 7 to 4 ADC_I Shows the actual value of ADC I channel. 3 to 0 ADC_Q Shows the actual value of ADC Q channel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 68 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.13 RFTReg 10. Digital interfaces 10.1 Automatic microcontroller interface detection The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART interfaces. The PN512 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The PN512 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections. Table 141 shows the different connection configurations. Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 136. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 138. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 140. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 69 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] only available in HVQFN 40. Table 141. Connection protocol for detecting different interface types Pin Interface type UART (input) SPI (output) I2C-bus (I/O) SDA RX NSS SDA I2C 0 0 1 EA 0 1 EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5 Table 142. Connection scheme for detecting the different interface types PN512 Parallel Interface Type Serial Interface Types Separated Read/Write Strobe Common Read/Write Strobe Pin Dedicated Address Bus Multiplexed Address Bus Dedicated Address Bus Multiplexed Address Bus UART SPI I2C ALE 1 ALE 1 AS RX NSS SDA A5[1] A5 0 A5 0 0 0 0 A4[1] A4 0 A4 0 0 0 0 A3[1] A3 0 A3 0 0 0 0 A2[1] A2 1 A2 1 0 0 0 A1 A1 1 A1 1 0 0 1 A0 A0 1 A0 0 0 1 EA NRD[1] NRD NRD NDS NDS 1 1 1 NWR[1] NWR NWR RD/NWR RD/NWR 1 1 1 NCS[1] NCS NCS NCS NCS NCS NCS NCS D7 D7 D7 D7 D7 TX MISO SCL D6 D6 D6 D6 D6 MX MOSI ADR_0 D5 D5 AD5 D5 AD5 DTRQ SCK ADR_1 D4 D4 AD4 D4 AD4 - - ADR_2 D3 D3 AD3 D3 AD3 - - ADR_3 D2 D2 AD2 D2 AD2 - - ADR_4 D1 D1 AD1 D1 AD1 - - ADR_5 D0 D0 AD0 D0 AD0 - - ADR_6 Remark: Overview on the pin behavior Pin behavior Input Output In/Out PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 70 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds up to 10 Mbit/s. When communicating with a host, the PN512 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication. An interface compatible with SPI enables high-speed serial communication between the PN512 and a microcontroller. The implemented interface is in accordance with the SPI standard. The timing specification is given in Section 26.1 on page 117. The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line is used to send data from the PN512 to the master. Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is provided by the PN512 on the falling clock edge and is stable during the rising clock edge. 10.2.1 SPI read data Reading data using SPI requires the byte order shown in Table 143 to be used. It is possible to read out up to n-data bytes. The first byte sent defines both the mode and the address. [1] X = Do not care. Remark: The MSB must be sent first. 10.2.2 SPI write data To write data to the PN512 using SPI requires the byte order shown in Table 144. It is possible to write up to n data bytes by only sending one address byte. Fig 13. SPI connection to host 001aan220 PN512 SCK SCK MOSI MOSI MISO MISO NSS NSS Table 143. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 address 1 address 2 ... address n 00 MISO X[1] data 0 data 1 ... data n  1 data n PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 71 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The first send byte defines both the mode and the address byte. [1] X = Do not care. Remark: The MSB must be sent first. 10.2.3 SPI address byte The address byte has to meet the following format. The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is set to logic 1. To write data to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define the address and the LSB is set to logic 0. 10.3 UART interface 10.3.1 Connection to a host Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s RS232LineEn bit. 10.3.2 Selectable UART transfer speeds The internal UART interface is compatible with an RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new transfer speed to the SerialSpeedReg register. Bits BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the SerialSpeedReg register. The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different transfer speeds and the relevant register settings are given in Table 11. Table 144. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 data 0 data 1 ... data n  1 data n MISO X[1] X[1] X[1] ... X[1] X[1] Table 145. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write address 0 Fig 14. UART connection to microcontrollers 001aan221 PN512 RX RX TX TX DTRQ DTRQ MX MX PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 72 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds. The selectable transfer speeds shown in Table 11 are calculated according to the following equations: If BR_T0[2:0] = 0: (1) If BR_T0[2:0] > 0: (2) Remark: Transfer speeds above 1228.8 kBd are not supported. 10.3.3 UART framing Table 146. BR_T0 and BR_T1 settings BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 BR_T0 factor 1 1 2 4 8 16 32 64 BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 147. Selectable UART transfer speeds Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1] Decimal Hexadecimal 7.2 250 FAh 0.25 9.6 235 EBh 0.32 14.4 218 DAh 0.25 19.2 203 CBh 0.32 38.4 171 ABh 0.32 57.6 154 9Ah 0.25 115.2 122 7Ah 0.25 128 116 74h 0.06 230.4 90 5Ah 0.25 460.8 58 3Ah 0.25 921.6 28 1Ch 1.45 1228.8 21 15h 0.32 transfer speed 27.12  106 BR_T0 + 1 = ------------------------------- transfer speed 27.12  106 BR_T1 + 33 2BR_T0 – 1 ----------------------------------- -----------------------------------           = Table 148. UART framing Bit Length Value Start 1-bit 0 Data 8 bits data Stop 1-bit 1 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 73 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the flow shown in Table 149 must be used. The first byte sent defines both the mode and the address. Write data: To write data to the PN512 using the UART interface, the structure shown in Table 150 must be used. The first byte sent defines both the mode and the address. Table 149. Read data byte order Pin Byte 0 Byte 1 RX (pin 24) address - TX (pin 31) - data 0 (1) Reserved. Fig 15. UART read data timing diagram 001aak588 SA ADDRESS RX TX MX DTRQ A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO DATA R/W Table 150. Write data byte order Pin Byte 0 Byte 1 RX (pin 24) address 0 data 0 TX (pin 31) - address 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 74 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The address byte has to meet the following format: (1) Reserved. Fig 16. UART write data timing diagram 001aak589 SA ADDRESS RX TX MX DTRQ A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO SA A0 A1 A2 A3 A4 A5 (1) SO DATA ADDRESS R/W R/W PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 75 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 151. 10.4 I2C Bus Interface An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I2C-bus interface is implemented according to NXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. The interface can only act in Slave mode. Therefore the PN512 does not implement clock generation or access arbitration. The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The PN512 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode. If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA as defined in the I2C-bus interface specification. See Table 171 on page 117 for timing requirements. Table 151. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write reserved address Fig 17. I2C-bus interface 001aan222 PN512 SDA SCL I2C EA ADR_[5:0] PULL-UP NETWORK CONFIGURATION WIRING PULL-UP NETWORK MICROCONTROLLER PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 76 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. 10.4.2 START and STOP conditions To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. • A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH. • A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH. The I2C-bus master always generates the START and STOP conditions. The bus is busy after the START condition. The bus is free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. The START (S) and repeated START (Sr) conditions are functionally identical. Therefore, S is used as a generic term to represent both the START (S) and repeated START (Sr) conditions. 10.4.3 Byte format Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first; see Figure 22. The number of transmitted bytes during one data transfer is unrestricted but must meet the read/write cycle format. Fig 18. Bit transfer on the I2C-bus mbc621 data line stable; data valid change of data allowed SDA SCL Fig 19. START and STOP conditions mbc622 SDA SCL P STOP condition SDA SCL S START condition PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 77 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer or a repeated START (Sr) condition to start a new transfer. A master-receiver indicates the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter releases the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. Fig 20. Acknowledge on the I2C-bus mbc602 S START condition 1 2 8 9 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master Fig 21. Data transfer on the I2C-bus msc608 Sr or P SDA Sr P SCL STOP or repeated START condition S or Sr START or repeated START condition 1 2 3 - 8 9 ACK 9 ACK 1 2 7 8 MSB acknowledgement signal from slave byte complete, interrupt within slave clock line held LOW while interrupts are serviced acknowledgement signal from receiver PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 78 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.5 7-Bit addressing During the I2C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus specification for a complete list of reserved addresses. The I2C-bus address specification is dependent on the definition of pin EA. Immediately after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus address according to pin EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I2C-bus devices. If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins according to Table 141 on page 69. ADR_6 is always set to logic 0. In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration. Depending on the external wiring, the I2C-bus address pins can be used for test signal outputs. 10.4.6 Register write access To write data from the host controller using the I2C-bus to a specific register in the PN512 the following frame format must be used. • The first byte of a frame indicates the device address according to the I2C-bus rules. • The second byte indicates the register address followed by up to n-data bytes. In one frame all data bytes are written to the same register address. This enables fast FIFO buffer access. The Read/Write (R/W) bit is set to logic 0. Fig 22. First byte following the START procedure slave address 001aak591 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W MSB LSB PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 79 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.7 Register read access To read out data from a specific register address in the PN512, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I2C-bus rules • The second byte indicates the register address. No data bytes are added • The Read/Write bit is 0 After the write access, read access can start. The host sends the device address of the PN512. In response, the PN512 sends the content of the read access register. In one frame all data bytes can be read from the same register address. This enables fast FIFO buffer access or register polling. The Read/Write (R/W) bit is set to logic 1. Fig 23. Register read and write access 001aak592 S A 0 0 I2C-BUS SLAVE ADDRESS [A7:A0] JOINER REGISTER ADDRESS [A5:A0] write cycle 0 (W) A DATA [7:0] [0:n] [0:n] [0:n] A P S A 0 0 I2C-BUS SLAVE ADDRESS [A7:A0] JOINER REGISTER ADDRESS [A5:A0] read cycle optional, if the previous access was on the same register address 0 (W) A P P S S start condition P stop condition A acknowledge A not acknowledge W write cycle R read cycle A I2C-BUS SLAVE ADDRESS [A7:A0] sent by master sent by slave DATA [7:0] 1 (R) A DATA [7:0] A PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 80 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates of up to 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system. 10.4.9 High-speed transfer To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to I2C-bus operation. • The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger on the SDA and SCL inputs and different timing constants when compared to F/S mode • The output buffers of the device in HS mode incorporate slope control of the falling edges of the SDA and SCL signals with different fall times compared to F/S mode 10.4.10 Serial data transfer format in HS mode The HS mode serial data transfer format meets the Standard mode I2C-bus specification. HS mode can only start after all of the following conditions (all of which are in F/S mode): 1. START condition (S) 2. 8-bit master code (00001XXXb) 3. Not-acknowledge bit (A) When HS mode starts, the active master sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from the selected PN512. Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions (Sr). Fig 24. I2C-bus HS mode protocol switch F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode 001aak749 A A DATA A/A (n-bytes + A) S MASTER CODE Sr SLAVE ADDRESS R/W HS mode continues Sr SLAVE ADDRESS P PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 81 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 25. I2C-bus HS mode protocol frame msc618 8-bit master code 0000 1xxx A tH t1 S F/S mode HS mode If P then F/S mode If Sr (dotted lines) then HS mode 1 6 7 8 9 1 6 7 8 9 1 2 to 5 2 to 5 2 to 5 6 7 8 9 SDA high SCL high SDA high SCL high tH tFS Sr Sr P 7-bit SLA R/W A n + (8-bit data + A/A) = Master current source pull-up = Resistor pull-up PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 82 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.11 Switching between F/S mode and HS mode After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting. The following actions are taken: 1. Adapt the SDA and SCL input filters according to the spike suppression requirement in HS mode. 2. Adapt the slope control of the SDA output stages. It is possible for system configurations that do not have other I2C-bus devices involved in the communication to switch to HS mode permanently. This is implemented by setting Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code is not required to be sent. This is not defined in the specification and must only be used when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines must be avoided because of the reduced spike suppression. 10.4.12 PN512 at lower speed modes PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus system. The device stays in F/S mode and communicates at F/S mode speeds because a master code is not transmitted in this configuration. 11. 8-bit parallel interface The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola compatible modes. 11.1 Overview of supported host controller interfaces The PN512 supports direct interfacing to various -Controllers. The following table shows the parallel interface types supported by the PN512. Table 152. Supported interface types Supported interface types Bus Separated Address and Data Bus Multiplexed Address and Data Bus Separated Read and Write Strobes (INTEL compatible) control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7 Multiplexed Read and Write Strobe (Motorola compatible) control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 83 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 11.2 Separated Read/Write strobe For timing requirements refer to Section 26.2 “8-bit parallel interface timing”. 11.3 Common Read/Write strobe For timing requirements refer to Section 26.2 “8-bit parallel interface timing” Fig 26. Connection to host controller with separated Read/Write strobes 001aan223 PN512 NCS A0...A3[A5*] D0...D7 A0 A1 A2 A3 A4* A5* address bus (A0...A3[A5*]) ALE NRD NWR ADDRESS DECODER data bus (D0...D7) high not data strobe (NRD) not write (NWR) address bus remark: *depending on the package type. multiplexed address/data AD0...AD7) PN512 NCS D0...D7 ALE NRD NWR ADDRESS DECODER low low high high high low address latch enable (ALE) not read strobe (NRD) not write (NWR) non multiplexed address Fig 27. Connection to host controller with common Read/Write strobes 001aan224 PN512 NCS A0...A3[A5*] D0...D7 A0 A1 A2 A3 A4* A5* address bus (A0...A3[A5*]) ALE NRD NWR ADDRESS DECODER Data bus (D0...D7) high not data strobe (NDS) read not write (RD/NWR) address bus remark: *depending on the package type. multiplexed address/data AD0...AD7) PN512 NCS D0...D7 ALE NRD NWR ADDRESS DECODER low low high high low low address strobe (AS) not data strobe (NDS) read not write (RD/NWR) non multiplexed address PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 84 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12. Analog interface and contactless UART 12.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In addition, it handles error detection such as parity and CRC, based on the various supported contactless communication protocols. Remark: The size and tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance. 12.2 TX driver The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering; see Section 15 on page 96. The signal on pins TX1 and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on page 40. The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning. The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds. [1] X = Do not care. Table 153. Register and bit settings controlling the signal on pin TX1 Bit Tx1RFEn Bit Force 100ASK Bit InvTx1RFOn Bit InvTx1RFOff Envelope Pin TX1 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is switched off 1 0 0 X[1] 0 RF pMod nMod 100 % ASK: pin TX1 pulled to logic 0, independent of the InvTx1RFOff bit 1 RF pCW nCW 0 1 X[1] 0 RF pMod nMod 1 RF pCW nCW 1 1 X[1] 0 0 pMod nMod 1 RF_n pCW nCW PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 85 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] X = Do not care. The following abbreviations have been used in Table 153 and Table 154: • RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 • RF_n: inverted 13.56 MHz clock • GSPMos: conductance, configuration of the PMOS array • GSNMos: conductance, configuration of the NMOS array • pCW: PMOS conductance value for continuous wave defined by the CWGsPReg register • pMod: PMOS conductance value for modulation defined by the ModGsPReg register • nCW: NMOS conductance value for continuous wave defined by the GsNReg register’s CWGsN[3:0] bits • nMod: NMOS conductance value for modulation defined by the GsNReg register’s ModGsN[3:0] bits • X = do not care. Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and GsNReg registers are used for both drivers. 12.3 RF level detector The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF collision avoidance). Furthermore the RF level detector can be used to wake up the PN512 and to generate an interrupt. Table 154. Register and bit settings controlling the signal on pin TX2 Bit Tx1RFEn Bit Force 100ASK Bit Tx2CW Bit InvTx2RFOn Bit InvTx2RFOff Envelope Pin TX2 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is switched off 1 0 0 0 X[1] 0 RF pMod nMod - 1 RF pCW nCW 1 X[1] 0 RF_n pMod nMod 1 RF_n pCW nCW 1 0 X[1] X[1] RF pCW nCW conductance always CW for the Tx2CW bit 1 X[1] X[1] RF_n pCW nCW 1 0 0 X[1] 0 0 pMod nMod 100 % ASK: pin TX2 pulled to logic 0 (independent of the InvTx2RFOn/In vTx2RFOff bits) 1 RF pCW nCW 1 X[1] 0 0 pMod nMod 1 RF_n pCW nCW 1 0 X[1] X[1] RF pCW nCW 1 X[1] X[1] RF_n pCW nCW PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 86 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register RFCfgReg. The sensitivity itself depends on the antenna configuration and tuning. Possible sensitivity levels at the RX pin are listed in the Table 154. To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp in register RFCfgReg to 1. Remark: During soft Power-down mode the RF level detector amplifier is automatically switched off to ensure that the power consumption is less than 10 A at 3 V. Remark: With typical antennas lower sensitivity levels can provoke misleading results because of intrinsic noise in the environment. Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings. 12.4 Data mode detector The Data mode detector gives the possibility to detect received signals according to the ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and convenient way for further data processing. The Data mode detector can only be activated by the AutoColl command. The mode detector resets, when no external RF field is detected by the RF level detector. The Data mode detector could be switched off during the AutoColl command by setting bit ModeDetOff in register ModeReg to 1. Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) V~Rx [Vpp] RFLevel ~2 1111 ~1.4 1110 ~0.99 1101 ~0.69 1100 ~0.49 1011 ~0.35 1010 ~0.24 1001 ~0.17 1000 ~0.12 0111 ~0.083 0110 ~0.058 0101 ~0.041 0100 ~0.029 0011 ~0.020 0010 ~0.014 0001 ~0.010 0000 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 87 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 28. Data mode detector 001aan225 HOST INTERFACES RECEIVER I/Q DEMODULATOR REGISTERS REGISTERSETTING FOR THE DETECTED MODE DATA MODE DETECTOR PN512 RX NFC @ 106 kbit/s NFC @ 212 kbit/s NFC @ 424 kbit/s PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 88 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.5 Serial data switch Two main blocks are implemented in the PN512. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above 424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional external circuit to generate transfer speeds above 424 kbit (including 106, 212 and 424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S2C interface in the card SAM mode to emulate a card functionality with the PN512 and a secure IC. A secure IC can be the SmartMX smart card controller IC. This topology allows the analog block of the PN512 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. Figure 29 shows the serial data switch for TX1 and TX2. 12.6 S2C interface support The S2C provides the possibility to directly connect a secure IC to the PN512 in order act as a contactless smart card IC via the PN512. The interfacing signals can be routed to the pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC provided by NXP Semiconductors. The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and SIGOUT pads. Figure 31 outlines possible ways of communications via the PN512 to the secure IC. Fig 29. Serial data switch for TX1 and TX2 001aak593 INTERNAL CODER INVERT IF InvMod = 1 DriverSel[1:0] 00 01 10 11 3-state to driver TX1 and TX2 0 = impedance = modulated 1 = impedance = CW 1 INVERT IF PolMFin = 0 MFIN envelope PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 89 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and performs the communication on the SIGOUT line. To enable the Secure Access module mode the clock has to be derived by the internal oscillator of the PN512, see bits SAMClockSel in register TestSel1Reg. Configured in Contactless Card mode the secure IC can act as contactless smart card IC via the PN512. In this mode the signal on the SIGOUT line is provided by the external RF field of the external reader/writer. To enable the Contactless Card mode the clock derived by the external RF field has to be used. The configuration of the S2C interface differs for the FeliCa and MIFARE scheme as outlined in the following chapters. Fig 30. Communication flows using the S2C interface 001aan226 CONTACTLESS UART SERIAL SIGNAL SWITCH FIFO AND STATE MACHINE SPI, I2C, SERIAL UART HOST CONTROLLER PN512 SECURE CORE IC SIGOUT SIGIN 2. contactless card mode 1. secure access module (SAM) mode PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 90 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.6.1 Signal shape for Felica S2C interface support The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or. To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first. The time delay for that digital filtering is in the range of one bit length. The demodulated signal changes only at a positive edge of the clock. The register TxSelReg controls the setting at SIGOUT. The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver. The modulation is done according to the register settings of the antenna drivers. The clock is switched to AUX1 or AUX2 (see AnalogSelAux). Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock output if a serial interface is used. The HIGH level at D0 is the same as PVDD. Note: The signal on the antenna is shown in principle only. In reality the waveform is sinusoidal. Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode Fig 32. Signal shape for SIGIN in SAM mode 001aan227 clock signal on SIGIN signal on antenna 001aan228 clock demodulated signal signal on SIGOUT PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 91 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode. The register TxSelReg controls the setting at SIGOUT. Note: The clock settings for the Secure Access mode and the Contactless Card mode differ, refer to the description of the bits SAMClockSel in register TestSel1Reg. The signal at SIGIN is a digital Manchester coded signal according to the requirements of the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure IC. Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode 001aan229 1 0 bit value RF signal on antenna signal on SIGOUT 0 1 0 0 1 001aan230 0 1 0 1 0 0 1 bit value signal on antenna signal on SIGIN PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 92 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.7 Hardware support for FeliCa and NFC polling 12.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot, or if required an interrupt is generated at the end of the last timeslot. 2. The receiver can be configured in a way to receive continuously. In this mode it can receive any number of packets. The receiver is ready to receive the next packet directly after the last packet has been received. This mode is active by setting the bit RxMultiple in register RxModeReg to 1 and has to be stopped by software. 3. The internal UART adds one byte to the end of every received packet, before it is transferred into the FIFO-buffer. This byte indicates if the received byte packet is correct (see register ErrReg). The first byte of each packet contains the length byte of the packet. 4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a length of 64 bytes. This means three packets can be stored in the FIFO at the same time. If more than three packets are expected, the host controller has to empty the FIFO, before the FIFO is filled completely. In case of a FIFO-overflow data is lost (See bit BufferOvfl in register ErrorReg). 12.7.2 Polling sequence functionality for target 1. The host controller has to configure the PN512 with the correct polling response parameters for the polling command. 2. To activate the automatic polling in Target mode, the AutoColl Command has to be activated. 3. The PN512 receives the polling command send out by an initiator and answers with the polling response. The timeslot is selected automatically (The timeslot itself is randomly generated, but in the range 0 to TSN, which is defined by the Polling command). The PN512 compares the system code, stored in byte 17 and 18 of the Config Command with the system code received by the polling command of an initiator. If the system code is equal, the PN512 answers according to the configured polling response. The system code FF (hex) acts as a wildcard for the system code bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex). If the system code does not match no answer is sent back by the PN512. If a valid command is received by the PN512, which is not a Polling command, no answer is sent back and the command AutoColl is stopped. The received packet is stored in the FIFO. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 93 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length. This register is six bit long. Each bit represents a length of four bytes. DataLenMax in register FelNFC2Reg defines the maximum length of the accepted package. This register is six bit long. Each bit represents a length of four bytes. If set to logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not transferred to the FIFO and receiving is kept active. Example 1: • DataLenMin = 4 – The length shall be greater or equal 16. • DataLenMax = 5 – The length shall be smaller than 20. Valid area: 16, 17, 18, 19 Example 2: • DataLenMin = 9 – The length shall be greater or equal 36. • DataLenMax = 0 – The length shall be smaller than 256. Valid area: 36 to 255 12.7.4 CRC coprocessor The following CRC coprocessor parameters can be configured: • The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting • The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1 • The CRCResultReg register indicates the result of the CRC calculation. This register is split into two 8-bit registers representing the higher and lower bytes. • The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB first. Table 156. CRC coprocessor parameters Parameter Value CRC register length 16-bit CRC CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the ModeReg register’s CRCPreset[1:0] bits PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 94 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 13. FIFO buffer An 8  64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream between the host and the PN512’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account. 13.1 Accessing the FIFO buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register. Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register. When the microcontroller starts a command, the PN512 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses. 13.2 Controlling the FIFO buffer The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer accessible allowing the FIFO buffer to be filled with another 64 bytes. 13.3 FIFO buffer status information The host can get the following FIFO buffer status information: • Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0] • FIFO buffer almost full warning: Status1Reg register’s HiAlert bit • FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit • FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit. The PN512 can generate an interrupt signal when: • ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register’s LoAlert bit changes to logic 1. • ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register’s HiAlert bit changes to logic 1. If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to Equation 3: HiAlert = 64 – FIFOLength  WaterLevel (3) PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 95 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4: (4) 14. Interrupt request system The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 14.1 Interrupt sources overview Table 157 shows the available interrupt bits, the corresponding source and the condition for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by the timer unit which is set when the timer decrements from 1 to 0. The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by CRCReady bit = 1. The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on page 101). The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. LoAlert = FIFOLength  WaterLevel Table 157. Interrupt sources Interrupt flag Interrupt source Trigger action TimerIRq timer unit the timer counts from 1 to 0 TxIRq transmitter a transmitted data stream ends CRCIRq CRC coprocessor all data from the FIFO buffer has been processed RxIRq receiver a received data stream ends IdleIRq ComIrqReg register command execution finishes HiAlertIRq FIFO buffer the FIFO buffer is almost full LoAlertIRq FIFO buffer the FIFO buffer is almost empty ErrIRq contactless UART an error is detected PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 96 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 15. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • Time-out counter • Watch-dog counter • Stop watch • Programmable one-shot • Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A time-out during data reception does not influence the reception process automatically). Furthermore, several timer related bits are set and these bits can be used to generate an interrupt. Timer The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer consists of two stages: 1 prescaler and 1 counter. The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between 0 and 4095 in register TModeReg and TPrescalerReg. The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the register TReloadReg. The current value of the timer is indicated by the register TCounterValReg. If the counter reaches 0 an interrupt will be generated automatically indicated by setting the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on the configuration the timer will stop at 0 or restart with the value from register TReloadReg. The status of the timer is indicated by bit TRunning in register Status1Reg. The timer can be manually started by TStartNow in register ControlReg or manually stopped by TStopNow in register ControlReg. Furthermore the timer can be activated automatically by setting the bit TAuto in the register TModeReg to fulfill dedicated protocol requirements automatically. The time delay of a timer stage is the reload value +1. The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz Maximum time: TPrescaler = 4095,TReloadVal = 65535 => (2*4095 +2)*65536/13.56 MHz = 39.59 s Example: PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 97 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution To indicate 25 us it is required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us. The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 98 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 16. Power reduction modes 16.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level. 16.2 Soft power-down mode Soft Power-down mode is entered immediately after the CommandReg register’s PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input buffers are not separated from the input pins and keep their functionality. The digital output pins do not change their state. During soft power-down, all register values, the FIFO buffer content and the configuration keep their current contents. After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited. Remark: If the internal oscillator is used, you must take into account that it is supplied by pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock cycles can be detected by the internal logic. It is recommended for the serial UART, to first send the value 55h to the PN512. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the PN512 answers to the last read command with the register content of address 0. This indicates that the PN512 is ready. 16.3 Transmitter power-down mode The Transmitter Power-down mode switches off the internal antenna drivers thereby, turning off the RF field. Transmitter power-down mode is entered by setting either the TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 99 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 17. Oscillator circuitry The clock applied to the PN512 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, special care must be taken with the clock duty cycle and clock jitter and the clock quality must be verified. 18. Reset and oscillator start-up time 18.1 Reset timing requirements The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns. 18.2 Oscillator start-up time If the PN512 has been set to a Power-down mode or is powered by a VDDX supply, the start-up time for the PN512 depends on the oscillator used and is shown in Figure 36. The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator start-up time is defined by the crystal. The time (td) is the internal delay time of the PN512 when the clock signal is stable before the PN512 can be addressed. The delay time is calculated by: (5) The time (tosc) is the sum of td and tstartup. Fig 35. Quartz crystal connection 001aan231 PN512 27.12 MHz OSCOUT OSCIN td 1024 27 s = -------------- = 37.74 s PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 100 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19. PN512 command set The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.1 General description The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.2 General behavior • Each command that needs a data bit stream (or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the Transceive command. Using this command, transmission is started with the BitFramingReg register’s StartSend bit. • Each command that needs a certain number of arguments, starts processing only when it has received the correct number of arguments from the FIFO buffer. • The FIFO buffer is not automatically cleared when commands start. This makes it possible to write command arguments and/or the data bytes to the FIFO buffer and then start the command. • Each command can be interrupted by the host writing a new command code to the CommandReg register, for example, the Idle command. Fig 36. Oscillator start-up time 001aak596 tstartup td tosc t device activation oscillator clock stable clock ready PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 101 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3 PN512 command overview 19.3.1 PN512 command descriptions 19.3.1.1 Idle Places the PN512 in Idle mode. The Idle command also terminates itself. 19.3.1.2 Config command To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for these transactions has to be stored internally. All the following data have to be written to the FIFO in this order: SENS_RES (2 bytes); in order byte 0, byte 1 NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h and the check byte is calculated automatically. SEL_RES (1 Byte) polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes system code) NFCID3 (1 byte) In total 25 bytes are transferred into an internal buffer. The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2 bytes and the one NFCID3 byte which are listed above. To read out this configuration the command Config with an empty FIFO-buffer has to be started. In this case the 25 bytes are transferred from the internal buffer to the FIFO. Table 158. Command overview Command Command code Action Idle 0000 no action, cancels current command execution Configure 0001 Configures the PN512 for FeliCa, MIFARE and NFCIP-1 communication Generate RandomID 0010 generates a 10-byte random ID number CalcCRC 0011 activates the CRC coprocessor or performs a self test Transmit 0100 transmits data from the FIFO buffer NoCmdChange 0111 no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit Receive 1000 activates the receiver circuits Transceive 1100 transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and MIFARE anticollision (Card Operation mode only) MFAuthent 1110 performs the MIFARE standard authentication as a reader SoftReset 1111 resets the PN512 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 102 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The PN512 has to be configured after each power up, before using the automatic Anticollision/Polling function (AutoColl command). During a hard power down (reset pin) this configuration remains unchanged. This command terminates automatically when finished and the active command is idle. 19.3.1.3 Generate RandomID This command generates a 10-byte random number which is initially stored in the internal buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the PN512 returns to Idle mode. 19.3.1.4 CalcCRC The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped when the FIFO buffer is empty during the data stream. The next byte written to the FIFO buffer is added to the calculation. The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The value is loaded in to the CRC coprocessor when the command starts. This command must be terminated by writing a command to the CommandReg register, such as, the Idle command. If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self Test mode. Starting the CalcCRC command initiates a digital self test. The result of the self test is written to the FIFO buffer. 19.3.1.5 Transmit The FIFO buffer content is immediately transmitted after starting this command. Before transmitting the FIFO buffer content, all relevant registers must be set for data transmission. This command automatically terminates when the FIFO buffer is empty. It can be terminated by another command written to the CommandReg register. 19.3.1.6 NoCmdChange This command does not influence any running command in the CommandReg register. It can be used to manipulate any bit except the CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit. 19.3.1.7 Receive The PN512 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command. This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 103 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3.1.8 Transceive This command continuously repeats the transmission of data from the FIFO buffer and the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream. Each transmit process must be started by setting the BitFramingReg register’s StartSend bit to logic 1. This command must be cleared by writing any command to the CommandReg register. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive command never leaves the receive state because this state cannot be cancelled automatically. 19.3.1.9 AutoColl This command automatically handles the MIFARE activation and the FeliCa polling in the Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0 for correct operation. During this command also the mode detector is active if not deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode detector detects a mode, all the mode dependent registers are set according to the received data. In case of no external RF field the command resets the internal state machine and returns to the initial state but it will not be terminated. When the command terminates the transceive command gets active. During protocol processing the IRQ bits are not supported. Only the last received frame will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the protocol. During ISO/IEC 14443A activation the enable bits are defined by the command AutoColl. The changes cannot be observed at the register TXModeReg and RXModeReg. After the Transceive command is active, the value of the register bit is relevant. The FIFO will also receive the two CRC check bytes of the last command even if they already checked and correct, if the state machine (Anticollision and Select routine) has to not been executed and 106 kbit is detected. During Felica activation the register bit is always relevant and is not overruled by the command settings. This command can be cleared by software by writing any other command to the CommandReg register, e.g. the idle command. Writing the same content again to the CommandReg register resets the state machine. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 104 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution NFCIP-1 106 kbps Passive Communication mode: The MIFARE anticollision is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit TargetActivated in the Status2Reg register is set to logic 1. NFCIP-1 212/424 kbps Passive Communication mode: The FeliCa polling command is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ. The bit TargetActivated in the Status2Reg register is set to logic 1. NFCIP-1 106/212/424 kbps Active Communication mode: This command is changing the automatically to the command Transceive. The FIFO contains the ATR REQ The bit TargetActivated in the Status2Reg register is set to logic 0. For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC is added to the FIFO. Fig 37. Autocoll Command NFCIP-1 106 kB aud ISO14443-3 NPCIP-1 > 106 kB aud FELICA IDLE MODEO MODE detection RXF raming MFHalted = 1 HALT AC nAC SELECT nSELECT HLTA AC polling, polling response next frame received next frame received REQA, WUPA READY ACTIVE WUPA SELECT SELECT READY* ACTIVE* TRANSCEIVE wait for transmit next frame received J N HLTA REQA, WUPA, AC, nAC, SELECT, nSELECT, error REQA, AC, nAC, SELECT, nSELECT, HLTA REQA, WUPA, nAC, nSELECT, HLTA, error REQA, WUPA, nAC, nSELECT, HLTA, error REQA, WUPA, AC, SELECT, nSELECT, error 00 10 AC aaa-001826 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 105 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution MIFARE (Card Operation mode): The MIFARE anticollision is finished and the command has automatically changed to transceive. The FIFO contains the first command after the Select. The bit TargetActivated in the Status2Reg register is set to logic 1. Felica (Card Operation mode): The FeliCa polling command is finished and the command has automatically changed to transceive. The FIFO contains the first command followed after the Poling by the FeliCa protocol. The bit TargetActivated in the Status2Reg register is set to logic 1. 19.3.1.10 MFAuthent This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the FIFO buffer before the command can be activated: • Authentication command code (60h, 61h) • Block address • Sector key byte 0 • Sector key byte 1 • Sector key byte 2 • Sector key byte 3 • Sector key byte 4 • Sector key byte 5 • Card serial number byte 0 • Card serial number byte 1 • Card serial number byte 2 • Card serial number byte 3 In total 12 bytes are written to the FIFO. Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set. This command automatically terminates when the MIFARE card is authenticated and the Status2Reg register’s MFCrypto1On bit is set to logic 1. This command does not terminate automatically if the card does not answer, so the timer must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the TimerIRq bit can be used as the termination criteria. During authentication processing, the RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of the MFAuthent command, either after processing the protocol or writing Idle to the CommandReg register. If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 106 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3.1.11 SoftReset This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished. Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to 9.6 kBd. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 107 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 20. Testsignals 20.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. 4. Write 00h to the FIFO. 5. Start the Selftest with the CalcCRC Command. 6. The Selftest will be performed. 7. When the Selftest is finished, the FIFO contains the following bytes: Version 1.0 has a different Selftest answer, explained in Section 21. Correct answer for VersionReg equal to 82h: 00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh, 9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h, 49h, 7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h, 21h, A9h, 86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh, 95h, 3Bh, 2Fh 20.2 Testbus The testbus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the PN512. The testbus allows to route internal signals to the digital interface. The testbus signals are selected by accessing TestBusSel in register TestSel2Reg. Table 159. Testsignal routing (TestSel2Reg = 07h) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal sdata scoll svalid sover RCV_reset RFon, filtered Envelope Table 160. Description of Testsignals Pins Testsignal Description D6 sdata shows the actual received data stream. D5 scoll shows if in the actual bit a collision has been detected (106 kbit only) D4 svalid shows if sdata and scoll are valid D3 sover shows that the receiver has detected a stop condition (ISO/IEC 14443A/ MIFARE mode only). D2 RCV_reset shows if the receiver is reset D1 RFon, filtered shows the value of the internal RF level detector D0 Envelope shows the output of the internal coder PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 108 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 20.3 Testsignals at pin AUX Table 161. Testsignal routing (TestSel2Reg = 0Dh) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf Table 162. Description of Testsignals Pins Testsignal Description D6 clkstable shows if the oscillator delivers a stable signal. D5 clk27/8 shows the output signal of the oscillator divided by 8 D4 clk27rf/8 shows the clk27rf signal divided by 8 D3 clkrf13/4 shows the clk13rf divided by 4. D2 clk27 shows the output signal of the oscillator D1 clk27rf shows the RF clock multiplied by 2. D0 clk13rf shows the RF clock of 13.56 MHz Table 163. Testsignal routing (TestSel2Reg = 19h) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal - TRunning - - - - - Table 164. Description of Testsignals Pins Testsignal Description D6 - - D5 TRunning TRunning stops 1 clockcycle after TimerIRQ is raised D4 - - D3 - - D2 - - D1 - - D0 - - Table 165. Testsignals description SelAux Description for Aux1 / Aux2 0000 Tristate 0001 DAC: register TestDAC 1/2 0010 DAC: testsignal corr1 0011 DAC: testsignal corr2 0100 DAC: testsignal MinLevel 0101 DAC: ADC_I 0110 DAC: ADC_Q 0111 DAC: testsignal ADC_I combined with ADC_Q 1000 Testsignal for production test 1001 SAM clock 1010 High 1011 low 1100 TxActive PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 109 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Note: The DAC has a current output, it is recommended to use a 1 k pull-down resistance at pins AUX1/AUX2. 20.4 PRBS Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the transmission of the defined datastream the command send has to be activated. The preamble/Sync byte/start bit/parity bit are generated automatically depending on the selected mode. Note: All relevant register to transmit data have to be configured before entering PRBS mode according ITU-TO150. 21. Errata sheet This data sheet is describing the functionality for version 2.0 and the industrial version. This chapter lists all differences from version 1.0 to version 2.0: The value of the version in Section 9.2.4.8 is set to80h. The behaviour ‘RFU’ for the register is undefined. The answer to the Selftest (see Section 20.1) for version 1.0 (VersionReg equal to 80h): 00h, AAh, E3h, 29h, 0Ch, 10h, 29zhh, 6Bh, 76h, 8Dh, AFh, 4Bh, A2h, DAh, 76h, 99h C7h, 5Eh, 24h, 69h, D2h, BAh, FAh, BCh 3Eh, DAh, 96h, B5h, F5h, 94h, B0h, 3Ah 4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh 38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh 4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh 38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh FBh, F4h, 19h, 94h, 82h, 5Ah, 72h, 9Dh BAh, 0Dh, 1Fh, 17h, 56h, 22h, B9h, 08h Only the default setting for the prescaler (see Section 15 “Timer unit” on page 96): t = ((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula fTimer = 13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in Table 100 “Description of TModeReg bits” on page 57 and TPrescalerLo in Table 101 “TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b” on page 58. As there is no option for the prescaler available, also the TPrescalEven is not available Section 9.2.2.10 on page 45. This bit is set to ‘RFU’. 1101 RxActive 1110 Subcarrier detected 1111 TstBusBit Table 165. Testsignals description SelAux Description for Aux1 / Aux2 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 110 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Especially when using time slot protocols, it is needed that the error flag is copied into the status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4 on page 39) within version 1.0 the protocol error flag is not included in the status information for the frame. In addition the CRCOk is copied instead of the CRCErr. This can be a problem in frames without length information e.g. ISO/IEC 14443-B. The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits, as such the configuration within Section 9.2.2.15 “TypeBReg” on page 50 bit 4 for RxEOFReq does not exist. In addition the IC only has the possibility to select the minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section 9.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only setting minimum and maximum length according ISO/IEC 14443-B, see Section 9.2.2.15 “TypeBReg” on page 50, bit 4. 22. Application design-in information The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN512. The antenna tuning and RF part matching is described in the application note “NFC Transmission Module Antenna and RF Design Guide”. Fig 38. Typical circuit diagram AVDD TVDD RX VMID supply TX1 TVSS TX2 DVSS DVDD DVDD PVDD SVDD AVSS IRQ NRSTPD R1 R2 L0 C0 C0 C2 C1 CRX RQ C1 RQ C2 L0 Cvmid 001aan232 27.12 MHz OSCIN OSCOUT HOST CONTROLLER interface PN512 antenna Lant PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 111 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 23. Limiting values 24. Recommended operating conditions Table 166. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDA analog supply voltage 0.5 +4.0 V VDDD digital supply voltage 0.5 +4.0 V VDD(PVDD) PVDD supply voltage 0.5 +4.0 V VDD(TVDD) TVDD supply voltage 0.5 +4.0 V VDD(SVDD) SVDD supply voltage 0.5 +4.0 V VI input voltage all input pins except pins SIGIN and RX VSS(PVSS)  0.5 VDD(PVDD) + 0.5 V pin MFIN VSS(PVSS)  0.5 VDD(SVDD) + 0.5 V Ptot total power dissipation per package; and VDDD in shortcut mode - 200 mW Tj junction temperature - 125 C VESD electrostatic discharge voltage HBM; 1500 , 100 pF; JESD22-A114-B - 2000 V MM; 0.75 H, 200 pF; JESD22-A114-A - 200 V Charged device model; JESD22-C101-A on all pins - 200 V on all pins except SVDD in TFBGA64 package - 500 V Industrial version: VESD electrostatic discharge voltage HBM; 1500 , 100 pF; JESD22-A114-B - 2000 V MM; 0.75 H, 200 pF; JESD22-A114-A - 200 V Charged device model; AEC-Q100-011 on all pins - 200 V on all pins except SVDD - 500 V Table 167. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V VDDD digital supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V VDD(TVDD) TVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 112 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] Supply voltages below 3 V reduce the performance (the achievable operating distance). [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. 25. Thermal characteristics 26. Characteristics VDD(PVDD) PVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [3] 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 - +85 C Industrial version: Tamb ambient temperature HVQFN32 40 - +90 C Table 167. Operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit Table 168. Thermal characteristics Symbol Parameter Conditions Package Typ Unit Rthj-a Thermal resistance from junction to ambient In still air with exposed pad soldered on a 4 layer Jedec PCB In still air HVQFN32 40 K/W HVQFN40 35 K/W TFBGA64 K/W Table 169. Characteristics Symbol Parameter Conditions Min Typ Max Unit Input characteristics Pins A0, A1 and NRSTPD ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD)- - V VIL LOW-level input voltage - - 0.3VDD(PVDD) V Pin SIGIN ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(SVDD)- - V VIL LOW-level input voltage - - 0.3VDD(SVDD) V Pin ALE ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD)- - V VIL LOW-level input voltage - - 0.3VDD(PVDD) V Pin RX[1] Vi input voltage 1 - VDDA +1 V Ci input capacitance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.5 V (DC) offset - 10 - pF PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 113 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Ri input resistance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.5 V (DC) offset - 350 -  Input voltage range; see Figure 39 Vi(p-p)(min) minimum peak-to-peak input voltage Manchester encoded; VDDA = 3 V - 100 - mV Vi(p-p)(max) maximum peak-to-peak input voltage Manchester encoded; VDDA = 3 V - 4 - V Input sensitivity; see Figure 39 Vmod modulation voltage minimum Manchester encoded; VDDA = 3 V; RxGain[2:0] = 111b (48 dB) - 5 - mV Pin OSCIN ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDDA - - V VIL LOW-level input voltage - - 0.3VDDA V Ci input capacitance VDDA = 2.8 V; DC = 0.65 V; AC = 1 V (p-p) - 2 - pF Input/output characteristics pins D1, D2, D3, D4, D5, D6 and D7 ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD)- - V VIL LOW-level input voltage - - 0.3VDD(PVDD) V VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)  0.4 - VDD(PVDD) V VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOH HIGH-level output current VDD(PVDD) = 3 V - - 4 mA IOL LOW-level output current VDD(PVDD) = 3 V - - 4 mA Output characteristics Pin SIGOUT VOH HIGH-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VDD(SVDD)  0.4 - VDD(SVDD) V VOL LOW-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDD(SVDD) = 3 V - - 4 mA IOH HIGH-level output current VDD(SVDD) = 3 V - - 4 mA Pin IRQ VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)  0.4 - VDD(PVDD) V VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDD(PVDD) = 3 V - - 4 mA IOH HIGH-level output current VDD(PVDD) = 3 V - - 4 mA Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 114 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Pins AUX1 and AUX2 VOH HIGH-level output voltage VDDD = 3 V; IO = 4 mA VDDD  0.4 - VDDD V VOL LOW-level output voltage VDDD = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDDD= 3 V - - 4 mA IOH HIGH-level output current VDDD= 3 V - - 4 mA Pins TX1 and TX2 VOL LOW-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh - - 0.15 V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh - - 0.4 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh - - 0.24 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh - - 0.64 V VOH HIGH-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.15 - - V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.4 - - V VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.24 - - V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.64 - - V Industrial version: VOL LOW-level output voltage VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh - - 0.18 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh - - 0.44 V VOH HIGH-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.18 - - V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.44 - - V Output resistance for TX1/TX2, Industrial Version: ROP,01H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 01h 123 180 261  Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 115 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution ROP,02H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 02h 61 90 131  ROP,04H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 04h 30 46 68  ROP,08H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 08h 15 23 35  ROP,10H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 10h 7.5 12 19  ROP,20H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 20h 4.2 6 9  ROP,3FH High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 3Fh 2 3 5  RON,10H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 10h 30 46 68  RON,20H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 20h 15 23 35  RON,40H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 40h 7.5 12 19  RON,80H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 80h 4.2 6 9  RON,F0H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = F0h 2 3 5  Current consumption Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [2]- - 5 A soft power-down; RF level detector on [2]- - 10 A IDD(PVDD) PVDD supply current pin PVDD [3]- - 40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [4][5][6]- 60 100 mA IDD(SVDD) SVDD supply current pin SVDD [7]- - 4 mA IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA= 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register’s RcvOff bit = 1 - 3 5 mA Industrial version: IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9,5 mA Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 116 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD. [2] Ipd is the total current for all supplies. [3] IDD(PVDD) depends on the overall load at the digital pins. [4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [5] During typical circuit operation, the overall current is below 100 mA. [6] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz. [7] IDD(SVDD) depends on the load at pin MFOUT. Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [2]- - 15 A soft power-down; RF level detector on [2]- - 30 A Clock frequency fclk clock frequency - 27.12 - MHz clk clock duty cycle 40 50 60 % tjit jitter time RMS - - 10 ps Crystal oscillator VOH HIGH-level output voltage pin OSCOUT - 1.1 - V VOL LOW-level output voltage pin OSCOUT - 0.2 - V Ci input capacitance pin OSCOUT - 2 - pF pin OSCIN - 2 - pF Typical input requirements fxtal crystal frequency - 27.12 - MHz ESR equivalent series resistance - - 100  CL load capacitance - 10 - pF Pxtal crystal power dissipation - 50 100 W Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 117 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 26.1 Timing characteristics Fig 39. Pin RX input voltage range 001aak012 VMID 0 V Vmod Vi(p-p)(max) Vi(p-p)(min) 13.56 MHz carrier Table 170. SPI timing characteristics Symbol Parameter Conditions Min Typ Max Unit tWL pulse width LOW line SCK 50 - - ns tWH pulse width HIGH line SCK 50 - - ns th(SCKH-D) SCK HIGH to data input hold time SCK to changing MOSI 25 - - ns tsu(D-SCKH) data input to SCK HIGH set-up time changing MOSI to SCK 25 - - ns th(SCKL-Q) SCK LOW to data output hold time SCK to changing MISO - - 25 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns Table 171. I2C-bus timing in Fast mode Symbol Parameter Conditions Fast mode High-speed mode Unit Min Max Min Max fSCL SCL clock frequency 0 400 0 3400 kHz tHD;STA hold time (repeated) START condition after this period, the first clock pulse is generated 600 - 160 - ns tSU;STA set-up time for a repeated START condition 600 - 160 - ns tSU;STO set-up time for STOP condition 600 - 160 - ns tLOW LOW period of the SCL clock 1300 - 160 - ns tHIGH HIGH period of the SCL clock 600 - 60 - ns tHD;DAT data hold time 0 900 0 70 ns PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 118 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution tSU;DAT data set-up time 100 - 10 - ns tr rise time SCL signal 20 300 10 40 ns tf fall time SCL signal 20 300 10 40 ns tr rise time SDA and SCL signals 20 300 10 80 ns tf fall time SDA and SCL signals 20 300 10 80 ns tBUF bus free time between a STOP and START condition 1.3 - 1.3 - s Remark: The signal NSS must be LOW to be able to send several bytes in one data stream. To send more than one data stream NSS must be set HIGH between the data streams. Fig 40. Timing diagram for SPI Fig 41. Timing for Fast and Standard mode devices on the I2C-bus Table 171. I2C-bus timing in Fast mode …continued Symbol Parameter Conditions Fast mode High-speed mode Unit Min Max Min Max 001aaj634 tSCKL tSCKH tSCKL tDXSH tSHDX tDXSH tSLDX tSLNH MOSI SCK MISO MSB MSB LSB LSB NSS 001aaj635 SDA tf SCL tLOW tf tSP tr tHD;STA tHD;DAT tHD;STA tr tHIGH tSU;DAT S Sr P S tSU;STA tSU;STO tBUF PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 119 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 26.2 8-bit parallel interface timing 26.2.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Example: tAVLL = time for address valid to ALE low 26.2.2 AC operating specification 26.2.2.1 Bus timing for separated Read/Write strobe Table 172. AC symbols Designation Signal Designation Logic Level A address H HIGH D data L LOW W NWR or nWait Z high impedance R NRD or R/NW or nWrite X any level or data L ALE or AS V any valid signal or data C NCS N NSS S NDS or nDStrb and nAStrb, SCK Table 173. Timing specification for separated Read/Write strobe Symbol Parameter Min Max Unit tLHLL ALE pulse width 10 - ns tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 5 - ns tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 5 - ns tLLWL ALE low to NWR, NRD low 10 - ns tCLWL NCS low to NRD, NWR low 0 - ns tWHCH NRD, NWR high to NCS high 0 - ns tRLDV NRD low to DATA valid - 35 ns tRHDZ NRD high to DATA high impedance - 10 ns tDVWH DATA valid to NWR high 5 - ns tWHDX DATA hold after NWR high (Data Hold Time) 5 - ns tWLWH NRD, NWR pulse width 40 - ns tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 - ns tWHAX Separated Address Bus valid after NWR high (Hold Time) 5 - ns tWHWL period between sequenced read/write accesses 40 - ns PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 120 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A3 have to be connected as described in chapter Automatic host controller Interface Type Detection. 26.2.2.2 Bus timing for common Read/Write strobe Fig 42. Timing diagram for separated Read/Write strobe 001aan233 tLHLL tCLWL tLLWL tWHWL tWLWH tWHWL tWHDX tRHDZ tWLDV tRLDV tWHCH tWHAX tAVLL tLLAX tAVWL ALE NCS NWR NRD D0...D7 D0...D7 A0...A3 multiplexed addressbus A0...A3 SEPARATED ADDRESSBUS A0...A3 Table 174. Timing specification for common Read/Write strobe Symbol Parameter Min Max Unit tLHLL AS pulse width 10 - ns tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 5 - ns tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 5 - ns tLLSL AS low to NDS low 10 - ns tCLSL NCS low to NDS low 0 - ns tSHCH NDS high to NCS high 0 - ns tSLDV,R NDS low to DATA valid (for read cycle) - 35 ns tSHDZ NDS low to DATA high impedance (read cycle) - 10 ns tDVSH DATA valid to NDS high (for write cycle) 5 - ns tSHDX DATA hold after NDS high (write cycle, Hold Time) 5 - ns tSHRX R/NW hold after NDS high 5 - ns tSLSH NDS pulse width 40 - ns tAVSL Separated Address Bus valid to NDS low (Hold Time) 30 - ns tSHAX Separated Address Bus valid after NDS high (Set Up Time) 5 - ns PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 121 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A3 have to be connected as described in Automatic -Controller Interface Type Detection. Fig 43. Timing diagram for common Read/Write strobe SEPARATED ADDRESSBUS A0...A3 multiplexed addressbus A0...A3 ALE tLHLL tCLSL R/NW NDS D0...D7 D0...D7 A0...A3 NCS tSHCH tRVSL tSHRX tLLSL tSLSH tSHSL tAVLL tLLAX tSLDV, R tSLDV, W tSHDX tSHDZ tSHAX tAVSL tSHSL 001aan234 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 122 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 27. Package information The PN512 can be delivered in 3 different packages. Table 175. Package information Package Remarks HVQFN32 8-bit parallel interface not supported HVQFN40 Supports the 8-bit parallel interface TFBGA64 Ball grid array facilitating development of an PCI compliant device PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 123 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 28. Package outline Fig 44. Package outline package version (HVQFN32) 1 0.5 UNIT A1 b Eh e y 0.2 c OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 5.1 4.9 Dh 3.25 2.95 y1 5.1 4.9 3.25 2.95 e1 3.5 e2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT617-1 - - - MO-220 - - - 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT617-1 HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A(1) max. A A1 c detail X e y1 C y L Eh Dh e e1 b 9 16 32 25 24 17 8 1 X D E C B A e2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e C A C v M B w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 124 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 45. Package outline package version (HVQFN40) Outline References version European projection Issue date IEC JEDEC JEITA SOT618-1 MO-220 sot618-1_po 02-10-22 13-11-05 Unit mm max nom min 1.00 0.05 0.2 6.1 4.25 6.1 0.4 A(1) Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 A1 b 0.30 c D(1) Dh E(1) Eh 4.10 e e1 e2 L v w 0.05 y 0.05 y1 0.1 0.85 0.02 0.21 6.0 4.10 6.0 0.80 0.00 0.18 5.9 3.95 5.9 3.95 0.3 4.25 0.5 4.5 4.5 0.5 0.1 e e 1/2 e 1/2 e y terminal 1 index area A A1 c L Eh Dh b 11 20 40 31 30 10 21 1 D E terminal 1 index area 0 2.5 5 mm scale e1 C A C v B w y1 C C e2 X detail X B A PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 125 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 46. Package outline package version (TFBGA64) Outline References version European projection Issue date IEC JEDEC JEITA SOT1336-1 - - - sot1336-1_po 12-06-19 12-08-28 Unit mm max nom min 1.15 0.35 0.45 5.6 5.6 4.55 0.15 0.1 A Dimensions (mm are the original dimensions) TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls A1 A2 0.80 1.00 0.30 0.70 0.40 5.5 5.5 0.65 b D E e e1 4.55 0.90 0.25 0.65 0.35 5.4 5.4 e2 v w 0.08 y y1 0.1 SOT1336-1 C y1 C y 0 5 mm scale X A A2 A1 detail X ball A1 index area ball A1 index area A E D B e2 e A B C D E F G H 1 2 3 4 5 6 7 8 e1 e Ø v C A B Ø w C b 1/2 e 1/2 e PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 126 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 29. Abbreviations 30. Glossary Modulation index — Defined as the voltage ratio (Vmax  Vmin) / (Vmax + Vmin). Load modulation index — Defined as the voltage ratio for the card (Vmax  Vmin) / (Vmax + Vmin) measured at the card’s coil. Initiator — Generates RF field at 13.56 MHz and starts the NFCIP-1 communication. Target — Responds to command either using load modulation scheme (RF field generated by Initiator) or using modulation of self generated RF field (no RF field generated by initiator). 31. References [1] Application note — NFC Transmission Module Antenna and RF Design Guide Table 176. Abbreviations Acronym Description ADC Analog-to-Digital Converter ASK Amplitude Shift keying BPSK Binary Phase Shift Keying CRC Cyclic Redundancy Check CW Continuous Wave DAC Digital-to-Analog Converter EOF End of frame HBM Human Body Model I2C Inter-integrated Circuit LSB Least Significant Bit MISO Master In Slave Out MM Machine Model MOSI Master Out Slave In MSB Most Significant Bit NSS Not Slave Select PCB Printed-Circuit Board PLL Phase-Locked Loop PRBS Pseudo-Random Bit Sequence RX Receiver SOF Start Of Frame SPI Serial Peripheral Interface TX Transmitter UART Universal Asynchronous Receiver Transmitter PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 127 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 32. Revision history Table 177. Revision history Document ID Release date Data sheet status Change notice Supersedes PN512 v.4.5 20131217 Product data sheet - PN512 v.4.4 Modifications: • Typo corrected PN512 v.4.4 20130730 Product data sheet - PN512 v.4.3 Modifications: • Value added in Table 166 “Limiting values” • Change of descriptive title PN512 v.4.3 20130507 Product data sheet - PN512 v.4.2 Modifications: • New type PN5120A0ET/C2 added • Table 72 “Description of MifNFCReg bits”: description of TxWait updated • Table 153 “Register and bit settings controlling the signal on pin TX1” and Table 153 “Register and bit settings controlling the signal on pin TX1”: updated • Table 166 “Limiting values”: VESD values added PN512 v.4.2 20120828 Product data sheet - PN512 v.4.1 Modifications: • Table 123 “AutoTestReg register (address 36h); reset value: 40h, 01000000b”: description of bits 4 and 5 corrected PN512 v.4.1 20120821 Product data sheet - PN512 v.4.0 Modifications: • Table 124 “Description of bits”: description of bits 4 and 5 corrected PN512 v.4.0 20120712 Product data sheet - PN512 v.3.9 Modifications: • Section 33.4 “Licenses”: updated PN512 v.3.9 20120201 Product data sheet - PN512 v.3.8 Modifications: • Adding information on the different version in General description. • Adding Section 21 “Errata sheet” on page 109 for explanation of differences between 1.0 and 2.0. • Adding ordering information for version 1.0 and industrial version in Table 2 “Ordering information” on page 5 • Adding the limitations and characteristics for the industrial version, see Table 1 “Quick reference data” on page 4, Table 166 “Limiting values” on page 111, Table 1 “Quick reference data” on page 4 • Referring to the Section 21 “Errata sheet” on page 109 within the following sections: Section 9.2.2.4 “RxModeReg” on page 39, Section 9.2.2.10 “DemodReg” on page 45, Section 9.2.2.15 “TypeBReg” on page 50, Section 9.2.3.10 “TMode Register, TPrescaler Register” on page 57, Section 9.2.4.7 “AutoTestReg” on page 64, Section 9.2.4.8 “VersionReg” on page 64, Section 9.1.1 “Register bit behavior” on page 23, Section 15 “Timer unit” on page 96, Section 20 “Testsignals” on page 107; • Update of command ‘Mem’ to ‘Configure’ and ‘RFU’ to ‘Autocoll’ in Table 158 “Command overview” on page 101. • Change of ‘Mem’ to ‘Configure’ in ‘Mem’ in Section 19.3.1.2 “Config command” on page 101 • Adding Autocoll in Section 19.3.1.9 “AutoColl” on page 103 PN512 v.3.8 20111025 Product data sheet - PN512 v.3.7 Modifications: • Table 168 “Characteristics”: unit of Pxtal corrected 111310 June 2005 Objective data sheet - Modifications: • Initial version PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 128 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 33. Legal information 33.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 33.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 33.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 129 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 33.4 Licenses 33.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. MIFARE — is a trademark of NXP B.V. 34. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron Technology Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 130 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 35. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5 Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . .10 Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . 11 Table 5. Pin description TFBGA64 . . . . . . . . . . . . . . . . .12 Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer . . . . .14 Table 7. Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 8. FeliCa framing and coding . . . . . . . . . . . . . . . .16 Table 9. Start value for the CRC Polynomial: (00h), (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 10. Communication overview for Active communication mode . . . . . . . . . . . . . . . . . . . .18 Table 11. Communication overview for Passive communication mode . . . . . . . . . . . . . . . . . . . .19 Table 12. Framing and coding overview. . . . . . . . . . . . . .20 Table 13. MIFARE Card operation mode . . . . . . . . . . . . .20 Table 14. FeliCa Card operation mode . . . . . . . . . . . . . .21 Table 15. PN512 registers overview . . . . . . . . . . . . . . . .21 Table 16. Behavior of register bits and its designation. . .23 Table 17. PageReg register (address 00h); reset value: 00h, 0000000b . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 18. Description of PageReg bits . . . . . . . . . . . . . . .24 Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .24 Table 20. Description of CommandReg bits. . . . . . . . . . .24 Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . .25 Table 22. Description of CommIEnReg bits . . . . . . . . . . .25 Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .26 Table 24. Description of DivIEnReg bits . . . . . . . . . . . . . .26 Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b . . . . . . . . . . . . . . . . . . .27 Table 26. Description of CommIRqReg bits . . . . . . . . . . .27 Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb . . . . . . . . . . . . . . . . . .28 Table 28. Description of DivIRqReg bits . . . . . . . . . . . . .28 Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .29 Table 30. Description of ErrorReg bits . . . . . . . . . . . . . . .29 Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb . . . . . . . . . . . . . . . . . .30 Table 32. Description of Status1Reg bits . . . . . . . . . . . . .30 Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .31 Table 34. Description of Status2Reg bits . . . . . . . . . . . . .31 Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . .32 Table 36. Description of FIFODataReg bits . . . . . . . . . . .32 Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .32 Table 38. Description of FIFOLevelReg bits. . . . . . . . . . .32 Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .33 Table 40. Description of WaterLevelReg bits. . . . . . . . . . 33 Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 33 Table 42. Description of ControlReg bits . . . . . . . . . . . . 33 Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 34 Table 44. Description of BitFramingReg bits . . . . . . . . . . 34 Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb . . . . . . . . . . . . . . . . . 35 Table 46. Description of CollReg bits. . . . . . . . . . . . . . . . 35 Table 47. PageReg register (address 10h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 36 Table 48. Description of PageReg bits . . . . . . . . . . . . . . 36 Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 50. Description of ModeReg bits . . . . . . . . . . . . . . 37 Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 38 Table 52. Description of TxModeReg bits . . . . . . . . . . . . 38 Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 39 Table 54. Description of RxModeReg bits . . . . . . . . . . . . 39 Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 40 Table 56. Description of TxControlReg bits . . . . . . . . . . . 40 Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 41 Table 58. Description of TxAutoReg bits . . . . . . . . . . . . . 41 Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b. . . . . . . . . . . . . . . . . . . . . . . . 42 Table 60. Description of TxSelReg bits . . . . . . . . . . . . . . 42 Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b. . . . . . . . . . . . . . . . . . . . . . . . 44 Table 62. Description of RxSelReg bits . . . . . . . . . . . . . . 44 Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b . . . . . . . . . . . . . . 44 Table 64. Description of RxThresholdReg bits . . . . . . . . 44 Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b . . . . . . . . . . . . . . . . . . 45 Table 66. Description of DemodReg bits . . . . . . . . . . . . . 45 Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 46 Table 68. Description of FelNFC1Reg bits . . . . . . . . . . . 46 Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 47 Table 70. Description of FelNFC2Reg bits . . . . . . . . . . . 47 Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b. . . . . . . . . . . . . . . . . . . 48 Table 72. Description of MifNFCReg bits. . . . . . . . . . . . . 48 Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b . . . . . . . . . . . . . . 49 Table 74. Description of ManualRCVReg bits . . . . . . . . . 49 Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 50 Table 76. Description of TypeBReg bits. . . . . . . . . . . . . . 50 Table 77. SerialSpeedReg register (address 1Fh); PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 131 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution reset value: EBh, 11101011b . . . . . . . . . . . . . .51 Table 78. Description of SerialSpeedReg bits . . . . . . . . .51 Table 79. PageReg register (address 20h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .52 Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52 Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 82. Description of CRCResultReg bits . . . . . . . . . .52 Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 84. Description of CRCResultReg bits . . . . . . . . . .52 Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .53 Table 86. Description of GsNOffReg bits . . . . . . . . . . . . .53 Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b . . . . . . . . . . . . . . . . . . .54 Table 88. Description of ModWidthReg bits . . . . . . . . . . .54 Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .54 Table 90. Description of TxBitPhaseReg bits . . . . . . . . . .54 Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b . . . . . . . . . . . . . . . . . . .55 Table 92. Description of RFCfgReg bits . . . . . . . . . . . . .55 Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .56 Table 94. Description of GsNOnReg bits . . . . . . . . . . . . .56 Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .56 Table 96. Description of CWGsPReg bits. . . . . . . . . . . . .56 Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .57 Table 98. Description of ModGsPReg bits . . . . . . . . . . . .57 Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .57 Table 100. Description of TModeReg bits . . . . . . . . . . . . .57 Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .58 Table 102. Description of TPrescalerReg bits . . . . . . . . . .58 Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b . . . . . . . . .59 Table 104. Description of the higher TReloadReg bits . . .59 Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b . . . . . . . . .59 Table 106. Description of lower TReloadReg bits . . . . . . .59 Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb . . . . . . .60 Table 108. Description of the higher TCounterValReg bits 60 Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .60 Table 110. Description of lower TCounterValReg bits . . . .60 Table 111. PageReg register (address 30h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .60 Table 112. Description of PageReg bits. . . . . . . . . . . . . . .61 Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62 Table 114. Description of TestSel1Reg bits . . . . . . . . . . . .62 Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62 Table 116. Description of TestSel2Reg bits. . . . . . . . . . . . 62 Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 63 Table 118. Description of TestPinEnReg bits . . . . . . . . . . 63 Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 63 Table 120. Description of TestPinValueReg bits . . . . . . . . 63 Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 64 Table 122. Description of TestBusReg bits . . . . . . . . . . . . 64 Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b . . . . . . . . . . . . . . . . . . 64 Table 124. Description of bits . . . . . . . . . . . . . . . . . . . . . . 64 Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 65 Table 126. Description of VersionReg bits . . . . . . . . . . . . 65 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 66 Table 128. Description of AnalogTestReg bits . . . . . . . . . 66 Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67 Table 130. Description of TestDAC1Reg bits . . . . . . . . . . 67 Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67 Table 132. Description ofTestDAC2Reg bits. . . . . . . . . . . 67 Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 67 Table 134. Description of TestADCReg bits . . . . . . . . . . . 67 Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 136. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 68 Table 138. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 140. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 141. Connection protocol for detecting different interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 142. Connection scheme for detecting the different interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 70 Table 144. MOSI and MISO byte order . . . . . . . . . . . . . . 71 Table 145. Address byte 0 register; address MOSI . . . . . 71 Table 146. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 72 Table 147. Selectable UART transfer speeds . . . . . . . . . 72 Table 148. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 149. Read data byte order . . . . . . . . . . . . . . . . . . . 73 Table 150. Write data byte order . . . . . . . . . . . . . . . . . . . 73 Table 151. Address byte 0 register; address MOSI . . . . . 75 Table 152. Supported interface types . . . . . . . . . . . . . . . . 82 Table 153. Register and bit settings controlling the signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . 84 Table 154. Register and bit settings controlling the signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . 85 Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) . . . 86 Table 156. CRC coprocessor parameters . . . . . . . . . . . . 93 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 132 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .95 Table 158. Command overview . . . . . . . . . . . . . . . . . . .101 Table 159. Testsignal routing (TestSel2Reg = 07h) . . . . .107 Table 160. Description of Testsignals . . . . . . . . . . . . . . .107 Table 161. Testsignal routing (TestSel2Reg = 0Dh) . . . .108 Table 162. Description of Testsignals . . . . . . . . . . . . . . .108 Table 163. Testsignal routing (TestSel2Reg = 19h) . . . . .108 Table 164. Description of Testsignals . . . . . . . . . . . . . . .108 Table 165. Testsignals description. . . . . . . . . . . . . . . . . .108 Table 166. Limiting values . . . . . . . . . . . . . . . . . . . . . . . 111 Table 167. Operating conditions . . . . . . . . . . . . . . . . . . . 111 Table 168. Thermal characteristics . . . . . . . . . . . . . . . . . 112 Table 169. Characteristics . . . . . . . . . . . . . . . . . . . . . . . 112 Table 170. SPI timing characteristics . . . . . . . . . . . . . . . 117 Table 171. I2C-bus timing in Fast mode . . . . . . . . . . . . . 117 Table 172. AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 173. Timing specification for separated Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . 119 Table 174. Timing specification for common Read/Write strobe. . . . . . . . . . . . . . . . . . . . . .120 Table 175. Package information . . . . . . . . . . . . . . . . . . .122 Table 176. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .126 Table 177. Revision history . . . . . . . . . . . . . . . . . . . . . . .127 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 133 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 36. Figures Fig 1. Simplified block diagram of the PN512 . . . . . . . . .6 Fig 2. Detailed block diagram of the PN512 . . . . . . . . . .7 Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .8 Fig 4. Pinning configuration HVQFN40 (SOT618-1) . . . .8 Fig 5. Pin configuration TFBGA64 (SOT1336-1) . . . . . . .9 Fig 6. PN512 Read/Write mode. . . . . . . . . . . . . . . . . . .14 Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram. . . . . . . . . . . . . . . . . . . .14 Fig 8. Data coding and framing according to ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . .15 Fig 9. FeliCa reader/writer communication diagram . . .16 Fig 10. NFCIP-1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . .17 Fig 11. Active communication mode . . . . . . . . . . . . . . . .18 Fig 12. Passive communication mode . . . . . . . . . . . . . . .19 Fig 13. SPI connection to host. . . . . . . . . . . . . . . . . . . . .70 Fig 14. UART connection to microcontrollers . . . . . . . . .71 Fig 15. UART read data timing diagram . . . . . . . . . . . . .73 Fig 16. UART write data timing diagram . . . . . . . . . . . . .74 Fig 17. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .75 Fig 18. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .76 Fig 19. START and STOP conditions . . . . . . . . . . . . . . .76 Fig 20. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .77 Fig 21. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .77 Fig 22. First byte following the START procedure . . . . . .78 Fig 23. Register read and write access . . . . . . . . . . . . . .79 Fig 24. I2C-bus HS mode protocol switch . . . . . . . . . . . .80 Fig 25. I2C-bus HS mode protocol frame. . . . . . . . . . . . .81 Fig 26. Connection to host controller with separated Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83 Fig 27. Connection to host controller with common Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83 Fig 28. Data mode detector . . . . . . . . . . . . . . . . . . . . . . .87 Fig 29. Serial data switch for TX1 and TX2 . . . . . . . . . . .88 Fig 30. Communication flows using the S2C interface. . .89 Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Fig 32. Signal shape for SIGIN in SAM mode . . . . . . . . .90 Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 35. Quartz crystal connection . . . . . . . . . . . . . . . . . .99 Fig 36. Oscillator start-up time . . . . . . . . . . . . . . . . . . . .100 Fig 37. Autocoll Command . . . . . . . . . . . . . . . . . . . . . .104 Fig 38. Typical circuit diagram . . . . . . . . . . . . . . . . . . . . 110 Fig 39. Pin RX input voltage range . . . . . . . . . . . . . . . . 116 Fig 40. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . 118 Fig 41. Timing for Fast and Standard mode devices on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Fig 42. Timing diagram for separated Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Fig 43. Timing diagram for common Read/Write strobe 121 Fig 44. Package outline package version (HVQFN32) .123 Fig 45. Package outline package version (HVQFN40) .124 Fig 46. Package outline package version (TFBGA64). .125 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 134 of 136 continued >> NXP Semiconductors PN512 Full NFC Forum compliant solution 37. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Different available versions. . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information. . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 14 8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . 14 8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . 15 8.3 FeliCa reader/writer functionality . . . . . . . . . . 16 8.3.1 FeliCa framing and coding . . . . . . . . . . . . . . . 16 8.4 NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4.1 Active communication mode . . . . . . . . . . . . . 18 8.4.2 Passive communication mode . . . . . . . . . . . . 19 8.4.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 20 8.4.4 NFCIP-1 protocol support. . . . . . . . . . . . . . . . 20 8.4.5 MIFARE Card operation mode . . . . . . . . . . . . 20 8.4.6 FeliCa Card operation mode . . . . . . . . . . . . . 21 9 PN512 register SET . . . . . . . . . . . . . . . . . . . . . 21 9.1 PN512 registers overview. . . . . . . . . . . . . . . . 21 9.1.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . 23 9.2 Register description . . . . . . . . . . . . . . . . . . . . 24 9.2.1 Page 0: Command and status . . . . . . . . . . . . 24 9.2.1.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1.2 CommandReg . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1.3 CommIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.1.4 DivIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.2.1.5 CommIRqReg. . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.1.6 DivIRqReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.1.7 ErrorReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.1.8 Status1Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.1.9 Status2Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.1.10 FIFODataReg . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1.11 FIFOLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1.12 WaterLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.1.13 ControlReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.1.14 BitFramingReg . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.1.15 CollReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2.2 Page 1: Communication . . . . . . . . . . . . . . . . . 36 9.2.2.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.2.2 ModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2.2.3 TxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2.2.4 RxModeReg. . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2.2.5 TxControlReg. . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.2.6 TxAutoReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2.7 TxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.2.8 RxSelReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.2.9 RxThresholdReg . . . . . . . . . . . . . . . . . . . . . . 44 9.2.2.10 DemodReg. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.2.11 FelNFC1Reg . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.2.12 FelNFC2Reg . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2.2.13 MifNFCReg . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.2.14 ManualRCVReg. . . . . . . . . . . . . . . . . . . . . . . 49 9.2.2.15 TypeBReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2.2.16 SerialSpeedReg. . . . . . . . . . . . . . . . . . . . . . . 50 9.2.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 52 9.2.3.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.3.2 CRCResultReg . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.3.3 GsNOffReg . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2.3.4 ModWidthReg . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3.5 TxBitPhaseReg . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3.6 RFCfgReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.3.7 GsNOnReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.8 CWGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.9 ModGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.3.10 TMode Register, TPrescaler Register . . . . . . 57 9.2.3.11 TReloadReg. . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2.3.12 TCounterValReg . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.2 TestSel1Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.3 TestSel2Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.4 TestPinEnReg . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.4.5 TestPinValueReg . . . . . . . . . . . . . . . . . . . . . . 63 9.2.4.6 TestBusReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.7 AutoTestReg . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.8 VersionReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.9 AnalogTestReg. . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.4.10 TestDAC1Reg . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.11 TestDAC2Reg . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.12 TestADCReg . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.13 RFTReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . 68 10.1 Automatic microcontroller interface detection 68 10.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 70 10.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.2 SPI write data. . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 71 10.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.1 Connection to a host . . . . . . . . . . . . . . . . . . . 71 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 135 of 136 continued >> NXP Semiconductors PN512 Full NFC Forum compliant solution 10.3.2 Selectable UART transfer speeds . . . . . . . . . 71 10.3.3 UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 75 10.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4.2 START and STOP conditions . . . . . . . . . . . . . 76 10.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 78 10.4.6 Register write access . . . . . . . . . . . . . . . . . . . 78 10.4.7 Register read access . . . . . . . . . . . . . . . . . . . 79 10.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 80 10.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 80 10.4.10 Serial data transfer format in HS mode . . . . . 80 10.4.11 Switching between F/S mode and HS mode . 82 10.4.12 PN512 at lower speed modes . . . . . . . . . . . . 82 11 8-bit parallel interface . . . . . . . . . . . . . . . . . . . 82 11.1 Overview of supported host controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2 Separated Read/Write strobe . . . . . . . . . . . . . 83 11.3 Common Read/Write strobe . . . . . . . . . . . . . . 83 12 Analog interface and contactless UART . . . . 84 12.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.2 TX driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3 RF level detector . . . . . . . . . . . . . . . . . . . . . . 85 12.4 Data mode detector . . . . . . . . . . . . . . . . . . . . 86 12.5 Serial data switch . . . . . . . . . . . . . . . . . . . . . . 88 12.6 S2C interface support . . . . . . . . . . . . . . . . . . . 88 12.6.1 Signal shape for Felica S2C interface support 90 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support . . . . . . . . . . . . . . . . . . . 91 12.7 Hardware support for FeliCa and NFC polling 92 12.7.1 Polling sequence functionality for initiator. . . . 92 12.7.2 Polling sequence functionality for target . . . . . 92 12.7.3 Additional hardware support for FeliCa and NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.7.4 CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 93 13 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 94 13.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 94 13.3 FIFO buffer status information . . . . . . . . . . . . 94 14 Interrupt request system. . . . . . . . . . . . . . . . . 95 14.1 Interrupt sources overview . . . . . . . . . . . . . . . 95 15 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 16 Power reduction modes . . . . . . . . . . . . . . . . . 98 16.1 Hard power-down . . . . . . . . . . . . . . . . . . . . . . 98 16.2 Soft power-down mode. . . . . . . . . . . . . . . . . . 98 16.3 Transmitter power-down mode . . . . . . . . . . . . 98 17 Oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . 99 18 Reset and oscillator start-up time . . . . . . . . . 99 18.1 Reset timing requirements . . . . . . . . . . . . . . . 99 18.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 99 19 PN512 command set . . . . . . . . . . . . . . . . . . . 100 19.1 General description . . . . . . . . . . . . . . . . . . . 100 19.2 General behavior . . . . . . . . . . . . . . . . . . . . . 100 19.3 PN512 command overview . . . . . . . . . . . . . 101 19.3.1 PN512 command descriptions . . . . . . . . . . . 101 19.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 19.3.1.2 Config command . . . . . . . . . . . . . . . . . . . . . 101 19.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . 102 19.3.1.4 CalcCRC . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.6 NoCmdChange . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.7 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.8 Transceive . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.3.1.9 AutoColl . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.3.1.10 MFAuthent . . . . . . . . . . . . . . . . . . . . . . . . . . 105 19.3.1.11 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 20 Testsignals. . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.2 Testbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.3 Testsignals at pin AUX . . . . . . . . . . . . . . . . . 108 20.4 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 109 22 Application design-in information. . . . . . . . . 110 23 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 111 24 Recommended operating conditions . . . . . . 111 25 Thermal characteristics . . . . . . . . . . . . . . . . . 112 26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112 26.1 Timing characteristics . . . . . . . . . . . . . . . . . . 117 26.2 8-bit parallel interface timing . . . . . . . . . . . . . 119 26.2.1 AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119 26.2.2 AC operating specification . . . . . . . . . . . . . . . 119 26.2.2.1 Bus timing for separated Read/Write strobe . 119 26.2.2.2 Bus timing for common Read/Write strobe . 120 27 Package information. . . . . . . . . . . . . . . . . . . 122 28 Package outline. . . . . . . . . . . . . . . . . . . . . . . 123 29 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 126 30 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 31 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 126 32 Revision history . . . . . . . . . . . . . . . . . . . . . . 127 33 Legal information . . . . . . . . . . . . . . . . . . . . . 128 33.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 128 33.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 128 33.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 128 33.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 33.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 129 NXP Semiconductors PN512 Full NFC Forum compliant solution © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 December 2013 111345 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 34 Contact information. . . . . . . . . . . . . . . . . . . . 129 35 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 36 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 37 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 1. General description The UHF EPCglobal Generation 2 standard allows the commercialized provision of mass adoption of UHF RFID technology for passive smart tags and labels. Main fields of applications are supply chain management and logistics for worldwide use with special consideration of European, US and Chinese frequencies to ensure that operating distances of several meters can be realized. The NXP Semiconductors UCODE product family is compliant to this EPC gen2 standard offering anti-collision and collision arbitration functionality. This allows a reader to simultaneously operate multiple labels/tags within its antenna field. The UCODE based label/ tag requires no external power supply for contactless operation. Its contactless interface generates the power supply via the antenna circuit by propagative energy transmission from the interrogator (reader), while the system clock is generated by an on-chip oscillator. Data transmitted from the interrogator to the label/tag is demodulated by the interface, and it also modulates the interrogator's electromagnetic field for data transmission from the label/tag to the interrogator. A label/tag can be then operated without the need for line of sight or battery, as long as it is connected to a dedicated antenna for the targeted frequency range. When the label/tag is within the interrogator's operating range, the high-speed wireless interface allows data transmission in both directions. With the UCODE I2C product, NXP Semiconductors introduces now the possibility to combine 2 independent UHF Interfaces (following EPC gen 2 standard) with an I2C interface. Its large memory can be then read or write via both interfaces. This I2C functionality enables the standard EPC gen 2 functionalities to be linked to an electronic device microprocessor. By linking the rich functionalities of the EPC gen 2 standards to the Electronics world, the UCODE I2C product opens a whole new range of application. The I2C interface needs to be supplied externally and supports standard and fast I2C modes. Its large memory is based on a field proven non-volatile memory technology commonly used in high quality automotive applications SL3S4011_4021 UCODE I²C Rev. 3.1 — 3 July 2013 204931 Product data sheet COMPANY PUBLIC SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 2 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 2. Features and benefits 2.1 UHF interface  Dual UHF antenna port  18 dBm READ sensitivity  11 dBm WRITE sensitivity  23 dBm READ & WRITE sensitivity with the chip powered  Compliant to EPCglobal Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for communications at 860 MHz to 960 MHz version 1.2.0  Wide RF interface temperature range: 40 °C up to +85 °C  Memory read protection  Interrupt output  RF - I2C bridge function based on SRAM memory 2.2 I2C interface  Supports Standard (100 kHz) and Fast (400 kHz) mode (see Ref. 1)  UCODE I2C can be used as standard I2C EEPROMs 2.3 Command set  All mandatory EPC Gen2 v1.2.0 commands  Optional commands: Access, Block Write (32 bit)  Custom command: ChangeConfig 2.4 Memory  3328-bit user memory  160-bit EPC memory  96-bit tag identifier (TID) including 48-bit unique serial number  32-bit KILL password to permanently disable the tag  32-bit ACCESS password to allow a transition into the secured transmission state  Data retention: 20 years at 55 °C  Write endurance: 50 kcycles at 85 °C 2.5 Package  SOT-902-3; MO-255B footprint  Outline 1.6 × 1.6 mm  Thickness  0.5 mm SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 3 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 3. Applications  Firmware downloads  Return management  Counterfeit protection and authentication  Production information  Theft protection and deterrence  Production automation  Device customization/product configuration  Offline Diagnostics 4. Ordering information [1] RFP1, RFN1 Table 1. Ordering information Type number Package Name Description Version SL3S4011FHK XQFN8 Single differential RF Front End [1]- Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-3 SL3S4021FHK XQFN8 Dual differential RF Front End - Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-3 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 4 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 5. Block diagram Fig 1. Block diagram RFP1 DIFFERENTIAL UHF FRONTEND 1 RFN1 RFN2 DIFFERENTIAL UHF FRONTEND 2 NON VOLATILE MEMORY I2C INTERFACE ISO18000-6 DIGITAL INTERFACE ANALOG UHF antenna 2 UHF antenna 1 I2C DRIVER/SCL INT SIGNALLING DRIVER 50 ns SPIKE INPUT FILTER RFP2 SCL SDA I2C DRIVER/SDA CE OUPUT DRIVER 50 ns SPIKE INPUT FILTER VDDB VDDB POWER MANAGEMENT/ GND 001aao224 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 5 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 6. Pinning information 6.1 Pinning 6.2 Pin description (1) Dimension A: 1.6 mm (2) Dimension B: 0.5 mm Fig 2. Pin configuration 001aao225 VDD Transparent top view side view 4 8 6 5 7 3 1 RF1N 2 RF1P SCL A B GND A RF2N SDA RF2P Table 2. Pin description Pin Symbol Description 1 RF1P active antenna 1 connector 2 RF1N antenna 1 3 SCL I2C clock / _INT 4 VDD supply 5 SDA I2C data 6 RF2N antenna 2 7 RF2P active antenna 2 connector 8 GND ground SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 6 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 7. Mechanical specification 7.1 SOT902 specification 8. Functional description 8.1 Air interface standards The UCODE I2C fully supports all mandatory parts of the "Specification for RFID Air Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 8.2 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE I2C. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the UCODE I2C on the tag. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. For I2C operation the UCODE I2C has to be supplied externally via the VDD pin. 8.3 Data transfer air interface 8.3.1 Interrogator to tag Link An interrogator transmits information to the UCODE I2C by modulating a UHF RF signal. The UCODE I2C receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. An interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. The interrogator communicates to the UCODE I2C by modulating an RF carrier using DSB-ASK with PIE encoding. 8.3.2 Tag to reader Link An interrogator receives information from a UCODE I2C by transmitting an unmodulated RF carrier and listening for a backscattered reply. The UCODE I2C backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. Table 3. Mechanical properties XQFN8 Package name Outline code Package size Reel format SOT902 SOT902-3 size:1.6 mm × 1.6 mm 4000 pcs thickness: 0.5 mm 7” diameter Carrier tape width 8 mm Carrier pocket pitch 4 mm SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 7 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C The UCODE I2C communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subaltern. 8.4 Data transfer to I2C interface The UCODE I2C memory can be read/written similar to a standard I2C serial EEPROM device. The address space is arranged in a linear manner. When performing a sequential read the address pointer is increased linearly from start of the EPC memory to the end of the user memory. At the end address of each bank the address pointer jumps automatically to the first address in the subsequent bank. In I2C write modes only even address values are accepted, due to the word wise organization of the EEPROM. Regarding arbitration between RF and I2C, see Section 11 “RF interface/I2C interface arbitration”). Write operation: • Write word • Write block (2 words) Read operation: • current address read • random address read • sequential current read • random sequential read 8.5 Supported commands The UCODE I2C supports all mandatory EPCglobal V1.2.0 commands. In addition the UCODE I2C supports the following optional commands. • Access • BlockWrite (32 bit) The UCODE I2C features the following custom commands described in more detail later: • ChangeConfig 8.6 UCODE I2C memory The UCODE I2C memory is implemented according to EPCglobal Gen2 and organized in four sections all accessible via both RF and I2C operation except the reserved memory section which only accessible via RF: SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 8 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C The logical addresses of all memory banks begin at zero (00h). In addition to the 4 memory banks one configuration word to handle the UCODE I2C specific features is available at EPC bank 01b address 200h. The configuration word is described in detail in section “UCODE I2C special features”. Table 4. UCODE I2C memory sections Name Size Bank Reserved memory (32-bit ACCESS and 32-bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16-bit PC) 160 bit 01b Download register 16 bit 01b UCODE I2C Configuration Word 16 bit 01b TID (including unique 48 bit serial number) 96 bit 10b User Memory 3328 bit 11b xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 9 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 8.6.1 UCODE I2C overall memory map [1] SL3S4011 EPC: E200 680D 0000 0000 0000 0000 0000 0000 0000 0000 SL3S4021 EPC: E200 688D 0000 0000 0000 0000 0000 0000 0000 0000 [2] see TID paragraph Table 5. Memory map Bank address Memory address Type Content Initial value Remark RF I2C Bank 00 00h to 1Fh not accessible via i2C reserved kill password all 00h unlocked memory 20h to 3Fh not accessible via i2C reserved access password all 00h unlocked memory Bank 01 EPC 00h to 0Fh 2000h EPC CRC-16: refer to Ref. 5 memory mapped calculated CRC 10h to 1Fh 2002h EPC PC 3000h unlocked memory 20h to 2Fh 2004h EPC EPC bit [0 to 15] [1] unlocked memory ... EPC ... unlocked memory 20h to BFh 2016h EPC EPC bit [144 to 159] unlocked memory 1F0h to 1FFh 203Eh EPC download register for the bridge function 200h to 20Fh 2040h EPC Configuration word, see Section 9.2 Bank 10 TID 00h to 0Fh 4000h TID TID header n.a. locked memory 10h to 1Fh 4002h TID TID header n.a. locked memory 20h to 2Fh 4004h TID XTID_header 0000h locked memory 30h to 3Fh 4006h TID TID serial number [2] locked memory 40h to 4Fh 4008h TID TID serial number n.a. locked memory 50h to 5Fh 400Ah TID TID serial number n.a. locked memory Bank 11 User memory 000h to 00Fh 6000h UM user memory bit [0 to 15] all 00h unlocked memory 010h to 01Fh 6002h UM user memory bit [16 to 31] all 00h unlocked memory ... UM all 00h unlocked memory CF0h to CFFh 619Eh UM user memory bit [3311 to 3327] all 00h unlocked memory xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 10 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 8.6.2 UCODE I2C TID memory details Table 6. UCODE I2C TID description Model number Type First 32 bit of TID memory Class ID Mask designer ID Config Word indicator Sub version number Version (Silicon) number UCODE SL3S4011 E200680D E2h 006h 1 0000b 0001101 UCODE SL3S4021 E200688D E2h 006h 1 0001b 0001101 Fig 3. UCODE I2C TID memory structure aaa-006851 Class Identifier MS Byte MS Bit LS Bit TID Mask-Designer Identifier Model Number XTID Header Serial Number Bits 7 0 11 0 11 0 15 0 47 0 Addresses 00h 07h 13h 1Fh 5Fh Addresses 00h CFh 08h 14h 20h 2Fh 30h E2h (EAN.UCC) TID Example (UCODE I2C) 006h (NXP) 0000h Sub Version Number Version Number 000b or 001b 0001101b (UCODE I2C) Bits 0 3 0 6 0 Addresses 14h 18h 19h 1Fh 80Dh or 88Dh (UCODE I2C) LS Byte SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 11 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9. Supported features The UCODE I2C is equipped with a number of additional features and a custom command. Nevertheless, the chip is designed in a way that standard EPCglobal READ / WRITE / ACCESS commands can be used to operate the features. The memory map in the previous section describes the Configuration Word used to control the additional features located after address 200h of the EPC memory, hence UCODE I2C features are controlled by bits located in the EPC number space. For this reason the standard READ / WRITE commands of a UHF EPCglobal compliant reader can be used to select the flags or activate/deactivate features if the memory bank is not locked. In case of locked memory banks the ChangeConfig custom command has to be used. The bits (flags) of the ConfigurationWord are selectable using the standard EPC SELECT command. 9.1 UCODE I2C special feature • Externally Supplied flag The flag will indicate the availability of an external supply. • RF active flag The flag will indicate on which RF port power is available and signal transmission ongoing. • RF Interface on/off switching For privacy reasons the two RF ports as well as the I2C interface can be switched on/off by toggling the related bits of the ConfigurationWord. The ConfigurationWord is accessible via RF and I2C interface. Although it is possible to kill the RF interface via the KILL feature of EPC gen2, a minimum of one port shall be active at all times. In the case of the dual port version, either one or both RF can be active. In the case of the single front end version, the RF port can not be deactivated. • I2C Interface on/off switching For privacy reasons the I2C port can be disabled by toggling the related bit of the Config-Word but only via RF. • RF - I2C Bridge feature The UCODE I2C can be used as an RF- I2C bridge to directly forward data from the RF interface to the I2C interface and vice versa. The UCODE I2C is equipped with a download/upload register of 16-bit data buffer located in the EPC bank. The data received via RF can be read via I2C like regular memory content. In case the buffer is empty reading the register returns NAK. This feature can be combined with the Download Indicator. – Upload Indicator flag (I2C to UHF) - address 203h in the configuration word The flag will indicate if data in the download/upload register is available. Will be automatically cleared when the download/upload register is read out via UHF. – Download Indicator flag (UHF to I2C) - address 200h in the configuration word The flag will indicate if data in the download/upload register is available. Will be automatically cleared when the download/upload register is read out via I2C. SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 12 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C • Interrupt signaling/Download Indicator The UCODE I2C features two methods of signaling: 1. Signaling via ConfigWord "Download/Upload Indicator" (200h or 203h): – The Download/Upload Indicator will go high as soon new data from the RF reader or from the I2C interface is written to the buffer register. This flag can be polled via I2C READ or using the SELECT command. Reading an empty buffer register will return NAK. – The Download/Upload Indicator will automatically return to low as soon as the data is read. 2. Interrupt Signaling via the I2C-SCL line: – If the SCL INT enabler of the ConfigWord is set (20Bh) the SCL line will be pulled low for at least 210 s in case new data was written by the reader or at least 85 s in case new data has been read by the reader (see Figure 4 “SCL interrupt signalling” and Table 7 “Interrupt signaling via the I2C-SCL line timing”). [1] This timing parameter is dependent on the chosen return link frequency. [2] At 640 kHz return link frequency. Remark: The features can even be operated (enabled/disabled) with '0' as ACCESS password. It is recommended to set an ACCESS password to avoid unauthorized manipulation of the features via the RF interface. 9.2 UCODE I2C special features control mechanism Special features of the UCODE I2C are managed using a Configuration Word (ConfigWord) located at the end of the EPC memory bank (address 200h via RF or 2040h via I2C) - see Table 8 and Table 9. Fig 4. SCL interrupt signalling Table 7. Interrupt signaling via the I2C-SCL line timing Symbol Min Typ Max Unit tSCL low_write 210 266 320 s tSCL low_read[1] 85 102[2] 7800 s aaa-005682 UHF Write DL Reg Command SCL UHF SCL Read DL Reg Command Read DL Reg Response Write DL Reg Response tSCL low_read tSCL low_write SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 13 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C The bits of the ConfigWord are selectable (using the standard EPC SELECT command) and can be read, via RF, using standard EPC READ command and via I2C. They can be modified using the ChangeConfig custom command or standard READ/WRITE commands or via the I2C interface (if allowed). [1] Indicator bits are reset at power-up but cannot be changed by command [2] Permanent bits are permanently stored bits in the memory [3] Defaults values for bit3/bit2/bit1 are 0/0/1 (see Table 14) Table 8. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (1 RF front end version SL3S4011) Feature Bit type via RF via I2C Address Access Address Access Download indicator indicator[1] 200h read 2040h read Externally supplied flag indicator 201h read read RF active flag indicator 202h read read Upload indicator Indicator 203h read read I2C address bit 3[3] permanent[2] 204h r/w read only I2C address bit 2[3] permanent 205h r/w read only I2C address bit 1[3] permanent 206h r/w read only I2C port on/off permanent 207h r/w read only UHF antenna port1 on locked 208h read only read only rfu 209h rfu 20Ah SCL INT enable permanent 20Bh r/w read only bit for read protect user memory permanent 20Ch r/w r/w bit for read protect EPC permanent 20Dh r/w r/w bit for read protect TID SNR (48 bits) permanent 20Eh r/w r/w PSF alarm flag permanent 20Fh r/w read only Table 9. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (2 RF front end version SL3S4021) Feature Bit type via RF via I2C Address Access Address Access Download indicator indicator[1] 200h read 2040h read Externally supplied flag indicator 201h read read RF active flag indicator 202h read read Upload indicator indicator 203h read read I2C address bit 3[3] permanent[2] 204h r/w read only I2C address bit 2[3] permanent 205h r/w read only I2C address bit 1[3] permanent 206h r/w read only I2C port on/off permanent 207h r/w read only UHF antenna port1 on/off permanent 208h r/w r/w UHF antenna port2 on/off permanent 209h r/w r/w rfu 20Ah SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 14 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C [1] Indicator bits are reset at power-up but cannot be changed by command [2] Permanent bits are permanently stored bits in the memory [3] Defaults values for bit3/bit2/bit1 are 0/0/1 (see Table 14) SCL INT enable permanent 20Bh r/w read only bit for read protect user memory permanent 20Ch r/w r/w bit for read protect EPC permanent 20Dh r/w r/w bit for read protect TID SNR (48 bits) permanent 20Eh r/w r/w PSF alarm flag permanent 20Fh r/w read only Table 9. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (2 RF front end version SL3S4021) Feature Bit type via RF via I2C Address Access Address Access SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 15 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9.3 Change Config Command The UCODE I2C ChangeConfig custom command allows handling the special features described in the previous paragraph. As long the EPC bank is not write locked standard EPC READ/WRITE commands can be used to modify the flags. The bits to be toggled in the configuration register need to be set to '1'. E.g. sending 0000 0000 0000 0000 1001 XOR RN16 will activate the EPC Read Protect and PSF bit. Sending the very same command a second time will disable the features. The reply of the ChangeConfig will return the current register setting. The features can only be activated/deactivated in the open or secured state and with a non-zero ACCESS password. If the EPC memory bank is locked for writing, the ChangeConfig command is needed to modify the ConfigurationWord. Table 10. ChangeConfig custom command Command RFU Data RN CRC-16 No. of bits 16 8 16 16 16 Description 11100000 00000111 00000000 Toggle bits XOR RN16 handle - Table 11. ChangeConfig custom response table Starting state Condition Response Next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle, Status word needs to change Backscatter unchanged StatusWord immediately open valid handle, Status word does not need to change Backscatter StatusWord immediately open secured valid handle, Status word needs to change Backscatter modified StatusWord, when done secured valid handle, Status word does not need to change Backscatter StatusWord immediately secured invalid handle - secured killed all - killed xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 16 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9.4 UCODE I2C memory bank locking mechanism 9.4.1 Possibilities 9.4.2 Via RF The UCODE I2C memory banks can be locked following EPC Gen2 mandatory command via RF (see table Table 13). Table 12. Memory banks locking possibilities for UCODE I2C via RF and I2C I2C interface RF interface Memory bank Lock (entire bank) PermaLock (entire bank) Lock (entire bank) via Access Password PermaLock (entire bank) via Access Password 01 EPC yes yes yes yes 11 User Memory yes yes yes yes Table 13. Lock payload and usage Kill pwd Access pwd EPC memory TID memory User memory 19 18 17 16 15 14 13 12 11 10 Mask skip/write skip/write skip/write skip/write skip/write skip/write skip/write skip/write skip/write skip/write 9 8 7 6 5 4 3 2 1 0 Action pwd read/write permalock pwd read/write permalock pwd write permalock pwd write permalock pwd write permalock SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 17 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9.4.3 Via I2C The EPC Gen2 locking bits for the memory banks are also accessible via the I2C interface for read and write operation and are located at the I2C address 803Ch. But it is not possible to read and write the access and kill password. Fig 5. I2C memory bank lock write and read access Data Byte 1 Mask field Action field Kill PWD Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write X X X X X X X X X X X X Access PWD User memory RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU EPC memory TID memory Kill PWD n/a n/a n/a n/a permalock permalock permalock PWD write PWD write PWD write Access PWD EPC memory TID memory User memory MSB Data Byte 2 LSB MSB Data Byte 3 Data Byte 4 LSB aaa-003734 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 18 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10. I2C commands 10.1 UCODE I2C operation For details on I2C interface refer to Ref. 1. The UCODE I2C supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. 10.2 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The UCODE I2C continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Fig 6. I2C bus protocol SCL SDA SCL 1 2 3 7 8 9 1 2 3 7 8 9 MSB ACK MSB ACK Start Condition SDA Input SDA Change Stop Condition Stop Condition Start Condition SDA SCL SDA 001aao231 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 19 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.3 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the UCODE I2C and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the UCODE I2C into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle. 10.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 10.5 Data input During data input, the UCODE I2C samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 10.6 Addressing To start communication between a bus master and the UCODE I2C slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code. The 7-bit device select code consists of a 4-bit device identifier (value Ah) which is initialized in wafer test and cannot be changed in the user mode. Three additional bits in the configuration word are reserved to alter the device address via RF interface after initialization. This allows up to eight UCODE I2C devices to be connected to a bus master at the same time. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the UCODE I2C gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the UCODE I2C does not match the device select code, it deselects itself from the bus. [1] Initial values - can be changed - See also Table 8 and Table 9. Table 14. Device select code Device type identifier Device address in configuration word 204h to 206h R/W Device select code b7 b6 b5 b4 b3 b2 b1 b0 Value 1 0 1 0 0 [1] 0 [1] 1 [1] 1/0 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 20 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.7 Write Operation The byte address must be an even value due to the word wise organization of the EEPROM. Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The UCODE I2C acknowledges this, as shown in Figure 7 and waits for two address bytes. The UCODE I2C responds to each address byte with an acknowledge bit, and then waits for the data Byte. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 15) is sent first, followed by the Least Significant Byte (Table 15). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the ACK bit (in the "10th bit" time slot), either at the end of a Word Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the UCODE I2C does not respond to any requests. Table 15. I2C addressing Most significant byte b15 b14 b13 b12 b11 b10 b9 b8 EPC address EPC/Lock EPC memory bank EPC memory word address Least significant byte b7 b6 b5 b4 b3 b2 b1 b0 EPC address EPC memory word address MSB/ LSB Fig 7. I2C write operation ACK Word Write Page Write Page Write (cont’d) ACK ACK ACK ACK Stop Start R/W Dev select Byte address Byte address Data in 1 Data in 2 ACK Stop 001aao230 ACK ACK ACK ACK Start R/W Dev select Byte address Byte address Data in 1 Data in 2 ACK Data in N SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 21 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.7.1 Word Write After the device select code and the address word, the bus master sends one word data. If the addressed location is Write-protected, the UCODE I2C replies with NACK, and the location is not modified. If, instead, the addressed location is not Write-protected, the UCODE I2C replies with ACK. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. 10.7.2 Page Write The Page Write mode allows 2 words to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits (b12-b2) are the same and b1= 0 and b0 = 0. If more than two words are sent than each additional byte will cause a NACK on SDA. The bus master sends from 1 to 2 words of data, each of which is acknowledged by the UCODE I2C. The transfer is terminated by the bus master generating a Stop condition. 10.8 Read operation After the successful completion of a read operation, the UCODE I2C's internal address counter is incremented by one, to point to the next byte address. Fig 8. I2C read operation ACK ACK NO ACK Current Address Read Random Address Read Sequential Current Read Sequential Random Read ACK ACK ACK NO ACK Stop Start Start Start Stop R/W R/W R/W R/W Dev select * Byte address Dev select * Data out Dev select Data out Byte address ACK ACK ACK NO ACK NO ACK Stop Stop Start Dev select Data out 1 Data out N 001aao229 ACK ACK ACK ACK ACK Start Start R/W R/W Dev select * Byte address Byte address Dev select * Data out 1 ACK Data out N SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 22 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.8.1 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 8) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The UCODE I2C acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 10.8.2 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a UCODE I2C select code with the Read/Write bit (RW) set to 1. The UCODE I2C acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without acknowledging the Byte. 10.8.3 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the UCODE I2C continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. 10.8.4 Acknowledge in Read mode For all Read commands, the UCODE I2C waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the UCODE I2C terminates the data transfer and switches to its Standby mode. 10.8.5 EPC memory bank handling After the last memory address within one EPC memory bank, the address counter 'rolls-over' to the next EPC memory bank, and the UCODE I2C continues to output data from memory address 00h in the successive EPC memory bank. Example: EPC Bank 01  EPC Bank 10  EPC Bank 11  EPC Bank 01 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 23 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 11. RF interface/I2C interface arbitration The UCODE I2C needs to arbitrate the EEPROM access between the RF and the I2C interface. The arbitration is implemented as following: • First come, first serve strategy - the interface which provides data by having a first valid preamble on RF envelope (begin of a command) or a start condition and a valid I2C device address on the I2C interface will be favored. • I2C access to the chip memory is possible regardless if it is in the EPC Gen2 secured state or not • During an I2C command, starting with an I2C start followed by valid I2C device address and ending with an I2C stop condition, any RF command is ignored. • During any EPC Gen2 command any I2C command is ignored 12. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP8 package. [4] For ESD measurement, the die chip has been mounted into a CDIP8 package. Table 16. Limiting values[1][2] [3][4] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit Die Vmax maximum voltage on pin VDD, SDA, SCL, GND 0.3 3.6 V Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage Human body model; SNW-FQ-302A - 2 kV Charged device model - 500 V SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 24 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 13. Characteristics [1] Some legacy Standard-mode devices had fixed input levels of VIL = 1.5 V and VIH = 3.0 V. Refer to component data sheets. [2] Maximum VIH = VDD(max) + 0.5 V or 5.5 V, which ever is lower. See component data sheets. [3] The same resistor value to drive 3 mA at 3.0 V VDD provides the same RC time constant when using <2 V VDD with a smaller current draw. [4] Only applies to Fast Mode and Fast Mode Plus. Table 17. Characteristics Symbol Parameter Conditions Min Typ Max Unit EEPROM characteristics tret retention time Tamb  55 C 20 - - year Nendu(W) write endurance Tamb  85 C 50000 - - cycle Interface characteristics Ptot total power dissipation - - 30 mW foper operating frequency 840 - 960 MHz Pmin minimum operating power supply Read mode - 18 - dBm Write mode - 11 - dBm Read and Write mode with VDD input - 23 - dBm VDD supply voltage I2C, on VDD input 1.8 - 3.6 V VDD supply voltage rise time requirements 100 - - s IDD supply current from VDD in I2C read mode - 10 - A from VDD in I2C write mode - 40 - A Z impedance (package) 915 MHz - 12,7-j 199 -  - modulated jammer suppression  1.0 MHz - 4 - dB - unmodulated jammer suppression  1.0 MHz - 4 - dB VIL LOW-level input voltage[1] -0.5 - 0.3 VDD V VIH HIGH-level input voltage[1] 0.7 VDD - -[2] V Vhys hysteresis of Schmitt trigger inputs[4] 0.05 VDD - - V VOL1 LOW-level output voltage 1 (open-drain or open-collector) at 3 mA sink current[3]; VDD > 2 V 0 - 0.4 V VOL2 LOW-level output voltage 2[4] (open-drain or open-collector) at 2 mA sink current[3]; VDD  2 V 0 - 0.2VDD V SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 25 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 14. Package outline Fig 9. Package outline SOT902-3 Outline References version European projection Issue date IEC JEDEC JEITA SOT902-3 - - - MO-255 - - - sot902-3_po 11-08-16 11-08-18 Unit mm max nom min 0.5 0.05 0.00 1.65 1.60 1.55 1.65 1.60 1.55 0.6 0.5 0.1 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-3 A1 b 0.25 0.20 0.15 D E e e1 L 0.45 0.40 0.35 v w 0.05 y y1 0.05 0 1 2 mm scale terminal 1 index area D B A E X C y1 C y terminal 1 index area 3 L e1 e v C A B w C 2 1 5 6 7 metal area not for soldering 8 4 e1 e b A1 A detail X SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 26 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 15. Abbreviations 16. References [1] I2C-bus specification and user manual (NXP standard UM10204.pdf / Rev. 03 - 19 June 2007) [2] EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz - 960 MHz Version 1.2.0 [3] EPC Conformance Standard Version 1.0.5 [4] ESD Method SNW -FQ-302A [5] ISO/IEC 18000-1: Information technology - Radio frequency identification for item management - Part 1: Reference architecture and definition of parameters to be standardized Table 18. Abbreviations Acronym Description CRC Cyclic Redundancy Check CW Continuous Wave EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bhi phase space modulation HBM Human Body Model IC Integrated Circuit LSB Least Significant Byte/Bit MSB Most Significant Byte/Bit NRZ Non-Return to Zero coding RF Radio Frequency RTF Reader Talks First Tari Type A Reference Interval (ISO 18000-6) UHF Ultra High Frequency Xxb Value in binary notation XXhex Value in hexadecimal notation SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 27 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 17. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3S4011_4021 v. 3.1 20130703 Product data sheet - SL3S4011_4021 v. 3.0 Modifications: • General update SL3S4011_4021 v. 3.0 20130416 Product data sheet - SL3S4011_4021 v. 2.3 Modifications: • Data sheet status changed to Product data sheet SL3S4011_4021 v. 2.3 20130305 Preliminary data sheet - SL3S4011_4021 v. 2.2 Modifications: • General update • Security status changed into COMPANY PUBLIC SL3S4011_4021 v. 2.2 20121127 Preliminary data sheet SL3S4011_4021 v. 2.1 Modifications: • General update SL3S4011_4021 v. 2.1 20120726 Preliminary data sheet - SL3S4001FHK v. 2.0 Modifications: • General update SL3S4011_4021 v. 2.0 20120627 Preliminary data sheet - SL3S4001FHK v. 1.2 Modifications: • General update SL3S4001FHK v. 1.2 20111004 Objective data sheet - SL3S4001FHK v. 1.1 Modifications: • Table 1 “Ordering information”: updated • Figure 3 “UCODE I2C wafer layout”: values updated SL3S4001FHK v. 1.1 20110707 Objective data sheet - SL3S4001FHK v. 1.0 Modifications: • Table 3 “Mechanical properties XQFN8”: updated • Section 10.6 “Addressing”: updated SL3S4001FHK v. 1.0 20110609 Objective data sheet - - SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 28 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 29 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 30 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 20. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Mechanical properties XQFN8 . . . . . . . . . . . . . .6 Table 4. UCODE I2C memory sections . . . . . . . . . . . . . .8 Table 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 6. UCODE I2C TID description . . . . . . . . . . . . . . .10 Table 7. Interrupt signaling via the I2C-SCL line timing .12 Table 8. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (1 RF front end version SL3S4011) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 9. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (2 RF front end version SL3S4021) . . . . . . . . . . . . . . . . . . . . . 13 Table 10. ChangeConfig custom command. . . . . . . . . . . 15 Table 11. ChangeConfig custom response table. . . . . . . 15 Table 12. Memory banks locking possibilities for UCODE I2C via RF and I2C . . . . . . . . . . . . . . . 16 Table 13. Lock payload and usage . . . . . . . . . . . . . . . . . 16 Table 14. Device select code. . . . . . . . . . . . . . . . . . . . . . 19 Table 15. I2C addressing . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 16. Limiting values[1][2] [3][4] . . . . . . . . . . . . . . . . . . 23 Table 17. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 18. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 19. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 21. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. UCODE I2C TID memory structure . . . . . . . . . . .10 Fig 4. SCL interrupt signalling . . . . . . . . . . . . . . . . . . . .12 Fig 5. I2C memory bank lock write and read access . . .17 Fig 6. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .18 Fig 7. I2C write operation . . . . . . . . . . . . . . . . . . . . . . . .20 Fig 8. I2C read operation . . . . . . . . . . . . . . . . . . . . . . . .21 Fig 9. Package outline SOT902-3 . . . . . . . . . . . . . . . . .25 NXP Semiconductors SL3S4011_4021 UCODE I²C © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 July 2013 204931 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 UHF interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Mechanical specification . . . . . . . . . . . . . . . . . 6 7.1 SOT902 specification . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Air interface standards . . . . . . . . . . . . . . . . . . . 6 8.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 Data transfer air interface . . . . . . . . . . . . . . . . . 6 8.3.1 Interrogator to tag Link . . . . . . . . . . . . . . . . . . . 6 8.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . . 6 8.4 Data transfer to I2C interface . . . . . . . . . . . . . . 7 8.5 Supported commands . . . . . . . . . . . . . . . . . . . 7 8.6 UCODE I2C memory. . . . . . . . . . . . . . . . . . . . . 7 8.6.1 UCODE I2C overall memory map. . . . . . . . . . . 9 8.6.2 UCODE I2C TID memory details . . . . . . . . . . 10 9 Supported features . . . . . . . . . . . . . . . . . . . . . 11 9.1 UCODE I2C special feature . . . . . . . . . . . . . . 11 9.2 UCODE I2C special features control mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.3 Change Config Command . . . . . . . . . . . . . . . 15 9.4 UCODE I2C memory bank locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.1 Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.2 Via RF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.3 Via I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 I2C commands . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.1 UCODE I2C operation. . . . . . . . . . . . . . . . . . . 18 10.2 Start condition. . . . . . . . . . . . . . . . . . . . . . . . . 18 10.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . 19 10.5 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.7 Write Operation. . . . . . . . . . . . . . . . . . . . . . . . 20 10.7.1 Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.7.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.8 Read operation . . . . . . . . . . . . . . . . . . . . . . . 21 10.8.1 Random Address Read . . . . . . . . . . . . . . . . . 22 10.8.2 Current Address Read . . . . . . . . . . . . . . . . . . 22 10.8.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . 22 10.8.4 Acknowledge in Read mode . . . . . . . . . . . . . 22 10.8.5 EPC memory bank handling . . . . . . . . . . . . . 22 11 RF interface/I2C interface arbitration. . . . . . . 23 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 25 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 27 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 28 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 19 Contact information . . . . . . . . . . . . . . . . . . . . 29 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1. General description NXP’s UCODE G2iL series transponder ICs offer leading-edge read range and support industry-first features such as a Tag Tamper Alarm, Data Transfer, Digital Switch, and advanced privacy-protection modes. Very high chip sensitivity (18 dBm) enables longer read ranges with simple, single-port antenna designs. When connected to a power supply, the READ as well as the WRITE range can be boosted to a sensitivity of 27 dBm. In fashion and retail the UCODE G2iL series improve read rates and provide for theft deterrence. For consumer electronics the UCODE G2iL series is suited for device configuration, activation, production control, and PCB tagging. In authentication applications the transponders can be used to protect brands and guard against counterfeiting. They can also be used to tag containers, electronic vehicles, airline baggage, and more. In addition to the EPC specifications the G2iL offers an integrated Product Status Flag (PSF) feature and read protection of the memory content. On top of the G2iL features the G2iL+ offers an integrated tag tamper alarm, RF field detection, digital switch, external supply mode, read range reduction and data transfer mode. 2. Features and benefits 2.1 Key features  UHF RFID Gen2 tag chip according EPCglobal v1.2.0 with 128 bit EPC memory  Memory read protection  Integrated Product Status Flag (PSF)  Tag tamper alarm  RF field detection  Digital switch  Data transfer mode  Real Read Range Reduction (Privacy Mode)  External supply mode where both the READ & WRITE range are boosted to -27dBm 2.1.1 Memory  128-bit of EPC memory  64-bit Tag IDentifier (TID) including 32-bit factory locked unique serial number  32-bit kill password to permanently disable the tag  32-bit access password to allow a transition into the secured state SL3S1203_1213 UCODE G2iL and G2iL+ Rev. 4.4 — 17 March 2014 178844 Product data sheet COMPANY PUBLIC SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 2 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+  Data retention: 20 years  Broad international operating frequency: from 840 MHz to 960 MHz  Long read/write ranges due to extremely low power design  Reliable operation of multiple tags due to advanced anti-collision  READ protection  WRITE Lock  Wide specified temperature range: 40 C up to +85 C 2.2 Key benefits 2.2.1 End user benefit  Prevention of unauthorized memory access through read protection  Indication of tag tampering attempt by use of the tag tamper alarm feature  Electronic device configuration and / or activation by the use of the digital switch / data transfer mode  Theft deterrence supported by the PSF feature (PSF alarm or EPC code)  Small label sizes, long read ranges due to high chip sensitivity  Product identification through unalterable extended TID range, including a 32-bit serial number  Reliable operation in dense reader and noisy environments through high interference suppression 2.2.2 Antenna design benefits  High sensitivity enables small and cost efficient antenna designs  Low Q-Value eases broad band antenna design for global usage 2.2.3 Label manufacturer benefit  Consistent performance on different materials due to low Q-factor  Ease of assembly and high assembly yields through large chip input capacitance  Fast first WRITE of the EPC memory for fast label initialization 2.3 Custom commands  PSF Alarm Built-in PSF (Product Status Flag), enables the UHF RFID tag to be used as EAS tag (Electronic Article Surveillance) tag without the need for a back-end data base.  Read Protect Protects all memory content including CRC16 from unauthorized reading.  ChangeConfig Configures the additional features of the chip like external supply mode, tamper alarm, digital switch, read range reduction or data transfer. The UCODE G2iL is equipped with a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. No custom commands are needed to take advantage of all the features in case of unlocked EPC memory. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 3 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 3. Applications 3.1 Markets  Fashion (Apparel and footwear)  Retail  Electronics  Fast Moving Consumer Goods  Asset management  Electronic Vehicle Identification 3.2 Applications  Supply chain management  Item level tagging  Pallet and case tracking  Container identification  Product authentication  PCB tagging  Cost efficient, low level seals  Wireless firmware download  Wireless product activation Outside above mentioned applications, please contact NXP Semiconductors for support. 4. Ordering information 5. Marking Table 1. Ordering information Type number Package Name IC type Description Version SL3S1203FUF Wafer G2iL bumped die on sawn 8” 75 m wafer not applicable SL3S1213FUF Wafer G2iL+ bumped die on sawn 8” 75 m wafer not applicable SL3S1203FUD/BG Wafer G2iL bumped die on sawn 8” 120 m wafer, 7 m Polyimide spacer not applicable SL3S1213FUD/BG Wafer G2iL+ bumped die on sawn 8” 120 m wafer, 7 m Polyimide spacer not applicable SL3S1203FTB0 XSON6 G2iL plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886F1 Table 2. Marking codes Type number Marking code Comment Version SL3S1203FTB0 UN UCODE G2iL SOT886 SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 4 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 6. Block diagram The SL3S12x3 IC consists of three major blocks: - Analog Interface - Digital Control - EEPROM The analog part provides stable supply voltage and demodulates data received from the reader for being processed by the digital part. Further, the modulation transistor of the analog part transmits data back to the reader. The digital section includes the state machines, processes the protocol and handles communication with the EEPROM, which contains the EPC and the user data. Fig 1. Block diagram of G2iL IC 001aam226 MOD DEMOD VREG VDD VDD data in data out R/W ANALOG RF INTERFACE PAD PAD RECT DIGITAL CONTROL ANTENNA ANTICOLLISION READ/WRITE CONTROL ACCESS CONTROL EEPROM INTERFACE CONTROL RF INTERFACE CONTROL I/O CONTROL I/O CONTROL EEPROM MEMORY SEQUENCER CHARGE PUMP PAD OUT PAD SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 5 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 7. Pinning information 7.1 Pin description Fig 2. Pinning bare die Fig 3. Pin configuration for SOT886 001aam529 VDD OUT RFN NXP trademark RFP SL3S12x3FTB0 n.c. 001aan103 RFP RFN n.c. VDD OUT Transparent top view 2 3 1 5 4 6 Table 3. Pin description bare die Symbol Description OUT output pin RFN grounded antenna connector VDD external supply RFP ungrounded antenna connector Table 4. Pin description SOT886 Pin Symbol Description 1 RFP ungrounded antenna connector 2 n.c. not connected 3 RFN grounded antenna connector 4 OUT output pin 5 n.c. not connected 6 VDD external supply SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 6 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 8. Wafer layout 8.1 Wafer layout (1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m) (2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m) (3) Chip step, x-length: 485 m (4) Chip step, y-length: 435 m (5) Bump to bump distance X (OUT - RFN): 383 m (6) Bump to bump distance Y (RFN - RFP): 333 m (7) Distance bump to metal sealring X: 40,3 m (outer edge - top metal) (8) Distance bump to metal sealring Y: 40,3 m Bump size X x Y: 60 m x 60 m Remark: OUT and VDD are used with G2iL+ only Fig 4. G2iL wafer layout not to scale! 001aak871 (1) (7) (2) (8) (5) (6) (4) (3) Y X VDD OUT RFN RFP SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 7 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 9. Mechanical specification The UCODE G2iL/G2iL+ wafers are available in 75 m and 120 m thickness. The 75m thick wafer allows ultra thin label design but require a proper tuning of the glue dispenser during production. Because of the more robust structure of the 120m wafer, the wafer is ideal for harsh applications. The 120 m thick wafer is also enhanced with 7m Polyimide spacer allowing additional protection of the active circuit. 9.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**”. 9.1.1 Wafer Table 5. Specifications Wafer Designation each wafer is scribed with batch number and wafer number Diameter 200 mm (8”) Thickness SL3S12x3FUF 75 m  15 m SL3S12x3FUD 120 m  15 m Number of pads 4 Pad location non diagonal/ placed in chip corners Distance pad to pad RFN-RFP 333.0 m Distance pad to pad OUT-RFN 383.0 m Process CMOS 0.14 m Batch size 25 wafers Potential good dies per wafer 139.351 Wafer backside Material Si Treatment ground and stress release Roughness Ra max. 0.5 m, Rt max. 5 m Chip dimensions Die size including scribe 0.485 mm  0.435 mm = 0.211 mm2 Scribe line width: x-dimension = 15 m y-dimension = 15 m Passivation on front Type Sandwich structure Material PE-Nitride (on top) Thickness 1.75 m total thickness of passivation Polyimide spacer 7 m  1 m (SL3S12x3FUD only) Au bump Bump material > 99.9 % pure Au SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 8 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer. 9.1.2 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 9.1.3 Map file distribution See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 10. Functional description 10.1 Air interface standards The UCODE G2iL fully supports all parts of the "Specification for RFID Air Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 10.2 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE G2iL. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the G2iL on the tag. The G2iL+ can also be supplied externally. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. Bump hardness 35 – 80 HV 0.005 Bump shear strength > 70 MPa Bump height SL3S12x3FUF 18 m SL3S12x3FUD 25 m[1] Bump height uniformity within a die  2 m – within a wafer  3 m – wafer to wafer  4 m Bump flatness  1.5 m Bump size – RFP, RFN 60  60 m – OUT, VDD 60  60 m Bump size variation  5 m Table 5. Specifications SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 9 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The antenna that is attached to the chip may use a DC connection between the two antenna pads. Therefore the G2iL also enables loop antenna design. Possible examples of supported antenna structures can be found in the reference antenna design guide. 10.3 Data transfer 10.3.1 Reader to tag Link An interrogator transmits information to the UCODE G2iL by modulating an UHF RF signal. The G2iL receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. In order to further improve the read range the UCODE G2iL+ can be externally supplied as well so the energy to operate the chip does not need to be transmitted by the reader. An interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. It communicates to the G2iL by modulating an RF carrier using DSB-ASK with PIE encoding. For further details refer to Section 16, Ref. 1. Interrogator-to-tag (R=>T) communications. 10.3.2 Tag to reader Link An interrogator receives information from a G2iL by transmitting an unmodulated RF carrier and listening for a backscattered reply. The G2iL backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. For further details refer to Section 16, Ref. 1, chapter 6.3.1.3. The UCODE G2iL communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subcarrier. 10.4 G2iL and G2iL+ differences The UCODE G2iL is tailored for application where mainly EPC or TID number space is needed. The G2iL+ in addition provides functionality such as tag tamper alarm, external supply operation to further boost read/write range (external supply mode), a Privacy mode reducing the read range or I/O functionality (data transfer to externally connected devices) required. The following table provides an overview of G2iL, G2iL+ special features. Table 6. Overview of G2iL and G2iL+ features Features G2iL G2iL+ Read protection (bankwise) yes yes PSF (Built-in Product Status Flag) yes yes Backscatter strength reduction yes yes Real read range reduction yes yes Digital switch / Digital input - yes External supply mode - yes SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 10 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.5 Supported commands The G2iL supports all mandatory EPCglobal V1.2.0 commands. In addition the G2iL supports the following optional commands: • ACCESS • Block Write (32 bit) The G2iL features the following custom commands described more in detail later: • ResetReadProtect (backward compatible to G2X) • ReadProtect (backward compatible to G2X) • ChangeEAS (backward compatible to G2X) • EAS_Alarm (backward compatible to G2X) • ChangeConfig (new with G2iL) 10.6 G2iL, G2iL+ memory The G2iL, G2iL+ memory is implemented according EPCglobal Class1Gen2 and organized in three sections: The logical address of all memory banks begin at zero (00h). In addition to the three memory banks one configuration word to handle the G2iL specific features is available at EPC bank 01 address 200h. The configuration word is described in detail in Section 10.7.1 “ChangeConfig”. Memory pages (16 bit words) pre-programmed to zero will not execute an erase cycle before writing data to it. This approach accelerates initialization of the chip and enables faster programming of the memory. RF field detection - yes Data transfer - yes Tag tamper alarm - yes Table 6. Overview of G2iL and G2iL+ features …continued Features G2iL G2iL+ Table 7. G2iL memory sections Name Size Bank Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16 bit PC) 128 bit 01b G2iL Configuration Word 16 bit 01b TID (including permalocked unique 32 bit serial number) 64 bit 10b SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 11 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.6.1 G2iL, G2iL+ overall memory map [1] See Figure 5 [2] Indicates the existence of a Configuration Word at the end of the EPC number [3] See also Table 12 for further details. Table 8. G2iL, G2iL+ overall memory map Bank address Memory address Type Content Initial Remark Bank 00 00h to 1Fh reserved kill password all 00h unlocked memory 20h to 3Fh reserved access password all 00h unlocked memory Bank 01 EPC 00h to 0Fh EPC CRC-16: refer to Ref. 16 memory mapped calculated CRC 10h to 14h EPC backscatter length 00110b unlocked memory 15h EPC UMI 0b unlocked memory 16h EPC XPC indicator 0b hardwired to 0 17h to 1Fh EPC numbering system indicator 00h unlocked memory 20h to 9Fh EPC EPC [1] unlocked memory Bank 01 Config Word 200h EPC tamper alarm flag 0b[3] indicator bit 201h EPC external supply flag or input signal 0b[3] indicator bit 202h EPC RFU 0b[3] locked memory 203h EPC RFU 0b[3] locked memory 204h EPC invert digital output: 0b[3] temporary bit 205h EPC transparent mode on/off 0b[3] temporary bit 206h EPC transparent mode data/raw 0b[3] temporary bit 207h EPC RFU 0b[3] locked memory 208h EPC RFU 0b[3] locked memory 209h EPC max. backscatter strength 1b[3] unlocked memory 20Ah EPC digital output 0b[3] unlocked memory 20Bh EPC read range reduction on/off 0b[3] unlocked memory 20Ch EPC RFU 0b[3] locked memory 20Dh EPC read protect EPC Bank 0b[3] unlocked memory 20Eh EPC read protect TID 0b[3] unlocked memory 20Fh EPC PSF alarm flag 0b[3] unlocked memory Bank 10 TID 00h to 07h TID allocation class identifier 1110 0010b locked memory 08h to 13h TID tag mask designer identifier 0000 0000 0110b locked memory 14h TID config word indicator 1b[2] locked memory 14h to 1Fh TID tag model number TMNR[1] locked memory 20h to 3Fh TID serial number SNR locked memory xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 12 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.6.2 G2iL TID memory details Fig 5. G2iL TID memory structure aaa-010217 E2006906 E2h 006h 1 0010b 0000110b Ucode G2iL+ E2006807 E2h 006h 1 0000b 0000111b E2006907 E2h 006h 1 0010b 0000111b Ucode G2iL E2006806 E2h 006h 1 0000b 0000110b First 32 bit of TID memory Class ID Mask Designer ID Config Word Indicator Sub Version Nr. Model Number Version (Silicon) Nr. Class Identifier MS Byte MS Bit LS Bit LS Byte TID MS Bit LS Bit Mask-Designer Identifier Model Number Serial Number Bits 7 0 11 0 11 0 31 0 Addresses 00h 07h 13h 1Fh 3Fh Addresses 00h 3Fh 08h 14h 20h E2h (EAN.UCC) 006h (NXP) 806h or 906h or B06h (UCODE G2iL) 00000001h to FFFFFFFFh Sub Version Number Version Number 000b or 001b or 0110b 0000110b (UCODE G2iL) Bits 0 3 0 6 0 Addresses 14h 18h 19h 1Fh E2006B06 E2h 006h 1 0110b 0000110b E2006B07 E2h 006h 1 0110b 0000111b SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 13 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.7 Custom commands The UCODE G2iL, G2iL+ is equipped with a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. The memory map stated in the previous section describes the Configuration Word used to control the additional features located at address 200h of the EPC memory. For this reason the standard READ/WRITE commands of an UHF EPCglobal compliant reader can be used to select the flags or activate/deactivate features. The features can only be activated/deactivated (written) using standard EPC WRITE command as long the EPC is not locked. In case the EPC is locked either the bank needs to be unlocked to apply changes or the ChangeConfig custom command is used to change the settings. The UCODE G2iL is also equipped with the complete UCODE G2X command set for backward compatibility reasons. Nevertheless, the one ChangeConfig command of the G2iL can be used instead of the entire G2X command set. Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable selecting Config-Word enhanced transponders in mixed tag populations. 10.7.1 ChangeConfig Although G2iL is tailored for supply chain management, item level tagging and product authentication the G2iL+ version enables active interaction with products. Among the password protected features are the capability of download firmware to electronics, activate/deactivate electronics which can also be used as theft deterrence, a dedicated privacy mode by reducing the read range, integrated PSF (Product Status Flag) or Tag Tamper Alarm. The G2iL ChangeConfig custom command allows handling the special NXP Semiconductors features described in the following paragraph. Please also see the memory map in Section 10.6 “G2iL, G2iL+ memory” and “Section 10.7.2 “G2iL, G2iL+ special features control mechanism”. If the EPC memory is not write locked the standard EPC READ/WRITE command can be used to change the settings. G2iL, G2iL+ special features1 UCODE G2iL and G2iL+ common special features are: • Bank wise read protection (separate for EPC and TID) EPC bank and the serial number part of the TID can be read protected independently. When protected reading of the particular memory will return '0'. The flags of the configuration word can be selected using the standard SELECT2 command. Only read protected parts will then participate an inventory round. The G2X ReadProtect command will set both EPC and TID read protect flags. 1. The features can only be manipulated (enabled/disabled) with unlocked EPC bank, otherwise the ChangeConfig command can be used. 2. SELECT has to be applied onto the Configuration Word with pointer address 200h. Selecting bits within the Configuration Word using a pointer address not equal to 200h is not possible. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 14 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • Integrated PSF (Product Status Flag) The PSF is a general purpose flag that can be used as an EAS (Electronic Article Surveillance) flag, quality checked flag or similar. The G2iL offers two ways of detecting an activated PSF. In cases extremely fast detection is needed the EAS_Alarm command can be used. The UCODE G2iL will reply a 64-bit alarm code like described in section EAS_Alarm upon sending the command. As a second option the EPC SELECT2 command selecting the PSF flag of the configuration word can be used. In the following inventory round only PSF enabled chips will reply their EPC number. • Backscatter strength reduction The UCODE G2iL features two levels of backscatter strengths. Per default maximum backscatter is enabled in order to enable maximum read rates. When clearing the flag the strength can be reduced if needed. • Real Read Range Reduction 4R Some applications require the reduction of the read range to close proximity for privacy reasons. Setting the 4R flag will significantly reduce the chip sensitivity to +12 dBm. The +12 dBm have to be available at chip start up (slow increase of field strength is not applicable). For additional privacy, the read protection can be activated in the same configuration step. The related flag of the configuration word can be selected using the standard SELECT2 command so only chips with reduced read range will be part of an inventory. Remark: The attenuation will result in only a few centimeter of read range at 36 dBm EIRP! UCODE G2iL+ specific special features are:1 • Tag Tamper Alarm (G2iL+ only) The UCODE G2iL+ Tamper Alarm will flag the status of the VDD to OUT pad connection which can be designed as an predetermined breaking point (see Figure 6). The status of the pad connection (open/closed) can be read in the configuration register and/or selected using the EPC SELECT2. This feature will enable designing a wireless RFID safety seal. When breaking the connection by peeling off the label or manipulating a lock an alarm can be triggered. Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal 001aam228 OUT VDD GND RFP SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 15 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • RF field detection (G2iL+ only) The UCODE G2iL+ VDD pin can be also used as a RF field detector. Upon bringing the tag within an RF field, a pulse signal will be immediately sent from the VDD test pad. (for details see Ref. 21). • Digital Switch (G2iL+ only) The UCODE G2iL+ OUT pin can be used as digital switch. The state of the output pad can be switched to VDD or GND depending on the Digital OUT bit of the Configuration Word register. The state of the output is persistent in the memory even after KILL or switching off the supply. This feature will allow activating/deactivating externally connected peripherals or can be used as theft deterrence of electronics. The state of the OUT pin can also be changed temporary by toggling the 'Invert Digital Output' bit. • Data transfer Mode (G2iL+ only) In applications where not switching the output like described in "Digital Switch" but external device communication is needed the G2iL+ Data Transfer Mode can be used by setting the according bit of the Configuration Word register. When activated the air interface communication will be directly transferred to the OUT pad of the chip. Two modes of data transfer are available and can be switched using the Transparent Mode DATA/RAW bit. The default Transparent Mode DATA will remove the Frame Sync of the communication and toggle the output with every raising edge in the RF field. This will allow implementing a Manchester type of data transmission. The Transparent Mode RAW will switch the demodulated air interface communication to the OUT pad. • External Supply Indicator - Digital Input (G2iL+ only) The VDD pad of the UCODE G2iL+ can be used as a single bit digital input pin. The state of the pad is directly associated with the External Supply Indicator bit of the configuration register. Simple one bit return signaling (chip to reader) can be implemented by polling this Configuration Word register flag. RF reset is necessary for proper polling. • External Supply Mode (G2iL+ only) The UCODE G2iL+ can be supplied externally by connecting 1.85 V (Iout = 0μA) supply. When externally supplied less energy from the RF field is needed to operate the chip. This will not just enable further improved sensitivity and read ranges (up to 27 dBm) but also enable a write range that is equal to the read range. The figure schematically shows the supply connected to the UCODE G2iL+. Remark: When permanently externally supplied there will not be a power-on-reset. This will result in the following limitations: • When externally supplied session flag S0 will keep it’s state during RF-OFF phase. • When externally supplied session flag S2, S3, SL will have infinite persistence time and will behave similar to S0. • Session flag S1 will behave regular like in pure passive operation. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 16 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The bits to be toggled in the configuration register need to be set to '1'. E.g. sending 0000 0000 0001 0001 XOR RN16 will activate the 4R and PSF. Sending the very same command a second time will disable the features again. The reply of the ChangeConfig will return the current register setting. Fig 7. Schematic of external power supply Table 9. ChangeConfig custom command Command RFU Data RN CRC-16 No. of bits 16 8 16 16 16 Description 11100000 00000111 00000000 Toggle bits XOR RN 16 handle - Table 10. ChangeConfig custom command reply Header Status bits RN CRC-16 No. of bits 1 16 16 16 Description 0 Config-Word Handle - Table 11. ChangeConfig command-response table Starting state Condition Response Next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle Status word needs to change Backscatter unchanged Config-WordConfig-Word immediately open valid handle Status word does not need to change Backscatter Config-Word immediately open secured valid handle Status word needs to change Backscatter modified Config-Word, when done secured valid handle Status word does not need to change Backscatter Config-Word immediately secured killed all - killed 001aam229 OUT VDD Vsupply GND RFP SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 17 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The features can only be activated/deactivated using standard EPC WRITE if the EPC bank is unlocked. The permanent and temporary bits of the Configuration Word can be toggled without the need for an ACCESS password in case the ACCESS password is set to zero. In case the EPC bank is locked the lock needs to be removed before applying changes or the ChangeConfig command has to be used. 10.7.2 G2iL, G2iL+ special features control mechanism Special features of the G2iL are managed using a configuration word (Config-Word) located at address 200h in the EPC memory bank. The entire Config-Word is selectable (using the standard EPC SELECT2 command) and can be read using standard EPC READ command and modified using the standard EPC WRITE or ChangeConfig custom command in case the EPC memory is locked for writing. ChangeConfig can be executed from the OPEN and SECURED state. The chip will take all “Toggle Bits” for ’0’ if the chip is in the OPEN state or the ACCESS password is zero; therefore it will not alter any status bits, but report the current status only. The command will be ignored with an invalid CRC-16 or an invalid handle. The chip will then remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A ChangeConfig command without frame-sync and proceeding Req_RN will be ignored. The command will also be ignored if any of the RFU bits are toggled. In order to change the configuration, to activate/deactivate a feature a ’1’ has to be written to the corresponding register flag to toggle the status. E.g. sending 0x0002 to the register will activate the read protection of the TID. Sending the same command a second time will again clear the read protection of the TID. Invalid toggling on indicator or RFU bits are ignored. Executing the command with zero as payload or in the OPEN state will return the current register settings. The chip will reply to a successful ChangeConfig with an extended preamble regardless of the TRext value of the Query command. After sending a ChangeConfig an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeConfig command and the chip’s backscattered reply. An interrogator may observe three possible responses after sending a ChangeConfig, depending on the success or failure of the operation • ChangeConfigChangeConfig succeeded: The chip will backscatter the reply shown above comprising a header (a 0-bit), the current Status Word setting, the handle, and a CRC-16 calculated over the 0-bit, the status word and the handle. If the interrogator observes this reply within 20 ms then the ChangeConfig completed successfully. • The chip encounters an error: The chip will backscatter an error code during the CW period rather than the reply shown below (see EPCglobal Spec for error-code definitions and for the reply format). • ChangeConfig does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeStatus did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the chip is still in the interrogator's field, and may reissue the ChangeConfig command. The G2iL configuration word is located at address 200h of the EPC memory and is structured as following: SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 18 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The configuration word contains three different type of bits: • Indicator bits cannot be changed by command: Tag Tamper Alarm Indicator External Supply Indicator (digital input) • Temporary bits are reset at power up: Invert Output Transparent Mode on/off Data Mode data/raw • Permanent bits: permanently stored bits in the memory Max. Backscatter Strength Digital Output Read Range Reduction Read Protect EPC Read Protect TID PSF Alarm 10.7.3 ReadProtect3 The G2iL ReadProtect custom command enables reliable read protection of the entire G2iL memory. Executing ReadProtect from the Secured state will set the ProtectEPC and ProtectTID bits of the Configuration Word to '1'. With the ReadProtect-Bit set the G2iL will continue to work unaffected but veil its protected content. The read protection can be removed by executing Reset ReadProtect. The ReadProtect-Bits will than be cleared. Devices whose access password is zero will ignore the command. A frame-sync must be pre-pended the command. After sending the ReadProtect command an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect command and the backscattered reply. An interrogator may observe three possible responses after sending a ReadProtect, depending on the success or failure of the operation: Table 12. Address 200h to 207h Indicator bits Temporary bits Tamper indicator External supply indicator RFU RFU Invert Output Transparent mode on/off Data mode data/raw RFU 0 1 2 3 4 5 6 7 Table 13. Address 208h to 20Fh Permanent bits RFU max. backscatter strength Digital output Privacy mode RFU Protect EPC Protect TID PSF Alarm bit 8 9 10 11 12 13 14 15 3. Note: The ChangeConfig command can be used instead of “ReadProtect”, “ResetReadProtect”, “ChangeEAS”. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 19 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • ReadProtect succeeds: After completing the ReadProtect the G2iL shall backscatter the reply shown in Table 15 comprising a header (a 0-bit), the tag's handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this reply the G2iL will render itself to this ReadProtect mode. If the interrogator observes this reply within 20 ms then the ReadProtect completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code definitions and for the reply format). • ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogation zone, and may re-initiate the ReadProtect command. The G2iL reply to the ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. 10.7.4 Reset ReadProtect3 Reset ReadProtect allows an interrogator to clear the ProtectEPC and ProtectTID bits of the Configuration Word. This will re-enable reading of the related G2iL memory content. For details on the command response please refer to Table 17 “Reset ReadProtect command”. Table 14. ReadProtect command Command RN CRC-16 # of bits 16 16 16 description 11100000 00000001 handle - Table 15. G2iL reply to a successful ReadProtect procedure Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 16. ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all - open secured valid handle & invalid access password – arbitrate valid handle & valid non zero access password Backscatter handle, when done secured invalid handle – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 20 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect command and the G2iL backscattered reply. A Req_RN command prior to the Reset ReadProtect is necessary to successfully execute the command. A frame-sync must be pre-pended the command. An interrogator may observe three possible responses after sending a Reset ReadProtect, depending on the success or failure of the operation: • Reset ReadProtect succeeds: After completing the Reset ReadProtect a G2iL will backscatter the reply shown in Table 18 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the Reset ReadProtect completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in Table 18 (see EPCglobal Spec for error-code definitions and for the reply format). • Reset ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the Reset ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogation zone, and may reissue the Reset ReadProtect command. The G2iL reply to the Reset ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a G2iL will reply as if TRext=1 regardless of the TRext value in the Query that initiated the round. The Reset ReadProtect command is structured as following: • 16 bit command • Password: 32 bit Access-Password XOR with 2 times current RN16 Remark: To generate the 32 bit password the 16 bit RN16 is duplicated and used two times to generate the 32 bit (e.g. a RN16 of 1234 will result in 1234 1234). • 16 bit handle • CRC-16 calculate over the first command-code bit to the last handle bit Table 17. Reset ReadProtect command Command Password RN CRC-16 # of bits 16 32 16 16 description 11100000 00000010 (access password)  2*RN16 handle - Table 18. G2iL reply to a successful Reset ReadProtect command Header RN CRC-16 # of bits 1 16 16 description 0 handle - SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 21 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.7.5 ChangeEAS3 UCODE G2iL equipped RFID tags will also feature a stand-alone operating EAS alarm mechanism for fast and offline electronic article surveillance. The PSF bit of the Configuration Word directly relates to the EAS Alarm feature. With an PSF bit set to '1' the tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the need of a Select or Query. The EAS is a built-in solution so no connection to a backend database is required. In case the EAS_Alarm command is not implemented in the reader a standard EPC SELCET to the Configuration Word and Query can be used. When using standard SELECT/QUERY the EPC will be returned during inventory. ChangeEAS can be executed from the Secured state only. The command will be ignored if the Access Password is zero, the command will also be ignored with an invalid CRC-16 or an invalid handle, the G2iL will than remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A frame-sync must be pre-pended the command. The G2iL reply to a successful ChangeEAS will use the extended preamble, as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeEAS command and the G2iL backscattered reply. An interrogator may observe three possible responses after sending a ChangeEAS, depending on the success or failure of the operation • ChangeEAS succeeds: After completing the ChangeEAS a G2iL will backscatter the reply shown in Table 21 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the ChangeEAS completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in Table 21 (see EPCglobal Spec for error-code definitions and for the reply format). Table 19. Reset ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open valid handle & valid access password Backscatter handle, when done open valid handle & invalid access password – arbitrate invalid handle – open secured valid handle & valid access password Backscatter handle, when done secured valid handle & invalid access password – arbitrate invalid handle – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 22 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • ChangeEAS does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeEAS did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogator's field, and may reissue the ChangeEAS command. Upon receiving a valid ChangeEAS command a G2iL will perform the commanded set/reset operation of the PSF bit of the Configuration Word. If PSF bit is set, the EAS_Alarm command will be available after the next power up and reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be ignored. 10.7.6 EAS_Alarm Upon receiving an EAS_Alarm custom command the UCODE G2iL will immediately backscatter an EAS-Alarmcode in case the PSF bit of the Configuration Word is set. The alarm code is returned without any delay caused by Select, Query and without the need for a backend database. The EAS feature of the G2iL is available after enabling it by sending a ChangeEAS command described in Section 10.7.5 “ChangeEAS3” or after setting the PSF bit of the Configuration Word to ’1’. With the EAS-Alarm enabled the G2iL will reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A G2iL will reply to an EAS_Alarm command from the ready state only. As an alternative to the fast EAS_Alarm command a standard SELECT2 (upon the Configuration Word) and QUERY can be used. If the PSF bit is reset to '0' by sending a ChangeEAS command in the password protected Secure state or clearing the PSF bit the G2iL will not reply to an EAS_Alarm command. Table 20. ChangeEAS command Command ChangeEAS RN CRC-16 # of bits 16 1 16 16 description 11100000 00000011 1 ... set PSF bit 0 ... reset PSF bit handle Table 21. G2iL reply to a successful ChangeEAS command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 22. ChangeEAS command-response table Starting State Condition Response Next state ready all – ready arbitrate, reply, acknowledged all – arbitrate open all – open secured valid handle backscatter handle, when done secured invalid handle – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 23 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The EAS_Alarm command is structured as following: • 16 bit command • 16 bit inverted command • DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec. 6.3.1.2.8 and Table 6.9. • M (cycles per symbol) sets the T=>R data rate and modulation format as shown in EPCglobal Spec. Table 6.10. • TRext chooses whether the T=>R preamble is pre-pended with a pilot tone as described in EPCglobal Spec. 6.3.1.3. A preamble must be pre-pended the EAS_Alarm command according EPCglobal Spec, 6.3.1.2.8. Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate the CRC5 over the backscattered 64 bits received to verify the received code. Table 23. EAS_Alarm command Command Inv_Command DR M TRext CRC-16 # of bits 16 16 1 2 1 16 description 11100000 00000100 00011111 11111011 0: DR = 8 1: DR = 64/3 00: M = 1 01: M = 2 10: M = 4 11: M = 8 0: no pilot tone 1: use pilot tone - Table 24. G2iL reply to a successful EAS_Alarm command Header EAS Code # of bits 1 64 description 0 CRC5 (MSB) Table 25. EAS_Alarm command-response table Starting State Condition Response Next state ready PSF bit is set PSF bit is cleard backscatter alarm code -- ready arbitrate, reply, acknowledged all – arbitrate open all – open secured all – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 24 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 11. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP20 package. Table 26. Limiting values[1][2] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to RFN Symbol Parameter Conditions Min Max Unit Bare die and SOT886 limitations Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage Human body model [3] - 2 kV Pad limitations Vi input voltage absolute limits, VDD-OUT pad 0.5 +2.5 V Io output current absolute limits input/output current, VDD-OUT pad 0.5 +0.5 mA Pi input power maximum power dissipation, RFP pad - 100 mW SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 25 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 12. Characteristics 12.1 UCODE G2iL, G2iL+ bare die characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. [4] It has to be assured the reader (system) is capable of providing enough field strength to give +12 dBm at the chip otherwise communication with the chip will not be possible. [5] Enables tag designs to be within ETSI limits for return link data rates of e.g. 320 kHz/M4. [6] Will result in up to 10 dB higher tag backscatter power at high field strength. [7] Results in approx. 18.5 dBm tag sensitivity on a 2 dBi gain antenna. Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit fi input frequency 840 - 960 MHz Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2][7] - 18 - dBm Pi(min) minimum input power WRITE sensitivity, (write range/read range - ratio) - 30 - % Ci input capacitance parallel [3] - 0.77 - pF Q quality factor 915 MHz [3] - 9.7 - - Z impedance 866 MHz [3] - 25 -j237 -  915 MHz [3] - 23 -j224 -  953 MHz [3] - 21 -j216 -  External supply mode - VDD pad supplied, read range reduction OFF Pi(min) minimum input power Ext. supplied READ [1][2] - 27 - dBm Ext. supplied WRITE [2] - 27 - dBm Z impedance externally supplied, 915 MHz [3] - 7 -j230 -  Read range reduction ON - no external supply Pi(min) minimum input power 4R on READ [1][2][4] - +12 - dBm 4R on WRITE [2][4] - +12 - dBm Z impedance 4R on, 915 MHz [3] - 18 -j2 -  Modulation resistance R resistance modulation resistance, max. backscatter = off [5] - 170 -  modulation resistance, max. backscatter = on [6] - 55 -  SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 26 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [1] Activates Digital Output (OUT pin), increases read range (external supplied). [2] Activates Digital Output (OUT pin), increases read and write range (external supplied). [3] Operating the chip outside the specified voltage range may lead to undefined behaviour. [4] Either the voltage or the current needs to be above given values to guarantee specified functionality. [5] No proper operation is guaranteed if both, voltage and current, limits are exceeded. [1] Is the sum of the allowed capacitance of the VDD and OUT pin referenced to RFN. [2] Is the maximum allowed RF input voltage coupling to the VDD/OUT pin to guarantee undisturbed chip functionality. [3] Resistance between VDD and OUT pin in checked during power up only. [4] Resistance range to achieve tamper alarm flag = 1. [5] Resistance range to achieve tamper alarm flag = 0: Table 28. VDD pin characteristics Symbol Parameter Conditions Min Typ Max Unit Minimum supply voltage/current - without assisted EEPROM WRITE [1][3][4] VDD supply voltage minimum voltage - - 1.8 V IDD supply current minimum current, Iout-^- = 0 A - - 7 A Iout = 100 A - - 110 A Minimum supply voltage/current - assisted EEPROM READ and WRITE [2][3][4] VDD supply voltage minimum voltage, Iout = 0 A - 1.8 1.85 V Iout = 100 A - - 1.95 V IDD supply current minimum current, Iout = 0 A - - 125 A Iout = 100 A - - 265 A Maximum supply voltage/current [3][5] VDD supply voltage absolute maximum voltage 2.2 - - V Ii(max) maximum input current absolute maximum current 280 - - A Table 29. G2iL, G2iL+ VDD and OUT pin characteristics Symbol Parameter Conditions Min Typ Max Unit OUT pin characteristics VOL Low-level output voltage Isink = 1 mA - - 100 mV VOH HIGH-level output voltage VDD = 1.8 V; Isource = 100 μA 1.5 - - V VDD/OUT pin characteristics CL load capacitance VDD - OUT pin max. [1] - - 5 pF Vo output voltage maximum RF peak voltage on VDD-OUT pins [2] - - 500 mV VDD/OUT pin tamper alarm characteristics [3] RL(max) maximum load resistance resistance range high [4] - - <2 M RL(min) minimum load resistance resistance range low [5] >20 - - M SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 27 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ For further reading we recommend application note “FAQ UCODE G2iL+“ (Ref. 21) describing the output characteristics more in detail. An example schematic is available in application note “UCODE G2iL+ Demo board Manual“ (Ref. 22). The documents are available at NXP Document Control or at the website www.nxp.com. [1] Tamb 25 C 12.2 UCODE G2iL SOT886 characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. Remark: For DC and memory characteristics refer to Table 28, Table 29 and Table 30. Table 30. G2iL, G2iL+ memory characteristics Symbol Parameter Conditions Min Typ Max Unit EEPROM characteristics tret retention time Tamb 55 C 20 - - year Nendu(W) write endurance 1000 10000[1] - cycle Table 31. G2iL RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 17.6 - dB m Z impedance 915 MHz [3] - 21 j199 -  Normal mode - externally supplied, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 27 - dB m Z impedance 915 MHz [3] - 5.6 j204 -  SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 28 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 13. Package outline Fig 8. Package outline SOT886 Outline References version European projection Issue date IEC JEDEC JEITA SOT886 MO-252 sot886_po 04-07-22 12-01-05 Unit mm max nom min 0.5 0.04 1.50 1.45 1.40 1.05 1.00 0.95 0.35 0.30 0.27 0.40 0.35 0.32 0.6 A(1) Dimensions (mm are the original dimensions) Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 A1 b 0.25 0.20 0.17 D E e e1 0.5 L L1 terminal 1 index area D E e1 e A1 b L1 L e1 0 1 2 mm scale 1 6 2 5 3 4 6x (2) 4x (2) A SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 29 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 14. Packing information 14.1 Wafer See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 14.2 SOT886 Part orientation T1. For details please refer to http://www.standardics.nxp.com/packaging/packing/pdf/sot886.t1.t4.pdf 15. Abbreviations Table 32. Abbreviations Acronym Description CRC Cyclic Redundancy Check CW Continuous Wave DSB-ASK Double Side Band-Amplitude Shift Keying DC Direct Current EAS Electronic Article Surveillance EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bi phase space modulation G2 Generation 2 IC Integrated Circuit PIE Pulse Interval Encoding RRRR Real Read Range Reduction PSF Product Status Flag RF Radio Frequency UHF Ultra High Frequency SECS Semi Equipment Communication Standard TID Tag IDentifier SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 30 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 16. References [1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0 (December 17, 2005) [2] EPCglobal: EPC Tag Data Standards [3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft) [4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference (draft) [5] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 1 – Technical characteristics and test methods [6] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive [7] [CEPT1]: CEPT REC 70-03 Annex 1 [8] [ETSI1]: ETSI EN 330 220-1, 2 [9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1: Technical characteristics and test methods. [10] [FCC1]: FCC 47 Part 15 Section 247 [11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International Standards [12] ISO/IEC 3309: Information technology – Telecommunications and information exchange between systems – High-level data link control (HDLC) procedures – Frame structure [13] ISO/IEC 15961: Information technology, Automatic identification and data capture – Radio frequency identification (RFID) for item management – Data protocol: application interface [14] ISO/IEC 15962: Information technology, Automatic identification and data capture techniques – Radio frequency identification (RFID) for item management – Data protocol: data encoding rules and logical memory functions [15] ISO/IEC 15963: Information technology — Radio frequency identification for item management — Unique identification for RF tags [16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item management — Part 1: Reference architecture and definition of parameters to be standardized [17] ISO/IEC 18000-6: Information technology automatic identification and data capture techniques — Radio frequency identification for item management air interface — Part 6: Parameters for air interface communications at 860–960 MHz [18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary – Part 3: radio-frequency identification (RFID) SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 31 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15: Radio-frequency devices, U.S. Federal Communications Commission. [20] Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**4 [21] Application note - FAQ UCODE G2i, BU-ID document number: AN10940 [22] Application note - UCODE G2iM+ demo board documentation, BU-ID document number: AN11237 4. ** ... document version number SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 32 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 17. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3S1203_1213 v.4.4 20140317 Product data sheet - SL3S1203_1213 v.4.3 Modifications: • Table 8 “G2iL, G2iL+ overall memory map”: Table notes updated • Figure 5 “G2iL TID memory structure”: TIDs updated SL3S1203_1213 v.4.3 20131127 Product data sheet - SL3S1203_1213 v.4.2 Modifications: • Figure 5 “G2iL TID memory structure”: updated SL3S1203_1213 v.4.2 20130701 Product data sheet - SL3S1203_1213 v.4.1 Modifications: • Update of delivery form • Update RF field detection SL3S1203_1213 v.4.1 20120917 Product data sheet - SL3S1203_1213 v.4.0 Modifications: • Update of delivery form SL3S1203_1213 v.4.0 20120227 Product data sheet - SL3S1203_1213 v.3.9 Modifications: • Figure 4 “G2iL wafer layout”: Figure notes (1) and (2) updated SL3S1203_1213 v.3.9 20120130 Product data sheet - SL3S1203_1213 v.3.8 Modifications: • Table 6 “Specifications”: “Passivation on front” updated • Section 15.2.1 “General assembly recommendations”: updated SL3S1203_1213 v.3.8 20120111 Product data sheet - SL3S1203_1213 v.3.7 Modifications: • Section 8.1 “Wafer layout”: Figure notes (1) and (2) updated SL3S1203_1213 v.3.7 20111124 Product data sheet - SL3S1203_1213 v.3.6 Modifications: • Table 11 “G2iL, G2iL+ overall memory map”: updated • Table 34 “G2iL, G2iL+ RF interface characteristics (RFN, RFP)”: updated SL3S1203_1213 v.3.6 20110803 Product data sheet - SL3S1203_1213 v.3.5 Modifications: • Real Read Range Reduction feature added to G2iL SL3S1203_1213 v.3.5 20110531 Product data sheet - SL3S1203_1213 v.3.4 Modifications: • Superfluous text removed from Table 6 SL3S1203_1213 v.3.4 20110511 Product data sheet - SL3S1203_1213 v.3.3 Modifications: • Security status changed into COMPANY PUBLIC • Delivery form of FCS2 strap added • Section 13 “Package information”, Section 15 “Handling information” and Section 16 “Packing information” added SL3S1203_1213 v.3.3 20110131 Product data sheet - SL3S1203_1213 v.3.2 Modifications: • Section 4 “Ordering information”: new types SL3S1203FUD and SL3S1213FUD added • Section 9 “Mechanical specification”: updated according to the new types • Replaced wording of “ChangeStatus” with “ChangeConfig” SL3S1203_1213 v.3.2 20101109 Product data sheet - SL3S1203_1213 v.3.1 Modifications: • Version SOT886F1 added • Section 5 “Marking”, Section 13 “Package outline” and Section 14 “Packing information” added SL3S1203_1213 v.3.1 20100922 Product data sheet - SL3S1203_1213 v.3.0 Modifications: • General Modifications SL3S1203_1213 v.3.0 20100621 Product data sheet - 178810 SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 33 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ Modifications: • General update 178810 20100304 Objective data sheet - - Table 33. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 34 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 35 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 36 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 20. Tables Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description bare die . . . . . . . . . . . . . . . . . . .5 Table 4. Pin description SOT886 . . . . . . . . . . . . . . . . . . .5 Table 5. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 6. Overview of G2iL and G2iL+ features . . . . . . . .9 Table 7. G2iL memory sections . . . . . . . . . . . . . . . . . . .10 Table 8. G2iL, G2iL+ overall memory map. . . . . . . . . . . 11 Table 9. ChangeConfig custom command . . . . . . . . . . .16 Table 10. ChangeConfig custom command reply. . . . . . .16 Table 11. ChangeConfig command-response table . . . . .16 Table 12. Address 200h to 207h . . . . . . . . . . . . . . . . . . .18 Table 13. Address 208h to 20Fh . . . . . . . . . . . . . . . . . . .18 Table 14. ReadProtect command. . . . . . . . . . . . . . . . . . .19 Table 15. G2iL reply to a successful ReadProtect procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 16. ReadProtect command-response table . . . . . .19 Table 17. Reset ReadProtect command . . . . . . . . . . . . .20 Table 18. G2iL reply to a successful Reset ReadProtect command. . . . . . . . . . . . . . . . . . .20 Table 19. Reset ReadProtect command-response table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 20. ChangeEAS command . . . . . . . . . . . . . . . . . . 22 Table 21. G2iL reply to a successful ChangeEAS command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 22. ChangeEAS command-response table . . . . . . 22 Table 23. EAS_Alarm command . . . . . . . . . . . . . . . . . . . 23 Table 24. G2iL reply to a successful EAS_Alarm c ommand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 25. EAS_Alarm command-response table . . . . . . 23 Table 26. Limiting values[1][2] . . . . . . . . . . . . . . . . . . . . . . 24 Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 28. VDD pin characteristics . . . . . . . . . . . . . . . . . . 26 Table 29. G2iL, G2iL+ VDD and OUT pin characteristics . . . . . . . . . . . . . . . . . . . . . . 26 Table 30. G2iL, G2iL+ memory characteristics . . . . . . . . 27 Table 31. G2iL RF interface characteristics (RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 33. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32 21. Figures Fig 1. Block diagram of G2iL IC . . . . . . . . . . . . . . . . . . .4 Fig 2. Pinning bare die. . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. Pin configuration for SOT886 . . . . . . . . . . . . . . . .5 Fig 4. G2iL wafer layout. . . . . . . . . . . . . . . . . . . . . . . . . .6 Fig 5. G2iL TID memory structure . . . . . . . . . . . . . . . . .12 Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal . .14 Fig 7. Schematic of external power supply . . . . . . . . . .16 Fig 8. Package outline SOT886. . . . . . . . . . . . . . . . . . .28 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 March 2014 178844 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1.1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.1 End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.2 Antenna design benefits . . . . . . . . . . . . . . . . . . 2 2.2.3 Label manufacturer benefit. . . . . . . . . . . . . . . . 2 2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Mechanical specification . . . . . . . . . . . . . . . . . 7 9.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 Fail die identification . . . . . . . . . . . . . . . . . . . . 8 9.1.3 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 8 10 Functional description . . . . . . . . . . . . . . . . . . . 8 10.1 Air interface standards . . . . . . . . . . . . . . . . . . . 8 10.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 8 10.3 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.3.1 Reader to tag Link . . . . . . . . . . . . . . . . . . . . . . 9 10.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . . 9 10.4 G2iL and G2iL+ differences . . . . . . . . . . . . . . . 9 10.5 Supported commands . . . . . . . . . . . . . . . . . . 10 10.6 G2iL, G2iL+ memory . . . . . . . . . . . . . . . . . . . 10 10.6.1 G2iL, G2iL+ overall memory map. . . . . . . . . . 11 10.6.2 G2iL TID memory details . . . . . . . . . . . . . . . . 12 10.7 Custom commands. . . . . . . . . . . . . . . . . . . . . 13 10.7.1 ChangeConfig. . . . . . . . . . . . . . . . . . . . . . . . . 13 G2iL, G2iL+ special features . . . . . . . . . . . . . .13 10.7.2 G2iL, G2iL+ special features control mechanism . . . . . . . . . . . . . . . . . . . . . 17 10.7.3 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.7.4 Reset ReadProtect3 . . . . . . . . . . . . . . . . . . . . 19 10.7.5 ChangeEAS3 . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.7.6 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1 UCODE G2iL, G2iL+ bare die characteristics 25 12.2 UCODE G2iL SOT886 characteristics . . . . . . 27 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 28 14 Packing information . . . . . . . . . . . . . . . . . . . . 29 14.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.2 SOT886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 34 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19 Contact information . . . . . . . . . . . . . . . . . . . . 35 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 Specification Issue 1 26/6/2012 SERIAL TFT MODULE APPLICATION NOTE 1 Compiling and transferring image files via the USB interface. Date Description of change 26/6/12 Initial creation 2 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 Overview The Midas range of serial TFT modules offer the ability to store images which are then selected for display using serial commands. This overcomes the need to transfer large amounts of data over the serial interface. The following application note describes how to prepare image files and transfer them to the display module flash memory drive via the USB interface. Requirements Midas Serial TFT display module. USB cable type A to mini B. BmpToBin application software (available from Midas). Procedure 1) Create two directories one called BMP_DATA and the other BMP_FILE . 2) Place all the bitmap files you require for your project in the BMP_FILE directory. Note that the files must be 24-bit bitmap type. Note that the size of the combined images must not be greater than 2M bytes. This is the sum of x*y*2 for each image. Ie. For the above (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (1315*32*2)=1159360 3 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 3) Re-name each image numerically in the sequence required bearing in mind that any short animation sequences need to be in sequential order. i.e: 4) Exit this directory and place the BmpToBin application file in the parent directory i.e 5) Run the BmpToBinForM.exe application by double clicking the icon. This will then create two files within the BMP_DATA directory. 6) Plug the TFT module into your PC using a USB A to mini B cable. The module should then appear on your PC as a flash memory device. 4 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 7) Simply Copy the two files BMPDATA.BIN and TABLE.BIN created earlier to the module flash drive. These images are then available to be displayed via serial command. If there are already files on the module flash drive you may want to back them up to your PC. You can now via the serial interface view the images on the display module using commands such as: Browse Pictures, Cut a Picture, Animation, Call on PIC and Run Demo. Command Summary Commands are sent to the board via the Serial UART (TTL levels) on J1. The default serial format is 9600,N,8,1. All commands are ASCII characters followed by CR LF (0D0A hex). Function Command Format Example Busy Low time Browse Pictures ALL “ALL\n” - Draw a circle CIRCLE Xa Ya R C “CIRCLE 100 100 50 31\n” 4ms Fill in colour CLR Xa Ya Xe Ye C “CLR 0 0 100 100 31\n” 5ms Clear Screen CLS C “CLS 31\n” 28ms Cut a picture CUT Pn Xa Ya Xb Yb Xs Ys “CUT 1 30 30 0 0 100 100 \n” 20ms Draw a dot DOT Xa Ya C “DOT 100 100 31\n” 0.12ms Draw a frame with line type and chamfer FRAME Xa Ya Xe Ye Ds Do C “FRAME 10 10 200 40 2 3 31\n” 4ms Draw a line LINE Xa Ya Xe Ye C “LINE 10 10 50 50 31\n” 0.7ms Backlight on LEDON “LEDON\n” 4us Backlight off LEDOFF “LEDOFF\n” 4us Animation MOT Xa Ya Ps Pe Pt “MOT 0 0 10 14 100\n” 0.15ms Animation off MOFF “MOFF\n” 4us Call on PIC PIC Pn Xa Ya “PIC 1 30 30\n” 125ms Draw a rectangle RECT Xa Ya Xe Ye C “RECT 10 10 100 100 31\n” 5ms Get screen size * SIZE “SIZE\n” 13ms Display alphabetic string STR Xa Ya C Str “STR 0 0 31 Hello World\n” 0.8ms / char Display alphabetic string with background colour STR Xa Ya C Cb Str “STR 0 20 65535 31 Hello World\n” 30us / char Set baud rate BAUD b1 b2 “BAUD 9600 9600\n” 20ms Run demo DEMO Dt Xa Ya “DEMO 1000 0 0\n” 20ms Stop demo DMOFF “DMOFF\n” 20ms Change orientation TURN Tn “TURN 90\n” 140ms 5 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 Notes: Xa Ya :Start x y coordinates. Xe Ye :End x y coordinates. C :Colour (16 bits,RGB 565). Xb Yb :Start x y coordinates in flash image. Xs yS :Size of flash image block. Ds Do :Length of solid line / dotted line. Str :ASCII String (8x16). Pn :Picture number in flash 000-999. R :Radius in pixels. Ps :Start Picture number. Pe :End picture number. Pt :Time between pictures (step:100ms). * :Returned on RX “STY Xsize Ysize\n” b1 b2 :Baud rate (2400,4800,9600,19200,38400,56000,57600,115200) Dt :Time between pictures (step:100ms). Tn :Rotation angle (0,90) Notes: Anti-static precautions should be observed whilst handling this product. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MIDAS MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Midas disclaims all liability arising from this information and its use. Use of Midas’s products as critical components in life support systems is not authorized except with express written approval by Midas. No licenses are conveyed, implicitly or otherwise, under any Midas intellectual property rights. A Premier Farnell Company MIDAS un traitement complet du signal Bien que les algorithmes de traitement complexes rendent cela possible, ils sont en général exécutés plus vite et de manière plus économique dans un système numérique. Le monde réel ne suit pas l’évolution informatique définie par la Loi de Moore, et le désir humain d’aller toujours plus vite et à moindre coût, incite résolument à rester en analogique. En conséquence, les ingénieurs doivent continuer à relever des défis relatifs à la détection précise de signaux dans l’univers analogique et les restituer le plus fidèlement possible dans un format numérique. Alchimie analogique La conception analogique a longtemps été considérée comme un art ésotérique, exigeant une connaissance pointue et une intuition pour garantir la stabilité du système, optimiser le gain et la réponse en fréquence, traiter les problèmes de mise à la masse, gérer les impédances et leur comparaison, ainsi que minimiser les effets de bruit. Parallèlement, la pression augmente pour satisfaire aux exigences rigoureuses en matière de coût, commercialisation et capacité de production de masse. La grande majorité des ingénieurs modernes ne peut tout simplement pas s’offrir le luxe d’optimiser individuellement des circuits analogiques. Pour relever ces défis, l’alchimie analogique la plus mystérieuse a tendance désormais à se produire au niveau du silicium ; la technique de dorure est intégrée aux composants qui constituent le traitement du signal. Les produits analogiques les plus récents visent maintenant à « pré résoudre » un grand nombre des défis qui occupaient les spécialistes en technique analogique. Ils sont plus riches en fonctionnalités et moins sensibles aux variables, telles que configuration et longueurs de tracé PCB. Ils sont aussi intrinsèquement moins gourmands en énergie que leurs prédécesseurs. Ainsi, les produits de dernière génération proposés sur le marché des circuits intégrés offrent une conception interne plus simple, nécessitant moins de composants externes et supportant une gestion de l’alimentation au niveau du système. La gamme des produits Farnell En offrant l’un des portefeuilles produits, les plus étendus en technologies de traitement du signal, provenant d’innovateurs influents dans le domaine des produits analogiques de pointe, hautement performants, Farnell est idéalement placé pour aider le concepteur à identifier, sélectionner et évaluer les produits haute performance du marché actuel. Pour faciliter l’évaluation, la sélection et l’intégration de produits de traitement du signal en vue d’atteindre des objectifs de système ambitieux, Farnell a classé les principales technologies en cinq catégories, regroupées sous l’acronyme MIDAS : Mixed-signal, Interface, Data conversion, Amplification, and Sensors (ou signaux mixtes, interface, conversion de données, amplification et capteurs). La catégorie Signaux mixtes comprend des appareils comme les multiplexeurs, les commutateurs analogiques, les filtres, les potentiomètres numériques, les isolateurs, les résistances et les compensateurs. Concernant les produits d’interface, les ingénieurs ont de nombreuses options de connectivité, dont SERDES, transmetteurs LVDS et interfaces Ethernet. Ce groupe englobe également les oscillateurs, les circuits d’horloge et les PLL. La conversion de donnée est la phase du traitement du signal la plus proche du domaine numérique, comprenant diverses classes de convertisseurs N/A et A/N dont des appareils polyvalents à haut débit et de grande précision, selon les spécifications de l’application ou du système. Dans la catégorie Amplificateurs, les ingénieurs ont la possibilité de choisir parmi une gamme extrêmement étendue d’options disponibles, là aussi le choix étant en grande partie déterminé par l’application et les exigences de performance du système. Les amplificateurs proposés par les principaux fournisseurs distribués par Farnell incluent des amplificateurs audio, à détection de courant, différentiels, polyvalents, d’instrumentation, d’isolement, logarithmiques, ‘Médaille d’or’ de la conception analogique avancée Le monde actuel est très dépendant du contrôle et de la régulation d’une grande variété d’effets physiques. Par exemple pour utiliser des ressources énergétiques de manière plus efficace et pour améliorer la qualité de vie, les exemples de produits électroniques utilisés pour atteindre ces objectifs incluent les systèmes de contrôle et de mesure des gaz d’échappement, les scanners médicaux, les instruments de surveillance médicale, la télésurveillance d’état d’un équipement et les systèmes de sécurité sophistiqués. opérationnels, à gain programmable et amplis buffer vidéo, ainsi qu’une gamme étendue de comparateurs et de compresseurs/extenseurs. Enfin, concernant les capteurs appropriés, avec les accéléromètres, capteurs de courant, à effet hall, de pression, de proximité et de température, complétés des quatre autres catégories, les ingénieurs peuvent compléter leur analyse des besoins en traitement du signal pour tout système de contrôle, d’enregistrement ou de régulation. Ceux-ci peuvent élargir les possibilités d’application, allant des systèmes médicaux, automobile aux systèmes industriels, commerciaux et domestiques. En analysant le traitement du signal de cette manière, les ingénieurs peuvent rapidement identifier les éléments nécessaires pour compléter une solution et commencer l’assemblage d’une combinaison optimale. Technologie d’avant-garde, présentée en avant-première Dans le cadre de cette campagne Technology First, nous étudions quelques-unes des dernières innovations et tendances dans chacune des cinq catégories afin identifier comment les caractéristiques et les performances des composants viennent en aide aux défis de la conception analogique, en améliorant le rapport qualité/prix tout en supportant encombrement et consommation énergétique moindres. En conclusion, il est important de noter que Farnell est en mesure de fournir des composants complémentaires pour satisfaire aux exigences de la conception numérique, réaliser un système complet et hautement performant. DATA SHEET Product specification October 1998 DISCRETE SEMICONDUCTORS BYW29EX series Rectifier diodes ultrafast, rugged NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged GENERAL DESCRIPTION QUICK REFERENCE DATA Glass passivated epitaxial rectifier SYMBOL PARAMETER MAX. MAX. UNIT diodes in a full pack plastic envelope, featuring low forward voltage drop, BYW29EX- 150 200 ultra-fast recovery times, soft recovery VRRM Repetitive peak reverse 150 200 V characteristic and guaranteed reverse voltage surge and ESD capability. They are VF Forward voltage 0.895 0.895 V intended for use in switchedmode power IF(AV) Forward current 8 8 A supplies and high frequency circuits in trr Reverse recovery time 25 25 ns general where low conduction and IRRM Repetitive peak reverse 0.2 0.2 A switching losses are essential. current PINNING - SOD113 PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 cathode 2 anode case isolated LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT -150 -200 VRRM Repetitive peak reverse voltage - 150 200 V VRWM Crest working reverse voltage - 150 200 V VR Continuous reverse voltage - 150 200 V IF(AV) Average forward current1 square wave; d = 0.5; Ths £ 106 °C - 8 A sinusoidal; a = 1.57; Ths £ 109 °C - 7.3 A IF(RMS) RMS forward current - 11.3 A IFRM Repetitive peak forward current t = 25 μs; d = 0.5; - 16 A Ths £ 106 °C IFSM Non-repetitive peak forward t = 10 ms - 80 A current t = 8.3 ms - 88 A sinusoidal; with reapplied VRWM(max) I2t I2t for fusing t = 10 ms - 32 A2s IRRM Repetitive peak reverse current tp = 2 μs; d = 0.001 - 0.2 A IRSM Non-repetitive peak reverse tp = 100 μs - 0.2 A current Tstg Storage temperature -40 150 °C Tj Operating junction temperature - 150 °C 1 2 case k a 1 2 1 Neglecting switching and reverse current losses October 1998 1 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VC Electrostatic discharge Human body model; - 8 kV capacitor voltage C = 250 pF; R = 1.5 kW ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 °C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Visol R.M.S. isolation voltage from f = 50-60 Hz; sinusoidal - 2500 V both terminals to external waveform; heatsink R.H. £ 65% ; clean and dustfree Cisol Capacitance from both terminals f = 1 MHz - 10 - pF to external heatsink THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Rth j-hs Thermal resistance junction to with heatsink compound - - 5.5 K/W heatsink without heatsink compound - - 7.2 K/W Rth j-a Thermal resistance junction to in free air - 55 - K/W ambient STATIC CHARACTERISTICS Tj = 25 °C unless otherwise stated SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VF Forward voltage IF = 8 A; Tj = 150°C - 0.80 0.895 V IF = 8 A - 0.92 1.05 V IF = 20 A - 1.1 1.3 V IR Reverse current VR = VRWM; Tj = 100 °C - 0.2 0.6 mA VR = VRWM - 2 10 μA DYNAMIC CHARACTERISTICS Tj = 25 °C unless otherwise stated SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Qs Reverse recovery charge IF = 2 A; VR ³ 30 V; -dIF/dt = 20 A/μs - 4 11 nC trr1 Reverse recovery time IF = 1 A; VR ³ 30 V; - 20 25 ns -dIF/dt = 100 A/μs trr2 Reverse recovery time IF = 0.5 A to IR = 1 A; Irec = 0.25 A - 15 20 ns Vfr Forward recovery voltage IF = 1 A; dIF/dt = 10 A/μs - 1 - V October 1998 2 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged Fig.1. Definition of trr1, Qs and Irrm Fig.2. Definition of Vfr Fig.3. Circuit schematic for trr2 Fig.4. Definition of trr2 Fig.5. Maximum forward dissipation PF = f(IF(AV)); square current waveform where IF(AV) =IF(RMS) x ÖD. Fig.6. Maximum forward dissipation PF = f(IF(AV)); sinusoidal current waveform where a = form factor = IF(RMS) / IF(AV). Q s 10% 100% time dI dt F I R I F I rrm t rr I = 1A R I rec = 0.25A 0A trr2 0.5A IF IR time time V F V fr V F I F 0 2 4 6 8 10 12 0 2 4 6 8 10 12 D = 1.0 0.5 0.2 0.1 BYW29 IF(AV) / A PF / W tp D = tp T T t I Ths(max) / C 150 139 128 117 106 95 84 Vo = 0.791 V Rs = 0.013 ohms shunt Current to ’scope D.U.T. Voltage Pulse Source R 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 a = 1.57 1.9 2.2 2.8 4 BYW29 IF(AV) / A PF / W Ths(max) / C 150 144.5 139 133.5 128 122.5 117 111.5 106 Vo = 0.791 V Rs = 0.013 Ohms October 1998 3 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged Fig.7. Maximum trr at Tj = 25 °C. Fig.8. Maximum Irrm at Tj = 25 °C. Fig.9. Typical and maximum forward characteristic IF = f(VF); parameter Tj Fig.10. Maximum Qs at Tj = 25 °C. Fig.11. Transient thermal impedance; Zth j-hs = f(tp). 1 10 trr / ns 1 10 100 1000 100 dIF/dt (A/us) IF=1A IF=10A 10 1.0 1.0 10 100 -dIF/dt (A/us) Qs / nC IF=10A 5A 2A 1A 100 10 1 0.1 0.01 Irrm / A 1 10 100 -dIF/dt (A/us) IF=1A IF=10A 1us 10us 100us 1ms 10ms 100ms 1s 10s 0.001 0.01 0.1 1 10 pulse width, tp (s) BYW29F/EX Transient thermal impedance, Zth j-hs (K/W) tp D = tp T T P t D 0 1 2 30 20 10 0 typ max IF / A 0.5 1.5 VF / V Tj=150 C Tj=25 C BYW29 October 1998 4 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged MECHANICAL DATA Dimensions in mm Net Mass: 2 g Fig.12. SOD113; The seating plane is electrically isolated from all terminals. Notes 1. Refer to mounting instructions for F-pack envelopes. 2. Epoxy meets UL94 V0 at 1/8". 10.3 max 3.2 3.0 4.6 max 2.9 max 2.8 seating plane 6.4 15.8 max 0.6 2.5 2.54 5.08 1 2 3 max. not tinned 3 0.5 2.5 0.9 0.7 0.4 M 15.8 max. 19 max. 13.5 min. Recesses (2x) 2.5 0.8 max. depth 1.0 (2x) October 1998 5 Rev 1.200 NXP Semiconductors Legal information DATA SHEET STATUS Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DEFINITIONS Product specification ⎯ The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. DISCLAIMERS Limited warranty and liability ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors Legal information NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products ⎯ Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the content, except for the legal definitions and disclaimers. © NXP B.V. 2011 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands CSM_EE-SPX303N_403N_DS_E_3_2 Broad Slot-type Photomicrosensor EE-SPX303N/403N A Wide Slot Width of 13 mm and Superior Resistance to Light Interference and Noise. • Noise resistance equivalent to photomicrosensors with built-in amplifiers. • Resistance to common noise at least 30 times that of previous models. • Resistance to inverter noise at least 10 times that of previous models. • Reverse polarity protection built in. Be sure to read Safety Precautions on page 3. For the most recent information on models that have been certified for safety standards, refer to your OMRON website. Ordering Information Sensors Accessories (Order Separately) * Refer to Accessories for details. Appearance Sensing method Sensing distance (slot width) Output type Output configuration Model Through-beam type (with slot) NPN output Dark-ON EE-SPX303N Light-ON EE-SPX403N Type Cable length Model Connector EE-1001 EE-1009 Connector with Cable 1 m EE-1006 1M EE-1010 1M 2 m EE-1006 2M EE-1010 2M Connector with Robot Cable 1 m EE-1010-R 1M 2 m EE-1010-R 2M NPN/PNP Conversion Connector 0.46 m (total length) EE-2002 Infrared light 13 mm (slot width) 2 EE-SPX303N/403N Ratings and Specifications Engineering Data (Reference Value) Sensing Position Characteristics EE-SPX303N Item Models EE-SPX303N, EE-SPX403N Sensing distance 13 mm (slot width) Sensing object Opaque: 2.2 × 0.5 mm min. Differential distance 0.05 mm max. Light source Infrared LED (pulse lighting) with a peak wavelength of 940 nm Indicator Light indicator (red) Supply voltage 12 to 24 VDC ±10%, ripple (p-p): 5% max. Current consumption 15 mA max. Control output NPN voltage output: Load power supply voltage: 12 to 24 VDC Load current: 80 mA max. OFF current: 0.5 mA max. 80 mA load current with a residual voltage of 2.0 V max. 10 mA load current with a residual voltage of 1.0 V max. Protection circuits Power supply reverse polarity protection, Output reverse polarity protection Response frequency * 100 Hz min. Ambient illumination 3,000 lx max. with incandescent light or sunlight on the surface of the receiver. Ambient temperature range Operating: −10 to +55°C Storage: −25 to +65°C Ambient humidity range Operating: 5% to 85% Storage: 5% to 95% Vibration resistance Destruction: 10 to 55 Hz, 1.5-mm double amplitude for 2 h each in X, Y, and Z directions Shock resistance Destruction: 500 m/s2 for 3 times each in X, Y, and Z directions Degree of protection IEC IP50 Connecting method Special connector (soldering not possible) Weight Approx. 4 g Material Polycarbonate * The response frequency was measured by detecting the following rotating disk. 2 mm Disk 2 mm 2 mm 0 1 2 3 4 5 6 Distance d (mm) Tr ON Tr OFF Dark-ON d 0 1 2 3 4 5 6 Distance d (mm) Tr ON Tr OFF Dark-ON d EE-SPX303N/403N 3 I/O Circuit Diagrams NPN Output Safety Precautions Refer to Warranty and Limitations of Liability. This product is not designed or rated for ensuring safety of persons either directly or indirectly. Do not use it for such purposes. Make sure that this product is used within the rated ambient environment conditions. ● Wiring • Connection is made using a connector. Do not solder to the pins (leads). The pins (leads) are soldered to the internal board of the Sensor. Therefore, direct soldering of the pins (leads) may result in an internal disconnection causing malfunction. • When extending the cable, use an extension cable with conductors having a total cross-section area of 0.3 mm2. The total cable length must be 2 m maximum. • To use a cable length longer than 2 m, attach a capacitor with a capacitance of approximately 10 μF to the wires as shown below. The distance between the terminal and the capacitor must be within 2 m. (Use a capacitor with a dielectric strength that is at least twice the Sensor's power supply voltage.) • Make sure the total length of the power cable connected to the product is less than 10 m even if a capacitor is inserted. Model Output configuration Timing charts Output circuit EE-SPX403N Light-ON EE-SPX303N Dark-ON Incident Interrupted ON OFF ON OFF Operates Releases H L Light indicator (red) Output transistor Load 1 (relay) Load 2 lC Light indicator (red) 1.5 to 3 mA Load 1 Load 2 Main circuit OUT ∗ * Voltage output (when the sensor is connected to a transistor circuit) 12 to 24 VDC Incident Interrupted ON OFF ON OFF Operates Releases H L Light indicator (red) Output transistor Load 1 (relay) Load 2 WARNING Precautions for Correct Use OUT Extension cable A capacitance of 10 μF min. + − 12 to 24 VDC 0 V 2 m max. 4 EE-SPX303N/403N (Unit: mm) Dimensions Tolerance class IT16 applies to dimensions in this datasheet unless otherwise specified. Sensors Accessories (Order Separately) * Refer to Accessories for details. 7.4 0.3 0.7 13 10 19 3.2 26 26 2-3.7 5.08 13 19.5 2.54 1 2 3 Four, R1.6 Indicator window Sensing window (0.5 × 2.2) EE-SPX303N, EE-SPX403N Terminal Arrangement (1) + Vcc (2) OUT OUTPUT (3) − GND (0 V) Read and Understand This Catalog Please read and understand this catalog before purchasing the products. Please consult your OMRON representative if you have any questions or comments. Warranty and Limitations of Liability WARRANTY OMRON's exclusive warranty is that the products are free from defects in materials and workmanship for a period of one year (or other period if specified) from date of sale by OMRON. OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, REGARDING NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR PARTICULAR PURPOSE OF THE PRODUCTS. ANY BUYER OR USER ACKNOWLEDGES THAT THE BUYER OR USER ALONE HAS DETERMINED THAT THE PRODUCTS WILL SUITABLY MEET THE REQUIREMENTS OF THEIR INTENDED USE. OMRON DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED. LIMITATIONS OF LIABILITY OMRON SHALL NOT BE RESPONSIBLE FOR SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES, LOSS OF PROFITS OR COMMERCIAL LOSS IN ANY WAY CONNECTED WITH THE PRODUCTS, WHETHER SUCH CLAIM IS BASED ON CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT LIABILITY. In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which liability is asserted. IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS REGARDING THE PRODUCTS UNLESS OMRON'S ANALYSIS CONFIRMS THAT THE PRODUCTS WERE PROPERLY HANDLED, STORED, INSTALLED, AND MAINTAINED AND NOT SUBJECT TO CONTAMINATION, ABUSE, MISUSE, OR INAPPROPRIATE MODIFICATION OR REPAIR. Application Considerations SUITABILITY FOR USE OMRON shall not be responsible for conformity with any standards, codes, or regulations that apply to the combination of products in the customer's application or use of the products. At the customer's request, OMRON will provide applicable third party certification documents identifying ratings and limitations of use that apply to the products. This information by itself is not sufficient for a complete determination of the suitability of the products in combination with the end product, machine, system, or other application or use. The following are some examples of applications for which particular attention must be given. This is not intended to be an exhaustive list of all possible uses of the products, nor is it intended to imply that the uses listed may be suitable for the products:  Outdoor use, uses involving potential chemical contamination or electrical interference, or conditions or uses not described in this catalog.  Nuclear energy control systems, combustion systems, railroad systems, aviation systems, medical equipment, amusement machines, vehicles, safety equipment, and installations subject to separate industry or government regulations.  Systems, machines, and equipment that could present a risk to life or property. Please know and observe all prohibitions of use applicable to the products. NEVER USE THE PRODUCTS FOR AN APPLICATION INVOLVING SERIOUS RISK TO LIFE OR PROPERTY WITHOUT ENSURING THAT THE SYSTEM AS AWHOLE HAS BEEN DESIGNED TO ADDRESS THE RISKS, AND THAT THE OMRON PRODUCTS ARE PROPERLY RATED AND INSTALLED FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR SYSTEM. PROGRAMMABLE PRODUCTS OMRON shall not be responsible for the user's programming of a programmable product, or any consequence thereof. Disclaimers CHANGE IN SPECIFICATIONS Product specifications and accessories may be changed at any time based on improvements and other reasons. It is our practice to change model numbers when published ratings or features are changed, or when significant construction changes are made. However, some specifications of the products may be changed without any notice. When in doubt, special model numbers may be assigned to fix or establish key specifications for your application on your request. Please consult with your OMRON representative at any time to confirm actual specifications of purchased products. DIMENSIONS ANDWEIGHTS Dimensions and weights are nominal and are not to be used for manufacturing purposes, even when tolerances are shown. PERFORMANCE DATA Performance data given in this catalog is provided as a guide for the user in determining suitability and does not constitute a warranty. It may represent the result of OMRON’s test conditions, and the users must correlate it to actual application requirements. Actual performance is subject to the OMRON Warranty and Limitations of Liability. ERRORS AND OMISSIONS The information in this document has been carefully checked and is believed to be accurate; however, no responsibility is assumed for clerical, typographical, or proofreading errors, or omissions. 2012.8 In the interest of product improvement, specifications are subject to change without notice. OMRON Corporation Industrial Automation Company http://www.ia.omron.com/ (c)Copyright OMRON Corporation 2012 All Right Reserved. DATA SHEET Product data sheet Supersedes data of 1999 Apr 29 2004 Jan 22 DISCRETE SEMICONDUCTORS PMBTA13; PMBTA14 NPN Darlington transistors 2004 Jan 22 2 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 FEATURES •High current (max. 500 mA) •Low voltage (max. 30 V) •High DC current gain (min. 10000). APPLICATIONS •High input impedance preamplifiers. DESCRIPTION NPN Darlington transistor in a SOT23 plastic package. PNP complement: PMBTA64. MARKING Note 1.* = p : Made in Hong Kong. * = t : Made in Malaysia. * = W : Made in China. PINNING TYPE NUMBER MARKING CODE(1) PMBTA13 *1M PMBTA14 *1N PIN DESCRIPTION 1 base 2 emitter 3 collector Fig.1 Simplified outline (SOT23) and symbol.handbook, halfpageMAM298132132TR2TR1Top view ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION PMBTA13 − plastic surface mounted package; 3 leads SOT23 PMBTA14 2004 Jan 22 3 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1.Transistor mounted on an FR4 printed-circuit board. THERMAL CHARACTERISTICS Note 1.Transistor mounted on an FR4 printed-circuit board. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCBO collector-base voltage open emitter − 30 V VCES collector-emitter voltage VBE = 0 − 30 V VEBO emitter-base voltage open collector − 10 V IC collector current (DC) − 500 mA ICM peak collector current − 800 mA IB base current (DC) − 200 mA Ptot total power dissipation Tamb ≤ 25 °C; note 1 − 250 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb operating ambient temperature −65 +150 °C SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-a) thermal resistance from junction to ambient note 1 500 K/W SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT ICBO collector cut-off current IE = 0; VCB = 30 V − 100 nA IEBO emitter cut-off current IC = 0; VEB = 10 V − 100 nA hFE DC current gain IC = 10 mA; VCE = 5 V; (see Fig.2) PMBTA13 5000 − PMBTA14 10000 − DC current gain IC = 100 mA; VCE = 5 V; (see Fig.2) PMBTA13 10000 − PMBTA14 20000 − VCEsat collector-emitter saturation voltage IC = 100 mA; IB = 0.1 mA − 1.5 V VBEon base-emitter on-state voltage IC = 100 mA; VCE = 5 V − 1.4 V fT transition frequency IC = 10 mA; VCE = 5 V; f = 100 MHz 125 − MHz 2004 Jan 22 4 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 Fig.2 DC current gain; typical values.handbook, full pagewidth060000800002000040000MGD83710−11IC (mA)hFE10102 103VCE = 2 V. 2004 Jan 22 5 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 PACKAGE OUTLINEUNITA1max.bpcDE e1HELpQwv REFERENCESOUTLINEVERSIONEUROPEANPROJECTIONISSUE DATE04-11-0406-03-16 IEC JEDEC JEITAmm0.10.480.380.150.093.02.81.41.20.95e1.92.52.10.550.450.10.2DIMENSIONS (mm are the original dimensions)0.450.15 SOT23TO-236ABbpDe1eAA1LpQdetail XHEEwMvMABAB012 mmscaleA1.10.9cX123Plastic surface-mounted package; 3 leadsSOT23 2004 Jan 22 6 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 DATA SHEET STATUS Notes 1.Please consult the most recently issued document before initiating or completing a design. 2.The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENTSTATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DISCLAIMERS General ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. NXP Semiconductors Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com © NXP B.V. 2009 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Printed in The Netherlands R75/05/pp7 Date of release: 2004 Jan 22 Document order number: 9397 750 12507 http://www.tracopower.com Page 1 of 4 DC/DC Converters TDR 3 Series, 3 Watt Features ◆ Compact design in SMD or DIP package ◆ Wide 2:1 input voltage range ◆ Fully regulated outputs ◆ Low ripple and noise ◆ No minimum load required ◆ Temperature range –40°C to +85°C ◆ I/O isolation 1500 VDC ◆ Continuous short-circuit protection ◆ Remote On/Off control ◆ Fully RoHS compliant ◆ 3-year product warranty The TDR-3 series is a family of compact 3 W dc/dc-converters with 2:1 input voltage ranges and tightly regulated output voltages even under no load conditions. The product is available in SMD-package or in DIP-package. They work with high efficiency over the full load range and come with a remote On/Off input. The usability in temperature ranges of up to 85°C, continuous short circuit protection and excellent immunity against environmental influences make these converters very reliable. A TDR-3 converter is the ideal solution for space critical high end applications in communication equipment, instrumentation and industrial electronics. Order code DIP models Order code SMD models Input voltage range Output voltage Output current max. Efficiency typ. TDR 3-0511 TDR 3-0511SM 5.0 VDC 600 mA 79 % TDR 3-0512 TDR 3-0512SM 12 VDC 250 mA 80 % TDR 3-0513 TDR 3-0513SM 4.5 – 9.0 VDC 15 VDC 200 mA 81 % TDR 3-0522 TDR 3-0522SM (5 VDC nominal) ±12 VDC ±125 mA 80 % TDR 3-0523 TDR 3-0523SM ±15 VDC ±100 mA 81 % TDR 3-1211 TDR 3-1211SM 5.0 VDC 600 mA 81 % TDR 3-1212 TDR 3-1212SM 12 VDC 250 mA 82 % TDR 3-1213 TDR 3-1213SM 9 – 18 VDC 15 VDC 200 mA 82 % TDR 3-1222 TDR 3-1222SM (12 VDC nominal) ±12 VDC ±125 mA 82 % TDR 3-1223 TDR 3-1223SM ±15 VDC ±100 mA 83 % TDR 3-2411 TDR 3-2411SM 5.0 VDC 600 mA 81 % TDR 3-2412 TDR 3-2412SM 12 VDC 250 mA 82 % TDR 3-2413 TDR 3-2413SM 18 – 36 VDC 15 VDC 200 mA 83 % TDR 3-2422 TDR 3-2422SM (24 VDC nominal) ±12 VDC ±125 mA 83 % TDR 3-2423 TDR 3-2423SM ±15 VDC ±100 mA 83 % TDR 3-4811 TDR 3-4811SM 5.0 VDC 600 mA 81 % TDR 3-4812 TDR 3-4812SM 12 VDC 250 mA 82 % TDR 3-4813 TDR 3-4813SM 36 – 75 VDC 15 VDC 200 mA 82 % TDR 3-4822 TDR 3-4822SM (48 VDC nominal) ±12 VDC ±125 mA 83 % TDR 3-4823 TDR 3-4823SM ±15 VDC ±100 mA 83 % Models UL 60950-1 http://www.tracopower.com Page 2 of 4 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. DC/DC Converters TDR 3 Series 3 Watt Input Specifications Input current at no load (nominal input voltage) 5 Vin models: 50 mA typ. 12 Vin models: 30 mA typ. 24 Vin models: 13 mA typ. 48 Vin models: 10 mA typ. Input current at full load (nominal input voltage) 5 Vin models: 790 mA typ. 12 Vin models: 320 mA typ. 24 Vin models: 160 mA typ. 48 Vin models: 80 mA typ. Surge voltage (1 sec. max.) 5 Vin models: 15 V max. 12 Vin models: 25 V max. 24 Vin models: 50 V max. 48 Vin models: 100 V max. Input filter capacitor type (see EMC considerations page 3 for compliance to EN 55022 class A/B) ESD (electrostatic discharge) EN 61000-4-2, air ±8 kV, contact ±6 kV, perf. criteria A Radiated immunity EN 61000-4-3 10 V/m, perf. criteria A Fast transient / Surge EN 61000-4-4, ±2 kV, perf. criteria A EN 61000-4-5, ±1 kV perf. criteria A with external input capacitor e.g. Nippon chemi-con KY 220 μF, 100 V, ESR 48 mOhm Conducted immunity EN 61000-4-6, 10 Vrms, perf. criteria A Reflected ripple current 5 Vin models: 80 mAp-p typ. (measured with input filter according class A) 12 Vin models: 40 mAp-p typ. 24 Vin models: 30 mAp-p typ. 48 Vin models: 20 mAp-p typ. Output Specifications Voltage set accuracy ±1 % max Regulation – Input variation Vin min. to Vin max. 0.2 % max. – Load variation 0 – 100 % single output models: 1.0 % max. dual output models: 1.0 % max. balanced load – Load variation 10 – 90 % single output models: 0.5 % max. dual output models: 0.8 % max. balanced load – Load cross regulation 25/100 % 5.0 % max. (dual output models) Minimum load 0 % of rated max. load Temperature coefficient ±0.02 %/K Ripple and noise (20 MHz bandwidth) 30 mVp-p typ. Start up time – Power On 5 ms typ. (constant resistive load) – Remote On 5 ms typ. Transient response setting time (25 % load step change) 250 μs typ. Short circuit protection continuous, automatic recovery Capacitive load 5 VDC models: 1680 μF max. 12 VDC models: 820 μF max. 15 VDC models: 680 μF max. ±12 VDC models: ±470 μF max. ±15 VDC models: ±330 μF max. http://www.tracopower.com Page 3 of 4 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. DC/DC Converters TDR 3 Series 3 Watt EMC Consideration Recommended filter for EN 55022 class A compliance Input models C1 C3 L1 value order code datasheet 5 VDC 4.7 μF / 25 V 1812 MLCC 10 μH TCK-047 www.tracopower.com/products/tck047.pdf 12 VDC 6.8 μF / 50 V 1812 MLCC 12 μH TCK-062 www.tracopower.com/products/tck062.pdf 24 VDC 4.7 μF / 50 V 1812 MLCC 220pF / 3 kV 1808 MLCC 10 μH TCK-047 www.tracopower.com/products/tck047.pdf 48 VDC 4.7 μF / 100 V 1812 MLCC 10 μH General Specifications Temperature ranges – Operating –40°C to +85°C – Storage –55°C to +125°C – Case temperature tba. Load derating 3.3 %/K above +70°C Humidity (non condensing) 5 % to 90 % rel. H max. Thermal shock acc. MIL-STD-810F Vibration acc. MIL-STD-810F Reliability, calculated MTBF (MIL-HDBK-217F, at+25°C, ground benign) >2.4 Mio h Isolation voltage (60 sec.) – Input/Output 1500 VDC Isolation capacitance – Input/Output 50 pF max. Isolation resistance – Input/Output (500 VDC) >10 GOhm Altitude during operation tba. Safety standard (designed to meet) IEC/EN 60950-1, UL 60950-1 Safety approvals – UL/cUL www.ul.com -> certifications -> File e188913 Switching frequency 100 kHz (PWM) Remote On/Off – On: open or high impedance – Off: 2...4 mA current applied via 1KOhm resistor – Off stand by input current 2.5 mA max. TDR 3 dc/dc-converter Load L1 C1 C3 +Vin -Vin +Vout -Vout TDR 3 dc/dc-converter Load L1 C1 C2 C3 +Vin -Vin +Vout -Vout Input models C1 & C2 C3 L1 value order code (SMD type) datasheet 5 VDC 6.8 μF / 25 V 1812 MLCC 10 μH TCK-047 www.tracopower.com/products/tck047.pdf 12 VDC 4.7 μF / 50 V 1812 MLCC 12 μH TCK-062 www.tracopower.com/products/tck062.pdf 24 VDC 220pF / 3 kV 1808 MLCC 18 μH TCK-046 48 VDC 4.7 μF / 100 V 1812 MLCC 18 μH TCK-046 www.tracopower.com/products/tck046.pdf Recommended filter for EN 55022 class B compliance Page 4 of 4 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com DC/DC Converters TDR 3 Series 3 Watt Outline Dimensions Pin Single Dual 1 –Vin (GND) –Vin (GND) 2 Remote On/Off Remote On/Off 6 NC Common 7 NC –Vout 8 +Vout +Vout 9 –Vout Common 14 +Vin (Vcc) +Vin (Vcc) Pin-Out Rev. February 22. 2013 Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Pin pich tolerances: ±0.25 (±0.01) Pysical Specifications Casing material non-conductive plastic (UL94V-0 rated) Package weight 4.5 g (0.16 oz) Soldering profile for DIP-package models max. 265°C / 10 sec. (wave soldering) Lead-free reflow solder process for SMD-package models as per J-STD-020D.01 (to find at: www.jedec.org - free registration required) Moisture sensivity level (for SMD-package models) level 2a as per J-STD-033B.01 (to find at: www.jedec.org - free registration required) Environmental compliance – Reach www.tracopower.com/products/tdr3-reach.pdf – RoHS RoHS directive 2011/65/EU Packaging – Tube 10 pcs packing unit – Tape & Reel (only SMD models, add suffix –TR) 200 pcs packing unit 18.9 8.7 12.8 13.55 (0.74) (0.35) (0.533) (0.50) 3.8 (0.15) 0.8(0.03) 1.3(0.05) top view 14 9 8 1 2 6 7 1.8 2.54 10.16 2.54 (0.07) (0.1) (0.4) (0.1) 0.25 (0.01) 0-15° 1.8 2.54 10.16 2.54 18.9 8.7 12.8 17.2 (0.07) (0.1) (0.4) (0.74) (0.35) (0.68) (0.50) (0.1) 1.0 (0.04) 1.5 (0.06) top view 14 9 8 1 2 6 7 7.4 (0.29) 0.25 (0.01) 0-4° 1.2 (0.05) DIP-Models SMD-Models NC = not to connect Recommended Solder Pad Dimension: 18.1 (0.71) 1.8 2.54 10.16 2.54 (0.07) (0.1) (0.4) (0.1) 1.8 (0.07) 2.0 (0.08) Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 1 / 60 Features  Single output current up to 700 mA  3 watts maximum output power  High efficiency up to 82%  RoHS directive compliant  Sip package, 21.8 x 11.2 x 9.1mm (0.86 x 0.36x 0.44 inch)  4:1 wide input voltage range  Low ripple & noise  UL94-V0 case potting materials  Input to output isolation: 1500Vdc,min for 60 seconds  Continuous short circuit protection  Remote ON/OFF  International safety standard approval Options  3000Vdc isolation for 60 seconds Applications  Wireless Network  Telecom / Datacom  Industry Control System  Measurement Equipment  Semiconductor Equipment TMR 3-WI Series Application Note DC/DC Converter 4.5 to 18Vdc, 9 to 36Vdc or 18 to 75Vdc Input 3.3 to 15Vdc Single Outputs ±5Vdc to ±15Vdc Dual Outputs and 3 Watt Output Power Pending Complete TMR 3-WI datasheet can be downloaded at: http://www.tracopower.com/products/tmr3wi.pdf General Description The TMR 3WI series offer 3 watts of output power from a 21.8 x 11.2 x 9.1mm (0.86 x 0.36 x 0.44 inch) package without derating up to 71°C. The TMR 3WI series have 4:1 wide input voltage range from 4.5-18Vdc, 9-36Vdc or 18-75Vdc and features 1500Vdc of isolation test voltage, short-circuit protection. All models are particularly suited to telecommunications, industrial, mobile telecom and test equipment applications. Table of contents Absolute Maximum Rating P2 Thermal Consideration P57 Output Specification P2 Remote ON/OFF Control P57 Input Specification P3 – P4 Mechanical Data P58 General Specification P4 – P5 Recommended Pad Layout P58 Environmental Specification P5 Soldering Consideration P59 EMC Characteristic P5 Packaging Information P59 Characteristic Curves P6 – P53 Order Code P60 Test Configurations P54 Safety and Installation Instruction P60 EMI Considerations P55 – P56 MTBF and Reliability P60 Input Source Impedance P57 Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 2 / 60 3W Single & Dual Output Absolute Maximum Rating Parameter Model Min Max Unit Input Voltage Continuous Transient (100ms) TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI 18 36 75 36 50 100 Vdc Operating Ambient Temperature (without derating) All -40 +71 °C Storage Temperature All -55 +125 °C Output Specification Parameter Model Min Typ Max Unit Output Voltage (Vin = Vin nom; Full Load; TA = 25°C) TMR 3-xx10WI TMR 3-xx11WI TMR 3-xx09WI TMR 3-xx12WI TMR 3-xx13WI TMR 3-xx21WI TMR 3-xx22WI TMR 3-xx23WI 3.267 4.95 8.91 11.88 14.85 ±4.95 ±11.88 ±14.85 3.3 5 9 12 15 ±5 ±12 ±15 3.333 5.05 9.09 12.12 15.15 ±5.05 ±12.12 ±15.15 Vdc Output Regulation Line (Vin min to Vin max at Full Load) Load (0% to 100% of Full Load) Load (5% to 100% of Full Load) All -0.2 -1.0 -0.5 +0.2 +1.0 +0.5 % Output Ripple & Noise Peak-to-Peak (5Hz to 20MHz Bandwidth) All 30 mV pk-pk Temperature Coefficient All -0.02 +0.02 %/°C Dynamic Load Response (Vin = Vin nom; TA = 25°C) Load step change from 75% to 100% or 100 to 75% of Full Load Setting Time (Vout < 10% peak deviation) All 250 μS Output Current TMR 3-xx10WI TMR 3-xx11WI TMR 3-xx09WI TMR 3-xx12WI TMR 3-xx13WI TMR 3-xx21WI TMR 3-xx22WI TMR 3-xx23WI 0 0 0 0 0 0 0 0 700 600 333 250 200 ±300 ±125 ±100 mA Max. Capacitive Load on the Output TMR 3-xx10WI TMR 3-xx11WI TMR 3-xx09WI TMR 3-xx12WI TMR 3-xx13WI TMR 3-xx21WI TMR 3-xx22WI TMR 3-xx23WI 3300 1680 1000 820 680 ±1000 ±470 ±330 μF Output Short Circuit Protection All Continuous, automatics recovery Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 3 / 60 3W Single & Dual Output Input Specification Parameter Model Min Typ Max Unit Operating Input Voltage TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI 4.5 9 18 12 24 48 18 36 75 Vdc Input Current (Maximum Value at Vin = Vin nom; Full Load) TMR 3-1210WI TMR 3-1211WI TMR 3-1209WI TMR 3-1212WI TMR 3-1213WI TMR 3-1221WI TMR 3-1222WI TMR 3-1223WI TMR 3-2410WI TMR 3-2411WI TMR 3-2409WI TMR 3-2412WI TMR 3-2413WI TMR 3-2421WI TMR 3-2422WI TMR 3-2423WI TMR 3-4810WI TMR 3-4811WI TMR 3-4809WI TMR 3-4812WI TMR 3-4813WI TMR 3-4821WI TMR 3-4822WI TMR 3-4823WI 285 338 333 329 329 329 329 329 140 165 165 160 160 167 162 162 71 82 82 81 81 84 81 81 mA Input Standby Current (Typical Value at Vin = Vin nom; No Load) TMR 3-1210WI TMR 3-1211WI TMR 3-1209WI TMR 3-1212WI TMR 3-1213WI TMR 3-1221WI TMR 3-1222WI TMR 3-1223WI TMR 3-2410WI TMR 3-2411WI TMR 3-2409WI TMR 3-2412WI TMR 3-2413WI TMR 3-2421WI TMR 3-2422WI TMR 3-2423WI TMR 3-4810WI TMR 3-4811WI TMR 3-4809WI TMR 3-4812WI TMR 3-4813WI TMR 3-4821WI TMR 3-4822WI TMR 3-4823WI 35 40 40 40 40 40 40 40 20 20 19 20 19 25 25 25 12 12 13 14 14 14 14 14 mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 4 / 60 3W Single & Dual Output Input Specification Parameter Model Min Typ Max Unit Input Reflected Ripple Current (See Page 54) TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI 25 10 8 mA pk-pk Start Up Time (Vin = Vin nom and constant resistive load) Power up Remote ON/OFF All 30 30 mS Remote ON/OFF Control (See Page 57) DC-DC ON DC-DC OFF All 2 Open 4 mA Remote Off Input Current All 2.5 mA General Specification Parameter Model Min Typ Max Unit Efficiency (See Page 60) (Vin = Vin nom; Full Load; TA = 25°C) TMR 3-1210WI TMR 3-1211WI TMR 3-1209WI TMR 3-1212WI TMR 3-1213WI TMR 3-1221WI TMR 3-1222WI TMR 3-1223WI TMR 3-2410WI TMR 3-2411WI TMR 3-2409WI TMR 3-2412WI TMR 3-2413WI TMR 3-2421WI TMR 3-2422WI TMR 3-2423WI TMR 3-4810WI TMR 3-4811WI TMR 3-4809WI TMR 3-4812WI TMR 3-4813WI TMR 3-4821WI TMR 3-4822WI TMR 3-4823WI 74 78 79 80 80 80 80 80 75 80 80 82 82 79 81 81 74 80 80 81 81 79 81 81 % Isolation Voltage (for 60 seconds) Input to Output Standard Suffix ”H” All All 1500 3000 Vdc Isolation Resistance All 109 Ω Isolation Capacitance Standard Suffix ”H” All 200 40 pF Switching Frequency All 100 KHz Weight All 4.8 g Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 5 / 60 3W Single & Dual Output General Specification Parameter Model Min Typ Max Unit MTBF (See Page 60) Bellcore TR-NWT-000332, TC = 40°C MIL-HDBK-217F All 3’963’000 1’707’000 hours Case Material Non-conductive black plastic Base Material None Potting material Silicon (UL94-V0) Dimensions 21.8 X 9.2 X 11.1 mm (0.86 X 0.36 X 0.44 Inch) Environmental Specification Thermal shock MIL-STD-810F Vibration MIL-STD-810F Relative humidity 5% to 95% RH EMC Characteristic EMI (See Page 55 & 56) EN55022 Class A Class B ESD EN61000-4-2 Air ±8KV Contact ±6KV Performance Criteria A Radiated immunity EN61000-4-3 10V/m Performance Criteria A Fast transient * EN61000-4-4 ±2KV Performance Criteria A Surge * EN61000-4-5 ±1KV Performance Criteria A Conducted immunity EN61000-4-6 10Vr.m.s Performance Criteria A * An external input filter capacitor is required if the module has to comply with EN 61000-4-4, EN 61000-4-5. The filter capacitor Tracopower suggest: Nippon Chemi-Con KY series, 100μF/100V, ESR = 110mΩ. Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 6 / 60 3W Single & Dual Output Characteristic Curves All test conditions are at 25°C. The figures are identical for TMR 3-1210WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 7 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1210WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 8 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1211WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 9 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1211WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 10 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1209WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 11 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1209WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 12 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1212WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 13 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1212WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 14 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1213WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 15 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1213WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 16 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1221WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 17 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1221WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 18 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1222WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 19 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1222WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 20 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1223WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 21 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1223WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 22 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2410WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 23 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2410WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 24 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2411WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 25 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2411WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 26 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2409WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 27 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2409WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 28 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2412WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 29 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2412WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 30 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2413WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 31 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2413WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 32 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2421WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 33 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2421WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 34 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2422WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 35 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2422WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 36 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2423WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 37 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2423WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 38 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4810WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 39 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4810WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 40 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4811WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 41 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4811WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 42 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4809WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 43 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4809WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 44 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4812WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 45 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4812WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 46 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4813WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 47 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4813WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 48 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4821WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 49 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4821WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 50 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4822WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 51 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4822WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 52 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4823WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 53 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4823WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 54 / 60 3W Single & Dual Output Testing Configurations Input reflected-ripple current measurement test up Component Value Voltage Reference L 2u2H ---- SMD Inductor C 1μF 100V 1210 MLCC Peak-to-peak output ripple & noise measurement test up Output voltage and efficiency measurement test up Note: All measurements are taken at the module terminals. % 100            in in o o V I V I Efficiency Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 55 / 60 3W Single & Dual Output EMI considerations +Vin -Vin +Vout -Vout C1 L1 D/D Converter +INPUT -INPUT LOAD Suggested Schematic to comply with EN55022 Conducted Noise Class A recommended PCB Layout with Input Filter To comply with conducted noise according to EN55022 CLASS A following components are recommended: TMR 3-12xxWI Component Value Voltage Reference C1 4.7μF 25V 1210 MLCC L1 2.2μH ---- SMD Inductor, P/N: TCK-059 TMR 3-24xxWI Component Value Voltage Reference C1 2.2μF 50V 1210 MLCC L1 10μH ---- SMD Inductor, P/N: TCK-047 TMR 3-48xxWI Component Value Voltage Reference C1 2.2μF 100V 1210 MLCC L1 10μH ---- SMD Inductor, P/N: TCK-047 PDL03W SERIES Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 56 / 60 3W Single & Dual Output EMI considerations (Continued) +Vin -Vin +Vout -Vout C1 L1 D/D Converter +INPUT -INPUT LOAD Suggested Schematic to comply with EN55022 Conducted Noise Class B recommended PCB Layout with Input Filter To comply with conducted noise according to EN55022 CLASS B following components are recommended: TMR 3-12xxWI Component Value Voltage Reference C1 10μF 25V 1812 MLCC L1 2.2μH ---- SMD Inductor, P/N: TCK-059 TMR 3-24xxWI Component Value Voltage Reference C1 6.8μF 50V 1812 MLCC L1 18μH ---- SMD Inductor, P/N: TCK-046 TMR 3-48xxWI Component Value Voltage Reference C1 2.2μF 100V 1812 MLCC L1 18μH ---- SMD Inductor, P/N: TCK-046 PDL03W SERIES Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 57 / 60 3W Single & Dual Output Input Source Impedance The power module should be connected to a low impedance input source. Highly inductive source impedance can affect the stability of the power module. Input external L-C filter is recommended to minimize input reflected ripple current. The capacitor must as close as possible to the input terminals of the power module for lower impedance. Thermal Consideration The power module operates in a variety of thermal environments. However, sufficient cooling should be provided to help ensure reliable operation of the unit. Heat is removed by conduction, convection, and radiation to the surrounding Environment. Proper cooling can be verified by measuring the point as the figure below. The temperature at this location should not exceed 100°C. When Operating, adequate cooling must be provided to maintain the test point temperature at or below 100°C. Although the maximum point Temperature of the power modules is 100°C, you can limit this Temperature to a lower value for extremely high reliability. TOP VIEW Remote ON/OFF Control The positive logic remote ON/OFF control circuit is included. Turns the module ON during a logic High on the On/Off pin and turns OFF during a logic Low. The On/Off pin is an open collector/drain logic input signal (Von/off) that referenced to GND. If not using the remote on/off feature, please open circuit between on/off pin and input pin to turn the module on. Recommended external ON/OFF Ctrl circuit and components R1 R2 1K Vcc CONTROL TTL Signal 5K1 ON/OFF PIN RIN ZD1 DC/DC Converter Logic Positive R1(K) R2(K) ZD1 Vcc = 4.5~18Vdc 0 7.5 10V, 5mA Vcc = 9~36Vdc 2.2 16 18V, 5mA Vcc = 18~75Vdc 6.8 33 36V, 5mA Measurement shown in inches and (millimeters) Temperature Measurement Point Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 58 / 60 3W Single & Dual Output Mechanical Data Pin Connection Pin Single Dual 1 -Input (GND) -Input (GND) 2 +Input (Vcc) +Input (Vcc) 3 Remote on/off Remote on/off 5 NC* / No Pin** NC* / No Pin** 6 +Output (+Vout) +Output (+Vout) 7 -Output (-Vout) Com 8 NC -Output (-Vout) Recommended Pad Layout All Dimensions in Inches (mm) Tolerance: X.XX ±0.02 (X.X ±0.5) X.XXX ±0.01 (X.XX ±0.25) Pin Pitch Tolerance: ±0.01 (±0.25) Pin Dimension Tolerance: ±0.004 (±0.1) 0.16 (4.10) 0.44 (11.2) 1 2 3 5 6 7 8 0.100(2.54) 0.86(21.80) FRONT VIEW 0.02(0.50) 0.700(17.78) .0.01(0.25) Rectangular pin 0.08(2.0) 0.36(9.10) 0.13(3.3) BOTTOM VIEW 0.02(0.50) * NC pin for standard. ** No pin for 3KV isolation. (P/N suffix ”H”) Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 59 / 60 3W Single & Dual Output Soldering Considerations Lead free wave solder profile for TMR 3WI SIP type Zone Reference Parameter Preheat zone Rise temp. speed: 3°C/ sec max. Preheat temperature: 100~130°C Actual heating Peak temperature: 250~260°C Peak time (T1+T2 time): 4~6 sec Reference Solder: Sn-Ag-Cu; Sn-Cu Hand Welding: Soldering iron: Power 90W Welding Time: 2~4 sec Temperature: 380~400°C Packaging Information 10 pc’s per TUBE Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 60 / 60 3W Single & Dual Output Order Code Note 1: Maximum value at nominal input voltage and full load of standard type. Note 2: Typical value at nominal input voltage and full load. Model Output Current Input Current Number Input Range Output Voltage Full Load Full Load(1) Eff (2) (%) TMR 3-1210WI 4.5 – 18Vdc 3.3Vdc 700mA 285mA 74 TMR 3-1211WI 4.5– 18Vdc 5.0Vdc 600mA 338mA 78 TMR 3-1209WI 4.5– 18Vdc 9.0Vdc 333mA 333mA 79 TMR 3-1212WI 4.5– 18Vdc 12.0Vdc 250mA 329mA 80 TMR 3-1213WI 4.5– 18Vdc 15.0Vdc 200mA 329mA 80 TMR 3-1221WI 4.5– 18Vdc ±5.0Vdc ±300mA 329mA 80 TMR 3-1222WI 4.5– 18Vdc ±12.0Vdc ±125mA 329mA 80 TMR 3-1223WI 4.5– 18Vdc ±15.0Vdc ±100mA 329mA 80 TMR 3-2410WI 9– 36Vdc 3.3Vdc 700mA 140mA 75 TMR 3-2411WI 9 – 36Vdc 5.0Vdc 600mA 165mA 80 TMR 3-2409WI 9 – 36Vdc 9.0Vdc 333mA 165mA 80 TMR 3-2412WI 9 – 36Vdc 12.0Vdc 250mA 160mA 82 TMR 3-2413WI 9 – 36Vdc 15.0Vdc 200mA 160mA 82 TMR 3-2421WI 9 – 36Vdc ±5.0Vdc ±300mA 167mA 79 TMR 3-2422WI 9 – 36Vdc ±12.0Vdc ±125mA 162mA 81 TMR 3-2423WI 9 – 36Vdc ±15.0Vdc ±100mA 162mA 81 TMR 3-4810WI 18 – 75Vdc 3.3Vdc 700mA 71mA 74 TMR 3-4811WI 18 – 75Vdc 5.0Vdc 600mA 82mA 80 TMR 3-4809WI 18 – 75Vdc 9.0Vdc 333mA 82mA 80 TMR 3-4812WI 18 – 75Vdc 12.0Vdc 250mA 81mA 81 TMR 3-4813WI 18 – 75Vdc 15.0Vdc 200mA 81mA 81 TMR 3-4821WI 18 – 75Vdc ±5.0Vdc ±300mA 84mA 79 TMR 3-4822WI 18 – 75Vdc ±12.0Vdc ±125mA 81mA 81 TMR 3-4823WI 18 – 75Vdc ±15.0Vdc ±100mA 81mA 81 Safety and Installation Instruction Fusing Consideration Caution: This power module is not internally fused. An input line fuse must always be used. This encapsulated power module can be used in a wide variety of applications, ranging from simple stand-alone operation to an integrated part of sophisticated power architecture. To maximum flexibility, internal fusing is not included; however, to achieve maximum safety and system protection, always use an input line fuse. The safety agencies require a slow-blow fuse with maximum rating of 1.6A for TMR 3-12xxWI modules, 1A for TMR 3-24xxWI and TMR 3-48xxWI modules. Based on the information provided in this data sheet on Inrush energy and maximum dc input current; the same type of fuse with lower rating can be used. Refer to the fuse manufacturer’s data for further information. MTBF and Reliability The MTBF of TMR 3WI-SERIES of DC/DC converters has been calculated using Bellcore TR-NWT-000332 Case I: 50% stress, operating temperature at 40°C (Ground fixed and controlled environment). The resulting figure for MTBF is 3’963’000 hours. MIL-HDBK 217F NOTICE2 FULL LOAD, operating temperature at 25°C. The resulting figure for MTBF is 1’707’000 hours. Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 1 / 23 Features • SIP package: 21.8 x 9.2 x 11.1 mm (0.86 x 0.36 x 0.44inch) • 2:1 wide input voltage of 4.5-9, 9-18,18-36 and 36-75VDC • 2 Watts output power • Low ripple & noise • UL94-V0 case potting materials • Input to output isolation: 1000Vdc, for 1 minute • Operating temperature range: up to 75°C max without derating • Continuous short circuit protection • RoHS directive compliant • External on/off control • ISO 9001 certified manufacturing facilities • UL60950-1 Recognized E188913 Applications • test equipment • Communication equipment • Computer equipment • mobile telecom equipment TMR 2 Series Application Note DC/DC Converter 4.5 to 9Vdc, 9 to 18Vdc, 18 to 36Vdc or 36 to 75 Vdc Input 3.3 to 15Vdc Single Outputs and ±5 to ±15Vdc Dual Outputs, 2 Watt E188913 Complete TMR-2 datasheet can be downloaded at: http://www.tracopower.com/products/tmr.pdf General Description The TMR 2 series offer 2 watts of output power from a 21.8 x 9.2 x 11.1 mm package up to an operating temperature of +75°C without derating and without need of any external components. This product has a 2:1 wide input voltage range of 4.5-9Vdc, 9-18Vdc, 18-36Vdc or 36-75Vdc and features an input to output isolation of 1000Vdc, indefinite short-circuit protection. All models are particularly suited to telecommunications, industrial, mobile telecom and test equipment applications. Table of contents Block Diagram P2 EMC consideration P8 Absolute maximum rating P2 Input Source Impedance P8 Output Specifications P2 & P3 Characteristic curve P9 - P20 Input Specifications P3 & P4 Thermal Consideration P21 General Specifications P5 Part number structure P21 Remote on/off control P6 EMC Specifications P21 & P22 Output over current protection P6 Mechanical data P22 Short circuitry protection P6 Safety and installation instruction P23 Solder, clearing, and drying considerations P7 MTBF and Reliability P23 Test configurations P7 & P8 Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 2 / 23 2W, Single and Dual Output Block Diagram Absolute Maximum Rating Parameter Device Min Typ Max Unit Continuous TMR 05xx TMR 12xx TMR 24xx TMR 48xx 9 18 36 75 Vdc Vdc Vdc Vdc Input Voltage Transient (100ms) TMR 05xx TMR 12xx TMR 24xx TMR 48xx 15 36 50 100 Vdc Vdc Vdc Vdc Output power 2 W Temperature coefficient ±0.1 %/°C Output Specifications Parameter Device Min Typ Max Unit Operating Output Range TMR xx10 TMR xx11 TMR xx09 TMR xx12 TMR xx13 TMR xx21 TMR xx22 TMR xx23 3.267 4.950 8.910 11.880 14.850 ±4.950 ±11.880 ±14.850 3.300 5.000 9.000 12.000 15.000 ±5.000 ±12.000 ±15.000 3.333 5.050 9.090 12.120 15.150 ±5.050 ±12.120 ±15.150 Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Output Current TMR xx10 TMR xx11 TMR xx09 TMR xx12 TMR xx13 TMR xx21 TMR xx22 TMR xx23 50 40 22 17 13 ±20 ±8 ±7 500 400 222 167 134 ±200 ±83 ±67 mA mA mA mA mA mA mA mA Max. Output Capacitive Load TMR xx10 TMR xx11 TMR xx09 TMR xx12 TMR xx13 TMR xx21 TMR xx22 TMR xx23 2200 1000 470 170 110 ±470 ±100 ±47 μF μF μF μF μF μF μF μF Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 3 / 23 2W, Single and Dual Output Output Specifications (continue) Parameter Device Min Typ Max Unit Line Regulation (LL to HL at Full Load) All 0.5 % Load Regulation (10% to 100% of Full Load) TMR xx10 Other single output Dual output ±0.85 ±0.75 ±1.00 % Cross regulation (Asymmetrical load 25% to 100% of Full Load) ±5.0 Output Ripple & Noise (20MHz bandwidth) All 50 mV pk-pk Transient Response Recovery Time (25% load step change) All 500 μS Input Specifications Parameter Device Min Typ Max Unit Input Voltage Continuous TMR 05xx TMR 12xx TMR 24xx TMR 48xx 4.5 9 18 36 5.0 12.0 24.0 48.0 9 18 36 75 Vdc Vdc Vdc Vdc Input Current (Maximum Value at Vin = Vin nom; Full Load) TMR 0510 TMR 0511 TMR 0509 TMR 0512 TMR 0513 TMR 0521 TMR 0522 TMR 0523 TMR 1210 TMR 1211 TMR 1209 TMR 1212 TMR 1213 TMR 1221 TMR 1222 TMR 1223 TMR 2410 TMR 2411 TMR 2409 TMR 2412 TMR 2413 TMR 2421 TMR 2422 TMR 2423 TMR 4810 TMR 4811 TMR 4809 TMR 4812 TMR 4813 TMR 4821 TMR 4822 TMR 4823 540 615 596 588 582 645 595 598 202 234 222 219 220 242 224 226 102 115 109 109 108 117 112 110 52 60 56 55 55 62 57 57 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 4 / 23 2W, Single and Dual Output Input Specifications (continue) Parameter Device Min Typ Max Unit Input Standby Current (Typical Value at Vin = Vin nom; No Load) TMR 0510 TMR 0511 TMR 0509 TMR 0512 TMR 0513 TMR 0521 TMR 0522 TMR 0523 TMR 1210 TMR 1211 TMR 1209 TMR 1212 TMR 1213 TMR 1221 TMR 1222 TMR 1223 TMR 2410 TMR 2411 TMR 2409 TMR 2412 TMR 2413 TMR 2421 TMR 2422 TMR 2423 TMR 4810 TMR 4811 TMR 4809 TMR 4812 TMR 4813 TMR 4821 TMR 4822 TMR 4823 60 55 55 75 40 75 75 90 20 25 25 30 30 50 40 40 10 10 15 15 15 15 20 20 10 10 10 10 10 10 10 12 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 5V input (100μF) 12V input (100μF) 24V input (10μF) Input reflected ripple current (It will not damage the device if the capacitor on the input is not equipped) 48V input (10μF) 400 150 380 170 mA pk-pk mA pk-pk mA pk-pk mA pk-pk Start up time Power up (nominal Vin and constant resistive load power up) Remote ON/OFF 1 1 mS mS Remote ON/OFF Control (See Page 13) DC-DC ON DC-DC OFF All 4 Open 8 mA Remote Off Input Current All 2.5 mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 5 / 23 2W, Single and Dual Output General Specifications Parameter Device Min Typ Max Unit Efficiency at Vin nom and full load (Please see the testing configurations part) TMR 0510 TMR 0511 TMR 0509 TMR 0512 TMR 0513 TMR 0521 TMR 0522 TMR 0523 TMR 1210 TMR 1211 TMR 1209 TMR 1212 TMR 1213 TMR 1221 TMR 1222 TMR 1223 TMR 2410 TMR 2411 TMR 2409 TMR 2412 TMR 2413 TMR 2421 TMR 2422 TMR 2423 TMR 4810 TMR 4811 TMR 4809 TMR 4812 TMR 4813 TMR 4821 TMR 4822 TMR 4823 65 69 71 72 73 66 71 71 72 75 79 80 80 73 78 78 71 76 80 80 81 75 78 80 70 74 78 80 79 75 77 77 % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % Isolation resistance All 109 Ω Isolation Capacitance All 300 1000 pF Switching Frequency (full load to minimum load) All 100 650 KHz Weight All 4.8 g MTBF (please see the MTBF and reliability part) All 5.107×106 hours Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 6 / 23 2W, Single and Dual Output Vout Pi (Input Power) Iocp Remote On/Off Control Only one type of remote on/off control is available for TMR. The module will turn on during the ctrl pin left open or high impedance between ctrl pin and -Vin pin. The module will turn off if the control pin is applied with a current of 4~8mA. In off condition the input current is app. 1mA max. Positive Logic: Negative Logic: Output over current protection When excessive output currents occur in the system, circuit protection is required on all converters. Normally, overload current is maintained at approximately 115~175% percent of rated current. The TMR converters have a fold-back over current protection. Fold back current protection reduces the load current during over current condition. The figure below shows a typical curve. Since the over current protection is a fold-back characteristic the highest power dissipation occurs at point S. During start-up this product provides less output current, hence the output rises slower, or the power supply may not start up at all if the load current during start up is larger than the fold back current. Short Circuitry Protection Continuous, hiccup and auto-recovery mode. During short circuit, converter will shut down and will switch on again to detect if the short circuit is still present or not. The average current during this condition will be very low and the device will be safe in short circuit condition. Due to that is the TMR converters indefinite short circuit protected. ● ● +Input -Input 6mA current Source Ctrl 1KΩ DC-DC OFF +Input -Input 6mA current Source Ctrl 1KΩ DC-DC ON S (Iout, max, Pi, max) Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 7 / 23 2W, Single and Dual Output Solder, clearing, and drying considerations Soldering Flow (wave) soldering: 250°C ±10°C less than10 seconds (see below) Soldering iron: 370°C ±10°C less than 5 seconds Note: the pin of this product is Tin coated. To assure the solder-ability, modules should be kept in their original shipping containers to provide adequate protection. Also, the storage environment shall be well controlled to protect any oxidation. Cleaning process In aqueous cleaning, it is preferred to have an in-line cleaner system consisting of several cleaning stages (pre-wash, wash, rinse, final rinse, and drying). Deionize (DI) water is recommend for aqueous cleaning; the minimum resistive level is 1MΩ-cm. Tap-water quality varies per region in terms of hardness, chloride, and solid contents; therefore, the use of tap water is not recommended for aqueous cleaning. Drying The drying section of the cleaner system should be equipped with blowers capable of generating 1000cfm -1500cfm of air so that the amount of rinse water left to be dried off with heat is minimal. Handheld air guns are not recommended due the variability and consistency of the operation. Note: after post-wash, the marking (date code) of converter may fall off. These only impacts the appearance and do not affect the operation of the module. Testing Configurations Input reflected-ripple current measurement test up TMR 05xx and TMR 12xx Component Value Voltage Reference C 100μF 50V Aluminium Electrolytic Capacitor TMR 24xx and TMR 48xx Component Value Voltage Reference C 10μF 100V Aluminium Electrolytic Capacitor Peak-to-peak output ripple & noise measurement test up Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 8 / 23 2W, Single and Dual Output Testing Configurations (continue) Output voltage and efficiency measurement test up Note: All measurements are taken at the module terminals. % 100 ×        × × = in in o o V I V I Efficiency EMC considerations Suggested Schematic for EN55022 Conducted Emission Class B Limits To comply with EN55022 CLASS B conducted emissions the following components are recommended: TMR 05xx and TMR 12xx Component Value Voltage Reference C1 22 μF 25V 1812 MLCC Capacitor L1 3.3 μH 2.0A / 0.06Ω / 0504 SMD Inductor, P/N: TCK-044 TMR 24xx Component Value Voltage Reference C1 4.7 μF 50V 1812 MLCC Capacitor L1 12 μH 1.4A / 0.12Ω / 0504 SMD Inductor, P/N: TCK-062 TMR 48xx Component Value Voltage Reference C1 2.2 μF 100V 1812 MLCC Capacitor L1 27 μH 0.9A / 0.2Ω / 0504 SMD Inductor, P/N: TCK-063 Input Source Impedance The power module should be connected to a low impedance input source. Highly inductive source impedance can affect the stability of the power module. Input external L-C filter is recommended to minimize input reflected ripple current. The capacitor should be equipped as close as possible to the input terminals of the power module for lower impedance. +Vin -Vin +Vout -Vout C1 L1 D/D Converter +INPUT -INPUT LOAD Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 9 / 23 2W, Single and Dual Output Characteristic Curve Efficiency a. Efficiency with load change under different line condition at room temperature TMR 0510 15.00 25.00 35.00 45.00 55.00 65.00 75.00 50 100 150 200 250 300 350 400 450 500 lout (mA ) Efficiency (%) TMR 1213 25.00 35.00 45.00 55.00 65.00 75.00 85.00 13 27 40 54 67 80 94 107 121 134 lout (mA ) Efficiency (%) TMR 4810 20.00 30.00 40.00 50.00 60.00 70.00 80.00 50 100 150 200 250 300 350 400 450 500 lout (mA ) Efficiency (%) 9V 12V 18V 4.5V 5V 9V 36V 48V 75V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 10 / 23 2W, Single and Dual Output TMR 1221 15.00 25.00 35.00 45.00 55.00 65.00 75.00 20 40 60 80 100 120 140 160 180 200 lout (mA ) Efficiency (%) TMR 2422 25.00 35.00 45.00 55.00 65.00 75.00 85.00 8 17 25 33 42 50 58 66 75 83 lout (mA ) Efficiency (%) TMR 4823 20.00 30.00 40.00 50.00 60.00 70.00 80.00 7 13 20 27 34 40 47 54 60 67 lout (mA ) Efficiency (%) 9V 12V 18V 18V 24V 36V 36V 48V 75V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 11 / 23 2W, Single and Dual Output b. Efficiency at input voltage change under different load condition at room temperature TMR 0510 15.00 25.00 35.00 45.00 55.00 65.00 75.00 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 Vin (V) Efficiency (%) TMR 1213 25.00 35.00 45.00 55.00 65.00 75.00 85.00 9 10 11 12 13 14 15 16 17 18 Vin (V) Efficiency (%) TMR 4810 20.00 30.00 40.00 50.00 60.00 70.00 80.00 36V 40V 44V 48V 52V 56V 60V 64V 68V 75V Vin(V) Eff(%) 500mA 250mA 50mA 134mA 67mA 13mA 500mA 250mA 50mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 12 / 23 2W, Single and Dual Output TMR 1221 15.00 25.00 35.00 45.00 55.00 65.00 75.00 85.00 9 10 11 12 13 14 15 16 17 18 Vin (V) Efficiency (%) TMR 2422 25.00 35.00 45.00 55.00 65.00 75.00 85.00 18 20 22 24 26 28 30 32 34 36 Vin (V) Efficiency (%) TMR 4823 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 36 40 44 48 52 56 60 64 68 75 Vin (V) Efficiency (%) 200mA 100mA 20mA 83mA 42mA 8mA 67mA 34mA 7mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 13 / 23 2W, Single and Dual Output Power dissipation curve TMR 0510 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 50 100 150 200 250 300 350 400 450 500 lout (mA ) Pd (W) TMR 1213 0.200 0.300 0.400 0.500 0.600 13 27 40 54 67 80 94 107 121 134 lout (mA ) Pd (W) TMR 4810 0.200 0.300 0.400 0.500 0.600 0.700 0.800 50 100 150 200 250 300 350 400 450 500 lout (mA ) Pd (W) 9V 5V 4.5V 18V 12V 9V 75V 48V 36V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 14 / 23 2W, Single and Dual Output TMR 1221 0.300 0.400 0.500 0.600 0.700 0.800 0.900 20 40 60 80 100 120 140 160 180 200 lout (mA ) Pd (W) TMR 2422 0.100 0.200 0.300 0.400 0.500 0.600 0.700 8 17 25 33 42 50 58 66 75 83 lout (mA ) Pd (W) TMR 4823 0.200 0.300 0.400 0.500 0.600 0.700 0.800 7 13 20 27 34 40 47 54 60 67 lout (mA ) Pd (W) 75V 48V 36V 36V 24V 18V 18V 12V 9V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 15 / 23 2W, Single and Dual Output Output ripple & noise TMR 0510 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Output Ripple & Noise = 26.8mV Output Ripple & Noise = 20.8mV Output Ripple & Noise = 14.8mV TMR 1213 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Output Ripple & Noise = 25.2mV Output Ripple & Noise = 14.0mV Output Ripple & Noise = 11.6mV TMR 4810 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Output Ripple & Noise = 20.0mV Output Ripple & Noise = 13.6mV Output Ripple & Noise = 10.8mV Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 16 / 23 2W, Single and Dual Output TMR 1221 Vin min, Full Load Vin nom, Full Load Vin max, Full Load +Vout = 18.8mV / – Vout = 14.4mV + Vout = 17.6mV / –Vout = 14.0mV + Vout = 17.6mV / – Vout = 15.2mV TMR 2422 Vin min, Full Load Vin nom, Full Load Vin max, Full Load + Vout = 30.8mV / – Vout = 19.2mV + Vout = 25.6mV / – Vout = 18.0mV + Vout = 18.4mV / – Vout = 12.8mV TMR 4823 Vin min, Full Load Vin nom, Full Load Vin max, Full Load + Vout = 26.8mV / – Vout = 24.4mV + Vout = 14.8mV / – Vout = 14.0mV + Vout = 12.8mV / – Vout = 10.4mV Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 17 / 23 2W, Single and Dual Output Transient Peak and Response TMR 0510 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 85.0mV Transient Peak 81.0mV Transient Peak 75.0mV Transient Response 332.0μS Transient Response 328.0μS Transient Response 316.0μS TMR 1213 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 123.0mV Transient Peak 102.0mV Transient Peak 88.0mV Transient Response 488μS Transient Response 488μS Transient Response 488μS TMR 4810 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 79.0mV Transient Peak 68.0mV Transient Peak 63.0mV Transient Response 316μS Transient Response 316μS Transient Response 316μS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 18 / 23 2W, Single and Dual Output TMR 1221 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 270mV Transient Peak 246mV Transient Peak 240mV Transient Response 496μS Transient Response 480μS Transient Response 472μS TMR 2422 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 152mV Transient Peak 133mV Transient Peak 124mV Transient Response 320μS Transient Response 328μS Transient Response 320μS TMR 4823 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 119mV Transient Peak 100mV Transient Peak 93mV Transient Response 400μS Transient Response 384μS Transient Response 392μS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 19 / 23 2W, Single and Dual Output Start-up Time and Rise Time TMR 0510 Vin nom, Full Load Vin nom, Full Load Rise Time = 247.6μS Start-up Time = 408.0μS TMR 1213 Vin nom, Full Load Vin nom, Full Load Rise Time = 530.3μS Start-up Time = 640.0μS TMR 4810 Vin nom, Full Load Vin nom, Full Load Rise Time = 176.3μS Start-up Time = 240.0μS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 20 / 23 2W, Single and Dual Output TMR 1221 Vin nom, Full Load Vin nom, Full Load Rise Time = 297.2μS Start-up Time = 640.0μS TMR 2422 Vin nom, Full Load Vin nom, Full Load Rise Time = 324.8uS Start-up Time = 432.0uS TMR 4823 Vin nom, Full Load Vin nom, Full Load Rise Time=1.056mS Start-up Time= 1.180mS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 21 / 23 2W, Single and Dual Output Thermal Consideration The power module operates in a variety of thermal environments. However, sufficient cooling should be provided to help ensure reliable operation of the unit. Heat is removed by conduction, convection, and radiation to the surrounding Environment. Proper cooling can be verified by measuring the point as shown in the figure below. The temperature at this location should not exceed 100°C. During performance, adequate cooling must be provided to maintain the test point temperature at or below 100°C. Although the maximum point Temperature of the power modules is 100°C, you can limit the case temperature to a lower value for high reliability. TOP VIEW Part Number Structure TMR 4812 EMC Specifications Contact discharge Air discharge level test voltage (KV) level test voltage (KV) 1 ±2 1 ±2 2 ±4 2 ±4 3 ±6 3 ±8 EN61000-4-2 ESD (performance criteria B) 4 ±8 4 ±15 level test field strength (V/m) 1 1 2 3 EN61000-4-3 RS (performance criteria B) 3 10 Input Voltage Range: 05xx : 4.5~9V 12xx : 9~18V 24xx : 18~36V 48xx : 36~75V Output Voltage 10 : 3.3V 11 : 5V 09 : 9V 12 : 12V 13 : 15V 21 : ±5V 22 : ±12V 23 : ±15V TEMPERATURE MEASURE POINT Measurement shown in inches and (millimeters) Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 22 / 23 2W, Single and Dual Output EMC Specifications (continue) open circuit output test voltage ±10% level power line 1 ±0.5KV 2 ±1.0KV 3 ±2.0KV EN61000-4-4 EFT (performance criteria B) 4 ±4.0KV level open circuit output test voltage ±10% 1 ±0.5KV 2 ±1.0KV 3 ±2.0KV EN61000-4-5 Surge (performance criteria B) 4 ±4.0KV level voltage level(EMF) 1 1V/rms 2 3V/rms EN61000-4-6 CS (performance criteria B) 3 10V/rms Mechanical Data .0.01 (0.32) Rectangular pin 0.08 (2.01)±0.5 0.36 0.13 (3.20) BOTTOMVIEW All Dimensions in Inches (mm) Tolerance: X.XX ±0.02 (X.X ±0.5) X.XXX ±0.01(X.XX ±0.25) Pin Pitch Tolerance ±0.02(0.5) 0.16 (4.10)±0.5 0.02 (0.50)±0.05 0.44 1 2 3 5 6 7 8 0.10(2.54) 0.86(21.80) FRONT VIEW 0.02 (0.50) 0.70(17.78) PIN CONNECTION PIN SINGLE 1 - INPUT 2 + INPUT 3 CTRL 5 NC 6 + OUTPUT 7 - OUTPUT 8 NC DUAL OUTPUT - INPUT + INPUT CTRL NC + OUTPUT COM -OUTPUT Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 23 / 23 2W, Single and Dual Output Safety and Installation Instruction Isolation consideration The TMR series features 1.0k Volt DC isolation for 60 seconds from input to output, input to case, and output to case. The input to output resistance is greater than 109 ohms. Nevertheless, if the system using the TMR converter needs to get safety agency approval, certain rules must be followed in the design of the system. In particular, all of the creepage and clearance requirements of the end-use safety requirement must be observed. These documents include UL60950-1, EN60950-1 and CSA 22.2-60950, although specific applications may have other or additional requirements. Fusing Consideration Caution: The TMR converter is not internally fused. An input line fuse must always be used. This encapsulated power module can be used in a wide variety of applications, ranging from simple stand-alone operation to an integrated part of a sophisticated power architecture. To maximum flexibility, internal fusing is not included; however, to achieve maximum safety and system protection, always use an input line fuse. The safety agencies require a slow-blow fuse with maximum rating of 6.3 A. Based on the information provided in this data sheet on inrush energy and maximum dc input current, the same type of fuse with lower rating can be used. Minimum Load Requirement 25% (of full load) minimum load required to maintain a stable output voltage and to comply with the published specifications. The TMR Series is not getting damaged at no load or low load conditions but at loads below 25% a proper and accurate regulation of the output voltage cannot be ensured. The output voltage drops by app. 10%. MTBF and Reliability The MTBF of TMR series has been calculated according to: 1. MIL-HDBK-217F under the following conditions: Nominal Input Voltage and GB Iout = Iout max TA = +25°C The resulting figure for MTBF is 2.399× 106 hours. 2. Bell-core TR-NWT-000332 Case I: 50% stress, Operating Temperature at 40 ℃ (Ground fixed and controlled environment) The resulting figure for MTBF is 5.107× 106 hours. http://www.tracopower.com Page 1 of 13 Industrial Power Supplies TIS Series, 50–600 Watt Features ◆ Switch mode power supplies for DIN-rail mount ◆ 6 power ranges with 2, 3, 6, 12, 20 and 24 A output current (24 VDC models) ◆ Selectable 115/230 VAC input ◆ Very low ripple and noise ◆ EMI complies with EN 61000-6-3 and EN 61000-6-4 ◆ Operating temp. range –25°C to +70°C ◆ For system operation available with built-in functions: RED: Redundancy module for N+1 Systems with true current sharing SIG: Signal module with AC-powerfail, power good signal and external On/Off control UDS: DC-UPS module for uninterruptable battery backed-up power systems ◆ Worldwide safety approvals incl. class I, div. 2 location ◆ Easy snap-on mount on DIN-rails or chassis mount ◆ 3-year product warranty The switching power supplies of the TIS series have been particularly designed for applications in industrial process control systems and with machine tools. Excellent specifications and high immunity against electrical disturbances guarantee reliable power for sensitive loads in rugged industrial environments. With the help of optional function modules specific requirements for system applications can be easily realized with a standard model. With the UDS module the power supplies can be extended to a perfect DC-UPS with automatic battery- backup. This function is very often required in applications where a time delayed shutdown of a system is necessary. To monitor and control the power supply a signal module can be installed. For parallel operation with active power sharing a redundancy option is available. This flexibility makes the TIS series power supplies a cost effective solution for many industrial applications. Order Code Input Voltage Output Power Output Voltage Output Current (includes terminal plugs) nom. max. nom. max. TIS 50-112 115–240 VAC 50 W 12 VDC 3.5 A TIS 50-124 universal input 24 VDC 2.0 A TIS 75-112 115/230 VAC 12 VDC 6.0 A TIS 75-124 selectable 75 W 24 VDC 3.0 A TIS 75-148 48 VDC 1.5 A TIS 150-124 115/230 VAC 150 W 24 VDC 6.0 A TIS 150-148 selectable 48 VDC 3.0 A TIS 300-124 115/230 VAC 24 VDC 12.0 A TIS 300-148 selectable 300 W 48 VDC 6.0 A TIS 300-172 72 VDC 4.2 A TIS 500-124-115 115 VAC 500 W 24 VDC 20.0 A TIS 500-124-230 230 VAC 500 W 24 VDC 20.0 A TIS 600-124 24 VDC 24.0 A TIS 600-148 115/230 VAC 600 W 48 VDC 12.0 A TIS 600-172 selectable 72 VDC 8.5 A Models CB Scheme (LVD) UL 60950-1 UL 508 UL 1604 http://www.tracopower.com Page 2 of 13 Industrial Power Supplies TIS Series 50–600 Watt Input Specifications Input voltage range TIS 50: 93 – 264 VAC TIS 75, 150, 300, 600: 93 – 132 VAC / 187 – 264 VAC TIS 500-124-230. 187 – 264 VAC TIS 500-124-115: 93 – 132 VAC Input frequency 47 – 63 Hz Input current at full load (typ.) at 115 VAC at 230 VAC TIS 50: 0.85 A 0.50 A TIS 75: 1.3 A 0.75 A TIS 150: 2.7 A 1.6 A TIS 300: 4.9 A 2.9 A TIS 500: 6.0 A 4.3 A TIS 600: 7.0 A 5.0 A Recommended circuit breaker, TIS 50: 5.0 A characteristic C TIS 75: 5.0 A or fuse, slow blow typ TIS 150: 10.0 A TIS 300: 15.0 A TIS 500: 15.0 A TIS 600: 20.0 A Output Specifications Output voltage adj. range 12 VDC models: 12 – 14 VDC 24 VDC models: 24 – 28 VDC 48 VDC models: 48 – 52 VDC 72 VDC models: 60 – 76 VDC Regulation – Input variation 0.2 % – Load variation (10–90%) TIS 50, TIS 75, TIS 150: 1.0 % TIS 300, TIS 500, TIS 600: 0.3 % (2.0 % in parallel operation) Ripple and noise (20MHz bandwidth) <50 mV pk-pk Electronic short circuit protection current limitation at 110 % typ. (constant current, automatic restart) Over voltage protection, trigger point at 140 % typ. Vout nom. Hold-up time 115 VAC 230 VAC TIS 50 ... TIS 300: min. 25 ms min. 30 ms TIS 500: min. 20 ms min. 40 ms TIS 600: min. 15 ms min. 25 ms http://www.tracopower.com Page 3 of 13 General Specifications Temperature ranges – Operating (ambient temp.) –25°C to +70°C – Derating above 50°C (122°F) 2 %/K – Storage (non operating) –25°C to +85°C Humidity (non condensing) 95 % rel. H max. Pollution degree 2 Temperature coefficient 0.02 %/K Switching frequency 80 kHz typ. (pulse width modulation) Efficiency TIS 50 ... TIS 300: 85 % typ. TIS 500: 90 % typ. TIS 600: 90 % typ. Isolation according to IEC/EN 60950, UL 60950, UL 508 Reliability, calculated MTBF TIS 50/75: 450’000 h / 420’000 h (MIL-HDBK-217F, at +25°C, ground benign) TIS 150/300: 420’000 h / 360’000 h TIS 500/600: 340’000 h / 300’000 h Safety standards IEC/EN 60950-1 (SELV, except 72 VDC models) UL/cUL 60950-1, UL 508, UL/cUL 1604 Safety approvals – CB report for IEC 60950 www.tracopower.com/products/tis-cb.pdf – UL approvals UL/cUL 60950, File e181381 UL/cUL 508, File e210002 UL/cUL 1604, File e213613 not for TIS 50 & 500 (Class I, Div. 2, Groups A, B, C and D hazardous locations) www.ul.com -> certifications – CSA certificate (UL 60950-1, CSA 60950-1) www.tracopower.com/products/tis-csa.pdf Electromagnetic compatibility (EMC), Emissions EN 61000-6-3 / EN 61000-6-4 – Conducted RI suppression on input EN 55011 class B, EN 55022 class B, FCC part 15, level B – Radiated RI suppression EN 55011 class A, EN 55022 class A, FCC part 15, level A Electromagnetic compatibility (EMC), Immunity EN 61000-6-2 – Electrostatic discharge (ESD) IEC/EN 61000-4-2 4 kV/8 kV – Radiated RF field immunity IEC/EN 61000-4-3 10 V/m – Electrical fast transient / burst immunity IEC/EN 61000-4-4 2 kV – Surge immunity IEC/EN 61000-4-5 2 kV/4 kV – Immunity to conducted RF disturbances IEC/EN 61000-4-6 10 V – Power frequency field immunity IEC/EN 61000-4-8 30 A/m Safety class degree of electrical protection 1 (IEC 536) Case protection IP 20 (IEC 529) Environment – Vibration IEC 60068-2-6; 1 gn, 200 sweeps, each axis – Shock IEC 60068-2-27; 15 gn, 11 ms, each axis Enclosure material aluminium (chassis) / zinc plated steel (cover) Mounting (snap-on with self locking spring) for 35 mm DIN-rails as per EN 50022 Connection detachable screw terminal block (plugs included) (TIS 600: fixed screw terminal block) Industrial Power Supplies TIS Series 50–600 Watt Instruction manual can be downloaded under: www.tracopower.com/products/tis-manual.pdf All specifications valid at nominal input voltage, full load and +25 °C after warm-up time unless otherwise stated. http://www.tracopower.com Page 4 of 13 Power Supplies with Redundancy Function With this option a parallel operation of up to 5 units is possible. Decoupling diodes and current share lines allow to build true N +1 redundant systems with active current sharing for all units. This function also includes an alarm relay to signal a single unit failure. This option is available for TIS 150 W, TIS 300 W and TIS 600 W models. Please note: This option cannot be combined with other options. Industrial Power Supplies TIS Series 50–600 Watt Order Code Input Voltage Output Power Output Voltage Output Current (includes terminal plugs) max. nom. max. TIS 150-124 RED 115/230 VAC 150 W 24 VDC 6.0 A TIS 150-148 RED selectable 48 VDC 3.0 A TIS 300-124 RED 115/230 VAC 300 W 24 VDC 12 A TIS 300-148 RED selectable 48 VDC 6.0 A TIS 600-124 RED 115/230 VAC 600 W 24 VDC 24 A TIS 600-148 RED selectable 48 VDC 12 A Models I-Sense Regulator L Con1 Pin3 N 115/230VAC Con1 Pin1 AC Con1 Pin2 DC Common Unit OK Unit OK Con3 - Pin1 Bus Indicator Con2 - Pin1/2 Con2 - Pin3/4 V-Sense +Vout Current Shareline Unit OK Con3 - Pin4 Con3 - Pin3 Con3 - Pin2 -Vout 24/48VDC Specifications Rating per relay contact 60 VDC /0.36 A max. Instruction manual for RED option can be downloaded under: http://www.tracopower.com/products/tis-red_manual.pdf http://www.tracopower.com Page 5 of 13 Power Supplies with Powerfail Functions These models provide 3 functions required in many process control system applications: ◆ AC-Powerfail signal (relay contact) ◆ Power Good signal (relay contact) ◆ Remote On/Off Industrial Power Supplies TIS Series 50–600 Watt Order Code Input Voltage Output Power Output Voltage Output Current (includes terminal plugs) max. nom. max. TIS 150-124 SIG 115/230 VAC 150 W 24 VDC 6.0 A TIS 150-148 SIG selectable 48 VDC 3.0 A TIS 300-124 SIG 115/230 VAC 300 W 24 VDC 12 A TIS 300-148 SIG selectable 48 VDC 6.0 A TIS 600-124 SIG 115/230 VAC 600 W 24 VDC 24 A TIS 600-148 SIG selectable 48 VDC 12 A Models Remote ON/OFF L 115/230VAC Con1 Pin1 N Con1 Pin2 Con1 Pin3 AC DC Mains Fail Detection Mains OK Remote ON/OFF +Vout Con2 - Pin3/4 -Vout 24/48VDC Common AC-Powerfail Con3 - Pin2 Con3 - Pin7 Con3 - Pin6 Con2 - Pin1/2 Output OK Power Good Detection Power Good Common Power Good Power Good Con3 - Pin5 Con3 - Pin4 Con3 - Pin3 + - Con3 - Pin1 (Relay A) (Relay B) Specifications Power Good signal trigger point models with 24 Vout: >22.8 VDC ±0.5 V relay B closed (pin 4 – pin 3) models with 48 Vout: >45.6 VDC ±1.0 V relay B closed (pin 4 – pin 3) AC-Powerfail signal Vin <93 resp. <187 VAC relay A closed (pin 7 – pin 6) Raiting per relay contact 60 VDC /0.36 A max. Remote On/Off – On short circuit con 3 pin 1 and pin 2 – Off open circuit con 3 pin 1 and pin 2 Instruction manual for SIG option can be downloaded under: http://www.tracopower.com/products/tis-sig_manual.pdf http://www.tracopower.com Page 6 of 13 DC-UPS-System Industrial Power Supplies TIS Series 50–600 Watt In addition to the standard power supply function, these models include a professional battery management system to charge and monitor an external battery. In the event of a power failure the battery is switched automatically and without any interruption to the DC output. Once mains power is available again, the battery is switched off. The backup time is limited only by battery capacity and load. Charge current and voltage can be adjusted to values as required by battery type. Power fail and low battery alarm signals are available via two independent relay contacts. During normal operation the battery status is monitored by periodically loading the battery for a short time. If a cell resistance is high, there is a relay alarm is available. The battery is fully protected under any operational conditions. The power supply is short circuit protected even in battery backup operation but, for safety reasons, the battery should be fitted with a fast blow fuse. Battery mode can be activated by interconnecting pin 7 and 8. Complete external battery packs (3.2 Ah or 7 Ah standard) with lead batteries and circuit breaker are available (see page 8). Order Code 1) Input Voltage Output Power Output Voltage Output Current 2) max. nom. max. TIS 300-124 UDS 115/230 VAC 300 W 24 VDC 12 A selectable TIS 600-124 UDS 115/230 VAC 600 W 24 VDC 24 A selectable Models 1) Includes terminal plugs, does not include batteries 2) reduce max. output current by battery charging current http://www.tracopower.com Page 7 of 13 DC-UPS-System Industrial Power Supplies TIS Series 50–600 Watt Battery ON/OFF Con4 Pin7 L 115/230VAC Con1 Pin1 Con4 Pin8 N Con1 Pin2 Battery - Battery + Con1 Pin3 Con3 - Pin1 Con3 - Pin2 AC DC Mains Fail Detection Battery Test Battery OK Battery Low / failure Common Low Battery Con4 - Pin4 AC-Powerfail Con4 - Pin6 Con4 - Pin5 Battery Switch Logic I V Battery Charger +Vout Con2 - Pin3/4 -Vout 24VDC Common AC-Power OK AC-Powerfail Con4 - Pin3 Con4 - Pin2 Con4 - Pin1 Con2 - Pin1/2 Output OK VBat>18V Bat ON/OFF Mains Fail (Relay B) (Relay A) Specifications Charging current (factory set) TIS 300-124 UDS: 1.2 A TIS 600-124 UDS: 2.4 A Adjustment range of charging current TIS 300-124 UDS: 0.15 – 1.5 A TIS 600-124 UDS: 0.25 – 2.5 A Holding current for charged battery at voltage 27.3 VDC <50 mA Overload or short circuit during battery operation system switches off AC-Powerfail signal Vin <93 or <187 VAC relay A closed (pin 2 – pin 3) Low battery signal – Battery voltage below 22 V relay B closed (pin 5 – pin 6) – Raiting per relay contact 60 VDC /0.36 A max. During battery charge operation output current reduction by 1.4 x battery charge current Instruction manual for UDS option can be downloaded under: http://www.tracopower.com/products/tis-uds_manual.pdf http://www.tracopower.com Page 8 of 13 Battery-Pack for DC-UPS Systems The battery pack contains high quality, maintenance free lead-acid batteries with 3.2 Ah or 7.0 Ah capacity. The batteries are fixed together with a re-settable electronic fuse on a solid mounting frame. Together with power supply models TIS 300-124 UDS or TIS 600-124 UDS the battery pack provides a complete and reliable DC-UPS system. Backup time depends on load current and battery capacity. Industrial Power Supplies TIS Series 50–600 Watt Order Code Battery Voltage Battery Capacity Permissable Charge (25 °C, 20 h-rate) Current max. TIS 24-32AP 24 VDC 3.2 Ah 1.2 A TIS 24-70AP 24 VDC 7.0 Ah 2.4 A Models Specifications Max. charge voltage 27 – 27.6 VDC Temperature coefficient –36 mV/°C Temperature range – at charge operation –15°C to +50°C – at load operation –20°C to +60°C – Storage –20°C to +60°C Average lifetime on standby operation at tA =20°C 4 – 5 years (Limited Warranty on Battery) Cable length 1.0 m Cable diameter TIS 24-32 AP: 2.5 mm2 (AWG 12) TIS 24-70 AP: 4.0 mm2 (AWG 11) Weight TIS 24-32 AP: 2.9 kg (6.4 lb) TIS 24-70 AP: 4.1 kg (9.1 lb) Recommended combinations TIS 24-32 AP: TIS 300-124 UDS (power supplies) TIS 24-70 AP: TIS 600-124 UDS http://www.tracopower.com Page 9 of 13 100.0 (3.94) 75 (2.95) 37.5 (1.48) 74.0 (2.91) 56.7 (2.23) 26 (1.02) 5 (0.2) 31.5 (1.24) 10 (0.39) TIS 50-112 Input 115/230 VAC 1,2/0,7 A L N 12 VDC 3,5 A Output + – Industrial Power Supply Model DC-ON adj 114.6 (4.51) 90 (3.54) 45 (1.77) 10 (0.39) 56.7 (2.23) 86.5 (3.4) 34 (1.34) 5 (0.2) 39.5 (1.56) TIS 75-112 Input 115/230 VAC 1,7/0,9 A L N 12 VDC 6 A Output + – Industrial Power Supply Model DC-ON adj 114.6 (4.51) 10 (0.39) 157 (6.18) 56.7 (2.23) 38.5 80 (3.15) (1.52) 86.5 (3.4) 34 (1.34) 5 (0.2) 39.5 (1.56) TIS 150-124 Input 115/230 50/60Hz 3,7/1,7 A N L 24 VDC / 6 A Output + – Industrial Power Supply Model DC-ON Case Dimensions Industrial Power Supplies TIS Series 50–600 Watt TIS 50 models TIS 75 models Weight: 0.48 kg (1.06 lb) Weight: 0.80 kg (1.76 lb) TIS 150 models Weight: 0.41 kg (0.9 lb) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) TIS PLUG-1 Connector Set for TIS 50/ 75/ 150 TIS PLUG-1-RED Connector Set for TIS 150-1xx RED Connectors ( Included in shipment) http://www.tracopower.com Page 10 of 13 114.6 (4.51) 10 (0.39) 83 (3.27) 38.5 (1.52) 130 (5.12) 83 (3.27) 207 (8.15) 91.5 (3.6) (1.36) 34.5 34 (1.34) 5 (0.2) 39.5 (1.56) TIS300-172 Input 115/230 50/60Hz 5,4/3,3 A N L 72 VDC / 4 A Output + – Industrial Power Supply Model DC-ON + – 83 (3.27) 130 (5.12) 220 (8.66) 46 (1.81) 130 (5.12) 10 (0.39) (0.2) 94 (3.7) 41.5(1.63) 5 47 (1.85) TIS 500-124-230 Input 230 VAC 50/60Hz 5,3 A N L 24 VDC / 20 A Output + – Industrial Power Supply Model DC-ON + – Case Dimensions Industrial Power Supplies TIS Series 50–600 Watt TIS 300 models Weight: 1.4 kg (3.09 lb) Weight: 1.9 kg (4.19 lb) TIS 500 models Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) TIS PLUG-3 Connector Set for TIS 300 TIS PLUG-3-RED Connector Set for TIS 300-1xx RED TIS PLUG-3-UDS Connector Set for TIS 300-1xx UDS TIS PLUG-5 Connector Set for TIS 500 Connectors ( Included in shipment) http://www.tracopower.com Page 11 of 13 6.8 (0.27) 82.8 (3.26) 177.2 (6.98) 32 (1.26) 120.2 (4.73) 82.6 (3.25) 179 (7.05) 243 (9.57) TIS 600-124 Input 115/230 VAC 50/60Hz 10,5/6,4 A N L 24 VDC / 20 A Output – + Industrial Power Supply Model – + Outline Dimensions mm (inches) Industrial Power Supplies TIS Series 50–600 Watt TIS 600 models Weight: 2.0 kg (4.41 lb) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) TIS PLUG-6-RED Connector Set for TIS 600-1xx RED TIS PLUG-6-UDS Connector Set for TIS 600-1xx UDS Connectors ( Included in shipment) http://www.tracopower.com Page 12 of 13 Optional Mounting Systems Industrial Power Supplies TIS Series 50–600 Watt Wall mounting kit B A C 7.5 (0.30) D E 4.6 (0.18) TIS 75 MK-75 37 (1.46) 14.5 (0.57) – 134.5 (5.30) 150.5 (5.93) TIS 150 MK-150 132 (5.20) 13.5 (0.53) 105 (4.13) 134.5 (5.30) 150.5 (5.93) TIS 300 MK-300 132 (5.20) 13.5 (0.53) 105 (4.13) 134.5 (5.30) 150.5 (5.93) TIS 500 MK-500 132 (5.20) 13.5 (0.53) 105 (4.13) 134.5 (5.30) 150.5 (5.93) TIS 600 MK-600 190 (7.48) 37.5 (1.48) 115 (4.53) 197.0 (7.76) 207.0 (8.15) Models Order code A B C D E Rugged DIN-Rail mounting kit 4.2 (0.17) 25 (0.98) 50.1 (1.97) A B C countersink M4 TIS 150 RMK-150 150 (5.91) 115 (4.53) 35 (1.38) TIS 300 RMK-300 200 (7.87) 165 (6.50) 35 (1.38) TIS 500 RMK-300 200 (7.87) 165 (6.50) 35 (1.38) TIS 600 standard 180 (7.09) 165 (6.50) 15 (0.59) Models Order code A B C Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Page 13 of 13 Outline Dimensions mm (inches) Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Industrial Power Supplies TIS Series 50–600 Watt TIS 24-32AP Weight (incl. batteries): TIS 24-32AP 2.9 kg (6.4 lb) TIS 24-70AP TIS 24-70AP 4.1 kg (9.1 lb) A B A B 204 (8.03) 184 (7.24) 69 (2.72) Detail B Detail A 9 (0.35) 5.8 (0.23) 12 (0.47) 14 (0.55) 7 (0.28) 100 (3.94) 135 (5.14) 7 (0.28) B A 272 (10.71) 252 (9.92) B A 100 (3.94) 69 (2.72) 152 (5.98) Rev. May 17. 2013 Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) http://www.tracopower.com Industrial DC/DC-Converter TCL-DC Series, 24 to 60 Watt Features ◆ Ultra-wide input voltage range ◆ Output voltage adjustable ◆ Overload and short circuit protection ◆ Low ripple and noise ◆ I/O isolation 1500 VDC ◆ Compact, slim plastic case ◆ Reliable snap-on mount on DIN-rail ◆ Bracket for wall mount included ◆ 3-year product warranty In the TCL range of DIN-rail power supplies are 6 models for DC input voltage available. The wide input ranges of 9.5–18 VDC resp. 18–75 VDC means these models can be operated from all popular DC supply voltage systems. With tightly regulated output voltage these DC/DC converters provide a reliable power source for sensitive loads in industrial process controls, factory automation and other equipment exposed to a critical industrial environment. Further applications for these converters are isolation of a specific load or refreshing the 24 V bus voltage. Easy installation is provided with snap-on mounting on DIN-rails and detachable screw terminal block. Order Code Input Voltage Range Output Voltage Output Current max. TCL 012-124 DC 9.5 – 18.0 VDC 24 VDC 1.0 A TCL 024-105 DC 5 VDC 5.0 A TCL 024-112 DC 18 – 75 VDC 12 VDC 2.0 A TCL 024-124 DC 24 VDC 1.0 A TCL 060-112 DC TCL 060-124 DC 18 – 75 VDC 12 VDC 24 VDC 5.0 A 2.5 A Models Page 1 of 3 UL 508 CB Scheme http://www.tracopower.com Industrial DC/DC-Converter TCL-DC Series 24 to 60 Watt Input Specifications Input power at no load 1.0 Watt max. Start-up voltage/under voltage shut down TCL 012 model: 8.4 VDC / 7.6 VDC TCL 024 & TCL 060 models: 17.2 VDC / 15.7 VDC Reverse polarity protection by internal fuse Efficiency 86 % typ. Output Specifications Output voltage adj. range 5 VDC model: 5.0 – 5.25 VDC 12 VDC models: 12.0 – 15.0 VDC 24 VDC models: 24.0 – 28.0 VDC Regulation – Input variation Vin min. to Vin max. 0.5 % max – Load variation 0...100% 0.5 % max Ripple and noise (20 MHz bandwidth) <50 mV pk-pk Electronic short circuit protection current limitation at 110 % typ. (constant current, automatic recovery) Overvoltage protection, trigger point 5 VDC model: <6.5 V 12 VDC models: <24 V 24 VDC models: <42 V General Specifications Temperature ranges – Operating –25°C to +70°C max. – Storage (non operating) –25°C to +85°C Temperature derating 1.5 %/K above +50°C Humidity (non condensing) 95 % rel. H max. Temperature coefficient 0.02 %/K Switching frequency 55 – 180 kHz depending on load (frequency modulation) Isolation voltage (60 sec.) – Input/Output 1500 VDC Reliability, calculated MTBF at +25°C (according to IEC 61709) >2.5 Mio h Safety standards – Information technology equipment IEC 60950-1, EN 60950-1 (output SELV), UL Std. 60950-1 (2nd Edition) +Am1:2011, CAN/CSA-C22.2 No. 60950-1-07 +Am1:2011 – Industrial control equipment UL 508 – Electronic equipment for power installation EN 50178 – Electrical equipment for machines EN 60204 Safety approvals – CB test certificate (IEC 60950-1) www.tracopower.com/products/tcl-cb.pdf – UL approval www.ul.com -> certifications UL 508C listed, CSA C22.2 No.14 File e210002 – CSA certification UL 60950-1, CSA 60950-1-03 www.tracopower.com/products/tcl-csa.pdf – GS certification www.tracopower.com/products/tcl060dc_gs.pdf Electromagnetic compatibility (EMC), emissions EN 61000-6-3 – Conducted RI suppression on input EN 55022 class B – Radiated RI suppression EN 55022 class B Electromagnetic compatibility (EMC), immunity EN 61000-6-2 – Electrostatic discharge (ESD) EN 61000-4-2 4 kV / 8 kV – Radiated RF field immunity EN 61000-4-3 10 V/m – Electrical fast transient / burst immunity EN 61000-4-4 Level 3 – Surge immunity EN 61000-4-5 Level 3 – Immunity to conducted RF disturbances EN 61000-4-6 10 Vrms Environmental compliance – Reach www.tracopower.com/products/reach-declaration.pdf – RoHS RoHS directive 2011/65/EU Case protection IP 20 (IEC 60529) Enclosure material plastic UL 94V-0 rated Mounting DIN-rails as per EN 50022-35x15/7.5 (snap-on with self-locking spring) bracket for wall/chassis mount included Installation instructions www.tracopower.com/products/tcl-dc-inst.pdf All specifications valid at nominal input voltage, full load and +25 °C after warm-up time unless otherwise stated. Page 2 of 3 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Industrial DC/DC-Converter TCL-DC Series 24 to 60 Watt Rev. October 18. 2013 Page 3 of 3 27 (1.06) 2.2 (0.09) 100.0 (3.94) 75.0 (2.95) DC-ON LED Output voltage adjust INPUT 1 2 3 OUTPUT 1 2 Output Input 1 + Vout 1 Protective earth 2 – Vout 2 –Vin 3 +Vin Weight: 140g (4.9 oz) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Case Dimensions Wall Mounting Bracket Instead on a DIN-rail, the modules can be also mounted on a chassis or wall with help of a mounting bracket which is supplied as standard with each Converter 75.0 (2.95) 100.0 (3.94) 3.2 (0.13) 45 (1.77) DC-ON LED Output voltage adjust OUTPUT 1 1 2 2 INPUT 1 2 3 TCL 012 and TCL 024 models TCL 060 model Weight: 265 g (9.4 oz) Output Input 1 + Vout 1 Protective earth 2 – Vout 2 –Vin 3 +Vin http://www.tracopower.com DC/DC Converters TOS Series, Point-of-Load (POL) Converter Features  Small size, low profile  SMT package or SIP version  Cost-efficient open frame design  Wide input voltage ranges  Output voltages trim from 0.75 VDC to 5.5 VDC  Delivers up to 30 A with minimal derating  Ultra high efficiency to 96 %  Fast transient response  Remote On/Off control  Wide temperature range –40°C to +85°C  SMT package fully DOSA compatible  Lead free design – RoHS compliant The TOS series is a range of high performance non-isolated dc-dc converters With very high efficiency that can supply up to 30A of output current. These modules provide precisely regulated output voltages which can be set via an external resistor to a value from 0.75 VDC to 5.5 VDC. These converters work over a wide input voltage range of 2.4 to 5.5 VDC or 8.3 to 14.0 VDC.Further features include remote On/Off, under voltage lockout, over temperature and over current protection. These products have an open-frame construction with very small footprint and are available in an industry standard SIP or in a SMT package. The TOS series is fully RoHS compliant and can withstand industry standard handling, cleaning and the high temperatures of lead-free reflow solder processes. Order code SMT-version Input voltage range Output voltage range Output current max. Efficiency typ. TOS 06-05SM 6 A 94 % TOS 10-05SM 2.4 – 5.5 VDC 0.75 – 3.3 VDC** 10 A 93 % TOS 16-05SM 16 A 95 % TOS 06-12SM 6 A 89 % TOS 10-12SM 8.3 – 14.0 VDC 0.75 – 5.0 VDC 10 A 93 % TOS 16-12SM 16 A 92 % SIL-version TOS 06-05SIL 6 A 94 % TOS 10-05SIL 2.4 – 5.5 VDC 0.75 – 3.3 VDC* 10 A 93 % TOS 16-05SIL 16 A 95 % TOS 06-12SIL 6 A 89 % TOS 10-12SIL 8.3 – 14 VDC 0.75 – 5.0 VDC 10 A 93 % TOS 16-12SIL 16 A 92 % Models * 25 A output voltage higher than 2.75 VDC ** Max output voltage to be adjusted min. 0.5 VDC below impressed input voltage Page 1 of 4 Order code SMT-version Input voltage range Output voltage range Output current max. Efficiency typ. TOS 30-05SM 4.5 – 5.5 VDC 0.80 – 3.6 VDC 30 A 93 % TOS 30-12SM 6.0 – 14.0 VDC 0.80 – 3.6 VDC 30 A* 92 % SIL-version TOS 30-05SIL 4.5 – 5.5 VDC 0.80 – 5.5 VDC 30 A 93 % TOS 30-12SIL 6.0 – 14.0 VDC 0.80 – 5.5 VDC 30 A* 92 % Models Datasheet for 30A Models see: www.tracopower.com/products/tos30.pdf http://www.tracopower.com DC/DC Converters TOS Series, POL Converter Input Specifications Input current no load – Vin 5 VDC (at Vout min./Vout max.) 6 A models: 20 mA / 45 mA typ. 10 A models: 25 mA / 30 mA typ. 16 A models: 25 mA / 40 mA typ. – Vin 12 VDC (at Vout min./Vout max.) 6 A models: 17 mA / 100 mA typ. 10 A models: 40 mA / 100 mA typ. 16 A models: 40 mA / 100 mA typ. Stand by input current (at remote Off) 6 A models: 1 mA typ. 10 A / 16 A models: 2 mA typ. Max. input current – Vin 5 VDC 6 A models: 6 A 10 A models: 10 A 16 A models: 16 A – Vin 12 VDC 6 A models: 4.5 A 10 A models: 7 A 16 A models: 10 A Start up voltage / under voltage lockout 5 Vin models: 2.2 VDC / 2.0 VDC typ. 12 Vin models: 7.9 VDC / 7.8 VDC typ. Start up time (power / remote On till Vout set) 8 mS typ. Reflected ripple current – Vin 5 VDC 6 A models: 35 mA typ. (with input filter) 10 A / 16 A models: 100 mA typ. – Vin 12 VDC 6 A models: 30 mA typ. 10 A models: 20 mA typ. 16 A models: 20 mA typ. Input filter external (recommended) 2 x 150 μF low ESR polymer capacitors and 2 x 47 μF ceramic capacitors Output Specifications Voltage set accuracy ±2 % max. (see page 3 for set up) Voltage balance (dual output models) ±1 % max. Regulation – Input variation ±0.3 % max. – Load variation 0 – 100 % ±0.4 % max. Dynamic load response – 50 % load change (upper half) with external 1 μF ceramic- and 10 μF tantalum capacitors max. peak variation / response time Vin 5 VDC, 6 A models: 130 mV / 60 μS typ. Vin 12 VDC, 6 A models: 200 mV / 35 μS typ. Vin 5 VDC, 10 A models: 200 mV / 25 μS typ. Vin 12 VDC, 10 A models: 200 mV / 25 μS typ. Vin 5 VDC, 16 A models: 300 mV / 25 μS typ. Vin 12 VDC, 16 A models: 200 mV / 25 μS typ. – 50 % load change (upper half) with external 2 x 150 μF polymer capacitors Vin 5 VDC, 6 A models: 50 mV / 100 μS typ. Vin 12 VDC, 6 A models: 50 mV / 50 μS typ. Vin 5 VDC, 10 A models: 100 mV / 100 μS typ. Vin 12 VDC, 10 A models: 100 mV / 25 μS typ. Vin 5 VDC, 16 A models: 150 mV / 100 μS typ. Vin 12 VDC, 16 A models: 100 mV / 50 μS typ. Ripple and noise (20 MHz Bandwidth) 5 Vin models: 50 mV pk-pk max. 12 Vin models: 75 mV pk-pk max Temperature coefficient ±0.4 % typ. Over current protection at +200 % of Iout max. typ. Short circuit protection indefinite, automatic recovery Capacitive load – ESR <1 mOhm 1000 μF max. – ESR <10 mOhm 6 A models: 3000 μF max. 10 A / 16 A models: 5000 μF max. All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Page 2 of 4 http://www.tracopower.com DC/DC Converters TOS Series, POL Converter General Specifications Temperature ranges – Operating –40°C to +85°C – Storage –55°C to +125°C Derating see application note Over temperature protection at +125°C typ. Humidity (non condensing) 95 % rel H max. Reliability, calculated MTBF (Bellcore TR-NWT-000332) 6 A models: >20 mio. h at +40°C 10 A / 16 A models: >14 mio. h at +40°C Switching frequency 300 kHz typ. (pulse width modulation - PWM) Remote On/Off On: 1 VDC to Vin max. or open circuit. (reference to GND) Off: 0 to 0.3 VDC Physical Specifications Weight 6 A models: 2.8 g 10 A / 16 A models: 6.0 g Soldering profile – SIL - Version max. 265°C / 10 sec. (wave soldering) – SMT - Version peak temp. 245°C for 10 sec. max., 217°C for 90 sec. max. (Convection reflow solder process is recommended) Output Voltage Adjustment Rd GND Prog Load (+Vout) Vo 5 VDC input models: Rd [Ohm] = 21070 – 5110 Vo – 0.7525 12 VDC input models: Rd [Ohm] = 10570 – 1000 Vo – 0.7525 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Page 3 of 4 Application note: www.tracopower.com/products/tos-application.pdf Jenatschstrasse 1 · CH-8002 Zurich · Switzerland Tel. +41 43 311 45 11 · Fax +41 43 311 45 45 · info@traco.ch · www.tracopower.com DC/DC Converters TOS Series, POL Converter Outline Dimensions mm (inches) Rev. 12/12 Surface Mount (SMT-Version) Single-in-Line (SIL-Version) 10.2 (0.40) 22.9 (0.90) 3.29 (0.13) 20.32 (0.8) Vin GND Prog Vout On/Off 6 A output Models Vin GND Prog Vout On/Off 0.70 (0.028) 6.65 (0.26) 10A & 16A output models Sens No Pin 0.64 (0.025) 0.51 (0.02) 1.28 (0.05) 3.24 (0.128) 1.18 (0.046) 8.28 (0.33) 0.51 (0.02) 0.64 (0.025) 1.28 (0.05) 5 x 2.54 (5 x 0.10) 4 x 2.54 (4 x 0.10) 50.8 (2.00) 12.7 (0.50) 25.4 (1.0) Vin Vout Vout GND 2.54 (0.1) 15.24 (0.6) 17.78 (0.7) 1.5 11.4 (0.45) 2.29 20.3 (0.8) (0.09) (0.05) 1.3 1.57 8.9 (0.35) (0.82) 4.06 (0.16) 4.06 (0.16) 4.57 (0.18) 17.52 (0.69) (0.06) 8.64 (0.34) Vin GND Prog Vout On/Off 1.57 (0.82) 5.97 (0.24) Bottom View 6 A output Models 1.9 13.5 (0.53) 2.84 33.0 (1.3) (0.112) (0.05) 1.3 1.57 10.92 (0.43) (0.82) 4.83 (0.19) 4.83 (0.19) 7.54 (0.30) 29.9 (1.18) (0.075) 10.29 (0.41) Vin GND Vout Prog On/Off 1.57 (0.82) 8.28 (0.33) Bottom View 10A & 16A output models 4.83 (0.19) 4.83 (0.19) No Pin Sens Page 4 of 4 Specifications can be changed any time without notice. http://www.tracopower.com Page 1 of 6 AC/DC Power Modules TML Series, 5to 30 Watt The TML series are ultra compact AC/DC power supplies in a fully encapsulated plastic case. They feature versions with screw terminals for easy installation or with solder pins for direct PCB mounting. International safety approvals qualify this product for worldwide markets. The TML series AC/DC modules offer an interesting solution for many space critical applications in commercial and industrial electronic equipment. Features ◆ Encapsulated power Supplies ◆ PCB mount or chassis mount with screw terminals ◆ Single, dual and triple output models ◆ Universal input 85–264 VAC, 47–440 Hz ◆ EMI meets EN 55022, class B and FCC, level B ◆ Low ripple and noise ◆ Short circuit and overload protection ◆ 3-year product warranty Order Code Output Power max. Output 1 Output 2 Output 3 TML 05105 5 VDC/1000 mA TML 05112 12 VDC/416 mA TML 05115 15 VDC/333 mA TML 05124 5 Watt 24 VDC/200 mA TML 05205 5 VDC/500 mA –5 VDC/500 mA TML 05212 12 VDC/200 mA –12 VDC/200 mA TML 05215 15 VDC/160 mA –15 VDC/160 mA TML 10105 5 VDC/2000 mA TML 10112 12 VDC/833 mA TML 10115 15 VDC/666 mA TML 10124 10 Watt 24 VDC/416 mA TML 10205 5 VDC/800 mA –5 VDC/800 mA TML 10212 12 VDC/380 mA –12 VDC/380 mA TML 10215 15 VDC/300 mA –15 VDC/300 mA Models LVD UL 60950-1 http://www.tracopower.com Page 2 of 6 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. AC/DC Power Modules TML Series 5 to 30 Watt Input Specifications Input voltage ranges – AC input 85–264 VAC – DC Input TML 30 models: 100 – 370 VDC output power derating 1 %/V below 110 VDC other models: 85 – 370 VDC output power derating 0.8 %/V below 110 VDC Input frequency 47–440 Hz Input current no load 115 VAC / 230 VAC TML 5 models: 10 mA / 15 mA typ TML 10 models: 15 mA / 20 mA typ TML 15 models: 18 mA / 25 mA typ. TML 30 models: 30 mA / 55 mA typ. Input current full load 115 VAC / 230 VAC TML 5 models: 160 mA / 80 mA typ. TML 10 models: 200 mA / 120 mA typ TML 15 models: 280 mA / 165 mA typ. TML 30 models: 550 mA / 320 mA typ. External fuse (required) 1.5 A slow blow type (recommendation) Order Code Output Power Output 1 Output 2 Output 3 PCB-mounting Chassis mounting max. TML 15105 TML 15105C 5 VDC/3000 mA TML 15112 TML 15112C 12 VDC/1250 mA TML 15115 TML 15115C 15 VDC/1000 mA TML 15124 TML 15124C 24 VDC/625 mA TML 15205 TML 15205C 15 Watt 5 VDC/1500 mA –5 VDC/1500 mA TML 15212 TML 15212C 12 VDC/650 mA –12 VDC/650 mA TML 15215 TML 15215C 15 VDC/500 mA –15 VDC/500 mA TML 15512 TML 15512C 5 VDC/2000 mA 12 VDC/200 mA –12 VDC/200 mA TML 15515 TML 15515C 5 VDC/2000 mA 15 VDC/150 mA –15 VDC/150 mA TML 30103 TML 30103C 3.3 VDC/6000 mA TML 30105 TML 30105C 5 VDC/6000 mA TML 30112 TML 30112C 12 VDC/2500 mA TML 30115 TML 30115C 15 VDC/2000 mA TML 30124 TML 30124C 24 VDC/1250 mA TML 30205 TML 30205C 30 Watt 5 VDC/3000 mA –5 VDC/3000 mA TML 30212 TML 30212C 12 VDC/1300 mA –12 VDC/1300 mA TML 30215 TML 30215C 15 VDC/1000 mA –15 VDC/1000 mA TML 30252 TML 30252C *5 VDC/3000 mA *12 VDC/1250 mA TML 30512 TML 30512C * 5 VDC/3000 mA 12 VDC/630 mA –12 VDC/630 mA TML 30515 TML 30515C *5 VDC/3000 mA 15 VDC/500 mA –15 VDC/500 mA Models * Output floating http://www.tracopower.com Page 3 of 6 AC/DC Power Modules TML Series 5 to 30 Watt Output Specifications Voltage set accuracy ± 2 % Regulation – Input variation 0.3 % max. – Load variation (10–100%) single output models: 1.0 % max. dual / triple output models: 5 % max. Minimum load single output models: 5 % dual output models: 3 % (each output) triple output 15W models: 10 % (main output only) triple output 30W models: 20 % (each output) Ripple and noise (20 MHz bandwidth) – 3.3 & 5 VDC output models: <1.5 % of Vout – other models: <1.0 % of Vout Current limitation 120– 80 % fold back Short circuit protection hiccup mode, indefinite (automatic recovery) Maximum capacitive load 470–50’000 μF depending on model General Specifications Temperature ranges – Operating –25 °C to +60 °C – Power derating above 50 °C 3.75 %/°C – Storage (non operating) –40 °C to +85 °C Temperature coefficient 0.02 %/°C Efficiency 72–80 % (depending on model) Humidity (non condensing) 95 % rel max. Switching frequency 100 kHz typ. (pulse width modulation PWM) Hold-up time 40 ms min. (Vin 115...230 VAC) Isolation voltage – Input/Output 3‘000 VAC Reliability /calculated MTBF (MIL-HDBK-217F at +25°C, ground benign) >660’000 h EMI / RFI conducted EN 55022, class B, FCC part 15, level B EMC compliance – Electrostatic discharge ESD IEC / EN 61000-4-2 4 kV / 8 kV – RF field susceptibility IEC / EN 61000-4-3 3 V/m – Electrical fast transients/bursts on mainsline IEC / EN 61000-4-4 1 kV Safety class II (only 30 watt models) to IEC / EN 60536 Safety standards UL 60950-1, IEC/EN 60950-1 Safety approval cUL/UL File e188913 www.ul.com -> certifications Case material plastic resin + fiberglass (flammability to UL 94-V0) Environmental compliance – Reach www.tracopower.com/products/tml-reach.pdf – RoHS RoHS directive 2011/65/EU All specifications valid at nominal input voltage, full load and +25 °C after warm-up time unless otherwise stated. http://www.tracopower.com Page 4 of 6 AC/DC Power Modules TML Series 5 to 30 Watt Outline Dimensions TML 5 Models Pin diameter ø 1.0 mm TML 10 Models Weight: 80 g (2.8 oz) Weight: 95 g (3.4 oz) ( ) = Inches Tolerances = 0.5mm (0.02) 1 2 3 4 5 6 45.0 (1.77) 17.5 ±0.3 (0.69 ±0.012) 17.5 ±0.3 (0.69 ±0.012) 4.0 (0.16) 47.0 ±0.3 (1.85 ±0.012) 55.0 (2.17) 10 ±0.3 (0.39 ±0.012) 10 ±0.3 (0.39 ±0.012) 20.5 (0.81) 10 (0.39) Bottom view Bottom view 1 2 3 4 5 45.0 (1.77) 20.5 (0.79) 10 (0.39) 17.5 ±0.3 (0.69 ±0.012) 4.0 (0.16) 6 17.5 ±0.3 (0.69 ±0.012) 54.0 ±0.3 (2.13 ±0.012) 64.0 (2.52) 10 ±0.3 (0.39 ±0.012) 10 ±0.3 (0.39 ±0.012) Pin diameter ø 1.0 mm Pin Single Dual 1 FG FG 2 AC(N) AC(N) 3 AC(L) AC(L) 4 –V out –V out 5 NC Common 6 +V out +V out Pin-Out Pin Single Dual 1 FG FG 2 AC(N) AC(N) 3 AC(L) AC(L) 4 –V out –V out 5 NC Common 6 +V out +V out Pin-Out NC = Not to connect NC = Not to connect http://www.tracopower.com Page 5 of 6 AC/DC Power Modules TML Series 5 to 30 Watt Outline Dimensions TML 15 Models PCB mounting: TML 15-C Models Chassis mounting: Bottom view 1 2 3 8 7 6 5 4 54.0 (2.13) 20.0 ±0.3 (0.79 ±0.012) 20.0 ±0.3 (0.79 ±0.012) 6.0 (0.24) 62.0 ±0.3 (2.44 ±0.012) 74.0 (2.91) 8.5 ±0.3 (0.33 ±0.012) 8.5 ±0.3 (0.33 ±0.012) 11.5 ±0.3 (0.45 ±0.012) 11.5 ±0.3 (0.45 ±0.012) 22.0 (0.87) 10 (0.39) Top view 54.0 (2.13) 5.0 (0.20) 86.0 ±0.3 (3.39 ±0.012) 96.0 (3.78) 4 x ø3.5 (4 x ø0.14) 1 2 3 8 7 6 5 4 27.6 (1.08) 5.0 (0.20) 46.0 ±0.3 (1.81 ±0.012) Pin diameter ø 1.0 mm Weight: 120 g (4.2 oz) Weight: 150 g (5.3 oz) Pin Single Dual Triple 1 FG FG FG 2 AC(N) AC(N) AC(N) 3 AC(L) AC(L) AC(L) 4 No Pin No Pin –V out 3 5 –V out –V out Com. 2/3 6 No Pin Common +V out 2 7 +V out +V out –V out 1 8 No Pin No Pin +V out 1 Pin-Out Page 6 of 6 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com AC/DC Power Modules TML Series 5 to 30 Watt TML 30 Models PCB mounting: 1 2 7 6 5 4 3 Bottom view 63.5 (2.50) 27.9 ±0.3 (1.10 ±0.012) 3.8 (0.15) 81.3 ±0.3 (3.20 ±0.012) 88.9 (3.50) 15.24 ±0.3 (0.60 ±0.012) 12.7 ±0.3 (0.50 ±0.012) 12.7 ±0.3 (0.50 ±0.012) 15.24 ±0.3 (0.60 ±0.012) 25.0 (0.98) 6 (0.24) 27.9 ±0.3 (1.10 ±0.012) Top view 1 2 7 6 5 4 3 31.0 (1.22) 5.5 (0.22) 64.7 (2.55) 50.0 ±0.3 (1.97 ±0.012) 6.0 (0.20) 100.0 ±0.3 (3.94 ±0.012) 112.0 (4.41) 4 x ø3.5 (4 x ø0.14) NC TML 30-C Models Chassis mounting: Pin diameter ø 1.0 mm Weight : 230 g (8.1 oz) Weight : 275 g (9.7 oz) Dimensions in[mm], () = Inches Tolerances = 0.5mm (0.02) Pin Single Dual sym. Dual asym. Triple 1 AC(N) AC(N) AC(N) AC(N) 2 AC(L) AC(L) AC(L) AC(L) 3 +V out +V out +V out 2 +V out 2 4 No Pin No Pin +V out 1 +V out 1 5 –V out Common –V out 2 Com. 2/3 6 No Pin No Pin –V out 1 –V out 1 7 NC. –V out NC. –V out 3 Pin-Out Rev. February 14. 2014 Outline Dimensions NC = Not to connecthttp://www.tracopower.com Features ◆ Shielded metal case with screw terminals ◆ Compact dimensions: 98 x 52 x 34 mm ◆ Ultra-wide 4:1 input voltage range ◆ Very high efficiency up to 87% ◆ Constant current output characteristic for battery load applications ◆ Optional with input filter to meet EN55022 class B ◆ Overtemperature protection ◆ Wide Operating temperature range: –40°C to +75°C ◆ Reverse input protection ◆ Under voltage lock-out ◆ I/O isolation 2250 VDC ◆ Easy chassis and wall mounting ◆ 3-year product warranty DC/DC Converters TEP 150WI Series, 150 Watt The TEP-150WI Series is a family of high power density dc-dc converter modules with ultra-wide 4:1 input voltage range which come in an ultra-compact metal case with screw terminal connection. Suitable for a wide range of applications, the TEP-150WI series was particularly designed with industrial applications in mind. The modules have flanges for easy chassis or wall mounting. A very high efficiency allows an operating temperature up to +50°C with natural convection cooling. Further features include adjustable output voltage with constant current characteristic for battery charger applications. Page 1 of 5 Order code* Input voltage Output voltage Output current max. Efficiency typ. TEP 150-2412WI 12 VDC 12.5 A 86 % TEP 150-2413WI 9 – 36 VDC 15 VDC 10 A 86 % TEP 150-2415WI (24 VDC nominal) 24 VDC 6.3 A 87 % TEP 150-2416WI 28 VDC 5.4 A 87 % TEP 150-2418WI 48 VDC 3.2 A 86 % TEP 150-4812WI 12 VDC 12.5 A 87 % TEP 150-4813WI 18 – 75 VDC 15 VDC 10 A 87 % TEP 150-4815WI (48 VDC nominal) 24 VDC 6.3 A 88 % TEP 150-4816WI 28 VDC 5.4 A 88 % TEP 150-4818WI 48 VDC 3.2 A 87 % TEP 150-7212WI 12 VDC 12.5 A 86 % TEP 150-7213WI 43 – 160 VDC 15 VDC 10 A 86 % TEP 150-7215WI (72 VDC nominal) 24 VDC 6.3 A 87 % TEP 150-7216WI 28 VDC 5.4 A 87 % TEP 150-7218WI 48 VDC 3.2 A 86 % Options suffix –F Modules with input filter to meet EN 55022 class B, see page 5 on demand Negative (passive = Off) remote On/Off function (standard is passive = On)range Models CB Scheme UL 60950-1 http://www.tracopower.com Input Specifications Input current (no load) 24 Vin, 12 – 24 VDC models: 80 mA typ. 24 Vin, 28 – 48 VDC models: 130 mA typ. 48 Vin, 12 – 24 VDC models: 60 mA typ. 48 Vin, 28 – 48 VDC models: 70 mA typ. 110 Vin, 12 – 24 VDC models: 30 mA typ. 110 Vin, 28 – 48 VDC models: 40 mA typ. Start-up voltage / under voltage lock-out 24 Vin models: 9 VDC / 8.2 VDC typ. 48 Vin models: 18 VDC / 16.2 VDC typ. 110 Vin models: 43 VDC / 34.5 VDC typ. Surge voltage (1sec. max.) 24 Vin models: 50 V 48 Vin models: 100 V 110 Vin models: 170 V Conducted noise (input) EN 55022 class A, FCC part 15, class A without external components. optional filter for class B – suffix F ESD (electrostatic discharge) EN 61000-4-2, air ±8 kV, contact ±6 kV, perf. criteria A Radiated immunity EN 61000-4-3, 10 V/m, perf. criteria A Fast transient / Surge (with input capacitor for models without filter module) EN 61000-4-4, ±2 kV, perf. criteria A EN 61000-4-5, ±1 kV perf. criteria A – Input capacitor: 24 VDC models: Nippon chemi-con KY 470 μF, 50 V, ESR 45 mOhm 48 VDC models: Nippon chemi-con KY 220 μF, 100 V, ESR 48 mOhm 110 VDC models: Nippon chemi-con KXJ series, 150 μF, 200V models with filter module (suffix F): no input capacitor required Conducted immunity EN 61000-4-6, 10 Vrms, perf. criteria A Reverse voltage protection parallel diode (input fuse required) Recommended input fuse (slow blow) 24 Vin models: 15 A 48 Vin models: 10 A 72 Vin models: 5 A Output Specifications Voltage set accuracy ±1 % Output voltage adjustment +20 % by external resistor (see application note) Regulation – Input variation Vin min. to Vin max. 0.2 % max. – Load variation 0 – 100 % 0.4 % max. Temperature coefficient ±0.02 %/K Minimum load not required Ripple and noise (20 MHz Bandwidth) 12 & 15 VDC models: 100 mVpk-pk max. 24 & 28 VDC models: 200 mVpk-pk max. 48 VDC models: 350 mVpk-pk max. Start up time (nominal Vin and constant resistive load) 25 ms typ. (at power On or remote On) Transient response (25 % load step change) 200 μs typ. Output current – Constant voltage (CV) up to 110 % of Iout max. – Constant current (CC) above 110 % of Iout max. Over voltage protection at 125 –140 % of Vout nom. Short circuit protection indefinite, automatic recovery Capacitive load 12 VDC models: 40‘000 μF max. 15 VDC models: 26‘000 μF max. 24 VDC models: 10‘000 μF max. 28 VDC models: 7‘600 μF max. 48 VDC models: 2‘600 μF max. DC/DC Converters TEP 150WI Series 150 Watt Page 2 of 5 http://www.tracopower.com DC/DC Converters TEP 150WI Series 150 Watt General Specifications Temperature ranges – Operating –40°C to +75°C – Case temperature +100°C max. – Storage –55°C to +125°C Thermal consideration – Mounting surface Optimize thermal coupling to heat conducting surface. Not to mount on flammable surface! – Derating and temperature test point see application note Over temperature protection at 110°C (auto restart) Vibration and thermal shock acc. MIL-STD-810F Humidity (non condensing) 95 % rel H max. Reliability, calculated MTBF (MIL-HDBK-217F, at +40°C, ground benign) >135‘000 h Isolation voltage (60 sec.) – Input/Output 2250 VDC (functional insulation) – Input/Case 1500 VDC – Output/Case 1500 VDC Isolation capacitance – Input/Output 3500 pF max. Isolation resistance – Input/Output (500 VDC) >1 GOhm min. Switching frequency 220 – 330 kHz depending on model (puls width modulation) Safety standards UL 60950-1, IEC/EN 60950-1 Safety approvals – UL/cUL 60950-1 www.ul.com -> certifications -> File e188913 – CB test certificate (IEC 60950-1) www.tracopower.com/products/tep150wi-cb.pdf (72 Vin models pending) Remote On/Off – positive logic (standard) – On: 3 to 12 VDC or open circuit – Off: 0 to 1.2 VDC or short circuit pin 5 and 3 – negative logic (option -N) – On: 0 to 1.2 VDC or short circuit pin 5 and 3 – Off: 3 to 12 VDC or open circuit – Off idle current: 3 mA Environmental compliance – Reach www.tracopower.com/products/tep150wi-reach.pdf – RoHS RoHS directive 2011/65/EU Physical Specifications Casing material metal Potting material silicon (UL 94V-0 rated) Case protection IP 50 (in accordance to IEC/EN60529) Weight 300 g (10.6 oz) All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Page 3 of 5 Application note: www.tracopower.com/products/tep150wi-application.pdf (72 Vin models pending) http://www.tracopower.com DC/DC Converters TEP 150WI Series 150 Watt Page 4 of 5 Weight: 300g (10.6 oz) Dimensions in [mm], () = Inch Mounting slot tolerance: ±0.25 (±0.001) Case tolerances: ±0.5 (±0.02) Outline Dimensions 52.5 65.0 1.2 35.7 (2.07) (2.56) (1.6) (0.05) 59.0 (2.07) 98.0 (3.86) 56.0 (2.20) 21.0 (0.83) 4 x r2 (0.08) 1 2 3 4 5 6 7 8 9 Pin Connection pin function recommended wire 1 + Vin 14 – 16 AWG 2 + Vin 14 – 16 AWG 3 – Vin 14 – 16 AWG 4 – Vin 14 – 16 AWG 5 Remote On/Off 14 – 24 AWG 6 + Vout 14 – 16 AWG 7 – Vout 14 – 16 AWG 8 Trim 14 – 24 AWG 9 Trim 14 – 24 AWG Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Rev. June 14. 2013 Page 5 of 5 DC/DC Converters TEP 150WI Series 150 Watt Outline Dimensions Pin Connection 52.5 65.0 1.2 35.7 (2.07) (2.56) (1.6) (0.05) 59.0 (2.07) 139.5 (5.49) 56.0 (2.20) 21.0 (0.83) 6 x r2 (0.08) 160.5 (6.32) 1 2 3 4 5 6 7 8 9 90.0 (3.54) 18.7 (0.74) Weight: 435g (15.3 oz) Dimensions in [mm], () = Inch Mounting slot tolerance: ±0.25 (±0.001) Case tolerances: ±0.5 (±0.02) pin function recommended wire 1 + Vin 14 – 16 AWG 2 + Vin 14 – 16 AWG 3 – Vin 14 – 16 AWG 4