Farnell PDF PN512 Full NFC Forum compliant solution - NXP - Farnell Element 14

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Branding Farnell element14 (France)

 

Farnell Element 14 :

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1. Introduction This document describes the functionality and electrical specifications of the transceiver IC PN512. The PN512 is a highly integrated transceiver IC for contactless communication at 13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 MHz. 1.1 Different available versions The PN512 is available in three versions: • PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2 (TFBGA64), hereafter named as version 2.0 • PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In), hereafter named as industrial version, fulfilling the automotive qualification stated in AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical stress test qualification for automotive integrated circuits (ICs). • PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named as version 1.0 The data sheet describes the functionality for the industrial version and version 2.0. The differences of the version 1.0 to the version 2.0 are summarized in Section 21. The industrial version has only differences within the outlined characteristics and limitations. 2. General description The PN512 transceiver ICs support 4 different operating modes • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Reader/Writer mode supporting ISO/IEC 14443B • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal transmitter part is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The receiver part provides a robust and efficient implementation of a demodulation and PN512 Full NFC Forum compliant solution Rev. 4.5 — 17 December 2013 111345 Product data sheet COMPANY PUBLIC PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 2 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and transponders. The digital part handles the complete ISO/IEC 14443A framing and error detection (Parity & CRC). The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both directions. Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa communication scheme. The receiver part provides a robust and efficient implementation of the demodulation and decoding circuitry for FeliCa coded signals. The digital part handles the FeliCa framing and error detection like CRC. The PN512 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication scheme, given correct implementation of additional components, like oscillator, power supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4 and/or ISO/IEC 14443B anticollision are correctly implemented. In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card functionality is only possible in combination with a secure IC using the S2C interface. Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection. Various host controller interfaces are implemented: • 8-bit parallel interface1 • SPI interface • serial UART (similar to RS232 with voltage levels according pad voltage supply) • I2C interface. A purchaser of this NXP IC has to take care for appropriate third party patent licenses. 1. 8-bit parallel Interface only available in HVQFN40 package. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 3 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 3. Features and benefits  Highly integrated analog circuitry to demodulate and decode responses  Buffered output drivers for connecting an antenna with the minimum number of external components  Integrated RF Level detector  Integrated data mode detector  Supports ISO/IEC 14443 A/MIFARE  Supports ISO/IEC 14443 B Read/Write modes  Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning  Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna size and tuning and power supply  Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation mode of about 100 mm depending on the antenna size and tuning and the external field strength  Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode  ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s  Contactless communication according to the FeliCa scheme at 212 kbit/s and 424 kbit/s  Integrated RF interface for NFCIP-1 up to 424 kbit/s  S2C interface  Additional power supply to directly supply the smart card IC connected via S2C  Supported host interfaces  SPI up to 10 Mbit/s  I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode  RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply  8-bit parallel interface with and without Address Latch Enable  FIFO buffer handles 64 byte send and receive  Flexible interrupt modes  Hard reset with low power function  Power-down mode per software  Programmable timer  Internal oscillator for connection to 27.12 MHz quartz crystal  2.5 V to 3.6 V power supply  CRC coprocessor  Programmable I/O pins  Internal self-test PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 4 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 4. Quick reference data [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. [4] Ipd is the total current for all supplies. [5] IDD(PVDD) depends on the overall load at the digital pins. [6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz. Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V VDDD digital supply voltage VDD(TVDD) TVDD supply voltage VDD(PVDD) PVDD supply voltage [3] 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [4]- - 5 A soft power-down; RF level detector on [4]- - 10 A IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register’s RcvOff bit = 1 - 3 5 mA IDD(PVDD) PVDD supply current pin PVDD [5]- - 40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8]- 60 100 mA Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 +85 C lndustrial version: Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [4]- - 15 A soft power-down; RF level detector on [4]- - 30 A Tamb ambient temperature HVQFN32 40 - +90 C PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 5 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 5. Ordering information Table 2. Ordering information Type number Package Name Description Version PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-1 PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5  5  0.85 mm SOT617-1 PN5120A0HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-1 PN5120A0ET/C2 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT1336-1 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 6 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6. Block diagram The analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN512. The communication (S2C) interface provides digital signals to support communication for transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC. The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa. Various host interfaces are implemented to meet different customer requirements. Fig 1. Simplified block diagram of the PN512 001aaj627 HOST ANTENNA FIFO BUFFER ANALOG INTERFACE CONTACTLESS UART SERIAL UART SPI I2C-BUS REGISTER BANK PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 7 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 2. Detailed block diagram of the PN512 001aak602 DVDD NRSTPD IRQ MFIN MFOUT SVDD OSCIN OSCOUT VMID AUX1 AUX2 RX TVSS TX1 TX2 TVDD 16 19 20 17 10, 14 11 13 12 DVSS AVDD SDA/NSS/RX EA I2C PVDD PVSS 24 32 1 2 5 D1/ADR_5 25 D2/ADR_4 26 D3/ADR_3 27 D4/ADR_2 28 D5/ADR_1/ SCK/DTRQ 29 D6/ADR_0/ MOSI/MX 30 D7/SCL/ MISO/TX 31 AVSS 3 6 23 7 8 9 21 22 4 15 18 FIFO CONTROL MIFARE CLASSIC UNIT STATE MACHINE COMMAND REGISTER PROGRAMABLE TIMER INTERRUPT CONTROL CRC16 GENERATION AND CHECK PARALLEL/SERIAL CONVERTER SERIAL DATA SWITCH TRANSMITTER CONTROL BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK BIT DECODING BIT ENCODING RANDOM NUMBER GENERATOR ANALOG TO DIGITAL CONVERTER I-CHANNEL AMPLIFIER ANALOG TEST MULTIPLEXOR AND DIGITAL TO ANALOG CONVERTER I-CHANNEL DEMODULATOR Q-CHANNEL AMPLIFIER CLOCK GENERATION, FILTERING AND DISTRIBUTION Q-CLOCK GENERATION OSCILLATOR TEMPERATURE SENSOR Q-CHANNEL DEMODULATOR AMPLITUDE RATING REFERENCE VOLTAGE 64-BYTE FIFO BUFFER CONTROL REGISTER BANK SPI, UART, I2C-BUS INTERFACE CONTROL VOLTAGE MONITOR AND POWER ON DETECT RESET CONTROL POWER-DOWN CONTROL PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 8 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1) Fig 4. Pinning configuration HVQFN40 (SOT618-1) 001aan212 PN512 Transparent top view RX SIGIN SIGOUT AVSS NRSTPD AUX1 PVSS AUX2 DVSS OSCIN DVDD OSCOUT PVDD IRQ A1 ALE SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID A0 D7 D6 D5 D4 D3 D2 D1 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 001aan213 PN512 AVSS NRSTPD SIGIN AUX1 PVSS AUX2 DVSS OSCIN DVDD OSCOUT PVDD IRQ A5 NWR A4 NRD A3 ALE A2 NCS SIGOUT SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID RX A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 terminal 1 index area Transparent top view PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 9 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 5. Pin configuration TFBGA64 (SOT1336-1) aaa-005873 TFBGA64 Transparent top view ball A1 index area H G F E D C B A 1 2 3 4 5 6 7 8 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 10 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 7.2 Pin description Table 3. Pin description HVQFN32 Pin Symbol Type Description 1 A1 I Address Line 2 PVDD PWR Pad power supply 3 DVDD PWR Digital Power Supply 4 DVSS PWR Digital Ground 5 PVSS PWR Pad power supply ground 6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. 7 SIGIN I Communication Interface Input: accepts a digital, serial data stream 8 SIGOUT O Communication Interface Output: delivers a serial data stream 9 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads 10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 15 AVDD PWR Analog Power Supply 16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 17 RX I Receiver Input 18 AVSS PWR Analog Ground 19 AUX1 O Auxiliary Outputs: These pins are used for testing. 20 AUX2 O 21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). 22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 23 IRQ O Interrupt Request: output to signal an interrupt event 24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus. Remark: An 8-bit parallel interface is not available. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. Remark: For serial interfaces this pins can be used for test signals or I/Os. 32 A0 I Address Line PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 11 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 4. Pin description HVQFN40 Pin Symbol Type Description 1 to 4 A2 to A5 I Address Line 5 PVDD PWR Pad power supply 6 DVDD PWR Digital Power Supply 7 DVSS PWR Digital Ground 8 PVSS PWR Pad power supply ground 9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. 10 SIGIN I Communication Interface Input: accepts a digital, serial data stream 11 SIGOUT O Communication Interface Output: delivers a serial data stream 12 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads 13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier 15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier 17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 18 AVDD PWR Analog Power Supply 19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. 20 RX I Receiver Input 21 AVSS PWR Analog Ground 22 AUX1 O Auxiliary Outputs: These pins are used for testing. 23 AUX2 O 24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz). 25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. 26 IRQ O Interrupt Request: output to signal an interrupt event 27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register 28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7) 29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. 30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512 31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. 39 to 40 A0 to A1 I Address Line PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 12 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 5. Pin description TFBGA64 Pin Symbol Type Description A1 to A5, A8, B3, B4, B8, E1 PVSS PWR Pad power supply ground A6 D4 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. A7 D2 I/O B1 PVDD PWR Pad power supply B2 A0 I Address Line B5 D5 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. B6 D3 I/O B7 D1 I/O C1 DVDD PWR Digital Power Supply C2 A1 I Address Line C3 D7 I/O 8-bit Bi-directional Data Bus. Remark: For serial interfaces this pins can be used for test signals or I/Os. Remark: If the host controller selects I2C as digital host controller interface, these pins can be used to define the I2C address. C4 D6 I/O C5 IRQ O Interrupt Request: output to signal an interrupt event C6 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH. C7, C8, D6, D8, E6, E8, F7, G8, H8 AVSS PWR Analog Ground D1 DVSS PWR Digital Ground D2 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world. With a positive edge on this pin the internal reset phase starts. D3 to D5, E3 to E5, F3, F4, G1 to G6, H1, H2, H6 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2 D7 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. E2 SIGIN I Communication Interface Input: accepts a digital, serial data stream E7 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12MHz). F1 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads F2 SIGOUT O Communication Interface Output: delivers a serial data stream F5 AUX1 O Auxiliary Outputs: These pins are used for testing. F6 AUX2 O F8 RX I Receiver Input G7 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage. H3 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 13 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2 H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier H7 AVDD PWR Analog Power Supply Table 5. Pin description TFBGA64 Pin Symbol Type Description PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 14 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8. Functional description The PN512 transmission module supports the Read/Write mode for ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and modulation protocols. PN512 transceiver IC supports the following operating modes: • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail. Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance. 8.1 ISO/IEC 14443 A/MIFARE functionality The physical level communication is shown in Figure 7. The physical parameters are described in Table 4. Fig 6. PN512 Read/Write mode 001aan218 BATTERY reader/writer contactless card MICROCONTROLLER PN512 ISO/IEC 14443 A CARD Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer Communication direction Signal type Transfer speed 106 kBd 212 kBd 424 kBd Reader to card (send data from the PN512 to a card) reader side modulation 100 % ASK 100 % ASK 100 % ASK bit encoding modified Miller encoding modified Miller encoding modified Miller encoding bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s) (1) (2) 001aan219 PN512 ISO/IEC 14443 A CARD ISO/IEC 14443 A READER PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 15 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The PN512’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol. Figure 8 shows the data coding and framing according to ISO/IEC 14443 A/MIFARE. The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the ManualRCVReg register’s ParityDisable bit. 8.2 ISO/IEC 14443 B functionality The PN512 reader IC fully supports international standard ISO 14443 which includes communication schemes ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. Card to reader (PN512 receives data from a card) card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit encoding Manchester encoding BPSK BPSK Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued Communication direction Signal type Transfer speed 106 kBd 212 kBd 424 kBd Fig 8. Data coding and framing according to ISO/IEC 14443 A 001aak585 ISO/IEC 14443 A framing at 106 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start odd start bit is 1 parity ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd 8-bit data 8-bit data 8-bit data odd parity odd parity start even parity start bit is 0 burst of 32 subcarrier clocks even parity at the end of the frame PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 16 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.3 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. The contactless UART of PN512 and a dedicated external host controller are required to handle the complete FeliCa protocol. 8.3.1 FeliCa framing and coding To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h) and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver. The following Len byte indicates the length of the sent data bytes plus the LEN byte itself. The CRC calculation is done according to the FeliCa definitions with the MSB first. To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the PN512 automatically and must not be written to the FIFO by the host controller. The PN512 performs internally the CRC calculation and adds the result to the data frame. Example for FeliCa CRC Calculation: Fig 9. FeliCa reader/writer communication diagram Table 7. Communication overview for FeliCa reader/writer Communication direction FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s PN512  card Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s card  PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK bit coding Manchester coding Manchester coding 2. PICC to PCD, > 12 % ASK loadmodulation Manchester coded, baudrate 212 to 424 kbaud 1. PCD to PICC, 8-30 % ASK Manchester coded, baudrate 212 to 424 kbaud 001aan214 PN512 FeliCa CARD (PICC) Felica READER (PCD) Table 8. FeliCa framing and coding Preamble Sync Len n-Data CRC 00h 00h 00h 00h 00h 00h B2h 4Dh Table 9. Start value for the CRC Polynomial: (00h), (00h) Preamble Sync Len 2 Data Bytes CRC 00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35h PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 17 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4 NFCIP-1 mode The NFCIP-1 communication differentiates between an active and a Passive Communication mode. • Active Communication mode means both the initiator and the target are using their own RF field to transmit data. • Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active in terms of generating the RF field. • Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication • Target: responds to initiator command either in a load modulation scheme in Passive Communication mode or using a self generated and self modulated RF field for Active Communication mode. In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. Fig 10. NFCIP-1 mode 001aan215 BATTERY initiator: active target: passive or active MICROCONTROLLER PN512 BATTERY MICROCONTROLLER PN512 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 18 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated external circuits. Fig 11. Active communication mode Table 10. Communication overview for Active communication mode Communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s Initiator  Target According to ISO/IEC 14443A 100 % ASK, Modified Miller Coded According to FeliCa, 8-30 % ASK Manchester Coded digital capability to handle Target  Initiator this communication host NFC INITIATOR powered to generate RF field 1. initiator starts communication at selected transfer speed Initial command response 2. target answers at the same transfer speed host NFC INITIATOR powered for digital processing host host NFC TARGET NFC TARGET powered for digital processing powered to generate RF field 001aan216 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 19 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. The contactless UART of PN512 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN512 supports these transfer speeds only with dedicated external circuits. Fig 12. Passive communication mode Table 11. Communication overview for Passive communication mode Communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s, 3.39 Mbit/s Initiator  Target According to ISO/IEC 14443A 100 % ASK, Modified Miller Coded According to FeliCa, 8-30 % ASK Manchester Coded digital capability to handle this communication Target  Initiator According to ISO/IEC 14443A subcarrier load modulation, Manchester Coded According to FeliCa, > 12 % ASK Manchester Coded host NFC INITIATOR powered to generate RF field 1. initiator starts communication at selected transfer speed 2. targets answers using load modulated data at the same transfer speed host NFC TARGET powered for digital processing 001aan217 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 20 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. 8.4.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is according to the following policy: • Speed shall not be changed while continuum data exchange in a transaction. • Transaction includes initialization and anticollision methods and data exchange (in continuous way, meaning no interruption by another transaction). In order not to disturb current infrastructure based on 13.56 MHz general rules to start NFCIP-1 communication are defined in the following way. 1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off. 2. The RF level detector is active. 3. Only if application requires the NFCIP-1 device shall switch to Initiator mode. 4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level detector during a time of TIDT. 5. The initiator performs initialization according to the selected mode. 8.4.5 MIFARE Card operation mode Table 12. Framing and coding overview Transfer speed Framing and Coding 106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme 212 kbit/s According to the FeliCa scheme 424 kbit/s According to the FeliCa scheme Table 13. MIFARE Card operation mode Communication direction ISO/IEC 14443A/ MIFARE MIFARE Higher transfer speeds transfer speed 106 kbit/s 212 kbit/s 424 kbit/s reader/writer  PN512 Modulation on reader side 100 % ASK 100 % ASK 100 % ASK bit coding Modified Miller Modified Miller Modified Miller Bitlength (128/13.56) s (64/13.56) s (32/13.56) s PN512  reader/ writer Modulation on PN512 side subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz/16 13.56 MHz/16 13.56 MHz/16 bit coding Manchester coding BPSK BPSK PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 21 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 8.4.6 FeliCa Card operation mode 9. PN512 register SET 9.1 PN512 registers overview Table 14. FeliCa Card operation mode Communication direction FeliCa FeliCa Higher transfer speeds Transfer speed 212 kbit/s 424 kbit/s reader/writer  PN512 Modulation on reader side 8-30 % ASK 8-30 % ASK bit coding Manchester Coding Manchester Coding Bitlength (64/13.56) s (32/13.56) s PN512  reader/ writer Load modulation on PN512 side > 12 % ASK load modulation > 12 % ASK load modulation bit coding Manchester coding Manchester coding Table 15. PN512 registers overview Addr (hex) Register Name Function Page 0: Command and Status 0 PageReg Selects the register page 1 CommandReg Starts and stops command execution 2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests 3 DivlEnReg Controls bits to enable and disable the passing of Interrupt Requests 4 ComIrqReg Contains Interrupt Request bits 5 DivIrqReg Contains Interrupt Request bits 6 ErrorReg Error bits showing the error status of the last command executed 7 Status1Reg Contains status bits for communication 8 Status2Reg Contains status bits of the receiver and transmitter 9 FIFODataReg In- and output of 64 byte FIFO-buffer A FIFOLevelReg Indicates the number of bytes stored in the FIFO B WaterLevelReg Defines the level for FIFO under- and overflow warning C ControlReg Contains miscellaneous Control Registers D BitFramingReg Adjustments for bit oriented frames E CollReg Bit position of the first bit collision detected on the RF-interface F RFU Reserved for future use Page 1: Command 0 PageReg Selects the register page 1 ModeReg Defines general modes for transmitting and receiving 2 TxModeReg Defines the data rate and framing during transmission 3 RxModeReg Defines the data rate and framing during receiving 4 TxControlReg Controls the logical behavior of the antenna driver pins TX1 and TX2 5 TxAutoReg Controls the setting of the antenna drivers PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 22 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6 TxSelReg Selects the internal sources for the antenna driver 7 RxSelReg Selects internal receiver settings 8 RxThresholdReg Selects thresholds for the bit decoder 9 DemodReg Defines demodulator settings A FelNFC1Reg Defines the length of the valid range for the receive package B FelNFC2Reg Defines the length of the valid range for the receive package C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit D ManualRCVReg Allows manual fine tuning of the internal receiver E TypeBReg Configure the ISO/IEC 14443 type B F SerialSpeedReg Selects the speed of the serial UART interface Page 2: CFG 0 PageReg Selects the register page 1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation 2 3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when the driver is switched off 4 ModWidthReg Controls the setting of the ModWidth 5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit 6 RFCfgReg Configures the receiver gain and RF level 7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation when the drivers are switched on 8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during times of no modulation 9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during modulation A TModeReg TPrescalerReg Defines settings for the internal timer B C TReloadReg Describes the 16-bit timer reload value D E TCounterValReg Shows the 16-bit actual timer value F Page 3: TestRegister 0 PageReg selects the register page 1 TestSel1Reg General test signal configuration 2 TestSel2Reg General test signal configuration and PRBS control 3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial interfaces only) 4 TestPin ValueReg Defines the values for the 8-bit parallel bus when it is used as I/O bus 5 TestBusReg Shows the status of the internal testbus 6 AutoTestReg Controls the digital selftest Table 15. PN512 registers overview …continued Addr (hex) Register Name Function PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 23 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.1.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In Table 16 the access conditions are described. 7 VersionReg Shows the version 8 AnalogTestReg Controls the pins AUX1 and AUX2 9 TestDAC1Reg Defines the test value for the TestDAC1 A TestDAC2Reg Defines the test value for the TestDAC2 B TestADCReg Shows the actual value of ADC I and Q C-F RFT Reserved for production tests Table 15. PN512 registers overview …continued Addr (hex) Register Name Function Table 16. Behavior of register bits and its designation Abbreviation Behavior Description r/w read and write These bits can be written and read by the -Controller. Since they are used only for control means, there content is not influenced by internal state machines, e.g. the PageSelect-Register may be written and read by the -Controller. It will also be read by internal state machines, but never changed by them. dy dynamic These bits can be written and read by the -Controller. Nevertheless, they may also be written automatically by internal state machines, e.g. the Command-Register changes its value automatically after the execution of the actual command. r read only These registers hold bits, which value is determined by internal states only, e.g. the CRCReady bit can not be written from external but shows internal states. w write only Reading these registers returns always ZERO. RFU - These registers are reserved for future use. In case of a PN512 Version version 2.0 (VersionReg = 82h) a read access to these registers returns always the value “0”. Nevertheless this is not guaranteed for future chips versions where the value is undefined. In case of a write access, it is recommended to write always the value “0”. RFT - These registers are reserved for production tests and shall not be changed. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 24 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2 Register description 9.2.1 Page 0: Command and status 9.2.1.1 PageReg Selects the register page. 9.2.1.2 CommandReg Starts and stops command execution. Table 17. PageReg register (address 00h); reset value: 00h, 0000000b 7 6 5 4 3 2 1 0 UsePage Select 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 18. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case it specifies the register page (which is A5 and A4 of the register address). Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 RcvOff Power Down Command Access Rights RFU RFU r/w dy dy dy dy dy Table 20. Description of CommandReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 RcvOff Set to logic 1, the analog part of the receiver is switched off. 4 PowerDown Set to logic 1, Soft Power-down mode is entered. Set to logic 0, the PN512 starts the wake up procedure. During this procedure this bit still shows a 1. A 0 indicates that the PN512 is ready for operations; see Section 16.2 “Soft power-down mode”. Note: The bit Power Down cannot be set, when the command SoftReset has been activated. 3 to 0 Command Activates a command according to the Command Code. Reading this register shows, which command is actually executed (see Section 19.3 “PN512 command overview”). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 25 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 22. Description of CommIEnReg bits Bit Symbol Description 7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with bit IRqPushPull in register DivIEnReg, the default value of 1 ensures, that the output level on pin IRQ is 3-state. 6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be propagated to pin IRQ. 5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be propagated to pin IRQ. 4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to pin IRQ. 3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be propagated to pin IRQ. 2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be propagated to pin IRQ. 1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated to pin IRQ. 0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 26 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn Access Rights r/w RFU RFU r/w r/w r/w r/w r/w Table 24. Description of DivIEnReg bits Bit Symbol Description 7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad. Set to logic 0, the pin IRQ works as open drain output pad. 6 to 5 - Reserved for future use. 4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ. 3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be propagated to pin IRQ. 2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be propagated to pin IRQ. 1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to be propagated to pin IRQ. 0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to be propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 27 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b 7 6 5 4 3 2 1 0 Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq Access Rights w dy dy dy dy dy dy dy Table 26. Description of CommIRqReg bits All bits in the register CommIRqReg shall be cleared by software. Bit Symbol Description 7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg are set. Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg are cleared. 6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out. 5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream. If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set to logic 1 when data bytes are available in the FIFO. 4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the CommandReg changes its value from any command to the Idle Command. If an unknown command is started, the CommandReg changes its content to the idle state and the bit IdleIRq is set. Starting the Idle Command by the -Controller does not set bit IdleIRq. 3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit Set1. 2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit Set1. 1 ErrIRq Set to logic 1 if any error bit in the Error Register is set. 0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 28 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb 7 6 5 4 3 2 1 0 Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq Access Rights w RFU RFU dy dy dy dy dy Table 28. Description of DivIRqReg bits All bits in the register DivIRqReg shall be cleared by software. Bit Symbol Description 7 Set2 Set to logic 1, Set2 defines that the marked bits in the register DivIRqReg are set. Set to logic 0, Set2 defines, that the marked bits in the register DivIRqReg are cleared 6 to 5 - Reserved for future use. 4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “S2C interface support”. This interrupt is set when either a rising or falling signal edge is detected. 3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode detector. Note: The Data mode detector can only be activated by the AutoColl command and is terminated automatically having detected the Communication mode. Note: The Data mode detector is automatically restarted after each RF Reset. 2 CRCIRq Set to logic 1, when the CRC command is active and all data are processed. 1 RFOnIRq Set to logic 1, when an external RF field is detected. 0 RFOffIRq Set to logic 1, when a present external RF field is switched off. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 29 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. [1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr Access Rights r r r r r r r r Table 30. Description of ErrorReg bits Bit Symbol Description 7 WrErr Set to logic 1, when data is written into FIFO by the host controller during the AutoColl command or MFAuthent command or if data is written into FIFO by the host controller during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface. 6 TempErr[1] Set to logic 1, if the internal temperature sensor detects overheating. In this case, the antenna drivers are switched off automatically. 5 RFErr Set to logic 1, if in Active Communication mode the counterpart does not switch on the RF field in time as defined in NFCIP-1 standard. Note: RFErr is only used in Active Communication mode. The bits RxFraming or the bits TxFraming has to be set to 01 to enable this functionality. 4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine (e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer although the FIFO-buffer is already full. 3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at receiver start-up phase. This bit is only valid during the bitwise anticollision at 106 kbit. During communication schemes at 212 and 424 kbit this bit is always set to logic 1. 2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the CRC calculation fails. It is cleared to 0 automatically at receiver start-up phase. 1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or NFCIP-1 communication at 106 kbit. 0 ProtocolErr Set to logic 1, if one out of the following cases occur: • Set to logic 1 if the SOF is incorrect. It is cleared automatically at receiver start-up phase. The bit is only valid for 106 kbit in Active and Passive Communication mode. • If bit DetectSync in register ModeReg is set to logic 1 during FeliCa communication or active communication with transfer speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in case of a byte length violation. • During the AutoColl command, bit ProtocolErr is set to logic 1, if the bit Initiator in register ControlReg is set to logic 1. • During the MFAuthent Command, bit ProtocolErr is set to logic 1, if the number of bytes received in one data stream is incorrect. • Set to logic 1, if the Miller Decoder detects 2 pulses below the minimum time according to the ISO/IEC 14443A definitions. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 30 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb 7 6 5 4 3 2 1 0 RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert Access Rights r r r r r r r r Table 32. Description of Status1Reg bits Bit Symbol Description 7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of 13.56 MHz. Set to logic 1, if the frequency at the RX pin is in the range 12 MHz < RX pin frequency < 15 MHz. Note: The value of RFFreqOK is not defined if the external RF frequency is in the range from 9 to 12 MHz or in the range from 15 to 19 MHz. 6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and reception the bit CRCOk is undefined (use CRCErr in register ErrorReg). CRCOk indicates the status of the CRC co-processor, during calculation the value changes to ZERO, when the calculation is done correctly, the value changes to ONE. 5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only valid for the CRC co-processor calculation using the command CalcCRC. 4 IRq This bit shows, if any interrupt source requests attention (with respect to the setting of the interrupt enable bits, see register CommIEnReg and DivIEnReg). 3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will decrement the TCounterValReg with the next timer clock. Note: In the gated mode the bit TRunning is set to logic 1, when the timer is enabled by the register bits. This bit is not influenced by the gated signal. 2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store the state of the RF field. 1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer fulfills the following equation: Example: FIFOLength = 60, WaterLevel = 4  HiAlert = 1 FIFOLength = 59, WaterLevel = 4  HiAlert = 0 0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer fulfills the following equation: Example: FIFOLength = 4, WaterLevel = 4  LoAlert = 1 FIFOLength = 5, WaterLevel = 4  LoAlert = 0 HiAlert = 64 – FIFOLength   WaterLevel LoAlert = FIFOLength  WaterLevel PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 31 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TempSensClear I2CForceHS 0 TargetActivated MFCrypto1On Modem State Access Rights r/w r/w RFU dy dy r r r Table 34. Description of Status2Reg bits Bit Symbol Description 7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature is below the alarm limit of 125 C. 6 I2CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the High-speed mode independent of the I2C protocol. Set to logic 0, the I2C input filter is set to the used I2C protocol. 5 - Reserved for future use. 4 TargetActivated Set to logic 1 if the Select command or if the Polling command was answered. Note: This bit can only be set during the AutoColl command in Passive Communication mode. Note: This bit is cleared automatically by switching off the external RF field. 3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and therefore all data communication with the card is encrypted. This bit can only be set to logic 1 by a successful execution of the MFAuthent Command. This bit is only valid in Reader/Writer mode for MIFARE cards. This bit shall be cleared by software. 2 to 0 Modem State ModemState shows the state of the transmitter and receiver state machines. Value Description 000 IDLE 001 Wait for StartSend in register BitFramingReg 010 TxWait: Wait until RF field is present, if the bit TxWaitRF is set to logic 1. The minimum time for TxWait is defined by the TxWaitReg register. 011 Sending 100 RxWait: Wait until RF field is present, if the bit RxWaitRF is set to logic 1. The minimum time for RxWait is defined by the RxWaitReg register. 101 Wait for data 110 Receiving PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 32 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. 9.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 FIFOData Access Rights dy dy dy dy dy dy dy dy Table 36. Description of FIFODataReg bits Bit Symbol Description 7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The FIFO-buffer acts as parallel in/parallel out converter for all serial data stream in- and outputs. Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 FlushBuffer FIFOLevel Access Rights w r r r r r r r Table 38. Description of FIFOLevelReg bits Bit Symbol Description 7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and write-pointer and the bit BufferOvfl in the register ErrReg immediately. Reading this bit will always return 0. 6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the FIFODataReg increments, reading decrements the FIFOLevel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 33 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. 9.2.1.13 ControlReg Miscellaneous control bits. Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b 7 6 5 4 3 2 1 0 0 0 WaterLevel Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 40. Description of WaterLevelReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or underflow: The bit HiAlert in Status1Reg is set to logic 1, if the remaining number of bytes in the FIFO-buffer space is equal or less than the defined number of WaterLevel bytes. The bit LoAlert in Status1Reg is set to logic 1, if equal or less than WaterLevel bytes are in the FIFO. Note: For the calculation of HiAlert and LoAlert see Table 31 Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits Access Rights w w dy r/w RFU r r r Table 42. Description of ControlReg bits Bit Symbol Description 7 TStopNow Set to logic 1, the timer stops immediately. Reading this bit will always return 0. 6 TStartNow Set to logic 1 starts the timer immediately. Reading this bit will always return 0. 5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the FIFO. Afterwards the bit is cleared automatically 4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target 3 - Reserved for future use. 2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the whole byte is valid. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 34 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 StartSend RxAlign 0 TxLastBits Access Rights w r/w r/w r/w RFU r/w r/w r/w Table 44. Description of BitFramingReg bits Bit Symbol Description 7 StartSend Set to logic 1, the transmission of data starts. This bit is only valid in combination with the Transceive command. 6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position for the first bit received to be stored in the FIFO. Further received bits are stored at the following bit positions. Example: RxAlign = 0: the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1. RxAlign = 1: the LSB of the received bit is stored at bit 1, the second received bit is stored at bit position 2. RxAlign = 7: the LSB of the received bit is stored at bit 7, the second received bit is stored in the following byte at bit position 0. This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive Communication mode. In all other modes it shall be set to logic 0. 3 - Reserved for future use. 2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the number of bits of the last byte that shall be transmitted. A 000 indicates that all bits of the last byte shall be transmitted. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 35 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb 7 6 5 4 3 2 1 0 Values AfterColl 0 CollPos NotValid CollPos Access Rights r/w RFU r r r r r r Table 46. Description of CollReg bits Bit Symbol Description 7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a collision. This bit shall only be used during bitwise anticollision at 106 kbit, otherwise it shall be set to logic 1. 6 - Reserved for future use. 5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the Collision is out of the range of bits CollPos. This bit shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode. 4 to 0 CollPos These bits show the bit position of the first detected collision in a received frame, only data bits are interpreted. Example: 00h indicates a bit collision in the 32th bit 01h indicates a bit collision in the 1st bit 08h indicates a bit collision in the 8th bit These bits shall only be interpreted in Passive Communication mode at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit CollPosNotValid is set to logic 0. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 36 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2 Page 1: Communication 9.2.2.1 PageReg Selects the register page. Table 47. PageReg register (address 10h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePage Select 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 48. Description of PageReg bits Bit Symbol Description 7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to logic 1. In this case it specifies the register page (which is A5 and A4 of the register address). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 37 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b 7 6 5 4 3 2 1 0 MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 50. Description of ModeReg bits Bit Symbol Description 7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB first and the CRCResultMSB and the CRCResultLSB in the CRCResultReg register are bit reversed. Note: During RF communication this bit is ignored. 6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before the receiver is activated and F0h is added as a Sync-byte for transmission. This bit is only valid for 106 kbit during NFCIP-1 data exchange protocol. In all other modes it shall be set to logic 0. 5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for NFCIP-1 can only be started, if an RF field is generated. 4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field is detected in Target mode for NFCIP-1 or in Card Communication mode. 3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN pin is active low. Note: The internal envelope signal is coded active low. Note: Changing this bit will generate a SiginActIRq event. 2 ModeDetOff Set to logic 1, the internal mode detector is switched off. Note: The mode detector is only active during the AutoColl command. 1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command CalCRC. Note: During any communication, the preset values is selected automatically according to the definition in the bits RxMode and TxMode. Value Description 00 0000 01 6363 10 A671 11 FFFF PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 38 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TxCRCEn TxSpeed InvMod TxMix TxFraming Access Rights r/w dy dy dy r/w r/w dy dy Table 52. Description of TxModeReg bits Bit Symbol Description 7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data transmission. Note: This bit shall only be set to logic 0 at 106 kbit. 6 to 4 TxSpeed Defines the bit rate while data transmission. Value Description 000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to the bit coding of Active Communication mode 424 kbit (Ecma 340). 3 InvMod Set to logic 1, the modulation for transmitting data is inverted. 2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder (see Section 12.6 “S2C interface support”). 1 to 0 TxFraming Defines the framing used for data transmission. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive communication mode 212 and 424 kbit 11 ISO/IEC 14443B PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 39 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming Access Rights r/w dy dy dy r/w r/w dy dy Table 54. Description of RxModeReg bits Bit Symbol Description 7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception. Note: This bit shall only be set to logic 0 at 106 kbit. 6 to 4 RxSpeed Defines the bit rate while data transmission. The PN512’s analog part handles only transfer speeds up to 424 kbit internally, the digital UART handles the higher transfer speeds as well. Value Description 000 106 kbit 001 212 kbit 010 424 kbit 011 848 kbit 100 1696 kbit 101 3392 kbit 110 Reserved 111 Reserved Note: The bit coding for transfer speeds above 424 kbit is equivalent to the bit coding of Active Communication mode 424 kbit (Ecma 340). 3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits received) will be ignored. The receiver will remain active. For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non valid datastream. 2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame. Set to logic 1, it is possible to receive more than one data frame. Having set this bit, the receive and transceive commands will not terminate automatically. In this case the multiple receiving can only be deactivated by writing any command (except the Receive command) to the CommandReg register or by clearing the bit by the host controller. At the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the ErrorReg register. The behaviour for version 1.0 is described in Section 21 “Errata sheet” on page 109. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 40 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. 1 to 0 RxFraming Defines the expected framing for data reception. Value Description 00 ISO/IEC 14443A/MIFARE and Passive Communication mode 106 kbit 01 Active Communication mode 10 FeliCa and Passive Communication mode 212 and 424 kbit 11 ISO/IEC 14443B Table 54. Description of RxModeReg bits Bit Symbol Description Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 InvTx2RF On InvTx1RF On InvTx2RF Off InvTx1RF Off Tx2CW CheckRF Tx2RF En Tx1RF En Access Rights r/w r/w r/w r/w r/w w r/w r/w Table 56. Description of TxControlReg bits Bit Symbol Description 7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is enabled. 6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is enabled. 5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2 is disabled. 4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1 is disabled. 3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the un-modulated 13.56 MHz energy carrier. Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy carrier. 2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF field is detected. Only valid when using in combination with bit Tx2RFEn or Tx1RFEn 1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz energy carrier modulated by the transmission data. 0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz energy carrier modulated by the transmission data. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 41 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 AutoRF OFF Force100 ASK Auto WakeUp 0 CAOn InitialRF On Tx2RFAut oEn Tx1RFAuto En Access Rights r/w r/w r/w RFU r/w r/w r/w r/w Table 58. Description of TxAutoReg bits Bit Symbol Description 7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last data bit has been transmitted as defined in the NFCIP-1. 6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation independent of the setting in register ModGsPReg. 5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by the RF level detector. 4 - Reserved for future use. 3 CAOn Set to logic 1, the collision avoidance is activated and internally the value n is set in accordance to the NFCIP-1 Standard. 2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit InitialRFOn is cleared automatically, if the RF is switched on. Note: The driver, which should be switched on, has to be enabled by bit Tx2RFAutoEn or bit Tx1RFAutoEn. 1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field is switched off according to the time TADT. If the bits InitialRFOn and Tx2RFAutoEn are set to logic 1, Tx2 is switched on if no external RF field is detected during the time TIDT. Note: The times TADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092). 0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field is switched off according to the time TADT. If the bit InitialRFOn and Tx1RFAutoEn are set to logic 1, Tx1 is switched on if no external RF field is detected during the time TIDT. Note: The times TADT and TIDT are defined in the NFC IP-1 standard (ISO/IEC 18092). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 42 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.7 TxSelReg Selects the sources for the analog part. Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b 7 6 5 4 3 2 1 0 0 0 DriverSel SigOutSel Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 60. Description of TxSelReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 DriverSel Selects the input of driver Tx1 and Tx2. Value Description 00 Tristate Note: In soft power down the drivers are only in Tristate mode if DriverSel is set to Tristate mode. 01 Modulation signal (envelope) from the internal coder 10 Modulation signal (envelope) from SIGIN 11 HIGH Note: The HIGH level depends on the setting of InvTx1RFOn/ InvTx1RFOff and InvTx2RFOn/InvTx2RFOff. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 43 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 3 to 0 SigOutSel Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. 0100 Modulation signal (envelope) from the internal coder 0101 Serial data stream to be transmitted 0110 Output signal of the receiver circuit (card modulation signal regenerated and delayed). This signal is used as data output signal for SAM interface connection using 3 lines. Note: To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. Note: Do not use this setting in MIFARE mode. Manchester coding as data collisions will not be transmitted on the SIGOUT line. 0111 Serial data stream received. Note: Do not use this setting in MIFARE mode. Miller coding parameters as the bit length can vary. 1000-1011 FeliCa Sam modulation 1000 RX* 1001 TX 1010 Demodulator comparator output 1011 RFU Note: * To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. 1100-1111 MIFARE Sam modulation 1100 RX* with RF carrier 1101 TX with RF carrier 1110 RX with RF carrier un-filtered 1111 RX envelope un-filtered Note: *To have a valid signal the PN512 has to be set to the receiving mode by either the Transceive or Receive command. The bit RxMultiple can be used to keep the PN512 in receiving mode. Table 60. Description of TxSelReg bits …continued Bit Symbol Description PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 44 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.8 RxSelReg Selects internal receiver settings. 9.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b 7 6 5 4 3 2 1 0 UartSel RxWait Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 62. Description of RxSelReg bits Bit Symbol Description 7 to 6 UartSel Selects the input of the contactless UART Value Description 00 Constant Low 01 Envelope signal at SIGIN 10 Modulation signal from the internal analog part 11 Modulation signal from SIGIN pin. Only valid for transfer speeds above 424 kbit 5 to 0 RxWait After data transmission, the activation of the receiver is delayed for RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX is ignored. This parameter is ignored by the Receive command. All other commands (e.g. Transceive, Autocoll, MFAuthent) use this parameter. Depending on the mode of the PN512, the counter starts different. In Passive Communication mode the counter starts with the last modulation pulse of the transmitted data stream. In Active Communication mode the counter starts immediately after the external RF field is switched on. Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b 7 6 5 4 3 2 1 0 MinLevel 0 CollLevel Access Rights r/w r/w r/w r/w RFU r/w r/w r/w Table 64. Description of RxThresholdReg bits Bit Symbol Description 7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be accepted. If the signal strength is below this level, it is not evaluated. 3 - Reserved for future use. 2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be reached by the weaker half-bit of the Manchester-coded signal to generate a bit-collision relatively to the amplitude of the stronger half-bit. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 45 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.10 DemodReg Defines demodulator settings. Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b 7 6 5 4 3 2 1 0 AddIQ FixIQ TPrescal Even TauRcv TauSync Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 66. Description of DemodReg bits Bit Symbol Description 7 to 6 AddIQ Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings. Value Description 00 Select the stronger channel 01 Select the stronger and freeze the selected during communication 10 combines the I and Q channel 11 Reserved 5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to I channel. If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to Q channel. NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ set to X0 is rewired. 4 TPrescalE ven If set to logic 0 the following formula is used to calculate fTimer of the prescaler: fTimer = 13.56 MHz / (2 * TPreScaler + 1). If set to logic 1 the following formula is used to calculate fTimer of the prescaler: fTimer = 13.56 MHz / (2 * TPreScaler + 2). (Default TPrescalEven is logic 0) The behaviour for the version 1.0 is described in Section 21 “Errata sheet” on page 109. 3 to 2 TauRcv Changes the time constant of the internal during data reception. Note: If set to 00, the PLL is frozen during data reception. 1 to 0 TauSync Changes the time constant of the internal PLL during burst. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 46 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 FelSyncLen DataLenMin Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 68. Description of FelNFC1Reg bits Bit Symbol Description 7 to 6 FelSyncLen Defines the length of the Sync bytes. Value Sync- bytes in hex 00 B2 4D 01 00 B2 4D 10 00 00 B2 4D 11 00 00 00 B2 4D 5 to 0 DataLenMin These bits define the minimum length of the accepted packet length: DataLenMin * 4  data packet length This parameter is ignored at 106 kbit if the bit DetectSync in register ModeReg is set to logic 0. If a received data packet is shorter than the defined DataLenMin value, the data packet will be ignored. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 47 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 WaitForSelected ShortTimeSlot DataLenMax Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 70. Description of FelNFC2Reg bits Bit Symbol Description 7 WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1. A valid command has been received after performing a valid Select procedure according ISO/IEC 14443A. 2. A valid command has been received after performing a valid Polling procedure according to the FeliCa specification. Note: If this bit is set, no active communication is possible. Note: Setting this bit reduces the host controller interaction in case of a communication to another device in the same RF field during Passive Communication mode. 6 ShortTimeSlot Defines the time slot length for Passive Communication mode at 424 kbit. Set to logic 1 a short time slot is used (half of the timeslot at 212 kbit). Set to logic 0 a long timeslot is used (equal to the timeslot for 212 kbit). 5 to 0 DataLenMax These bits define the maximum length of the accepted packet length: DataLenMax * 4  data packet length Note: If set to logic 0 the maximum data length is 256 bytes. This parameter is ignored at 106 kbit if the bit DetectSync in register ModeReg is set to logic 0. If a received packet is larger than the defined DataLenMax value, the packet will be ignored. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 48 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b 7 6 5 4 3 2 1 0 SensMiller TauMiller MFHalted TxWait Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 72. Description of MifNFCReg bits Bit Symbol Description 7 to 5 SensMiller These bits define the sensitivity of the Miller decoder. 4 to 3 TauMiller These bits define the time constant of the Miller decoder. 2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in Card Operation mode at 106 kbit. This bit is either set by the host controller or by the internal state machine and indicates that only the code 52h is accepted as a request command. This bit is cleared automatically by a RF reset. 1 to 0 TxWait These bits define the minimum response time between receive and transmit in number of data bits + 7 data bits. The shortest possible minimum response time is 7 data bits. (TxWait=0). The minimum response time can be increased by the number of bits defined in TxWait. The longest minimum response time is 10 data bits (TxWait = 3). If a transmission of a frame is started before the minimum response time is over, the PN512 waits before transmitting the data until the minimum response time is over. If a transmission of a frame is started after the minimum response time is over, the frame is started immediately if the data bit synchronization is correct. (adjustable with TxBitPhase). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 49 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 0 FastFilt MF_SO Delay MF_SO Parity Disable LargeBW PLL Manual HPCF HPFC Access Rights RFU r/w r/w r/w r/w r/w r/w r/w Table 74. Description of ManualRCVReg bits Bit Symbol Description 7 - Reserved for future use. 6 FastFilt MF_SO If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is set to Fast mode. Note: This bit should only set to logic 1, if Millerpulses of less than 400 ns Pulse length are expected. At 106 kBaud the typical value is 3 us. 5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that in SAM mode the Signal at SIGIN must be 128/fc faster compared to the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the RF-Field. Note: This delay shall only be activated for setting bits SigOutSel to (1110b) or (1111b) in register TxSelReg. 4 Parity Disable If this bit is set to logic 1, the generation of the Parity bit for transmission and the Parity-Check for receiving is switched off. The received Parity bit is handled like a data bit. 3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock recovery is extended. 2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are adapted automatically to the receiving mode. Set to logic 1, values of HPCF are valid. 1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the internal receiver chain 00 For signals with frequency spectrum down to 106 kHz. 01 For signals with frequency spectrum down to 212 kHz. 10 For signals with frequency spectrum down to 424 kHz. 11 For signals with frequency spectrum down to 848 kHz PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 50 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.2.15 TypeBReg 9.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 RxSOF Req RxEOF Req 0 EOFSO FWidth NoTxSOF NoTxEOF TxEGT Access Rights r/w r/w RFU r/w r/w r/w r/w r/w Table 76. Description of TypeBReg bits Bit Symbol Description 7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting without SOF is ignored. If this bit is cleared, a datastream with and without SOF is accepted. The SOF will be removed and not written into the FIFO. 6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending without EOF will generate a Protocol-Error. If this bit is cleared, a datastream with and without EOF is accepted. The EOF will be removed and not written into the FIFO. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 5 - Reserved for future use. 4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF and EOF will have the maximum length defined in ISO/IEC 14443B. If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and EOF will have the minimum length defined in ISO/IEC 14443B. If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in SOF low = (11etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in an incorrect system behavior in respect to ISO specification. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed. 2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed. 1 to 0 TxEGT These bits define the length of the EGT. Value Description 00 0 bit 01 1 bit 10 2 bits 11 3 bits PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 51 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b 7 6 5 4 3 2 1 0 BR_T0 BR_T1 Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 78. Description of SerialSpeedReg bits Bit Symbol Description 7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”. 3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section 10.3.2 “Selectable UART transfer speeds”. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 52 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3 Page 2: Configuration 9.2.3.1 PageReg Selects the register page. 9.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Note: The CRC is split into two 8-bit register. Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is not changed. Table 79. PageReg register (address 20h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePageSelect 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w Table 80. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case, it specifies the register page (which is A5 and A4of the register address). Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 CRCResultMSB Access Rights r r r r r r r r Table 82. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of the CRCResultReg register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 CRCResultLSB Access Rights r r r r r r r r Table 84. Description of CRCResultReg bits Bit Symbol Description 7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of the CRCResult register. It is valid only if bit CRCReady in register Status1Reg is set to logic 1. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 53 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.3 GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b 7 6 5 4 3 2 1 0 CWGsNOff ModGsNOff Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 86. Description of GsNOffReg bits Bit Symbol Description 7 to 4 CWGsNOff The value of this register defines the conductance of the output N-driver during times of no modulation. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched off. Otherwise the bit value CWGsNOn of register GsNOnReg is used. Note: This value is used for LoadModulation. 3 to 0 ModGsNOff The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: The value of the register is only used if the driver is switched off. Otherwise the bit value ModGsNOn of register GsNOnReg is used Note: This value is used for LoadModulation. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 54 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.4 ModWidthReg Controls the modulation width settings. 9.2.3.5 TxBitPhaseReg Adjust the bitphase at 106 kbit during transmission. Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b 7 6 5 4 3 2 1 0 ModWidth Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 88. Description of ModWidthReg bits Bit Symbol Description 7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active and Passive Communication mode as multiples of the carrier frequency (ModWidth + 1/fc). The maximum value is half the bit period. Acting as a target in Passive Communication mode at 106 kbit or in Card Operating mode for ISO/IEC 14443A/MIFARE these bits are used to change the duty cycle of the subcarrier frequency. The resulting number of carrier periods are calculated according to the following formulas: LOW value: #clocksLOW = (ModWidth modulo 8) + 1. HIGH value: #clocksHIGH = 16-#clocksLOW. Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b 7 6 5 4 3 2 1 0 RcvClkChange TxBitPhase Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 90. Description of TxBitPhaseReg bits Bit Symbol Description 7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF field. 6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock cycles, which are added to the waiting period before transmitting data in all communication modes. TXBitPhase is used to adjust the TX bit synchronization during passive NFCIP-1 communication mode at 106 kbit and in ISO/IEC 14443A/MIFARE card mode. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 55 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b 7 6 5 4 3 2 1 0 RFLevelAmp RxGain RFLevel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 92. Description of RFCfgReg bits Bit Symbol Description 7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier. 6 to 4 RxGain This register defines the receivers signal voltage gain factor: Value Description 000 18 dB 001 23 dB 010 18 dB 011 23 dB 100 33 dB 101 38 dB 110 43 dB 111 48 dB 3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see Section 12.3 “RF level detector”. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 56 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. 9.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b 7 6 5 4 3 2 1 0 CWGsNOn ModGsNOn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 94. Description of GsNOnReg bits Bit Symbol Description 7 to 4 CWGsNOn The value of this register defines the conductance of the output N-driver during times of no modulation. This may be used to regulate the output power and subsequently current consumption and operating distance. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or TX2 are switched on. Otherwise the value of the bits CWGsNOff of register GsNOffReg is used. 3 to 0 ModGsNOn The value of this register defines the conductance of the output N-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Note: This value is only used if the driver TX1 or Tx2 are switched on. Otherwise the value of the bits ModsNOff of register GsNOffReg is used. Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 CWGsP Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 96. Description of CWGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 CWGsP The value of this register defines the conductance of the output P-driver. This may be used to regulate the output power and subsequently current consumption and operating distance. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 57 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. [1] If Force100ASK is set to logic 1, the value of ModGsP has no effect. 9.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Note: The Prescaler value is split into two 8-bit registers Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b 7 6 5 4 3 2 1 0 0 0 ModGsP Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 98. Description of ModGsPReg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 ModGsP[1] The value of this register defines the conductance of the output P-driver for the time of modulation. This may be used to regulate the modulation index. Note: The conductance value is binary weighted. Note: During soft Power-down mode the highest bit is forced to 1. Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TAuto TGated TAutoRestart TPrescaler_Hi Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 100. Description of TModeReg bits Bit Symbol Description 7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission in all communication modes at all speeds or when bit InitialRFOn is set to logic 1 and the RF field is switched on. In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is not set. In all other modes, the timer stops after the 4th bit if the bit RxMultiple the register RxModeReg is not set. If RxMultiple is set to logic 1, the timer never stops. In this case the timer can be stopped by setting the bit TStopNow in register ControlReg to 1. Set to logic 0 indicates, that the timer is not influenced by the protocol. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 58 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 6 to 5 TGated The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits. This bit does not influence the gating signal. Value Description 00 Non gated mode 01 Gated by SIGIN 10 Gated by AUX1 11 Gated by A3 4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from TReloadValue, instead of counting down to zero. Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set to logic 1. 3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler. The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 0: fTimer = 13.56 MHz/(2*TPreScaler+1). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) (Default TPrescalEven is logic 0) The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1: fTimer = 13.56 MHz/(2*TPreScaler+2). For detailed description see Section 15 “Timer unit”. For the behaviour within version 1.0, see Section 21 “Errata sheet” on page 109. Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TPrescaler_Lo Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 102. Description of TPrescalerReg bits Bit Symbol Description 7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler. The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 0: fTimer = 13.56 MHz/(2*TPreScaler+1). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) The following formula is used to calculate fTimer if TPrescalEven bit in Demot Reg is set to logic 1: fTimer = 13.56 MHz/(2*TPreScaler+2). Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) For detailed description see Section 15 “Timer unit”. Table 100. Description of TModeReg bits …continued Bit Symbol Description PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 59 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TReloadVal_Hi Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 104. Description of the higher TReloadReg bits Bit Symbol Description 7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TReloadVal_Lo Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 106. Description of lower TReloadReg bits Bit Symbol Description 7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg. With a start event the timer loads the TReloadVal. Changing this register affects the timer only at the next start event. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 60 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. 9.2.4 Page 3: Test 9.2.4.1 PageReg Selects the register page. Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TCounterVal_Hi Access Rights r r r r r r r r Table 108. Description of the higher TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits. Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TCounterVal_Lo Access Rights r r r r r r r r Table 110. Description of lower TCounterValReg bits Bit Symbol Description 7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits. Table 111. PageReg register (address 30h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UsePageSelect 0 0 0 0 0 PageSelect Access Rights r/w RFU RFU RFU RFU RFU r/w r/w PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 61 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 112. Description of PageReg bits Bit Symbol Description 7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “Automatic microcontroller interface detection”. 6 to 2 - Reserved for future use. 1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to logic 1. In this case, it specifies the register page (which is A5 and A4 of the register address). PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 62 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.2 TestSel1Reg General test signal configuration. 9.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 - - SAMClockSel SAMClkD1 TstBusBitSel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 114. Description of TestSel1Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock Value Description 00 GND- Sam Clock switched off 01 clock derived by the internal oscillator 10 internal UART clock 11 clock derived by the RF field 3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1. Note: Only possible if the 8bit parallel interface is not used. 2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT. Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 TstBusFlip PRBS9 PRBS15 TestBusSel Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 116. Description of TestSel2Reg bits Bit Symbol Description 7 TstBusFlip If set to logic 1, the testbus is mapped to the parallel port by the following order: D4, D3, D2, D6, D5, D0, D1. See Section 20 “Testsignals”. 6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150. Note: All relevant registers to transmit data have to be configured before entering PRBS9 mode. Note: The data transmission of the defined sequence is started by the send command. 5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150. Note: All relevant registers to transmit data have to be configured before entering PRBS15 mode. Note: The data transmission of the defined sequence is started by the send command. 4 to 0 TestBusSel Selects the testbus. See Section 20 “Testsignals” PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 63 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. 9.2.4.5 TestPinValueReg Defines the values for the 7-bit parallel port when it is used as I/O. Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b 7 6 5 4 3 2 1 0 RS232LineEn TestPinEn Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 118. Description of TestPinEnReg bits Bit Symbol Description 7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are disabled. 6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface. Example: Setting bit 0 to 1 enables D0 Setting bit 5 to 1 enables D5 Note: Only valid if one of serial interfaces is used. If the SPI interface is used only D0 to D4 can be used. If the serial UART interface is used and RS232LineEn is set to logic 1 only D0 to D4 can be used. Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 UseIO TestPinValue Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 120. Description of TestPinValueReg bits Bit Symbol Description 7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel port in case one of the serial interfaces is used. The input/output behavior is defined by TestPinEn in register TestPinEnReg. The value for the output behavior is defined in the bits TestPinVal. Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O. 6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each output has to be enabled by the TestPinEn bits in register TestPinEnReg. Note: Reading the register indicates the actual status of the pins D6 - D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the register TestPinValueReg is read back. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 64 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.6 TestBusReg Shows the status of the internal testbus. 9.2.4.7 AutoTestReg Controls the digital selftest. 9.2.4.8 VersionReg Shows the version. Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 TestBus Access Rights r r r r r r r r Table 122. Description of TestBusReg bits Bit Symbol Description 7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the register TestSel2Reg. See Section 20 “Testsignals”. Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b 7 6 5 4 3 2 1 0 0 AmpRcv EOFSO FAdjust - SelfTest Access Rights RFT r/w RFU RFU r/w r/w r/w r/w Table 124. Description of bits Bit Symbol Description 7 - Reserved for production tests. 6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is performed non-linear. This increases the operating distance in communication modes at 106 kbit. Note: Due to the non linearity the effect of the bits MinLevel and CollLevel in the register RxThreshholdReg are as well non linear. 5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the Maximum length of SOF and EOF according to ISO/IEC14443B If set to logic 0 and the EOFSOFwidth is set to 0 will result in the Minimum length of SOF and EOF according to ISO/IEC14443B If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in SOF low = (11 etu  8 cycles)/fc SOF high = (2 etu + 8 cycles)/fc EOF low = (11 etu  8 cycles)/fc For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. 4 - Reserved for future use. 3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest command in the command register. The selftest is enabled by 1001. Note: For default operation the selftest has to be disabled by 0000. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 65 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 Version Access Rights r r r r r r r r Table 126. Description of VersionReg bits Bit Symbol Description 7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are described within Section 21 “Errata sheet” on page 109. 82h indicates PN512 version 2.0, which covers also the industrial version. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 66 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 AnalogSelAux1 AnalogSelAux2 Access Rights r/w r/w r/w r/w r/w r/w r/w r/w Table 128. Description of AnalogTestReg bits Bit Symbol Description 7 to 4 3 to 0 AnalogSelAux1 AnalogSelAux2 Controls the AUX pin. Note: All test signals are described in Section 20 “Testsignals”. Value Description 0000 Tristate 0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2) Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0010 Testsignal Corr1 Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0011 Testsignal Corr2 Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0100 Testsignal MinLevel Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0101 Testsignal ADC channel I Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0110 Testsignal ADC channel Q Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 0111 Testsignal ADC channel I combined with Q Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1000 Testsignal for production test Note: Current output. The use of 1 k pull-down resistor on AUX is recommended. 1001 SAM clock (13.56 MHz) 1010 HIGH 1011 LOW 1100 TxActive At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High during Preamble, Sync, Data and CRC. 1101 RxActive At 106 kbit: High during databit, Parity and CRC. At 212 and 424 kbit: High during data and CRC. 1110 Subcarrier detected 106 kbit: not applicable 212 and 424 kbit: High during last part of Preamble, Sync data and CRC 1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 67 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. 9.2.4.11 TestDAC2Reg Defines the testvalue for TestDAC2. 9.2.4.12 TestADCReg Shows the actual value of ADC I and Q channel. Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb 7 6 5 4 3 2 1 0 0 0 TestDAC1 Access Rights RFT RFU r/w r/w r/w r/w r/w r/w Table 130. Description of TestDAC1Reg bits Bit Symbol Description 7 - Reserved for production tests. 6 - Reserved for future use. 5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be switched to AUX1 by setting AnalogSelAux1 to 0001 in register AnalogTestReg. Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb 7 6 5 4 3 2 1 0 0 0 TestDAC2 Access Rights RFU RFU r/w r/w r/w r/w r/w r/w Table 132. Description ofTestDAC2Reg bits Bit Symbol Description 7 to 6 - Reserved for future use. 5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be switched to AUX2 by setting AnalogSelAux2 to 0001 in register AnalogTestReg. Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb 7 6 5 4 3 2 1 0 ADC_I ADC_Q Access Rights Table 134. Description of TestADCReg bits Bit Symbol Description 7 to 4 ADC_I Shows the actual value of ADC I channel. 3 to 0 ADC_Q Shows the actual value of ADC Q channel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 68 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 9.2.4.13 RFTReg 10. Digital interfaces 10.1 Automatic microcontroller interface detection The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART interfaces. The PN512 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The PN512 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections. Table 141 shows the different connection configurations. Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 136. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 138. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 Access Rights RFT RFT RFT RFT RFT RFT RFT RFT Table 140. Description of RFTReg bits Bit Symbol Description 7 to 0 - Reserved for production tests. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 69 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] only available in HVQFN 40. Table 141. Connection protocol for detecting different interface types Pin Interface type UART (input) SPI (output) I2C-bus (I/O) SDA RX NSS SDA I2C 0 0 1 EA 0 1 EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5 Table 142. Connection scheme for detecting the different interface types PN512 Parallel Interface Type Serial Interface Types Separated Read/Write Strobe Common Read/Write Strobe Pin Dedicated Address Bus Multiplexed Address Bus Dedicated Address Bus Multiplexed Address Bus UART SPI I2C ALE 1 ALE 1 AS RX NSS SDA A5[1] A5 0 A5 0 0 0 0 A4[1] A4 0 A4 0 0 0 0 A3[1] A3 0 A3 0 0 0 0 A2[1] A2 1 A2 1 0 0 0 A1 A1 1 A1 1 0 0 1 A0 A0 1 A0 0 0 1 EA NRD[1] NRD NRD NDS NDS 1 1 1 NWR[1] NWR NWR RD/NWR RD/NWR 1 1 1 NCS[1] NCS NCS NCS NCS NCS NCS NCS D7 D7 D7 D7 D7 TX MISO SCL D6 D6 D6 D6 D6 MX MOSI ADR_0 D5 D5 AD5 D5 AD5 DTRQ SCK ADR_1 D4 D4 AD4 D4 AD4 - - ADR_2 D3 D3 AD3 D3 AD3 - - ADR_3 D2 D2 AD2 D2 AD2 - - ADR_4 D1 D1 AD1 D1 AD1 - - ADR_5 D0 D0 AD0 D0 AD0 - - ADR_6 Remark: Overview on the pin behavior Pin behavior Input Output In/Out PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 70 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.2 Serial Peripheral Interface A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds up to 10 Mbit/s. When communicating with a host, the PN512 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication. An interface compatible with SPI enables high-speed serial communication between the PN512 and a microcontroller. The implemented interface is in accordance with the SPI standard. The timing specification is given in Section 26.1 on page 117. The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line is used to send data from the PN512 to the master. Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is provided by the PN512 on the falling clock edge and is stable during the rising clock edge. 10.2.1 SPI read data Reading data using SPI requires the byte order shown in Table 143 to be used. It is possible to read out up to n-data bytes. The first byte sent defines both the mode and the address. [1] X = Do not care. Remark: The MSB must be sent first. 10.2.2 SPI write data To write data to the PN512 using SPI requires the byte order shown in Table 144. It is possible to write up to n data bytes by only sending one address byte. Fig 13. SPI connection to host 001aan220 PN512 SCK SCK MOSI MOSI MISO MISO NSS NSS Table 143. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 address 1 address 2 ... address n 00 MISO X[1] data 0 data 1 ... data n  1 data n PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 71 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The first send byte defines both the mode and the address byte. [1] X = Do not care. Remark: The MSB must be sent first. 10.2.3 SPI address byte The address byte has to meet the following format. The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is set to logic 1. To write data to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define the address and the LSB is set to logic 0. 10.3 UART interface 10.3.1 Connection to a host Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s RS232LineEn bit. 10.3.2 Selectable UART transfer speeds The internal UART interface is compatible with an RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new transfer speed to the SerialSpeedReg register. Bits BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the SerialSpeedReg register. The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different transfer speeds and the relevant register settings are given in Table 11. Table 144. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 data 0 data 1 ... data n  1 data n MISO X[1] X[1] X[1] ... X[1] X[1] Table 145. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write address 0 Fig 14. UART connection to microcontrollers 001aan221 PN512 RX RX TX TX DTRQ DTRQ MX MX PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 72 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds. The selectable transfer speeds shown in Table 11 are calculated according to the following equations: If BR_T0[2:0] = 0: (1) If BR_T0[2:0] > 0: (2) Remark: Transfer speeds above 1228.8 kBd are not supported. 10.3.3 UART framing Table 146. BR_T0 and BR_T1 settings BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 BR_T0 factor 1 1 2 4 8 16 32 64 BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 147. Selectable UART transfer speeds Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1] Decimal Hexadecimal 7.2 250 FAh 0.25 9.6 235 EBh 0.32 14.4 218 DAh 0.25 19.2 203 CBh 0.32 38.4 171 ABh 0.32 57.6 154 9Ah 0.25 115.2 122 7Ah 0.25 128 116 74h 0.06 230.4 90 5Ah 0.25 460.8 58 3Ah 0.25 921.6 28 1Ch 1.45 1228.8 21 15h 0.32 transfer speed 27.12  106 BR_T0 + 1 = ------------------------------- transfer speed 27.12  106 BR_T1 + 33 2BR_T0 – 1 ----------------------------------- -----------------------------------           = Table 148. UART framing Bit Length Value Start 1-bit 0 Data 8 bits data Stop 1-bit 1 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 73 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. Read data: To read data using the UART interface, the flow shown in Table 149 must be used. The first byte sent defines both the mode and the address. Write data: To write data to the PN512 using the UART interface, the structure shown in Table 150 must be used. The first byte sent defines both the mode and the address. Table 149. Read data byte order Pin Byte 0 Byte 1 RX (pin 24) address - TX (pin 31) - data 0 (1) Reserved. Fig 15. UART read data timing diagram 001aak588 SA ADDRESS RX TX MX DTRQ A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO DATA R/W Table 150. Write data byte order Pin Byte 0 Byte 1 RX (pin 24) address 0 data 0 TX (pin 31) - address 0 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 74 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: The data byte can be sent directly after the address byte on pin RX. Address byte: The address byte has to meet the following format: (1) Reserved. Fig 16. UART write data timing diagram 001aak589 SA ADDRESS RX TX MX DTRQ A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO SA A0 A1 A2 A3 A4 A5 (1) SO DATA ADDRESS R/W R/W PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 75 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 151. 10.4 I2C Bus Interface An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I2C-bus interface is implemented according to NXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. The interface can only act in Slave mode. Therefore the PN512 does not implement clock generation or access arbitration. The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The PN512 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode. If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA as defined in the I2C-bus interface specification. See Table 171 on page 117 for timing requirements. Table 151. Address byte 0 register; address MOSI 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1 = read 0 = write reserved address Fig 17. I2C-bus interface 001aan222 PN512 SDA SCL I2C EA ADR_[5:0] PULL-UP NETWORK CONFIGURATION WIRING PULL-UP NETWORK MICROCONTROLLER PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 76 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. 10.4.2 START and STOP conditions To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. • A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH. • A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH. The I2C-bus master always generates the START and STOP conditions. The bus is busy after the START condition. The bus is free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. The START (S) and repeated START (Sr) conditions are functionally identical. Therefore, S is used as a generic term to represent both the START (S) and repeated START (Sr) conditions. 10.4.3 Byte format Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first; see Figure 22. The number of transmitted bytes during one data transfer is unrestricted but must meet the read/write cycle format. Fig 18. Bit transfer on the I2C-bus mbc621 data line stable; data valid change of data allowed SDA SCL Fig 19. START and STOP conditions mbc622 SDA SCL P STOP condition SDA SCL S START condition PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 77 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer or a repeated START (Sr) condition to start a new transfer. A master-receiver indicates the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter releases the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. Fig 20. Acknowledge on the I2C-bus mbc602 S START condition 1 2 8 9 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master Fig 21. Data transfer on the I2C-bus msc608 Sr or P SDA Sr P SCL STOP or repeated START condition S or Sr START or repeated START condition 1 2 3 - 8 9 ACK 9 ACK 1 2 7 8 MSB acknowledgement signal from slave byte complete, interrupt within slave clock line held LOW while interrupts are serviced acknowledgement signal from receiver PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 78 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.5 7-Bit addressing During the I2C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus specification for a complete list of reserved addresses. The I2C-bus address specification is dependent on the definition of pin EA. Immediately after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus address according to pin EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I2C-bus devices. If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins according to Table 141 on page 69. ADR_6 is always set to logic 0. In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration. Depending on the external wiring, the I2C-bus address pins can be used for test signal outputs. 10.4.6 Register write access To write data from the host controller using the I2C-bus to a specific register in the PN512 the following frame format must be used. • The first byte of a frame indicates the device address according to the I2C-bus rules. • The second byte indicates the register address followed by up to n-data bytes. In one frame all data bytes are written to the same register address. This enables fast FIFO buffer access. The Read/Write (R/W) bit is set to logic 0. Fig 22. First byte following the START procedure slave address 001aak591 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W MSB LSB PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 79 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.7 Register read access To read out data from a specific register address in the PN512, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I2C-bus rules • The second byte indicates the register address. No data bytes are added • The Read/Write bit is 0 After the write access, read access can start. The host sends the device address of the PN512. In response, the PN512 sends the content of the read access register. In one frame all data bytes can be read from the same register address. This enables fast FIFO buffer access or register polling. The Read/Write (R/W) bit is set to logic 1. Fig 23. Register read and write access 001aak592 S A 0 0 I2C-BUS SLAVE ADDRESS [A7:A0] JOINER REGISTER ADDRESS [A5:A0] write cycle 0 (W) A DATA [7:0] [0:n] [0:n] [0:n] A P S A 0 0 I2C-BUS SLAVE ADDRESS [A7:A0] JOINER REGISTER ADDRESS [A5:A0] read cycle optional, if the previous access was on the same register address 0 (W) A P P S S start condition P stop condition A acknowledge A not acknowledge W write cycle R read cycle A I2C-BUS SLAVE ADDRESS [A7:A0] sent by master sent by slave DATA [7:0] 1 (R) A DATA [7:0] A PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 80 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates of up to 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode (F/S mode) for bidirectional communication in a mixed-speed bus system. 10.4.9 High-speed transfer To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to I2C-bus operation. • The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger on the SDA and SCL inputs and different timing constants when compared to F/S mode • The output buffers of the device in HS mode incorporate slope control of the falling edges of the SDA and SCL signals with different fall times compared to F/S mode 10.4.10 Serial data transfer format in HS mode The HS mode serial data transfer format meets the Standard mode I2C-bus specification. HS mode can only start after all of the following conditions (all of which are in F/S mode): 1. START condition (S) 2. 8-bit master code (00001XXXb) 3. Not-acknowledge bit (A) When HS mode starts, the active master sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from the selected PN512. Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions (Sr). Fig 24. I2C-bus HS mode protocol switch F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode 001aak749 A A DATA A/A (n-bytes + A) S MASTER CODE Sr SLAVE ADDRESS R/W HS mode continues Sr SLAVE ADDRESS P PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 81 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 25. I2C-bus HS mode protocol frame msc618 8-bit master code 0000 1xxx A tH t1 S F/S mode HS mode If P then F/S mode If Sr (dotted lines) then HS mode 1 6 7 8 9 1 6 7 8 9 1 2 to 5 2 to 5 2 to 5 6 7 8 9 SDA high SCL high SDA high SCL high tH tFS Sr Sr P 7-bit SLA R/W A n + (8-bit data + A/A) = Master current source pull-up = Resistor pull-up PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 82 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 10.4.11 Switching between F/S mode and HS mode After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting. The following actions are taken: 1. Adapt the SDA and SCL input filters according to the spike suppression requirement in HS mode. 2. Adapt the slope control of the SDA output stages. It is possible for system configurations that do not have other I2C-bus devices involved in the communication to switch to HS mode permanently. This is implemented by setting Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code is not required to be sent. This is not defined in the specification and must only be used when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines must be avoided because of the reduced spike suppression. 10.4.12 PN512 at lower speed modes PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus system. The device stays in F/S mode and communicates at F/S mode speeds because a master code is not transmitted in this configuration. 11. 8-bit parallel interface The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola compatible modes. 11.1 Overview of supported host controller interfaces The PN512 supports direct interfacing to various -Controllers. The following table shows the parallel interface types supported by the PN512. Table 152. Supported interface types Supported interface types Bus Separated Address and Data Bus Multiplexed Address and Data Bus Separated Read and Write Strobes (INTEL compatible) control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7 Multiplexed Read and Write Strobe (Motorola compatible) control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0 … A3 [..A5*] AD0 … AD7 data D0 … D7 AD0 … AD7 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 83 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 11.2 Separated Read/Write strobe For timing requirements refer to Section 26.2 “8-bit parallel interface timing”. 11.3 Common Read/Write strobe For timing requirements refer to Section 26.2 “8-bit parallel interface timing” Fig 26. Connection to host controller with separated Read/Write strobes 001aan223 PN512 NCS A0...A3[A5*] D0...D7 A0 A1 A2 A3 A4* A5* address bus (A0...A3[A5*]) ALE NRD NWR ADDRESS DECODER data bus (D0...D7) high not data strobe (NRD) not write (NWR) address bus remark: *depending on the package type. multiplexed address/data AD0...AD7) PN512 NCS D0...D7 ALE NRD NWR ADDRESS DECODER low low high high high low address latch enable (ALE) not read strobe (NRD) not write (NWR) non multiplexed address Fig 27. Connection to host controller with common Read/Write strobes 001aan224 PN512 NCS A0...A3[A5*] D0...D7 A0 A1 A2 A3 A4* A5* address bus (A0...A3[A5*]) ALE NRD NWR ADDRESS DECODER Data bus (D0...D7) high not data strobe (NDS) read not write (RD/NWR) address bus remark: *depending on the package type. multiplexed address/data AD0...AD7) PN512 NCS D0...D7 ALE NRD NWR ADDRESS DECODER low low high high low low address strobe (AS) not data strobe (NDS) read not write (RD/NWR) non multiplexed address PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 84 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12. Analog interface and contactless UART 12.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In addition, it handles error detection such as parity and CRC, based on the various supported contactless communication protocols. Remark: The size and tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance. 12.2 TX driver The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering; see Section 15 on page 96. The signal on pins TX1 and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on page 40. The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning. The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds. [1] X = Do not care. Table 153. Register and bit settings controlling the signal on pin TX1 Bit Tx1RFEn Bit Force 100ASK Bit InvTx1RFOn Bit InvTx1RFOff Envelope Pin TX1 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is switched off 1 0 0 X[1] 0 RF pMod nMod 100 % ASK: pin TX1 pulled to logic 0, independent of the InvTx1RFOff bit 1 RF pCW nCW 0 1 X[1] 0 RF pMod nMod 1 RF pCW nCW 1 1 X[1] 0 0 pMod nMod 1 RF_n pCW nCW PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 85 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] X = Do not care. The following abbreviations have been used in Table 153 and Table 154: • RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 • RF_n: inverted 13.56 MHz clock • GSPMos: conductance, configuration of the PMOS array • GSNMos: conductance, configuration of the NMOS array • pCW: PMOS conductance value for continuous wave defined by the CWGsPReg register • pMod: PMOS conductance value for modulation defined by the ModGsPReg register • nCW: NMOS conductance value for continuous wave defined by the GsNReg register’s CWGsN[3:0] bits • nMod: NMOS conductance value for modulation defined by the GsNReg register’s ModGsN[3:0] bits • X = do not care. Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and GsNReg registers are used for both drivers. 12.3 RF level detector The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF collision avoidance). Furthermore the RF level detector can be used to wake up the PN512 and to generate an interrupt. Table 154. Register and bit settings controlling the signal on pin TX2 Bit Tx1RFEn Bit Force 100ASK Bit Tx2CW Bit InvTx2RFOn Bit InvTx2RFOff Envelope Pin TX2 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is switched off 1 0 0 0 X[1] 0 RF pMod nMod - 1 RF pCW nCW 1 X[1] 0 RF_n pMod nMod 1 RF_n pCW nCW 1 0 X[1] X[1] RF pCW nCW conductance always CW for the Tx2CW bit 1 X[1] X[1] RF_n pCW nCW 1 0 0 X[1] 0 0 pMod nMod 100 % ASK: pin TX2 pulled to logic 0 (independent of the InvTx2RFOn/In vTx2RFOff bits) 1 RF pCW nCW 1 X[1] 0 0 pMod nMod 1 RF_n pCW nCW 1 0 X[1] X[1] RF pCW nCW 1 X[1] X[1] RF_n pCW nCW PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 86 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel in register RFCfgReg. The sensitivity itself depends on the antenna configuration and tuning. Possible sensitivity levels at the RX pin are listed in the Table 154. To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp in register RFCfgReg to 1. Remark: During soft Power-down mode the RF level detector amplifier is automatically switched off to ensure that the power consumption is less than 10 A at 3 V. Remark: With typical antennas lower sensitivity levels can provoke misleading results because of intrinsic noise in the environment. Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings. 12.4 Data mode detector The Data mode detector gives the possibility to detect received signals according to the ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and convenient way for further data processing. The Data mode detector can only be activated by the AutoColl command. The mode detector resets, when no external RF field is detected by the RF level detector. The Data mode detector could be switched off during the AutoColl command by setting bit ModeDetOff in register ModeReg to 1. Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) V~Rx [Vpp] RFLevel ~2 1111 ~1.4 1110 ~0.99 1101 ~0.69 1100 ~0.49 1011 ~0.35 1010 ~0.24 1001 ~0.17 1000 ~0.12 0111 ~0.083 0110 ~0.058 0101 ~0.041 0100 ~0.029 0011 ~0.020 0010 ~0.014 0001 ~0.010 0000 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 87 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 28. Data mode detector 001aan225 HOST INTERFACES RECEIVER I/Q DEMODULATOR REGISTERS REGISTERSETTING FOR THE DETECTED MODE DATA MODE DETECTOR PN512 RX NFC @ 106 kbit/s NFC @ 212 kbit/s NFC @ 424 kbit/s PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 88 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.5 Serial data switch Two main blocks are implemented in the PN512. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above 424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional external circuit to generate transfer speeds above 424 kbit (including 106, 212 and 424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S2C interface in the card SAM mode to emulate a card functionality with the PN512 and a secure IC. A secure IC can be the SmartMX smart card controller IC. This topology allows the analog block of the PN512 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. Figure 29 shows the serial data switch for TX1 and TX2. 12.6 S2C interface support The S2C provides the possibility to directly connect a secure IC to the PN512 in order act as a contactless smart card IC via the PN512. The interfacing signals can be routed to the pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC provided by NXP Semiconductors. The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and SIGOUT pads. Figure 31 outlines possible ways of communications via the PN512 to the secure IC. Fig 29. Serial data switch for TX1 and TX2 001aak593 INTERNAL CODER INVERT IF InvMod = 1 DriverSel[1:0] 00 01 10 11 3-state to driver TX1 and TX2 0 = impedance = modulated 1 = impedance = CW 1 INVERT IF PolMFin = 0 MFIN envelope PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 89 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and performs the communication on the SIGOUT line. To enable the Secure Access module mode the clock has to be derived by the internal oscillator of the PN512, see bits SAMClockSel in register TestSel1Reg. Configured in Contactless Card mode the secure IC can act as contactless smart card IC via the PN512. In this mode the signal on the SIGOUT line is provided by the external RF field of the external reader/writer. To enable the Contactless Card mode the clock derived by the external RF field has to be used. The configuration of the S2C interface differs for the FeliCa and MIFARE scheme as outlined in the following chapters. Fig 30. Communication flows using the S2C interface 001aan226 CONTACTLESS UART SERIAL SIGNAL SWITCH FIFO AND STATE MACHINE SPI, I2C, SERIAL UART HOST CONTROLLER PN512 SECURE CORE IC SIGOUT SIGIN 2. contactless card mode 1. secure access module (SAM) mode PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 90 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.6.1 Signal shape for Felica S2C interface support The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or. To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first. The time delay for that digital filtering is in the range of one bit length. The demodulated signal changes only at a positive edge of the clock. The register TxSelReg controls the setting at SIGOUT. The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver. The modulation is done according to the register settings of the antenna drivers. The clock is switched to AUX1 or AUX2 (see AnalogSelAux). Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock output if a serial interface is used. The HIGH level at D0 is the same as PVDD. Note: The signal on the antenna is shown in principle only. In reality the waveform is sinusoidal. Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode Fig 32. Signal shape for SIGIN in SAM mode 001aan227 clock signal on SIGIN signal on antenna 001aan228 clock demodulated signal signal on SIGOUT PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 91 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode. The register TxSelReg controls the setting at SIGOUT. Note: The clock settings for the Secure Access mode and the Contactless Card mode differ, refer to the description of the bits SAMClockSel in register TestSel1Reg. The signal at SIGIN is a digital Manchester coded signal according to the requirements of the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure IC. Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode 001aan229 1 0 bit value RF signal on antenna signal on SIGOUT 0 1 0 0 1 001aan230 0 1 0 1 0 0 1 bit value signal on antenna signal on SIGIN PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 92 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.7 Hardware support for FeliCa and NFC polling 12.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot, or if required an interrupt is generated at the end of the last timeslot. 2. The receiver can be configured in a way to receive continuously. In this mode it can receive any number of packets. The receiver is ready to receive the next packet directly after the last packet has been received. This mode is active by setting the bit RxMultiple in register RxModeReg to 1 and has to be stopped by software. 3. The internal UART adds one byte to the end of every received packet, before it is transferred into the FIFO-buffer. This byte indicates if the received byte packet is correct (see register ErrReg). The first byte of each packet contains the length byte of the packet. 4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a length of 64 bytes. This means three packets can be stored in the FIFO at the same time. If more than three packets are expected, the host controller has to empty the FIFO, before the FIFO is filled completely. In case of a FIFO-overflow data is lost (See bit BufferOvfl in register ErrorReg). 12.7.2 Polling sequence functionality for target 1. The host controller has to configure the PN512 with the correct polling response parameters for the polling command. 2. To activate the automatic polling in Target mode, the AutoColl Command has to be activated. 3. The PN512 receives the polling command send out by an initiator and answers with the polling response. The timeslot is selected automatically (The timeslot itself is randomly generated, but in the range 0 to TSN, which is defined by the Polling command). The PN512 compares the system code, stored in byte 17 and 18 of the Config Command with the system code received by the polling command of an initiator. If the system code is equal, the PN512 answers according to the configured polling response. The system code FF (hex) acts as a wildcard for the system code bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex). If the system code does not match no answer is sent back by the PN512. If a valid command is received by the PN512, which is not a Polling command, no answer is sent back and the command AutoColl is stopped. The received packet is stored in the FIFO. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 93 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 12.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length. This register is six bit long. Each bit represents a length of four bytes. DataLenMax in register FelNFC2Reg defines the maximum length of the accepted package. This register is six bit long. Each bit represents a length of four bytes. If set to logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not transferred to the FIFO and receiving is kept active. Example 1: • DataLenMin = 4 – The length shall be greater or equal 16. • DataLenMax = 5 – The length shall be smaller than 20. Valid area: 16, 17, 18, 19 Example 2: • DataLenMin = 9 – The length shall be greater or equal 36. • DataLenMax = 0 – The length shall be smaller than 256. Valid area: 36 to 255 12.7.4 CRC coprocessor The following CRC coprocessor parameters can be configured: • The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting • The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1 • The CRCResultReg register indicates the result of the CRC calculation. This register is split into two 8-bit registers representing the higher and lower bytes. • The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB first. Table 156. CRC coprocessor parameters Parameter Value CRC register length 16-bit CRC CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the ModeReg register’s CRCPreset[1:0] bits PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 94 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 13. FIFO buffer An 8  64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream between the host and the PN512’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account. 13.1 Accessing the FIFO buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register. Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register. When the microcontroller starts a command, the PN512 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses. 13.2 Controlling the FIFO buffer The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer accessible allowing the FIFO buffer to be filled with another 64 bytes. 13.3 FIFO buffer status information The host can get the following FIFO buffer status information: • Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0] • FIFO buffer almost full warning: Status1Reg register’s HiAlert bit • FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit • FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit. The PN512 can generate an interrupt signal when: • ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register’s LoAlert bit changes to logic 1. • ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register’s HiAlert bit changes to logic 1. If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to Equation 3: HiAlert = 64 – FIFOLength  WaterLevel (3) PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 95 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4: (4) 14. Interrupt request system The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 14.1 Interrupt sources overview Table 157 shows the available interrupt bits, the corresponding source and the condition for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by the timer unit which is set when the timer decrements from 1 to 0. The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by CRCReady bit = 1. The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on page 101). The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. LoAlert = FIFOLength  WaterLevel Table 157. Interrupt sources Interrupt flag Interrupt source Trigger action TimerIRq timer unit the timer counts from 1 to 0 TxIRq transmitter a transmitted data stream ends CRCIRq CRC coprocessor all data from the FIFO buffer has been processed RxIRq receiver a received data stream ends IdleIRq ComIrqReg register command execution finishes HiAlertIRq FIFO buffer the FIFO buffer is almost full LoAlertIRq FIFO buffer the FIFO buffer is almost empty ErrIRq contactless UART an error is detected PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 96 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 15. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • Time-out counter • Watch-dog counter • Stop watch • Programmable one-shot • Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. A time-out during data reception does not influence the reception process automatically). Furthermore, several timer related bits are set and these bits can be used to generate an interrupt. Timer The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer consists of two stages: 1 prescaler and 1 counter. The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between 0 and 4095 in register TModeReg and TPrescalerReg. The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the register TReloadReg. The current value of the timer is indicated by the register TCounterValReg. If the counter reaches 0 an interrupt will be generated automatically indicated by setting the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on the configuration the timer will stop at 0 or restart with the value from register TReloadReg. The status of the timer is indicated by bit TRunning in register Status1Reg. The timer can be manually started by TStartNow in register ControlReg or manually stopped by TStopNow in register ControlReg. Furthermore the timer can be activated automatically by setting the bit TAuto in the register TModeReg to fulfill dedicated protocol requirements automatically. The time delay of a timer stage is the reload value +1. The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz Maximum time: TPrescaler = 4095,TReloadVal = 65535 => (2*4095 +2)*65536/13.56 MHz = 39.59 s Example: PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 97 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution To indicate 25 us it is required to count 339 clock cycles. This means the value for TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us. The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version 1.0, see Section 21 “Errata sheet” on page 109. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 98 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 16. Power reduction modes 16.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level. 16.2 Soft power-down mode Soft Power-down mode is entered immediately after the CommandReg register’s PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input buffers are not separated from the input pins and keep their functionality. The digital output pins do not change their state. During soft power-down, all register values, the FIFO buffer content and the configuration keep their current contents. After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited. Remark: If the internal oscillator is used, you must take into account that it is supplied by pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock cycles can be detected by the internal logic. It is recommended for the serial UART, to first send the value 55h to the PN512. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the PN512 answers to the last read command with the register content of address 0. This indicates that the PN512 is ready. 16.3 Transmitter power-down mode The Transmitter Power-down mode switches off the internal antenna drivers thereby, turning off the RF field. Transmitter power-down mode is entered by setting either the TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 99 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 17. Oscillator circuitry The clock applied to the PN512 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, special care must be taken with the clock duty cycle and clock jitter and the clock quality must be verified. 18. Reset and oscillator start-up time 18.1 Reset timing requirements The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns. 18.2 Oscillator start-up time If the PN512 has been set to a Power-down mode or is powered by a VDDX supply, the start-up time for the PN512 depends on the oscillator used and is shown in Figure 36. The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator start-up time is defined by the crystal. The time (td) is the internal delay time of the PN512 when the clock signal is stable before the PN512 can be addressed. The delay time is calculated by: (5) The time (tosc) is the sum of td and tstartup. Fig 35. Quartz crystal connection 001aan231 PN512 27.12 MHz OSCOUT OSCIN td 1024 27 s = -------------- = 37.74 s PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 100 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19. PN512 command set The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.1 General description The PN512 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see Table 158) to the CommandReg register. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 19.2 General behavior • Each command that needs a data bit stream (or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the Transceive command. Using this command, transmission is started with the BitFramingReg register’s StartSend bit. • Each command that needs a certain number of arguments, starts processing only when it has received the correct number of arguments from the FIFO buffer. • The FIFO buffer is not automatically cleared when commands start. This makes it possible to write command arguments and/or the data bytes to the FIFO buffer and then start the command. • Each command can be interrupted by the host writing a new command code to the CommandReg register, for example, the Idle command. Fig 36. Oscillator start-up time 001aak596 tstartup td tosc t device activation oscillator clock stable clock ready PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 101 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3 PN512 command overview 19.3.1 PN512 command descriptions 19.3.1.1 Idle Places the PN512 in Idle mode. The Idle command also terminates itself. 19.3.1.2 Config command To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for these transactions has to be stored internally. All the following data have to be written to the FIFO in this order: SENS_RES (2 bytes); in order byte 0, byte 1 NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h and the check byte is calculated automatically. SEL_RES (1 Byte) polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes system code) NFCID3 (1 byte) In total 25 bytes are transferred into an internal buffer. The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2 bytes and the one NFCID3 byte which are listed above. To read out this configuration the command Config with an empty FIFO-buffer has to be started. In this case the 25 bytes are transferred from the internal buffer to the FIFO. Table 158. Command overview Command Command code Action Idle 0000 no action, cancels current command execution Configure 0001 Configures the PN512 for FeliCa, MIFARE and NFCIP-1 communication Generate RandomID 0010 generates a 10-byte random ID number CalcCRC 0011 activates the CRC coprocessor or performs a self test Transmit 0100 transmits data from the FIFO buffer NoCmdChange 0111 no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit Receive 1000 activates the receiver circuits Transceive 1100 transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and MIFARE anticollision (Card Operation mode only) MFAuthent 1110 performs the MIFARE standard authentication as a reader SoftReset 1111 resets the PN512 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 102 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution The PN512 has to be configured after each power up, before using the automatic Anticollision/Polling function (AutoColl command). During a hard power down (reset pin) this configuration remains unchanged. This command terminates automatically when finished and the active command is idle. 19.3.1.3 Generate RandomID This command generates a 10-byte random number which is initially stored in the internal buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the PN512 returns to Idle mode. 19.3.1.4 CalcCRC The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped when the FIFO buffer is empty during the data stream. The next byte written to the FIFO buffer is added to the calculation. The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The value is loaded in to the CRC coprocessor when the command starts. This command must be terminated by writing a command to the CommandReg register, such as, the Idle command. If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self Test mode. Starting the CalcCRC command initiates a digital self test. The result of the self test is written to the FIFO buffer. 19.3.1.5 Transmit The FIFO buffer content is immediately transmitted after starting this command. Before transmitting the FIFO buffer content, all relevant registers must be set for data transmission. This command automatically terminates when the FIFO buffer is empty. It can be terminated by another command written to the CommandReg register. 19.3.1.6 NoCmdChange This command does not influence any running command in the CommandReg register. It can be used to manipulate any bit except the CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit. 19.3.1.7 Receive The PN512 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command. This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 103 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3.1.8 Transceive This command continuously repeats the transmission of data from the FIFO buffer and the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream. Each transmit process must be started by setting the BitFramingReg register’s StartSend bit to logic 1. This command must be cleared by writing any command to the CommandReg register. Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive command never leaves the receive state because this state cannot be cancelled automatically. 19.3.1.9 AutoColl This command automatically handles the MIFARE activation and the FeliCa polling in the Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0 for correct operation. During this command also the mode detector is active if not deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode detector detects a mode, all the mode dependent registers are set according to the received data. In case of no external RF field the command resets the internal state machine and returns to the initial state but it will not be terminated. When the command terminates the transceive command gets active. During protocol processing the IRQ bits are not supported. Only the last received frame will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the protocol. During ISO/IEC 14443A activation the enable bits are defined by the command AutoColl. The changes cannot be observed at the register TXModeReg and RXModeReg. After the Transceive command is active, the value of the register bit is relevant. The FIFO will also receive the two CRC check bytes of the last command even if they already checked and correct, if the state machine (Anticollision and Select routine) has to not been executed and 106 kbit is detected. During Felica activation the register bit is always relevant and is not overruled by the command settings. This command can be cleared by software by writing any other command to the CommandReg register, e.g. the idle command. Writing the same content again to the CommandReg register resets the state machine. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 104 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution NFCIP-1 106 kbps Passive Communication mode: The MIFARE anticollision is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit TargetActivated in the Status2Reg register is set to logic 1. NFCIP-1 212/424 kbps Passive Communication mode: The FeliCa polling command is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ. The bit TargetActivated in the Status2Reg register is set to logic 1. NFCIP-1 106/212/424 kbps Active Communication mode: This command is changing the automatically to the command Transceive. The FIFO contains the ATR REQ The bit TargetActivated in the Status2Reg register is set to logic 0. For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC is added to the FIFO. Fig 37. Autocoll Command NFCIP-1 106 kB aud ISO14443-3 NPCIP-1 > 106 kB aud FELICA IDLE MODEO MODE detection RXF raming MFHalted = 1 HALT AC nAC SELECT nSELECT HLTA AC polling, polling response next frame received next frame received REQA, WUPA READY ACTIVE WUPA SELECT SELECT READY* ACTIVE* TRANSCEIVE wait for transmit next frame received J N HLTA REQA, WUPA, AC, nAC, SELECT, nSELECT, error REQA, AC, nAC, SELECT, nSELECT, HLTA REQA, WUPA, nAC, nSELECT, HLTA, error REQA, WUPA, nAC, nSELECT, HLTA, error REQA, WUPA, AC, SELECT, nSELECT, error 00 10 AC aaa-001826 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 105 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution MIFARE (Card Operation mode): The MIFARE anticollision is finished and the command has automatically changed to transceive. The FIFO contains the first command after the Select. The bit TargetActivated in the Status2Reg register is set to logic 1. Felica (Card Operation mode): The FeliCa polling command is finished and the command has automatically changed to transceive. The FIFO contains the first command followed after the Poling by the FeliCa protocol. The bit TargetActivated in the Status2Reg register is set to logic 1. 19.3.1.10 MFAuthent This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the FIFO buffer before the command can be activated: • Authentication command code (60h, 61h) • Block address • Sector key byte 0 • Sector key byte 1 • Sector key byte 2 • Sector key byte 3 • Sector key byte 4 • Sector key byte 5 • Card serial number byte 0 • Card serial number byte 1 • Card serial number byte 2 • Card serial number byte 3 In total 12 bytes are written to the FIFO. Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set. This command automatically terminates when the MIFARE card is authenticated and the Status2Reg register’s MFCrypto1On bit is set to logic 1. This command does not terminate automatically if the card does not answer, so the timer must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the TimerIRq bit can be used as the termination criteria. During authentication processing, the RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of the MFAuthent command, either after processing the protocol or writing Idle to the CommandReg register. If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 106 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 19.3.1.11 SoftReset This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished. Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to 9.6 kBd. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 107 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 20. Testsignals 20.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. 4. Write 00h to the FIFO. 5. Start the Selftest with the CalcCRC Command. 6. The Selftest will be performed. 7. When the Selftest is finished, the FIFO contains the following bytes: Version 1.0 has a different Selftest answer, explained in Section 21. Correct answer for VersionReg equal to 82h: 00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh, 9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h, 49h, 7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h, 21h, A9h, 86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh, 95h, 3Bh, 2Fh 20.2 Testbus The testbus is implemented for production test purposes. The following configuration can be used to improve the design of a system using the PN512. The testbus allows to route internal signals to the digital interface. The testbus signals are selected by accessing TestBusSel in register TestSel2Reg. Table 159. Testsignal routing (TestSel2Reg = 07h) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal sdata scoll svalid sover RCV_reset RFon, filtered Envelope Table 160. Description of Testsignals Pins Testsignal Description D6 sdata shows the actual received data stream. D5 scoll shows if in the actual bit a collision has been detected (106 kbit only) D4 svalid shows if sdata and scoll are valid D3 sover shows that the receiver has detected a stop condition (ISO/IEC 14443A/ MIFARE mode only). D2 RCV_reset shows if the receiver is reset D1 RFon, filtered shows the value of the internal RF level detector D0 Envelope shows the output of the internal coder PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 108 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 20.3 Testsignals at pin AUX Table 161. Testsignal routing (TestSel2Reg = 0Dh) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf Table 162. Description of Testsignals Pins Testsignal Description D6 clkstable shows if the oscillator delivers a stable signal. D5 clk27/8 shows the output signal of the oscillator divided by 8 D4 clk27rf/8 shows the clk27rf signal divided by 8 D3 clkrf13/4 shows the clk13rf divided by 4. D2 clk27 shows the output signal of the oscillator D1 clk27rf shows the RF clock multiplied by 2. D0 clk13rf shows the RF clock of 13.56 MHz Table 163. Testsignal routing (TestSel2Reg = 19h) Pins D6 D5 D4 D3 D2 D1 D0 Testsignal - TRunning - - - - - Table 164. Description of Testsignals Pins Testsignal Description D6 - - D5 TRunning TRunning stops 1 clockcycle after TimerIRQ is raised D4 - - D3 - - D2 - - D1 - - D0 - - Table 165. Testsignals description SelAux Description for Aux1 / Aux2 0000 Tristate 0001 DAC: register TestDAC 1/2 0010 DAC: testsignal corr1 0011 DAC: testsignal corr2 0100 DAC: testsignal MinLevel 0101 DAC: ADC_I 0110 DAC: ADC_Q 0111 DAC: testsignal ADC_I combined with ADC_Q 1000 Testsignal for production test 1001 SAM clock 1010 High 1011 low 1100 TxActive PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 109 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Note: The DAC has a current output, it is recommended to use a 1 k pull-down resistance at pins AUX1/AUX2. 20.4 PRBS Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the transmission of the defined datastream the command send has to be activated. The preamble/Sync byte/start bit/parity bit are generated automatically depending on the selected mode. Note: All relevant register to transmit data have to be configured before entering PRBS mode according ITU-TO150. 21. Errata sheet This data sheet is describing the functionality for version 2.0 and the industrial version. This chapter lists all differences from version 1.0 to version 2.0: The value of the version in Section 9.2.4.8 is set to80h. The behaviour ‘RFU’ for the register is undefined. The answer to the Selftest (see Section 20.1) for version 1.0 (VersionReg equal to 80h): 00h, AAh, E3h, 29h, 0Ch, 10h, 29zhh, 6Bh, 76h, 8Dh, AFh, 4Bh, A2h, DAh, 76h, 99h C7h, 5Eh, 24h, 69h, D2h, BAh, FAh, BCh 3Eh, DAh, 96h, B5h, F5h, 94h, B0h, 3Ah 4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh 38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh 4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh 38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh FBh, F4h, 19h, 94h, 82h, 5Ah, 72h, 9Dh BAh, 0Dh, 1Fh, 17h, 56h, 22h, B9h, 08h Only the default setting for the prescaler (see Section 15 “Timer unit” on page 96): t = ((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula fTimer = 13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in Table 100 “Description of TModeReg bits” on page 57 and TPrescalerLo in Table 101 “TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b” on page 58. As there is no option for the prescaler available, also the TPrescalEven is not available Section 9.2.2.10 on page 45. This bit is set to ‘RFU’. 1101 RxActive 1110 Subcarrier detected 1111 TstBusBit Table 165. Testsignals description SelAux Description for Aux1 / Aux2 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 110 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Especially when using time slot protocols, it is needed that the error flag is copied into the status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4 on page 39) within version 1.0 the protocol error flag is not included in the status information for the frame. In addition the CRCOk is copied instead of the CRCErr. This can be a problem in frames without length information e.g. ISO/IEC 14443-B. The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits, as such the configuration within Section 9.2.2.15 “TypeBReg” on page 50 bit 4 for RxEOFReq does not exist. In addition the IC only has the possibility to select the minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section 9.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only setting minimum and maximum length according ISO/IEC 14443-B, see Section 9.2.2.15 “TypeBReg” on page 50, bit 4. 22. Application design-in information The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN512. The antenna tuning and RF part matching is described in the application note “NFC Transmission Module Antenna and RF Design Guide”. Fig 38. Typical circuit diagram AVDD TVDD RX VMID supply TX1 TVSS TX2 DVSS DVDD DVDD PVDD SVDD AVSS IRQ NRSTPD R1 R2 L0 C0 C0 C2 C1 CRX RQ C1 RQ C2 L0 Cvmid 001aan232 27.12 MHz OSCIN OSCOUT HOST CONTROLLER interface PN512 antenna Lant PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 111 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 23. Limiting values 24. Recommended operating conditions Table 166. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDDA analog supply voltage 0.5 +4.0 V VDDD digital supply voltage 0.5 +4.0 V VDD(PVDD) PVDD supply voltage 0.5 +4.0 V VDD(TVDD) TVDD supply voltage 0.5 +4.0 V VDD(SVDD) SVDD supply voltage 0.5 +4.0 V VI input voltage all input pins except pins SIGIN and RX VSS(PVSS)  0.5 VDD(PVDD) + 0.5 V pin MFIN VSS(PVSS)  0.5 VDD(SVDD) + 0.5 V Ptot total power dissipation per package; and VDDD in shortcut mode - 200 mW Tj junction temperature - 125 C VESD electrostatic discharge voltage HBM; 1500 , 100 pF; JESD22-A114-B - 2000 V MM; 0.75 H, 200 pF; JESD22-A114-A - 200 V Charged device model; JESD22-C101-A on all pins - 200 V on all pins except SVDD in TFBGA64 package - 500 V Industrial version: VESD electrostatic discharge voltage HBM; 1500 , 100 pF; JESD22-A114-B - 2000 V MM; 0.75 H, 200 pF; JESD22-A114-A - 200 V Charged device model; AEC-Q100-011 on all pins - 200 V on all pins except SVDD - 500 V Table 167. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VDDA analog supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V VDDD digital supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V VDD(TVDD) TVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [1][2] 2.5 - 3.6 V PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 112 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] Supply voltages below 3 V reduce the performance (the achievable operating distance). [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. 25. Thermal characteristics 26. Characteristics VDD(PVDD) PVDD supply voltage VDD(PVDD)  VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V [3] 1.6 - 3.6 V VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 - +85 C Industrial version: Tamb ambient temperature HVQFN32 40 - +90 C Table 167. Operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit Table 168. Thermal characteristics Symbol Parameter Conditions Package Typ Unit Rthj-a Thermal resistance from junction to ambient In still air with exposed pad soldered on a 4 layer Jedec PCB In still air HVQFN32 40 K/W HVQFN40 35 K/W TFBGA64 K/W Table 169. Characteristics Symbol Parameter Conditions Min Typ Max Unit Input characteristics Pins A0, A1 and NRSTPD ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD)- - V VIL LOW-level input voltage - - 0.3VDD(PVDD) V Pin SIGIN ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(SVDD)- - V VIL LOW-level input voltage - - 0.3VDD(SVDD) V Pin ALE ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD)- - V VIL LOW-level input voltage - - 0.3VDD(PVDD) V Pin RX[1] Vi input voltage 1 - VDDA +1 V Ci input capacitance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.5 V (DC) offset - 10 - pF PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 113 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Ri input resistance VDDA = 3 V; receiver active; VRX(p-p) = 1 V; 1.5 V (DC) offset - 350 -  Input voltage range; see Figure 39 Vi(p-p)(min) minimum peak-to-peak input voltage Manchester encoded; VDDA = 3 V - 100 - mV Vi(p-p)(max) maximum peak-to-peak input voltage Manchester encoded; VDDA = 3 V - 4 - V Input sensitivity; see Figure 39 Vmod modulation voltage minimum Manchester encoded; VDDA = 3 V; RxGain[2:0] = 111b (48 dB) - 5 - mV Pin OSCIN ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDDA - - V VIL LOW-level input voltage - - 0.3VDDA V Ci input capacitance VDDA = 2.8 V; DC = 0.65 V; AC = 1 V (p-p) - 2 - pF Input/output characteristics pins D1, D2, D3, D4, D5, D6 and D7 ILI input leakage current 1 - +1 A VIH HIGH-level input voltage 0.7VDD(PVDD)- - V VIL LOW-level input voltage - - 0.3VDD(PVDD) V VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)  0.4 - VDD(PVDD) V VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOH HIGH-level output current VDD(PVDD) = 3 V - - 4 mA IOL LOW-level output current VDD(PVDD) = 3 V - - 4 mA Output characteristics Pin SIGOUT VOH HIGH-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VDD(SVDD)  0.4 - VDD(SVDD) V VOL LOW-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDD(SVDD) = 3 V - - 4 mA IOH HIGH-level output current VDD(SVDD) = 3 V - - 4 mA Pin IRQ VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)  0.4 - VDD(PVDD) V VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDD(PVDD) = 3 V - - 4 mA IOH HIGH-level output current VDD(PVDD) = 3 V - - 4 mA Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 114 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Pins AUX1 and AUX2 VOH HIGH-level output voltage VDDD = 3 V; IO = 4 mA VDDD  0.4 - VDDD V VOL LOW-level output voltage VDDD = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) + 0.4 V IOL LOW-level output current VDDD= 3 V - - 4 mA IOH HIGH-level output current VDDD= 3 V - - 4 mA Pins TX1 and TX2 VOL LOW-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh - - 0.15 V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh - - 0.4 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh - - 0.24 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh - - 0.64 V VOH HIGH-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.15 - - V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.4 - - V VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.24 - - V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.64 - - V Industrial version: VOL LOW-level output voltage VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh - - 0.18 V VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh - - 0.44 V VOH HIGH-level output voltage VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.18 - - V VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 3Fh VDD(TVDD)  0.44 - - V Output resistance for TX1/TX2, Industrial Version: ROP,01H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 01h 123 180 261  Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 115 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution ROP,02H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 02h 61 90 131  ROP,04H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 04h 30 46 68  ROP,08H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 08h 15 23 35  ROP,10H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 10h 7.5 12 19  ROP,20H High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 20h 4.2 6 9  ROP,3FH High level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsP = 3Fh 2 3 5  RON,10H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 10h 30 46 68  RON,20H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 20h 15 23 35  RON,40H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 40h 7.5 12 19  RON,80H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = 80h 4.2 6 9  RON,F0H Low level output resistance TVDD = 3 V, VTX = TVDD - 100 mV, CWGsN = F0h 2 3 5  Current consumption Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [2]- - 5 A soft power-down; RF level detector on [2]- - 10 A IDD(PVDD) PVDD supply current pin PVDD [3]- - 40 mA IDD(TVDD) TVDD supply current pin TVDD; continuous wave [4][5][6]- 60 100 mA IDD(SVDD) SVDD supply current pin SVDD [7]- - 4 mA IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9 mA IDDA analog supply current pin AVDD; VDDA= 3 V, CommandReg register’s RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register’s RcvOff bit = 1 - 3 5 mA Industrial version: IDDD digital supply current pin DVDD; VDDD= 3 V - 6.5 9,5 mA Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 116 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution [1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD. [2] Ipd is the total current for all supplies. [3] IDD(PVDD) depends on the overall load at the digital pins. [4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [5] During typical circuit operation, the overall current is below 100 mA. [6] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz. [7] IDD(SVDD) depends on the load at pin MFOUT. Ipd power-down current VDDA= VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW [2]- - 15 A soft power-down; RF level detector on [2]- - 30 A Clock frequency fclk clock frequency - 27.12 - MHz clk clock duty cycle 40 50 60 % tjit jitter time RMS - - 10 ps Crystal oscillator VOH HIGH-level output voltage pin OSCOUT - 1.1 - V VOL LOW-level output voltage pin OSCOUT - 0.2 - V Ci input capacitance pin OSCOUT - 2 - pF pin OSCIN - 2 - pF Typical input requirements fxtal crystal frequency - 27.12 - MHz ESR equivalent series resistance - - 100  CL load capacitance - 10 - pF Pxtal crystal power dissipation - 50 100 W Table 169. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 117 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 26.1 Timing characteristics Fig 39. Pin RX input voltage range 001aak012 VMID 0 V Vmod Vi(p-p)(max) Vi(p-p)(min) 13.56 MHz carrier Table 170. SPI timing characteristics Symbol Parameter Conditions Min Typ Max Unit tWL pulse width LOW line SCK 50 - - ns tWH pulse width HIGH line SCK 50 - - ns th(SCKH-D) SCK HIGH to data input hold time SCK to changing MOSI 25 - - ns tsu(D-SCKH) data input to SCK HIGH set-up time changing MOSI to SCK 25 - - ns th(SCKL-Q) SCK LOW to data output hold time SCK to changing MISO - - 25 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns Table 171. I2C-bus timing in Fast mode Symbol Parameter Conditions Fast mode High-speed mode Unit Min Max Min Max fSCL SCL clock frequency 0 400 0 3400 kHz tHD;STA hold time (repeated) START condition after this period, the first clock pulse is generated 600 - 160 - ns tSU;STA set-up time for a repeated START condition 600 - 160 - ns tSU;STO set-up time for STOP condition 600 - 160 - ns tLOW LOW period of the SCL clock 1300 - 160 - ns tHIGH HIGH period of the SCL clock 600 - 60 - ns tHD;DAT data hold time 0 900 0 70 ns PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 118 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution tSU;DAT data set-up time 100 - 10 - ns tr rise time SCL signal 20 300 10 40 ns tf fall time SCL signal 20 300 10 40 ns tr rise time SDA and SCL signals 20 300 10 80 ns tf fall time SDA and SCL signals 20 300 10 80 ns tBUF bus free time between a STOP and START condition 1.3 - 1.3 - s Remark: The signal NSS must be LOW to be able to send several bytes in one data stream. To send more than one data stream NSS must be set HIGH between the data streams. Fig 40. Timing diagram for SPI Fig 41. Timing for Fast and Standard mode devices on the I2C-bus Table 171. I2C-bus timing in Fast mode …continued Symbol Parameter Conditions Fast mode High-speed mode Unit Min Max Min Max 001aaj634 tSCKL tSCKH tSCKL tDXSH tSHDX tDXSH tSLDX tSLNH MOSI SCK MISO MSB MSB LSB LSB NSS 001aaj635 SDA tf SCL tLOW tf tSP tr tHD;STA tHD;DAT tHD;STA tr tHIGH tSU;DAT S Sr P S tSU;STA tSU;STO tBUF PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 119 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 26.2 8-bit parallel interface timing 26.2.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Example: tAVLL = time for address valid to ALE low 26.2.2 AC operating specification 26.2.2.1 Bus timing for separated Read/Write strobe Table 172. AC symbols Designation Signal Designation Logic Level A address H HIGH D data L LOW W NWR or nWait Z high impedance R NRD or R/NW or nWrite X any level or data L ALE or AS V any valid signal or data C NCS N NSS S NDS or nDStrb and nAStrb, SCK Table 173. Timing specification for separated Read/Write strobe Symbol Parameter Min Max Unit tLHLL ALE pulse width 10 - ns tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 5 - ns tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 5 - ns tLLWL ALE low to NWR, NRD low 10 - ns tCLWL NCS low to NRD, NWR low 0 - ns tWHCH NRD, NWR high to NCS high 0 - ns tRLDV NRD low to DATA valid - 35 ns tRHDZ NRD high to DATA high impedance - 10 ns tDVWH DATA valid to NWR high 5 - ns tWHDX DATA hold after NWR high (Data Hold Time) 5 - ns tWLWH NRD, NWR pulse width 40 - ns tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 - ns tWHAX Separated Address Bus valid after NWR high (Hold Time) 5 - ns tWHWL period between sequenced read/write accesses 40 - ns PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 120 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A3 have to be connected as described in chapter Automatic host controller Interface Type Detection. 26.2.2.2 Bus timing for common Read/Write strobe Fig 42. Timing diagram for separated Read/Write strobe 001aan233 tLHLL tCLWL tLLWL tWHWL tWLWH tWHWL tWHDX tRHDZ tWLDV tRLDV tWHCH tWHAX tAVLL tLLAX tAVWL ALE NCS NWR NRD D0...D7 D0...D7 A0...A3 multiplexed addressbus A0...A3 SEPARATED ADDRESSBUS A0...A3 Table 174. Timing specification for common Read/Write strobe Symbol Parameter Min Max Unit tLHLL AS pulse width 10 - ns tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 5 - ns tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 5 - ns tLLSL AS low to NDS low 10 - ns tCLSL NCS low to NDS low 0 - ns tSHCH NDS high to NCS high 0 - ns tSLDV,R NDS low to DATA valid (for read cycle) - 35 ns tSHDZ NDS low to DATA high impedance (read cycle) - 10 ns tDVSH DATA valid to NDS high (for write cycle) 5 - ns tSHDX DATA hold after NDS high (write cycle, Hold Time) 5 - ns tSHRX R/NW hold after NDS high 5 - ns tSLSH NDS pulse width 40 - ns tAVSL Separated Address Bus valid to NDS low (Hold Time) 30 - ns tSHAX Separated Address Bus valid after NDS high (Set Up Time) 5 - ns PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 121 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines A0 to A3 have to be connected as described in Automatic -Controller Interface Type Detection. Fig 43. Timing diagram for common Read/Write strobe SEPARATED ADDRESSBUS A0...A3 multiplexed addressbus A0...A3 ALE tLHLL tCLSL R/NW NDS D0...D7 D0...D7 A0...A3 NCS tSHCH tRVSL tSHRX tLLSL tSLSH tSHSL tAVLL tLLAX tSLDV, R tSLDV, W tSHDX tSHDZ tSHAX tAVSL tSHSL 001aan234 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 122 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 27. Package information The PN512 can be delivered in 3 different packages. Table 175. Package information Package Remarks HVQFN32 8-bit parallel interface not supported HVQFN40 Supports the 8-bit parallel interface TFBGA64 Ball grid array facilitating development of an PCI compliant device PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 123 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 28. Package outline Fig 44. Package outline package version (HVQFN32) 1 0.5 UNIT A1 b Eh e y 0.2 c OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 5.1 4.9 Dh 3.25 2.95 y1 5.1 4.9 3.25 2.95 e1 3.5 e2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT617-1 - - - MO-220 - - - 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT617-1 HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A(1) max. A A1 c detail X e y1 C y L Eh Dh e e1 b 9 16 32 25 24 17 8 1 X D E C B A e2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e C A C v M B w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 124 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 45. Package outline package version (HVQFN40) Outline References version European projection Issue date IEC JEDEC JEITA SOT618-1 MO-220 sot618-1_po 02-10-22 13-11-05 Unit mm max nom min 1.00 0.05 0.2 6.1 4.25 6.1 0.4 A(1) Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm SOT618-1 A1 b 0.30 c D(1) Dh E(1) Eh 4.10 e e1 e2 L v w 0.05 y 0.05 y1 0.1 0.85 0.02 0.21 6.0 4.10 6.0 0.80 0.00 0.18 5.9 3.95 5.9 3.95 0.3 4.25 0.5 4.5 4.5 0.5 0.1 e e 1/2 e 1/2 e y terminal 1 index area A A1 c L Eh Dh b 11 20 40 31 30 10 21 1 D E terminal 1 index area 0 2.5 5 mm scale e1 C A C v B w y1 C C e2 X detail X B A PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 125 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Fig 46. Package outline package version (TFBGA64) Outline References version European projection Issue date IEC JEDEC JEITA SOT1336-1 - - - sot1336-1_po 12-06-19 12-08-28 Unit mm max nom min 1.15 0.35 0.45 5.6 5.6 4.55 0.15 0.1 A Dimensions (mm are the original dimensions) TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls A1 A2 0.80 1.00 0.30 0.70 0.40 5.5 5.5 0.65 b D E e e1 4.55 0.90 0.25 0.65 0.35 5.4 5.4 e2 v w 0.08 y y1 0.1 SOT1336-1 C y1 C y 0 5 mm scale X A A2 A1 detail X ball A1 index area ball A1 index area A E D B e2 e A B C D E F G H 1 2 3 4 5 6 7 8 e1 e Ø v C A B Ø w C b 1/2 e 1/2 e PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 126 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 29. Abbreviations 30. Glossary Modulation index — Defined as the voltage ratio (Vmax  Vmin) / (Vmax + Vmin). Load modulation index — Defined as the voltage ratio for the card (Vmax  Vmin) / (Vmax + Vmin) measured at the card’s coil. Initiator — Generates RF field at 13.56 MHz and starts the NFCIP-1 communication. Target — Responds to command either using load modulation scheme (RF field generated by Initiator) or using modulation of self generated RF field (no RF field generated by initiator). 31. References [1] Application note — NFC Transmission Module Antenna and RF Design Guide Table 176. Abbreviations Acronym Description ADC Analog-to-Digital Converter ASK Amplitude Shift keying BPSK Binary Phase Shift Keying CRC Cyclic Redundancy Check CW Continuous Wave DAC Digital-to-Analog Converter EOF End of frame HBM Human Body Model I2C Inter-integrated Circuit LSB Least Significant Bit MISO Master In Slave Out MM Machine Model MOSI Master Out Slave In MSB Most Significant Bit NSS Not Slave Select PCB Printed-Circuit Board PLL Phase-Locked Loop PRBS Pseudo-Random Bit Sequence RX Receiver SOF Start Of Frame SPI Serial Peripheral Interface TX Transmitter UART Universal Asynchronous Receiver Transmitter PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 127 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 32. Revision history Table 177. Revision history Document ID Release date Data sheet status Change notice Supersedes PN512 v.4.5 20131217 Product data sheet - PN512 v.4.4 Modifications: • Typo corrected PN512 v.4.4 20130730 Product data sheet - PN512 v.4.3 Modifications: • Value added in Table 166 “Limiting values” • Change of descriptive title PN512 v.4.3 20130507 Product data sheet - PN512 v.4.2 Modifications: • New type PN5120A0ET/C2 added • Table 72 “Description of MifNFCReg bits”: description of TxWait updated • Table 153 “Register and bit settings controlling the signal on pin TX1” and Table 153 “Register and bit settings controlling the signal on pin TX1”: updated • Table 166 “Limiting values”: VESD values added PN512 v.4.2 20120828 Product data sheet - PN512 v.4.1 Modifications: • Table 123 “AutoTestReg register (address 36h); reset value: 40h, 01000000b”: description of bits 4 and 5 corrected PN512 v.4.1 20120821 Product data sheet - PN512 v.4.0 Modifications: • Table 124 “Description of bits”: description of bits 4 and 5 corrected PN512 v.4.0 20120712 Product data sheet - PN512 v.3.9 Modifications: • Section 33.4 “Licenses”: updated PN512 v.3.9 20120201 Product data sheet - PN512 v.3.8 Modifications: • Adding information on the different version in General description. • Adding Section 21 “Errata sheet” on page 109 for explanation of differences between 1.0 and 2.0. • Adding ordering information for version 1.0 and industrial version in Table 2 “Ordering information” on page 5 • Adding the limitations and characteristics for the industrial version, see Table 1 “Quick reference data” on page 4, Table 166 “Limiting values” on page 111, Table 1 “Quick reference data” on page 4 • Referring to the Section 21 “Errata sheet” on page 109 within the following sections: Section 9.2.2.4 “RxModeReg” on page 39, Section 9.2.2.10 “DemodReg” on page 45, Section 9.2.2.15 “TypeBReg” on page 50, Section 9.2.3.10 “TMode Register, TPrescaler Register” on page 57, Section 9.2.4.7 “AutoTestReg” on page 64, Section 9.2.4.8 “VersionReg” on page 64, Section 9.1.1 “Register bit behavior” on page 23, Section 15 “Timer unit” on page 96, Section 20 “Testsignals” on page 107; • Update of command ‘Mem’ to ‘Configure’ and ‘RFU’ to ‘Autocoll’ in Table 158 “Command overview” on page 101. • Change of ‘Mem’ to ‘Configure’ in ‘Mem’ in Section 19.3.1.2 “Config command” on page 101 • Adding Autocoll in Section 19.3.1.9 “AutoColl” on page 103 PN512 v.3.8 20111025 Product data sheet - PN512 v.3.7 Modifications: • Table 168 “Characteristics”: unit of Pxtal corrected 111310 June 2005 Objective data sheet - Modifications: • Initial version PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 128 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 33. Legal information 33.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 33.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 33.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 129 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 33.4 Licenses 33.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. MIFARE — is a trademark of NXP B.V. 34. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron Technology Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 130 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 35. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5 Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . .10 Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . 11 Table 5. Pin description TFBGA64 . . . . . . . . . . . . . . . . .12 Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer . . . . .14 Table 7. Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 8. FeliCa framing and coding . . . . . . . . . . . . . . . .16 Table 9. Start value for the CRC Polynomial: (00h), (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 10. Communication overview for Active communication mode . . . . . . . . . . . . . . . . . . . .18 Table 11. Communication overview for Passive communication mode . . . . . . . . . . . . . . . . . . . .19 Table 12. Framing and coding overview. . . . . . . . . . . . . .20 Table 13. MIFARE Card operation mode . . . . . . . . . . . . .20 Table 14. FeliCa Card operation mode . . . . . . . . . . . . . .21 Table 15. PN512 registers overview . . . . . . . . . . . . . . . .21 Table 16. Behavior of register bits and its designation. . .23 Table 17. PageReg register (address 00h); reset value: 00h, 0000000b . . . . . . . . . . . . . . . . . . . . . . . . .24 Table 18. Description of PageReg bits . . . . . . . . . . . . . . .24 Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .24 Table 20. Description of CommandReg bits. . . . . . . . . . .24 Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . .25 Table 22. Description of CommIEnReg bits . . . . . . . . . . .25 Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .26 Table 24. Description of DivIEnReg bits . . . . . . . . . . . . . .26 Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b . . . . . . . . . . . . . . . . . . .27 Table 26. Description of CommIRqReg bits . . . . . . . . . . .27 Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb . . . . . . . . . . . . . . . . . .28 Table 28. Description of DivIRqReg bits . . . . . . . . . . . . .28 Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .29 Table 30. Description of ErrorReg bits . . . . . . . . . . . . . . .29 Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb . . . . . . . . . . . . . . . . . .30 Table 32. Description of Status1Reg bits . . . . . . . . . . . . .30 Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .31 Table 34. Description of Status2Reg bits . . . . . . . . . . . . .31 Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . .32 Table 36. Description of FIFODataReg bits . . . . . . . . . . .32 Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .32 Table 38. Description of FIFOLevelReg bits. . . . . . . . . . .32 Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .33 Table 40. Description of WaterLevelReg bits. . . . . . . . . . 33 Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 33 Table 42. Description of ControlReg bits . . . . . . . . . . . . 33 Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 34 Table 44. Description of BitFramingReg bits . . . . . . . . . . 34 Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb . . . . . . . . . . . . . . . . . 35 Table 46. Description of CollReg bits. . . . . . . . . . . . . . . . 35 Table 47. PageReg register (address 10h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 36 Table 48. Description of PageReg bits . . . . . . . . . . . . . . 36 Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 50. Description of ModeReg bits . . . . . . . . . . . . . . 37 Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 38 Table 52. Description of TxModeReg bits . . . . . . . . . . . . 38 Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 39 Table 54. Description of RxModeReg bits . . . . . . . . . . . . 39 Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 40 Table 56. Description of TxControlReg bits . . . . . . . . . . . 40 Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 41 Table 58. Description of TxAutoReg bits . . . . . . . . . . . . . 41 Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b. . . . . . . . . . . . . . . . . . . . . . . . 42 Table 60. Description of TxSelReg bits . . . . . . . . . . . . . . 42 Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b. . . . . . . . . . . . . . . . . . . . . . . . 44 Table 62. Description of RxSelReg bits . . . . . . . . . . . . . . 44 Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b . . . . . . . . . . . . . . 44 Table 64. Description of RxThresholdReg bits . . . . . . . . 44 Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b . . . . . . . . . . . . . . . . . . 45 Table 66. Description of DemodReg bits . . . . . . . . . . . . . 45 Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 46 Table 68. Description of FelNFC1Reg bits . . . . . . . . . . . 46 Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 47 Table 70. Description of FelNFC2Reg bits . . . . . . . . . . . 47 Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b. . . . . . . . . . . . . . . . . . . 48 Table 72. Description of MifNFCReg bits. . . . . . . . . . . . . 48 Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b . . . . . . . . . . . . . . 49 Table 74. Description of ManualRCVReg bits . . . . . . . . . 49 Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 50 Table 76. Description of TypeBReg bits. . . . . . . . . . . . . . 50 Table 77. SerialSpeedReg register (address 1Fh); PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 131 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution reset value: EBh, 11101011b . . . . . . . . . . . . . .51 Table 78. Description of SerialSpeedReg bits . . . . . . . . .51 Table 79. PageReg register (address 20h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .52 Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52 Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 82. Description of CRCResultReg bits . . . . . . . . . .52 Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52 Table 84. Description of CRCResultReg bits . . . . . . . . . .52 Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .53 Table 86. Description of GsNOffReg bits . . . . . . . . . . . . .53 Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b . . . . . . . . . . . . . . . . . . .54 Table 88. Description of ModWidthReg bits . . . . . . . . . . .54 Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .54 Table 90. Description of TxBitPhaseReg bits . . . . . . . . . .54 Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b . . . . . . . . . . . . . . . . . . .55 Table 92. Description of RFCfgReg bits . . . . . . . . . . . . .55 Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .56 Table 94. Description of GsNOnReg bits . . . . . . . . . . . . .56 Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .56 Table 96. Description of CWGsPReg bits. . . . . . . . . . . . .56 Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .57 Table 98. Description of ModGsPReg bits . . . . . . . . . . . .57 Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .57 Table 100. Description of TModeReg bits . . . . . . . . . . . . .57 Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .58 Table 102. Description of TPrescalerReg bits . . . . . . . . . .58 Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b . . . . . . . . .59 Table 104. Description of the higher TReloadReg bits . . .59 Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b . . . . . . . . .59 Table 106. Description of lower TReloadReg bits . . . . . . .59 Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh, XXXXXXXXb . . . . . . .60 Table 108. Description of the higher TCounterValReg bits 60 Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .60 Table 110. Description of lower TCounterValReg bits . . . .60 Table 111. PageReg register (address 30h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .60 Table 112. Description of PageReg bits. . . . . . . . . . . . . . .61 Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62 Table 114. Description of TestSel1Reg bits . . . . . . . . . . . .62 Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62 Table 116. Description of TestSel2Reg bits. . . . . . . . . . . . 62 Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 63 Table 118. Description of TestPinEnReg bits . . . . . . . . . . 63 Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 63 Table 120. Description of TestPinValueReg bits . . . . . . . . 63 Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 64 Table 122. Description of TestBusReg bits . . . . . . . . . . . . 64 Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b . . . . . . . . . . . . . . . . . . 64 Table 124. Description of bits . . . . . . . . . . . . . . . . . . . . . . 64 Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 65 Table 126. Description of VersionReg bits . . . . . . . . . . . . 65 Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 66 Table 128. Description of AnalogTestReg bits . . . . . . . . . 66 Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67 Table 130. Description of TestDAC1Reg bits . . . . . . . . . . 67 Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67 Table 132. Description ofTestDAC2Reg bits. . . . . . . . . . . 67 Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 67 Table 134. Description of TestADCReg bits . . . . . . . . . . . 67 Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 136. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 68 Table 138. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 140. Description of RFTReg bits . . . . . . . . . . . . . . . 68 Table 141. Connection protocol for detecting different interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 142. Connection scheme for detecting the different interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 70 Table 144. MOSI and MISO byte order . . . . . . . . . . . . . . 71 Table 145. Address byte 0 register; address MOSI . . . . . 71 Table 146. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 72 Table 147. Selectable UART transfer speeds . . . . . . . . . 72 Table 148. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 149. Read data byte order . . . . . . . . . . . . . . . . . . . 73 Table 150. Write data byte order . . . . . . . . . . . . . . . . . . . 73 Table 151. Address byte 0 register; address MOSI . . . . . 75 Table 152. Supported interface types . . . . . . . . . . . . . . . . 82 Table 153. Register and bit settings controlling the signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . 84 Table 154. Register and bit settings controlling the signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . 85 Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated) . . . 86 Table 156. CRC coprocessor parameters . . . . . . . . . . . . 93 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 132 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .95 Table 158. Command overview . . . . . . . . . . . . . . . . . . .101 Table 159. Testsignal routing (TestSel2Reg = 07h) . . . . .107 Table 160. Description of Testsignals . . . . . . . . . . . . . . .107 Table 161. Testsignal routing (TestSel2Reg = 0Dh) . . . .108 Table 162. Description of Testsignals . . . . . . . . . . . . . . .108 Table 163. Testsignal routing (TestSel2Reg = 19h) . . . . .108 Table 164. Description of Testsignals . . . . . . . . . . . . . . .108 Table 165. Testsignals description. . . . . . . . . . . . . . . . . .108 Table 166. Limiting values . . . . . . . . . . . . . . . . . . . . . . . 111 Table 167. Operating conditions . . . . . . . . . . . . . . . . . . . 111 Table 168. Thermal characteristics . . . . . . . . . . . . . . . . . 112 Table 169. Characteristics . . . . . . . . . . . . . . . . . . . . . . . 112 Table 170. SPI timing characteristics . . . . . . . . . . . . . . . 117 Table 171. I2C-bus timing in Fast mode . . . . . . . . . . . . . 117 Table 172. AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 173. Timing specification for separated Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . 119 Table 174. Timing specification for common Read/Write strobe. . . . . . . . . . . . . . . . . . . . . .120 Table 175. Package information . . . . . . . . . . . . . . . . . . .122 Table 176. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .126 Table 177. Revision history . . . . . . . . . . . . . . . . . . . . . . .127 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 133 of 136 NXP Semiconductors PN512 Full NFC Forum compliant solution 36. Figures Fig 1. Simplified block diagram of the PN512 . . . . . . . . .6 Fig 2. Detailed block diagram of the PN512 . . . . . . . . . .7 Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .8 Fig 4. Pinning configuration HVQFN40 (SOT618-1) . . . .8 Fig 5. Pin configuration TFBGA64 (SOT1336-1) . . . . . . .9 Fig 6. PN512 Read/Write mode. . . . . . . . . . . . . . . . . . .14 Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram. . . . . . . . . . . . . . . . . . . .14 Fig 8. Data coding and framing according to ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . .15 Fig 9. FeliCa reader/writer communication diagram . . .16 Fig 10. NFCIP-1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . .17 Fig 11. Active communication mode . . . . . . . . . . . . . . . .18 Fig 12. Passive communication mode . . . . . . . . . . . . . . .19 Fig 13. SPI connection to host. . . . . . . . . . . . . . . . . . . . .70 Fig 14. UART connection to microcontrollers . . . . . . . . .71 Fig 15. UART read data timing diagram . . . . . . . . . . . . .73 Fig 16. UART write data timing diagram . . . . . . . . . . . . .74 Fig 17. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .75 Fig 18. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .76 Fig 19. START and STOP conditions . . . . . . . . . . . . . . .76 Fig 20. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .77 Fig 21. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .77 Fig 22. First byte following the START procedure . . . . . .78 Fig 23. Register read and write access . . . . . . . . . . . . . .79 Fig 24. I2C-bus HS mode protocol switch . . . . . . . . . . . .80 Fig 25. I2C-bus HS mode protocol frame. . . . . . . . . . . . .81 Fig 26. Connection to host controller with separated Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83 Fig 27. Connection to host controller with common Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83 Fig 28. Data mode detector . . . . . . . . . . . . . . . . . . . . . . .87 Fig 29. Serial data switch for TX1 and TX2 . . . . . . . . . . .88 Fig 30. Communication flows using the S2C interface. . .89 Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Fig 32. Signal shape for SIGIN in SAM mode . . . . . . . . .90 Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Fig 35. Quartz crystal connection . . . . . . . . . . . . . . . . . .99 Fig 36. Oscillator start-up time . . . . . . . . . . . . . . . . . . . .100 Fig 37. Autocoll Command . . . . . . . . . . . . . . . . . . . . . .104 Fig 38. Typical circuit diagram . . . . . . . . . . . . . . . . . . . . 110 Fig 39. Pin RX input voltage range . . . . . . . . . . . . . . . . 116 Fig 40. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . 118 Fig 41. Timing for Fast and Standard mode devices on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Fig 42. Timing diagram for separated Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Fig 43. Timing diagram for common Read/Write strobe 121 Fig 44. Package outline package version (HVQFN32) .123 Fig 45. Package outline package version (HVQFN40) .124 Fig 46. Package outline package version (TFBGA64). .125 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 134 of 136 continued >> NXP Semiconductors PN512 Full NFC Forum compliant solution 37. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Different available versions. . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information. . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 14 8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . 14 8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . 15 8.3 FeliCa reader/writer functionality . . . . . . . . . . 16 8.3.1 FeliCa framing and coding . . . . . . . . . . . . . . . 16 8.4 NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4.1 Active communication mode . . . . . . . . . . . . . 18 8.4.2 Passive communication mode . . . . . . . . . . . . 19 8.4.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 20 8.4.4 NFCIP-1 protocol support. . . . . . . . . . . . . . . . 20 8.4.5 MIFARE Card operation mode . . . . . . . . . . . . 20 8.4.6 FeliCa Card operation mode . . . . . . . . . . . . . 21 9 PN512 register SET . . . . . . . . . . . . . . . . . . . . . 21 9.1 PN512 registers overview. . . . . . . . . . . . . . . . 21 9.1.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . 23 9.2 Register description . . . . . . . . . . . . . . . . . . . . 24 9.2.1 Page 0: Command and status . . . . . . . . . . . . 24 9.2.1.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1.2 CommandReg . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2.1.3 CommIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2.1.4 DivIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.2.1.5 CommIRqReg. . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.1.6 DivIRqReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.1.7 ErrorReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.1.8 Status1Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.1.9 Status2Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.1.10 FIFODataReg . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1.11 FIFOLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2.1.12 WaterLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.1.13 ControlReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2.1.14 BitFramingReg . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2.1.15 CollReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2.2 Page 1: Communication . . . . . . . . . . . . . . . . . 36 9.2.2.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.2.2 ModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2.2.3 TxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2.2.4 RxModeReg. . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2.2.5 TxControlReg. . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2.2.6 TxAutoReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2.7 TxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.2.8 RxSelReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.2.9 RxThresholdReg . . . . . . . . . . . . . . . . . . . . . . 44 9.2.2.10 DemodReg. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2.2.11 FelNFC1Reg . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.2.12 FelNFC2Reg . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2.2.13 MifNFCReg . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2.2.14 ManualRCVReg. . . . . . . . . . . . . . . . . . . . . . . 49 9.2.2.15 TypeBReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.2.2.16 SerialSpeedReg. . . . . . . . . . . . . . . . . . . . . . . 50 9.2.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 52 9.2.3.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.3.2 CRCResultReg . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.3.3 GsNOffReg . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2.3.4 ModWidthReg . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3.5 TxBitPhaseReg . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3.6 RFCfgReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.3.7 GsNOnReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.8 CWGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.9 ModGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.3.10 TMode Register, TPrescaler Register . . . . . . 57 9.2.3.11 TReloadReg. . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2.3.12 TCounterValReg . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.2 TestSel1Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.3 TestSel2Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.4.4 TestPinEnReg . . . . . . . . . . . . . . . . . . . . . . . . 63 9.2.4.5 TestPinValueReg . . . . . . . . . . . . . . . . . . . . . . 63 9.2.4.6 TestBusReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.7 AutoTestReg . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.8 VersionReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.2.4.9 AnalogTestReg. . . . . . . . . . . . . . . . . . . . . . . . 66 9.2.4.10 TestDAC1Reg . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.11 TestDAC2Reg . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.12 TestADCReg . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.2.4.13 RFTReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . 68 10.1 Automatic microcontroller interface detection 68 10.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 70 10.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.2 SPI write data. . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 71 10.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . 71 10.3.1 Connection to a host . . . . . . . . . . . . . . . . . . . 71 PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.5 — 17 December 2013 111345 135 of 136 continued >> NXP Semiconductors PN512 Full NFC Forum compliant solution 10.3.2 Selectable UART transfer speeds . . . . . . . . . 71 10.3.3 UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 75 10.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4.2 START and STOP conditions . . . . . . . . . . . . . 76 10.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 78 10.4.6 Register write access . . . . . . . . . . . . . . . . . . . 78 10.4.7 Register read access . . . . . . . . . . . . . . . . . . . 79 10.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 80 10.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 80 10.4.10 Serial data transfer format in HS mode . . . . . 80 10.4.11 Switching between F/S mode and HS mode . 82 10.4.12 PN512 at lower speed modes . . . . . . . . . . . . 82 11 8-bit parallel interface . . . . . . . . . . . . . . . . . . . 82 11.1 Overview of supported host controller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2 Separated Read/Write strobe . . . . . . . . . . . . . 83 11.3 Common Read/Write strobe . . . . . . . . . . . . . . 83 12 Analog interface and contactless UART . . . . 84 12.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.2 TX driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3 RF level detector . . . . . . . . . . . . . . . . . . . . . . 85 12.4 Data mode detector . . . . . . . . . . . . . . . . . . . . 86 12.5 Serial data switch . . . . . . . . . . . . . . . . . . . . . . 88 12.6 S2C interface support . . . . . . . . . . . . . . . . . . . 88 12.6.1 Signal shape for Felica S2C interface support 90 12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support . . . . . . . . . . . . . . . . . . . 91 12.7 Hardware support for FeliCa and NFC polling 92 12.7.1 Polling sequence functionality for initiator. . . . 92 12.7.2 Polling sequence functionality for target . . . . . 92 12.7.3 Additional hardware support for FeliCa and NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12.7.4 CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 93 13 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 13.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 94 13.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 94 13.3 FIFO buffer status information . . . . . . . . . . . . 94 14 Interrupt request system. . . . . . . . . . . . . . . . . 95 14.1 Interrupt sources overview . . . . . . . . . . . . . . . 95 15 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 16 Power reduction modes . . . . . . . . . . . . . . . . . 98 16.1 Hard power-down . . . . . . . . . . . . . . . . . . . . . . 98 16.2 Soft power-down mode. . . . . . . . . . . . . . . . . . 98 16.3 Transmitter power-down mode . . . . . . . . . . . . 98 17 Oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . 99 18 Reset and oscillator start-up time . . . . . . . . . 99 18.1 Reset timing requirements . . . . . . . . . . . . . . . 99 18.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 99 19 PN512 command set . . . . . . . . . . . . . . . . . . . 100 19.1 General description . . . . . . . . . . . . . . . . . . . 100 19.2 General behavior . . . . . . . . . . . . . . . . . . . . . 100 19.3 PN512 command overview . . . . . . . . . . . . . 101 19.3.1 PN512 command descriptions . . . . . . . . . . . 101 19.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 19.3.1.2 Config command . . . . . . . . . . . . . . . . . . . . . 101 19.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . 102 19.3.1.4 CalcCRC . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.6 NoCmdChange . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.7 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 19.3.1.8 Transceive . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.3.1.9 AutoColl . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19.3.1.10 MFAuthent . . . . . . . . . . . . . . . . . . . . . . . . . . 105 19.3.1.11 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 20 Testsignals. . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.2 Testbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 20.3 Testsignals at pin AUX . . . . . . . . . . . . . . . . . 108 20.4 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 21 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 109 22 Application design-in information. . . . . . . . . 110 23 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 111 24 Recommended operating conditions . . . . . . 111 25 Thermal characteristics . . . . . . . . . . . . . . . . . 112 26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112 26.1 Timing characteristics . . . . . . . . . . . . . . . . . . 117 26.2 8-bit parallel interface timing . . . . . . . . . . . . . 119 26.2.1 AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119 26.2.2 AC operating specification . . . . . . . . . . . . . . . 119 26.2.2.1 Bus timing for separated Read/Write strobe . 119 26.2.2.2 Bus timing for common Read/Write strobe . 120 27 Package information. . . . . . . . . . . . . . . . . . . 122 28 Package outline. . . . . . . . . . . . . . . . . . . . . . . 123 29 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 126 30 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 31 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 126 32 Revision history . . . . . . . . . . . . . . . . . . . . . . 127 33 Legal information . . . . . . . . . . . . . . . . . . . . . 128 33.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 128 33.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 128 33.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 128 33.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 33.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 129 NXP Semiconductors PN512 Full NFC Forum compliant solution © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 December 2013 111345 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 34 Contact information. . . . . . . . . . . . . . . . . . . . 129 35 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 36 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 37 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 1. General description The UHF EPCglobal Generation 2 standard allows the commercialized provision of mass adoption of UHF RFID technology for passive smart tags and labels. Main fields of applications are supply chain management and logistics for worldwide use with special consideration of European, US and Chinese frequencies to ensure that operating distances of several meters can be realized. The NXP Semiconductors UCODE product family is compliant to this EPC gen2 standard offering anti-collision and collision arbitration functionality. This allows a reader to simultaneously operate multiple labels/tags within its antenna field. The UCODE based label/ tag requires no external power supply for contactless operation. Its contactless interface generates the power supply via the antenna circuit by propagative energy transmission from the interrogator (reader), while the system clock is generated by an on-chip oscillator. Data transmitted from the interrogator to the label/tag is demodulated by the interface, and it also modulates the interrogator's electromagnetic field for data transmission from the label/tag to the interrogator. A label/tag can be then operated without the need for line of sight or battery, as long as it is connected to a dedicated antenna for the targeted frequency range. When the label/tag is within the interrogator's operating range, the high-speed wireless interface allows data transmission in both directions. With the UCODE I2C product, NXP Semiconductors introduces now the possibility to combine 2 independent UHF Interfaces (following EPC gen 2 standard) with an I2C interface. Its large memory can be then read or write via both interfaces. This I2C functionality enables the standard EPC gen 2 functionalities to be linked to an electronic device microprocessor. By linking the rich functionalities of the EPC gen 2 standards to the Electronics world, the UCODE I2C product opens a whole new range of application. The I2C interface needs to be supplied externally and supports standard and fast I2C modes. Its large memory is based on a field proven non-volatile memory technology commonly used in high quality automotive applications SL3S4011_4021 UCODE I²C Rev. 3.1 — 3 July 2013 204931 Product data sheet COMPANY PUBLIC SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 2 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 2. Features and benefits 2.1 UHF interface  Dual UHF antenna port  18 dBm READ sensitivity  11 dBm WRITE sensitivity  23 dBm READ & WRITE sensitivity with the chip powered  Compliant to EPCglobal Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for communications at 860 MHz to 960 MHz version 1.2.0  Wide RF interface temperature range: 40 °C up to +85 °C  Memory read protection  Interrupt output  RF - I2C bridge function based on SRAM memory 2.2 I2C interface  Supports Standard (100 kHz) and Fast (400 kHz) mode (see Ref. 1)  UCODE I2C can be used as standard I2C EEPROMs 2.3 Command set  All mandatory EPC Gen2 v1.2.0 commands  Optional commands: Access, Block Write (32 bit)  Custom command: ChangeConfig 2.4 Memory  3328-bit user memory  160-bit EPC memory  96-bit tag identifier (TID) including 48-bit unique serial number  32-bit KILL password to permanently disable the tag  32-bit ACCESS password to allow a transition into the secured transmission state  Data retention: 20 years at 55 °C  Write endurance: 50 kcycles at 85 °C 2.5 Package  SOT-902-3; MO-255B footprint  Outline 1.6 × 1.6 mm  Thickness  0.5 mm SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 3 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 3. Applications  Firmware downloads  Return management  Counterfeit protection and authentication  Production information  Theft protection and deterrence  Production automation  Device customization/product configuration  Offline Diagnostics 4. Ordering information [1] RFP1, RFN1 Table 1. Ordering information Type number Package Name Description Version SL3S4011FHK XQFN8 Single differential RF Front End [1]- Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-3 SL3S4021FHK XQFN8 Dual differential RF Front End - Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-3 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 4 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 5. Block diagram Fig 1. Block diagram RFP1 DIFFERENTIAL UHF FRONTEND 1 RFN1 RFN2 DIFFERENTIAL UHF FRONTEND 2 NON VOLATILE MEMORY I2C INTERFACE ISO18000-6 DIGITAL INTERFACE ANALOG UHF antenna 2 UHF antenna 1 I2C DRIVER/SCL INT SIGNALLING DRIVER 50 ns SPIKE INPUT FILTER RFP2 SCL SDA I2C DRIVER/SDA CE OUPUT DRIVER 50 ns SPIKE INPUT FILTER VDDB VDDB POWER MANAGEMENT/ GND 001aao224 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 5 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 6. Pinning information 6.1 Pinning 6.2 Pin description (1) Dimension A: 1.6 mm (2) Dimension B: 0.5 mm Fig 2. Pin configuration 001aao225 VDD Transparent top view side view 4 8 6 5 7 3 1 RF1N 2 RF1P SCL A B GND A RF2N SDA RF2P Table 2. Pin description Pin Symbol Description 1 RF1P active antenna 1 connector 2 RF1N antenna 1 3 SCL I2C clock / _INT 4 VDD supply 5 SDA I2C data 6 RF2N antenna 2 7 RF2P active antenna 2 connector 8 GND ground SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 6 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 7. Mechanical specification 7.1 SOT902 specification 8. Functional description 8.1 Air interface standards The UCODE I2C fully supports all mandatory parts of the "Specification for RFID Air Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 8.2 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE I2C. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the UCODE I2C on the tag. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. For I2C operation the UCODE I2C has to be supplied externally via the VDD pin. 8.3 Data transfer air interface 8.3.1 Interrogator to tag Link An interrogator transmits information to the UCODE I2C by modulating a UHF RF signal. The UCODE I2C receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. An interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. The interrogator communicates to the UCODE I2C by modulating an RF carrier using DSB-ASK with PIE encoding. 8.3.2 Tag to reader Link An interrogator receives information from a UCODE I2C by transmitting an unmodulated RF carrier and listening for a backscattered reply. The UCODE I2C backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. Table 3. Mechanical properties XQFN8 Package name Outline code Package size Reel format SOT902 SOT902-3 size:1.6 mm × 1.6 mm 4000 pcs thickness: 0.5 mm 7” diameter Carrier tape width 8 mm Carrier pocket pitch 4 mm SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 7 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C The UCODE I2C communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subaltern. 8.4 Data transfer to I2C interface The UCODE I2C memory can be read/written similar to a standard I2C serial EEPROM device. The address space is arranged in a linear manner. When performing a sequential read the address pointer is increased linearly from start of the EPC memory to the end of the user memory. At the end address of each bank the address pointer jumps automatically to the first address in the subsequent bank. In I2C write modes only even address values are accepted, due to the word wise organization of the EEPROM. Regarding arbitration between RF and I2C, see Section 11 “RF interface/I2C interface arbitration”). Write operation: • Write word • Write block (2 words) Read operation: • current address read • random address read • sequential current read • random sequential read 8.5 Supported commands The UCODE I2C supports all mandatory EPCglobal V1.2.0 commands. In addition the UCODE I2C supports the following optional commands. • Access • BlockWrite (32 bit) The UCODE I2C features the following custom commands described in more detail later: • ChangeConfig 8.6 UCODE I2C memory The UCODE I2C memory is implemented according to EPCglobal Gen2 and organized in four sections all accessible via both RF and I2C operation except the reserved memory section which only accessible via RF: SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 8 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C The logical addresses of all memory banks begin at zero (00h). In addition to the 4 memory banks one configuration word to handle the UCODE I2C specific features is available at EPC bank 01b address 200h. The configuration word is described in detail in section “UCODE I2C special features”. Table 4. UCODE I2C memory sections Name Size Bank Reserved memory (32-bit ACCESS and 32-bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16-bit PC) 160 bit 01b Download register 16 bit 01b UCODE I2C Configuration Word 16 bit 01b TID (including unique 48 bit serial number) 96 bit 10b User Memory 3328 bit 11b xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 9 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 8.6.1 UCODE I2C overall memory map [1] SL3S4011 EPC: E200 680D 0000 0000 0000 0000 0000 0000 0000 0000 SL3S4021 EPC: E200 688D 0000 0000 0000 0000 0000 0000 0000 0000 [2] see TID paragraph Table 5. Memory map Bank address Memory address Type Content Initial value Remark RF I2C Bank 00 00h to 1Fh not accessible via i2C reserved kill password all 00h unlocked memory 20h to 3Fh not accessible via i2C reserved access password all 00h unlocked memory Bank 01 EPC 00h to 0Fh 2000h EPC CRC-16: refer to Ref. 5 memory mapped calculated CRC 10h to 1Fh 2002h EPC PC 3000h unlocked memory 20h to 2Fh 2004h EPC EPC bit [0 to 15] [1] unlocked memory ... EPC ... unlocked memory 20h to BFh 2016h EPC EPC bit [144 to 159] unlocked memory 1F0h to 1FFh 203Eh EPC download register for the bridge function 200h to 20Fh 2040h EPC Configuration word, see Section 9.2 Bank 10 TID 00h to 0Fh 4000h TID TID header n.a. locked memory 10h to 1Fh 4002h TID TID header n.a. locked memory 20h to 2Fh 4004h TID XTID_header 0000h locked memory 30h to 3Fh 4006h TID TID serial number [2] locked memory 40h to 4Fh 4008h TID TID serial number n.a. locked memory 50h to 5Fh 400Ah TID TID serial number n.a. locked memory Bank 11 User memory 000h to 00Fh 6000h UM user memory bit [0 to 15] all 00h unlocked memory 010h to 01Fh 6002h UM user memory bit [16 to 31] all 00h unlocked memory ... UM all 00h unlocked memory CF0h to CFFh 619Eh UM user memory bit [3311 to 3327] all 00h unlocked memory xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 10 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 8.6.2 UCODE I2C TID memory details Table 6. UCODE I2C TID description Model number Type First 32 bit of TID memory Class ID Mask designer ID Config Word indicator Sub version number Version (Silicon) number UCODE SL3S4011 E200680D E2h 006h 1 0000b 0001101 UCODE SL3S4021 E200688D E2h 006h 1 0001b 0001101 Fig 3. UCODE I2C TID memory structure aaa-006851 Class Identifier MS Byte MS Bit LS Bit TID Mask-Designer Identifier Model Number XTID Header Serial Number Bits 7 0 11 0 11 0 15 0 47 0 Addresses 00h 07h 13h 1Fh 5Fh Addresses 00h CFh 08h 14h 20h 2Fh 30h E2h (EAN.UCC) TID Example (UCODE I2C) 006h (NXP) 0000h Sub Version Number Version Number 000b or 001b 0001101b (UCODE I2C) Bits 0 3 0 6 0 Addresses 14h 18h 19h 1Fh 80Dh or 88Dh (UCODE I2C) LS Byte SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 11 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9. Supported features The UCODE I2C is equipped with a number of additional features and a custom command. Nevertheless, the chip is designed in a way that standard EPCglobal READ / WRITE / ACCESS commands can be used to operate the features. The memory map in the previous section describes the Configuration Word used to control the additional features located after address 200h of the EPC memory, hence UCODE I2C features are controlled by bits located in the EPC number space. For this reason the standard READ / WRITE commands of a UHF EPCglobal compliant reader can be used to select the flags or activate/deactivate features if the memory bank is not locked. In case of locked memory banks the ChangeConfig custom command has to be used. The bits (flags) of the ConfigurationWord are selectable using the standard EPC SELECT command. 9.1 UCODE I2C special feature • Externally Supplied flag The flag will indicate the availability of an external supply. • RF active flag The flag will indicate on which RF port power is available and signal transmission ongoing. • RF Interface on/off switching For privacy reasons the two RF ports as well as the I2C interface can be switched on/off by toggling the related bits of the ConfigurationWord. The ConfigurationWord is accessible via RF and I2C interface. Although it is possible to kill the RF interface via the KILL feature of EPC gen2, a minimum of one port shall be active at all times. In the case of the dual port version, either one or both RF can be active. In the case of the single front end version, the RF port can not be deactivated. • I2C Interface on/off switching For privacy reasons the I2C port can be disabled by toggling the related bit of the Config-Word but only via RF. • RF - I2C Bridge feature The UCODE I2C can be used as an RF- I2C bridge to directly forward data from the RF interface to the I2C interface and vice versa. The UCODE I2C is equipped with a download/upload register of 16-bit data buffer located in the EPC bank. The data received via RF can be read via I2C like regular memory content. In case the buffer is empty reading the register returns NAK. This feature can be combined with the Download Indicator. – Upload Indicator flag (I2C to UHF) - address 203h in the configuration word The flag will indicate if data in the download/upload register is available. Will be automatically cleared when the download/upload register is read out via UHF. – Download Indicator flag (UHF to I2C) - address 200h in the configuration word The flag will indicate if data in the download/upload register is available. Will be automatically cleared when the download/upload register is read out via I2C. SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 12 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C • Interrupt signaling/Download Indicator The UCODE I2C features two methods of signaling: 1. Signaling via ConfigWord "Download/Upload Indicator" (200h or 203h): – The Download/Upload Indicator will go high as soon new data from the RF reader or from the I2C interface is written to the buffer register. This flag can be polled via I2C READ or using the SELECT command. Reading an empty buffer register will return NAK. – The Download/Upload Indicator will automatically return to low as soon as the data is read. 2. Interrupt Signaling via the I2C-SCL line: – If the SCL INT enabler of the ConfigWord is set (20Bh) the SCL line will be pulled low for at least 210 s in case new data was written by the reader or at least 85 s in case new data has been read by the reader (see Figure 4 “SCL interrupt signalling” and Table 7 “Interrupt signaling via the I2C-SCL line timing”). [1] This timing parameter is dependent on the chosen return link frequency. [2] At 640 kHz return link frequency. Remark: The features can even be operated (enabled/disabled) with '0' as ACCESS password. It is recommended to set an ACCESS password to avoid unauthorized manipulation of the features via the RF interface. 9.2 UCODE I2C special features control mechanism Special features of the UCODE I2C are managed using a Configuration Word (ConfigWord) located at the end of the EPC memory bank (address 200h via RF or 2040h via I2C) - see Table 8 and Table 9. Fig 4. SCL interrupt signalling Table 7. Interrupt signaling via the I2C-SCL line timing Symbol Min Typ Max Unit tSCL low_write 210 266 320 s tSCL low_read[1] 85 102[2] 7800 s aaa-005682 UHF Write DL Reg Command SCL UHF SCL Read DL Reg Command Read DL Reg Response Write DL Reg Response tSCL low_read tSCL low_write SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 13 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C The bits of the ConfigWord are selectable (using the standard EPC SELECT command) and can be read, via RF, using standard EPC READ command and via I2C. They can be modified using the ChangeConfig custom command or standard READ/WRITE commands or via the I2C interface (if allowed). [1] Indicator bits are reset at power-up but cannot be changed by command [2] Permanent bits are permanently stored bits in the memory [3] Defaults values for bit3/bit2/bit1 are 0/0/1 (see Table 14) Table 8. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (1 RF front end version SL3S4011) Feature Bit type via RF via I2C Address Access Address Access Download indicator indicator[1] 200h read 2040h read Externally supplied flag indicator 201h read read RF active flag indicator 202h read read Upload indicator Indicator 203h read read I2C address bit 3[3] permanent[2] 204h r/w read only I2C address bit 2[3] permanent 205h r/w read only I2C address bit 1[3] permanent 206h r/w read only I2C port on/off permanent 207h r/w read only UHF antenna port1 on locked 208h read only read only rfu 209h rfu 20Ah SCL INT enable permanent 20Bh r/w read only bit for read protect user memory permanent 20Ch r/w r/w bit for read protect EPC permanent 20Dh r/w r/w bit for read protect TID SNR (48 bits) permanent 20Eh r/w r/w PSF alarm flag permanent 20Fh r/w read only Table 9. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (2 RF front end version SL3S4021) Feature Bit type via RF via I2C Address Access Address Access Download indicator indicator[1] 200h read 2040h read Externally supplied flag indicator 201h read read RF active flag indicator 202h read read Upload indicator indicator 203h read read I2C address bit 3[3] permanent[2] 204h r/w read only I2C address bit 2[3] permanent 205h r/w read only I2C address bit 1[3] permanent 206h r/w read only I2C port on/off permanent 207h r/w read only UHF antenna port1 on/off permanent 208h r/w r/w UHF antenna port2 on/off permanent 209h r/w r/w rfu 20Ah SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 14 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C [1] Indicator bits are reset at power-up but cannot be changed by command [2] Permanent bits are permanently stored bits in the memory [3] Defaults values for bit3/bit2/bit1 are 0/0/1 (see Table 14) SCL INT enable permanent 20Bh r/w read only bit for read protect user memory permanent 20Ch r/w r/w bit for read protect EPC permanent 20Dh r/w r/w bit for read protect TID SNR (48 bits) permanent 20Eh r/w r/w PSF alarm flag permanent 20Fh r/w read only Table 9. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (2 RF front end version SL3S4021) Feature Bit type via RF via I2C Address Access Address Access SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 15 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9.3 Change Config Command The UCODE I2C ChangeConfig custom command allows handling the special features described in the previous paragraph. As long the EPC bank is not write locked standard EPC READ/WRITE commands can be used to modify the flags. The bits to be toggled in the configuration register need to be set to '1'. E.g. sending 0000 0000 0000 0000 1001 XOR RN16 will activate the EPC Read Protect and PSF bit. Sending the very same command a second time will disable the features. The reply of the ChangeConfig will return the current register setting. The features can only be activated/deactivated in the open or secured state and with a non-zero ACCESS password. If the EPC memory bank is locked for writing, the ChangeConfig command is needed to modify the ConfigurationWord. Table 10. ChangeConfig custom command Command RFU Data RN CRC-16 No. of bits 16 8 16 16 16 Description 11100000 00000111 00000000 Toggle bits XOR RN16 handle - Table 11. ChangeConfig custom response table Starting state Condition Response Next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle, Status word needs to change Backscatter unchanged StatusWord immediately open valid handle, Status word does not need to change Backscatter StatusWord immediately open secured valid handle, Status word needs to change Backscatter modified StatusWord, when done secured valid handle, Status word does not need to change Backscatter StatusWord immediately secured invalid handle - secured killed all - killed xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 16 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9.4 UCODE I2C memory bank locking mechanism 9.4.1 Possibilities 9.4.2 Via RF The UCODE I2C memory banks can be locked following EPC Gen2 mandatory command via RF (see table Table 13). Table 12. Memory banks locking possibilities for UCODE I2C via RF and I2C I2C interface RF interface Memory bank Lock (entire bank) PermaLock (entire bank) Lock (entire bank) via Access Password PermaLock (entire bank) via Access Password 01 EPC yes yes yes yes 11 User Memory yes yes yes yes Table 13. Lock payload and usage Kill pwd Access pwd EPC memory TID memory User memory 19 18 17 16 15 14 13 12 11 10 Mask skip/write skip/write skip/write skip/write skip/write skip/write skip/write skip/write skip/write skip/write 9 8 7 6 5 4 3 2 1 0 Action pwd read/write permalock pwd read/write permalock pwd write permalock pwd write permalock pwd write permalock SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 17 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 9.4.3 Via I2C The EPC Gen2 locking bits for the memory banks are also accessible via the I2C interface for read and write operation and are located at the I2C address 803Ch. But it is not possible to read and write the access and kill password. Fig 5. I2C memory bank lock write and read access Data Byte 1 Mask field Action field Kill PWD Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write Skip/ write X X X X X X X X X X X X Access PWD User memory RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU EPC memory TID memory Kill PWD n/a n/a n/a n/a permalock permalock permalock PWD write PWD write PWD write Access PWD EPC memory TID memory User memory MSB Data Byte 2 LSB MSB Data Byte 3 Data Byte 4 LSB aaa-003734 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 18 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10. I2C commands 10.1 UCODE I2C operation For details on I2C interface refer to Ref. 1. The UCODE I2C supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. 10.2 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The UCODE I2C continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Fig 6. I2C bus protocol SCL SDA SCL 1 2 3 7 8 9 1 2 3 7 8 9 MSB ACK MSB ACK Start Condition SDA Input SDA Change Stop Condition Stop Condition Start Condition SDA SCL SDA 001aao231 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 19 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.3 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the UCODE I2C and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the UCODE I2C into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle. 10.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 10.5 Data input During data input, the UCODE I2C samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 10.6 Addressing To start communication between a bus master and the UCODE I2C slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code. The 7-bit device select code consists of a 4-bit device identifier (value Ah) which is initialized in wafer test and cannot be changed in the user mode. Three additional bits in the configuration word are reserved to alter the device address via RF interface after initialization. This allows up to eight UCODE I2C devices to be connected to a bus master at the same time. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the UCODE I2C gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the UCODE I2C does not match the device select code, it deselects itself from the bus. [1] Initial values - can be changed - See also Table 8 and Table 9. Table 14. Device select code Device type identifier Device address in configuration word 204h to 206h R/W Device select code b7 b6 b5 b4 b3 b2 b1 b0 Value 1 0 1 0 0 [1] 0 [1] 1 [1] 1/0 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 20 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.7 Write Operation The byte address must be an even value due to the word wise organization of the EEPROM. Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The UCODE I2C acknowledges this, as shown in Figure 7 and waits for two address bytes. The UCODE I2C responds to each address byte with an acknowledge bit, and then waits for the data Byte. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 15) is sent first, followed by the Least Significant Byte (Table 15). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the ACK bit (in the "10th bit" time slot), either at the end of a Word Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the UCODE I2C does not respond to any requests. Table 15. I2C addressing Most significant byte b15 b14 b13 b12 b11 b10 b9 b8 EPC address EPC/Lock EPC memory bank EPC memory word address Least significant byte b7 b6 b5 b4 b3 b2 b1 b0 EPC address EPC memory word address MSB/ LSB Fig 7. I2C write operation ACK Word Write Page Write Page Write (cont’d) ACK ACK ACK ACK Stop Start R/W Dev select Byte address Byte address Data in 1 Data in 2 ACK Stop 001aao230 ACK ACK ACK ACK Start R/W Dev select Byte address Byte address Data in 1 Data in 2 ACK Data in N SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 21 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.7.1 Word Write After the device select code and the address word, the bus master sends one word data. If the addressed location is Write-protected, the UCODE I2C replies with NACK, and the location is not modified. If, instead, the addressed location is not Write-protected, the UCODE I2C replies with ACK. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 7. 10.7.2 Page Write The Page Write mode allows 2 words to be written in a single Write cycle, provided that they are all located in the same 'row' in the memory: that is, the most significant memory address bits (b12-b2) are the same and b1= 0 and b0 = 0. If more than two words are sent than each additional byte will cause a NACK on SDA. The bus master sends from 1 to 2 words of data, each of which is acknowledged by the UCODE I2C. The transfer is terminated by the bus master generating a Stop condition. 10.8 Read operation After the successful completion of a read operation, the UCODE I2C's internal address counter is incremented by one, to point to the next byte address. Fig 8. I2C read operation ACK ACK NO ACK Current Address Read Random Address Read Sequential Current Read Sequential Random Read ACK ACK ACK NO ACK Stop Start Start Start Stop R/W R/W R/W R/W Dev select * Byte address Dev select * Data out Dev select Data out Byte address ACK ACK ACK NO ACK NO ACK Stop Stop Start Dev select Data out 1 Data out N 001aao229 ACK ACK ACK ACK ACK Start Start R/W R/W Dev select * Byte address Byte address Dev select * Data out 1 ACK Data out N SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 22 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 10.8.1 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 8) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The UCODE I2C acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 10.8.2 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a UCODE I2C select code with the Read/Write bit (RW) set to 1. The UCODE I2C acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 8, without acknowledging the Byte. 10.8.3 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the UCODE I2C continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 8. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. 10.8.4 Acknowledge in Read mode For all Read commands, the UCODE I2C waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the UCODE I2C terminates the data transfer and switches to its Standby mode. 10.8.5 EPC memory bank handling After the last memory address within one EPC memory bank, the address counter 'rolls-over' to the next EPC memory bank, and the UCODE I2C continues to output data from memory address 00h in the successive EPC memory bank. Example: EPC Bank 01  EPC Bank 10  EPC Bank 11  EPC Bank 01 SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 23 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 11. RF interface/I2C interface arbitration The UCODE I2C needs to arbitrate the EEPROM access between the RF and the I2C interface. The arbitration is implemented as following: • First come, first serve strategy - the interface which provides data by having a first valid preamble on RF envelope (begin of a command) or a start condition and a valid I2C device address on the I2C interface will be favored. • I2C access to the chip memory is possible regardless if it is in the EPC Gen2 secured state or not • During an I2C command, starting with an I2C start followed by valid I2C device address and ending with an I2C stop condition, any RF command is ignored. • During any EPC Gen2 command any I2C command is ignored 12. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP8 package. [4] For ESD measurement, the die chip has been mounted into a CDIP8 package. Table 16. Limiting values[1][2] [3][4] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit Die Vmax maximum voltage on pin VDD, SDA, SCL, GND 0.3 3.6 V Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage Human body model; SNW-FQ-302A - 2 kV Charged device model - 500 V SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 24 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 13. Characteristics [1] Some legacy Standard-mode devices had fixed input levels of VIL = 1.5 V and VIH = 3.0 V. Refer to component data sheets. [2] Maximum VIH = VDD(max) + 0.5 V or 5.5 V, which ever is lower. See component data sheets. [3] The same resistor value to drive 3 mA at 3.0 V VDD provides the same RC time constant when using <2 V VDD with a smaller current draw. [4] Only applies to Fast Mode and Fast Mode Plus. Table 17. Characteristics Symbol Parameter Conditions Min Typ Max Unit EEPROM characteristics tret retention time Tamb  55 C 20 - - year Nendu(W) write endurance Tamb  85 C 50000 - - cycle Interface characteristics Ptot total power dissipation - - 30 mW foper operating frequency 840 - 960 MHz Pmin minimum operating power supply Read mode - 18 - dBm Write mode - 11 - dBm Read and Write mode with VDD input - 23 - dBm VDD supply voltage I2C, on VDD input 1.8 - 3.6 V VDD supply voltage rise time requirements 100 - - s IDD supply current from VDD in I2C read mode - 10 - A from VDD in I2C write mode - 40 - A Z impedance (package) 915 MHz - 12,7-j 199 -  - modulated jammer suppression  1.0 MHz - 4 - dB - unmodulated jammer suppression  1.0 MHz - 4 - dB VIL LOW-level input voltage[1] -0.5 - 0.3 VDD V VIH HIGH-level input voltage[1] 0.7 VDD - -[2] V Vhys hysteresis of Schmitt trigger inputs[4] 0.05 VDD - - V VOL1 LOW-level output voltage 1 (open-drain or open-collector) at 3 mA sink current[3]; VDD > 2 V 0 - 0.4 V VOL2 LOW-level output voltage 2[4] (open-drain or open-collector) at 2 mA sink current[3]; VDD  2 V 0 - 0.2VDD V SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 25 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 14. Package outline Fig 9. Package outline SOT902-3 Outline References version European projection Issue date IEC JEDEC JEITA SOT902-3 - - - MO-255 - - - sot902-3_po 11-08-16 11-08-18 Unit mm max nom min 0.5 0.05 0.00 1.65 1.60 1.55 1.65 1.60 1.55 0.6 0.5 0.1 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-3 A1 b 0.25 0.20 0.15 D E e e1 L 0.45 0.40 0.35 v w 0.05 y y1 0.05 0 1 2 mm scale terminal 1 index area D B A E X C y1 C y terminal 1 index area 3 L e1 e v C A B w C 2 1 5 6 7 metal area not for soldering 8 4 e1 e b A1 A detail X SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 26 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 15. Abbreviations 16. References [1] I2C-bus specification and user manual (NXP standard UM10204.pdf / Rev. 03 - 19 June 2007) [2] EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz - 960 MHz Version 1.2.0 [3] EPC Conformance Standard Version 1.0.5 [4] ESD Method SNW -FQ-302A [5] ISO/IEC 18000-1: Information technology - Radio frequency identification for item management - Part 1: Reference architecture and definition of parameters to be standardized Table 18. Abbreviations Acronym Description CRC Cyclic Redundancy Check CW Continuous Wave EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bhi phase space modulation HBM Human Body Model IC Integrated Circuit LSB Least Significant Byte/Bit MSB Most Significant Byte/Bit NRZ Non-Return to Zero coding RF Radio Frequency RTF Reader Talks First Tari Type A Reference Interval (ISO 18000-6) UHF Ultra High Frequency Xxb Value in binary notation XXhex Value in hexadecimal notation SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 27 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 17. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3S4011_4021 v. 3.1 20130703 Product data sheet - SL3S4011_4021 v. 3.0 Modifications: • General update SL3S4011_4021 v. 3.0 20130416 Product data sheet - SL3S4011_4021 v. 2.3 Modifications: • Data sheet status changed to Product data sheet SL3S4011_4021 v. 2.3 20130305 Preliminary data sheet - SL3S4011_4021 v. 2.2 Modifications: • General update • Security status changed into COMPANY PUBLIC SL3S4011_4021 v. 2.2 20121127 Preliminary data sheet SL3S4011_4021 v. 2.1 Modifications: • General update SL3S4011_4021 v. 2.1 20120726 Preliminary data sheet - SL3S4001FHK v. 2.0 Modifications: • General update SL3S4011_4021 v. 2.0 20120627 Preliminary data sheet - SL3S4001FHK v. 1.2 Modifications: • General update SL3S4001FHK v. 1.2 20111004 Objective data sheet - SL3S4001FHK v. 1.1 Modifications: • Table 1 “Ordering information”: updated • Figure 3 “UCODE I2C wafer layout”: values updated SL3S4001FHK v. 1.1 20110707 Objective data sheet - SL3S4001FHK v. 1.0 Modifications: • Table 3 “Mechanical properties XQFN8”: updated • Section 10.6 “Addressing”: updated SL3S4001FHK v. 1.0 20110609 Objective data sheet - - SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 28 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 29 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 3 July 2013 204931 30 of 31 NXP Semiconductors SL3S4011_4021 UCODE I²C 20. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Mechanical properties XQFN8 . . . . . . . . . . . . . .6 Table 4. UCODE I2C memory sections . . . . . . . . . . . . . .8 Table 5. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 6. UCODE I2C TID description . . . . . . . . . . . . . . .10 Table 7. Interrupt signaling via the I2C-SCL line timing .12 Table 8. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (1 RF front end version SL3S4011) . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 9. Configuration Word accessible located at address 200h via UHF of the EPC bank and I2C address 2040h (2 RF front end version SL3S4021) . . . . . . . . . . . . . . . . . . . . . 13 Table 10. ChangeConfig custom command. . . . . . . . . . . 15 Table 11. ChangeConfig custom response table. . . . . . . 15 Table 12. Memory banks locking possibilities for UCODE I2C via RF and I2C . . . . . . . . . . . . . . . 16 Table 13. Lock payload and usage . . . . . . . . . . . . . . . . . 16 Table 14. Device select code. . . . . . . . . . . . . . . . . . . . . . 19 Table 15. I2C addressing . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 16. Limiting values[1][2] [3][4] . . . . . . . . . . . . . . . . . . 23 Table 17. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 18. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 19. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 21. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. UCODE I2C TID memory structure . . . . . . . . . . .10 Fig 4. SCL interrupt signalling . . . . . . . . . . . . . . . . . . . .12 Fig 5. I2C memory bank lock write and read access . . .17 Fig 6. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .18 Fig 7. I2C write operation . . . . . . . . . . . . . . . . . . . . . . . .20 Fig 8. I2C read operation . . . . . . . . . . . . . . . . . . . . . . . .21 Fig 9. Package outline SOT902-3 . . . . . . . . . . . . . . . . .25 NXP Semiconductors SL3S4011_4021 UCODE I²C © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 July 2013 204931 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 UHF interface . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Mechanical specification . . . . . . . . . . . . . . . . . 6 7.1 SOT902 specification . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Air interface standards . . . . . . . . . . . . . . . . . . . 6 8.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.3 Data transfer air interface . . . . . . . . . . . . . . . . . 6 8.3.1 Interrogator to tag Link . . . . . . . . . . . . . . . . . . . 6 8.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . . 6 8.4 Data transfer to I2C interface . . . . . . . . . . . . . . 7 8.5 Supported commands . . . . . . . . . . . . . . . . . . . 7 8.6 UCODE I2C memory. . . . . . . . . . . . . . . . . . . . . 7 8.6.1 UCODE I2C overall memory map. . . . . . . . . . . 9 8.6.2 UCODE I2C TID memory details . . . . . . . . . . 10 9 Supported features . . . . . . . . . . . . . . . . . . . . . 11 9.1 UCODE I2C special feature . . . . . . . . . . . . . . 11 9.2 UCODE I2C special features control mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9.3 Change Config Command . . . . . . . . . . . . . . . 15 9.4 UCODE I2C memory bank locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.1 Possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.2 Via RF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.4.3 Via I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 I2C commands . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.1 UCODE I2C operation. . . . . . . . . . . . . . . . . . . 18 10.2 Start condition. . . . . . . . . . . . . . . . . . . . . . . . . 18 10.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . 19 10.5 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.7 Write Operation. . . . . . . . . . . . . . . . . . . . . . . . 20 10.7.1 Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.7.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.8 Read operation . . . . . . . . . . . . . . . . . . . . . . . 21 10.8.1 Random Address Read . . . . . . . . . . . . . . . . . 22 10.8.2 Current Address Read . . . . . . . . . . . . . . . . . . 22 10.8.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . 22 10.8.4 Acknowledge in Read mode . . . . . . . . . . . . . 22 10.8.5 EPC memory bank handling . . . . . . . . . . . . . 22 11 RF interface/I2C interface arbitration. . . . . . . 23 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 25 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 26 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 27 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 28 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29 19 Contact information . . . . . . . . . . . . . . . . . . . . 29 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1. General description NXP’s UCODE G2iL series transponder ICs offer leading-edge read range and support industry-first features such as a Tag Tamper Alarm, Data Transfer, Digital Switch, and advanced privacy-protection modes. Very high chip sensitivity (18 dBm) enables longer read ranges with simple, single-port antenna designs. When connected to a power supply, the READ as well as the WRITE range can be boosted to a sensitivity of 27 dBm. In fashion and retail the UCODE G2iL series improve read rates and provide for theft deterrence. For consumer electronics the UCODE G2iL series is suited for device configuration, activation, production control, and PCB tagging. In authentication applications the transponders can be used to protect brands and guard against counterfeiting. They can also be used to tag containers, electronic vehicles, airline baggage, and more. In addition to the EPC specifications the G2iL offers an integrated Product Status Flag (PSF) feature and read protection of the memory content. On top of the G2iL features the G2iL+ offers an integrated tag tamper alarm, RF field detection, digital switch, external supply mode, read range reduction and data transfer mode. 2. Features and benefits 2.1 Key features  UHF RFID Gen2 tag chip according EPCglobal v1.2.0 with 128 bit EPC memory  Memory read protection  Integrated Product Status Flag (PSF)  Tag tamper alarm  RF field detection  Digital switch  Data transfer mode  Real Read Range Reduction (Privacy Mode)  External supply mode where both the READ & WRITE range are boosted to -27dBm 2.1.1 Memory  128-bit of EPC memory  64-bit Tag IDentifier (TID) including 32-bit factory locked unique serial number  32-bit kill password to permanently disable the tag  32-bit access password to allow a transition into the secured state SL3S1203_1213 UCODE G2iL and G2iL+ Rev. 4.4 — 17 March 2014 178844 Product data sheet COMPANY PUBLIC SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 2 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+  Data retention: 20 years  Broad international operating frequency: from 840 MHz to 960 MHz  Long read/write ranges due to extremely low power design  Reliable operation of multiple tags due to advanced anti-collision  READ protection  WRITE Lock  Wide specified temperature range: 40 C up to +85 C 2.2 Key benefits 2.2.1 End user benefit  Prevention of unauthorized memory access through read protection  Indication of tag tampering attempt by use of the tag tamper alarm feature  Electronic device configuration and / or activation by the use of the digital switch / data transfer mode  Theft deterrence supported by the PSF feature (PSF alarm or EPC code)  Small label sizes, long read ranges due to high chip sensitivity  Product identification through unalterable extended TID range, including a 32-bit serial number  Reliable operation in dense reader and noisy environments through high interference suppression 2.2.2 Antenna design benefits  High sensitivity enables small and cost efficient antenna designs  Low Q-Value eases broad band antenna design for global usage 2.2.3 Label manufacturer benefit  Consistent performance on different materials due to low Q-factor  Ease of assembly and high assembly yields through large chip input capacitance  Fast first WRITE of the EPC memory for fast label initialization 2.3 Custom commands  PSF Alarm Built-in PSF (Product Status Flag), enables the UHF RFID tag to be used as EAS tag (Electronic Article Surveillance) tag without the need for a back-end data base.  Read Protect Protects all memory content including CRC16 from unauthorized reading.  ChangeConfig Configures the additional features of the chip like external supply mode, tamper alarm, digital switch, read range reduction or data transfer. The UCODE G2iL is equipped with a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. No custom commands are needed to take advantage of all the features in case of unlocked EPC memory. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 3 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 3. Applications 3.1 Markets  Fashion (Apparel and footwear)  Retail  Electronics  Fast Moving Consumer Goods  Asset management  Electronic Vehicle Identification 3.2 Applications  Supply chain management  Item level tagging  Pallet and case tracking  Container identification  Product authentication  PCB tagging  Cost efficient, low level seals  Wireless firmware download  Wireless product activation Outside above mentioned applications, please contact NXP Semiconductors for support. 4. Ordering information 5. Marking Table 1. Ordering information Type number Package Name IC type Description Version SL3S1203FUF Wafer G2iL bumped die on sawn 8” 75 m wafer not applicable SL3S1213FUF Wafer G2iL+ bumped die on sawn 8” 75 m wafer not applicable SL3S1203FUD/BG Wafer G2iL bumped die on sawn 8” 120 m wafer, 7 m Polyimide spacer not applicable SL3S1213FUD/BG Wafer G2iL+ bumped die on sawn 8” 120 m wafer, 7 m Polyimide spacer not applicable SL3S1203FTB0 XSON6 G2iL plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886F1 Table 2. Marking codes Type number Marking code Comment Version SL3S1203FTB0 UN UCODE G2iL SOT886 SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 4 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 6. Block diagram The SL3S12x3 IC consists of three major blocks: - Analog Interface - Digital Control - EEPROM The analog part provides stable supply voltage and demodulates data received from the reader for being processed by the digital part. Further, the modulation transistor of the analog part transmits data back to the reader. The digital section includes the state machines, processes the protocol and handles communication with the EEPROM, which contains the EPC and the user data. Fig 1. Block diagram of G2iL IC 001aam226 MOD DEMOD VREG VDD VDD data in data out R/W ANALOG RF INTERFACE PAD PAD RECT DIGITAL CONTROL ANTENNA ANTICOLLISION READ/WRITE CONTROL ACCESS CONTROL EEPROM INTERFACE CONTROL RF INTERFACE CONTROL I/O CONTROL I/O CONTROL EEPROM MEMORY SEQUENCER CHARGE PUMP PAD OUT PAD SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 5 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 7. Pinning information 7.1 Pin description Fig 2. Pinning bare die Fig 3. Pin configuration for SOT886 001aam529 VDD OUT RFN NXP trademark RFP SL3S12x3FTB0 n.c. 001aan103 RFP RFN n.c. VDD OUT Transparent top view 2 3 1 5 4 6 Table 3. Pin description bare die Symbol Description OUT output pin RFN grounded antenna connector VDD external supply RFP ungrounded antenna connector Table 4. Pin description SOT886 Pin Symbol Description 1 RFP ungrounded antenna connector 2 n.c. not connected 3 RFN grounded antenna connector 4 OUT output pin 5 n.c. not connected 6 VDD external supply SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 6 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 8. Wafer layout 8.1 Wafer layout (1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m) (2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m) (3) Chip step, x-length: 485 m (4) Chip step, y-length: 435 m (5) Bump to bump distance X (OUT - RFN): 383 m (6) Bump to bump distance Y (RFN - RFP): 333 m (7) Distance bump to metal sealring X: 40,3 m (outer edge - top metal) (8) Distance bump to metal sealring Y: 40,3 m Bump size X x Y: 60 m x 60 m Remark: OUT and VDD are used with G2iL+ only Fig 4. G2iL wafer layout not to scale! 001aak871 (1) (7) (2) (8) (5) (6) (4) (3) Y X VDD OUT RFN RFP SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 7 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 9. Mechanical specification The UCODE G2iL/G2iL+ wafers are available in 75 m and 120 m thickness. The 75m thick wafer allows ultra thin label design but require a proper tuning of the glue dispenser during production. Because of the more robust structure of the 120m wafer, the wafer is ideal for harsh applications. The 120 m thick wafer is also enhanced with 7m Polyimide spacer allowing additional protection of the active circuit. 9.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**”. 9.1.1 Wafer Table 5. Specifications Wafer Designation each wafer is scribed with batch number and wafer number Diameter 200 mm (8”) Thickness SL3S12x3FUF 75 m  15 m SL3S12x3FUD 120 m  15 m Number of pads 4 Pad location non diagonal/ placed in chip corners Distance pad to pad RFN-RFP 333.0 m Distance pad to pad OUT-RFN 383.0 m Process CMOS 0.14 m Batch size 25 wafers Potential good dies per wafer 139.351 Wafer backside Material Si Treatment ground and stress release Roughness Ra max. 0.5 m, Rt max. 5 m Chip dimensions Die size including scribe 0.485 mm  0.435 mm = 0.211 mm2 Scribe line width: x-dimension = 15 m y-dimension = 15 m Passivation on front Type Sandwich structure Material PE-Nitride (on top) Thickness 1.75 m total thickness of passivation Polyimide spacer 7 m  1 m (SL3S12x3FUD only) Au bump Bump material > 99.9 % pure Au SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 8 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer. 9.1.2 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 9.1.3 Map file distribution See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 10. Functional description 10.1 Air interface standards The UCODE G2iL fully supports all parts of the "Specification for RFID Air Interface EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0". 10.2 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE G2iL. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the G2iL on the tag. The G2iL+ can also be supplied externally. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. Bump hardness 35 – 80 HV 0.005 Bump shear strength > 70 MPa Bump height SL3S12x3FUF 18 m SL3S12x3FUD 25 m[1] Bump height uniformity within a die  2 m – within a wafer  3 m – wafer to wafer  4 m Bump flatness  1.5 m Bump size – RFP, RFN 60  60 m – OUT, VDD 60  60 m Bump size variation  5 m Table 5. Specifications SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 9 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The antenna that is attached to the chip may use a DC connection between the two antenna pads. Therefore the G2iL also enables loop antenna design. Possible examples of supported antenna structures can be found in the reference antenna design guide. 10.3 Data transfer 10.3.1 Reader to tag Link An interrogator transmits information to the UCODE G2iL by modulating an UHF RF signal. The G2iL receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. In order to further improve the read range the UCODE G2iL+ can be externally supplied as well so the energy to operate the chip does not need to be transmitted by the reader. An interrogator is using a fixed modulation and data rate for the duration of at least one inventory round. It communicates to the G2iL by modulating an RF carrier using DSB-ASK with PIE encoding. For further details refer to Section 16, Ref. 1. Interrogator-to-tag (R=>T) communications. 10.3.2 Tag to reader Link An interrogator receives information from a G2iL by transmitting an unmodulated RF carrier and listening for a backscattered reply. The G2iL backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. For further details refer to Section 16, Ref. 1, chapter 6.3.1.3. The UCODE G2iL communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subcarrier. 10.4 G2iL and G2iL+ differences The UCODE G2iL is tailored for application where mainly EPC or TID number space is needed. The G2iL+ in addition provides functionality such as tag tamper alarm, external supply operation to further boost read/write range (external supply mode), a Privacy mode reducing the read range or I/O functionality (data transfer to externally connected devices) required. The following table provides an overview of G2iL, G2iL+ special features. Table 6. Overview of G2iL and G2iL+ features Features G2iL G2iL+ Read protection (bankwise) yes yes PSF (Built-in Product Status Flag) yes yes Backscatter strength reduction yes yes Real read range reduction yes yes Digital switch / Digital input - yes External supply mode - yes SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 10 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.5 Supported commands The G2iL supports all mandatory EPCglobal V1.2.0 commands. In addition the G2iL supports the following optional commands: • ACCESS • Block Write (32 bit) The G2iL features the following custom commands described more in detail later: • ResetReadProtect (backward compatible to G2X) • ReadProtect (backward compatible to G2X) • ChangeEAS (backward compatible to G2X) • EAS_Alarm (backward compatible to G2X) • ChangeConfig (new with G2iL) 10.6 G2iL, G2iL+ memory The G2iL, G2iL+ memory is implemented according EPCglobal Class1Gen2 and organized in three sections: The logical address of all memory banks begin at zero (00h). In addition to the three memory banks one configuration word to handle the G2iL specific features is available at EPC bank 01 address 200h. The configuration word is described in detail in Section 10.7.1 “ChangeConfig”. Memory pages (16 bit words) pre-programmed to zero will not execute an erase cycle before writing data to it. This approach accelerates initialization of the chip and enables faster programming of the memory. RF field detection - yes Data transfer - yes Tag tamper alarm - yes Table 6. Overview of G2iL and G2iL+ features …continued Features G2iL G2iL+ Table 7. G2iL memory sections Name Size Bank Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16 bit PC) 128 bit 01b G2iL Configuration Word 16 bit 01b TID (including permalocked unique 32 bit serial number) 64 bit 10b SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 11 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.6.1 G2iL, G2iL+ overall memory map [1] See Figure 5 [2] Indicates the existence of a Configuration Word at the end of the EPC number [3] See also Table 12 for further details. Table 8. G2iL, G2iL+ overall memory map Bank address Memory address Type Content Initial Remark Bank 00 00h to 1Fh reserved kill password all 00h unlocked memory 20h to 3Fh reserved access password all 00h unlocked memory Bank 01 EPC 00h to 0Fh EPC CRC-16: refer to Ref. 16 memory mapped calculated CRC 10h to 14h EPC backscatter length 00110b unlocked memory 15h EPC UMI 0b unlocked memory 16h EPC XPC indicator 0b hardwired to 0 17h to 1Fh EPC numbering system indicator 00h unlocked memory 20h to 9Fh EPC EPC [1] unlocked memory Bank 01 Config Word 200h EPC tamper alarm flag 0b[3] indicator bit 201h EPC external supply flag or input signal 0b[3] indicator bit 202h EPC RFU 0b[3] locked memory 203h EPC RFU 0b[3] locked memory 204h EPC invert digital output: 0b[3] temporary bit 205h EPC transparent mode on/off 0b[3] temporary bit 206h EPC transparent mode data/raw 0b[3] temporary bit 207h EPC RFU 0b[3] locked memory 208h EPC RFU 0b[3] locked memory 209h EPC max. backscatter strength 1b[3] unlocked memory 20Ah EPC digital output 0b[3] unlocked memory 20Bh EPC read range reduction on/off 0b[3] unlocked memory 20Ch EPC RFU 0b[3] locked memory 20Dh EPC read protect EPC Bank 0b[3] unlocked memory 20Eh EPC read protect TID 0b[3] unlocked memory 20Fh EPC PSF alarm flag 0b[3] unlocked memory Bank 10 TID 00h to 07h TID allocation class identifier 1110 0010b locked memory 08h to 13h TID tag mask designer identifier 0000 0000 0110b locked memory 14h TID config word indicator 1b[2] locked memory 14h to 1Fh TID tag model number TMNR[1] locked memory 20h to 3Fh TID serial number SNR locked memory xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 12 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.6.2 G2iL TID memory details Fig 5. G2iL TID memory structure aaa-010217 E2006906 E2h 006h 1 0010b 0000110b Ucode G2iL+ E2006807 E2h 006h 1 0000b 0000111b E2006907 E2h 006h 1 0010b 0000111b Ucode G2iL E2006806 E2h 006h 1 0000b 0000110b First 32 bit of TID memory Class ID Mask Designer ID Config Word Indicator Sub Version Nr. Model Number Version (Silicon) Nr. Class Identifier MS Byte MS Bit LS Bit LS Byte TID MS Bit LS Bit Mask-Designer Identifier Model Number Serial Number Bits 7 0 11 0 11 0 31 0 Addresses 00h 07h 13h 1Fh 3Fh Addresses 00h 3Fh 08h 14h 20h E2h (EAN.UCC) 006h (NXP) 806h or 906h or B06h (UCODE G2iL) 00000001h to FFFFFFFFh Sub Version Number Version Number 000b or 001b or 0110b 0000110b (UCODE G2iL) Bits 0 3 0 6 0 Addresses 14h 18h 19h 1Fh E2006B06 E2h 006h 1 0110b 0000110b E2006B07 E2h 006h 1 0110b 0000111b SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 13 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.7 Custom commands The UCODE G2iL, G2iL+ is equipped with a number of additional features and custom commands. Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be used to operate the features. The memory map stated in the previous section describes the Configuration Word used to control the additional features located at address 200h of the EPC memory. For this reason the standard READ/WRITE commands of an UHF EPCglobal compliant reader can be used to select the flags or activate/deactivate features. The features can only be activated/deactivated (written) using standard EPC WRITE command as long the EPC is not locked. In case the EPC is locked either the bank needs to be unlocked to apply changes or the ChangeConfig custom command is used to change the settings. The UCODE G2iL is also equipped with the complete UCODE G2X command set for backward compatibility reasons. Nevertheless, the one ChangeConfig command of the G2iL can be used instead of the entire G2X command set. Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable selecting Config-Word enhanced transponders in mixed tag populations. 10.7.1 ChangeConfig Although G2iL is tailored for supply chain management, item level tagging and product authentication the G2iL+ version enables active interaction with products. Among the password protected features are the capability of download firmware to electronics, activate/deactivate electronics which can also be used as theft deterrence, a dedicated privacy mode by reducing the read range, integrated PSF (Product Status Flag) or Tag Tamper Alarm. The G2iL ChangeConfig custom command allows handling the special NXP Semiconductors features described in the following paragraph. Please also see the memory map in Section 10.6 “G2iL, G2iL+ memory” and “Section 10.7.2 “G2iL, G2iL+ special features control mechanism”. If the EPC memory is not write locked the standard EPC READ/WRITE command can be used to change the settings. G2iL, G2iL+ special features1 UCODE G2iL and G2iL+ common special features are: • Bank wise read protection (separate for EPC and TID) EPC bank and the serial number part of the TID can be read protected independently. When protected reading of the particular memory will return '0'. The flags of the configuration word can be selected using the standard SELECT2 command. Only read protected parts will then participate an inventory round. The G2X ReadProtect command will set both EPC and TID read protect flags. 1. The features can only be manipulated (enabled/disabled) with unlocked EPC bank, otherwise the ChangeConfig command can be used. 2. SELECT has to be applied onto the Configuration Word with pointer address 200h. Selecting bits within the Configuration Word using a pointer address not equal to 200h is not possible. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 14 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • Integrated PSF (Product Status Flag) The PSF is a general purpose flag that can be used as an EAS (Electronic Article Surveillance) flag, quality checked flag or similar. The G2iL offers two ways of detecting an activated PSF. In cases extremely fast detection is needed the EAS_Alarm command can be used. The UCODE G2iL will reply a 64-bit alarm code like described in section EAS_Alarm upon sending the command. As a second option the EPC SELECT2 command selecting the PSF flag of the configuration word can be used. In the following inventory round only PSF enabled chips will reply their EPC number. • Backscatter strength reduction The UCODE G2iL features two levels of backscatter strengths. Per default maximum backscatter is enabled in order to enable maximum read rates. When clearing the flag the strength can be reduced if needed. • Real Read Range Reduction 4R Some applications require the reduction of the read range to close proximity for privacy reasons. Setting the 4R flag will significantly reduce the chip sensitivity to +12 dBm. The +12 dBm have to be available at chip start up (slow increase of field strength is not applicable). For additional privacy, the read protection can be activated in the same configuration step. The related flag of the configuration word can be selected using the standard SELECT2 command so only chips with reduced read range will be part of an inventory. Remark: The attenuation will result in only a few centimeter of read range at 36 dBm EIRP! UCODE G2iL+ specific special features are:1 • Tag Tamper Alarm (G2iL+ only) The UCODE G2iL+ Tamper Alarm will flag the status of the VDD to OUT pad connection which can be designed as an predetermined breaking point (see Figure 6). The status of the pad connection (open/closed) can be read in the configuration register and/or selected using the EPC SELECT2. This feature will enable designing a wireless RFID safety seal. When breaking the connection by peeling off the label or manipulating a lock an alarm can be triggered. Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal 001aam228 OUT VDD GND RFP SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 15 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • RF field detection (G2iL+ only) The UCODE G2iL+ VDD pin can be also used as a RF field detector. Upon bringing the tag within an RF field, a pulse signal will be immediately sent from the VDD test pad. (for details see Ref. 21). • Digital Switch (G2iL+ only) The UCODE G2iL+ OUT pin can be used as digital switch. The state of the output pad can be switched to VDD or GND depending on the Digital OUT bit of the Configuration Word register. The state of the output is persistent in the memory even after KILL or switching off the supply. This feature will allow activating/deactivating externally connected peripherals or can be used as theft deterrence of electronics. The state of the OUT pin can also be changed temporary by toggling the 'Invert Digital Output' bit. • Data transfer Mode (G2iL+ only) In applications where not switching the output like described in "Digital Switch" but external device communication is needed the G2iL+ Data Transfer Mode can be used by setting the according bit of the Configuration Word register. When activated the air interface communication will be directly transferred to the OUT pad of the chip. Two modes of data transfer are available and can be switched using the Transparent Mode DATA/RAW bit. The default Transparent Mode DATA will remove the Frame Sync of the communication and toggle the output with every raising edge in the RF field. This will allow implementing a Manchester type of data transmission. The Transparent Mode RAW will switch the demodulated air interface communication to the OUT pad. • External Supply Indicator - Digital Input (G2iL+ only) The VDD pad of the UCODE G2iL+ can be used as a single bit digital input pin. The state of the pad is directly associated with the External Supply Indicator bit of the configuration register. Simple one bit return signaling (chip to reader) can be implemented by polling this Configuration Word register flag. RF reset is necessary for proper polling. • External Supply Mode (G2iL+ only) The UCODE G2iL+ can be supplied externally by connecting 1.85 V (Iout = 0μA) supply. When externally supplied less energy from the RF field is needed to operate the chip. This will not just enable further improved sensitivity and read ranges (up to 27 dBm) but also enable a write range that is equal to the read range. The figure schematically shows the supply connected to the UCODE G2iL+. Remark: When permanently externally supplied there will not be a power-on-reset. This will result in the following limitations: • When externally supplied session flag S0 will keep it’s state during RF-OFF phase. • When externally supplied session flag S2, S3, SL will have infinite persistence time and will behave similar to S0. • Session flag S1 will behave regular like in pure passive operation. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 16 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The bits to be toggled in the configuration register need to be set to '1'. E.g. sending 0000 0000 0001 0001 XOR RN16 will activate the 4R and PSF. Sending the very same command a second time will disable the features again. The reply of the ChangeConfig will return the current register setting. Fig 7. Schematic of external power supply Table 9. ChangeConfig custom command Command RFU Data RN CRC-16 No. of bits 16 8 16 16 16 Description 11100000 00000111 00000000 Toggle bits XOR RN 16 handle - Table 10. ChangeConfig custom command reply Header Status bits RN CRC-16 No. of bits 1 16 16 16 Description 0 Config-Word Handle - Table 11. ChangeConfig command-response table Starting state Condition Response Next state ready all - ready arbitrate, reply, acknowledged all - arbitrate open valid handle Status word needs to change Backscatter unchanged Config-WordConfig-Word immediately open valid handle Status word does not need to change Backscatter Config-Word immediately open secured valid handle Status word needs to change Backscatter modified Config-Word, when done secured valid handle Status word does not need to change Backscatter Config-Word immediately secured killed all - killed 001aam229 OUT VDD Vsupply GND RFP SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 17 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The features can only be activated/deactivated using standard EPC WRITE if the EPC bank is unlocked. The permanent and temporary bits of the Configuration Word can be toggled without the need for an ACCESS password in case the ACCESS password is set to zero. In case the EPC bank is locked the lock needs to be removed before applying changes or the ChangeConfig command has to be used. 10.7.2 G2iL, G2iL+ special features control mechanism Special features of the G2iL are managed using a configuration word (Config-Word) located at address 200h in the EPC memory bank. The entire Config-Word is selectable (using the standard EPC SELECT2 command) and can be read using standard EPC READ command and modified using the standard EPC WRITE or ChangeConfig custom command in case the EPC memory is locked for writing. ChangeConfig can be executed from the OPEN and SECURED state. The chip will take all “Toggle Bits” for ’0’ if the chip is in the OPEN state or the ACCESS password is zero; therefore it will not alter any status bits, but report the current status only. The command will be ignored with an invalid CRC-16 or an invalid handle. The chip will then remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A ChangeConfig command without frame-sync and proceeding Req_RN will be ignored. The command will also be ignored if any of the RFU bits are toggled. In order to change the configuration, to activate/deactivate a feature a ’1’ has to be written to the corresponding register flag to toggle the status. E.g. sending 0x0002 to the register will activate the read protection of the TID. Sending the same command a second time will again clear the read protection of the TID. Invalid toggling on indicator or RFU bits are ignored. Executing the command with zero as payload or in the OPEN state will return the current register settings. The chip will reply to a successful ChangeConfig with an extended preamble regardless of the TRext value of the Query command. After sending a ChangeConfig an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeConfig command and the chip’s backscattered reply. An interrogator may observe three possible responses after sending a ChangeConfig, depending on the success or failure of the operation • ChangeConfigChangeConfig succeeded: The chip will backscatter the reply shown above comprising a header (a 0-bit), the current Status Word setting, the handle, and a CRC-16 calculated over the 0-bit, the status word and the handle. If the interrogator observes this reply within 20 ms then the ChangeConfig completed successfully. • The chip encounters an error: The chip will backscatter an error code during the CW period rather than the reply shown below (see EPCglobal Spec for error-code definitions and for the reply format). • ChangeConfig does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeStatus did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the chip is still in the interrogator's field, and may reissue the ChangeConfig command. The G2iL configuration word is located at address 200h of the EPC memory and is structured as following: SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 18 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The configuration word contains three different type of bits: • Indicator bits cannot be changed by command: Tag Tamper Alarm Indicator External Supply Indicator (digital input) • Temporary bits are reset at power up: Invert Output Transparent Mode on/off Data Mode data/raw • Permanent bits: permanently stored bits in the memory Max. Backscatter Strength Digital Output Read Range Reduction Read Protect EPC Read Protect TID PSF Alarm 10.7.3 ReadProtect3 The G2iL ReadProtect custom command enables reliable read protection of the entire G2iL memory. Executing ReadProtect from the Secured state will set the ProtectEPC and ProtectTID bits of the Configuration Word to '1'. With the ReadProtect-Bit set the G2iL will continue to work unaffected but veil its protected content. The read protection can be removed by executing Reset ReadProtect. The ReadProtect-Bits will than be cleared. Devices whose access password is zero will ignore the command. A frame-sync must be pre-pended the command. After sending the ReadProtect command an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect command and the backscattered reply. An interrogator may observe three possible responses after sending a ReadProtect, depending on the success or failure of the operation: Table 12. Address 200h to 207h Indicator bits Temporary bits Tamper indicator External supply indicator RFU RFU Invert Output Transparent mode on/off Data mode data/raw RFU 0 1 2 3 4 5 6 7 Table 13. Address 208h to 20Fh Permanent bits RFU max. backscatter strength Digital output Privacy mode RFU Protect EPC Protect TID PSF Alarm bit 8 9 10 11 12 13 14 15 3. Note: The ChangeConfig command can be used instead of “ReadProtect”, “ResetReadProtect”, “ChangeEAS”. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 19 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • ReadProtect succeeds: After completing the ReadProtect the G2iL shall backscatter the reply shown in Table 15 comprising a header (a 0-bit), the tag's handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this reply the G2iL will render itself to this ReadProtect mode. If the interrogator observes this reply within 20 ms then the ReadProtect completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code definitions and for the reply format). • ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogation zone, and may re-initiate the ReadProtect command. The G2iL reply to the ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. 10.7.4 Reset ReadProtect3 Reset ReadProtect allows an interrogator to clear the ProtectEPC and ProtectTID bits of the Configuration Word. This will re-enable reading of the related G2iL memory content. For details on the command response please refer to Table 17 “Reset ReadProtect command”. Table 14. ReadProtect command Command RN CRC-16 # of bits 16 16 16 description 11100000 00000001 handle - Table 15. G2iL reply to a successful ReadProtect procedure Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 16. ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all - open secured valid handle & invalid access password – arbitrate valid handle & valid non zero access password Backscatter handle, when done secured invalid handle – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 20 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect command and the G2iL backscattered reply. A Req_RN command prior to the Reset ReadProtect is necessary to successfully execute the command. A frame-sync must be pre-pended the command. An interrogator may observe three possible responses after sending a Reset ReadProtect, depending on the success or failure of the operation: • Reset ReadProtect succeeds: After completing the Reset ReadProtect a G2iL will backscatter the reply shown in Table 18 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the Reset ReadProtect completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in Table 18 (see EPCglobal Spec for error-code definitions and for the reply format). • Reset ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the Reset ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogation zone, and may reissue the Reset ReadProtect command. The G2iL reply to the Reset ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a G2iL will reply as if TRext=1 regardless of the TRext value in the Query that initiated the round. The Reset ReadProtect command is structured as following: • 16 bit command • Password: 32 bit Access-Password XOR with 2 times current RN16 Remark: To generate the 32 bit password the 16 bit RN16 is duplicated and used two times to generate the 32 bit (e.g. a RN16 of 1234 will result in 1234 1234). • 16 bit handle • CRC-16 calculate over the first command-code bit to the last handle bit Table 17. Reset ReadProtect command Command Password RN CRC-16 # of bits 16 32 16 16 description 11100000 00000010 (access password)  2*RN16 handle - Table 18. G2iL reply to a successful Reset ReadProtect command Header RN CRC-16 # of bits 1 16 16 description 0 handle - SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 21 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 10.7.5 ChangeEAS3 UCODE G2iL equipped RFID tags will also feature a stand-alone operating EAS alarm mechanism for fast and offline electronic article surveillance. The PSF bit of the Configuration Word directly relates to the EAS Alarm feature. With an PSF bit set to '1' the tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the need of a Select or Query. The EAS is a built-in solution so no connection to a backend database is required. In case the EAS_Alarm command is not implemented in the reader a standard EPC SELCET to the Configuration Word and Query can be used. When using standard SELECT/QUERY the EPC will be returned during inventory. ChangeEAS can be executed from the Secured state only. The command will be ignored if the Access Password is zero, the command will also be ignored with an invalid CRC-16 or an invalid handle, the G2iL will than remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A frame-sync must be pre-pended the command. The G2iL reply to a successful ChangeEAS will use the extended preamble, as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeEAS command and the G2iL backscattered reply. An interrogator may observe three possible responses after sending a ChangeEAS, depending on the success or failure of the operation • ChangeEAS succeeds: After completing the ChangeEAS a G2iL will backscatter the reply shown in Table 21 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the ChangeEAS completed successfully. • The G2iL encounters an error: The G2iL will backscatter an error code during the CW period rather than the reply shown in Table 21 (see EPCglobal Spec for error-code definitions and for the reply format). Table 19. Reset ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open valid handle & valid access password Backscatter handle, when done open valid handle & invalid access password – arbitrate invalid handle – open secured valid handle & valid access password Backscatter handle, when done secured valid handle & invalid access password – arbitrate invalid handle – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 22 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ • ChangeEAS does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeEAS did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2iL is still in the interrogator's field, and may reissue the ChangeEAS command. Upon receiving a valid ChangeEAS command a G2iL will perform the commanded set/reset operation of the PSF bit of the Configuration Word. If PSF bit is set, the EAS_Alarm command will be available after the next power up and reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be ignored. 10.7.6 EAS_Alarm Upon receiving an EAS_Alarm custom command the UCODE G2iL will immediately backscatter an EAS-Alarmcode in case the PSF bit of the Configuration Word is set. The alarm code is returned without any delay caused by Select, Query and without the need for a backend database. The EAS feature of the G2iL is available after enabling it by sending a ChangeEAS command described in Section 10.7.5 “ChangeEAS3” or after setting the PSF bit of the Configuration Word to ’1’. With the EAS-Alarm enabled the G2iL will reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A G2iL will reply to an EAS_Alarm command from the ready state only. As an alternative to the fast EAS_Alarm command a standard SELECT2 (upon the Configuration Word) and QUERY can be used. If the PSF bit is reset to '0' by sending a ChangeEAS command in the password protected Secure state or clearing the PSF bit the G2iL will not reply to an EAS_Alarm command. Table 20. ChangeEAS command Command ChangeEAS RN CRC-16 # of bits 16 1 16 16 description 11100000 00000011 1 ... set PSF bit 0 ... reset PSF bit handle Table 21. G2iL reply to a successful ChangeEAS command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 22. ChangeEAS command-response table Starting State Condition Response Next state ready all – ready arbitrate, reply, acknowledged all – arbitrate open all – open secured valid handle backscatter handle, when done secured invalid handle – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 23 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ The EAS_Alarm command is structured as following: • 16 bit command • 16 bit inverted command • DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec. 6.3.1.2.8 and Table 6.9. • M (cycles per symbol) sets the T=>R data rate and modulation format as shown in EPCglobal Spec. Table 6.10. • TRext chooses whether the T=>R preamble is pre-pended with a pilot tone as described in EPCglobal Spec. 6.3.1.3. A preamble must be pre-pended the EAS_Alarm command according EPCglobal Spec, 6.3.1.2.8. Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate the CRC5 over the backscattered 64 bits received to verify the received code. Table 23. EAS_Alarm command Command Inv_Command DR M TRext CRC-16 # of bits 16 16 1 2 1 16 description 11100000 00000100 00011111 11111011 0: DR = 8 1: DR = 64/3 00: M = 1 01: M = 2 10: M = 4 11: M = 8 0: no pilot tone 1: use pilot tone - Table 24. G2iL reply to a successful EAS_Alarm command Header EAS Code # of bits 1 64 description 0 CRC5 (MSB) Table 25. EAS_Alarm command-response table Starting State Condition Response Next state ready PSF bit is set PSF bit is cleard backscatter alarm code -- ready arbitrate, reply, acknowledged all – arbitrate open all – open secured all – secured killed all – killed SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 24 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 11. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP20 package. Table 26. Limiting values[1][2] In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to RFN Symbol Parameter Conditions Min Max Unit Bare die and SOT886 limitations Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage Human body model [3] - 2 kV Pad limitations Vi input voltage absolute limits, VDD-OUT pad 0.5 +2.5 V Io output current absolute limits input/output current, VDD-OUT pad 0.5 +0.5 mA Pi input power maximum power dissipation, RFP pad - 100 mW SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 25 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 12. Characteristics 12.1 UCODE G2iL, G2iL+ bare die characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. [4] It has to be assured the reader (system) is capable of providing enough field strength to give +12 dBm at the chip otherwise communication with the chip will not be possible. [5] Enables tag designs to be within ETSI limits for return link data rates of e.g. 320 kHz/M4. [6] Will result in up to 10 dB higher tag backscatter power at high field strength. [7] Results in approx. 18.5 dBm tag sensitivity on a 2 dBi gain antenna. Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit fi input frequency 840 - 960 MHz Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2][7] - 18 - dBm Pi(min) minimum input power WRITE sensitivity, (write range/read range - ratio) - 30 - % Ci input capacitance parallel [3] - 0.77 - pF Q quality factor 915 MHz [3] - 9.7 - - Z impedance 866 MHz [3] - 25 -j237 -  915 MHz [3] - 23 -j224 -  953 MHz [3] - 21 -j216 -  External supply mode - VDD pad supplied, read range reduction OFF Pi(min) minimum input power Ext. supplied READ [1][2] - 27 - dBm Ext. supplied WRITE [2] - 27 - dBm Z impedance externally supplied, 915 MHz [3] - 7 -j230 -  Read range reduction ON - no external supply Pi(min) minimum input power 4R on READ [1][2][4] - +12 - dBm 4R on WRITE [2][4] - +12 - dBm Z impedance 4R on, 915 MHz [3] - 18 -j2 -  Modulation resistance R resistance modulation resistance, max. backscatter = off [5] - 170 -  modulation resistance, max. backscatter = on [6] - 55 -  SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 26 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [1] Activates Digital Output (OUT pin), increases read range (external supplied). [2] Activates Digital Output (OUT pin), increases read and write range (external supplied). [3] Operating the chip outside the specified voltage range may lead to undefined behaviour. [4] Either the voltage or the current needs to be above given values to guarantee specified functionality. [5] No proper operation is guaranteed if both, voltage and current, limits are exceeded. [1] Is the sum of the allowed capacitance of the VDD and OUT pin referenced to RFN. [2] Is the maximum allowed RF input voltage coupling to the VDD/OUT pin to guarantee undisturbed chip functionality. [3] Resistance between VDD and OUT pin in checked during power up only. [4] Resistance range to achieve tamper alarm flag = 1. [5] Resistance range to achieve tamper alarm flag = 0: Table 28. VDD pin characteristics Symbol Parameter Conditions Min Typ Max Unit Minimum supply voltage/current - without assisted EEPROM WRITE [1][3][4] VDD supply voltage minimum voltage - - 1.8 V IDD supply current minimum current, Iout-^- = 0 A - - 7 A Iout = 100 A - - 110 A Minimum supply voltage/current - assisted EEPROM READ and WRITE [2][3][4] VDD supply voltage minimum voltage, Iout = 0 A - 1.8 1.85 V Iout = 100 A - - 1.95 V IDD supply current minimum current, Iout = 0 A - - 125 A Iout = 100 A - - 265 A Maximum supply voltage/current [3][5] VDD supply voltage absolute maximum voltage 2.2 - - V Ii(max) maximum input current absolute maximum current 280 - - A Table 29. G2iL, G2iL+ VDD and OUT pin characteristics Symbol Parameter Conditions Min Typ Max Unit OUT pin characteristics VOL Low-level output voltage Isink = 1 mA - - 100 mV VOH HIGH-level output voltage VDD = 1.8 V; Isource = 100 μA 1.5 - - V VDD/OUT pin characteristics CL load capacitance VDD - OUT pin max. [1] - - 5 pF Vo output voltage maximum RF peak voltage on VDD-OUT pins [2] - - 500 mV VDD/OUT pin tamper alarm characteristics [3] RL(max) maximum load resistance resistance range high [4] - - <2 M RL(min) minimum load resistance resistance range low [5] >20 - - M SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 27 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ For further reading we recommend application note “FAQ UCODE G2iL+“ (Ref. 21) describing the output characteristics more in detail. An example schematic is available in application note “UCODE G2iL+ Demo board Manual“ (Ref. 22). The documents are available at NXP Document Control or at the website www.nxp.com. [1] Tamb 25 C 12.2 UCODE G2iL SOT886 characteristics [1] Power to process a Query command. [2] Measured with a 50  source impedance. [3] At minimum operating power. Remark: For DC and memory characteristics refer to Table 28, Table 29 and Table 30. Table 30. G2iL, G2iL+ memory characteristics Symbol Parameter Conditions Min Typ Max Unit EEPROM characteristics tret retention time Tamb 55 C 20 - - year Nendu(W) write endurance 1000 10000[1] - cycle Table 31. G2iL RF interface characteristics (RFN, RFP) Symbol Parameter Conditions Min Typ Max Unit Normal mode - no external supply, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 17.6 - dB m Z impedance 915 MHz [3] - 21 j199 -  Normal mode - externally supplied, read range reduction OFF Pi(min) minimum input power READ sensitivity [1][2] - 27 - dB m Z impedance 915 MHz [3] - 5.6 j204 -  SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 28 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 13. Package outline Fig 8. Package outline SOT886 Outline References version European projection Issue date IEC JEDEC JEITA SOT886 MO-252 sot886_po 04-07-22 12-01-05 Unit mm max nom min 0.5 0.04 1.50 1.45 1.40 1.05 1.00 0.95 0.35 0.30 0.27 0.40 0.35 0.32 0.6 A(1) Dimensions (mm are the original dimensions) Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 A1 b 0.25 0.20 0.17 D E e e1 0.5 L L1 terminal 1 index area D E e1 e A1 b L1 L e1 0 1 2 mm scale 1 6 2 5 3 4 6x (2) 4x (2) A SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 29 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 14. Packing information 14.1 Wafer See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**” 14.2 SOT886 Part orientation T1. For details please refer to http://www.standardics.nxp.com/packaging/packing/pdf/sot886.t1.t4.pdf 15. Abbreviations Table 32. Abbreviations Acronym Description CRC Cyclic Redundancy Check CW Continuous Wave DSB-ASK Double Side Band-Amplitude Shift Keying DC Direct Current EAS Electronic Article Surveillance EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bi phase space modulation G2 Generation 2 IC Integrated Circuit PIE Pulse Interval Encoding RRRR Real Read Range Reduction PSF Product Status Flag RF Radio Frequency UHF Ultra High Frequency SECS Semi Equipment Communication Standard TID Tag IDentifier SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 30 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 16. References [1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0 (December 17, 2005) [2] EPCglobal: EPC Tag Data Standards [3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft) [4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference (draft) [5] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 1 – Technical characteristics and test methods [6] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive [7] [CEPT1]: CEPT REC 70-03 Annex 1 [8] [ETSI1]: ETSI EN 330 220-1, 2 [9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1: Technical characteristics and test methods. [10] [FCC1]: FCC 47 Part 15 Section 247 [11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International Standards [12] ISO/IEC 3309: Information technology – Telecommunications and information exchange between systems – High-level data link control (HDLC) procedures – Frame structure [13] ISO/IEC 15961: Information technology, Automatic identification and data capture – Radio frequency identification (RFID) for item management – Data protocol: application interface [14] ISO/IEC 15962: Information technology, Automatic identification and data capture techniques – Radio frequency identification (RFID) for item management – Data protocol: data encoding rules and logical memory functions [15] ISO/IEC 15963: Information technology — Radio frequency identification for item management — Unique identification for RF tags [16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item management — Part 1: Reference architecture and definition of parameters to be standardized [17] ISO/IEC 18000-6: Information technology automatic identification and data capture techniques — Radio frequency identification for item management air interface — Part 6: Parameters for air interface communications at 860–960 MHz [18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary – Part 3: radio-frequency identification (RFID) SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 31 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ [19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15: Radio-frequency devices, U.S. Federal Communications Commission. [20] Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BU-ID document number: 1093**4 [21] Application note - FAQ UCODE G2i, BU-ID document number: AN10940 [22] Application note - UCODE G2iM+ demo board documentation, BU-ID document number: AN11237 4. ** ... document version number SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 32 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 17. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3S1203_1213 v.4.4 20140317 Product data sheet - SL3S1203_1213 v.4.3 Modifications: • Table 8 “G2iL, G2iL+ overall memory map”: Table notes updated • Figure 5 “G2iL TID memory structure”: TIDs updated SL3S1203_1213 v.4.3 20131127 Product data sheet - SL3S1203_1213 v.4.2 Modifications: • Figure 5 “G2iL TID memory structure”: updated SL3S1203_1213 v.4.2 20130701 Product data sheet - SL3S1203_1213 v.4.1 Modifications: • Update of delivery form • Update RF field detection SL3S1203_1213 v.4.1 20120917 Product data sheet - SL3S1203_1213 v.4.0 Modifications: • Update of delivery form SL3S1203_1213 v.4.0 20120227 Product data sheet - SL3S1203_1213 v.3.9 Modifications: • Figure 4 “G2iL wafer layout”: Figure notes (1) and (2) updated SL3S1203_1213 v.3.9 20120130 Product data sheet - SL3S1203_1213 v.3.8 Modifications: • Table 6 “Specifications”: “Passivation on front” updated • Section 15.2.1 “General assembly recommendations”: updated SL3S1203_1213 v.3.8 20120111 Product data sheet - SL3S1203_1213 v.3.7 Modifications: • Section 8.1 “Wafer layout”: Figure notes (1) and (2) updated SL3S1203_1213 v.3.7 20111124 Product data sheet - SL3S1203_1213 v.3.6 Modifications: • Table 11 “G2iL, G2iL+ overall memory map”: updated • Table 34 “G2iL, G2iL+ RF interface characteristics (RFN, RFP)”: updated SL3S1203_1213 v.3.6 20110803 Product data sheet - SL3S1203_1213 v.3.5 Modifications: • Real Read Range Reduction feature added to G2iL SL3S1203_1213 v.3.5 20110531 Product data sheet - SL3S1203_1213 v.3.4 Modifications: • Superfluous text removed from Table 6 SL3S1203_1213 v.3.4 20110511 Product data sheet - SL3S1203_1213 v.3.3 Modifications: • Security status changed into COMPANY PUBLIC • Delivery form of FCS2 strap added • Section 13 “Package information”, Section 15 “Handling information” and Section 16 “Packing information” added SL3S1203_1213 v.3.3 20110131 Product data sheet - SL3S1203_1213 v.3.2 Modifications: • Section 4 “Ordering information”: new types SL3S1203FUD and SL3S1213FUD added • Section 9 “Mechanical specification”: updated according to the new types • Replaced wording of “ChangeStatus” with “ChangeConfig” SL3S1203_1213 v.3.2 20101109 Product data sheet - SL3S1203_1213 v.3.1 Modifications: • Version SOT886F1 added • Section 5 “Marking”, Section 13 “Package outline” and Section 14 “Packing information” added SL3S1203_1213 v.3.1 20100922 Product data sheet - SL3S1203_1213 v.3.0 Modifications: • General Modifications SL3S1203_1213 v.3.0 20100621 Product data sheet - 178810 SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 33 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ Modifications: • General update 178810 20100304 Objective data sheet - - Table 33. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 34 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 35 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 4.4 — 17 March 2014 178844 36 of 37 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ 20. Tables Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .3 Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description bare die . . . . . . . . . . . . . . . . . . .5 Table 4. Pin description SOT886 . . . . . . . . . . . . . . . . . . .5 Table 5. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 6. Overview of G2iL and G2iL+ features . . . . . . . .9 Table 7. G2iL memory sections . . . . . . . . . . . . . . . . . . .10 Table 8. G2iL, G2iL+ overall memory map. . . . . . . . . . . 11 Table 9. ChangeConfig custom command . . . . . . . . . . .16 Table 10. ChangeConfig custom command reply. . . . . . .16 Table 11. ChangeConfig command-response table . . . . .16 Table 12. Address 200h to 207h . . . . . . . . . . . . . . . . . . .18 Table 13. Address 208h to 20Fh . . . . . . . . . . . . . . . . . . .18 Table 14. ReadProtect command. . . . . . . . . . . . . . . . . . .19 Table 15. G2iL reply to a successful ReadProtect procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 16. ReadProtect command-response table . . . . . .19 Table 17. Reset ReadProtect command . . . . . . . . . . . . .20 Table 18. G2iL reply to a successful Reset ReadProtect command. . . . . . . . . . . . . . . . . . .20 Table 19. Reset ReadProtect command-response table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 20. ChangeEAS command . . . . . . . . . . . . . . . . . . 22 Table 21. G2iL reply to a successful ChangeEAS command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 22. ChangeEAS command-response table . . . . . . 22 Table 23. EAS_Alarm command . . . . . . . . . . . . . . . . . . . 23 Table 24. G2iL reply to a successful EAS_Alarm c ommand. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 25. EAS_Alarm command-response table . . . . . . 23 Table 26. Limiting values[1][2] . . . . . . . . . . . . . . . . . . . . . . 24 Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 28. VDD pin characteristics . . . . . . . . . . . . . . . . . . 26 Table 29. G2iL, G2iL+ VDD and OUT pin characteristics . . . . . . . . . . . . . . . . . . . . . . 26 Table 30. G2iL, G2iL+ memory characteristics . . . . . . . . 27 Table 31. G2iL RF interface characteristics (RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 33. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32 21. Figures Fig 1. Block diagram of G2iL IC . . . . . . . . . . . . . . . . . . .4 Fig 2. Pinning bare die. . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. Pin configuration for SOT886 . . . . . . . . . . . . . . . .5 Fig 4. G2iL wafer layout. . . . . . . . . . . . . . . . . . . . . . . . . .6 Fig 5. G2iL TID memory structure . . . . . . . . . . . . . . . . .12 Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point to turn a standard RFID label into a wireless safety seal . .14 Fig 7. Schematic of external power supply . . . . . . . . . .16 Fig 8. Package outline SOT886. . . . . . . . . . . . . . . . . . .28 NXP Semiconductors SL3S1203_1213 UCODE G2iL and G2iL+ © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 March 2014 178844 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1.1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.1 End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2.2 Antenna design benefits . . . . . . . . . . . . . . . . . . 2 2.2.3 Label manufacturer benefit. . . . . . . . . . . . . . . . 2 2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Mechanical specification . . . . . . . . . . . . . . . . . 7 9.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 Fail die identification . . . . . . . . . . . . . . . . . . . . 8 9.1.3 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 8 10 Functional description . . . . . . . . . . . . . . . . . . . 8 10.1 Air interface standards . . . . . . . . . . . . . . . . . . . 8 10.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 8 10.3 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10.3.1 Reader to tag Link . . . . . . . . . . . . . . . . . . . . . . 9 10.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . . 9 10.4 G2iL and G2iL+ differences . . . . . . . . . . . . . . . 9 10.5 Supported commands . . . . . . . . . . . . . . . . . . 10 10.6 G2iL, G2iL+ memory . . . . . . . . . . . . . . . . . . . 10 10.6.1 G2iL, G2iL+ overall memory map. . . . . . . . . . 11 10.6.2 G2iL TID memory details . . . . . . . . . . . . . . . . 12 10.7 Custom commands. . . . . . . . . . . . . . . . . . . . . 13 10.7.1 ChangeConfig. . . . . . . . . . . . . . . . . . . . . . . . . 13 G2iL, G2iL+ special features . . . . . . . . . . . . . .13 10.7.2 G2iL, G2iL+ special features control mechanism . . . . . . . . . . . . . . . . . . . . . 17 10.7.3 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.7.4 Reset ReadProtect3 . . . . . . . . . . . . . . . . . . . . 19 10.7.5 ChangeEAS3 . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.7.6 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 12.1 UCODE G2iL, G2iL+ bare die characteristics 25 12.2 UCODE G2iL SOT886 characteristics . . . . . . 27 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 28 14 Packing information . . . . . . . . . . . . . . . . . . . . 29 14.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.2 SOT886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 34 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34 18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 19 Contact information . . . . . . . . . . . . . . . . . . . . 35 20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 Specification Issue 1 26/6/2012 SERIAL TFT MODULE APPLICATION NOTE 1 Compiling and transferring image files via the USB interface. Date Description of change 26/6/12 Initial creation 2 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 Overview The Midas range of serial TFT modules offer the ability to store images which are then selected for display using serial commands. This overcomes the need to transfer large amounts of data over the serial interface. The following application note describes how to prepare image files and transfer them to the display module flash memory drive via the USB interface. Requirements Midas Serial TFT display module. USB cable type A to mini B. BmpToBin application software (available from Midas). Procedure 1) Create two directories one called BMP_DATA and the other BMP_FILE . 2) Place all the bitmap files you require for your project in the BMP_FILE directory. Note that the files must be 24-bit bitmap type. Note that the size of the combined images must not be greater than 2M bytes. This is the sum of x*y*2 for each image. Ie. For the above (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (240*320*2)+ (1315*32*2)=1159360 3 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 3) Re-name each image numerically in the sequence required bearing in mind that any short animation sequences need to be in sequential order. i.e: 4) Exit this directory and place the BmpToBin application file in the parent directory i.e 5) Run the BmpToBinForM.exe application by double clicking the icon. This will then create two files within the BMP_DATA directory. 6) Plug the TFT module into your PC using a USB A to mini B cable. The module should then appear on your PC as a flash memory device. 4 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 7) Simply Copy the two files BMPDATA.BIN and TABLE.BIN created earlier to the module flash drive. These images are then available to be displayed via serial command. If there are already files on the module flash drive you may want to back them up to your PC. You can now via the serial interface view the images on the display module using commands such as: Browse Pictures, Cut a Picture, Animation, Call on PIC and Run Demo. Command Summary Commands are sent to the board via the Serial UART (TTL levels) on J1. The default serial format is 9600,N,8,1. All commands are ASCII characters followed by CR LF (0D0A hex). Function Command Format Example Busy Low time Browse Pictures ALL “ALL\n” - Draw a circle CIRCLE Xa Ya R C “CIRCLE 100 100 50 31\n” 4ms Fill in colour CLR Xa Ya Xe Ye C “CLR 0 0 100 100 31\n” 5ms Clear Screen CLS C “CLS 31\n” 28ms Cut a picture CUT Pn Xa Ya Xb Yb Xs Ys “CUT 1 30 30 0 0 100 100 \n” 20ms Draw a dot DOT Xa Ya C “DOT 100 100 31\n” 0.12ms Draw a frame with line type and chamfer FRAME Xa Ya Xe Ye Ds Do C “FRAME 10 10 200 40 2 3 31\n” 4ms Draw a line LINE Xa Ya Xe Ye C “LINE 10 10 50 50 31\n” 0.7ms Backlight on LEDON “LEDON\n” 4us Backlight off LEDOFF “LEDOFF\n” 4us Animation MOT Xa Ya Ps Pe Pt “MOT 0 0 10 14 100\n” 0.15ms Animation off MOFF “MOFF\n” 4us Call on PIC PIC Pn Xa Ya “PIC 1 30 30\n” 125ms Draw a rectangle RECT Xa Ya Xe Ye C “RECT 10 10 100 100 31\n” 5ms Get screen size * SIZE “SIZE\n” 13ms Display alphabetic string STR Xa Ya C Str “STR 0 0 31 Hello World\n” 0.8ms / char Display alphabetic string with background colour STR Xa Ya C Cb Str “STR 0 20 65535 31 Hello World\n” 30us / char Set baud rate BAUD b1 b2 “BAUD 9600 9600\n” 20ms Run demo DEMO Dt Xa Ya “DEMO 1000 0 0\n” 20ms Stop demo DMOFF “DMOFF\n” 20ms Change orientation TURN Tn “TURN 90\n” 140ms 5 | P a g e Address: Midas Components Ltd, Electra House, 32 Southtown Road, Great Yarmouth, Norfolk, England, NR31 ODU Email:sales@midascomponents.co.uk Website:www.midascomponents.co.uk Tel:+44(0)1493 602602 Fax:+44(0)1493 665111 Notes: Xa Ya :Start x y coordinates. Xe Ye :End x y coordinates. C :Colour (16 bits,RGB 565). Xb Yb :Start x y coordinates in flash image. Xs yS :Size of flash image block. Ds Do :Length of solid line / dotted line. Str :ASCII String (8x16). Pn :Picture number in flash 000-999. R :Radius in pixels. Ps :Start Picture number. Pe :End picture number. Pt :Time between pictures (step:100ms). * :Returned on RX “STY Xsize Ysize\n” b1 b2 :Baud rate (2400,4800,9600,19200,38400,56000,57600,115200) Dt :Time between pictures (step:100ms). Tn :Rotation angle (0,90) Notes: Anti-static precautions should be observed whilst handling this product. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MIDAS MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Midas disclaims all liability arising from this information and its use. Use of Midas’s products as critical components in life support systems is not authorized except with express written approval by Midas. No licenses are conveyed, implicitly or otherwise, under any Midas intellectual property rights. A Premier Farnell Company MIDAS un traitement complet du signal Bien que les algorithmes de traitement complexes rendent cela possible, ils sont en général exécutés plus vite et de manière plus économique dans un système numérique. Le monde réel ne suit pas l’évolution informatique définie par la Loi de Moore, et le désir humain d’aller toujours plus vite et à moindre coût, incite résolument à rester en analogique. En conséquence, les ingénieurs doivent continuer à relever des défis relatifs à la détection précise de signaux dans l’univers analogique et les restituer le plus fidèlement possible dans un format numérique. Alchimie analogique La conception analogique a longtemps été considérée comme un art ésotérique, exigeant une connaissance pointue et une intuition pour garantir la stabilité du système, optimiser le gain et la réponse en fréquence, traiter les problèmes de mise à la masse, gérer les impédances et leur comparaison, ainsi que minimiser les effets de bruit. Parallèlement, la pression augmente pour satisfaire aux exigences rigoureuses en matière de coût, commercialisation et capacité de production de masse. La grande majorité des ingénieurs modernes ne peut tout simplement pas s’offrir le luxe d’optimiser individuellement des circuits analogiques. Pour relever ces défis, l’alchimie analogique la plus mystérieuse a tendance désormais à se produire au niveau du silicium ; la technique de dorure est intégrée aux composants qui constituent le traitement du signal. Les produits analogiques les plus récents visent maintenant à « pré résoudre » un grand nombre des défis qui occupaient les spécialistes en technique analogique. Ils sont plus riches en fonctionnalités et moins sensibles aux variables, telles que configuration et longueurs de tracé PCB. Ils sont aussi intrinsèquement moins gourmands en énergie que leurs prédécesseurs. Ainsi, les produits de dernière génération proposés sur le marché des circuits intégrés offrent une conception interne plus simple, nécessitant moins de composants externes et supportant une gestion de l’alimentation au niveau du système. La gamme des produits Farnell En offrant l’un des portefeuilles produits, les plus étendus en technologies de traitement du signal, provenant d’innovateurs influents dans le domaine des produits analogiques de pointe, hautement performants, Farnell est idéalement placé pour aider le concepteur à identifier, sélectionner et évaluer les produits haute performance du marché actuel. Pour faciliter l’évaluation, la sélection et l’intégration de produits de traitement du signal en vue d’atteindre des objectifs de système ambitieux, Farnell a classé les principales technologies en cinq catégories, regroupées sous l’acronyme MIDAS : Mixed-signal, Interface, Data conversion, Amplification, and Sensors (ou signaux mixtes, interface, conversion de données, amplification et capteurs). La catégorie Signaux mixtes comprend des appareils comme les multiplexeurs, les commutateurs analogiques, les filtres, les potentiomètres numériques, les isolateurs, les résistances et les compensateurs. Concernant les produits d’interface, les ingénieurs ont de nombreuses options de connectivité, dont SERDES, transmetteurs LVDS et interfaces Ethernet. Ce groupe englobe également les oscillateurs, les circuits d’horloge et les PLL. La conversion de donnée est la phase du traitement du signal la plus proche du domaine numérique, comprenant diverses classes de convertisseurs N/A et A/N dont des appareils polyvalents à haut débit et de grande précision, selon les spécifications de l’application ou du système. Dans la catégorie Amplificateurs, les ingénieurs ont la possibilité de choisir parmi une gamme extrêmement étendue d’options disponibles, là aussi le choix étant en grande partie déterminé par l’application et les exigences de performance du système. Les amplificateurs proposés par les principaux fournisseurs distribués par Farnell incluent des amplificateurs audio, à détection de courant, différentiels, polyvalents, d’instrumentation, d’isolement, logarithmiques, ‘Médaille d’or’ de la conception analogique avancée Le monde actuel est très dépendant du contrôle et de la régulation d’une grande variété d’effets physiques. Par exemple pour utiliser des ressources énergétiques de manière plus efficace et pour améliorer la qualité de vie, les exemples de produits électroniques utilisés pour atteindre ces objectifs incluent les systèmes de contrôle et de mesure des gaz d’échappement, les scanners médicaux, les instruments de surveillance médicale, la télésurveillance d’état d’un équipement et les systèmes de sécurité sophistiqués. opérationnels, à gain programmable et amplis buffer vidéo, ainsi qu’une gamme étendue de comparateurs et de compresseurs/extenseurs. Enfin, concernant les capteurs appropriés, avec les accéléromètres, capteurs de courant, à effet hall, de pression, de proximité et de température, complétés des quatre autres catégories, les ingénieurs peuvent compléter leur analyse des besoins en traitement du signal pour tout système de contrôle, d’enregistrement ou de régulation. Ceux-ci peuvent élargir les possibilités d’application, allant des systèmes médicaux, automobile aux systèmes industriels, commerciaux et domestiques. En analysant le traitement du signal de cette manière, les ingénieurs peuvent rapidement identifier les éléments nécessaires pour compléter une solution et commencer l’assemblage d’une combinaison optimale. Technologie d’avant-garde, présentée en avant-première Dans le cadre de cette campagne Technology First, nous étudions quelques-unes des dernières innovations et tendances dans chacune des cinq catégories afin identifier comment les caractéristiques et les performances des composants viennent en aide aux défis de la conception analogique, en améliorant le rapport qualité/prix tout en supportant encombrement et consommation énergétique moindres. En conclusion, il est important de noter que Farnell est en mesure de fournir des composants complémentaires pour satisfaire aux exigences de la conception numérique, réaliser un système complet et hautement performant. DATA SHEET Product specification October 1998 DISCRETE SEMICONDUCTORS BYW29EX series Rectifier diodes ultrafast, rugged NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged GENERAL DESCRIPTION QUICK REFERENCE DATA Glass passivated epitaxial rectifier SYMBOL PARAMETER MAX. MAX. UNIT diodes in a full pack plastic envelope, featuring low forward voltage drop, BYW29EX- 150 200 ultra-fast recovery times, soft recovery VRRM Repetitive peak reverse 150 200 V characteristic and guaranteed reverse voltage surge and ESD capability. They are VF Forward voltage 0.895 0.895 V intended for use in switchedmode power IF(AV) Forward current 8 8 A supplies and high frequency circuits in trr Reverse recovery time 25 25 ns general where low conduction and IRRM Repetitive peak reverse 0.2 0.2 A switching losses are essential. current PINNING - SOD113 PIN CONFIGURATION SYMBOL PIN DESCRIPTION 1 cathode 2 anode case isolated LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT -150 -200 VRRM Repetitive peak reverse voltage - 150 200 V VRWM Crest working reverse voltage - 150 200 V VR Continuous reverse voltage - 150 200 V IF(AV) Average forward current1 square wave; d = 0.5; Ths £ 106 °C - 8 A sinusoidal; a = 1.57; Ths £ 109 °C - 7.3 A IF(RMS) RMS forward current - 11.3 A IFRM Repetitive peak forward current t = 25 μs; d = 0.5; - 16 A Ths £ 106 °C IFSM Non-repetitive peak forward t = 10 ms - 80 A current t = 8.3 ms - 88 A sinusoidal; with reapplied VRWM(max) I2t I2t for fusing t = 10 ms - 32 A2s IRRM Repetitive peak reverse current tp = 2 μs; d = 0.001 - 0.2 A IRSM Non-repetitive peak reverse tp = 100 μs - 0.2 A current Tstg Storage temperature -40 150 °C Tj Operating junction temperature - 150 °C 1 2 case k a 1 2 1 Neglecting switching and reverse current losses October 1998 1 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VC Electrostatic discharge Human body model; - 8 kV capacitor voltage C = 250 pF; R = 1.5 kW ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 °C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Visol R.M.S. isolation voltage from f = 50-60 Hz; sinusoidal - 2500 V both terminals to external waveform; heatsink R.H. £ 65% ; clean and dustfree Cisol Capacitance from both terminals f = 1 MHz - 10 - pF to external heatsink THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Rth j-hs Thermal resistance junction to with heatsink compound - - 5.5 K/W heatsink without heatsink compound - - 7.2 K/W Rth j-a Thermal resistance junction to in free air - 55 - K/W ambient STATIC CHARACTERISTICS Tj = 25 °C unless otherwise stated SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VF Forward voltage IF = 8 A; Tj = 150°C - 0.80 0.895 V IF = 8 A - 0.92 1.05 V IF = 20 A - 1.1 1.3 V IR Reverse current VR = VRWM; Tj = 100 °C - 0.2 0.6 mA VR = VRWM - 2 10 μA DYNAMIC CHARACTERISTICS Tj = 25 °C unless otherwise stated SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Qs Reverse recovery charge IF = 2 A; VR ³ 30 V; -dIF/dt = 20 A/μs - 4 11 nC trr1 Reverse recovery time IF = 1 A; VR ³ 30 V; - 20 25 ns -dIF/dt = 100 A/μs trr2 Reverse recovery time IF = 0.5 A to IR = 1 A; Irec = 0.25 A - 15 20 ns Vfr Forward recovery voltage IF = 1 A; dIF/dt = 10 A/μs - 1 - V October 1998 2 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged Fig.1. Definition of trr1, Qs and Irrm Fig.2. Definition of Vfr Fig.3. Circuit schematic for trr2 Fig.4. Definition of trr2 Fig.5. Maximum forward dissipation PF = f(IF(AV)); square current waveform where IF(AV) =IF(RMS) x ÖD. Fig.6. Maximum forward dissipation PF = f(IF(AV)); sinusoidal current waveform where a = form factor = IF(RMS) / IF(AV). Q s 10% 100% time dI dt F I R I F I rrm t rr I = 1A R I rec = 0.25A 0A trr2 0.5A IF IR time time V F V fr V F I F 0 2 4 6 8 10 12 0 2 4 6 8 10 12 D = 1.0 0.5 0.2 0.1 BYW29 IF(AV) / A PF / W tp D = tp T T t I Ths(max) / C 150 139 128 117 106 95 84 Vo = 0.791 V Rs = 0.013 ohms shunt Current to ’scope D.U.T. Voltage Pulse Source R 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 a = 1.57 1.9 2.2 2.8 4 BYW29 IF(AV) / A PF / W Ths(max) / C 150 144.5 139 133.5 128 122.5 117 111.5 106 Vo = 0.791 V Rs = 0.013 Ohms October 1998 3 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged Fig.7. Maximum trr at Tj = 25 °C. Fig.8. Maximum Irrm at Tj = 25 °C. Fig.9. Typical and maximum forward characteristic IF = f(VF); parameter Tj Fig.10. Maximum Qs at Tj = 25 °C. Fig.11. Transient thermal impedance; Zth j-hs = f(tp). 1 10 trr / ns 1 10 100 1000 100 dIF/dt (A/us) IF=1A IF=10A 10 1.0 1.0 10 100 -dIF/dt (A/us) Qs / nC IF=10A 5A 2A 1A 100 10 1 0.1 0.01 Irrm / A 1 10 100 -dIF/dt (A/us) IF=1A IF=10A 1us 10us 100us 1ms 10ms 100ms 1s 10s 0.001 0.01 0.1 1 10 pulse width, tp (s) BYW29F/EX Transient thermal impedance, Zth j-hs (K/W) tp D = tp T T P t D 0 1 2 30 20 10 0 typ max IF / A 0.5 1.5 VF / V Tj=150 C Tj=25 C BYW29 October 1998 4 Rev 1.200 NXP Semiconductors Product specification Rectifier diodes BYW29EX series ultrafast, rugged MECHANICAL DATA Dimensions in mm Net Mass: 2 g Fig.12. SOD113; The seating plane is electrically isolated from all terminals. Notes 1. Refer to mounting instructions for F-pack envelopes. 2. Epoxy meets UL94 V0 at 1/8". 10.3 max 3.2 3.0 4.6 max 2.9 max 2.8 seating plane 6.4 15.8 max 0.6 2.5 2.54 5.08 1 2 3 max. not tinned 3 0.5 2.5 0.9 0.7 0.4 M 15.8 max. 19 max. 13.5 min. Recesses (2x) 2.5 0.8 max. depth 1.0 (2x) October 1998 5 Rev 1.200 NXP Semiconductors Legal information DATA SHEET STATUS Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DEFINITIONS Product specification ⎯ The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. DISCLAIMERS Limited warranty and liability ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors Legal information NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products ⎯ Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the content, except for the legal definitions and disclaimers. © NXP B.V. 2011 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands CSM_EE-SPX303N_403N_DS_E_3_2 Broad Slot-type Photomicrosensor EE-SPX303N/403N A Wide Slot Width of 13 mm and Superior Resistance to Light Interference and Noise. • Noise resistance equivalent to photomicrosensors with built-in amplifiers. • Resistance to common noise at least 30 times that of previous models. • Resistance to inverter noise at least 10 times that of previous models. • Reverse polarity protection built in. Be sure to read Safety Precautions on page 3. For the most recent information on models that have been certified for safety standards, refer to your OMRON website. Ordering Information Sensors Accessories (Order Separately) * Refer to Accessories for details. Appearance Sensing method Sensing distance (slot width) Output type Output configuration Model Through-beam type (with slot) NPN output Dark-ON EE-SPX303N Light-ON EE-SPX403N Type Cable length Model Connector EE-1001 EE-1009 Connector with Cable 1 m EE-1006 1M EE-1010 1M 2 m EE-1006 2M EE-1010 2M Connector with Robot Cable 1 m EE-1010-R 1M 2 m EE-1010-R 2M NPN/PNP Conversion Connector 0.46 m (total length) EE-2002 Infrared light 13 mm (slot width) 2 EE-SPX303N/403N Ratings and Specifications Engineering Data (Reference Value) Sensing Position Characteristics EE-SPX303N Item Models EE-SPX303N, EE-SPX403N Sensing distance 13 mm (slot width) Sensing object Opaque: 2.2 × 0.5 mm min. Differential distance 0.05 mm max. Light source Infrared LED (pulse lighting) with a peak wavelength of 940 nm Indicator Light indicator (red) Supply voltage 12 to 24 VDC ±10%, ripple (p-p): 5% max. Current consumption 15 mA max. Control output NPN voltage output: Load power supply voltage: 12 to 24 VDC Load current: 80 mA max. OFF current: 0.5 mA max. 80 mA load current with a residual voltage of 2.0 V max. 10 mA load current with a residual voltage of 1.0 V max. Protection circuits Power supply reverse polarity protection, Output reverse polarity protection Response frequency * 100 Hz min. Ambient illumination 3,000 lx max. with incandescent light or sunlight on the surface of the receiver. Ambient temperature range Operating: −10 to +55°C Storage: −25 to +65°C Ambient humidity range Operating: 5% to 85% Storage: 5% to 95% Vibration resistance Destruction: 10 to 55 Hz, 1.5-mm double amplitude for 2 h each in X, Y, and Z directions Shock resistance Destruction: 500 m/s2 for 3 times each in X, Y, and Z directions Degree of protection IEC IP50 Connecting method Special connector (soldering not possible) Weight Approx. 4 g Material Polycarbonate * The response frequency was measured by detecting the following rotating disk. 2 mm Disk 2 mm 2 mm 0 1 2 3 4 5 6 Distance d (mm) Tr ON Tr OFF Dark-ON d 0 1 2 3 4 5 6 Distance d (mm) Tr ON Tr OFF Dark-ON d EE-SPX303N/403N 3 I/O Circuit Diagrams NPN Output Safety Precautions Refer to Warranty and Limitations of Liability. This product is not designed or rated for ensuring safety of persons either directly or indirectly. Do not use it for such purposes. Make sure that this product is used within the rated ambient environment conditions. ● Wiring • Connection is made using a connector. Do not solder to the pins (leads). The pins (leads) are soldered to the internal board of the Sensor. Therefore, direct soldering of the pins (leads) may result in an internal disconnection causing malfunction. • When extending the cable, use an extension cable with conductors having a total cross-section area of 0.3 mm2. The total cable length must be 2 m maximum. • To use a cable length longer than 2 m, attach a capacitor with a capacitance of approximately 10 μF to the wires as shown below. The distance between the terminal and the capacitor must be within 2 m. (Use a capacitor with a dielectric strength that is at least twice the Sensor's power supply voltage.) • Make sure the total length of the power cable connected to the product is less than 10 m even if a capacitor is inserted. Model Output configuration Timing charts Output circuit EE-SPX403N Light-ON EE-SPX303N Dark-ON Incident Interrupted ON OFF ON OFF Operates Releases H L Light indicator (red) Output transistor Load 1 (relay) Load 2 lC Light indicator (red) 1.5 to 3 mA Load 1 Load 2 Main circuit OUT ∗ * Voltage output (when the sensor is connected to a transistor circuit) 12 to 24 VDC Incident Interrupted ON OFF ON OFF Operates Releases H L Light indicator (red) Output transistor Load 1 (relay) Load 2 WARNING Precautions for Correct Use OUT Extension cable A capacitance of 10 μF min. + − 12 to 24 VDC 0 V 2 m max. 4 EE-SPX303N/403N (Unit: mm) Dimensions Tolerance class IT16 applies to dimensions in this datasheet unless otherwise specified. Sensors Accessories (Order Separately) * Refer to Accessories for details. 7.4 0.3 0.7 13 10 19 3.2 26 26 2-3.7 5.08 13 19.5 2.54 1 2 3 Four, R1.6 Indicator window Sensing window (0.5 × 2.2) EE-SPX303N, EE-SPX403N Terminal Arrangement (1) + Vcc (2) OUT OUTPUT (3) − GND (0 V) Read and Understand This Catalog Please read and understand this catalog before purchasing the products. Please consult your OMRON representative if you have any questions or comments. Warranty and Limitations of Liability WARRANTY OMRON's exclusive warranty is that the products are free from defects in materials and workmanship for a period of one year (or other period if specified) from date of sale by OMRON. OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, REGARDING NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR PARTICULAR PURPOSE OF THE PRODUCTS. ANY BUYER OR USER ACKNOWLEDGES THAT THE BUYER OR USER ALONE HAS DETERMINED THAT THE PRODUCTS WILL SUITABLY MEET THE REQUIREMENTS OF THEIR INTENDED USE. OMRON DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED. LIMITATIONS OF LIABILITY OMRON SHALL NOT BE RESPONSIBLE FOR SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES, LOSS OF PROFITS OR COMMERCIAL LOSS IN ANY WAY CONNECTED WITH THE PRODUCTS, WHETHER SUCH CLAIM IS BASED ON CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT LIABILITY. In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which liability is asserted. IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS REGARDING THE PRODUCTS UNLESS OMRON'S ANALYSIS CONFIRMS THAT THE PRODUCTS WERE PROPERLY HANDLED, STORED, INSTALLED, AND MAINTAINED AND NOT SUBJECT TO CONTAMINATION, ABUSE, MISUSE, OR INAPPROPRIATE MODIFICATION OR REPAIR. Application Considerations SUITABILITY FOR USE OMRON shall not be responsible for conformity with any standards, codes, or regulations that apply to the combination of products in the customer's application or use of the products. At the customer's request, OMRON will provide applicable third party certification documents identifying ratings and limitations of use that apply to the products. This information by itself is not sufficient for a complete determination of the suitability of the products in combination with the end product, machine, system, or other application or use. The following are some examples of applications for which particular attention must be given. This is not intended to be an exhaustive list of all possible uses of the products, nor is it intended to imply that the uses listed may be suitable for the products:  Outdoor use, uses involving potential chemical contamination or electrical interference, or conditions or uses not described in this catalog.  Nuclear energy control systems, combustion systems, railroad systems, aviation systems, medical equipment, amusement machines, vehicles, safety equipment, and installations subject to separate industry or government regulations.  Systems, machines, and equipment that could present a risk to life or property. Please know and observe all prohibitions of use applicable to the products. NEVER USE THE PRODUCTS FOR AN APPLICATION INVOLVING SERIOUS RISK TO LIFE OR PROPERTY WITHOUT ENSURING THAT THE SYSTEM AS AWHOLE HAS BEEN DESIGNED TO ADDRESS THE RISKS, AND THAT THE OMRON PRODUCTS ARE PROPERLY RATED AND INSTALLED FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR SYSTEM. PROGRAMMABLE PRODUCTS OMRON shall not be responsible for the user's programming of a programmable product, or any consequence thereof. Disclaimers CHANGE IN SPECIFICATIONS Product specifications and accessories may be changed at any time based on improvements and other reasons. It is our practice to change model numbers when published ratings or features are changed, or when significant construction changes are made. However, some specifications of the products may be changed without any notice. When in doubt, special model numbers may be assigned to fix or establish key specifications for your application on your request. Please consult with your OMRON representative at any time to confirm actual specifications of purchased products. DIMENSIONS ANDWEIGHTS Dimensions and weights are nominal and are not to be used for manufacturing purposes, even when tolerances are shown. PERFORMANCE DATA Performance data given in this catalog is provided as a guide for the user in determining suitability and does not constitute a warranty. It may represent the result of OMRON’s test conditions, and the users must correlate it to actual application requirements. Actual performance is subject to the OMRON Warranty and Limitations of Liability. ERRORS AND OMISSIONS The information in this document has been carefully checked and is believed to be accurate; however, no responsibility is assumed for clerical, typographical, or proofreading errors, or omissions. 2012.8 In the interest of product improvement, specifications are subject to change without notice. OMRON Corporation Industrial Automation Company http://www.ia.omron.com/ (c)Copyright OMRON Corporation 2012 All Right Reserved. DATA SHEET Product data sheet Supersedes data of 1999 Apr 29 2004 Jan 22 DISCRETE SEMICONDUCTORS PMBTA13; PMBTA14 NPN Darlington transistors 2004 Jan 22 2 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 FEATURES •High current (max. 500 mA) •Low voltage (max. 30 V) •High DC current gain (min. 10000). APPLICATIONS •High input impedance preamplifiers. DESCRIPTION NPN Darlington transistor in a SOT23 plastic package. PNP complement: PMBTA64. MARKING Note 1.* = p : Made in Hong Kong. * = t : Made in Malaysia. * = W : Made in China. PINNING TYPE NUMBER MARKING CODE(1) PMBTA13 *1M PMBTA14 *1N PIN DESCRIPTION 1 base 2 emitter 3 collector Fig.1 Simplified outline (SOT23) and symbol.handbook, halfpageMAM298132132TR2TR1Top view ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION PMBTA13 − plastic surface mounted package; 3 leads SOT23 PMBTA14 2004 Jan 22 3 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). Note 1.Transistor mounted on an FR4 printed-circuit board. THERMAL CHARACTERISTICS Note 1.Transistor mounted on an FR4 printed-circuit board. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCBO collector-base voltage open emitter − 30 V VCES collector-emitter voltage VBE = 0 − 30 V VEBO emitter-base voltage open collector − 10 V IC collector current (DC) − 500 mA ICM peak collector current − 800 mA IB base current (DC) − 200 mA Ptot total power dissipation Tamb ≤ 25 °C; note 1 − 250 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb operating ambient temperature −65 +150 °C SYMBOL PARAMETER CONDITIONS VALUE UNIT Rth(j-a) thermal resistance from junction to ambient note 1 500 K/W SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT ICBO collector cut-off current IE = 0; VCB = 30 V − 100 nA IEBO emitter cut-off current IC = 0; VEB = 10 V − 100 nA hFE DC current gain IC = 10 mA; VCE = 5 V; (see Fig.2) PMBTA13 5000 − PMBTA14 10000 − DC current gain IC = 100 mA; VCE = 5 V; (see Fig.2) PMBTA13 10000 − PMBTA14 20000 − VCEsat collector-emitter saturation voltage IC = 100 mA; IB = 0.1 mA − 1.5 V VBEon base-emitter on-state voltage IC = 100 mA; VCE = 5 V − 1.4 V fT transition frequency IC = 10 mA; VCE = 5 V; f = 100 MHz 125 − MHz 2004 Jan 22 4 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 Fig.2 DC current gain; typical values.handbook, full pagewidth060000800002000040000MGD83710−11IC (mA)hFE10102 103VCE = 2 V. 2004 Jan 22 5 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 PACKAGE OUTLINEUNITA1max.bpcDE e1HELpQwv REFERENCESOUTLINEVERSIONEUROPEANPROJECTIONISSUE DATE04-11-0406-03-16 IEC JEDEC JEITAmm0.10.480.380.150.093.02.81.41.20.95e1.92.52.10.550.450.10.2DIMENSIONS (mm are the original dimensions)0.450.15 SOT23TO-236ABbpDe1eAA1LpQdetail XHEEwMvMABAB012 mmscaleA1.10.9cX123Plastic surface-mounted package; 3 leadsSOT23 2004 Jan 22 6 NXP Semiconductors Product data sheet NPN Darlington transistors PMBTA13; PMBTA14 DATA SHEET STATUS Notes 1.Please consult the most recently issued document before initiating or completing a design. 2.The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DOCUMENTSTATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. DISCLAIMERS General ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. NXP Semiconductors Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com © NXP B.V. 2009 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Printed in The Netherlands R75/05/pp7 Date of release: 2004 Jan 22 Document order number: 9397 750 12507 http://www.tracopower.com Page 1 of 4 DC/DC Converters TDR 3 Series, 3 Watt Features ◆ Compact design in SMD or DIP package ◆ Wide 2:1 input voltage range ◆ Fully regulated outputs ◆ Low ripple and noise ◆ No minimum load required ◆ Temperature range –40°C to +85°C ◆ I/O isolation 1500 VDC ◆ Continuous short-circuit protection ◆ Remote On/Off control ◆ Fully RoHS compliant ◆ 3-year product warranty The TDR-3 series is a family of compact 3 W dc/dc-converters with 2:1 input voltage ranges and tightly regulated output voltages even under no load conditions. The product is available in SMD-package or in DIP-package. They work with high efficiency over the full load range and come with a remote On/Off input. The usability in temperature ranges of up to 85°C, continuous short circuit protection and excellent immunity against environmental influences make these converters very reliable. A TDR-3 converter is the ideal solution for space critical high end applications in communication equipment, instrumentation and industrial electronics. Order code DIP models Order code SMD models Input voltage range Output voltage Output current max. Efficiency typ. TDR 3-0511 TDR 3-0511SM 5.0 VDC 600 mA 79 % TDR 3-0512 TDR 3-0512SM 12 VDC 250 mA 80 % TDR 3-0513 TDR 3-0513SM 4.5 – 9.0 VDC 15 VDC 200 mA 81 % TDR 3-0522 TDR 3-0522SM (5 VDC nominal) ±12 VDC ±125 mA 80 % TDR 3-0523 TDR 3-0523SM ±15 VDC ±100 mA 81 % TDR 3-1211 TDR 3-1211SM 5.0 VDC 600 mA 81 % TDR 3-1212 TDR 3-1212SM 12 VDC 250 mA 82 % TDR 3-1213 TDR 3-1213SM 9 – 18 VDC 15 VDC 200 mA 82 % TDR 3-1222 TDR 3-1222SM (12 VDC nominal) ±12 VDC ±125 mA 82 % TDR 3-1223 TDR 3-1223SM ±15 VDC ±100 mA 83 % TDR 3-2411 TDR 3-2411SM 5.0 VDC 600 mA 81 % TDR 3-2412 TDR 3-2412SM 12 VDC 250 mA 82 % TDR 3-2413 TDR 3-2413SM 18 – 36 VDC 15 VDC 200 mA 83 % TDR 3-2422 TDR 3-2422SM (24 VDC nominal) ±12 VDC ±125 mA 83 % TDR 3-2423 TDR 3-2423SM ±15 VDC ±100 mA 83 % TDR 3-4811 TDR 3-4811SM 5.0 VDC 600 mA 81 % TDR 3-4812 TDR 3-4812SM 12 VDC 250 mA 82 % TDR 3-4813 TDR 3-4813SM 36 – 75 VDC 15 VDC 200 mA 82 % TDR 3-4822 TDR 3-4822SM (48 VDC nominal) ±12 VDC ±125 mA 83 % TDR 3-4823 TDR 3-4823SM ±15 VDC ±100 mA 83 % Models UL 60950-1 http://www.tracopower.com Page 2 of 4 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. DC/DC Converters TDR 3 Series 3 Watt Input Specifications Input current at no load (nominal input voltage) 5 Vin models: 50 mA typ. 12 Vin models: 30 mA typ. 24 Vin models: 13 mA typ. 48 Vin models: 10 mA typ. Input current at full load (nominal input voltage) 5 Vin models: 790 mA typ. 12 Vin models: 320 mA typ. 24 Vin models: 160 mA typ. 48 Vin models: 80 mA typ. Surge voltage (1 sec. max.) 5 Vin models: 15 V max. 12 Vin models: 25 V max. 24 Vin models: 50 V max. 48 Vin models: 100 V max. Input filter capacitor type (see EMC considerations page 3 for compliance to EN 55022 class A/B) ESD (electrostatic discharge) EN 61000-4-2, air ±8 kV, contact ±6 kV, perf. criteria A Radiated immunity EN 61000-4-3 10 V/m, perf. criteria A Fast transient / Surge EN 61000-4-4, ±2 kV, perf. criteria A EN 61000-4-5, ±1 kV perf. criteria A with external input capacitor e.g. Nippon chemi-con KY 220 μF, 100 V, ESR 48 mOhm Conducted immunity EN 61000-4-6, 10 Vrms, perf. criteria A Reflected ripple current 5 Vin models: 80 mAp-p typ. (measured with input filter according class A) 12 Vin models: 40 mAp-p typ. 24 Vin models: 30 mAp-p typ. 48 Vin models: 20 mAp-p typ. Output Specifications Voltage set accuracy ±1 % max Regulation – Input variation Vin min. to Vin max. 0.2 % max. – Load variation 0 – 100 % single output models: 1.0 % max. dual output models: 1.0 % max. balanced load – Load variation 10 – 90 % single output models: 0.5 % max. dual output models: 0.8 % max. balanced load – Load cross regulation 25/100 % 5.0 % max. (dual output models) Minimum load 0 % of rated max. load Temperature coefficient ±0.02 %/K Ripple and noise (20 MHz bandwidth) 30 mVp-p typ. Start up time – Power On 5 ms typ. (constant resistive load) – Remote On 5 ms typ. Transient response setting time (25 % load step change) 250 μs typ. Short circuit protection continuous, automatic recovery Capacitive load 5 VDC models: 1680 μF max. 12 VDC models: 820 μF max. 15 VDC models: 680 μF max. ±12 VDC models: ±470 μF max. ±15 VDC models: ±330 μF max. http://www.tracopower.com Page 3 of 4 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. DC/DC Converters TDR 3 Series 3 Watt EMC Consideration Recommended filter for EN 55022 class A compliance Input models C1 C3 L1 value order code datasheet 5 VDC 4.7 μF / 25 V 1812 MLCC 10 μH TCK-047 www.tracopower.com/products/tck047.pdf 12 VDC 6.8 μF / 50 V 1812 MLCC 12 μH TCK-062 www.tracopower.com/products/tck062.pdf 24 VDC 4.7 μF / 50 V 1812 MLCC 220pF / 3 kV 1808 MLCC 10 μH TCK-047 www.tracopower.com/products/tck047.pdf 48 VDC 4.7 μF / 100 V 1812 MLCC 10 μH General Specifications Temperature ranges – Operating –40°C to +85°C – Storage –55°C to +125°C – Case temperature tba. Load derating 3.3 %/K above +70°C Humidity (non condensing) 5 % to 90 % rel. H max. Thermal shock acc. MIL-STD-810F Vibration acc. MIL-STD-810F Reliability, calculated MTBF (MIL-HDBK-217F, at+25°C, ground benign) >2.4 Mio h Isolation voltage (60 sec.) – Input/Output 1500 VDC Isolation capacitance – Input/Output 50 pF max. Isolation resistance – Input/Output (500 VDC) >10 GOhm Altitude during operation tba. Safety standard (designed to meet) IEC/EN 60950-1, UL 60950-1 Safety approvals – UL/cUL www.ul.com -> certifications -> File e188913 Switching frequency 100 kHz (PWM) Remote On/Off – On: open or high impedance – Off: 2...4 mA current applied via 1KOhm resistor – Off stand by input current 2.5 mA max. TDR 3 dc/dc-converter Load L1 C1 C3 +Vin -Vin +Vout -Vout TDR 3 dc/dc-converter Load L1 C1 C2 C3 +Vin -Vin +Vout -Vout Input models C1 & C2 C3 L1 value order code (SMD type) datasheet 5 VDC 6.8 μF / 25 V 1812 MLCC 10 μH TCK-047 www.tracopower.com/products/tck047.pdf 12 VDC 4.7 μF / 50 V 1812 MLCC 12 μH TCK-062 www.tracopower.com/products/tck062.pdf 24 VDC 220pF / 3 kV 1808 MLCC 18 μH TCK-046 48 VDC 4.7 μF / 100 V 1812 MLCC 18 μH TCK-046 www.tracopower.com/products/tck046.pdf Recommended filter for EN 55022 class B compliance Page 4 of 4 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com DC/DC Converters TDR 3 Series 3 Watt Outline Dimensions Pin Single Dual 1 –Vin (GND) –Vin (GND) 2 Remote On/Off Remote On/Off 6 NC Common 7 NC –Vout 8 +Vout +Vout 9 –Vout Common 14 +Vin (Vcc) +Vin (Vcc) Pin-Out Rev. February 22. 2013 Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Pin pich tolerances: ±0.25 (±0.01) Pysical Specifications Casing material non-conductive plastic (UL94V-0 rated) Package weight 4.5 g (0.16 oz) Soldering profile for DIP-package models max. 265°C / 10 sec. (wave soldering) Lead-free reflow solder process for SMD-package models as per J-STD-020D.01 (to find at: www.jedec.org - free registration required) Moisture sensivity level (for SMD-package models) level 2a as per J-STD-033B.01 (to find at: www.jedec.org - free registration required) Environmental compliance – Reach www.tracopower.com/products/tdr3-reach.pdf – RoHS RoHS directive 2011/65/EU Packaging – Tube 10 pcs packing unit – Tape & Reel (only SMD models, add suffix –TR) 200 pcs packing unit 18.9 8.7 12.8 13.55 (0.74) (0.35) (0.533) (0.50) 3.8 (0.15) 0.8(0.03) 1.3(0.05) top view 14 9 8 1 2 6 7 1.8 2.54 10.16 2.54 (0.07) (0.1) (0.4) (0.1) 0.25 (0.01) 0-15° 1.8 2.54 10.16 2.54 18.9 8.7 12.8 17.2 (0.07) (0.1) (0.4) (0.74) (0.35) (0.68) (0.50) (0.1) 1.0 (0.04) 1.5 (0.06) top view 14 9 8 1 2 6 7 7.4 (0.29) 0.25 (0.01) 0-4° 1.2 (0.05) DIP-Models SMD-Models NC = not to connect Recommended Solder Pad Dimension: 18.1 (0.71) 1.8 2.54 10.16 2.54 (0.07) (0.1) (0.4) (0.1) 1.8 (0.07) 2.0 (0.08) Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 1 / 60 Features  Single output current up to 700 mA  3 watts maximum output power  High efficiency up to 82%  RoHS directive compliant  Sip package, 21.8 x 11.2 x 9.1mm (0.86 x 0.36x 0.44 inch)  4:1 wide input voltage range  Low ripple & noise  UL94-V0 case potting materials  Input to output isolation: 1500Vdc,min for 60 seconds  Continuous short circuit protection  Remote ON/OFF  International safety standard approval Options  3000Vdc isolation for 60 seconds Applications  Wireless Network  Telecom / Datacom  Industry Control System  Measurement Equipment  Semiconductor Equipment TMR 3-WI Series Application Note DC/DC Converter 4.5 to 18Vdc, 9 to 36Vdc or 18 to 75Vdc Input 3.3 to 15Vdc Single Outputs ±5Vdc to ±15Vdc Dual Outputs and 3 Watt Output Power Pending Complete TMR 3-WI datasheet can be downloaded at: http://www.tracopower.com/products/tmr3wi.pdf General Description The TMR 3WI series offer 3 watts of output power from a 21.8 x 11.2 x 9.1mm (0.86 x 0.36 x 0.44 inch) package without derating up to 71°C. The TMR 3WI series have 4:1 wide input voltage range from 4.5-18Vdc, 9-36Vdc or 18-75Vdc and features 1500Vdc of isolation test voltage, short-circuit protection. All models are particularly suited to telecommunications, industrial, mobile telecom and test equipment applications. Table of contents Absolute Maximum Rating P2 Thermal Consideration P57 Output Specification P2 Remote ON/OFF Control P57 Input Specification P3 – P4 Mechanical Data P58 General Specification P4 – P5 Recommended Pad Layout P58 Environmental Specification P5 Soldering Consideration P59 EMC Characteristic P5 Packaging Information P59 Characteristic Curves P6 – P53 Order Code P60 Test Configurations P54 Safety and Installation Instruction P60 EMI Considerations P55 – P56 MTBF and Reliability P60 Input Source Impedance P57 Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 2 / 60 3W Single & Dual Output Absolute Maximum Rating Parameter Model Min Max Unit Input Voltage Continuous Transient (100ms) TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI 18 36 75 36 50 100 Vdc Operating Ambient Temperature (without derating) All -40 +71 °C Storage Temperature All -55 +125 °C Output Specification Parameter Model Min Typ Max Unit Output Voltage (Vin = Vin nom; Full Load; TA = 25°C) TMR 3-xx10WI TMR 3-xx11WI TMR 3-xx09WI TMR 3-xx12WI TMR 3-xx13WI TMR 3-xx21WI TMR 3-xx22WI TMR 3-xx23WI 3.267 4.95 8.91 11.88 14.85 ±4.95 ±11.88 ±14.85 3.3 5 9 12 15 ±5 ±12 ±15 3.333 5.05 9.09 12.12 15.15 ±5.05 ±12.12 ±15.15 Vdc Output Regulation Line (Vin min to Vin max at Full Load) Load (0% to 100% of Full Load) Load (5% to 100% of Full Load) All -0.2 -1.0 -0.5 +0.2 +1.0 +0.5 % Output Ripple & Noise Peak-to-Peak (5Hz to 20MHz Bandwidth) All 30 mV pk-pk Temperature Coefficient All -0.02 +0.02 %/°C Dynamic Load Response (Vin = Vin nom; TA = 25°C) Load step change from 75% to 100% or 100 to 75% of Full Load Setting Time (Vout < 10% peak deviation) All 250 μS Output Current TMR 3-xx10WI TMR 3-xx11WI TMR 3-xx09WI TMR 3-xx12WI TMR 3-xx13WI TMR 3-xx21WI TMR 3-xx22WI TMR 3-xx23WI 0 0 0 0 0 0 0 0 700 600 333 250 200 ±300 ±125 ±100 mA Max. Capacitive Load on the Output TMR 3-xx10WI TMR 3-xx11WI TMR 3-xx09WI TMR 3-xx12WI TMR 3-xx13WI TMR 3-xx21WI TMR 3-xx22WI TMR 3-xx23WI 3300 1680 1000 820 680 ±1000 ±470 ±330 μF Output Short Circuit Protection All Continuous, automatics recovery Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 3 / 60 3W Single & Dual Output Input Specification Parameter Model Min Typ Max Unit Operating Input Voltage TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI 4.5 9 18 12 24 48 18 36 75 Vdc Input Current (Maximum Value at Vin = Vin nom; Full Load) TMR 3-1210WI TMR 3-1211WI TMR 3-1209WI TMR 3-1212WI TMR 3-1213WI TMR 3-1221WI TMR 3-1222WI TMR 3-1223WI TMR 3-2410WI TMR 3-2411WI TMR 3-2409WI TMR 3-2412WI TMR 3-2413WI TMR 3-2421WI TMR 3-2422WI TMR 3-2423WI TMR 3-4810WI TMR 3-4811WI TMR 3-4809WI TMR 3-4812WI TMR 3-4813WI TMR 3-4821WI TMR 3-4822WI TMR 3-4823WI 285 338 333 329 329 329 329 329 140 165 165 160 160 167 162 162 71 82 82 81 81 84 81 81 mA Input Standby Current (Typical Value at Vin = Vin nom; No Load) TMR 3-1210WI TMR 3-1211WI TMR 3-1209WI TMR 3-1212WI TMR 3-1213WI TMR 3-1221WI TMR 3-1222WI TMR 3-1223WI TMR 3-2410WI TMR 3-2411WI TMR 3-2409WI TMR 3-2412WI TMR 3-2413WI TMR 3-2421WI TMR 3-2422WI TMR 3-2423WI TMR 3-4810WI TMR 3-4811WI TMR 3-4809WI TMR 3-4812WI TMR 3-4813WI TMR 3-4821WI TMR 3-4822WI TMR 3-4823WI 35 40 40 40 40 40 40 40 20 20 19 20 19 25 25 25 12 12 13 14 14 14 14 14 mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 4 / 60 3W Single & Dual Output Input Specification Parameter Model Min Typ Max Unit Input Reflected Ripple Current (See Page 54) TMR 3-12xxWI TMR 3-24xxWI TMR 3-48xxWI 25 10 8 mA pk-pk Start Up Time (Vin = Vin nom and constant resistive load) Power up Remote ON/OFF All 30 30 mS Remote ON/OFF Control (See Page 57) DC-DC ON DC-DC OFF All 2 Open 4 mA Remote Off Input Current All 2.5 mA General Specification Parameter Model Min Typ Max Unit Efficiency (See Page 60) (Vin = Vin nom; Full Load; TA = 25°C) TMR 3-1210WI TMR 3-1211WI TMR 3-1209WI TMR 3-1212WI TMR 3-1213WI TMR 3-1221WI TMR 3-1222WI TMR 3-1223WI TMR 3-2410WI TMR 3-2411WI TMR 3-2409WI TMR 3-2412WI TMR 3-2413WI TMR 3-2421WI TMR 3-2422WI TMR 3-2423WI TMR 3-4810WI TMR 3-4811WI TMR 3-4809WI TMR 3-4812WI TMR 3-4813WI TMR 3-4821WI TMR 3-4822WI TMR 3-4823WI 74 78 79 80 80 80 80 80 75 80 80 82 82 79 81 81 74 80 80 81 81 79 81 81 % Isolation Voltage (for 60 seconds) Input to Output Standard Suffix ”H” All All 1500 3000 Vdc Isolation Resistance All 109 Ω Isolation Capacitance Standard Suffix ”H” All 200 40 pF Switching Frequency All 100 KHz Weight All 4.8 g Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 5 / 60 3W Single & Dual Output General Specification Parameter Model Min Typ Max Unit MTBF (See Page 60) Bellcore TR-NWT-000332, TC = 40°C MIL-HDBK-217F All 3’963’000 1’707’000 hours Case Material Non-conductive black plastic Base Material None Potting material Silicon (UL94-V0) Dimensions 21.8 X 9.2 X 11.1 mm (0.86 X 0.36 X 0.44 Inch) Environmental Specification Thermal shock MIL-STD-810F Vibration MIL-STD-810F Relative humidity 5% to 95% RH EMC Characteristic EMI (See Page 55 & 56) EN55022 Class A Class B ESD EN61000-4-2 Air ±8KV Contact ±6KV Performance Criteria A Radiated immunity EN61000-4-3 10V/m Performance Criteria A Fast transient * EN61000-4-4 ±2KV Performance Criteria A Surge * EN61000-4-5 ±1KV Performance Criteria A Conducted immunity EN61000-4-6 10Vr.m.s Performance Criteria A * An external input filter capacitor is required if the module has to comply with EN 61000-4-4, EN 61000-4-5. The filter capacitor Tracopower suggest: Nippon Chemi-Con KY series, 100μF/100V, ESR = 110mΩ. Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 6 / 60 3W Single & Dual Output Characteristic Curves All test conditions are at 25°C. The figures are identical for TMR 3-1210WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 7 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1210WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 8 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1211WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 9 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1211WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 10 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1209WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 11 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1209WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 12 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1212WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 13 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1212WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 14 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1213WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 15 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1213WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 16 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1221WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 17 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1221WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 18 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1222WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 19 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1222WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 20 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1223WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 21 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-1223WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 22 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2410WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 23 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2410WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 24 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2411WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 25 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2411WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 26 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2409WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 27 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2409WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 28 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2412WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 29 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2412WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 30 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2413WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 31 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2413WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 32 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2421WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 33 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2421WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 34 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2422WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 35 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2422WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 36 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2423WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 37 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-2423WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 38 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4810WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 39 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4810WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 40 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4811WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 41 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4811WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 42 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4809WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 43 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4809WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 44 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4812WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 45 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4812WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 46 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4813WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 47 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4813WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 48 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4821WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 49 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4821WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 50 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4822WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 51 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4822WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 52 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4823WI Efficiency versus Output Current Power Dissipation versus Output Current Efficiency versus Input Voltage. Full Load Derating Output Current versus Ambient Temperature and Airflow Vin = Vin nom Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 53 / 60 3W Single & Dual Output Characteristic Curves (Continued) All test conditions are at 25°C. The figures are identical for TMR 3-4823WI Typical Output Ripple and Noise. Vin = Vin nom, Full Load Transient Response to Dynamic Load Change from 100% to 75% to 100% of Full Load ; Vin = Vin nom Typical Input Start-Up and Output Rise Characteristic Vin = Vin nom, Full Load Using ON/OFF Voltage Start-Up and Vout Rise Characteristic Vin = Vin nom, Full Load Conduction Emission of EN55022 Class A Vin = Vin nom, Full Load Conduction Emission of EN55022 Class B Vin = Vin nom, Full Load Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 54 / 60 3W Single & Dual Output Testing Configurations Input reflected-ripple current measurement test up Component Value Voltage Reference L 2u2H ---- SMD Inductor C 1μF 100V 1210 MLCC Peak-to-peak output ripple & noise measurement test up Output voltage and efficiency measurement test up Note: All measurements are taken at the module terminals. % 100            in in o o V I V I Efficiency Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 55 / 60 3W Single & Dual Output EMI considerations +Vin -Vin +Vout -Vout C1 L1 D/D Converter +INPUT -INPUT LOAD Suggested Schematic to comply with EN55022 Conducted Noise Class A recommended PCB Layout with Input Filter To comply with conducted noise according to EN55022 CLASS A following components are recommended: TMR 3-12xxWI Component Value Voltage Reference C1 4.7μF 25V 1210 MLCC L1 2.2μH ---- SMD Inductor, P/N: TCK-059 TMR 3-24xxWI Component Value Voltage Reference C1 2.2μF 50V 1210 MLCC L1 10μH ---- SMD Inductor, P/N: TCK-047 TMR 3-48xxWI Component Value Voltage Reference C1 2.2μF 100V 1210 MLCC L1 10μH ---- SMD Inductor, P/N: TCK-047 PDL03W SERIES Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 56 / 60 3W Single & Dual Output EMI considerations (Continued) +Vin -Vin +Vout -Vout C1 L1 D/D Converter +INPUT -INPUT LOAD Suggested Schematic to comply with EN55022 Conducted Noise Class B recommended PCB Layout with Input Filter To comply with conducted noise according to EN55022 CLASS B following components are recommended: TMR 3-12xxWI Component Value Voltage Reference C1 10μF 25V 1812 MLCC L1 2.2μH ---- SMD Inductor, P/N: TCK-059 TMR 3-24xxWI Component Value Voltage Reference C1 6.8μF 50V 1812 MLCC L1 18μH ---- SMD Inductor, P/N: TCK-046 TMR 3-48xxWI Component Value Voltage Reference C1 2.2μF 100V 1812 MLCC L1 18μH ---- SMD Inductor, P/N: TCK-046 PDL03W SERIES Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 57 / 60 3W Single & Dual Output Input Source Impedance The power module should be connected to a low impedance input source. Highly inductive source impedance can affect the stability of the power module. Input external L-C filter is recommended to minimize input reflected ripple current. The capacitor must as close as possible to the input terminals of the power module for lower impedance. Thermal Consideration The power module operates in a variety of thermal environments. However, sufficient cooling should be provided to help ensure reliable operation of the unit. Heat is removed by conduction, convection, and radiation to the surrounding Environment. Proper cooling can be verified by measuring the point as the figure below. The temperature at this location should not exceed 100°C. When Operating, adequate cooling must be provided to maintain the test point temperature at or below 100°C. Although the maximum point Temperature of the power modules is 100°C, you can limit this Temperature to a lower value for extremely high reliability. TOP VIEW Remote ON/OFF Control The positive logic remote ON/OFF control circuit is included. Turns the module ON during a logic High on the On/Off pin and turns OFF during a logic Low. The On/Off pin is an open collector/drain logic input signal (Von/off) that referenced to GND. If not using the remote on/off feature, please open circuit between on/off pin and input pin to turn the module on. Recommended external ON/OFF Ctrl circuit and components R1 R2 1K Vcc CONTROL TTL Signal 5K1 ON/OFF PIN RIN ZD1 DC/DC Converter Logic Positive R1(K) R2(K) ZD1 Vcc = 4.5~18Vdc 0 7.5 10V, 5mA Vcc = 9~36Vdc 2.2 16 18V, 5mA Vcc = 18~75Vdc 6.8 33 36V, 5mA Measurement shown in inches and (millimeters) Temperature Measurement Point Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 58 / 60 3W Single & Dual Output Mechanical Data Pin Connection Pin Single Dual 1 -Input (GND) -Input (GND) 2 +Input (Vcc) +Input (Vcc) 3 Remote on/off Remote on/off 5 NC* / No Pin** NC* / No Pin** 6 +Output (+Vout) +Output (+Vout) 7 -Output (-Vout) Com 8 NC -Output (-Vout) Recommended Pad Layout All Dimensions in Inches (mm) Tolerance: X.XX ±0.02 (X.X ±0.5) X.XXX ±0.01 (X.XX ±0.25) Pin Pitch Tolerance: ±0.01 (±0.25) Pin Dimension Tolerance: ±0.004 (±0.1) 0.16 (4.10) 0.44 (11.2) 1 2 3 5 6 7 8 0.100(2.54) 0.86(21.80) FRONT VIEW 0.02(0.50) 0.700(17.78) .0.01(0.25) Rectangular pin 0.08(2.0) 0.36(9.10) 0.13(3.3) BOTTOM VIEW 0.02(0.50) * NC pin for standard. ** No pin for 3KV isolation. (P/N suffix ”H”) Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 59 / 60 3W Single & Dual Output Soldering Considerations Lead free wave solder profile for TMR 3WI SIP type Zone Reference Parameter Preheat zone Rise temp. speed: 3°C/ sec max. Preheat temperature: 100~130°C Actual heating Peak temperature: 250~260°C Peak time (T1+T2 time): 4~6 sec Reference Solder: Sn-Ag-Cu; Sn-Cu Hand Welding: Soldering iron: Power 90W Welding Time: 2~4 sec Temperature: 380~400°C Packaging Information 10 pc’s per TUBE Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: June 7th, 2011 / Rev.: 1.1 / Page 60 / 60 3W Single & Dual Output Order Code Note 1: Maximum value at nominal input voltage and full load of standard type. Note 2: Typical value at nominal input voltage and full load. Model Output Current Input Current Number Input Range Output Voltage Full Load Full Load(1) Eff (2) (%) TMR 3-1210WI 4.5 – 18Vdc 3.3Vdc 700mA 285mA 74 TMR 3-1211WI 4.5– 18Vdc 5.0Vdc 600mA 338mA 78 TMR 3-1209WI 4.5– 18Vdc 9.0Vdc 333mA 333mA 79 TMR 3-1212WI 4.5– 18Vdc 12.0Vdc 250mA 329mA 80 TMR 3-1213WI 4.5– 18Vdc 15.0Vdc 200mA 329mA 80 TMR 3-1221WI 4.5– 18Vdc ±5.0Vdc ±300mA 329mA 80 TMR 3-1222WI 4.5– 18Vdc ±12.0Vdc ±125mA 329mA 80 TMR 3-1223WI 4.5– 18Vdc ±15.0Vdc ±100mA 329mA 80 TMR 3-2410WI 9– 36Vdc 3.3Vdc 700mA 140mA 75 TMR 3-2411WI 9 – 36Vdc 5.0Vdc 600mA 165mA 80 TMR 3-2409WI 9 – 36Vdc 9.0Vdc 333mA 165mA 80 TMR 3-2412WI 9 – 36Vdc 12.0Vdc 250mA 160mA 82 TMR 3-2413WI 9 – 36Vdc 15.0Vdc 200mA 160mA 82 TMR 3-2421WI 9 – 36Vdc ±5.0Vdc ±300mA 167mA 79 TMR 3-2422WI 9 – 36Vdc ±12.0Vdc ±125mA 162mA 81 TMR 3-2423WI 9 – 36Vdc ±15.0Vdc ±100mA 162mA 81 TMR 3-4810WI 18 – 75Vdc 3.3Vdc 700mA 71mA 74 TMR 3-4811WI 18 – 75Vdc 5.0Vdc 600mA 82mA 80 TMR 3-4809WI 18 – 75Vdc 9.0Vdc 333mA 82mA 80 TMR 3-4812WI 18 – 75Vdc 12.0Vdc 250mA 81mA 81 TMR 3-4813WI 18 – 75Vdc 15.0Vdc 200mA 81mA 81 TMR 3-4821WI 18 – 75Vdc ±5.0Vdc ±300mA 84mA 79 TMR 3-4822WI 18 – 75Vdc ±12.0Vdc ±125mA 81mA 81 TMR 3-4823WI 18 – 75Vdc ±15.0Vdc ±100mA 81mA 81 Safety and Installation Instruction Fusing Consideration Caution: This power module is not internally fused. An input line fuse must always be used. This encapsulated power module can be used in a wide variety of applications, ranging from simple stand-alone operation to an integrated part of sophisticated power architecture. To maximum flexibility, internal fusing is not included; however, to achieve maximum safety and system protection, always use an input line fuse. The safety agencies require a slow-blow fuse with maximum rating of 1.6A for TMR 3-12xxWI modules, 1A for TMR 3-24xxWI and TMR 3-48xxWI modules. Based on the information provided in this data sheet on Inrush energy and maximum dc input current; the same type of fuse with lower rating can be used. Refer to the fuse manufacturer’s data for further information. MTBF and Reliability The MTBF of TMR 3WI-SERIES of DC/DC converters has been calculated using Bellcore TR-NWT-000332 Case I: 50% stress, operating temperature at 40°C (Ground fixed and controlled environment). The resulting figure for MTBF is 3’963’000 hours. MIL-HDBK 217F NOTICE2 FULL LOAD, operating temperature at 25°C. The resulting figure for MTBF is 1’707’000 hours. Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 1 / 23 Features • SIP package: 21.8 x 9.2 x 11.1 mm (0.86 x 0.36 x 0.44inch) • 2:1 wide input voltage of 4.5-9, 9-18,18-36 and 36-75VDC • 2 Watts output power • Low ripple & noise • UL94-V0 case potting materials • Input to output isolation: 1000Vdc, for 1 minute • Operating temperature range: up to 75°C max without derating • Continuous short circuit protection • RoHS directive compliant • External on/off control • ISO 9001 certified manufacturing facilities • UL60950-1 Recognized E188913 Applications • test equipment • Communication equipment • Computer equipment • mobile telecom equipment TMR 2 Series Application Note DC/DC Converter 4.5 to 9Vdc, 9 to 18Vdc, 18 to 36Vdc or 36 to 75 Vdc Input 3.3 to 15Vdc Single Outputs and ±5 to ±15Vdc Dual Outputs, 2 Watt E188913 Complete TMR-2 datasheet can be downloaded at: http://www.tracopower.com/products/tmr.pdf General Description The TMR 2 series offer 2 watts of output power from a 21.8 x 9.2 x 11.1 mm package up to an operating temperature of +75°C without derating and without need of any external components. This product has a 2:1 wide input voltage range of 4.5-9Vdc, 9-18Vdc, 18-36Vdc or 36-75Vdc and features an input to output isolation of 1000Vdc, indefinite short-circuit protection. All models are particularly suited to telecommunications, industrial, mobile telecom and test equipment applications. Table of contents Block Diagram P2 EMC consideration P8 Absolute maximum rating P2 Input Source Impedance P8 Output Specifications P2 & P3 Characteristic curve P9 - P20 Input Specifications P3 & P4 Thermal Consideration P21 General Specifications P5 Part number structure P21 Remote on/off control P6 EMC Specifications P21 & P22 Output over current protection P6 Mechanical data P22 Short circuitry protection P6 Safety and installation instruction P23 Solder, clearing, and drying considerations P7 MTBF and Reliability P23 Test configurations P7 & P8 Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 2 / 23 2W, Single and Dual Output Block Diagram Absolute Maximum Rating Parameter Device Min Typ Max Unit Continuous TMR 05xx TMR 12xx TMR 24xx TMR 48xx 9 18 36 75 Vdc Vdc Vdc Vdc Input Voltage Transient (100ms) TMR 05xx TMR 12xx TMR 24xx TMR 48xx 15 36 50 100 Vdc Vdc Vdc Vdc Output power 2 W Temperature coefficient ±0.1 %/°C Output Specifications Parameter Device Min Typ Max Unit Operating Output Range TMR xx10 TMR xx11 TMR xx09 TMR xx12 TMR xx13 TMR xx21 TMR xx22 TMR xx23 3.267 4.950 8.910 11.880 14.850 ±4.950 ±11.880 ±14.850 3.300 5.000 9.000 12.000 15.000 ±5.000 ±12.000 ±15.000 3.333 5.050 9.090 12.120 15.150 ±5.050 ±12.120 ±15.150 Vdc Vdc Vdc Vdc Vdc Vdc Vdc Vdc Output Current TMR xx10 TMR xx11 TMR xx09 TMR xx12 TMR xx13 TMR xx21 TMR xx22 TMR xx23 50 40 22 17 13 ±20 ±8 ±7 500 400 222 167 134 ±200 ±83 ±67 mA mA mA mA mA mA mA mA Max. Output Capacitive Load TMR xx10 TMR xx11 TMR xx09 TMR xx12 TMR xx13 TMR xx21 TMR xx22 TMR xx23 2200 1000 470 170 110 ±470 ±100 ±47 μF μF μF μF μF μF μF μF Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 3 / 23 2W, Single and Dual Output Output Specifications (continue) Parameter Device Min Typ Max Unit Line Regulation (LL to HL at Full Load) All 0.5 % Load Regulation (10% to 100% of Full Load) TMR xx10 Other single output Dual output ±0.85 ±0.75 ±1.00 % Cross regulation (Asymmetrical load 25% to 100% of Full Load) ±5.0 Output Ripple & Noise (20MHz bandwidth) All 50 mV pk-pk Transient Response Recovery Time (25% load step change) All 500 μS Input Specifications Parameter Device Min Typ Max Unit Input Voltage Continuous TMR 05xx TMR 12xx TMR 24xx TMR 48xx 4.5 9 18 36 5.0 12.0 24.0 48.0 9 18 36 75 Vdc Vdc Vdc Vdc Input Current (Maximum Value at Vin = Vin nom; Full Load) TMR 0510 TMR 0511 TMR 0509 TMR 0512 TMR 0513 TMR 0521 TMR 0522 TMR 0523 TMR 1210 TMR 1211 TMR 1209 TMR 1212 TMR 1213 TMR 1221 TMR 1222 TMR 1223 TMR 2410 TMR 2411 TMR 2409 TMR 2412 TMR 2413 TMR 2421 TMR 2422 TMR 2423 TMR 4810 TMR 4811 TMR 4809 TMR 4812 TMR 4813 TMR 4821 TMR 4822 TMR 4823 540 615 596 588 582 645 595 598 202 234 222 219 220 242 224 226 102 115 109 109 108 117 112 110 52 60 56 55 55 62 57 57 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 4 / 23 2W, Single and Dual Output Input Specifications (continue) Parameter Device Min Typ Max Unit Input Standby Current (Typical Value at Vin = Vin nom; No Load) TMR 0510 TMR 0511 TMR 0509 TMR 0512 TMR 0513 TMR 0521 TMR 0522 TMR 0523 TMR 1210 TMR 1211 TMR 1209 TMR 1212 TMR 1213 TMR 1221 TMR 1222 TMR 1223 TMR 2410 TMR 2411 TMR 2409 TMR 2412 TMR 2413 TMR 2421 TMR 2422 TMR 2423 TMR 4810 TMR 4811 TMR 4809 TMR 4812 TMR 4813 TMR 4821 TMR 4822 TMR 4823 60 55 55 75 40 75 75 90 20 25 25 30 30 50 40 40 10 10 15 15 15 15 20 20 10 10 10 10 10 10 10 12 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 5V input (100μF) 12V input (100μF) 24V input (10μF) Input reflected ripple current (It will not damage the device if the capacitor on the input is not equipped) 48V input (10μF) 400 150 380 170 mA pk-pk mA pk-pk mA pk-pk mA pk-pk Start up time Power up (nominal Vin and constant resistive load power up) Remote ON/OFF 1 1 mS mS Remote ON/OFF Control (See Page 13) DC-DC ON DC-DC OFF All 4 Open 8 mA Remote Off Input Current All 2.5 mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 5 / 23 2W, Single and Dual Output General Specifications Parameter Device Min Typ Max Unit Efficiency at Vin nom and full load (Please see the testing configurations part) TMR 0510 TMR 0511 TMR 0509 TMR 0512 TMR 0513 TMR 0521 TMR 0522 TMR 0523 TMR 1210 TMR 1211 TMR 1209 TMR 1212 TMR 1213 TMR 1221 TMR 1222 TMR 1223 TMR 2410 TMR 2411 TMR 2409 TMR 2412 TMR 2413 TMR 2421 TMR 2422 TMR 2423 TMR 4810 TMR 4811 TMR 4809 TMR 4812 TMR 4813 TMR 4821 TMR 4822 TMR 4823 65 69 71 72 73 66 71 71 72 75 79 80 80 73 78 78 71 76 80 80 81 75 78 80 70 74 78 80 79 75 77 77 % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % % Isolation resistance All 109 Ω Isolation Capacitance All 300 1000 pF Switching Frequency (full load to minimum load) All 100 650 KHz Weight All 4.8 g MTBF (please see the MTBF and reliability part) All 5.107×106 hours Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 6 / 23 2W, Single and Dual Output Vout Pi (Input Power) Iocp Remote On/Off Control Only one type of remote on/off control is available for TMR. The module will turn on during the ctrl pin left open or high impedance between ctrl pin and -Vin pin. The module will turn off if the control pin is applied with a current of 4~8mA. In off condition the input current is app. 1mA max. Positive Logic: Negative Logic: Output over current protection When excessive output currents occur in the system, circuit protection is required on all converters. Normally, overload current is maintained at approximately 115~175% percent of rated current. The TMR converters have a fold-back over current protection. Fold back current protection reduces the load current during over current condition. The figure below shows a typical curve. Since the over current protection is a fold-back characteristic the highest power dissipation occurs at point S. During start-up this product provides less output current, hence the output rises slower, or the power supply may not start up at all if the load current during start up is larger than the fold back current. Short Circuitry Protection Continuous, hiccup and auto-recovery mode. During short circuit, converter will shut down and will switch on again to detect if the short circuit is still present or not. The average current during this condition will be very low and the device will be safe in short circuit condition. Due to that is the TMR converters indefinite short circuit protected. ● ● +Input -Input 6mA current Source Ctrl 1KΩ DC-DC OFF +Input -Input 6mA current Source Ctrl 1KΩ DC-DC ON S (Iout, max, Pi, max) Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 7 / 23 2W, Single and Dual Output Solder, clearing, and drying considerations Soldering Flow (wave) soldering: 250°C ±10°C less than10 seconds (see below) Soldering iron: 370°C ±10°C less than 5 seconds Note: the pin of this product is Tin coated. To assure the solder-ability, modules should be kept in their original shipping containers to provide adequate protection. Also, the storage environment shall be well controlled to protect any oxidation. Cleaning process In aqueous cleaning, it is preferred to have an in-line cleaner system consisting of several cleaning stages (pre-wash, wash, rinse, final rinse, and drying). Deionize (DI) water is recommend for aqueous cleaning; the minimum resistive level is 1MΩ-cm. Tap-water quality varies per region in terms of hardness, chloride, and solid contents; therefore, the use of tap water is not recommended for aqueous cleaning. Drying The drying section of the cleaner system should be equipped with blowers capable of generating 1000cfm -1500cfm of air so that the amount of rinse water left to be dried off with heat is minimal. Handheld air guns are not recommended due the variability and consistency of the operation. Note: after post-wash, the marking (date code) of converter may fall off. These only impacts the appearance and do not affect the operation of the module. Testing Configurations Input reflected-ripple current measurement test up TMR 05xx and TMR 12xx Component Value Voltage Reference C 100μF 50V Aluminium Electrolytic Capacitor TMR 24xx and TMR 48xx Component Value Voltage Reference C 10μF 100V Aluminium Electrolytic Capacitor Peak-to-peak output ripple & noise measurement test up Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 8 / 23 2W, Single and Dual Output Testing Configurations (continue) Output voltage and efficiency measurement test up Note: All measurements are taken at the module terminals. % 100 ×        × × = in in o o V I V I Efficiency EMC considerations Suggested Schematic for EN55022 Conducted Emission Class B Limits To comply with EN55022 CLASS B conducted emissions the following components are recommended: TMR 05xx and TMR 12xx Component Value Voltage Reference C1 22 μF 25V 1812 MLCC Capacitor L1 3.3 μH 2.0A / 0.06Ω / 0504 SMD Inductor, P/N: TCK-044 TMR 24xx Component Value Voltage Reference C1 4.7 μF 50V 1812 MLCC Capacitor L1 12 μH 1.4A / 0.12Ω / 0504 SMD Inductor, P/N: TCK-062 TMR 48xx Component Value Voltage Reference C1 2.2 μF 100V 1812 MLCC Capacitor L1 27 μH 0.9A / 0.2Ω / 0504 SMD Inductor, P/N: TCK-063 Input Source Impedance The power module should be connected to a low impedance input source. Highly inductive source impedance can affect the stability of the power module. Input external L-C filter is recommended to minimize input reflected ripple current. The capacitor should be equipped as close as possible to the input terminals of the power module for lower impedance. +Vin -Vin +Vout -Vout C1 L1 D/D Converter +INPUT -INPUT LOAD Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 9 / 23 2W, Single and Dual Output Characteristic Curve Efficiency a. Efficiency with load change under different line condition at room temperature TMR 0510 15.00 25.00 35.00 45.00 55.00 65.00 75.00 50 100 150 200 250 300 350 400 450 500 lout (mA ) Efficiency (%) TMR 1213 25.00 35.00 45.00 55.00 65.00 75.00 85.00 13 27 40 54 67 80 94 107 121 134 lout (mA ) Efficiency (%) TMR 4810 20.00 30.00 40.00 50.00 60.00 70.00 80.00 50 100 150 200 250 300 350 400 450 500 lout (mA ) Efficiency (%) 9V 12V 18V 4.5V 5V 9V 36V 48V 75V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 10 / 23 2W, Single and Dual Output TMR 1221 15.00 25.00 35.00 45.00 55.00 65.00 75.00 20 40 60 80 100 120 140 160 180 200 lout (mA ) Efficiency (%) TMR 2422 25.00 35.00 45.00 55.00 65.00 75.00 85.00 8 17 25 33 42 50 58 66 75 83 lout (mA ) Efficiency (%) TMR 4823 20.00 30.00 40.00 50.00 60.00 70.00 80.00 7 13 20 27 34 40 47 54 60 67 lout (mA ) Efficiency (%) 9V 12V 18V 18V 24V 36V 36V 48V 75V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 11 / 23 2W, Single and Dual Output b. Efficiency at input voltage change under different load condition at room temperature TMR 0510 15.00 25.00 35.00 45.00 55.00 65.00 75.00 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 Vin (V) Efficiency (%) TMR 1213 25.00 35.00 45.00 55.00 65.00 75.00 85.00 9 10 11 12 13 14 15 16 17 18 Vin (V) Efficiency (%) TMR 4810 20.00 30.00 40.00 50.00 60.00 70.00 80.00 36V 40V 44V 48V 52V 56V 60V 64V 68V 75V Vin(V) Eff(%) 500mA 250mA 50mA 134mA 67mA 13mA 500mA 250mA 50mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 12 / 23 2W, Single and Dual Output TMR 1221 15.00 25.00 35.00 45.00 55.00 65.00 75.00 85.00 9 10 11 12 13 14 15 16 17 18 Vin (V) Efficiency (%) TMR 2422 25.00 35.00 45.00 55.00 65.00 75.00 85.00 18 20 22 24 26 28 30 32 34 36 Vin (V) Efficiency (%) TMR 4823 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 36 40 44 48 52 56 60 64 68 75 Vin (V) Efficiency (%) 200mA 100mA 20mA 83mA 42mA 8mA 67mA 34mA 7mA Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 13 / 23 2W, Single and Dual Output Power dissipation curve TMR 0510 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 50 100 150 200 250 300 350 400 450 500 lout (mA ) Pd (W) TMR 1213 0.200 0.300 0.400 0.500 0.600 13 27 40 54 67 80 94 107 121 134 lout (mA ) Pd (W) TMR 4810 0.200 0.300 0.400 0.500 0.600 0.700 0.800 50 100 150 200 250 300 350 400 450 500 lout (mA ) Pd (W) 9V 5V 4.5V 18V 12V 9V 75V 48V 36V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 14 / 23 2W, Single and Dual Output TMR 1221 0.300 0.400 0.500 0.600 0.700 0.800 0.900 20 40 60 80 100 120 140 160 180 200 lout (mA ) Pd (W) TMR 2422 0.100 0.200 0.300 0.400 0.500 0.600 0.700 8 17 25 33 42 50 58 66 75 83 lout (mA ) Pd (W) TMR 4823 0.200 0.300 0.400 0.500 0.600 0.700 0.800 7 13 20 27 34 40 47 54 60 67 lout (mA ) Pd (W) 75V 48V 36V 36V 24V 18V 18V 12V 9V Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 15 / 23 2W, Single and Dual Output Output ripple & noise TMR 0510 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Output Ripple & Noise = 26.8mV Output Ripple & Noise = 20.8mV Output Ripple & Noise = 14.8mV TMR 1213 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Output Ripple & Noise = 25.2mV Output Ripple & Noise = 14.0mV Output Ripple & Noise = 11.6mV TMR 4810 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Output Ripple & Noise = 20.0mV Output Ripple & Noise = 13.6mV Output Ripple & Noise = 10.8mV Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 16 / 23 2W, Single and Dual Output TMR 1221 Vin min, Full Load Vin nom, Full Load Vin max, Full Load +Vout = 18.8mV / – Vout = 14.4mV + Vout = 17.6mV / –Vout = 14.0mV + Vout = 17.6mV / – Vout = 15.2mV TMR 2422 Vin min, Full Load Vin nom, Full Load Vin max, Full Load + Vout = 30.8mV / – Vout = 19.2mV + Vout = 25.6mV / – Vout = 18.0mV + Vout = 18.4mV / – Vout = 12.8mV TMR 4823 Vin min, Full Load Vin nom, Full Load Vin max, Full Load + Vout = 26.8mV / – Vout = 24.4mV + Vout = 14.8mV / – Vout = 14.0mV + Vout = 12.8mV / – Vout = 10.4mV Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 17 / 23 2W, Single and Dual Output Transient Peak and Response TMR 0510 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 85.0mV Transient Peak 81.0mV Transient Peak 75.0mV Transient Response 332.0μS Transient Response 328.0μS Transient Response 316.0μS TMR 1213 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 123.0mV Transient Peak 102.0mV Transient Peak 88.0mV Transient Response 488μS Transient Response 488μS Transient Response 488μS TMR 4810 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 79.0mV Transient Peak 68.0mV Transient Peak 63.0mV Transient Response 316μS Transient Response 316μS Transient Response 316μS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 18 / 23 2W, Single and Dual Output TMR 1221 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 270mV Transient Peak 246mV Transient Peak 240mV Transient Response 496μS Transient Response 480μS Transient Response 472μS TMR 2422 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 152mV Transient Peak 133mV Transient Peak 124mV Transient Response 320μS Transient Response 328μS Transient Response 320μS TMR 4823 Vin min, Full Load Vin nom, Full Load Vin max, Full Load Transient Peak 119mV Transient Peak 100mV Transient Peak 93mV Transient Response 400μS Transient Response 384μS Transient Response 392μS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 19 / 23 2W, Single and Dual Output Start-up Time and Rise Time TMR 0510 Vin nom, Full Load Vin nom, Full Load Rise Time = 247.6μS Start-up Time = 408.0μS TMR 1213 Vin nom, Full Load Vin nom, Full Load Rise Time = 530.3μS Start-up Time = 640.0μS TMR 4810 Vin nom, Full Load Vin nom, Full Load Rise Time = 176.3μS Start-up Time = 240.0μS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 20 / 23 2W, Single and Dual Output TMR 1221 Vin nom, Full Load Vin nom, Full Load Rise Time = 297.2μS Start-up Time = 640.0μS TMR 2422 Vin nom, Full Load Vin nom, Full Load Rise Time = 324.8uS Start-up Time = 432.0uS TMR 4823 Vin nom, Full Load Vin nom, Full Load Rise Time=1.056mS Start-up Time= 1.180mS Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 21 / 23 2W, Single and Dual Output Thermal Consideration The power module operates in a variety of thermal environments. However, sufficient cooling should be provided to help ensure reliable operation of the unit. Heat is removed by conduction, convection, and radiation to the surrounding Environment. Proper cooling can be verified by measuring the point as shown in the figure below. The temperature at this location should not exceed 100°C. During performance, adequate cooling must be provided to maintain the test point temperature at or below 100°C. Although the maximum point Temperature of the power modules is 100°C, you can limit the case temperature to a lower value for high reliability. TOP VIEW Part Number Structure TMR 4812 EMC Specifications Contact discharge Air discharge level test voltage (KV) level test voltage (KV) 1 ±2 1 ±2 2 ±4 2 ±4 3 ±6 3 ±8 EN61000-4-2 ESD (performance criteria B) 4 ±8 4 ±15 level test field strength (V/m) 1 1 2 3 EN61000-4-3 RS (performance criteria B) 3 10 Input Voltage Range: 05xx : 4.5~9V 12xx : 9~18V 24xx : 18~36V 48xx : 36~75V Output Voltage 10 : 3.3V 11 : 5V 09 : 9V 12 : 12V 13 : 15V 21 : ±5V 22 : ±12V 23 : ±15V TEMPERATURE MEASURE POINT Measurement shown in inches and (millimeters) Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 22 / 23 2W, Single and Dual Output EMC Specifications (continue) open circuit output test voltage ±10% level power line 1 ±0.5KV 2 ±1.0KV 3 ±2.0KV EN61000-4-4 EFT (performance criteria B) 4 ±4.0KV level open circuit output test voltage ±10% 1 ±0.5KV 2 ±1.0KV 3 ±2.0KV EN61000-4-5 Surge (performance criteria B) 4 ±4.0KV level voltage level(EMF) 1 1V/rms 2 3V/rms EN61000-4-6 CS (performance criteria B) 3 10V/rms Mechanical Data .0.01 (0.32) Rectangular pin 0.08 (2.01)±0.5 0.36 0.13 (3.20) BOTTOMVIEW All Dimensions in Inches (mm) Tolerance: X.XX ±0.02 (X.X ±0.5) X.XXX ±0.01(X.XX ±0.25) Pin Pitch Tolerance ±0.02(0.5) 0.16 (4.10)±0.5 0.02 (0.50)±0.05 0.44 1 2 3 5 6 7 8 0.10(2.54) 0.86(21.80) FRONT VIEW 0.02 (0.50) 0.70(17.78) PIN CONNECTION PIN SINGLE 1 - INPUT 2 + INPUT 3 CTRL 5 NC 6 + OUTPUT 7 - OUTPUT 8 NC DUAL OUTPUT - INPUT + INPUT CTRL NC + OUTPUT COM -OUTPUT Application Note Created by Traco Electronic AG Arp. www.tracopower.com Date: October 9th, 2007 / Rev.: 1.4 / Page 23 / 23 2W, Single and Dual Output Safety and Installation Instruction Isolation consideration The TMR series features 1.0k Volt DC isolation for 60 seconds from input to output, input to case, and output to case. The input to output resistance is greater than 109 ohms. Nevertheless, if the system using the TMR converter needs to get safety agency approval, certain rules must be followed in the design of the system. In particular, all of the creepage and clearance requirements of the end-use safety requirement must be observed. These documents include UL60950-1, EN60950-1 and CSA 22.2-60950, although specific applications may have other or additional requirements. Fusing Consideration Caution: The TMR converter is not internally fused. An input line fuse must always be used. This encapsulated power module can be used in a wide variety of applications, ranging from simple stand-alone operation to an integrated part of a sophisticated power architecture. To maximum flexibility, internal fusing is not included; however, to achieve maximum safety and system protection, always use an input line fuse. The safety agencies require a slow-blow fuse with maximum rating of 6.3 A. Based on the information provided in this data sheet on inrush energy and maximum dc input current, the same type of fuse with lower rating can be used. Minimum Load Requirement 25% (of full load) minimum load required to maintain a stable output voltage and to comply with the published specifications. The TMR Series is not getting damaged at no load or low load conditions but at loads below 25% a proper and accurate regulation of the output voltage cannot be ensured. The output voltage drops by app. 10%. MTBF and Reliability The MTBF of TMR series has been calculated according to: 1. MIL-HDBK-217F under the following conditions: Nominal Input Voltage and GB Iout = Iout max TA = +25°C The resulting figure for MTBF is 2.399× 106 hours. 2. Bell-core TR-NWT-000332 Case I: 50% stress, Operating Temperature at 40 ℃ (Ground fixed and controlled environment) The resulting figure for MTBF is 5.107× 106 hours. http://www.tracopower.com Page 1 of 13 Industrial Power Supplies TIS Series, 50–600 Watt Features ◆ Switch mode power supplies for DIN-rail mount ◆ 6 power ranges with 2, 3, 6, 12, 20 and 24 A output current (24 VDC models) ◆ Selectable 115/230 VAC input ◆ Very low ripple and noise ◆ EMI complies with EN 61000-6-3 and EN 61000-6-4 ◆ Operating temp. range –25°C to +70°C ◆ For system operation available with built-in functions: RED: Redundancy module for N+1 Systems with true current sharing SIG: Signal module with AC-powerfail, power good signal and external On/Off control UDS: DC-UPS module for uninterruptable battery backed-up power systems ◆ Worldwide safety approvals incl. class I, div. 2 location ◆ Easy snap-on mount on DIN-rails or chassis mount ◆ 3-year product warranty The switching power supplies of the TIS series have been particularly designed for applications in industrial process control systems and with machine tools. Excellent specifications and high immunity against electrical disturbances guarantee reliable power for sensitive loads in rugged industrial environments. With the help of optional function modules specific requirements for system applications can be easily realized with a standard model. With the UDS module the power supplies can be extended to a perfect DC-UPS with automatic battery- backup. This function is very often required in applications where a time delayed shutdown of a system is necessary. To monitor and control the power supply a signal module can be installed. For parallel operation with active power sharing a redundancy option is available. This flexibility makes the TIS series power supplies a cost effective solution for many industrial applications. Order Code Input Voltage Output Power Output Voltage Output Current (includes terminal plugs) nom. max. nom. max. TIS 50-112 115–240 VAC 50 W 12 VDC 3.5 A TIS 50-124 universal input 24 VDC 2.0 A TIS 75-112 115/230 VAC 12 VDC 6.0 A TIS 75-124 selectable 75 W 24 VDC 3.0 A TIS 75-148 48 VDC 1.5 A TIS 150-124 115/230 VAC 150 W 24 VDC 6.0 A TIS 150-148 selectable 48 VDC 3.0 A TIS 300-124 115/230 VAC 24 VDC 12.0 A TIS 300-148 selectable 300 W 48 VDC 6.0 A TIS 300-172 72 VDC 4.2 A TIS 500-124-115 115 VAC 500 W 24 VDC 20.0 A TIS 500-124-230 230 VAC 500 W 24 VDC 20.0 A TIS 600-124 24 VDC 24.0 A TIS 600-148 115/230 VAC 600 W 48 VDC 12.0 A TIS 600-172 selectable 72 VDC 8.5 A Models CB Scheme (LVD) UL 60950-1 UL 508 UL 1604 http://www.tracopower.com Page 2 of 13 Industrial Power Supplies TIS Series 50–600 Watt Input Specifications Input voltage range TIS 50: 93 – 264 VAC TIS 75, 150, 300, 600: 93 – 132 VAC / 187 – 264 VAC TIS 500-124-230. 187 – 264 VAC TIS 500-124-115: 93 – 132 VAC Input frequency 47 – 63 Hz Input current at full load (typ.) at 115 VAC at 230 VAC TIS 50: 0.85 A 0.50 A TIS 75: 1.3 A 0.75 A TIS 150: 2.7 A 1.6 A TIS 300: 4.9 A 2.9 A TIS 500: 6.0 A 4.3 A TIS 600: 7.0 A 5.0 A Recommended circuit breaker, TIS 50: 5.0 A characteristic C TIS 75: 5.0 A or fuse, slow blow typ TIS 150: 10.0 A TIS 300: 15.0 A TIS 500: 15.0 A TIS 600: 20.0 A Output Specifications Output voltage adj. range 12 VDC models: 12 – 14 VDC 24 VDC models: 24 – 28 VDC 48 VDC models: 48 – 52 VDC 72 VDC models: 60 – 76 VDC Regulation – Input variation 0.2 % – Load variation (10–90%) TIS 50, TIS 75, TIS 150: 1.0 % TIS 300, TIS 500, TIS 600: 0.3 % (2.0 % in parallel operation) Ripple and noise (20MHz bandwidth) <50 mV pk-pk Electronic short circuit protection current limitation at 110 % typ. (constant current, automatic restart) Over voltage protection, trigger point at 140 % typ. Vout nom. Hold-up time 115 VAC 230 VAC TIS 50 ... TIS 300: min. 25 ms min. 30 ms TIS 500: min. 20 ms min. 40 ms TIS 600: min. 15 ms min. 25 ms http://www.tracopower.com Page 3 of 13 General Specifications Temperature ranges – Operating (ambient temp.) –25°C to +70°C – Derating above 50°C (122°F) 2 %/K – Storage (non operating) –25°C to +85°C Humidity (non condensing) 95 % rel. H max. Pollution degree 2 Temperature coefficient 0.02 %/K Switching frequency 80 kHz typ. (pulse width modulation) Efficiency TIS 50 ... TIS 300: 85 % typ. TIS 500: 90 % typ. TIS 600: 90 % typ. Isolation according to IEC/EN 60950, UL 60950, UL 508 Reliability, calculated MTBF TIS 50/75: 450’000 h / 420’000 h (MIL-HDBK-217F, at +25°C, ground benign) TIS 150/300: 420’000 h / 360’000 h TIS 500/600: 340’000 h / 300’000 h Safety standards IEC/EN 60950-1 (SELV, except 72 VDC models) UL/cUL 60950-1, UL 508, UL/cUL 1604 Safety approvals – CB report for IEC 60950 www.tracopower.com/products/tis-cb.pdf – UL approvals UL/cUL 60950, File e181381 UL/cUL 508, File e210002 UL/cUL 1604, File e213613 not for TIS 50 & 500 (Class I, Div. 2, Groups A, B, C and D hazardous locations) www.ul.com -> certifications – CSA certificate (UL 60950-1, CSA 60950-1) www.tracopower.com/products/tis-csa.pdf Electromagnetic compatibility (EMC), Emissions EN 61000-6-3 / EN 61000-6-4 – Conducted RI suppression on input EN 55011 class B, EN 55022 class B, FCC part 15, level B – Radiated RI suppression EN 55011 class A, EN 55022 class A, FCC part 15, level A Electromagnetic compatibility (EMC), Immunity EN 61000-6-2 – Electrostatic discharge (ESD) IEC/EN 61000-4-2 4 kV/8 kV – Radiated RF field immunity IEC/EN 61000-4-3 10 V/m – Electrical fast transient / burst immunity IEC/EN 61000-4-4 2 kV – Surge immunity IEC/EN 61000-4-5 2 kV/4 kV – Immunity to conducted RF disturbances IEC/EN 61000-4-6 10 V – Power frequency field immunity IEC/EN 61000-4-8 30 A/m Safety class degree of electrical protection 1 (IEC 536) Case protection IP 20 (IEC 529) Environment – Vibration IEC 60068-2-6; 1 gn, 200 sweeps, each axis – Shock IEC 60068-2-27; 15 gn, 11 ms, each axis Enclosure material aluminium (chassis) / zinc plated steel (cover) Mounting (snap-on with self locking spring) for 35 mm DIN-rails as per EN 50022 Connection detachable screw terminal block (plugs included) (TIS 600: fixed screw terminal block) Industrial Power Supplies TIS Series 50–600 Watt Instruction manual can be downloaded under: www.tracopower.com/products/tis-manual.pdf All specifications valid at nominal input voltage, full load and +25 °C after warm-up time unless otherwise stated. http://www.tracopower.com Page 4 of 13 Power Supplies with Redundancy Function With this option a parallel operation of up to 5 units is possible. Decoupling diodes and current share lines allow to build true N +1 redundant systems with active current sharing for all units. This function also includes an alarm relay to signal a single unit failure. This option is available for TIS 150 W, TIS 300 W and TIS 600 W models. Please note: This option cannot be combined with other options. Industrial Power Supplies TIS Series 50–600 Watt Order Code Input Voltage Output Power Output Voltage Output Current (includes terminal plugs) max. nom. max. TIS 150-124 RED 115/230 VAC 150 W 24 VDC 6.0 A TIS 150-148 RED selectable 48 VDC 3.0 A TIS 300-124 RED 115/230 VAC 300 W 24 VDC 12 A TIS 300-148 RED selectable 48 VDC 6.0 A TIS 600-124 RED 115/230 VAC 600 W 24 VDC 24 A TIS 600-148 RED selectable 48 VDC 12 A Models I-Sense Regulator L Con1 Pin3 N 115/230VAC Con1 Pin1 AC Con1 Pin2 DC Common Unit OK Unit OK Con3 - Pin1 Bus Indicator Con2 - Pin1/2 Con2 - Pin3/4 V-Sense +Vout Current Shareline Unit OK Con3 - Pin4 Con3 - Pin3 Con3 - Pin2 -Vout 24/48VDC Specifications Rating per relay contact 60 VDC /0.36 A max. Instruction manual for RED option can be downloaded under: http://www.tracopower.com/products/tis-red_manual.pdf http://www.tracopower.com Page 5 of 13 Power Supplies with Powerfail Functions These models provide 3 functions required in many process control system applications: ◆ AC-Powerfail signal (relay contact) ◆ Power Good signal (relay contact) ◆ Remote On/Off Industrial Power Supplies TIS Series 50–600 Watt Order Code Input Voltage Output Power Output Voltage Output Current (includes terminal plugs) max. nom. max. TIS 150-124 SIG 115/230 VAC 150 W 24 VDC 6.0 A TIS 150-148 SIG selectable 48 VDC 3.0 A TIS 300-124 SIG 115/230 VAC 300 W 24 VDC 12 A TIS 300-148 SIG selectable 48 VDC 6.0 A TIS 600-124 SIG 115/230 VAC 600 W 24 VDC 24 A TIS 600-148 SIG selectable 48 VDC 12 A Models Remote ON/OFF L 115/230VAC Con1 Pin1 N Con1 Pin2 Con1 Pin3 AC DC Mains Fail Detection Mains OK Remote ON/OFF +Vout Con2 - Pin3/4 -Vout 24/48VDC Common AC-Powerfail Con3 - Pin2 Con3 - Pin7 Con3 - Pin6 Con2 - Pin1/2 Output OK Power Good Detection Power Good Common Power Good Power Good Con3 - Pin5 Con3 - Pin4 Con3 - Pin3 + - Con3 - Pin1 (Relay A) (Relay B) Specifications Power Good signal trigger point models with 24 Vout: >22.8 VDC ±0.5 V relay B closed (pin 4 – pin 3) models with 48 Vout: >45.6 VDC ±1.0 V relay B closed (pin 4 – pin 3) AC-Powerfail signal Vin <93 resp. <187 VAC relay A closed (pin 7 – pin 6) Raiting per relay contact 60 VDC /0.36 A max. Remote On/Off – On short circuit con 3 pin 1 and pin 2 – Off open circuit con 3 pin 1 and pin 2 Instruction manual for SIG option can be downloaded under: http://www.tracopower.com/products/tis-sig_manual.pdf http://www.tracopower.com Page 6 of 13 DC-UPS-System Industrial Power Supplies TIS Series 50–600 Watt In addition to the standard power supply function, these models include a professional battery management system to charge and monitor an external battery. In the event of a power failure the battery is switched automatically and without any interruption to the DC output. Once mains power is available again, the battery is switched off. The backup time is limited only by battery capacity and load. Charge current and voltage can be adjusted to values as required by battery type. Power fail and low battery alarm signals are available via two independent relay contacts. During normal operation the battery status is monitored by periodically loading the battery for a short time. If a cell resistance is high, there is a relay alarm is available. The battery is fully protected under any operational conditions. The power supply is short circuit protected even in battery backup operation but, for safety reasons, the battery should be fitted with a fast blow fuse. Battery mode can be activated by interconnecting pin 7 and 8. Complete external battery packs (3.2 Ah or 7 Ah standard) with lead batteries and circuit breaker are available (see page 8). Order Code 1) Input Voltage Output Power Output Voltage Output Current 2) max. nom. max. TIS 300-124 UDS 115/230 VAC 300 W 24 VDC 12 A selectable TIS 600-124 UDS 115/230 VAC 600 W 24 VDC 24 A selectable Models 1) Includes terminal plugs, does not include batteries 2) reduce max. output current by battery charging current http://www.tracopower.com Page 7 of 13 DC-UPS-System Industrial Power Supplies TIS Series 50–600 Watt Battery ON/OFF Con4 Pin7 L 115/230VAC Con1 Pin1 Con4 Pin8 N Con1 Pin2 Battery - Battery + Con1 Pin3 Con3 - Pin1 Con3 - Pin2 AC DC Mains Fail Detection Battery Test Battery OK Battery Low / failure Common Low Battery Con4 - Pin4 AC-Powerfail Con4 - Pin6 Con4 - Pin5 Battery Switch Logic I V Battery Charger +Vout Con2 - Pin3/4 -Vout 24VDC Common AC-Power OK AC-Powerfail Con4 - Pin3 Con4 - Pin2 Con4 - Pin1 Con2 - Pin1/2 Output OK VBat>18V Bat ON/OFF Mains Fail (Relay B) (Relay A) Specifications Charging current (factory set) TIS 300-124 UDS: 1.2 A TIS 600-124 UDS: 2.4 A Adjustment range of charging current TIS 300-124 UDS: 0.15 – 1.5 A TIS 600-124 UDS: 0.25 – 2.5 A Holding current for charged battery at voltage 27.3 VDC <50 mA Overload or short circuit during battery operation system switches off AC-Powerfail signal Vin <93 or <187 VAC relay A closed (pin 2 – pin 3) Low battery signal – Battery voltage below 22 V relay B closed (pin 5 – pin 6) – Raiting per relay contact 60 VDC /0.36 A max. During battery charge operation output current reduction by 1.4 x battery charge current Instruction manual for UDS option can be downloaded under: http://www.tracopower.com/products/tis-uds_manual.pdf http://www.tracopower.com Page 8 of 13 Battery-Pack for DC-UPS Systems The battery pack contains high quality, maintenance free lead-acid batteries with 3.2 Ah or 7.0 Ah capacity. The batteries are fixed together with a re-settable electronic fuse on a solid mounting frame. Together with power supply models TIS 300-124 UDS or TIS 600-124 UDS the battery pack provides a complete and reliable DC-UPS system. Backup time depends on load current and battery capacity. Industrial Power Supplies TIS Series 50–600 Watt Order Code Battery Voltage Battery Capacity Permissable Charge (25 °C, 20 h-rate) Current max. TIS 24-32AP 24 VDC 3.2 Ah 1.2 A TIS 24-70AP 24 VDC 7.0 Ah 2.4 A Models Specifications Max. charge voltage 27 – 27.6 VDC Temperature coefficient –36 mV/°C Temperature range – at charge operation –15°C to +50°C – at load operation –20°C to +60°C – Storage –20°C to +60°C Average lifetime on standby operation at tA =20°C 4 – 5 years (Limited Warranty on Battery) Cable length 1.0 m Cable diameter TIS 24-32 AP: 2.5 mm2 (AWG 12) TIS 24-70 AP: 4.0 mm2 (AWG 11) Weight TIS 24-32 AP: 2.9 kg (6.4 lb) TIS 24-70 AP: 4.1 kg (9.1 lb) Recommended combinations TIS 24-32 AP: TIS 300-124 UDS (power supplies) TIS 24-70 AP: TIS 600-124 UDS http://www.tracopower.com Page 9 of 13 100.0 (3.94) 75 (2.95) 37.5 (1.48) 74.0 (2.91) 56.7 (2.23) 26 (1.02) 5 (0.2) 31.5 (1.24) 10 (0.39) TIS 50-112 Input 115/230 VAC 1,2/0,7 A L N 12 VDC 3,5 A Output + – Industrial Power Supply Model DC-ON adj 114.6 (4.51) 90 (3.54) 45 (1.77) 10 (0.39) 56.7 (2.23) 86.5 (3.4) 34 (1.34) 5 (0.2) 39.5 (1.56) TIS 75-112 Input 115/230 VAC 1,7/0,9 A L N 12 VDC 6 A Output + – Industrial Power Supply Model DC-ON adj 114.6 (4.51) 10 (0.39) 157 (6.18) 56.7 (2.23) 38.5 80 (3.15) (1.52) 86.5 (3.4) 34 (1.34) 5 (0.2) 39.5 (1.56) TIS 150-124 Input 115/230 50/60Hz 3,7/1,7 A N L 24 VDC / 6 A Output + – Industrial Power Supply Model DC-ON Case Dimensions Industrial Power Supplies TIS Series 50–600 Watt TIS 50 models TIS 75 models Weight: 0.48 kg (1.06 lb) Weight: 0.80 kg (1.76 lb) TIS 150 models Weight: 0.41 kg (0.9 lb) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) TIS PLUG-1 Connector Set for TIS 50/ 75/ 150 TIS PLUG-1-RED Connector Set for TIS 150-1xx RED Connectors ( Included in shipment) http://www.tracopower.com Page 10 of 13 114.6 (4.51) 10 (0.39) 83 (3.27) 38.5 (1.52) 130 (5.12) 83 (3.27) 207 (8.15) 91.5 (3.6) (1.36) 34.5 34 (1.34) 5 (0.2) 39.5 (1.56) TIS300-172 Input 115/230 50/60Hz 5,4/3,3 A N L 72 VDC / 4 A Output + – Industrial Power Supply Model DC-ON + – 83 (3.27) 130 (5.12) 220 (8.66) 46 (1.81) 130 (5.12) 10 (0.39) (0.2) 94 (3.7) 41.5(1.63) 5 47 (1.85) TIS 500-124-230 Input 230 VAC 50/60Hz 5,3 A N L 24 VDC / 20 A Output + – Industrial Power Supply Model DC-ON + – Case Dimensions Industrial Power Supplies TIS Series 50–600 Watt TIS 300 models Weight: 1.4 kg (3.09 lb) Weight: 1.9 kg (4.19 lb) TIS 500 models Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) TIS PLUG-3 Connector Set for TIS 300 TIS PLUG-3-RED Connector Set for TIS 300-1xx RED TIS PLUG-3-UDS Connector Set for TIS 300-1xx UDS TIS PLUG-5 Connector Set for TIS 500 Connectors ( Included in shipment) http://www.tracopower.com Page 11 of 13 6.8 (0.27) 82.8 (3.26) 177.2 (6.98) 32 (1.26) 120.2 (4.73) 82.6 (3.25) 179 (7.05) 243 (9.57) TIS 600-124 Input 115/230 VAC 50/60Hz 10,5/6,4 A N L 24 VDC / 20 A Output – + Industrial Power Supply Model – + Outline Dimensions mm (inches) Industrial Power Supplies TIS Series 50–600 Watt TIS 600 models Weight: 2.0 kg (4.41 lb) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) TIS PLUG-6-RED Connector Set for TIS 600-1xx RED TIS PLUG-6-UDS Connector Set for TIS 600-1xx UDS Connectors ( Included in shipment) http://www.tracopower.com Page 12 of 13 Optional Mounting Systems Industrial Power Supplies TIS Series 50–600 Watt Wall mounting kit B A C 7.5 (0.30) D E 4.6 (0.18) TIS 75 MK-75 37 (1.46) 14.5 (0.57) – 134.5 (5.30) 150.5 (5.93) TIS 150 MK-150 132 (5.20) 13.5 (0.53) 105 (4.13) 134.5 (5.30) 150.5 (5.93) TIS 300 MK-300 132 (5.20) 13.5 (0.53) 105 (4.13) 134.5 (5.30) 150.5 (5.93) TIS 500 MK-500 132 (5.20) 13.5 (0.53) 105 (4.13) 134.5 (5.30) 150.5 (5.93) TIS 600 MK-600 190 (7.48) 37.5 (1.48) 115 (4.53) 197.0 (7.76) 207.0 (8.15) Models Order code A B C D E Rugged DIN-Rail mounting kit 4.2 (0.17) 25 (0.98) 50.1 (1.97) A B C countersink M4 TIS 150 RMK-150 150 (5.91) 115 (4.53) 35 (1.38) TIS 300 RMK-300 200 (7.87) 165 (6.50) 35 (1.38) TIS 500 RMK-300 200 (7.87) 165 (6.50) 35 (1.38) TIS 600 standard 180 (7.09) 165 (6.50) 15 (0.59) Models Order code A B C Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Page 13 of 13 Outline Dimensions mm (inches) Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Industrial Power Supplies TIS Series 50–600 Watt TIS 24-32AP Weight (incl. batteries): TIS 24-32AP 2.9 kg (6.4 lb) TIS 24-70AP TIS 24-70AP 4.1 kg (9.1 lb) A B A B 204 (8.03) 184 (7.24) 69 (2.72) Detail B Detail A 9 (0.35) 5.8 (0.23) 12 (0.47) 14 (0.55) 7 (0.28) 100 (3.94) 135 (5.14) 7 (0.28) B A 272 (10.71) 252 (9.92) B A 100 (3.94) 69 (2.72) 152 (5.98) Rev. May 17. 2013 Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) http://www.tracopower.com Industrial DC/DC-Converter TCL-DC Series, 24 to 60 Watt Features ◆ Ultra-wide input voltage range ◆ Output voltage adjustable ◆ Overload and short circuit protection ◆ Low ripple and noise ◆ I/O isolation 1500 VDC ◆ Compact, slim plastic case ◆ Reliable snap-on mount on DIN-rail ◆ Bracket for wall mount included ◆ 3-year product warranty In the TCL range of DIN-rail power supplies are 6 models for DC input voltage available. The wide input ranges of 9.5–18 VDC resp. 18–75 VDC means these models can be operated from all popular DC supply voltage systems. With tightly regulated output voltage these DC/DC converters provide a reliable power source for sensitive loads in industrial process controls, factory automation and other equipment exposed to a critical industrial environment. Further applications for these converters are isolation of a specific load or refreshing the 24 V bus voltage. Easy installation is provided with snap-on mounting on DIN-rails and detachable screw terminal block. Order Code Input Voltage Range Output Voltage Output Current max. TCL 012-124 DC 9.5 – 18.0 VDC 24 VDC 1.0 A TCL 024-105 DC 5 VDC 5.0 A TCL 024-112 DC 18 – 75 VDC 12 VDC 2.0 A TCL 024-124 DC 24 VDC 1.0 A TCL 060-112 DC TCL 060-124 DC 18 – 75 VDC 12 VDC 24 VDC 5.0 A 2.5 A Models Page 1 of 3 UL 508 CB Scheme http://www.tracopower.com Industrial DC/DC-Converter TCL-DC Series 24 to 60 Watt Input Specifications Input power at no load 1.0 Watt max. Start-up voltage/under voltage shut down TCL 012 model: 8.4 VDC / 7.6 VDC TCL 024 & TCL 060 models: 17.2 VDC / 15.7 VDC Reverse polarity protection by internal fuse Efficiency 86 % typ. Output Specifications Output voltage adj. range 5 VDC model: 5.0 – 5.25 VDC 12 VDC models: 12.0 – 15.0 VDC 24 VDC models: 24.0 – 28.0 VDC Regulation – Input variation Vin min. to Vin max. 0.5 % max – Load variation 0...100% 0.5 % max Ripple and noise (20 MHz bandwidth) <50 mV pk-pk Electronic short circuit protection current limitation at 110 % typ. (constant current, automatic recovery) Overvoltage protection, trigger point 5 VDC model: <6.5 V 12 VDC models: <24 V 24 VDC models: <42 V General Specifications Temperature ranges – Operating –25°C to +70°C max. – Storage (non operating) –25°C to +85°C Temperature derating 1.5 %/K above +50°C Humidity (non condensing) 95 % rel. H max. Temperature coefficient 0.02 %/K Switching frequency 55 – 180 kHz depending on load (frequency modulation) Isolation voltage (60 sec.) – Input/Output 1500 VDC Reliability, calculated MTBF at +25°C (according to IEC 61709) >2.5 Mio h Safety standards – Information technology equipment IEC 60950-1, EN 60950-1 (output SELV), UL Std. 60950-1 (2nd Edition) +Am1:2011, CAN/CSA-C22.2 No. 60950-1-07 +Am1:2011 – Industrial control equipment UL 508 – Electronic equipment for power installation EN 50178 – Electrical equipment for machines EN 60204 Safety approvals – CB test certificate (IEC 60950-1) www.tracopower.com/products/tcl-cb.pdf – UL approval www.ul.com -> certifications UL 508C listed, CSA C22.2 No.14 File e210002 – CSA certification UL 60950-1, CSA 60950-1-03 www.tracopower.com/products/tcl-csa.pdf – GS certification www.tracopower.com/products/tcl060dc_gs.pdf Electromagnetic compatibility (EMC), emissions EN 61000-6-3 – Conducted RI suppression on input EN 55022 class B – Radiated RI suppression EN 55022 class B Electromagnetic compatibility (EMC), immunity EN 61000-6-2 – Electrostatic discharge (ESD) EN 61000-4-2 4 kV / 8 kV – Radiated RF field immunity EN 61000-4-3 10 V/m – Electrical fast transient / burst immunity EN 61000-4-4 Level 3 – Surge immunity EN 61000-4-5 Level 3 – Immunity to conducted RF disturbances EN 61000-4-6 10 Vrms Environmental compliance – Reach www.tracopower.com/products/reach-declaration.pdf – RoHS RoHS directive 2011/65/EU Case protection IP 20 (IEC 60529) Enclosure material plastic UL 94V-0 rated Mounting DIN-rails as per EN 50022-35x15/7.5 (snap-on with self-locking spring) bracket for wall/chassis mount included Installation instructions www.tracopower.com/products/tcl-dc-inst.pdf All specifications valid at nominal input voltage, full load and +25 °C after warm-up time unless otherwise stated. Page 2 of 3 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Industrial DC/DC-Converter TCL-DC Series 24 to 60 Watt Rev. October 18. 2013 Page 3 of 3 27 (1.06) 2.2 (0.09) 100.0 (3.94) 75.0 (2.95) DC-ON LED Output voltage adjust INPUT 1 2 3 OUTPUT 1 2 Output Input 1 + Vout 1 Protective earth 2 – Vout 2 –Vin 3 +Vin Weight: 140g (4.9 oz) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Case Dimensions Wall Mounting Bracket Instead on a DIN-rail, the modules can be also mounted on a chassis or wall with help of a mounting bracket which is supplied as standard with each Converter 75.0 (2.95) 100.0 (3.94) 3.2 (0.13) 45 (1.77) DC-ON LED Output voltage adjust OUTPUT 1 1 2 2 INPUT 1 2 3 TCL 012 and TCL 024 models TCL 060 model Weight: 265 g (9.4 oz) Output Input 1 + Vout 1 Protective earth 2 – Vout 2 –Vin 3 +Vin http://www.tracopower.com DC/DC Converters TOS Series, Point-of-Load (POL) Converter Features  Small size, low profile  SMT package or SIP version  Cost-efficient open frame design  Wide input voltage ranges  Output voltages trim from 0.75 VDC to 5.5 VDC  Delivers up to 30 A with minimal derating  Ultra high efficiency to 96 %  Fast transient response  Remote On/Off control  Wide temperature range –40°C to +85°C  SMT package fully DOSA compatible  Lead free design – RoHS compliant The TOS series is a range of high performance non-isolated dc-dc converters With very high efficiency that can supply up to 30A of output current. These modules provide precisely regulated output voltages which can be set via an external resistor to a value from 0.75 VDC to 5.5 VDC. These converters work over a wide input voltage range of 2.4 to 5.5 VDC or 8.3 to 14.0 VDC.Further features include remote On/Off, under voltage lockout, over temperature and over current protection. These products have an open-frame construction with very small footprint and are available in an industry standard SIP or in a SMT package. The TOS series is fully RoHS compliant and can withstand industry standard handling, cleaning and the high temperatures of lead-free reflow solder processes. Order code SMT-version Input voltage range Output voltage range Output current max. Efficiency typ. TOS 06-05SM 6 A 94 % TOS 10-05SM 2.4 – 5.5 VDC 0.75 – 3.3 VDC** 10 A 93 % TOS 16-05SM 16 A 95 % TOS 06-12SM 6 A 89 % TOS 10-12SM 8.3 – 14.0 VDC 0.75 – 5.0 VDC 10 A 93 % TOS 16-12SM 16 A 92 % SIL-version TOS 06-05SIL 6 A 94 % TOS 10-05SIL 2.4 – 5.5 VDC 0.75 – 3.3 VDC* 10 A 93 % TOS 16-05SIL 16 A 95 % TOS 06-12SIL 6 A 89 % TOS 10-12SIL 8.3 – 14 VDC 0.75 – 5.0 VDC 10 A 93 % TOS 16-12SIL 16 A 92 % Models * 25 A output voltage higher than 2.75 VDC ** Max output voltage to be adjusted min. 0.5 VDC below impressed input voltage Page 1 of 4 Order code SMT-version Input voltage range Output voltage range Output current max. Efficiency typ. TOS 30-05SM 4.5 – 5.5 VDC 0.80 – 3.6 VDC 30 A 93 % TOS 30-12SM 6.0 – 14.0 VDC 0.80 – 3.6 VDC 30 A* 92 % SIL-version TOS 30-05SIL 4.5 – 5.5 VDC 0.80 – 5.5 VDC 30 A 93 % TOS 30-12SIL 6.0 – 14.0 VDC 0.80 – 5.5 VDC 30 A* 92 % Models Datasheet for 30A Models see: www.tracopower.com/products/tos30.pdf http://www.tracopower.com DC/DC Converters TOS Series, POL Converter Input Specifications Input current no load – Vin 5 VDC (at Vout min./Vout max.) 6 A models: 20 mA / 45 mA typ. 10 A models: 25 mA / 30 mA typ. 16 A models: 25 mA / 40 mA typ. – Vin 12 VDC (at Vout min./Vout max.) 6 A models: 17 mA / 100 mA typ. 10 A models: 40 mA / 100 mA typ. 16 A models: 40 mA / 100 mA typ. Stand by input current (at remote Off) 6 A models: 1 mA typ. 10 A / 16 A models: 2 mA typ. Max. input current – Vin 5 VDC 6 A models: 6 A 10 A models: 10 A 16 A models: 16 A – Vin 12 VDC 6 A models: 4.5 A 10 A models: 7 A 16 A models: 10 A Start up voltage / under voltage lockout 5 Vin models: 2.2 VDC / 2.0 VDC typ. 12 Vin models: 7.9 VDC / 7.8 VDC typ. Start up time (power / remote On till Vout set) 8 mS typ. Reflected ripple current – Vin 5 VDC 6 A models: 35 mA typ. (with input filter) 10 A / 16 A models: 100 mA typ. – Vin 12 VDC 6 A models: 30 mA typ. 10 A models: 20 mA typ. 16 A models: 20 mA typ. Input filter external (recommended) 2 x 150 μF low ESR polymer capacitors and 2 x 47 μF ceramic capacitors Output Specifications Voltage set accuracy ±2 % max. (see page 3 for set up) Voltage balance (dual output models) ±1 % max. Regulation – Input variation ±0.3 % max. – Load variation 0 – 100 % ±0.4 % max. Dynamic load response – 50 % load change (upper half) with external 1 μF ceramic- and 10 μF tantalum capacitors max. peak variation / response time Vin 5 VDC, 6 A models: 130 mV / 60 μS typ. Vin 12 VDC, 6 A models: 200 mV / 35 μS typ. Vin 5 VDC, 10 A models: 200 mV / 25 μS typ. Vin 12 VDC, 10 A models: 200 mV / 25 μS typ. Vin 5 VDC, 16 A models: 300 mV / 25 μS typ. Vin 12 VDC, 16 A models: 200 mV / 25 μS typ. – 50 % load change (upper half) with external 2 x 150 μF polymer capacitors Vin 5 VDC, 6 A models: 50 mV / 100 μS typ. Vin 12 VDC, 6 A models: 50 mV / 50 μS typ. Vin 5 VDC, 10 A models: 100 mV / 100 μS typ. Vin 12 VDC, 10 A models: 100 mV / 25 μS typ. Vin 5 VDC, 16 A models: 150 mV / 100 μS typ. Vin 12 VDC, 16 A models: 100 mV / 50 μS typ. Ripple and noise (20 MHz Bandwidth) 5 Vin models: 50 mV pk-pk max. 12 Vin models: 75 mV pk-pk max Temperature coefficient ±0.4 % typ. Over current protection at +200 % of Iout max. typ. Short circuit protection indefinite, automatic recovery Capacitive load – ESR <1 mOhm 1000 μF max. – ESR <10 mOhm 6 A models: 3000 μF max. 10 A / 16 A models: 5000 μF max. All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Page 2 of 4 http://www.tracopower.com DC/DC Converters TOS Series, POL Converter General Specifications Temperature ranges – Operating –40°C to +85°C – Storage –55°C to +125°C Derating see application note Over temperature protection at +125°C typ. Humidity (non condensing) 95 % rel H max. Reliability, calculated MTBF (Bellcore TR-NWT-000332) 6 A models: >20 mio. h at +40°C 10 A / 16 A models: >14 mio. h at +40°C Switching frequency 300 kHz typ. (pulse width modulation - PWM) Remote On/Off On: 1 VDC to Vin max. or open circuit. (reference to GND) Off: 0 to 0.3 VDC Physical Specifications Weight 6 A models: 2.8 g 10 A / 16 A models: 6.0 g Soldering profile – SIL - Version max. 265°C / 10 sec. (wave soldering) – SMT - Version peak temp. 245°C for 10 sec. max., 217°C for 90 sec. max. (Convection reflow solder process is recommended) Output Voltage Adjustment Rd GND Prog Load (+Vout) Vo 5 VDC input models: Rd [Ohm] = 21070 – 5110 Vo – 0.7525 12 VDC input models: Rd [Ohm] = 10570 – 1000 Vo – 0.7525 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Page 3 of 4 Application note: www.tracopower.com/products/tos-application.pdf Jenatschstrasse 1 · CH-8002 Zurich · Switzerland Tel. +41 43 311 45 11 · Fax +41 43 311 45 45 · info@traco.ch · www.tracopower.com DC/DC Converters TOS Series, POL Converter Outline Dimensions mm (inches) Rev. 12/12 Surface Mount (SMT-Version) Single-in-Line (SIL-Version) 10.2 (0.40) 22.9 (0.90) 3.29 (0.13) 20.32 (0.8) Vin GND Prog Vout On/Off 6 A output Models Vin GND Prog Vout On/Off 0.70 (0.028) 6.65 (0.26) 10A & 16A output models Sens No Pin 0.64 (0.025) 0.51 (0.02) 1.28 (0.05) 3.24 (0.128) 1.18 (0.046) 8.28 (0.33) 0.51 (0.02) 0.64 (0.025) 1.28 (0.05) 5 x 2.54 (5 x 0.10) 4 x 2.54 (4 x 0.10) 50.8 (2.00) 12.7 (0.50) 25.4 (1.0) Vin Vout Vout GND 2.54 (0.1) 15.24 (0.6) 17.78 (0.7) 1.5 11.4 (0.45) 2.29 20.3 (0.8) (0.09) (0.05) 1.3 1.57 8.9 (0.35) (0.82) 4.06 (0.16) 4.06 (0.16) 4.57 (0.18) 17.52 (0.69) (0.06) 8.64 (0.34) Vin GND Prog Vout On/Off 1.57 (0.82) 5.97 (0.24) Bottom View 6 A output Models 1.9 13.5 (0.53) 2.84 33.0 (1.3) (0.112) (0.05) 1.3 1.57 10.92 (0.43) (0.82) 4.83 (0.19) 4.83 (0.19) 7.54 (0.30) 29.9 (1.18) (0.075) 10.29 (0.41) Vin GND Vout Prog On/Off 1.57 (0.82) 8.28 (0.33) Bottom View 10A & 16A output models 4.83 (0.19) 4.83 (0.19) No Pin Sens Page 4 of 4 Specifications can be changed any time without notice. http://www.tracopower.com Page 1 of 6 AC/DC Power Modules TML Series, 5to 30 Watt The TML series are ultra compact AC/DC power supplies in a fully encapsulated plastic case. They feature versions with screw terminals for easy installation or with solder pins for direct PCB mounting. International safety approvals qualify this product for worldwide markets. The TML series AC/DC modules offer an interesting solution for many space critical applications in commercial and industrial electronic equipment. Features ◆ Encapsulated power Supplies ◆ PCB mount or chassis mount with screw terminals ◆ Single, dual and triple output models ◆ Universal input 85–264 VAC, 47–440 Hz ◆ EMI meets EN 55022, class B and FCC, level B ◆ Low ripple and noise ◆ Short circuit and overload protection ◆ 3-year product warranty Order Code Output Power max. Output 1 Output 2 Output 3 TML 05105 5 VDC/1000 mA TML 05112 12 VDC/416 mA TML 05115 15 VDC/333 mA TML 05124 5 Watt 24 VDC/200 mA TML 05205 5 VDC/500 mA –5 VDC/500 mA TML 05212 12 VDC/200 mA –12 VDC/200 mA TML 05215 15 VDC/160 mA –15 VDC/160 mA TML 10105 5 VDC/2000 mA TML 10112 12 VDC/833 mA TML 10115 15 VDC/666 mA TML 10124 10 Watt 24 VDC/416 mA TML 10205 5 VDC/800 mA –5 VDC/800 mA TML 10212 12 VDC/380 mA –12 VDC/380 mA TML 10215 15 VDC/300 mA –15 VDC/300 mA Models LVD UL 60950-1 http://www.tracopower.com Page 2 of 6 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. AC/DC Power Modules TML Series 5 to 30 Watt Input Specifications Input voltage ranges – AC input 85–264 VAC – DC Input TML 30 models: 100 – 370 VDC output power derating 1 %/V below 110 VDC other models: 85 – 370 VDC output power derating 0.8 %/V below 110 VDC Input frequency 47–440 Hz Input current no load 115 VAC / 230 VAC TML 5 models: 10 mA / 15 mA typ TML 10 models: 15 mA / 20 mA typ TML 15 models: 18 mA / 25 mA typ. TML 30 models: 30 mA / 55 mA typ. Input current full load 115 VAC / 230 VAC TML 5 models: 160 mA / 80 mA typ. TML 10 models: 200 mA / 120 mA typ TML 15 models: 280 mA / 165 mA typ. TML 30 models: 550 mA / 320 mA typ. External fuse (required) 1.5 A slow blow type (recommendation) Order Code Output Power Output 1 Output 2 Output 3 PCB-mounting Chassis mounting max. TML 15105 TML 15105C 5 VDC/3000 mA TML 15112 TML 15112C 12 VDC/1250 mA TML 15115 TML 15115C 15 VDC/1000 mA TML 15124 TML 15124C 24 VDC/625 mA TML 15205 TML 15205C 15 Watt 5 VDC/1500 mA –5 VDC/1500 mA TML 15212 TML 15212C 12 VDC/650 mA –12 VDC/650 mA TML 15215 TML 15215C 15 VDC/500 mA –15 VDC/500 mA TML 15512 TML 15512C 5 VDC/2000 mA 12 VDC/200 mA –12 VDC/200 mA TML 15515 TML 15515C 5 VDC/2000 mA 15 VDC/150 mA –15 VDC/150 mA TML 30103 TML 30103C 3.3 VDC/6000 mA TML 30105 TML 30105C 5 VDC/6000 mA TML 30112 TML 30112C 12 VDC/2500 mA TML 30115 TML 30115C 15 VDC/2000 mA TML 30124 TML 30124C 24 VDC/1250 mA TML 30205 TML 30205C 30 Watt 5 VDC/3000 mA –5 VDC/3000 mA TML 30212 TML 30212C 12 VDC/1300 mA –12 VDC/1300 mA TML 30215 TML 30215C 15 VDC/1000 mA –15 VDC/1000 mA TML 30252 TML 30252C *5 VDC/3000 mA *12 VDC/1250 mA TML 30512 TML 30512C * 5 VDC/3000 mA 12 VDC/630 mA –12 VDC/630 mA TML 30515 TML 30515C *5 VDC/3000 mA 15 VDC/500 mA –15 VDC/500 mA Models * Output floating http://www.tracopower.com Page 3 of 6 AC/DC Power Modules TML Series 5 to 30 Watt Output Specifications Voltage set accuracy ± 2 % Regulation – Input variation 0.3 % max. – Load variation (10–100%) single output models: 1.0 % max. dual / triple output models: 5 % max. Minimum load single output models: 5 % dual output models: 3 % (each output) triple output 15W models: 10 % (main output only) triple output 30W models: 20 % (each output) Ripple and noise (20 MHz bandwidth) – 3.3 & 5 VDC output models: <1.5 % of Vout – other models: <1.0 % of Vout Current limitation 120– 80 % fold back Short circuit protection hiccup mode, indefinite (automatic recovery) Maximum capacitive load 470–50’000 μF depending on model General Specifications Temperature ranges – Operating –25 °C to +60 °C – Power derating above 50 °C 3.75 %/°C – Storage (non operating) –40 °C to +85 °C Temperature coefficient 0.02 %/°C Efficiency 72–80 % (depending on model) Humidity (non condensing) 95 % rel max. Switching frequency 100 kHz typ. (pulse width modulation PWM) Hold-up time 40 ms min. (Vin 115...230 VAC) Isolation voltage – Input/Output 3‘000 VAC Reliability /calculated MTBF (MIL-HDBK-217F at +25°C, ground benign) >660’000 h EMI / RFI conducted EN 55022, class B, FCC part 15, level B EMC compliance – Electrostatic discharge ESD IEC / EN 61000-4-2 4 kV / 8 kV – RF field susceptibility IEC / EN 61000-4-3 3 V/m – Electrical fast transients/bursts on mainsline IEC / EN 61000-4-4 1 kV Safety class II (only 30 watt models) to IEC / EN 60536 Safety standards UL 60950-1, IEC/EN 60950-1 Safety approval cUL/UL File e188913 www.ul.com -> certifications Case material plastic resin + fiberglass (flammability to UL 94-V0) Environmental compliance – Reach www.tracopower.com/products/tml-reach.pdf – RoHS RoHS directive 2011/65/EU All specifications valid at nominal input voltage, full load and +25 °C after warm-up time unless otherwise stated. http://www.tracopower.com Page 4 of 6 AC/DC Power Modules TML Series 5 to 30 Watt Outline Dimensions TML 5 Models Pin diameter ø 1.0 mm TML 10 Models Weight: 80 g (2.8 oz) Weight: 95 g (3.4 oz) ( ) = Inches Tolerances = 0.5mm (0.02) 1 2 3 4 5 6 45.0 (1.77) 17.5 ±0.3 (0.69 ±0.012) 17.5 ±0.3 (0.69 ±0.012) 4.0 (0.16) 47.0 ±0.3 (1.85 ±0.012) 55.0 (2.17) 10 ±0.3 (0.39 ±0.012) 10 ±0.3 (0.39 ±0.012) 20.5 (0.81) 10 (0.39) Bottom view Bottom view 1 2 3 4 5 45.0 (1.77) 20.5 (0.79) 10 (0.39) 17.5 ±0.3 (0.69 ±0.012) 4.0 (0.16) 6 17.5 ±0.3 (0.69 ±0.012) 54.0 ±0.3 (2.13 ±0.012) 64.0 (2.52) 10 ±0.3 (0.39 ±0.012) 10 ±0.3 (0.39 ±0.012) Pin diameter ø 1.0 mm Pin Single Dual 1 FG FG 2 AC(N) AC(N) 3 AC(L) AC(L) 4 –V out –V out 5 NC Common 6 +V out +V out Pin-Out Pin Single Dual 1 FG FG 2 AC(N) AC(N) 3 AC(L) AC(L) 4 –V out –V out 5 NC Common 6 +V out +V out Pin-Out NC = Not to connect NC = Not to connect http://www.tracopower.com Page 5 of 6 AC/DC Power Modules TML Series 5 to 30 Watt Outline Dimensions TML 15 Models PCB mounting: TML 15-C Models Chassis mounting: Bottom view 1 2 3 8 7 6 5 4 54.0 (2.13) 20.0 ±0.3 (0.79 ±0.012) 20.0 ±0.3 (0.79 ±0.012) 6.0 (0.24) 62.0 ±0.3 (2.44 ±0.012) 74.0 (2.91) 8.5 ±0.3 (0.33 ±0.012) 8.5 ±0.3 (0.33 ±0.012) 11.5 ±0.3 (0.45 ±0.012) 11.5 ±0.3 (0.45 ±0.012) 22.0 (0.87) 10 (0.39) Top view 54.0 (2.13) 5.0 (0.20) 86.0 ±0.3 (3.39 ±0.012) 96.0 (3.78) 4 x ø3.5 (4 x ø0.14) 1 2 3 8 7 6 5 4 27.6 (1.08) 5.0 (0.20) 46.0 ±0.3 (1.81 ±0.012) Pin diameter ø 1.0 mm Weight: 120 g (4.2 oz) Weight: 150 g (5.3 oz) Pin Single Dual Triple 1 FG FG FG 2 AC(N) AC(N) AC(N) 3 AC(L) AC(L) AC(L) 4 No Pin No Pin –V out 3 5 –V out –V out Com. 2/3 6 No Pin Common +V out 2 7 +V out +V out –V out 1 8 No Pin No Pin +V out 1 Pin-Out Page 6 of 6 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com AC/DC Power Modules TML Series 5 to 30 Watt TML 30 Models PCB mounting: 1 2 7 6 5 4 3 Bottom view 63.5 (2.50) 27.9 ±0.3 (1.10 ±0.012) 3.8 (0.15) 81.3 ±0.3 (3.20 ±0.012) 88.9 (3.50) 15.24 ±0.3 (0.60 ±0.012) 12.7 ±0.3 (0.50 ±0.012) 12.7 ±0.3 (0.50 ±0.012) 15.24 ±0.3 (0.60 ±0.012) 25.0 (0.98) 6 (0.24) 27.9 ±0.3 (1.10 ±0.012) Top view 1 2 7 6 5 4 3 31.0 (1.22) 5.5 (0.22) 64.7 (2.55) 50.0 ±0.3 (1.97 ±0.012) 6.0 (0.20) 100.0 ±0.3 (3.94 ±0.012) 112.0 (4.41) 4 x ø3.5 (4 x ø0.14) NC TML 30-C Models Chassis mounting: Pin diameter ø 1.0 mm Weight : 230 g (8.1 oz) Weight : 275 g (9.7 oz) Dimensions in[mm], () = Inches Tolerances = 0.5mm (0.02) Pin Single Dual sym. Dual asym. Triple 1 AC(N) AC(N) AC(N) AC(N) 2 AC(L) AC(L) AC(L) AC(L) 3 +V out +V out +V out 2 +V out 2 4 No Pin No Pin +V out 1 +V out 1 5 –V out Common –V out 2 Com. 2/3 6 No Pin No Pin –V out 1 –V out 1 7 NC. –V out NC. –V out 3 Pin-Out Rev. February 14. 2014 Outline Dimensions NC = Not to connecthttp://www.tracopower.com Features ◆ Shielded metal case with screw terminals ◆ Compact dimensions: 98 x 52 x 34 mm ◆ Ultra-wide 4:1 input voltage range ◆ Very high efficiency up to 87% ◆ Constant current output characteristic for battery load applications ◆ Optional with input filter to meet EN55022 class B ◆ Overtemperature protection ◆ Wide Operating temperature range: –40°C to +75°C ◆ Reverse input protection ◆ Under voltage lock-out ◆ I/O isolation 2250 VDC ◆ Easy chassis and wall mounting ◆ 3-year product warranty DC/DC Converters TEP 150WI Series, 150 Watt The TEP-150WI Series is a family of high power density dc-dc converter modules with ultra-wide 4:1 input voltage range which come in an ultra-compact metal case with screw terminal connection. Suitable for a wide range of applications, the TEP-150WI series was particularly designed with industrial applications in mind. The modules have flanges for easy chassis or wall mounting. A very high efficiency allows an operating temperature up to +50°C with natural convection cooling. Further features include adjustable output voltage with constant current characteristic for battery charger applications. Page 1 of 5 Order code* Input voltage Output voltage Output current max. Efficiency typ. TEP 150-2412WI 12 VDC 12.5 A 86 % TEP 150-2413WI 9 – 36 VDC 15 VDC 10 A 86 % TEP 150-2415WI (24 VDC nominal) 24 VDC 6.3 A 87 % TEP 150-2416WI 28 VDC 5.4 A 87 % TEP 150-2418WI 48 VDC 3.2 A 86 % TEP 150-4812WI 12 VDC 12.5 A 87 % TEP 150-4813WI 18 – 75 VDC 15 VDC 10 A 87 % TEP 150-4815WI (48 VDC nominal) 24 VDC 6.3 A 88 % TEP 150-4816WI 28 VDC 5.4 A 88 % TEP 150-4818WI 48 VDC 3.2 A 87 % TEP 150-7212WI 12 VDC 12.5 A 86 % TEP 150-7213WI 43 – 160 VDC 15 VDC 10 A 86 % TEP 150-7215WI (72 VDC nominal) 24 VDC 6.3 A 87 % TEP 150-7216WI 28 VDC 5.4 A 87 % TEP 150-7218WI 48 VDC 3.2 A 86 % Options suffix –F Modules with input filter to meet EN 55022 class B, see page 5 on demand Negative (passive = Off) remote On/Off function (standard is passive = On)range Models CB Scheme UL 60950-1 http://www.tracopower.com Input Specifications Input current (no load) 24 Vin, 12 – 24 VDC models: 80 mA typ. 24 Vin, 28 – 48 VDC models: 130 mA typ. 48 Vin, 12 – 24 VDC models: 60 mA typ. 48 Vin, 28 – 48 VDC models: 70 mA typ. 110 Vin, 12 – 24 VDC models: 30 mA typ. 110 Vin, 28 – 48 VDC models: 40 mA typ. Start-up voltage / under voltage lock-out 24 Vin models: 9 VDC / 8.2 VDC typ. 48 Vin models: 18 VDC / 16.2 VDC typ. 110 Vin models: 43 VDC / 34.5 VDC typ. Surge voltage (1sec. max.) 24 Vin models: 50 V 48 Vin models: 100 V 110 Vin models: 170 V Conducted noise (input) EN 55022 class A, FCC part 15, class A without external components. optional filter for class B – suffix F ESD (electrostatic discharge) EN 61000-4-2, air ±8 kV, contact ±6 kV, perf. criteria A Radiated immunity EN 61000-4-3, 10 V/m, perf. criteria A Fast transient / Surge (with input capacitor for models without filter module) EN 61000-4-4, ±2 kV, perf. criteria A EN 61000-4-5, ±1 kV perf. criteria A – Input capacitor: 24 VDC models: Nippon chemi-con KY 470 μF, 50 V, ESR 45 mOhm 48 VDC models: Nippon chemi-con KY 220 μF, 100 V, ESR 48 mOhm 110 VDC models: Nippon chemi-con KXJ series, 150 μF, 200V models with filter module (suffix F): no input capacitor required Conducted immunity EN 61000-4-6, 10 Vrms, perf. criteria A Reverse voltage protection parallel diode (input fuse required) Recommended input fuse (slow blow) 24 Vin models: 15 A 48 Vin models: 10 A 72 Vin models: 5 A Output Specifications Voltage set accuracy ±1 % Output voltage adjustment +20 % by external resistor (see application note) Regulation – Input variation Vin min. to Vin max. 0.2 % max. – Load variation 0 – 100 % 0.4 % max. Temperature coefficient ±0.02 %/K Minimum load not required Ripple and noise (20 MHz Bandwidth) 12 & 15 VDC models: 100 mVpk-pk max. 24 & 28 VDC models: 200 mVpk-pk max. 48 VDC models: 350 mVpk-pk max. Start up time (nominal Vin and constant resistive load) 25 ms typ. (at power On or remote On) Transient response (25 % load step change) 200 μs typ. Output current – Constant voltage (CV) up to 110 % of Iout max. – Constant current (CC) above 110 % of Iout max. Over voltage protection at 125 –140 % of Vout nom. Short circuit protection indefinite, automatic recovery Capacitive load 12 VDC models: 40‘000 μF max. 15 VDC models: 26‘000 μF max. 24 VDC models: 10‘000 μF max. 28 VDC models: 7‘600 μF max. 48 VDC models: 2‘600 μF max. DC/DC Converters TEP 150WI Series 150 Watt Page 2 of 5 http://www.tracopower.com DC/DC Converters TEP 150WI Series 150 Watt General Specifications Temperature ranges – Operating –40°C to +75°C – Case temperature +100°C max. – Storage –55°C to +125°C Thermal consideration – Mounting surface Optimize thermal coupling to heat conducting surface. Not to mount on flammable surface! – Derating and temperature test point see application note Over temperature protection at 110°C (auto restart) Vibration and thermal shock acc. MIL-STD-810F Humidity (non condensing) 95 % rel H max. Reliability, calculated MTBF (MIL-HDBK-217F, at +40°C, ground benign) >135‘000 h Isolation voltage (60 sec.) – Input/Output 2250 VDC (functional insulation) – Input/Case 1500 VDC – Output/Case 1500 VDC Isolation capacitance – Input/Output 3500 pF max. Isolation resistance – Input/Output (500 VDC) >1 GOhm min. Switching frequency 220 – 330 kHz depending on model (puls width modulation) Safety standards UL 60950-1, IEC/EN 60950-1 Safety approvals – UL/cUL 60950-1 www.ul.com -> certifications -> File e188913 – CB test certificate (IEC 60950-1) www.tracopower.com/products/tep150wi-cb.pdf (72 Vin models pending) Remote On/Off – positive logic (standard) – On: 3 to 12 VDC or open circuit – Off: 0 to 1.2 VDC or short circuit pin 5 and 3 – negative logic (option -N) – On: 0 to 1.2 VDC or short circuit pin 5 and 3 – Off: 3 to 12 VDC or open circuit – Off idle current: 3 mA Environmental compliance – Reach www.tracopower.com/products/tep150wi-reach.pdf – RoHS RoHS directive 2011/65/EU Physical Specifications Casing material metal Potting material silicon (UL 94V-0 rated) Case protection IP 50 (in accordance to IEC/EN60529) Weight 300 g (10.6 oz) All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Page 3 of 5 Application note: www.tracopower.com/products/tep150wi-application.pdf (72 Vin models pending) http://www.tracopower.com DC/DC Converters TEP 150WI Series 150 Watt Page 4 of 5 Weight: 300g (10.6 oz) Dimensions in [mm], () = Inch Mounting slot tolerance: ±0.25 (±0.001) Case tolerances: ±0.5 (±0.02) Outline Dimensions 52.5 65.0 1.2 35.7 (2.07) (2.56) (1.6) (0.05) 59.0 (2.07) 98.0 (3.86) 56.0 (2.20) 21.0 (0.83) 4 x r2 (0.08) 1 2 3 4 5 6 7 8 9 Pin Connection pin function recommended wire 1 + Vin 14 – 16 AWG 2 + Vin 14 – 16 AWG 3 – Vin 14 – 16 AWG 4 – Vin 14 – 16 AWG 5 Remote On/Off 14 – 24 AWG 6 + Vout 14 – 16 AWG 7 – Vout 14 – 16 AWG 8 Trim 14 – 24 AWG 9 Trim 14 – 24 AWG Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Rev. June 14. 2013 Page 5 of 5 DC/DC Converters TEP 150WI Series 150 Watt Outline Dimensions Pin Connection 52.5 65.0 1.2 35.7 (2.07) (2.56) (1.6) (0.05) 59.0 (2.07) 139.5 (5.49) 56.0 (2.20) 21.0 (0.83) 6 x r2 (0.08) 160.5 (6.32) 1 2 3 4 5 6 7 8 9 90.0 (3.54) 18.7 (0.74) Weight: 435g (15.3 oz) Dimensions in [mm], () = Inch Mounting slot tolerance: ±0.25 (±0.001) Case tolerances: ±0.5 (±0.02) pin function recommended wire 1 + Vin 14 – 16 AWG 2 + Vin 14 – 16 AWG 3 – Vin 14 – 16 AWG 4 – Vin 14 – 16 AWG 5 Remote On/Off 14 – 24 AWG 6 + Vout 14 – 16 AWG 7 – Vout 14 – 16 AWG 8 Trim 14 – 24 AWG 9 Trim 14 – 24 AWG http://www.tracopower.com Page 1 of 11 Enclosed Power Supplies TXL Series, 15– 1000 Watt Features ◆ Compact metal case with screw terminal block ◆ Dual and triple output models with isolated outputs ◆ Universal input 85–264 VAC ◆ EMI/EMC compliance with EN 61000-6-3 and EN 61000-6-1 ◆ Compliance to EN 61000-3-2 (PFC) ◆ Short circuit and overvoltage protection ◆ International safety approvals ◆ 3-year product warranty Order Code Case Type Output Power max. Output Voltage nom. Output Current max. TXL 015-3.3S 3.3 VDC 3.0 A TXL 015-05S 5 VDC 3.0 A TXL 015-12S B 15 Watt 12 VDC 1.3 A TXL 015-15S 15 VDC 1.0 A TXL 015-24S 24 VDC 0.63 A TXL 015-48S 48 VDC 0.32 A TXL 025-3.3S 3.3 VDC 6.0 A TXL 025-05S 5 VDC 5.0 A TXL 025-12S C 25 Watt 12 VDC 2.1 A TXL 025-15S 15 VDC 1.7 A TXL 025-24S 24 VDC 1.1 A TXL 025-48S 48 VDC 0.57 A TXL 035-3.3S D 3.3 VDC 9.0 A TXL 035-05S 5 VDC 7.0 A TXL 035-12S 35 Watt 12 VDC 3.0 A TXL 035-15S 15 VDC 2.4 A TXL 035-24S 24 VDC 1.5 A TXL 035-48S 48 VDC 0.8 A TXL 050-05S 5 VDC 10.0 A TXL 060-12S 50 / 60 Watt 12 VDC 5.0 A TXL 060-15S 15 VDC 4.0 A TXL 060-24S 24 VDC 2.5 A Models with Single Output The TRACOPOWER TXL series is a family of encased power supplies designed for a wide range of cost critical applications. With a low profile metal case and screw terminal block connection, they are easy to install in any equipment. There are 64 models in this range with single, dual, and triple output voltages from 3.3 VDC to 48 VDC in 12 power ranges from 15 W to 1000 W. These power supplies have universal input and comply with European EMC standards and the Low Voltage Directive (LVD). http://www.tracopower.com Page 2 of 11 Enclosed Power Supplies TXL Series 15–1000 Watt Order Code Case Type Output Power max. Output Voltage nom. Output Current max. TXL 060-3.3S 3.3 VDC 15.0 A TXL 060-05S 5 VDC 12.0 A TXL 070-12S E 60 / 70 Watt 12 VDC 6.0 A TXL 070-15S 15 VDC 4.8 A TXL 070-24S 24 VDC 3.0 A TXL 070-48S 48 VDC 1.5 A TXL 100-3.3S 3.3 VDC 23.0 A TXL 100-05S 5 VDC 20.0 A TXL 100-12S J 100 Watt 12 VDC 8.5 A TXL 100-15S 15 VDC 7.0 A TXL 100-24S 24 VDC 4.3 A TXL 100-48S 48 VDC 2.3 A TXL 150-05S 5 VDC 30.0 A TXL 150-12S L 150 Watt 12 VDC 12.5 A TXL 150-24S 24 VDC 6.3 A TXL 150-48S 48 VDC 3.2 A TXL 230-12S 12 VDC 19.2 A TXL 230-24S N 230 Watt 24 VDC 9.6 A TXL 230-48S 48 VDC 4.8 A TXL 350-24S O 350 Watt 24 VDC 14.7 A TXL 350-48S 48 VDC 7.5 A TXL 750-24S P 750 Watt 24 VDC 31.3 A TXL 750-48S 48 VDC 15.8 A TXL 1000-24S Q 1000 Watt 24 VDC 40.0 A TXL 1000-48S 48 VDC 21.0 A Models with Single Output Order Code Case Type Output Power max. * Output1 (Main Output) * Output 2 * Output 3 TXL 035-0512D +5 VDC/ 4.0 A +12 VDC/ 2.5 A TXL 035-0524D D 35 Watt +5 VDC/ 4.0 A +24 VDC/ 1.3 A TXL 035-1212D +12 VDC/ 3.0 A –12 VDC/ 1.5 A TXL 035-1515D +15 VDC/ 2.4 A –15 VDC/ 1.5 A TXL 060-0512DI 5 VDC/ 8.0 A 12 VDC/ 4.0 A TXL 060-0524DI 5 VDC/ 6.0 A 24 VDC/ 2.2 A TXL 060-0521TI E 60 Watt 5 VDC/ 8.0 A 12 VDC/ 3.5 A 5 VDC/ 1.0 A TXL 060-0522TI 5 VDC/ 7.0 A 12 VDC/ 3.5 A 12 VDC/ 1.0 A TXL 060-0533TI 5 VDC/ 7.0 A 15 VDC/ 3.0 A 15 VDC/ 1.0 A TXL 060-0534TI 5 VDC/ 6.0 A 12 VDC/ 1.5 A 24 VDC/ 1.2 A TXL 100-0512DI 5 VDC/ 12.0 A 12 VDC/ 7.0 A TXL 100-0524DI 5 VDC/ 12.0 A 24 VDC/ 3.5 A TXL 100-0521TI J 100 Watt 5 VDC/ 12.0 A 12 VDC/ 5.0 A 5 VDC/ 1.5 A TXL 100-0522TI 5 VDC/ 12.0 A 12 VDC/ 5.0 A 12 VDC/ 1.5 A TXL 100-0533TI 5 VDC/ 12.0 A 15 VDC/ 4.0 A 15 VDC/ 1.5 A TXL 100-0534TI 5 VDC/ 12.0 A 12 VDC/ 4.0 A 24 VDC/ 2.0 A Models with Multiple Output * Total power must not exceed specified max. output power http://www.tracopower.com Page 3 of 11 Enclosed Power Supplies TXL Series 15–1000 Watt Input Specifications Input voltage range – nominal 100 – 240 VAC – AC range (universal input) 85 – 264 VAC for 15 to 350 Watt model 90 – 264 VAC for 750 & 1000 Watt models – DC range 120 – 375 VDC for 15 to 350 Watt model 127 – 375 VDC for 750 & 1000 Watt models Input voltage frequency 47 – 63 Hz Input current (at full load) Vin = 115 VAC Vin = 230 VAC TXL 015/025 models: 0.50 A typ. 0.22 A typ. TXL 035 models: 0.70 A typ. 0.42 A typ. TXL 060/070 models: 1.00 A typ. 0.60 A typ. TXL 100 models: 1.65 A typ. 0.95 A typ. TXL 150 models: 2.10 A typ. 1.10 A typ. TXL 230 models: 3.20 A typ. 1.70 A typ. TXL 350 models: 3.30 A typ. 1.70 A typ. TXL 750 models: 8.0 A typ. 3.90 A typ TXL 1000 models: 11.0 A typ. 5.0 A typ. Input current (at no load) Vin = 115 VAC Vin = 230 VAC TXL 015/025 models: 10 mA typ. 17 mA typ. TXL 035 models: 50 mA typ. 55 mA typ. TXL 230/350 models: 115 mA typ. 140 mA typ. TXL 750 models: 210 mA typ. 220 mA typ. TXL 1000 models: 330 mA typ. 350 mA typ. other models: 100 mA typ. 80 mA typ. Recommended circuit breaker up to 70 Watt models: 5 A (characteristic C) or slow blow fuse up to 350 Watt models: 10 A TXL 750 & 1000 Watt models: 16 A Output Specifications Output voltage adjustment range ±10 % – 35 Watt dual output models: range Vout 1–2 – other multi output models: Vout 1 Regulation – Input variation 1 % max. – Load variation (10–100%) single output models: 2 % max. multiple output models: 4 % max. for main output 6 % max. for output 2/3 (20–100 % load) – Minimum load on main output of multiple output models: 0.3 A for TXL 035 (to provide the regulation on the auxilary outputs) 1.0 A for TXL 060 1.5 A for TXL 100 Ripple and noise (20 MHz bandwidth) 3.3 VDC output < 50 mV Output 3 (on triple output models) < 1.5 % of Vout all other output voltages < 1.0 % of Vout nom. Output current limitation 105 % – 150 % of Iout max. Overload protection mode Fold back, automatic recovery Over voltage protection (only output 1) 115 % – 140 % of Vout nom. (depending on model) Capacitive load, max. www.tracopower.com/products/txl-capload.pdf http://www.tracopower.com Page 4 of 11 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. General Specifications Temperature ranges – Operating –10°C to +70°C – Load derating above +45°C 2 %/°K (2.5 %/°K for TXL 120/230/1000) – Storage (non operating) –10°C to +75°C Temperature coefficient 0.02 %/°C Efficiency 70 – 84 % (depending on model) Humidity (non condensing) 85 % rel max. (non condensing) Switching frequency 50 kHz typ. (pulse width modulation) Hold-up time 20 ms min. Isolation voltage (60 sec.) – Input/Output 3‘000 VAC – Input/Case 1‘500 VAC – Output/Case 500 VAC – Output/Output 60–100 Watt multiple output models: 500 VAC (for all outputs of triple output models!) 35 Watt dual output models: outputs not isolated Reliability /calculated MTBF (MIL-HDBK-217F, at +25°C typ., ground benign) >250’000 h Electromagnetic compatibility – Conducted input RI suppression EN 55022, class B, FCC part 15, level B (EMC), Emissions – Harmonic current emissions IEC/EN 61000-3-2, class D (TXL 120/150/220) IEC/EN 61000-3-2, class A (others) – Flicker IEC/EN 61000-3-3 Electromagnetic compatibility – Electrostatic discharge ESD IEC/EN 61000-4-2 4 kV / 8 kV (EMC), Immunity – RF field immunity IEC/EN 61000-4-3 3 V/m – Electrical fast transients/burst immunity IEC/EN 61000-4-4 1 kV – Surge IEC/EN 61000-4-5 1 kV / 2 kV – Conducted RF IEC/EN 61000-4-6 3 V/m – Magnetic field IEC/EN 61000-4-8 3 A/m – Voltage dip IEC/EN 61000-4-11 Safety standards UL 60950-1, IEC/EN 60950-1 2nd edition Safety approvals – UL/cUL www.ul.com -> certifications -> File: e188913 – CB report TXL 015 models: www.tracopower.com/products/txl015-cb.pdf TXL 025 models: www.tracopower.com/products/txl025-cb.pdf TXL 035 models: www.tracopower.com/products/txl035-cb.pdf TXL 060/070 models: www.tracopower.com/products/txl060-cb.pdf TXL 100 models: www.tracopower.com/products/txl100-cb.pdf TXL 150 models: www.tracopower.com/products/txl150-cb.pdf TXL 230 models: www.tracopower.com/products/txl230-cb.pdf TXL 350 models: www.tracopower.com/products/txl350-cb.pdf TXL 750 models: www.tracopower.com/products/txl750-cb.pdf TXL 1000 models: www.tracopower.com/products/txl1000-cb.pdf Environmental compliance – Reach www.tracopower.com/products/txl-reach.pdf – RoHS RoHS directive 2011/65/EU Casing material TXL 025/035 nickel plated steel (chassis & cover) TXL 50/60/70/100 aluminium (chassis), nickel plated steel (cover) others aluminium (chassis & cover) Enclosed Power Supplies TXL Series 15–1000 Watt http://www.tracopower.com Page 5 of 11 Case Dimensions Enclosed Power Supplies TXL Series 15–1000 Watt 82 10 max. 99 (0.39 max.) (3.90) 55 (2.17) 23.5 (0.93) 45 (1.77) 74 (2.91) 7 (0.28) 17.5 (0.69) 35 (1. 38) (3.23) 3 1 45 6 2 2 x M3 THD (bottom) Top view 2x M3 THD Case C Case D Weight: 0.19 kg (6.7 oz) Weight: 0.3 kg (10 oz) single dual 1 AC L AC L 2 AC N AC N 3 AC FG AC FG 4 –Vout Common 5 +Vout Vout 1 6 No con. Vout 2 Connection Max mounting screw penetration: 2.0 mm (0.08) LN Vout 2x M3 THD 14 max. 79 (0.55 max.) (3.11) 55 11 (2.17) (0.43) 65 (2.56) 3 (0.12) 14.5 (0.57) 28.5 (1.12) 51 (2.0 1) 25.5 (1.0) Top view 2 x M3 THD (bottom) Case B LN Vout 2x M3 THD 14 max. 62 (0.55 max.) (2.44) 39.1 14.7 (1.54) (0.58) 11.5 (0.45) 15.1 (0.59) 28.0 (1.10) 51 (2.0 1) 25.25 (0.99) Top view 2 x M3 THD (bottom) + 39.1 (1.54) Weight: 0.13 kg (4.6 oz) http://www.tracopower.com Page 6 of 11 Enclosed Power Supplies TXL Series 15–1000 Watt Case E 10 max. 159 (0.39 max.) (6.26) 32 (1.26) 78 57 (3.07) (0.95) 118 19 (4.65 ) (0.75) 18 (0.71) 19 (0.75) 38 (1.50) 95 (3.74) 1234567 123456789 Dual & Triple output models Single output Top view 2 x M3 THD (bottom) 10 (0.39) 3 x M3 THD Case J 10 max. 198 (0.39 max.) (7.80) 9 (0.35) 80 (3.15) 120 (4.72) 4 x M3 THD (bottom) 1234567 123456789 Dual & Triple output models Single output 158 (6.22) 20 (0.79) 18 (0.71) 19 (0.75) 10 (0.39) 38 (1.50) 95 (3.74) 16.5 (0.45) Top view 3 x M3 THD Single Dual Triple 1 AC L AC L AC L 2 AC N AC N AC N 3 AC FG AC FG AC FG 4 –Vout No con. +Vout 3* 5 –Vout No con –Vout 3* 6 +Vout –Vout 1 –Vout 1 7 +Vout +Vout 1 +Vout 1 8 – –Vout 2 –Vout 2 9 – +Vout 2 +Vout 2 Connection Case Dimensions Weight: 0.7 kg (25 oz) Weight: 0.8 kg (28 oz) Single Dual Triple 1 AC L AC L AC L 2 AC N AC N AC N 3 AC FG AC FG AC FG 4 –Vout No con. +Vout 3* 5 –Vout No con –Vout 3* 6 +Vout –Vout 1 –Vout 1 7 +Vout +Vout 1 +Vout 1 8 – –Vout 2 –Vout 2 9 – +Vout 2 +Vout 2 Connection Max mounting screw penetration: 3.0 mm (0.12) * Opposite polarity for TXL 060-0534TI * Opposite polarity for TXL 100-0534TI http://www.tracopower.com Page 7 of 11 Enclosed Power Supplies TXL Series 15–1000 Watt Case Dimensions Case L 13 max. 198 (0.51 max.) (7.83) 50 (1.97 ) 99 (3.90) 10 (0.39) 28 (1.10) 79 (3.11) 10 (0.39) 168 (6.61) Vout L N ++ 49.5 (1.95) 2 x M4 thread (bottom) 65 (2.56) 63 (2.48) 117 (4.61) 56 25 (0.98) 12.5 (0.49) (2.20) 11.5 (0.45) (0.83) 21 (0.49) 12.5 176.5 (6.95) 6 x M4 THD 4 x M3 THD (bottom) Top view Weight: 0.89 kg (31 oz) 4x TXL-CMB chassis mount brackets included in shipment Max mounting screw penetration: 3.0 mm (0.12) http://www.tracopower.com Page 8 of 11 Enclosed Power Supplies TXL Series 15–1000 Watt Outline Dimensions 99 (3.9) 45 (1.77) Vout L N ++ 12 max. 198 (0.47 max.) (7.8) 117 (4.61) 56 25 (0.98) 12.5 (0.49) (2.20) 11.5 (0.45) (0.83) 21 (0.49) 12.5 176.5 (6.95) V adj. RC RS +--+ 65 (2.56) 10 (0.39) 168 (6.61) 63 (2.48) 6 x M4 THD air flow 10 (0.39) 28 (1.10) 79 (3.11) 49.5 (1.95) 2 x M4 THD (bottom) 4 x M3 THD (bottom) Top View 115 (4.53) 50 (1.97 ) 12 max. 212 (0.47 max.) (8.35) Vout L N +++ 7 (0.28) 177.5 (6.99) 87.5 (3.44) 10 (0.39) 95 (3.74) 54.5 (2.15) 29.5 (1.16) 150 (5.91) 50 (1.97) 32.5 (1.28) 4 x M4 THD 5 x M3 THD (bottom) (bottom) 29.5 (1.16) 150 ±0.8 (5.91 ±0.03) 25 ±0.8 (0.98 ±0.03) 12.5 (0.49) air flow 4 x M4 THD Weight: 1.05 kg (37 oz) Case N Case O Weight: 0.88 kg (30 oz) Max mounting screw penetration: 3.0 mm (0.12) RC Remote Control On/Off: RC+/RC–: 0–0.7 V = On 3–10 V = Off. RS Remote Sense Can be open or connected to the load under regard of polarity Connector 4x TXL-CMB chassis mount brackets included in shipment 4x TXL-CMB chassis mount brackets included in shipment http://www.tracopower.com Page 9 of 11 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Enclosed Power Supplies TXL Series 15–1000 Watt Outline Dimensions Case P Weight: 3.5 kg (123 oz) Max mounting screw penetration: 3.0 mm (0.12) 30 20 13 39 220 16 25 210 40 6 113 6 12.5 30 240 5 40 220 15 34.5 20 8.5 5 16.5 30 16.5 275 S/N LABEL MODE L LABE L 63 125 6 (bottom) 6 (bottom) 113(bottom) 6 29(bottom) 240(bottom) 25 145 125 210 40 air flow CN3 pin consideration: Pin 1: Current sharing to interconnect up to 3 units at parallel operation Max power = units x 0.9, max deviation of voltage adjustment among units =100mV Pin 2: Power Good Signal. TTL (3mA max.): 0 – 1 VDC = DC-Off, 3.3 – 5.6 VDC = DC-OK Pin 3/4: Remote sense to be connected at load side under regard of polarity Pin 5/6: Remote control input RC1& RC2 Pin 7/8 Auxillary output 12VDC/0.1A for remote control function PSU PSU +v +v +v -v -v -v PSU +V -V LOAD RS-(PIN4) RS+(PIN3) CN3 7 5 3 1 8 6 4 2 CN3 7 5 3 1 8 6 4 2 CN3 7 5 3 1 8 6 4 2 +v +v +v -v -v -v +v +v +v -v -v -v CN3 Parallel operation: AUX RC2 GND 12V SW RC1 2K 330 AUX RC2 RC1 GND 5V SW 12V 470 2K 330 AUX RC2 GND 12V SW RC1 2K 330 Using internal 12V auxiliary output Using internal 12V auxiliary output Using external voltage Remote On/Off function: Mating connector: Housing: HRS DF11-08DS-2C Terminal: HRS DF11-EP22SCB Mating cable with 500mm flyind leeds included! TXL-CMB chassis mount bracket set (4pcs) included in shipment. For dimensions see page 11. Enclosed Power Supplies TXL Series 15–1000 Watt Page 10 of 11 Outline Dimensions Specifications can be changed any time without notice. Case Q Vadj + (10.70) CN15 LED 1 CN14 −V +V +S 5V_AUX DC_OK CS −S GND ON/OFF GND CN15 N L PE 2 4 6 8 1 3 5 7 (bottom) 271.7 3 x M4 THD 20.5 25.4 17.3 7.8 127.0 40.6 295.0 (11.61) 3 x M4 THD 239.5 34.5 18.5 90.0 68.0 air flow air flow (9.43) (1.36) (XXX) (both sides) (0.81) (3.54) (0.73) (5.00) (XXX) (0.31) (1.00) (2.68) Dimensions in [mm], () = Inch Tolerances ±0.8 (±0.03) Monting hole pich tolerances ±0.5 (±0.02) CN14 Jumper on CN14 disables the Remote Off function CN15 On/Off (pin 4 & 6): Contact closed = Power On, Contact open = Power Off CN15 –S/+S (pin 1 & 2): Remote sense to be connected at load side under regard of polarity CN15 5V Aux (pin 3 & 8): Auxiliary output 5 VDC / 0.5 A CN15 DC–OK (pin 5 & 8): TTL signal (2.2 mA max.): 0 – 1 VDC = DC–Off, 3.3 – 5.6 VDC = DC–OK CN15 CS (pin 7): Current Sharing to interconnect up to 4 units at parallel operation Max power = units x 0.9, max deviation of voltage adjustment among units =100mV Parallel operation: 8 6 4 2 7 5 3 1 8 6 4 2 7 5 3 1 8 6 4 2 7 5 3 1 -V +V -V +V -V +V LOAD CN15 PS1 CN15 PS2 CN15 PS3 CS CS CS -S +S -S +S -S +S +S -S Caution! Max mounting screw penetration: 3.0 mm (0.12) Weight: 1.9 kg (67 oz) TXL-CMB1 chassis mount bracket set (4pcs) included in shipment. For dimensions see page 11. Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com AC/DC Power Modules TXL Series 15–1000 Watt Page 11 of 11 Rev. November 15. 2013 Chassi Mount Brackets 17.5 5.6 15.0 16.8 7.5 7.5 15.0 12.5 5.0 Ø4.2 R0.5 7.5 7.5 5.0 10.0 4x7 R1.0 Note: 1. Material: S.P.C.C. 2. Thickness: 0.8mm 3. Treatment: Nickel plated 4. Unit: mm The chassi mount brackets are bypacked along with the following models: Order code: TXL-CMB contains 4pcs brackets and screws For series models: • TXL 150; Case L • TXL 230; Case N • TXL 350; Case O • TXL 750; Case P Order code: TXL-CMB1 contains 4pcs brackets and screws For series models: • TXL 1000; Case Q 5.0 4x7 R1.0 6.9 6.9 6.9 Ø4.2 7.8 12.7 4.9 13.8 15.0 2.8 11.2 5.6 8.6 25.4 http://www.tracopower.com Page 1 of 3 DC/DC Converters TEL 5 Series, 5 Watt Features ◆ Wide 2:1 input range ◆ Cost efficient SMD-design ◆ High power density ◆ High efficiency up to 86% ◆ Regulated outputs ◆ I/O isolation 1’500 VDC ◆ Indefinite short-circuit protection 24-pin DIP with industry standard pinout ◆ High reliability, MTBF >1 Mio. h ◆ Lead free design, RoHS compliant ◆ 3-year product warranty The TEL 5 Series is a range of DC/DC-converter modules with wide input range of 2:1. State of the art SMD-technology guarantees a product with very high reliability and excellent cost /performance ratio. High efficiency allows an operating temperature range of –40°C to +85°C at full load. This product series provides an economical solution for many cost critical applications in industrial and consumer electronics. Ordercode Input voltage range Output voltage Output current max. Efficiency typ. TEL 5-1210 3.3 VDC 1200 mA 77 % TEL 5-1211 9 – 18 VDC 5 VDC 1000 mA 81 % TEL 5-1212 (nominal 12 VDC) 12 VDC 500 mA 84 % TEL 5-1222 ±12 VDC ±250 mA 84 % TEL 5-1223 ±15 VDC ±200 mA 84 % TEL 5-2410 3.3 VDC 1200 mA 79 % TEL 5-2411 18 – 36 VDC 5 VDC 1000 mA 83 % TEL 5-2412 (nominal 24 VDC) 12 VDC 500 mA 86 % TEL 5-2422 ±12 VDC ±250 mA 86 % TEL 5-2423 ±15 VDC ±200 mA 86 % Models UL 60950-1 CB Scheme http://www.tracopower.com Page 2 of 3 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Input Specifications Input current no load /full load 12 Vin models: 20 mA / 590 mA typ. 24 Vin models: 5 mA / 290 mA typ. Start-up voltage / 12 Vin models: 8.0 VDC / 8.0 VDC under voltage shut down 24 Vin models: 16.0 VDC / 16.0 VDC Surge voltage (1 sec. max.) 12 Vin models: 25 V max. 24 Vin models: 50 V max. Reverse voltage protection 1.0 A max. Output Specifications Voltage set accuracy ±1 % Regulation – Input variation Vin min. to Vin max. 0.3 % max. – Load variation 20 – 100 % single output models 1 % max dual output models balanced load 2 % max. Ripple and noise (20 MHz Bandwidth) 75 mVpk-pk max. Temperature coefficient ±0.02 %/K Output current limitation >120 % of Iout max., constant current Short circuit protection continuous (automatic recovery) Capacitive load single output models: 6800 μF max. dual output models: 1000 μF max. (each output) General Specifications Temperature ranges – Operating –40°C to +85°C – Case temperature +90°C – Storage –40°C to +125°C Derating (convection cooling) 3.3 %/K above 70°C Humidity (non condensing) 95 % rel H max. Reliability, calculated MTBF (MIL-HDBK-217F at +25°C, ground benign) >1 Mio. h Isolation voltage (60 sec.) – Input/Output 1’500 VDC Isolation capacitance – Input/Output 380 pF typ. Isolation resistance – Input/Output (500 VDC) >1‘000 M Ohm Switching frequency 300 kHz typ. Safety standards UL/cUL 60950-1, IEC/EN 60950-1 Safety approvals – CB report (SIQ) (IEC/EN 60950-1) www.tracopower.com/products/tel5-cb.pdf – CSA certification (UL 60950-1, CSA 60950-1-03) CSA File No. 226037 http://directories.csa-international.org www.tracopower.com/products/tel5-csa.pdf DC/DC Converters TEL 5 Series 5 Watt Page 3 of 3 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Physical Specifications Casing material non conductive plastic (UL 94V-0 rated) Weight 17 g (0.60 oz) Soldering temperature max. 265°C / 10 sec. Outline Dimensions mm (inches) 5.0 (0.2) 4.5 ±0.5 22.86 (0.9) 20.3 ±0.5 2.54 32 ±0.5 (1.25 ±0.02) 10.2 ±0.5 (0.4 ±0.02) 15.24 (0.6) 9 11 23 22 2 3 16 14 Bottom view 15.24 (0.6) 5.08 2.4 ±0.5 (0.8 ±0.02) (0.1 ±0.02) (0.18 ±0.02) (0.1) (0.2) Pin Single Dual 2 –Vin (GND) –Vin (GND) 3 –Vin (GND) –Vin (GND) 9 No pin Common 11 No con. –Vout 14 +Vout +Vout 16 –Vout Common 22 +Vin (Vcc) +Vin (Vcc) 23 +Vin (Vcc) +Vin (Vcc) Pin-Out Pin diameter ø 0.5 ±0.05 (0.02 ±0.002) Tolerances ±0.5 (±0.02) DC/DC Converters TEL 5 Series 5 Watt Rev. April 19. 2013 http://www.tracopower.com AC/DC Power Modules TMLM Series, 4 to 20 Watt The TMLM Series switching power supplies, offer highest power density in a fully encapsulated module which can be soldered directly on to PCBs. This feature makes these modules an ideal solution for all space critical applications in commercial and industrial electronic equipment. International safety approvals qualify the product for worldwide markets. SMD-technology and high efficiency guarantees a high reliability of these Power Supplies. Features ◆ AC/DC power modules for PCB mounting ◆ Highest power density ◆ Fully encapsulated plastic case ◆ Universal input 90–264 VAC, 47–440 Hz ◆ High efficiency ◆ EMI meets EN 55022, class B and FCC, level B ◆ Low ripple and noise ◆ Short circuit and overload protection ◆ 3-year product warranty Order Code Output Power max. Output 1 Output 2 Efficiency TMLM 04103 4.0 Watt 3.3 VDC / 1200 mA 68 % TMLM 04105 4.0 Watt 5.0 VDC / 800 mA 72 % TMLM 04109 4.0 Watt 9.0 VDC / 444 mA 75 % TMLM 04112 4.0 Watt 12 VDC / 333 mA 76 % TMLM 04115 4.0 Watt 15 VDC / 267 mA 76 % TMLM 04124 4.0 Watt 24 VDC / 167 mA 77 % TMLM 04253 3.5 Watt +5.0 VDC / 600 mA +3.3 VDC / 150 mA 72 % TMLM 04225 3.6 Watt +12 VDC / 250 mA +5.0 VDC / 120 mA 75 % TMLM 05103 4.1 Watt 3.3 VDC / 1250 mA 68 % TMLM 05105 5 Watt 5.0 VDC / 1000 mA 71 % TMLM 05112 5 Watt 12 VDC / 420 mA 75 % TMLM 05115 5 Watt 15 VDC / 333 mA 75 % TMLM 05124 5.5 Watt 24 VDC / 230 mA 77 % TMLM 10103 8.2 Watt 3.3 VDC / 2500 mA 74 % TMLM 10105 10 Watt 5.0 VDC / 2000 mA 79 % TMLM 10112 10 Watt 12 VDC / 833 mA 82 % TMLM 10115 10 Watt 15 VDC / 667 mA 78 % TMLM 10124 10 Watt 24 VDC / 417 mA 80 % TMLM 20103 12 Watt 3.3 VDC / 3600 mA 74 % TMLM 20105 18 Watt 5.0 VDC / 3600 mA 78 % TMLM 20112 20 Watt 12 VDC / 1660 mA 82 % TMLM 20115 20 Watt 15 VDC / 1330 mA 83 % TMLM 20124 20 Watt 24 VDC / 833 mA 83 % Models UL 60950-1 Page 1 of 4 http://www.tracopower.com AC/DC Power Modules TMLM Series 4 to 20 Watt Input Specifications Input voltage – Nominal 100 – 240 VAC – Range 90 – 264 VAC (universal input) – DC range 120 – 370 VDC Input frequency 47 – 440 Hz Input current at full load (115 VAC / 230 VAC) TMLM 04 models: 95 mA / 65 mA typ. TMLM 05 models: 110 mA / 70 mA typ. TMLM 10 models: 220 mA / 150 mA typ. TMLM 20 models: 385 mA / 250 mA typ. Inrush current (<2 ms) (115 VAC / 230 VAC) TMLM 04 models: 15 A max / 25 A max. TMLM 05 & TMLM 10 models: 10 A max / 20 A max. TMLM 20 models: 20 A max / 40 A max. External input fuse required (recommended value) 1.5 A slow blow type Output Specifications Voltage set accuracy ±2 % Regulation – Input variation 0.3 % max. (0.5% max. for TMLM 20 models, 3.0 % max for output 2) – Load variation TMLM 04; 3.3 VDC models: 1.0 % max. (0–100% load) TMLM 04 other models output 1: 0.5 % max. (0–100% load) TMLM 04 output 2: 5.0 % max. (25–100% load) TMLM 05 & TMLM 10 models: 0.5 % max. (5–100% load) TMLM 20 models: 1.0 % max. (5–100% load) Minimum load 0 % (25% for dual output models) operation at 0-load condition will not damage these power supplies, however, they may not meet all listed specifications Ripple and noise (20 MHz bandwidth) TMLM 04; 3.3 VDC models: <250 mV TMLM 04; 5.0 VDC models: <200 mV TMLM 04; other models: <100 mV TMLM 05 & TMLM 10; 3.3 & 5.0 VDC models: <130 mV TMLM 05 & TMLM 10; 12 & 15 VDC models: <210 mV TMLM 05 & TMLM 10; 24 VDC models: <280 mV TMLM 20; 3.3 & 5.0 VDC models: <200 mV TMLM 20; 12 VDC model: <240 mV TMLM 20; 15 VDC model: <300 mV TMLM 20; 24 VDC model: <480 mV Current limitation 120 – 180 % fold back Short circuit protection indefinite (automatic recovery) Overvoltage protection by Zehner diode (main output only) 120 % of Vout typ. Page 2 of 4 Max. capacitive load [μF] Model series Output: TMLM 04 TMLM 05 TMLM 10 TMLM 20 Single output models: 3.3 VDC 14‘000 13‘800 75‘000 4‘500 5.0 VDC 8‘000 6‘000 40‘000 3‘500 9.0 VDC 2‘400 - - - 12 VDC 1‘000 1‘400 8‘500 1‘800 15 VDC 700 1‘000 3‘500 1‘500 24 VDC 220 170 1‘200 1‘200 Dual output models: 5.0 VDC / 3.3 VDC 5‘600 / 4‘700 - - - 12 VDC / 5.0 VDC 330 / 4‘700 - - - http://www.tracopower.com Page 3 of 4 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. General Specifications Temperature ranges – Operating –25°C to +60°C – Storage (non operating) –40°C to +85°C Derating 3.75 %/K above +50°C TMLM 20 models: 2.5 %/K above +40°C Temperature coefficient 0.02 %/K Humidity (non condensing) 95 % rel max. Switching frequency approx. 100 kHz Hold-up time (115 VAC / 230 VAC) TMLM 20 models: 12 ms / 56 ms other models: 15 ms min. Isolation voltage (60 sec.) – Input/ Output 3‘000 VAC Leakage current TMLM 04 models: 0.25 mA max. TMLM 05 models: 0.75 mA max. TMLM 10 models: 0.25 mA max. TMLM 20 models: tba. Reliability /calculated MTBF (MIL-HDBK-217F, at +25°C, ground benign) >330’000 h TMLM 20 models: >250’000 h Electromagnetic compatibility (EMC), emissions EN 55022, class B, FCC part 15, level B Electromagnetic compatibility (EMC), immunity EN 61000-6-2: 2005 Degree of protection class II to IEC/EN 60536 Safety standards UL 60950-1, IEC/EN 60950-1 Safety approvals – UL/cUL 60950-1 www.ul.com -> certifications -> File e188913 – CB test certificate IEC 60950-1 for 4W models: www.tracopower.com/products/tmlm04-cb.pdf – CB test certificate IEC 60950-1 for other models: www.tracopower.com/products/tmlm-cb.pdf Environment – Vibration acc. IEC 60068-2-6; 3 axes, sine sweep, 10-55 Hz, 1g, 1oct/min. – Shock acc. IEC 60068-2-27 20 G (3 directions each 3 times) Environmental compliance – Reach www.tracopower.com/products/tmlm-reach.pdf – RoHS RoHS directive 2011/65/EU Casing material Plastic resin with fiberglass (UL 94V-0 rated) TMLM 04 Models: 21.5 (0.85) 36.5 (1.44) 2 x 3.75 (2 x 0.15) 3.75 (0.15) 1 2 3 4 7 6 5 27.0 (1.06) 3.0 21.0 (0.83) (0.12) 17.1 (0.67) 4.0 (0.16) Bottom view Pin-Out Weight: 26 g (0.92 oz) Pin diameter: 0.5 (0.02) (ntc = not to connect) Outline Dimensions Pin Single Dual 1 ntc ntc 2 +Vout Vout 1 3 –Vout Common 4 ntc Vout 2 5 AC (L) AC (L) 6 AC (N) AC (N) 7 ntc ntc AC/DC Power Modules TMLM Series 4 to 20 Watt Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com AC/DC Power Modules TMLM Series 4 to 20 Watt Weight: 30 g (1.06 oz) Pin diameter: 1.0 (0.04) Rev. September 27. 2013 Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Pin pitch tolerance: ±0.3 (±0.012) Max mounting screw penetration: 3.0 mm (0.12) TMLM 10 Models: Weight: 54 g (1.91 oz) Page 4 of 4 Outline Dimensions AC 25.4 (1.00) 20.32 (0.80) 10.16 (0.40) Bottom view 2.6 (0.81) 2.54 (0.10) 45.72 (1.80) 50.8 (2.00) AC +Vout – Vout 15.16 (0.59) 8.0 (0.31) 23.5 (0.93) 8.0 (0.31) AC 27.2 (1.07) 20.32 (0.80) 10.16 (0.40) Bottom view 3.5 (0.13) 3.4 (0.13) 45.72 (1.80) 52.4 (2.06) AC +Vout – Vout M3 THD 13.65 (0.54) 4.50 (0.18) AC 27.2 (1.07) 20.32 (0.80) 10.16 (0.40) Bottom view 3.5 (0.13) 3.4 (0.13) 45.72 (1.80) 52.4 (2.06) AC +Vout – Vout 23.5 (0.93) 8 (0.31) M3 THD 13.65 (0.54) 4.50 (0.18) TMLM 20 Models: Pin diameter: 1.0 (0.04) Pin diameter: 1.0 (0.04) TMLM 05 Models: Weight: 59 g (2.08 oz) http://www.tracopower.com Features ◆ Ultra compact, low profile plastic casing ◆ Fully encapsulated (pollution/dust) ◆ Single-, dual- and triple output models ◆ 2 package versions: - Screw terminal block for chassis mount - Solder pins for direct PCB mount ◆ DIN-rail mount adaptor (optional) ◆ Universal input 85-264 VAC, 47-440 Hz ◆ Protection class ll ◆ IEC/EN/UL 60950-1 approval, CB-report ◆ Over-temperature protection ◆ Protection against short circuit and oveload ◆ 3-year product warranty The TMP & TMPM series AC/DC Power Modules is a new range of fully encapsulated power supplies in an ultra-compact casing. They feature easy chassis mounting with screw terminal block connection or direct PCB mounting with solder pins. Full compliance with International safety standards for industrial control equipment qualifies the products for worldwide markets. These power supplies offer a cost effective solution for many space critical applications in commercial and industrial electronic equipment and for polluted and dusty environment. AC/DC Power Modules TMP & TMPM Series, 4 to 60 Watt Page 1 of 9 15 to 60 Watt and multi output models see next page --> CB Scheme UL 60950-1 UL 508 Order code Output power max. Output Efficiency PCB-mount with solder pins typ. TMPM 04103 3.3 VDC / 1200 mA 70 % TMPM 04105 5.0 VDC / 800 mA 72 % TMPM 04109 9.0 VDC / 444 mA 75 % TMPM 04112 4 W 12 VDC / 333 mA 76 % TMPM 04115 15 VDC / 267 mA 76 % TMPM 04124 24 VDC / 167 mA 77 % TMP 07103 4.6 W 3.3 VDC / 1400 mA 70 % TMP 07105 5.0 VDC / 1400 mA 73 % TMP 07112 7 W 12 VDC / 583 mA 78 % TMP 07115 15 VDC / 466 mA 78 % TMP 07124 24 VDC / 291 mA 78 % TMPM 10103 8.3 W 3.3 VDC / 2500 mA 70 % TMPM 10105 5.0 VDC / 2000 mA 72 % TMPM 10112 10 W 12 VDC / 833 mA 76 % TMPM 10115 15 VDC / 667 mA 75 % TMPM 10124 24 VDC / 417 mA 72 % TMP 10103 6.6 W 3.3 VDC / 2000 mA 70 % TMP 10105 5.0 VDC / 2000 mA 73 % TMP 10112 10 W 12 VDC / 833 mA 76 % TMP 10115 15 VDC / 666 mA 76 % TMP 10124 24 VDC / 416 mA 76 % Single Output Models 4 to 10 Watt Low profile Small footprint http://www.tracopower.com AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt Page 2 of 9 Order code Output power max. Output Efficiency PCB-mount with solder pins Chassis mount, screw terminal typ. TMP 15105 TMP 15105C 5 VDC / 3000 mA 75 % TMP 15112 TMP 15112C 12 VDC / 1250 mA 79 % TMP 15115 TMP 15115C 15 W 15 VDC / 1000 mA 79 % TMP 15124 TMP 15124C 24 VDC / 625 mA 79 % TMP 15148 TMP 15148C 48 VDC / 310 mA 79 % TMP 30105 TMP 30105C 5 VDC / 6000 mA 78 % TMP 30112 TMP 30112C 12 VDC / 2500 mA 80 % TMP 30115 TMP 30115C 30 W 15 VDC / 2000 mA 80 % TMP 30124 TMP 30124C 24 VDC / 1250 mA 80 % TMP 30148 TMP 30148C 48 VDC / 625 mA 80 % TMP 60105 TMP 60105C 51 W 5.1 VDC / 10‘000 mA 79 % TMP 60112 TMP 60112C 12 VDC / 5000 mA 82 % TMP 60115 TMP 60115C 15 VDC / 4000 mA 83 % TMP 60124 TMP 60124C 60 W 24 VDC / 2500 mA 84 % TMP 60136 TMP 60136C 36 VDC / 1665 mA 84 % TMP 60148 TMP 60148C 48 VDC / 1250 mA 84 % Single Output Models 15 to 60 Watt Peak current, total power not to exceede 30 Watt: 1) 133 % 2) 150 % 3) 200 % Order code Output Output 1 Output 2 Output 3 Eff. PCB-mount Chassis mount power typ. Models with common ground TMPM 04212 +12 VDC / 166 mA –12 VDC / 166 mA 77 % TMPM 04215 4 W +15 VDC / 133 mA –15 VDC / 133 mA 77 % TMPM 04253 +5.0 VDC / 600 mA +3.3 VDC / 150 mA 72 % TMPM 04225 +12 VDC / 250 mA +5.0 VDC / 120 mA 75 % TMP 10212 10 W +12 VDC / 380 mA –12 VDC / 380 mA 77 % TMP 10215 +15 VDC / 300 mA –15 VDC / 300 mA 77 % TMP 15212 TMP 15212C 15 W +12 VDC / 650 mA –12 VDC / 650 mA 79 % TMP 15215 TMP 15215C +15 VDC / 500 mA –15 VDC / 500 mA 79 % TMP 30212 TMP 30212C 30 W +12 VDC / 1300 mA –12 VDC / 1300 mA 80 % TMP 30215 TMP 30215C +15 VDC / 1000 mA –15 VDC / 1000 mA 80 % Models with output 1 isolated from output 2/3 (floating) TMP 15252 TMP 15252C 5.0 VDC / 1500 mA 12 VDC / 625 mA 72 % TMP 15512 TMP 15512C 15 W 5.0 VDC / 2000 mA +12 VDC / 200 mA –12 VDC / 200 mA 74 % TMP 15515 TMP 15515C 5.0 VDC / 2000 mA +15 VDC / 150 mA –15 VDC / 150 mA 74 % TMP 30252 TMP 30252C 5.0 VDC / 3000 mA2) 12 VDC /1250 mA2) 76 % TMP 30512 TMP 30512C 5.0 VDC / 3000 mA2) +12 VDC / 600 mA2) –12 VDC / 600 mA2) 76 % TMP 30515 TMP 30515C 30 W 5.0 VDC / 3000 mA2) +15 VDC / 500 mA2) –15 VDC / 500 mA2) 76 % TMP 30522 TMP 30522C 5.0 VDC / 3000 mA2) +12 VDC / 1000 mA2) –12 VDC / 250 mA3) 76 % TMP 30316 TMP 30316C 3.3 VDC / 4000 mA1) +5.0 VDC / 1500 mA1) +12 VDC / 250 mA3) 71 % TMP 30317 TMP 30317C 5.0 VDC / 4500 mA1) +3.3 VDC / 1000 mA2) +12 VDC / 250 mA3) 71 % Multi Output Models 4 to 30 Watt http://www.tracopower.com AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt Page 3 of 9 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. Max. capacitive load [μF] Model series Output: TMPM 04 TMP 07 TMPM 10 TMP 10 TMP 15 TMP 30 TMP 60 Single output models: 3.3 VDC 1200 2200 2200 3900 - - - 5.0 / 5.1 VDC 800 2200 2200 3300 3900 8000 8000 9.0 VDC 440 - - - - - - 12 / 15 VDC 260 1000 1000 2200 2200 3900 3900 24 VDC 160 680 680 1000 1000 1500 1500 36 VDC - - - - - - 1000 48 VDC - - - - 680 1000 800 Dual output models: 3.3 / 5.0 VDC 4700 - - - 2000 3900 - +12 / –12 / +15 / –15 VDC 260 - - 1000 1500 1500 - Triple output models: 3.3 / 5.0 VDC - - - - 2200 2200 - +12 / –12 / +15 / –15 VDC - - - - 1500 1500 - Input Specifications Input voltage – nominal 100 – 240 VAC – AC range (universal input) 85 – 264 VAC – DC range 120 – 370 VDC Input frequency – nominal 50 / 60 Hz – range 4 – 30 W models: 47 – 440 Hz 60 W models: 47 – 63 Hz Input current at full load – 115 VAC / 230 VAC input 4 W models: 80 mA / 55 mA typ. 7 W models: 150 mA / 100 mA typ. 10 W models: 200 mA / 130 mA typ. 15 W models: 300 mA / 190 mA typ. 30 W models: 550 mA / 330 mA typ. 60 W models: 1050 mA / 670 mA typ. External input fuse required (recommended value) 4 W models: 1.0 A slow blow 7 – 15 W models: 2.0 A slow blow 30 W models: 3.5 A slow blow 60 W models: 6.3 A slow blow Output Specifications Voltage set accuracy ±2 % max. Regulation – Input variation Output 1 1 % max. – Input variation Output 2/3 3 % max. – Load variation TMPM 04103 model (0–100%): 1.5 % max. single and floating outputs (10–100%): 1 % max. (0–100% for TMPM 04 models) common ground outputs balanced load (10–100%): 2.5 % max. common ground outputs unbalanced load (20/90%): 5.0 % max. Minimum load TMPM 04 single and sym.dual models: not required TMPM 04 asym. dual models: 25% per output single and dual output models: 10 % of rated max. current triple output models main output: 10 % of rated max. current triple output models auxiliary outputs: 20 % of rated max. current operation at lower load condition will not damage these power supplies, however, they may not meet all listed specifications. Ripple and noise (20MHz bandwidth) 3.3 VDC & 5.0 VDC outputs: 1.8 % of Vout [mVp-p] other outputs: 1.0 % of Vout [mVp-p] Overload protection by current limit 105 % min. of Inom, fold back, automatic recovery (long term overload condition may cause damage to the power supply) Overvoltage protection by Zehner diode (main output only) 120 % of Vout typ. Start-up time 400 ms typ. Hold-up time 20 ms typ. http://www.tracopower.com Page 4 of 9 AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. General Specifications Temperature ranges – Operating TMPM 04 models: –25°C to +60°C (no derating) TMP 10 models: –25°C to +50°C (no derating) other models: –25°C to +70°C (with derating) – Storage (non-operating) –40°C to +85°C Power derating 3.3 %/K above +50°C to +65°C 5.0 %/K above +65°C to +70°C (no derating aproved for TMPM04 and TMP10 models) Over temperature protection at 90°C (automatic recovery at 67°C) Temperature coefficient 0.02 %/K Humidity (non-condensing) 95 % rel. H max. Switching frequency 100 kHz typ. fixed Isolation voltage (60 sec.) – Input/Output 3‘000 VAC Isolation resistance – Input/Output 100 MOhm (at 500 VDC) Altitude during operation TMP 10, TMPM 04 & 10, : 2‘000 m max. (6’560 ft) approved other models: 3‘000 m max. (9‘840 ft) approved Electromagnetic compatibility (EMC), Emissions EN 61000-6-3: 2007 EN 61204-3: 2000, class A EN 55022, level B, FCC Part 15 level B Electromagnetic compatibility (EMC), Immunity EN 61000-6-2: 2005 EN 61204-3: 2000, class A – Electrostatic discharge ESD EN 61000-4-2 8 kV / 4 kV, criteria B – RF field susceptibility EN 61000-4-3 10 V/m, criteria A – Electrical fast transient / burst immunity input EN 61000-4-4 ±2 kV, criteria B – Electrical fast transient / burst immunity output EN 61000-4-4 ±2 kV, criteria B – Surge immunity line – neutral EN 61000-4-5, ±1 kV, criteria B – Surge immunity output EN 61000-4-5 ±0.5 kV, criteria B – Immunity to conducted RF disturbances EN 61000-4-6 10 V, criteria B – Mains voltage dips and interruptions EN 61000-4-11 30 % 10 ms, criteria B 60 % 100 ms, criteria C 95 % 5000 ms, criteria C EMC test certificates www.tracopower.com/products/tmp-emc.pdf Protection class II to IEC/EN 60536 Safety standards – Information technology equipment IEC/EN 60950-1, UL 60950-1 – Industrial control equipment UL/cUL 508 (chassis mount single and symetric dual output models only) Safety approvals – CB certificate for IEC 60950-1 TMPM 04 models: www.tracopower.com/products/tmpm04-cb.pdf TMP 07 models: www.tracopower.com/products/tmp07-cb.pdf TMP 10 models: www.tracopower.com/products/tmp10-cb.pdf TMPM 10 models: www.tracopower.com/products/tmpm10-cb.pdf TMP 15 models: www.tracopower.com/products/tmp15-cb.pdf TMP 30 single output models: www.tracopower.com/products/tmp30-cb.pdf TMP 30 dual / triple output models: www.tracopower.com/products/tmp30-cb2.pdf TMP 60 models: www.tracopower.com/products/tmp60-cb.pdf – UL approvals for UL 60950-1 www.ul.com -> certifications -> File: e188913 – UL approval for UL 508 (chassis mount models only) www.ul.com -> certifications -> File: e322109 Reliability /calculated MTBF TMP 07, TMPM 04 & 10 models: >330‘000 h (MIL-HDBK-217F, at +25°C, ground benign) TMP 10 models: >300‘000 h TMP 15 models: >280‘000 h TMP 30 models: >250‘000 h TMP 60 models: >125‘000 h Casing material plastic resin + fiberglass (UL 94V-0 rated) Environmental compliance – Reach www.tracopower.com/products/tmp-reach.pdf – RoHS RoHS directive 2011/65/EU http://www.tracopower.com Page 5 of 9 AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt Outline Dimensions Pin diameter: 1.0 (0.04) TMP 07 models: TMP 10 models: Weight: 44 g (1.55 oz) Dimensions in [mm], ( ) = Inches Case tolerances: ±0.5 (±0.02) Pin pich tolerance: ±0.25 (±0.01) 19.3 0.5 6.0 5.0 (0.02) (0.24) (0.76) (0.20) 5.0 (0.20) 2 1 4 3 10.16 25.4 20.32 2.54 45.72 50.80 (0.40) (1.00) (0.80) (0.10) Bottom view (1.80) (2.00) 2.54 (0.10) Pin Single 1 AC (N) 2 AC (L) 3 +Vout 4 –Vout Pinout 2 1 5 4 3 10.16 10.16 45.0 17.78 19.0 0.5 6.0 54.0 64.0 5.0 (0.40) (0.40) (1.77) (0.70) (0.02) (0.24) (0.75) (0.20) 5.0 (0.20) Bottom view (2.13) (2.52) 4.0 (0.16) 22.5 (0.89) Pin Single Dual 1 AC (N) AC (N) 2 AC (L) AC (L) 3 –Vout Vout 2 4 ntc com.1/2 5 +Vout Vout 1 Pinout Pin diameter: 1.0 (0.04) Weight: 92 g (3.25 oz) (ntc = not to connect) TMPM 10 models: 23.5 0.7 10.0 5.0 (0.03) (0.39) (0.93) (0.20) 5.0 (0.20) 2 1 4 3 10.16 27.2 20.32 3.45 45.72 52.4 (0.40) (1.07) (0.80) (0.14) Bottom view (1.80) (2.06) 3.35 (0.13) Pin Single 1 AC (N) 2 AC (L) 3 +Vout 4 –Vout Pinout Pin diameter: 1.0 (0.04) Weight: 54 g (1.90 oz) 7.50 (0.30) Bottom view 14.00 (0.55) 2x3.75 (2x0.15) 3.75 (0.15) 36.5 (1.44) 27.0 (1.06) 3.00 21.00 (0.83) (0.12) 7.50 (0.30) 25.25 (0.99) 17.1 (0.67) 4.0 (0.16) 1 2 3 4 5 6 7 TMPM 04 models: Pin diameter: 0.5 (0.02) Weight: 26 g (0.92 oz) Pin Single Dual 1 ntc 2 ntc 3 +Vout Vout 1 4 –Vout com.1/2 5 ntc Vout 2 6 AC (N) 7 AC (L) Pinout (ntc = not to connect) http://www.tracopower.com Page 6 of 9 AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt Outline Dimensions TMP 15 models for PCB mount: TMP 15 models for chassis mount: Dimensions in [mm], ( ) = Inches Case tolerances: ±0.5 (±0.02) Pin pich tolerance: ±0.25 (±0.01) Mounting hole tolerance: ±0.25 (±0.02) 2 1 6 5 4 11.43 54.0 20.32 62.0 74.0 (0.45) (2.13) (0.80) Bottom view (2.44) (2.91) 3 8.89 (0.35) 7 27.0 (1.06) 11.43 (0.45) 8.89 (0.35) 2 x M4 THD 19.9 (0.78) 19.9 (0.78) 40.0 (1.57) 6.0 (0.24) 19.3 0.5 6.0 5.0 (0.02) (0.24) (0.76) (0.20) 5.0 (0.20) Pin Single Dual sym. Dual asym. Triple 1 AC (N) 2 AC (L) 3 no pin Vout 3 4 –Vout Vout 2 –Vout 2 com.2/3 5 no pin com.1/2 +Vout 2 Vout 2 6 +Vout Vout 1 –Vout 1 –Vout 1 7 no pin +Vout 1 +Vout 1 Pin-Out 3 4 5 6 7 1 2 Top view 86.0 96.0 (3.39) (3.78) 5.0 (0.20) 54.0 (2.13) 4.0 (0.16) 46.0 (1.81) 10.0 76.0 (2.99) (0.39) 23.3 (0.92) 5.0 (0.20 11.8 (0.46) 4 x ø3.5 Pin Single Dual sym. Dual asym. Triple 1 AC (N) 2 AC (L) 3 ntc Vout 3 4 –Vout Vout 2 –Vout 2 com.2/3 5 ntc com.1/2 +Vout 2 Vout 2 6 +Vout Vout 1 –Vout 1 –Vout 1 7 ntc +Vout 1 +Vout 1 Connection (ntc = not to connect) Pin diameter: 1.0 (0.04) Weight: 114 g (4.02 oz) Weight: 162 g (5.71 oz) Max Screw penetration: 5.5 (0.21) http://www.tracopower.com Page 7 of 9 AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt Outline Dimensions TMP 30 models for PCB mount: 2 1 6 5 4 63.5 31.75 81.3 88.9 (2.50) (1.25) Bottom view (3.20) (3.50) 7 3 27.94 (1.10) 12.70 (0.50) 15.24 (0.60) 2 x M4 THD 27.5 (1.08) 3.8 (0.15) 5.0 (0.20) 27.65 (1.09) 12.70 (0.50) 15.24 (0.60) 27.94 (1.10) 21.5 0.5 6.0 5.0 (0.02) (0.24) (0.85) (0.20) 5.0 (0.20) Pin Single Dual sym. Dual asym. Triple 1 AC (N) 2 AC (L) 3 +Vout Vout 1 +Vout 2 Vout 2 4 no pin / ntc +Vout 1 +Vout 1 5 –Vout com.1/2 –Vout 2 com 2/3 6 no pin / ntc –Vout 1 –Vout 1 7 ntc Vout 2 ntc Vout 3 Pinout / Connection (ntc = not to connect) Dimensions in [mm], ( ) = Inches Case tolerances: ±0.5 (±0.02) Pin pich tolerance: ±0.25 (±0.01) Mounting hole tolerance: ±0.25 (±0.02) Pin diameter: 1.0 (0.04) Weight: 177 g (6.24 oz) TMP 30 models for chassis mount: Weight: 191 g (6.74 oz) 3 4 5 6 7 1 2 Top view 100.0 112.0 (3.94) (4.41) 6.0 (0.24) 63.8 (2.51) 6.9 (0.27) 50.0 (1.97) 4 x ø3.5 10.0 92.0 (3.62) (0.39) 25.6 (1.01) 5.0 (0.20) 11.8 (0.46) Max Screw penetration: 5.5 (0.21) http://www.tracopower.com Page 8 of 9 AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt Outline Dimensions TMP 60 models for chassis mount: (ntc = not to connect) Dimensions in [mm], ( ) = Inches Case tolerances: ±0.5 (±0.02) Mounting hole tolerance: ±0.25 (±0.02) Weight: 357 g (12.95 oz) Pin Single 1 AC (N) 2 AC (L) 3 ntc 4 +Vout 5 ntc 6 –Vout 7 ntc Connection 3 4 5 6 7 1 2 Top view 100.0 112.0 (3.94) (4.41) 6.0 (0.24) 67.8 (2.67) 8.9 (0.35) 50.0 (1.97) 4 x ø3.5 10.0 92.0 (3.62) (0.39) 38.0 (1.50) 5.0 (0.20) 11.8 (0.46) TMP 60 models for PCB mount: 2 1 6 4 67.5 33.75 81.3 89.0 (2.66) (1.33) Bottom view (3.20) (3.50) 7 3 27.94 (1.10) 12.70 (0.50) 15.24 (0.60) 2 x M4 THD 27.5 (1.08) 3.85 (0.15) 5.55 (0.219) 27.05 (1.065) 12.70 (0.50) 15.24 (0.60) 27.94 (1.10) 34.0 0.5 6.0 5.0 (0.02) (0.24) (1.34) (0.20) 5.0 (0.20) Weight: 345 g (12.17 oz) Pin diameter: 2.0 (0.08) Pin Single 1 AC (N) 2 AC (L) 3 no pin 4 +Vout 6 –Vout 7 no pin Pinout Max Screw penetration: 5.5 (0.21) Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Page 9 of 9 AC/DC Power Modules TMP & TMPM Series 4 to 60 Watt DIN-Rail Mounting Kit Order code For models TMP-MK1 TMP 15xxxC TMP-MK2 TMP 30xxxC & TMP 60xxxC DIN-Rail Mounting Kit Adapter for mounting on DIN-rails as per EN 50022-35 (snap-on mounting) Specifications can be changed any time without notice. Kit contains interface plate, DIN-rail clip and necessary screws. Rev. June 19. 2013 http://www.farnell.com/datasheets/1749862.pdf http://www.tracopower.com Page 1 of 3 DC/DC Converters TMR 2 Series, 2 Watt Features ◆ Wide 2:1 input voltage range ◆ Compact SIP-8 package ◆ Small footprint ◆ Full SMD design ◆ Temperature range –40° to +85°C ◆ High efficiency ◆ Excellent load and line regulation ◆ Indefinite short-circuit protection ◆ I/O isolation 1000VDC ◆ Remote On/Off control ◆ Fully RoHS compliant ◆ 3-year product warranty Ordercode Input voltage range Output voltage Output current max. Efficiency typ. TMR 0510 3.3 VDC 500 mA 76 % TMR 0511 5 VDC 400 mA 80 % TMR 0512 4.5 – 9.0 VDC 12 VDC 165 mA 81 % TMR 0521 (5 VDC nominal) ±5 VDC ±200 mA 79 % TMR 0522 ±12 VDC ±85 mA 82 % TMR 0523 ±15 VDC ±65 mA 81 % TMR 1210 3.3 VDC 500 mA 77 % TMR 1211 5 VDC 400 mA 81 % TMR 1212 9 – 18 VDC 12 VDC 165 mA 83 % TMR 1221 (12 VDC nominal) ±5 VDC ±200 mA 81 % TMR 1222 ±12 VDC ±85 mA 83 % TMR 1223 ±15 VDC ±65 mA 84 % TMR 2410 3.3 VDC 500 mA 78 % TMR 2411 5 VDC 400 mA 81 % TMR 2412 18 – 36 VDC 12 VDC 165 mA 83 % TMR 2421 (24 VDC nominal) ±5 VDC ±200 mA 80 % TMR 2422 ±12 VDC ±85 mA 83 % TMR 2423 ±15 VDC ±65 mA 82 % TMR 4810 3.3 VDC 500 mA 76 % TMR 4811 5 VDC 400 mA 78 % TMR 4812 36 – 75 VDC 12 VDC 165 mA 83 % TMR 4821 (48 VDC nominal) ±5 VDC ±200 mA 80 % TMR 4822 ±12 VDC ±85 mA 81 % TMR 4823 ±15 VDC ±65 mA 81 % Models The TMR-2 series is a family of isolated 2W dc-dc converter modules with regulated output, featuring wide 2:1 input voltage ranges. The product comes in a compact SIP-8 plastic package with small footprint occupying only 2.0 cm2 (0.3 square in.) of board space. An excellent efficiency allows –40° to +85°C operation temperatures. Further features include remote On/Off control and continuous short circuit protection. The ultra-compact dimensions of these converters make them an ideal solution for many space critical applications in communication equipment, instrumentation and industrial electronics. UL 60950-1 http://www.tracopower.com Page 2 of 3 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. DC/DC Converters TMR 2 Series 2 Watt Input Specifications Input current at full load (nominal input) 5 Vin models: 645 mA max. 12 Vin models: 242 mA max. 24 Vin models: 117 mA max. 48 Vin models: 62 mA max. Surge voltage (100 msec. max.) 5 Vin models: 15 V max. 12 Vin models: 36 V max. 24 Vin models: 50 V max. 48 Vin models: 100 V max. Input voltage variation (dv/dt) 5 V/ms, max. (complies to ETS 300 132 part. 4.4) Input Filter capacitor type Start up time 5 ms typ. (at nominal input and resistive load) ESD (electrostatic discharge) EN 61000-4-2, air ±8 kV, contact ±6 kV, perf. criteria A Radiated immunity EN 61000-4-3, 10 V/m, perf. criteria A Fast transient / surge (with external input capacitor) EN 61000-4-4, ±2 kV, perf. criteria A EN 61000-4-5, ±1 kV perf. criteria A – external input capacitor Nippon chemi-con KY 220 μF, 100 V, ESR 48 mOhm Conducted immunity EN 61000-4-6, 10 Vrms, perf. criteria A Output Specifications Voltage set accuracy ±1 % Regulation – Input variation Vin min. to Vin max. 0.2 % max. – No load to full load single output models: ±1.0 % max. dual output models: ±1.0 % max. – Load variation 10 – 90 % single output models: ±0.5 % max. dual output models: ±0.8 % max. dual output models asymetric load: 5.0 % max. (25% / 100%) Minimum load 0 % Ripple and noise (20 MHz Bandwidth) 50 mVpk-pk max. Temperature coefficient ±0.02 %/°C Transient response (25% load step change) 500 μs typ. Short circuit protection continuous, automatic recovery Capacitive load 3.3 VDC / 5 VDC output models: 2’200 μF max. / 1’000 μF max. 12 VDC / ±5 VDC output models: 170 μF max. / ±470 μF max. ±12 VDC / ±15 VDC output models: 100 μF max. / ±47 μF max. General Specifications Temperature ranges – Operating –40°C to +85°C (non derating) – Storage –55°C to +125°C Derating (convection cooling) 2 %/K above 75°C Humidity (non condensing) 95 % rel. H max. Reliability, calculated MTBF (Telcordia SR-332, 50% stress, Ta=40°C) 5.1 Mio. h Isolation voltage (60 sec.) – Input/Output 1’600 VDC Isolation capacitance – Input/Output 200 pF max. Isolation resistance – Input/Output (500 VDC) >1‘000 MOhm Switching frequency 100 to 650 kHz (PFM) Page 3 of 3 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com DC/DC Converters TMR 2 Series 2 Watt Outline Dimensions mm (inches) Bottom view 3.2 (0.13) 0.5 (0.02) 0.25 (0.01) 2.54 2.0 ±0.5 2.54 21.8 5.08 2.54 0.5 (0.02) 11.1 (0.44) (0.08 (0.1) (0.1) (0.1) ±0.025) (0.2) 4.0 2.54 (0.1) 2.54 (0.1) (0.86) (0.16) 9.2 (0.36) 1 2 3 5 6 7 8 Pin Single Dual 1 –Vin (GND) –Vin (GND) 2 +Vin (Vcc) +Vin (Vcc) 3 Remote On/Off Remote On/Off 5 No function No function 6 +Vout +Vout 7 –Vout Common 8 No function –Vout Pin-Out Rev. August 09/13 Dimensions in [mm], () = Inch Pin pitch tolerances: ±0.25 (±0.01) Tolerances: ±0.5 (±0.02) General Specifications Remote On/Off – On: open or high impedance – Off: 2...4 mA input current applied via 1KW resistor – Off stand by input current max. 2.5 mA Safety standards UL/cUL 60950-1, IEC/EN 60950-1 Safety approvals – UL/cUL www.ul.com -> certifications -> File e188913 Thermal shock, mechanical shock & vibration MIL-STD-810F – Test conditions www.tracopower.com/products/mil810.pdf Environmental compliance – Reach www.tracopower.com/products/tmr2-reach.pdf – RoHS RoHS Directive 2011/65/EU Altitude – operation < 40’000ft (12’000m) – non operation < 50’000ft (15’000m) – test report www.tracopower.com/products/tmr-altitude.pdf Physical Specifications Casing material non-conductive plastic Potting material epoxy (UL 94V-0-rated) Weight 4.8 g (0.17oz) Physical Specifications Application note: www.tracopower.com/products/tmr2-application.pdf http://www.tracopower.com Page 1 of 4 DC/DC Converters TMR 1 & TMR 1SM Series, 1 Watt Order code SIP-package Order code SMD-package Input voltage range Output voltage Output current max. Efficiency SIP typ. Efficiency SMD typ. TMR 1-0511 TMR 1-0511SM 5.0 VDC 200 mA 76 % 78 % TMR 1-0512 TMR 1-0512SM 12 VDC 83 mA 77 % 79 % TMR 1-0513 TMR 1-0513SM 4.5 – 9.0 VDC 15 VDC 67 mA 79 % 81 % TMR 1-0515 (5 VDC nominal) 24 VDC 42 mA 76 % TMR 1-0522 TMR 1-0522SM ±12 VDC ±42 mA 77 % 79 % TMR 1-0523 TMR 1-0523SM ±15 VDC ±33 mA 78 % 80 % TMR 1-1211 TMR 1-1211SM 5.0 VDC 200 mA 77 % 79 % TMR 1-1212 TMR 1-1212SM 12 VDC 83 mA 77 % 79 % TMR 1-1213 TMR 1-1213SM 9.0 – 18 VDC 15 VDC 67 mA 80 % 82 % TMR 1-1215 (12 VDC nominal) 24 VDC 42 mA 77 % TMR 1-1222 TMR 1-1222SM ±12 VDC ±42 mA 79 % 81 % TMR 1-1223 TMR 1-1223SM ±15 VDC ±33 mA 78 % 80 % TMR 1-2411 TMR 1-2411SM 5.0 VDC 200 mA 77 % 79 % TMR 1-2412 TMR 1-2412SM 12 VDC 83 mA 80 % 82 % TMR 1-2413 TMR 1-2413SM 18 – 36 VDC 15 VDC 67 mA 80 % 82 % TMR 1-2415 (24 VDC nominal) 24 VDC 42 mA 77 % TMR 1-2422 TMR 1-2422SM ±12 VDC ±42 mA 80 % 82 % TMR 1-2423 TMR 1-2423SM ±15 VDC ±33 mA 80 % 82 % TMR 1-4811 TMR 1-4811SM 5.0 VDC 200 mA 77 % 79 % TMR 1-4812 TMR 1-4812SM 12 VDC 83 mA 78 % 80 % TMR 1-4813 TMR 1-4813SM 36 – 75 VDC 15 VDC 67 mA 78 % 80 % TMR 1-4815 (48 VDC nominal) 24 VDC 42 mA 76 % TMR 1-4822 TMR 1-4822SM ±12 VDC ±42 mA 79 % 81 % TMR 1-4823 TMR 1-4823SM ±15 VDC ±33 mA 79 % 81 % Models Features ◆ Wide 2:1 input voltage range ◆ Compact SIP-6 or SMD package ◆ Fully regulated outputs ◆ Cost optimised design ◆ No minimum load required ◆ Continuous short circuit protection ◆ Temperature range –40°C to +85°C ◆ I/O isolation 1500 VDC ◆ Remote On/Off control (SMD) ◆ 3-year product warranty The TMR-1 and TMR 1SM series are families of isolated 1 W dc-dc converter modules with regulated output, featuring wide 2:1 input voltage ranges. These products come in a compact SIP-6 or SMD package with small footprint occupying only 1.2 cm2 (0.2 square inch) of board space. An excellent efficiency allows –40°C to +85°C operation temperature. Further features include remote On/Off control (SMD-Version) and continuous short circuit protection. The compact dimensions and cost optimised design make this converters an ideal solution for applications in communication equipment, instrumentation and industrial electronics. CB Scheme http://www.tracopower.com Page 2 of 4 All specifications valid at nominal input voltage, full load and +25°C after warm-up time unless otherwise stated. DC/DC Converters TMR 1 & TRM 1SM 1 Watt Input Specifications Input current at no load (nominal input voltage) 5.0 V models: 40 mA typ. 12 V models: 20 mA typ. 24 V models: 10 mA typ. 48 V models: 7 mA typ. Surge voltage (1 sec. max.) 5.0 V models: 15 V max. 12 V models: 25 V max. 24 V models: 50 V max. 48 V models: 100 V max. Start-up voltage / under voltage lockout 5.0 V models: 4.5 VDC / 4 VDC or lower 12 V models: 9 VDC / 8.5 VDC or lower 24 V models: 18 VDC / 17 VDC or lower 48 V models: 36 VDC / 34 VDC or lower long term operation at undervoltage will damage the converter! Conducted noise (input) EN 55022 level A, FCC part 15, level A with external capacitor. see EMC consideration Recommended input fuse (slow blow) 5 V models: 500 mA 12 V models: 250 mA 24 V models: 120 mA 48 V models: 60 mA Output Specifications Voltage set accuracy ±1 % max. Regulation – Input variation Vin min. to Vin max. 0.2 % max. – No load to full load Single & Dual output models: ±1.0 % max. – Load variation 10 – 90% Single output models: ±0.5 % max. Dual output models (balanced load): ±0.8 % max. Minimum load no minimum load required Temperature coefficient 0.02 %/K Ripple and noise (20 MHz bandwidth) SMD models: 30 mVp-p max. SIP models: 50 mVp-p max. Transient response setting time (25% load step change) 250 μs typ. (PFM) Current limitation >120 % of Iout max. Short circuit protection continuous, automatic recovery Capacitive load 5 VDC models: 1‘680 μF max. 12 VDC models: 820 μF max. 15 VDC models: 680 μF max. 24 VDC models: 470 μF max. ±12 VDC models: 470 μF max. (each output) ±15 VDC models: 330 μF max. (each output) General Specifications Temperature ranges – Operating SIP models: –40°C to +85°C with no derating SMD models: –40°C to +82°C with derating – Case temperature +105°C (SIP) / +95°C (SMD) max. – Storage –55°C to +125°C Load derating SMD models: 7.2 %/K above +75°C Humidity (non condensing) 95 % rel. H max. Reliability, calculated MTBF (MIL-HDBK-217F, at +25°C, ground benign) >2.8 Mio h Page 3 of 4 DC/DC Converters TMR 1 & TRM 1SM 1 Watt General Specifications Isolation voltage (60 sec.) – Input/Output 1’500 VDC Isolation capacitance – Input/Output 50 pF max. Isolation resistance – Input/Output (500 VDC) >1 GOhm Switching frequency 220 kHz (PFM) Safety standards UL 60950-1, IEC/EN 60950-1 IEC 60950-1:2005 (2nd Edition); Am 1:2009 EN 60950-1:2006+A11:2009+A1:2010+A12:2011 Safety approvals – CB test certificate (IEC 60950-1) www.tracopower.com/products/tmr1-cb.pdf Remote On/Off – On: < 0.6 VDC or open circuit (SMD models only) – Off: 2.7 to 15 VDC (ref. to –Vin) – Off standby current: 2.5 mA max. – Off control input current: 1 mA max. Physical Specifications Casing material non-conductive plastic (UL94V-0 rated) Potting material epoxy, (UL 94V-0 rated) Weight 3.1 g (0.11oz) (SIP)/3.3 g (0.12oz) (SMD) Soldering profile for SIP-package models max. 265°C / 10 sec. (wave soldering) Lead-free reflow solder process for SMD-package models as per J-STD-020D.01 (to find at: www.jedec.org - free registration required) Moisture sensivity level (for SMD-package models) level 2a as per J-STD-033B.01 (to find at: www.jedec.org - free registration required) Environmental compliance – Reach www.tracopower.com/products/reach-declaration.pdf – RoHS RoHS directive 2011/65/EU EMC Consideration +Vin -Vin +Vout -Vout C1 C2 L1 Load +Vin -Vin +Vout -Vout C1 C2 L1 Load Com. Load Single output models Input models C1 C2 L1 5 VDC 4.7μF /50V, 1210 X7R 4.7μH / 1.2 A, SR0302 12 VDC 4.7μF /50V, 1210 X7R 4.7μH / 1.2 A, SR0302 24 VDC SIP 4.7μF /50V, 1210 X7R 18μH / 0.58 A, SR0302 24 VDC SMD 4.7μF /50V, 1210 X7R 220pF /2 kV, 1808 X7R 12μH / 0.75 A, SR0302 48 VDC SIP 4.7μF /100V 1210 X7R 18μH / 0.58A, SR0302 48 VDC SMD 2.2μF / 00V 1210 X7R 18μH / 0.58A, SR0302 Dual output models Filter suggestion for to comply with EN55022 class A conducted noise emission Outline Dimensions mm (inches) Page 4 of 4 Specifications can be changed without notice! Make sure you are using the latest documentation, downloadable at www.tracopower.com www.tracopower.com Rev. August 30. 2013 DC/DC Converters TMR 1 & TRM 1SM 1 Watt Pin single output dual output 1 –Vin (GND) –Vin (GND) 2 +Vin (Vcc) +Vin (Vcc) 4 +Vout +Vout 5 No Pin Common 6 –Vout –Vout Pinout Bottom view 1 2 5 6 2.5 2.54 0.5 2.3 ±0.4 2.54 17.0 (0.67) 5.08 (0.2) 2.54 0.5 (0.02) 11.0 (0.4) 3.2 (0.13) (0.02) 0.5 (0.02) (0.09 (0.1) (0.1) (0.1) ±0.02) 7.62 (0.30) (0.10) (0.02) 4 0.5 0.25 (0.01) Dimensions in [mm], () = Inch Tolerances: ±0.5 (±0.02) Pin pitch tolerances: ±0.25 (±0.01) SIP-Package SMD-Package 1 6 7 14 9 8 2 13.7 [0.54] 17.2 [0.68] 8.45 [0.33] 8.7 [0.34] 0.25 [0.01] 1.00 [0.04] 18.9 [0.74] 12.7 [0.5] [0.1] 1.8 [0.1] 2.54 0~4 S SEATING PLANE 0.15 S 1.1 [0.04] 15.0 [0.6] Pin single output dual output 1 –Vin (GND) –Vin (GND) 2 Remote On/Off Remote On/Off 6 ntc Common 7 ntc –Vout 8 +Vout +Vout 9 –Vout Common 14 +Vin +Vin Pinout ntc = not to connect to electrical circuit SOURIAU Contacts and tooling For series UTP,UTS,UTG,UTO,MBG Contacts 13 Amps Diam 1.6mm Manu. Part No. Stock N° Gender mm² Crimping Tools RM20M12K 273‐2951 Male 0.32‐0.52 RC20M12K 273‐2917 Female 0.32‐0.52 RM16M23K 273‐2945 Male 0.52‐1.50 RC16M23K 273‐2901 Female 0.52‐1.50 Y16RCM RM14M30K 687‐6367 Male 1.5‐2.5 RC14M30K 687‐6370 Female 1.5‐2.5 SM16ML1TK6 437‐3762 Male 0.80‐1.50 Y14MTV SC16ML1TK6 437‐3778 Female 0.80‐1.50 RM16SE0K 510‐1079 Male 0.52‐1.50 Solder RC16SE4K 510‐1085 Female 0.52‐1.50 Contacts 5 Amps Diam 1.00 mm Manu. Part No. Stock N° mm² Crimping Tools Gender SM24WL3S26 687‐6392 Male 0.13‐0.25 SC24WL3S26 687‐6383 Female 0.13‐0.25 SM20WL3S26 540‐410 Male 0.35‐0.50 Y14MTV SC20WL3S25 540‐422 Female 0.35‐0.50 RM18W3K 191‐046 Male 0.50‐1.00 MH860 + 86‐5 RC18W3K 190‐908 Female 0.50‐1.00 Tooling Manu. Part No. Stock N° Description Y16RCM 481‐008 Crimp Tool Y14MTV 480‐998 Crimp Tool MH860 314‐8408 Crimp Tool 86‐5 314‐8414 Positioner for MH860 RX2025GE1 481‐046 Extraction tool RX20D44 233‐2731 Extraction tool 851 Series MIL-DTL-26482 Connectors 3 851 Sommaire / Contents • Sommaire / Contents............................................................... • Etendue de la gamme / Product Overview...................... • Présentation / Presentation.................................................... • Description / Description........................................................ • Tableau comparatif références SOURIAU et normes équivalentes / Cross reference list...................................... • Caractéristiques techniques / Technical characteristics. • Contacts / Contacts ................................................................ • Références / Ordering information...................................... • Arrangements / Contact layouts.......................................... • Positionnements / Orientations............................................. • Encombrements Connecteurs Etanches / Dimensions Environmental Connectors..................................................... • Encombrements Connecteurs Hermétiques / Dimensions Hermetic Connectors............................................................. • Encombrements Connecteurs pour connexions enroulées et à picots droits / Dimensions Wire-wrap and PC tail Connectors....................................................................................... • Perçage cloison / Panel cut-out............................................ 3 3 4-5 6 7-8 9 10 11-13 14-15 16 17-38 39-40 40-41 41 • Accessoires / Accessories..................................................... • Bouchons / Caps....................................................................... • Références des raccords / Backshell ordering information................................................................................... • Outillages / Tools....................................................................... • Notice de câblage / Wiring instructions............................ • Sertissage / Crimping............................................................... • Schémas d’implantations pour circuits imprimés / Coordinates for PC tail............................................................. • Prise largable push-pull / Push-pull lanyard release plug................................................................................................ • Connecteurs filtres 8F51 / 8F51 filter connector........... • Connecteurs spécifiques & accessoires SNC / Specific products & SNC accessories.................................................. • Traversée de cloison 851 RJ45 / 851 RJ45 feedthru.. • Traversée de cloison 851 USB / 851 USB feedtrhu..... • 8XE / 8XE.................................................................................... • Protection sans cadmium / Cadmium free plating......... 42 44-45 46-47 48-50 51 52-54 55-59 60-61 62 63 65-68 69-72 73-76 77 851 page 4-63 851 RJ45 Feedthru page 65-68 851 USB Feedthru page 69-72 8XE page 73-76 Etendue de la gamme / Product Overview 4 851 Présentation • Versions étanches et hermétiques • Large choix de raccords et accessoires • Protection cadmiée vert olive, oxydée anodique noire, nickelée ou zinc nickel • Contacts à souder, à sertir, à picot droit ou pour enroulement de fils • Contacts spéciaux thermocouples • La version 851 avec contacts à souder est qualifiée QPL (USA) • La gamme 851 est aussi commercialisée par un réseau de distributeurs. Les connecteurs circulaires 851 Souriau, initialement conçus pour la connexion des circuits électriques en aéronautique et armement, ont aujourd’hui conquis les domaines diversifiés de l’électricité et de l’électronique industrielles (Mesure, Instrumentation, Transport, Machine, Outil, Productique…). Ils correspondent aux normes et spécifications internationales et nationales en vigueur MIL-DTL-26482G série 1, NFC 93422, HE 301B, VG 95328, liste GAM/T1. Les connecteurs fixes (embases) et mobiles (fiches), mâles ou femelles, se verrouillent entre eux par un système mécanique endurant du type à baïonnette à 3 rampes hélicoïdales. Cinq clavettes de guidage longitudinal et cinq positionnements angulaires possibles de l’isolant assurent le détrompage entre connecteurs. Les mécaniques sont en alliage d’aluminium traité et protégé pour la version 851 étanche, et en acier protégé pour la version 851 hermétique. Les isolants sont en élastomère de la classe +125°C pour la version étanche et en verre pour la version hermétique. Les contacts sont dorés ou étamés sur sous-couche nickel. Nous proposons, afin de faciliter le câblage, des contacts à souder et à picot taille 20 (y compris version hermétique) avec protection dorure sur la partie avant et étamage sur la partie arrière. 5 851 Presentation • Sealed and hermetic types • Wide choice of body styles and back fittings • Olive green, black anodised, nickel or zinc nickel plated • Solder, crimp, PC-tail and wire-wrap versions • Thermocouple crimp contacts available • The 851 version with solder contacts is on US QPL • 851 connectors are also widely available from distributors. Souriau 851 circular connectors were originally conceived to ensure reliable electrical connections in aircraft but their lightweight compact size and general characteristics have contributed to successful adoption in numerous civil and military aviation applications and also in the fields of professional and general electronics (machine tools, automation, measuring equipment…). 851 connectors conform to the following international standards, MIL-DTL-26482G series 1, NFC 93422, HE 301B, VG 95328, GAM/T1 list. 851 connectors feature a positive bayonet coupling mechanism which ensures reliable mechanical and electrical connection between mating halves. A helical locking ring on the plug couples with three dowel pegs on the receptacle ensuring rapid locking. Orientation and location is ensured by a system of five raised keys on the plugs which couple with corresponding slots on the receptacles. Connectors with different angular positioning of the insulator relative to the shell can be provided to prevent mating of adjacent connectors with the same contact arrangements. The connector shells are manufactured from aluminium alloy. The insulators are moulded from elastomer and are bonded into the shells. Grommets are also made from elastomer and are supplied with appropriate accessories in the solder version, but are integral with the insulator for the crimp version. Copper alloy contacts have gold or tin over nickel plating. Hermetic receptacles with gold plated solder contacts are made from steel shells with nickel plating (01H) or yellow cadmium plating (02H and 07H). The contacts are permanently fused into a glass insulator providing a high level of sealing. To facilitate cabling we offer solder and straight spill contacts size 20 (including hermetic versions) with a gold plated active part and tin plated terminations. 6 851 Description Connecteurs assemblés avec contacts à sertir à clips Connectors with clip retained crimp contacts Connecteurs assemblés (embase avec contacts à picots ou avec contacts pour connexions enroulés) Connectors assemblies (receptacle with PC tail or wire-wrap terminals) Connecteurs assemblés avec contacts à souder Connectors assemblies with solder contacts 1 • Isolant arrière (passe-fils) 2 • Contact femelle à sertir 3 • Isolant femelle 4 • Isolant mâle 5 • Contact mâle à sertir 6 • Raccord simple 7 • Corps de fiche 8 • Embase 1 • Rear insulator (grommet) 2 • Female crimp contact 3 • Female insulator 4 • Male insulator 5 • Male crimp contact 6 • Backnut 7 • Plug body 8 • Receptacle 1 • Contact femelle à souder 2 • Contact mâle à souder 3 • Isolant femelle 4 • Isolant mâle 5 • Isolant arrière (passe-fils) 6 • Embase à collerette carrée 7 • Raccord simple 8 • Corps de fiche 9 • Ecrou de fixation 10 • Embase à fixation par écrou 11 • Raccord simple (pour embase à fixation par écrou) 1 • Female solder contact 2 • Male solder contact 3 • Female insulator 4 • Male insulator 5 • Rear insulator (grommet) 6 • Square flange receptacle 7 • Backnut 8 • Plug body 9 • Fixing nut 10 • Jam nut receptacle 11 • Backnut (for jam nut receptacle) 1 • Contact mâle ou femelle à souder ou à sertir 2 • Contact mâle ou femelle à picots droits 3 • Contact mâle ou femelle pour connexions enroulées 4 • Isolant mâle ou femelle 5 • Isolant arrière (passe-fils) 6 • Corps de fiche 7 • Raccord simple 8 • Isolant mâle ou femelle 9 • Embase sans possibilité de raccord 1 • Male or female crimp or solder contact 2 • Male or female PC tail contact 3 • Male or female wire-wrap contact 4 • Male or female insulator 5 • Rear insulator (grommet) 6 • Plug body 7 • Backnut 8 • Male or female insulator 9 • Receptacle not suitable for backshells 7 851 * Non QPL - Not QPL 22.1631 Connecteurs avec raccords / Connectors with backshells SOURIAU NCF 93422 (modèle HE 301B) MIL-DTL-26482G série 1 VG 95328 851 00 R .. .. .. 50 .. HE 301 B 00 R .. .. .. 1A * MS 3120 E .. .. .. VG 95328 A .. .. .. 851 00 RC .. .. .. 50 .. HE 301 B 00 RC .. .. .. 1A * MS 3120 F .. .. .. VG 95328 B .. .. .. 851 00 RP .. .. .. 50 .. HE 301 B 00 RP .. .. .. 1A * MS 3120 P .. .. .. 851 00 RG .. .. .. 50 .. VG 95328 R .. .. .. 851 00 RA .. .. .. 50 .. HE 301 B 00 RA .. .. .. 1A 851 01 R .. .. .. 50 .. HE 301 B 01 R .. .. .. 1A * MS 3121 E .. .. .. 851 01 RC .. .. .. 50 .. HE 301 B 01 RC .. .. .. 1A * MS 3121 F .. .. .. 851 01 RP .. .. .. 50 .. HE 301 B 01 RP .. .. .. 1A * MS 3121 P .. .. .. 851 01 RA .. .. .. 50 .. HE 301 B 01 RA .. .. .. 1A 851 02 R .. .. .. 50 .. HE 301 B 02 R .. .. .. 1A * MS 3122 E .. .. .. VG 95328 C .. .. .. 851 06 R .. .. .. 50 .. HE 301 B 06 R .. .. .. 1A * MS 3126 E .. .. .. 851 06 RC .. .. .. 50 .. HE 301 B 06 RC .. .. .. 1A * MS 3126 F .. .. .. VG 95328 K .. .. .. 851 06 RP .. .. .. 50 .. HE 301 B 06 RP .. .. .. 1A * MS 3126 P .. .. .. 851 06 RT .. .. .. 50 .. VG 95328 J .. .. .. 851 06 RA .. .. .. 50 .. HE 301 B 06 RA .. .. .. 1A 851 36 RG .. .. .. 50 .. VG 95328 M .. .. .. 851 36 RA .. .. .. 50 .. 851 07 R .. .. .. 50 .. HE 301 B 07 R .. .. .. 1A * MS 3124 E .. .. .. VG 95328 D .. .. .. 851 07 RC .. .. .. 50 .. HE 301 B 07 RC .. .. .. 1A * MS 3124 F .. .. .. VG 95328 E .. .. .. 851 07 RP .. .. .. 50 .. HE 301 B 07 RP .. .. .. 1A * MS 3124 P .. .. .. 851 07 RT .. .. .. 50 .. VG 95328 S .. .. .. 851 07 RG .. .. .. 50 .. VG 95328 T .. .. .. 851 76 RU .. .. .. 50 .. 851 08 RC .. .. .. 50 .. HE 301 B 08 RC .. .. .. 1A 851 08 RP .. .. .. 50 .. HE 301 B 08 RP .. .. .. 1A Tableau comparatif / Cross refence list Version 851 avec contacts à sertir (protection vert olive) 851 Version with crimp contacts (olive green cadmium plating) Autres protections / Other plating Protections Plating SOURIAU NFC 93422 Version à souder (modèle HE 301B) Solder version Version à sertir Crimp version Anodique noire Black anodised 851 .. .. .. .. 5029 851 .. .. .. .. .. 50031 HE 301B .. .. .. .. .. 4A Nickelé Nickel 851 .. .. .. .. 5044 851 .. .. .. .. .. 5044 HE 301B .. .. .. .. .. 5A 8 851 Connecteurs avec raccords / Connectors with backshells SOURIAU NCF 93422 (modèle HE 301B) MIL-DTL-26482G série 1 VG 95328 851 00 E .. .. .. 50 .. HE 301 B 00 E .. .. .. 1A MS 3110 E .. .. .. 851 00 EC .. .. .. 50 .. HE 301 B 00 EC .. .. .. 1A MS 3110 F .. .. .. 851 00 AC .. .. .. 50 .. HE 301 B 00 AC .. .. .. 1A 851 00 P .. .. .. 50 .. HE 301 B 00 P .. .. .. 1A MS 3110 P .. .. .. 851 00 A .. .. .. 50 .. HE 301 B 00 A .. .. .. 1A 851 00 J .. .. .. 50 .. HE 301 B 00 J .. .. .. 1A 851 00 JC .. .. .. 50 .. MS 3110 J .. .. .. 851 01 E .. .. .. 50 .. HE 301 B 01 E .. .. .. 1A MS 3111 E .. .. .. 851 01 EC .. .. .. 50 .. HE 301 B 01 EC .. .. .. 1A MS 3111 F .. .. .. 851 01 AC .. .. .. 50 .. HE 301 B 01 AC .. .. .. 1A 851 01 P .. .. .. 50 .. HE 301 B 01 P .. .. .. 1A MS 3111 P .. .. .. 851 01 A .. .. .. 50 .. HE 301 B 01 A .. .. .. 1A 851 01 J .. .. .. 50 .. HE 301 B 01 J .. .. .. 1A 851 01 JC .. .. .. 50 .. MS 3111 J .. .. .. 851 02 E .. .. .. 50 .. HE 301 B 02 E .. .. .. 1A MS 3112 E .. .. .. VG 95328 H .. .. .. 851 06 E .. .. .. 50 .. HE 301 B 06 E .. .. .. 1A MS 3116 E .. .. .. 851 06 EC .. .. .. 50 .. HE 301 B 06 EC .. .. .. 1A MS 3116 F .. .. .. 851 06 AC .. .. .. 50 .. HE 301 B 06 AC .. .. .. 1A 851 06 P .. .. .. 50 .. HE 301 B 06 P .. .. .. 1A MS 3116 P .. .. .. 851 06 A .. .. .. 50 .. HE 301 B 06 A .. .. .. 1A 851 06 J .. .. .. 50 .. HE 301 B 06 J .. .. .. 1A 851 06 JC .. .. .. 50 .. MS 3116 J .. .. .. 851 08 EC .. .. .. 50 .. HE 301 B 08 EC .. .. .. 1A 851 08 P .. .. .. 50 .. HE 301 B 08 P .. .. .. 1A 851 07 E .. .. .. 50 .. HE 301 B 07 E .. .. .. 1A MS 3114 E .. .. .. 851 07 EC .. .. .. 50 .. HE 301 B 07 EC .. .. .. 1A MS 3114 F .. .. .. 851 07 AC .. .. .. 50 .. HE 301 B 07 AC .. .. .. 1A 851 07 P .. .. .. 50 .. HE 301 B 07 P .. .. .. 1A MS 3114 P .. .. .. 851 07 A .. .. .. 50 .. HE 301 B 07 A .. .. .. 1A Tableau comparatif / Cross refence list Version 851 avec contacts à souder (protection vert olive) 851 Version with solder contacts (olive green cadmium plating) Version 851 hermétique / 851 Hermetic version SOURIAU NFC 93422 (modèle HE 301B) MIL-DTL-26482G série 1 VG 95328 851 02 H .. .. P.50 HE 301 B 02 H .. .. P.3A 851 07 H .. .. P.50 HE 301 B 07 H .. .. P.3A * MS 3114 H .. .. .. P. VG 95328 F .. .. .. 851 I H .. .. P.50 HE 301 B 1 H .. .. P.3A * MS 3113 H .. .. .. P. VG 95328 G .. .. . * Non QPL - Not QPL 9 851 Caractéristiques techniques / Technical characteristics Tension de tenue • A pression normale : connecteurs accouplés et non accouplés - 1500 Veff entre contacts taille 20 (service 1) - 2300 Veff entre contacts taille 16 (service 2) - 1500 Veff entre contacts panachés de taille 16 et de taille 20 (service 1) • A basse pression 10 mbar : connecteurs accouplés et non accouplés - 200 Veff entre contacts taille 20 (service 1) - 300 Veff entre contacts taille 16 (service 2) Résistance d’isolement ≥ 5000 MΩ sous 500 Vcc Intensité admissible par contact Taille 20 = 7,5 A / Taille 16 = 13 A Résistance de contact • Version étanche : Taille 20 ≤ 4 mΩ / Taille 16 ≤ 3 mΩ • Version hermétique : Taille 20 ≤ 30 mΩ / Taille 16 ≤ 14 mΩ Blindage 70 dB à 5 MHz / 40 dB à 100 MHz Tension de claquage mini Breakdown voltage (mini) Electriques Boîtier • Version étanche : alliage d’aluminium - Protection : - cadmié vert olive - oxydation anodique noire - cadmium incolore - nickelé satiné brillant - zinc cobalt (vert olive) - zinc nickel • Version hermétique : acier - Protection : - cadmié jaune irisé - nickelé Isolant • Partie avant : élastomère néoprène (dureté 85 shore) • Partie arrière (passe-fils) : élastomère néoprène (dureté 40 shore) Contact • A sertir : montable et démontable par l’arrière de l’isolant et retenu par clips métalliques, à souder et à picot non démontable, à connexion enroulée démontable et non démontable • Matière : alliage cuivreux • Protection : or ou or sur parties actives et étain/plomb sur parties raccordement • Effort mini de rétention des contacts dans l’isolant • Endurance mécanique : 500 cycles complets (verrouillage et déverrouillage) Vibration Selon NFC 20-616 Mécaniques Shell • Environmental version : aluminium alloy - Plating : - olive green cadmium - black anodised - white cadmium - satin finish bright nickel - zinc cobalt (olive green) - zinc nickel • Hermetic version : steel - Plating : - iridescent yellow cadmium - nickel Isolant • Front section : neoprene elastomer (85 shore) • Rear section : neoprene elastomer (40 shore) Contact • Crimp : inserted and removed from rear of insulator retained by metallic clips, solder Mechanical Taille des contacts A sertir à clip A souder A picot A wrapper 20 (Ø1mm) ≥ 68 N ≥ 68 N 16 (Ø1.6mm) ≥ 113 N ≥ 113 N Contact size Crimp Solder PC tail Wire wrap 20 (Ø1mm) ≥ 68 N ≥ 68 N 16 (Ø1.6mm) ≥ 113 N ≥ 113 N Working temperature -55°C to +125°C Sealing • Crimp contact version, 1 bar differential pressure, leakage ≤ 8 cm3/hr • Solder contact version, 2 bar differential pressure, leakage ≤ 16 cm3/hr Hermiticity • 1 bar differential pressure, leakage ≤ 2.8 mm3/hr Chemical resistance : to MIL-DTL-26482G series 1 and NFC 93422 - HE 301 B code A Resistance to salt spray • 48 hours at environmental temperature Damp heat : 21 days Climatic • Mechanical endurance : 500 cycles (full mating-unmating) Vibration To NFC 20-616 Dielectric withstanding voltage • At standard pressure : mated and unmated connectors - 1500 Vrms between size 20 contacts (service 1) - 2300 Vrms between size 16 contacts (service 2) - 1500 Vrms between mixed size 20 and 16 contacts (service 1) • At reduced pressure 10 mbar : connectors mated and unmated - 200 Vrms between size 20 contacts (service1) - 300 Vrms between size 16 contacts (service2) Insulation resistance ≥ 5000 MΩ under 500 Vcc Current rating per contact Size 20 = 7.5 A / Size 16 = 13 A Contact resistance • Environmental version : Size 20 ≤ 4 mΩ / Size 16 ≤ 3 mΩ • Hermetic version : Size 20 ≤ 30 mΩ / Size 16 ≤ 14 mΩ Shielding 70 dB to 5 MHz / 40 dB to 100 MHz Température d’utilisation -55°C à +125°C Etanchéité • Version contact à sertir sous pression différentielle de 1 bar, fuite ≤ 8 cm3/heure • Version contact à souder sous pression différentielle de 2 bars, fuite ≤ 16 cm3/heure Herméticité • Sous pression différentielle de 1 bar, fuite ≤ 2,8 mm3/heure Tenue aux agents chimiques : suivant norme MIL-DTL-26482G série 1 et NFC 93422 - HE 301 B code A Résistance au brouillard salin • 48 heures, à température ambiante Chaleur humide : 21 jours Climatiques and PC tail, non removable, wire-wrap removable or not removable • Material : copper alloy • Plating : gold overall or gold plated active zone and tin/lead plated termination • Min retention force of contacts in insulator Electrical 10 851 Contacts à sertir / Crimp contacts Type de contact / Contact type Taille de contact Contact size Références Part numbers Câble admissible Cable acceptance Ø extérieur sur gaine Ø over insulation Section (mm²) Jauge Gauge AWG min. max. standards standard mâle male pour arrangements 8-2, 8-3, 8-4 & 12-14 for layouts 8-2, 8-3, 8-4 & 12-14 20 8500-9573* 0.21 à/to 0.93 24 à/to 18 1.20 2.11 femelle female 8500-9213 900* mâle male autre arrangement for further contact layout 8500-697 femelle female 8500-1758A 900 mâle male 16 8500-1300 0.93 à/to 1.91 18 à/to 14 1.60 2.80 femelle female 8500-9331 900 embout réducteur reducing sleeve 20 8500-781 B1 0.06 à/to 0.21 30 à/to 24 16 8500-1985 B1 0.60 20 thermocouple thermocouple chromel mâle male 20 8500-809 A 0.21 à/to 0.93 24 à/to 18 1.20 2.11 alumel 8500-812 A chromel femelle female 8500-2054 900 alumel 8500-2055 900 chromel mâle male 16 8500-1053 0.93 à/to 1.91 18 à/to 14 1.60 2.80 alumel 8500-1058 chromel femelle female 8500-1054 900 alumel 8500-1059 900 Contacts Contacts pour connexions enroulées / Wire-wrap contacts Type de contact Contact type Taille de contact Contact size Références Part numbers Diagonales Diagonals Jauge Gauge (AWG) Nombre d’enroulements Number of wraps mâle male 20 8500-4220 MQ 0.78 0.85 26 28 30 3 femelle female 8500-9351 900 0.78 0.85 26 28 30 3 mâle male 16 8500-4304 LY 1.55 1.70 20 22 24 26 3 femelle female 8500-4305 900 1.55 1.70 20 22 24 26 3 * Ne pas utiliser avec embout réducteur / Not to be used with reducing sleeve 11 851 Racine / Basic series Version à souder / Solder version Version à sertir / Crimp version 851 851 00 00 E R 8 8 3A 3A P P - - 50 50 - - - - - - Type de boîtier / Shell type à souder à sertir solder crimp 00 00 01 01 02E 02R 07 07 07A 06 06 08 08 36 36 76 76 Type de raccord / Backshell type Voir tableau page 12 - See table page 12 Taille de boîtier / Shell size 8 - 10 - 12 - 14 - 16 - 18 - 20 - 22 - 24 Arrangements / Contact layouts Voir tableau page 14/15 - See table page 14/15 Type de contact / Contact type P = mâle/male - S = femelle/female Positionnement / Orientation Normal (n’apparaît pas dans la référence) w, x, y, z - voir tableau page 16 Normal (not included in part number) w, x, y, z - see table page 16 Indice obligatoire / Obligatory suffix B 50 51 52 54 Spécification / Specification sans spécification: protection cadmiée vert olive / without specification: olive green cadmium plating 29 031 44 38 42 66 Q7 R3 G4 Références / Ordering Information Connecteurs étanches / Environmental connectors embase à collerette carrée avec possibilité de raccord square flange receptacle accepting backshells prolongateur / cable connecting receptacle embase à collerette carrée sans possibilité de raccord square flange receptacle not accepting backshells embase à fixation par écrou avec possibilité de raccord jam nut receptacle accepting backshells embase à fixation par écrou sans possibilité de raccord jam nut receptacle not accepting backshells fiche droite sans bague de blindage plug for use with straight backshells fiche avec raccord coudé sans bague de blindage plug for use with 90° backshells fiche droite avec bague de blindage screened plug for use with straight backshells fiche droite avec bague de blindage et doigt de verrouillage screened plug with lock finger version à sertir sans clip avec arrangements 8-2 / 8-3 / 8-4 / 12-14 crimped version without clip which used layouts 8-2 / 8-3 / 8-4 / 12-14 contacts à sertir: dorés, toutes tailles / crimp contacts: gold plated, all sizes contacts à souder: taille 20, contacts dorés en partie active + étamés en partie arrière sauf arrangements 8-2, 8-3, 8-4 &12-14; taille 16, contacts dorés; mixte taille 20 & 16, contacts dorés / Solder contacts: size 20, contacts with gold plated active zone + tin plated termination area except layouts 8-2, 8-3, 8-4 &12-14; size 16, gold plated contacts all over; Mix size 20 & 16, gold plated contacts all over contacts à souder taille 20: dorés / solder contacts gold plated size 20 protection zinc cobalt vert olive (contacts: idem spécif.50) / zinc cobalt olive green plated (contacts idem specif.50) protection zinc nickel noir (contacts: idem spécif.50) / black zinc nickel plating (contacts idem specif.50) protection oxydation anodique noire (version à souder) / black anodised (solder version) protection oxydation anodique noire (version à sertir) / black anodised (crimp version) protection nickelée / nickel plating protection nickelée / nickel plating protection cadmiée vert olive / olive green cadmium plating version à sertir: livrée sans raccord, ni bague conique /crimp version: delivered without backshell, nor conical ring version à souder: idem version à sertir + sans grommet / solder version: idem crimp version + no grommet protection cadmiée vert olive, 500 heures brouillard salin - versions à sertir et à souder / olive green cadmium plating, salt spray 500 hr - crimp and solder versions protection cadmiée vert olive, 500 heures brouillard salin - versions à picots / olive green cadmium plating, salt spray 500 hr - PC tail version version à sertir: protection nickelée, livrée sans raccord, ni bague conique / crimp version: nickel plating, delivered without backshell, nor conical ring version à souder: idem version à sertir + sans grommet / solder version: idem crimp version + no grommet ]Pour raccord à reprise de tresse T* & RT* Backshell for screen termination, type T* & RT* 12 851 Types de raccord / Backshell types - Embases sans possibilité de raccord - 02E/02R/07A - voir page 25 - Receptacle not accepting backshells - 02E/02R/07A - see page 25 à souder solder à sertir crimp à souder solder à sertir crimp 00 01 07 06 08 36 76 00 01 07 06 08 36 76 E R raccord simple backnut 17 26 22 31 - - - 17 26 22 31 - - - EC RC raccord droit à serre-câbles straight cable clamp 17 26 22 31 - - - 17 26 22 31 - - - EC RC raccord coudé à serre-câbles 90° cable clamp - - - - 35 - - - - - - 35 - - AC raccord droit à serre-câbles sans passe-fils straight cable clamp without grommet 17 26 22 31 - - - - - - - - - - P RP raccord droit pour potting straight backshell for potting 18 27 23 32 - - - 18 27 23 32 - - - P RP raccord coudé pour potting 90° backshell for potting - - - - 35 - - - - - - 35 - - A RA raccord droit intermédiaire straight adaptor 18 27 - 32 - 36 - 18 27 - 32 - 36 - T RT raccord droit pour gaine thermorétractable straight backshell for heatshrink sleeving 19 28 23 33 - - - 19 28 23 33 - - - M RM raccord droit démontable pour gaine thermorétractable straight removable backshell for heatshrink sleeving 19 28 - 33 - - - 19 28 - 33 - - - *T *RT raccord droit démontable pour reprise de tresse et gaine thermorétractable straight removable backshell for screen termination and heatshrink sleeving Pour spécif. 38 & 42 / for specif. 38 & 42 20 29 24 - - 36 - 20 29 24 - - 36 - G RG raccord droit démontable pour reprise de tresse et gaine thermorétractable straight removable backshell for screen termination and heatshrink sleeving 20 29 24 - - 37 - 20 29 24 - - 37 - J raccord droit à presse-étoupe straight backshell with sealing gland 21 30 - 34 - - - - - - - - - - JC raccord droit à presse-étoupe et serrecâbles straight backshell with sealing gland and cable clamp 21 30 - 34 - - - - - - - - - - U RU raccord droit court pour reprise de tresse et gaine thermorétractable short backshell for screen termination and heatshrink sleeving - - - - - - 38 - - - - - - 38 Z RZ raccord droit intermédiaire pour adaptation de raccord au pas électrique straight adaptor for electrical pich access - - - 37 - - - - - - 37 - - - 13 851 Références / Ordering Information Connecteurs hermétiques / Hermetic connectors Racine / Basic series 851 02H 8 3A P - 50 - - Type de boîtier / Shell type 02H 07H IH Taille de boîtier / Shell size 8 - 10 - 12 - 14 - 16 - 18 - 20 - 22 - 24 Arrangements / Contact layouts Voir tableau page 14/15 - See table page 14/15 Type de contact / Contact type P = mâle uniquement / male only Positionnement / Orientation normal (n’apparaît pas dans la référence) w, x, y, z - voir tableau page 16 normal (not included in part number) w, x, y, z - see table page 16 Indice obligatoire / Obligatory suffix 50 Spécification / Specification sans spécification: 02H et 07H, protection cadmiée jaune / without specification: 02H and 07H, yellow cadmium plating sans spécification: IH, protection nickelée / IH, nickel 44 02H et 07H, protection nickelée / 02H and 07H, nickel Connecteurs à picots & connexions enroulées / PC tail & wire-wrap connectors Racine / Basic series 851 02E 8 3A P - 50 16 Type de boîtier / Shell type 02E 07A Taille de boîtier / Shell size 8 - 10 - 12 - 14 - 16 - 18 - 20 - 22 - 24 Arrangements / Contact layouts Voir tableau page 14/15 - See table page 14/15 Type de contact / Contact type P = mâle/male - S = femelle/female Positionnement / Orientation normal (n’apparaît pas dans la référence) w, x, y, z - voir tableau page 16 normal (not included in part number) w, x, y, z - see table page 16 Indice obligatoire / Obligatory suffix 50 51 52 54 Spécification obligatoire / Obligatory specification à picot droit à picot droit pour connexion enroulée PC tail à picot droit wire-wrap embase à collerette carrée / square flange receptacle embase à fixation par écrou / jam nut receptacle embase à collerette ronde fixation par brasage / solder fixing receptacle Contacts #20 et # 16: dorés Gold plating for size 20 and size 16 embase à collerette carrée sans possibilité de raccord square flange receptacle not accepting backshell embase à fixation par écrou sans possibilité de raccord jam nut receptacle not accepting backshell contacts à picots: taille 20, contacts dorés en partie active + étamés en partie arrière sauf arrangements 8-2, 8-3, 8-4 & 12-14; Taille 16, contacts dorés; Mixte taille 20 & 16, contacts dorés / PC tail contacts: size 20, contacts with gold plated active zone + tin plated termination area except 8-2, 8-3, 8-4 & 12-14 layouts; Size 16, gold plated contacts all over; Mix size 20 & 16, gold plated contacts all over contacts à picots taille 20: dorés / gold plating for PC tail contacts size 20 protection zinc cobalt vert olive (contacts: idem spécif.50) / zinc cobalt olive green plated (contacts idem specif.50) protection zinc nickel noir (contacts: idem spécif.50) / black zinc nickel plating (contacts idem specif.50) 16: corps cadmié vert olive 45: corps nickelé 34: contacts démontables, corps cadmié vert olive (voir tableau page 10) 34A: contacts non démontables, corps cadmié vert olive 16: olive green cadmium plated body 45: nickel plating 34: non-banded contacts, olive green cadmium plated shell (see table, page 10) 34A: banded contacts, olive green cadmium plated - Ø 1 mm contact, Ø 0.6 mm terminal / Ø 1.6 mm contact, Ø 1 mm terminal - Ø 1 mm contact, Ø 0.6 mm terminal / Ø 1.6 mm contact, Ø 1 mm terminal - contact Ø 1 mm, picot de Ø 0.6 mm / contact Ø 1.6 mm, picot de Ø 1 mm - contact Ø 1 mm, picot de Ø 0.6 mm / contact Ø 1.6 mm, picot de Ø 1 mm 14 851 Arrangements / Contact layouts Vue de face avant isolant mâle / Viewed from front face of male insulator 2 2 Ø 1 (#20) 3 3 Ø 1 (#20) 3A/98 3 Ø 1 (#20) 4 4 Ø 1 (#20) 33 3 Ø 1 (#20) 6 6 Ø 1 (#20) 7 7 Ø 1 (#20) 98 6 Ø 1 (#20) 12 3 3 Ø 1.6 (#16) 8 8 Ø 1 (#20) 10 10 Ø 1 (#20) 14 14 Ø 1 (#20) 2 2 Ø 1.6 (#16) 14 12 8 Ø 1 (#20) 4 Ø 1.6 (#16) 15 14 Ø 1 (#20) 1 Ø 1.6 (#16) 18 18 Ø 1 (#20) 19 19 Ø 1 (#20) 5 5 Ø 1.6 (#16) 16 8 8 Ø 1.6 (#16) 23 22 Ø 1 (#20) 1 Ø 1.6 (#16) 26 26 Ø 1 (#20) 18 11 11 Ø 1.6 (#16) 32 32 Ø 1 (#20) 30 29 Ø 1 (#20) 1 Ø 1.6 (#16) ■ ▲ ♦ ○ ■▲ ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ □ ♦ ○ ■ ▲ ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ □ ♦ ■ ▲ ● ♦ ○ □▲ ♦ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ♦ ○ ■ ▲ ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ♦ ○ ■ ▲ ● ♦ ○ ■ + ▲ ♦ ○ 8 10 15 851 20 16 16 Ø 1.6 (#16) 39 37 Ø 1 (#20) 2 Ø 1.6 (#1.6) 41 41 Ø 1 (#20) 24 24 Ø 1 (#20) 25 25 Ø 1 (#20) 22 36 36 Ø 1 (#20) 55 55 Ø 1 (#20) 32 32 Ø 1 (#20) 34 34 Ø 1 (#20) 21 21 Ø 1.6 (#16) 24 61 61 Ø 1 (#20) 27 27 Ø 1 (#20) Arrangements contacts à souder (QPL) / Solder contact layouts (QPL) Arrangements contacts à souder / Solder contact layouts Arrangements contacts à souder sans possibilité de passe-fils / Solder contact layouts without grommet Arrangements contacts à sertir / Crimp contact layouts Arrangements version hermétique / Hermetic version contact layouts Arrangements contacts à picots / PC tail contact layouts Arrangements contacts pour connexions enroulées / Wire-wrap contact layouts ■ □ + ▲ ● ♦ ○ ■ ▲ ♦ ○ ■ ▲ ♦ ○ □ + ▲ ♦ ○ ■ + ▲ ♦ ○ ■ ▲ ♦ ○ ■ ▲ ● ♦ ■ ▲ ♦ ○ ■ + ▲ ♦ ○ ■ ▲ ♦ ○ □ ▲ ♦ ○ ■ ▲ ● ♦ ○ ■ ▲ ● ♦ ○ Autres arrangements, nous consulter / Other layouts, please consult us 16 851 Positionnements / Orientations Isolant tournant à l’intérieur du corps métallique Insulator rotated inside metal body Vue face avant isolant mâle (corps d’embase ou corps de fiche) Viewed from front face of male insulator (receptacle or plug) boîtiers shells arrangements layouts angles en degrés / angle in degrees NFC 93422 HE 301B MIL-DTL-26482G serie 1 service1 1500 Veff 1500 Vrms service 2 2300 Veff W X Y Z 2300 Vrms souder solder sertir crimp souder solder sertir crimp 8 2 58 122 - - • X 3 60 210 - - • X 3A (98)* 60 210 - - • • X 4 45 - - - • X 33 90 - - - • • • X 10 6 90 - - - • • • • X 7* 90 - - - X 98 90 180 240 270 • • X 12 3 - - 180 - • • • • X 8 90 112 203 292 • • X 10 60 155 270 295 • • • • X 2 - - - - X 14* 45 • X 14 5 40 92 184 273 • • • • X 12 43 90 - - • • • • X 15 17 110 155 234 • • • • X 18 15 90 180 270 • • X 19 30 165 315 - • • • • X 16 8 54 152 180 331 • • • • X 23 158 270 - - • • • • X 26 60 - 275 338 • • • • X 18 11 62 119 241 340 • • • • X 32 85 138 222 265 • • • • X 30 180 193 285 350 • • X 20 16 238 318 333 347 • • • • X 39 63 144 252 333 • • • • X 41 45 126 225 - • • • • X 24 70 145 215 290 • • X 25 72 144 216 288 X 27 72 144 216 288 • • X 22 21 16 135 175 349 • • • • X 36 72 144 216 288 • X 55 30 142 226 314 • • • • X 32 72 145 215 288 • X 34 62 142 218 298 • X 24 61 90 180 270 324 • • • • X * Arrangement 8-98 : positionnements W et X non normalisés / 8-98 layout, W and X non standard ortientations Arrangements 10-7 & 12-14 : positionnement W non normalisé / 10-7 & 12-14 layouts, W non standard orientation 17 851 Embase à collerette carrée avec raccord simple Square flange receptacle with backnut Encombrements / Dimensions Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max contacts à souder J solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 E 8.. . 50.. 851 00 R 8.. . 50.. 32.70 32.00 12.03 11.70 1.32 13.50 15.09 20.99 3.13 10 851 00 E 10.. . 50.. 851 00 R 10.. . 50.. 32.70 32.00 15.01 11.70 1.32 16.70 18.26 24.19 3.13 12 851 00 E 12.. . 50.. 851 00 R 12.. . 50.. 32.70 32.00 19.07 11.70 1.32 19.90 20.62 26.54 3.13 14 851 00 E 14.. . 50.. 851 00 R 14.. . 50.. 32.70 32.00 22.25 11.70 1.32 23.40 23.00 28.89 3.13 16 851 00 E 16.. . 50.. 851 00 R 16.. . 50.. 32.70 32.00 25.42 11.70 1.32 26.60 24.61 31.29 3.13 18 851 00 E 18.. . 50.. 851 00 R 18.. . 50.. 32.70 32.00 28.60 11.70 1.32 29.50 26.97 33.69 3.13 20 851 00 E 20.. . 50.. 851 00 R 20.. . 50.. 34.50 33.40 31.77 14.35 2.15 32.70 29.36 36.89 3.13 22 851 00 E 22.. . 50.. 851 00 R 22.. . 50.. 34.50 33.40 34.95 14.35 2.15 36.00 31.75 39.99 3.13 24 851 00 E 24.. . 50.. 851 00 R 24.. . 50.. 34.50 33.40 38.12 15.20 2.15 39.10 34.92 43.15 3.81 00 E HE 301 B 00 E MS 3110 E 00 R HE 301 B 00 R MS 3120 E VG 95328 A PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Embase à collerette carrée avec raccord droit à serre-câbles Square flange receptacle with straight cable clamp Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max contacts à souder G J solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 8.. . 50.. 851 00 RC 8.. . 50 .. 48.00 47.30 12.03 11.70 1.32 19.90 15.09 20.99 3.50 3.13 10 851 00 10.. . 50.. 851 00 RC 10.. . 50.. 48.00 47.30 15.01 11.70 1.32 21.50 18.26 24.19 5.00 3.13 12 851 00 12.. . 50.. 851 00 RC 12.. . 50.. 48.00 47.30 19.07 11.70 1.32 25.00 20.62 26.54 8.20 3.13 14 851 00 14.. . 50.. 851 00 RC 14.. . 50.. 48.00 47.30 22.25 11.70 1.32 27.80 23.00 28.89 10.00 3.13 16 851 00 16.. . 50.. 851 00 RC 16.. . 50.. 51.00 50.50 25.42 11.70 1.32 29.40 24.61 31.29 13.00 3.13 18 851 00 18.. . 50.. 851 00 RC 18.. . 50.. 51.00 50.50 28.60 11.70 1.32 35.30 26.97 33.69 16.00 3.13 20 851 00 20.. . 50.. 851 00 RC 20.. . 50.. 53.00 51.50 31.77 14.35 2.15 35.30 29.36 36.89 16.00 3.13 22 851 00 22.. . 50.. 851 00 RC 22.. . 50.. 53.00 51.50 34.95 14.35 2.15 41.10 31.75 39.99 19.30 3.13 24 851 00 24.. . 50.. 851 00 RC 24.. . 50.. 53.00 51.50 38.12 15.20 2.15 42.40 34.92 43.15 20.60 3.81 00 EC HE 301 B 00 EC MS 3110 F 00 AC HE 301 B 00 AC 00 RC HE 301 B 00 RC MS 3120 F VG 95328 B PS PS PS PS PS PS PS PS PS EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC PS PS PS PS PS PS PS PS PS Note : toutes les dimensions sont en mm / all dimensions are in mm 18 851 Embase à collerette carrée avec raccord droit pour potting Square flange receptacle with straight backshell for potting 00 P HE 301 B 00 P MS 3110 P 00 RP HE 301 B 00 RP MS 3120 P Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G max contacts à souder J solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 P 8.. . 50.. 851 00 RP 8.. . 50 .. 36.20 41.70 12.03 11.70 1.32 15.34 15.09 20.99 10.46 3.13 10 851 00 P 10.. . 50.. 851 00 RP 10.. . 50.. 36.20 41.70 15.01 11.70 1.32 17.70 18.26 24.19 13.55 3.13 12 851 00 P 12.. . 50.. 851 00 RP 12.. . 50.. 36.20 41.70 19.07 11.70 1.32 21.69 20.62 26.54 13.96 3.13 14 851 00 P 14.. . 50.. 851 00 RP 14.. . 50.. 36.20 41.70 22.25 11.70 1.32 23.90 23.00 28.89 17.42 3.13 16 851 00 P 16.. . 50.. 851 00 RP 16.. . 50.. 36.20 41.70 25.42 11.70 1.32 27.00 24.61 31.29 20.56 3.13 18 851 00 P 18.. . 50.. 851 00 RP 18.. . 50.. 36.91 44.46 28.60 11.70 1.32 30.50 26.97 33.69 23.66 3.13 20 851 00 P 20.. . 50.. 851 00 RP 20.. . 50.. 43.80 50.93 31.77 14.35 2.15 33.65 29.36 36.89 23.92 3.13 22 851 00 P 22.. . 50.. 851 00 RP 22.. . 50.. 43.80 50.93 34.95 14.35 2.15 37.10 31.75 39.99 25.52 3.13 24 851 00 P 24.. . 50.. 851 00 RP 24.. . 50.. 43.80 51.40 38.12 15.20 2.15 40.00 34.92 43.15 32.00 3.81 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Embase à collerette carrée avec raccord droit intermédiaire Square flange receptacle with straight adaptor 00 A HE 301 B 00 A 00 RA HE 301 B 00 RA Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G max J K filetage threading UNEF 2A contacts à souder solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 A 8.. . 50.. 851 00 RA 8.. . 50 .. 41.00 12.03 11.70 1.32 14.50 15.09 20.99 9.10 3.13 1/2 18 10 851 00 A 10.. . 50.. 851 00 RA 10.. . 50.. 41.00 15.01 11.70 1.32 18.70 18.26 24.19 12.08 3.13 5/8 24 12 851 00 A 12.. . 50.. 851 00 RA 12.. . 50.. 41.00 19.07 11.70 1.32 21.70 20.62 26.54 15.25 3.13 3/4 20 14 851 00 A 14.. . 50.. 851 00 RA 14.. . 50.. 41.00 22.25 11.70 1.32 25.10 23.00 28.89 18.15 3.13 7/8 20 16 851 00 A 16.. . 50.. 851 00 RA 16.. . 50.. 41.00 25.42 11.70 1.32 28.13 24.61 31.29 21.32 3.13 1-20 18 851 00 A 18.. . 50.. 851 00 RA 18.. . 50.. 41.00 28.60 11.70 1.32 31.38 26.97 33.69 24.32 3.13 1-3/16 18 20 851 00 A 20.. . 50.. 851 00 RA 20.. . 50.. 44.00 31.77 14.35 2.15 34.30 29.36 36.89 26.73 3.13 1-3/16 18 22 851 00 A 22.. . 50.. 851 00 RA 22.. . 50.. 44.00 34.95 14.35 2.15 37.60 31.75 39.99 30.67 3.13 1-7/16 18 24 851 00 A 24.. . 50.. 851 00 RA 24.. . 50.. 44.00 38.12 15.20 2.15 40.70 34.92 43.15 33.08 3.81 1-7/16 18 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Note : toutes les dimensions sont en mm / all dimensions are in mm 19 851 Embase à collerette carrée avec raccord pour gaine thermorétractable Square flange receptacle with straight backshell for heatshrink sleeving 00 T 00 RT PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Embase à collerette carrée avec raccord droit démontable pour gaine thermorétractable Square flange receptacle with removable straight backshell for heatshrink sleeving PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G max J M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp souder solder sertir crimp 8 851 00 T 8.. . 50.. 851 00 RT 8.. . 50 .. 36.70 36.00 12.03 11.70 1.32 15.35 15.09 20.99 7.20 6.70 3.13 3.70 10 851 00 T 10.. . 50.. 851 00 RT 10.. . 50.. 36.70 36.00 15.01 11.70 1.32 18.15 18.26 24.19 10.20 9.40 3.13 3.70 12 851 00 T 12.. . 50.. 851 00 RT 12.. . 50.. 36.70 36.00 19.07 11.70 1.32 23.45 20.62 26.54 13.20 11.95 3.13 3.70 14 851 00 T 14.. . 50.. 851 00 RT 14.. . 50.. 36.70 36.00 22.25 11.70 1.32 24.25 23.00 28.89 16.10 15.15 3.13 3.70 16 851 00 T 16.. . 50.. 851 00 RT 16.. . 50.. 39.00 38.30 25.42 11.70 1.32 29.55 24.61 31.29 19.25 18.05 3.13 3.70 18 851 00 T 18.. . 50.. 851 00 RT 18.. . 50.. 39.00 38.30 28.60 11.70 1.32 31.75 26.97 33.69 21.30 19.95 3.13 3.70 20 851 00 T 20.. . 50.. 851 00 RT 20.. . 50.. 45.30 44.20 31.77 14.35 2.15 35.85 29.36 36.89 24.40 23.05 3.13 3.70 22 851 00 T 22.. . 50.. 851 00 RT 22.. . 50.. 45.30 44.20 34.95 14.35 2.15 38.20 31.75 39.99 27.50 25.55 3.13 3.70 24 851 00 T 24.. . 50.. 851 00 RT 24.. . 50.. 44.00 42.60 38.12 15.20 2.15 41.30 34.92 43.15 30.60 28.65 3.81 3.70 00 M 00 RM Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G max J M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 M 8.. . 50.. 851 00 RM 8.. . 50 .. 50.00 12.03 11.70 1.32 13.55 15.09 20.99 7.05 3.13 3.50 10 851 00 M 10.. . 50.. 851 00 RM 10.. . 50.. 50.00 15.01 11.70 1.32 15.35 18.26 24.19 9.90 3.13 3.50 12 851 00 M 12.. . 50.. 851 00 RM 12.. . 50.. 50.00 19.07 11.70 1.32 19.48 20.62 26.54 12.60 3.13 3.50 14 851 00 M 14.. . 50.. 851 00 RM 14.. . 50.. 50.00 22.25 11.70 1.32 21.30 23.00 28.89 15.90 3.13 3.50 16 851 00 M 16.. . 50.. 851 00 RM 16.. . 50.. 50.00 25.42 11.70 1.32 24.50 24.61 31.29 18.95 3.13 3.50 18 851 00 M 18.. . 50.. 851 00 RM 18.. . 50.. 50.00 28.60 11.70 1.32 26.45 26.97 33.69 20.90 3.13 3.50 20 851 00 M 20.. . 50.. 851 00 RM 20.. . 50.. 53.30 31.77 14.35 2.15 30.73 29.36 36.89 23.70 3.13 3.50 22 851 00 M 22.. . 50.. 851 00 RM 22.. . 50.. 53.30 34.95 14.35 2.15 34.24 31.75 39.99 26.60 3.13 3.50 24 851 00 M 24.. . 50.. 851 00 RM 24.. . 50.. 53.30 38.12 15.20 2.15 36.47 34.92 43.15 29.30 3.81 3.50 PS PS PS PS PS PS PS PS PS Note : toutes les dimensions sont en mm / all dimensions are in mm 20 851 Embase à collerette carrée avec raccord droit démontable pour reprise de tresse et gaine thermorétractable (spécifications 38 & 42) / Square flange receptacle with removable backshell for screen termination and heatshrink sleeving (38 & 42 suffix) 00 T 00 RT Embase à collerette carrée avec raccord droit démontable pour reprise de tresse et gaine thermorétractable / Square flange receptacle with removable straight backshell for screen termination and heatshrink sleeving 00 G 00 RG VG 95328 R Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G max J M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 G 8.. .50.. 851 00 RG 8.. .50 .. 54.00 12.03 11.70 1.32 16.30 15.09 20.99 7.45 3.13 3.60 10 851 00 G 10.. .50.. 851 00 RG 10.. .50.. 54.00 15.01 11.70 1.32 18.30 18.26 24.19 10.30 3.13 3.60 12 851 00 G 12.. .50.. 851 00 RG 12.. .50.. 54.00 19.07 11.70 1.32 22.30 20.62 26.54 13.20 3.13 3.60 14 851 00 G 14.. .50.. 851 00 RG 14.. .50.. 54.00 22.25 11.70 1.32 25.30 23.00 28.89 16.50 3.13 3.60 16 851 00 G 16.. .50.. 851 00 RG 16.. .50.. 54.00 25.42 11.70 1.32 28.30 24.61 31.29 19.35 3.13 3.60 18 851 00 G 18.. .50.. 851 00 RG 18.. .50.. 54.00 28.60 11.70 1.32 32.30 26.97 33.69 21.60 3.13 3.60 20 851 00 G 20.. .50.. 851 00 RG 20.. .50.. 59.30 31.77 14.35 2.15 34.30 29.36 36.89 24.80 3.13 3.60 22 851 00 G 22.. .50.. 851 00 RG 22.. .50.. 59.30 34.95 14.35 2.15 38.30 31.75 39.99 27.90 3.13 3.60 24 851 00 G 24.. .50.. 851 00 RG 24.. .50.. 59.30 38.12 15.20 2.15 41.30 34.92 43.15 31.00 3.81 3.60 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G max J M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 00 T 8.. . 50 851 00 RT 8.. . 50 51.60 12.03 11.70 1.32 18.25 15.09 20.99 7.45 3.13 3.70 10 851 00 T 10.. . 50 851 00 RT 10.. . 50 51.60 15.01 11.70 1.32 20.25 18.26 24.19 9.00 3.13 3.70 12 851 00 T 12.. . 50 851 00 RT 12.. . 50 51.60 19.07 11.70 1.32 24.75 20.62 26.54 13.30 3.13 3.70 14 851 00 T 14.. . 50 851 00 RT 14.. . 50 51.60 22.25 11.70 1.32 27.75 23.00 28.89 16.50 3.13 3.70 16 851 00 T 16.. . 50 851 00 RT 16.. . 50 51.60 25.42 11.70 1.32 30.05 24.61 31.29 18.50 3.13 3.70 18 851 00 T 18.. . 50 851 00 RT 18.. . 50 52.00 28.60 11.70 1.32 34.15 26.97 33.69 21.90 3.13 3.70 20 851 00 T 20.. . 50 851 00 RT 20.. . 50 55.10 31.77 14.35 2.15 37.25 29.36 36.89 25.10 3.13 3.70 22 851 00 T 22.. . 50 851 00 RT 22.. . 50 55.10 34.95 14.35 2.15 40.45 31.75 39.99 28.20 3.13 3.70 24 851 00 T 24.. . 50 851 00 RT 24.. . 50 55.10 38.12 15.20 2.15 43.65 34.92 43.15 31.40 3.81 3.70 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 Note : toutes les dimensions sont en mm / all dimensions are in mm 21 851 Embase à collerette carrée avec raccord droit presse-étoupe Square flange receptacle with straight sealing gland backshell 00 J HE 301 B 00J Embase à collerette carrée avec raccord droit à presse-étoupe et serre-câbles Square flange receptacle with straight sealing gland and cable clamp PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G contacts à souder J solder contacts contacts à sertir crimp contacts souder solder sertir crimp min max 8 851 00 J 8.. . 50.. - 47.60 - 12.03 11.70 1.32 14.40 15.09 20.99 5.02 5.84 3.13 10 851 00 J 10.. . 50.. - 47.60 - 15.01 11.70 1.32 17.60 18.26 24.19 5.94 6.76 3.13 12 851 00 J 12.. . 50.. - 48.70 - 19.07 11.70 1.32 21.10 20.62 26.54 9.34 10.16 3.13 14 851 00 J 14.. . 50.. - 53.50 - 22.25 11.70 1.32 24.40 23.00 28.89 11.32 12.14 3.13 16 851 00 J 16.. . 50.. - 59.00 - 25.42 11.70 1.32 27.60 24.61 31.29 14.73 15.55 3.13 18 851 00 J 18.. . 50.. - 65.00 - 28.60 11.70 1.32 30.80 26.97 33.69 16.00 16.82 3.13 20 851 00 J 20.. . 50.. - 79.10 - 31.77 14.35 2.15 34.10 29.36 36.89 16.89 17.70 3.13 22 851 00 J 22.. . 50.. - 80.00 - 34.95 14.35 2.15 37.30 31.75 39.99 17.78 18.60 3.13 24 851 00 J 24.. . 50.. - 90.00 - 38.12 15.20 2.15 40.50 34.92 43.15 20.34 21.16 3.81 PS PS PS PS PS PS PS PS PS 00 JC MS 3110 J Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max G contacts à souder J solder contacts contacts à sertir crimp contacts souder solder sertir crimp min max 8 851 00 JC 8.. .50.. - 57.68 - 12.03 11.70 1.32 19.90 15.09 20.99 5.02 5.84 3.13 10 851 00 JC 10.. .50.. - 57.68 - 15.01 11.70 1.32 21.50 18.26 24.19 5.94 6.76 3.13 12 851 00 JC 12.. .50.. - 61.24 - 19.07 11.70 1.32 25.00 20.62 26.54 9.34 10.16 3.13 14 851 00 JC 14.. .50.. - 66.01 - 22.25 11.70 1.32 27.80 23.00 28.89 11.32 12.14 3.13 16 851 00 JC 16.. .50.. - 74.75 - 25.42 11.70 1.32 29.40 24.61 31.29 14.73 15.55 3.13 18 851 00 JC 18.. .50.. - 80.57 - 28.60 11.70 1.32 35.30 26.97 33.69 16.00 16.82 3.13 20 851 00 JC 20.. .50.. - 91.69 - 31.77 14.35 2.15 35.30 29.36 36.89 16.89 17.70 3.13 22 851 00 JC 22.. .50.. - 95.66 - 34.95 14.35 2.15 41.10 31.75 39.99 17.78 18.60 3.13 24 851 00 JC 24.. .50.. - 101.22 - 38.12 15.20 2.15 42.40 34.92 43.15 20.34 21.16 3.81 Note : toutes les dimensions sont en mm / all dimensions are in mm 22 851 Embase à fixation par écrou avec raccord simple Jam nut receptacle with backnut 07 E HE 301 B 07 E MS 3114 E 07 R HE 301 B 07 R MS 3124 E VG 95328 D Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 07 E 8.. . 50.. 851 07 R 8.. . 50 .. 34.10 33.50 12.03 17.90 2.64 18.50 26.94 19.29 23.94 10 851 07 E 10.. . 50.. 851 07 R 10.. . 50.. 34.10 33.50 15.01 17.90 2.64 21.70 30.14 22.38 26.94 12 851 07 E 12.. . 50.. 851 07 R 12.. . 50.. 34.10 33.50 19.07 17.90 2.64 24.90 34.94 27.13 31.74 14 851 07 E 14.. . 50.. 851 07 R 14.. . 50.. 34.10 33.50 22.25 17.90 2.64 28.10 38.04 30.33 34.94 16 851 07 E 16.. . 50.. 851 07 R 16.. . 50.. 34.10 33.50 25.42 17.90 2.64 31.20 41.24 33.48 38.24 18 851 07 E 18.. . 50.. 851 07 R 18.. . 50.. 34.10 33.50 28.60 17.90 2.64 34.40 44.44 36.68 41.34 20 851 07 E 20.. . 50.. 851 07 R 20.. . 50.. 39.30 37.90 31.77 22.45 3.44 38.30 49.14 39.83 46.04 22 851 07 E 22.. . 50.. 851 07 R 22.. . 50.. 39.30 37.90 34.95 22.45 3.44 41.50 52.24 43.03 49.24 24 851 07 E 24.. . 50.. 851 07 R 24.. . 50.. 39.30 37.90 38.12 22.30 3.44 44.70 55.54 46.18 52.74 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 07 8.. . 50.. 851 07 RC 8.. . 50 .. 49.31 49.10 12.03 17.90 2.64 19.90 26.94 3.50 19.29 23.94 10 851 07 10.. . 50.. 851 07 RC 10.. . 50.. 49.31 49.10 15.01 17.90 2.64 21.50 30.14 5.00 22.38 26.94 12 851 07 12.. . 50.. 851 07 RC 12.. . 50.. 49.17 49.10 19.07 17.90 2.64 25.00 34.94 8.20 27.13 31.74 14 851 07 14.. . 50.. 851 07 RC 14.. . 50.. 49.17 49.10 22.25 17.90 2.64 27.80 38.04 10.00 30.33 34.94 16 851 07 16.. . 50.. 851 07 RC 16.. . 50.. 52.34 52.20 25.42 17.90 2.64 29.40 41.24 13.00 33.48 38.24 18 851 07 18.. . 50.. 851 07 RC 18.. . 50.. 53.22 53.10 28.60 17.90 2.64 35.30 44.44 16.00 36.68 41.34 20 851 07 20.. . 50.. 851 07 RC 20.. . 50.. 58.10 58.00 31.77 22.45 3.44 35.30 49.14 16.00 39.83 46.04 22 851 07 22.. . 50.. 851 07 RC 22.. . 50.. 58.10 58.00 34.95 22.45 3.44 41.10 52.24 19.30 43.03 49.24 24 851 07 24.. . 50.. 851 07 RC 24.. . 50.. 58.10 58.00 38.12 23.30 3.44 42.40 55.54 20.60 46.18 52.74 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 07 EC HE 301 B 07 EC MS 3114 F 07 AC HE 301 B 07 AC 07 RC HE 301 B 07 RC MS 3124 F VG 95328 E EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC Note : toutes les dimensions sont en mm / all dimensions are in mm Embase à fixation par écrou avec raccord droit à serre-câbles Jam nut receptacle with straight cable clamp 23 851 Embase à fixation par écrou avec raccord droit pour potting Jam nut receptacle with straight backshell for potting Embase à fixation par écrou avec raccord droit pour gaine thermorétractable Jam nut receptacle with straight backshell for heatshrink sleeving PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 07 T 07 RT VG 95328 S 07 P HE 301 B 07 P MS 3114 P 07 RP HE 301 B 07 RP MS 3124 P Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 07 P 8.. . 50.. 851 07 RP 8.. . 50 .. 34.30 39.80 12.03 17.90 2.64 15.34 26.94 10.46 19.29 23.94 10 851 07 P 10.. . 50.. 851 07 RP 10.. . 50.. 34.30 39.80 15.01 17.90 2.64 17.70 30.14 13.55 22.38 26.94 12 851 07 P 12.. . 50.. 851 07 RP 12.. . 50.. 34.30 39.80 19.07 17.90 2.64 21.69 34.94 13.96 27.13 31.74 14 851 07 P 14.. . 50.. 851 07 RP 14.. . 50.. 34.30 39.80 22.25 17.90 2.64 23.90 38.04 17.42 30.33 34.94 16 851 07 P 16.. . 50.. 851 07 RP 16.. . 50.. 34.30 39.80 25.42 17.90 2.64 27.00 41.24 20.56 33.48 38.24 18 851 07 P 18.. . 50.. 851 07 RP 18.. . 50.. 34.10 41.80 28.60 17.90 2.64 30.50 44.44 23.66 36.68 41.34 20 851 07 P 20.. . 50.. 851 07 RP 20.. . 50.. 42.25 49.92 31.77 22.45 3.44 33.65 49.14 23.92 39.83 46.04 22 851 07 P 22.. . 50.. 851 07 RP 22.. . 50.. 42.25 49.92 34.95 22.45 3.44 37.10 52.24 25.52 43.03 49.24 24 851 07 P 24.. . 50.. 851 07 RP 24.. . 50.. 43.26 51.30 38.12 23.30 3.44 40.00 55.54 32.00 46.18 52.74 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max M max P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp souder solder sertir crimp 8 851 07 T 8.. . 50.. 851 07 RT 8.. . 50 .. 42.60 41.50 12.03 17.90 2.64 15.35 26.94 7.20 6.70 3.70 19.29 23.94 10 851 07 T 10.. . 50.. 851 07 RT 10.. . 50.. 42.60 41.50 15.01 17.90 2.64 18.15 30.14 10.20 9.40 3.70 22.38 26.94 12 851 07 T 12.. . 50.. 851 07 RT 12.. . 50.. 42.60 41.50 19.07 17.90 2.64 23.45 34.94 13.20 11.95 3.70 27.13 31.74 14 851 07 T 14.. . 50.. 851 07 RT 14.. . 50.. 42.60 41.50 22.25 17.90 2.64 24.25 38.04 16.10 15.15 3.70 30.33 34.94 16 851 07 T 16.. . 50.. 851 07 RT 16.. . 50.. 44.40 43.80 25.42 17.90 2.64 29.55 41.24 19.25 18.05 3.70 33.48 38.24 18 851 07 T 18.. . 50.. 851 07 RT 18.. . 50.. 44.40 43.80 28.60 17.90 2.64 31.75 44.44 21.30 19.95 3.70 36.68 41.24 20 851 07 T 20.. . 50.. 851 07 RT 20.. . 50.. 50.90 49.80 31.77 22.45 3.44 35.85 49.14 24.40 23.05 3.70 39.83 46.04 22 851 07 T 22.. . 50.. 851 07 RT 22.. . 50.. 50.90 49.80 34.95 22.45 3.44 38.20 52.24 27.50 25.55 3.70 43.03 49.24 24 851 07 T 24.. . 50.. 851 07 RT 24.. . 50.. 49.90 48.50 38.12 23.30 3.44 41.30 55.54 30.60 28.65 3.70 46.18 52.74 Note : toutes les dimensions sont en mm / all dimensions are in mm 24 851 07 T 07 RT PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Embase à fixation par écrou avec raccord droit démontable pour reprise de tresse et gaine thermorétractable (spécifications 38 & 42) / Jam nut receptacle with removable straight backshell for screen termination and heatshrink sleeving (38 & 42 suffix) Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max M max P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 07 T 8.. . 50 851 07 RT 8.. . 50 60.00 12.03 17.90 2.64 18.25 26.94 7.45 3.70 19.29 23.94 10 851 07 T 10.. . 50 851 07 RT 10.. . 50 60.00 15.01 17.90 2.64 20.25 30.14 9.00 3.70 22.38 26.94 12 851 07 T 12.. . 50 851 07 RT 12.. . 50 60.00 19.07 17.90 2.64 24.75 34.94 13.30 3.70 27.13 31.74 14 851 07 T 14.. . 50 851 07 RT 14.. . 50 60.00 22.25 17.90 2.64 27.75 38.04 16.50 3.70 30.33 34.94 16 851 07 T 16.. . 50 851 07 RT 16.. . 50 60.00 25.42 17.90 2.64 30.05 41.24 18.50 3.70 33.48 38.24 18 851 07 T 18.. . 50 851 07 RT 18.. . 50 60.40 28.60 17.90 2.64 34.15 44.44 21.90 3.70 36.68 41.34 20 851 07 T 20.. . 50 851 07 RT 20.. . 50 63.40 31.77 22.45 3.44 37.25 49.14 25.10 3.70 39.83 46.04 22 851 07 T 22.. . 50 851 07 RT 22.. . 50 63.40 34.95 22.45 3.44 40.45 52.24 28.20 3.70 43.03 49.24 24 851 07 T 24.. . 50 851 07 RT 24.. . 50 63.40 38.12 23.30 3.44 43.65 55.54 31.40 3.70 46.18 52.74 Embase à fixation par écrou avec raccord droit démontable pour reprise de tresse et gaine thermorétractable / Jam nut receptacle with removable straight backshell for screen termination and heatshrink sleeving 07 G 07 RG VG 95328 T 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max M max P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 07 G 8.. . 50 851 07 RG 8.. . 50 62.20 12.03 17.90 2.64 16.30 26.94 7.45 3.60 19.29 23.94 10 851 07 G 10.. . 50 851 07 RG 10.. . 50 62.20 15.01 17.90 2.64 18.30 30.14 10.30 3.60 22.38 26.94 12 851 07 G 12.. . 50 851 07 RG 12.. . 50 62.20 19.07 17.90 2.64 22.30 34.94 13.20 3.60 27.13 31.74 14 851 07 G 14.. . 50 851 07 RG 14.. . 50 62.40 22.25 17.90 2.64 25.30 38.04 16.50 3.60 30.33 34.94 16 851 07 G 16.. . 50 851 07 RG 16.. . 50 62.40 25.42 17.90 2.64 28.30 41.24 19.35 3.60 33.48 38.24 18 851 07 G 18.. . 50 851 07 RG 18.. . 50 62.40 28.60 17.90 2.64 32.30 44.44 21.60 3.60 36.68 41.34 20 851 07 G 20.. . 50 851 07 RG 20.. . 50 67.50 31.77 22.45 3.44 34.30 49.14 24.80 3.60 39.83 46.04 22 851 07 G 22.. . 50 851 07 RG 22.. . 50 67.50 34.95 22.45 3.44 38.30 52.24 27.90 3.60 43.03 49.24 24 851 07 G 24.. . 50 851 07 RG 24.. . 50 67.50 38.12 23.30 3.44 41.30 55.54 31.00 3.60 46.18 52.74 Note : toutes les dimensions sont en mm / all dimensions are in mm 25 851 Embase à collerette carrée sans possibilité de raccord Square flange receptacle not accepting backshell Embase à fixation par écrou sans possibilité de raccord Jam nut receptacle not accepting backshell PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 07 A HE 301 B 07 A 02 E HE 301 B 02 E MS 3112 E VG 95328 H 02 R HE 301 B 02 R MS 3122 E VG 95328 C PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max E F max contacts à souder J solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 02 E 8.. . 50.. 851 02 R 8.. . 50 .. 25.18 32.35 12.03 11.70 1.32 10.84 15.09 20.99 3.13 10 851 02 E 10.. . 50.. 851 02 R 10.. . 50.. 25.10 32.35 15.01 11.70 1.32 13.99 18.26 24.19 3.13 12 851 02 E 12.. . 50.. 851 02 R 12.. . 50.. 25.10 32.35 19.07 11.70 1.32 17.37 20.62 26.54 3.13 14 851 02 E 14.. . 50.. 851 02 R 14.. . 50.. 25.10 32.35 22.25 11.70 1.32 20.57 23.00 28.89 3.13 16 851 02 E 16.. . 50.. 851 02 R 16.. . 50.. 25.10 32.35 25.42 11.70 1.32 23.72 24.61 31.29 3.13 18 851 02 E 18.. . 50.. 851 02 R 18.. . 50.. 25.10 32.35 28.60 11.70 1.32 26.69 26.97 33.69 3.13 20 851 02 E 20.. . 50.. 851 02 R 20.. . 50.. 26.67 33.95 31.77 14.35 2.15 29.89 29.36 36.89 3.13 22 851 02 E 22.. . 50.. 851 02 R 22.. . 50.. 26.67 33.95 34.95 14.35 2.15 33.04 31.75 39.99 3.13 24 851 02 E 24.. . 50.. 851 02 R 24.. . 50.. 26.67 33.95 38.12 15.20 2.15 36.24 34.92 43.15 3.81 Taille de boîtier Shell size Références / Part numbers L max A B max C max F max P max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 07 A 8.. . 50.. - 25.18 - 12.03 17.90 2.64 26.94 19.29 23.94 10 851 07 A 10.. . 50.. - 25.10 - 15.01 17.90 2.64 30.14 22.38 26.94 12 851 07 A 12.. . 50.. - 25.10 - 19.07 17.90 2.64 34.94 27.13 31.74 14 851 07 A 14.. . 50.. - 25.10 - 22.25 17.90 2.64 38.04 30.33 34.94 16 851 07 A 16.. . 50.. - 25.10 - 25.42 17.90 2.64 41.24 33.48 38.24 18 851 07 A 18.. . 50.. - 25.10 - 28.60 17.90 2.64 44.44 36.68 41.34 20 851 07 A 20.. . 50.. - 26.67 - 31.77 22.45 3.44 49.14 39.83 46.04 22 851 07 A 22.. . 50.. - 26.67 - 34.95 22.45 3.44 52.24 43.03 49.24 24 851 07 A 24.. . 50.. - 26.67 - 38.12 23.30 3.44 55.54 46.18 52.74 Note : toutes les dimensions sont en mm / all dimensions are in mm 26 851 Prolongateur avec raccord simple Cable connecting receptacle with backnut 01 E HE 301 B 01 E MS 3111 E 01 R HE 301 B 01 R MS 3121 E PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Prolongateur avec raccord droit à serre-câbles Cable connecting receptacle with straight cable clamp PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 01 EC HE 301 B 01 EC MS 3111 F 01 AC HE 301 B 01 AC 01 RC HE 301 B 01 RC MS 3121 F EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 E 8.. . 50.. 851 01 R 8.. . 50.. 32.70 32.00 12.03 10.60 2.10 13.50 24.24 20.99 10 851 01 E 10.. . 50.. 851 01 R 10.. . 50.. 32.70 32.00 15.01 10.60 2.10 16.70 27.44 24.19 12 851 01 E 12.. . 50.. 851 01 R 12.. . 50.. 32.70 32.00 19.07 10.60 2.10 19.90 29.79 26.54 14 851 01 E 14.. . 50.. 851 01 R 14.. . 50.. 32.70 32.00 22.25 10.60 2.10 23.40 32.10 28.89 16 851 01 E 16.. . 50.. 851 01 R 16.. . 50.. 32.70 32.00 25.42 10.60 2.10 26.60 34.59 31.29 18 851 01 E 18.. . 50.. 851 01 R 18.. . 50.. 32.70 32.00 28.60 10.60 2.10 29.50 36.94 33.69 20 851 01 E 20.. . 50.. 851 01 R 20.. . 50.. 34.50 33.40 31.77 13.85 2.65 32.70 40.14 36.89 22 851 01 E 22.. . 50.. 851 01 R 22.. . 50.. 34.50 33.40 34.95 13.85 2.65 36.00 43.24 40.00 24 851 01 E 24.. . 50.. 851 01 R 24.. . 50.. 34.50 33.40 38.12 14.70 2.65 39.10 46.44 43.29 Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 8.. . 50.. 851 01 RC 8.. . 50 .. 48.00 47.30 12.03 10.60 2.10 19.90 24.24 3.50 20.99 10 851 01 10.. . 50.. 851 01 RC 10.. . 50.. 48.00 47.30 15.01 10.60 2.10 21.50 27.44 5.00 24.19 12 851 01 12.. . 50.. 851 01 RC 12.. . 50.. 48.00 47.30 19.07 10.60 2.10 25.00 29.79 8.20 26.54 14 851 01 14.. . 50.. 851 01 RC 14.. . 50.. 48.00 47.30 22.25 10.60 2.10 27.80 32.10 10.00 28.89 16 851 01 16.. . 50.. 851 01 RC 16.. . 50.. 51.00 50.50 25.42 10.60 2.10 29.40 34.59 13.00 31.29 18 851 01 18.. . 50.. 851 01 RC 18.. . 50.. 51.00 50.50 28.60 10.60 2.10 35.30 36.94 16.00 33.69 20 851 01 20.. . 50.. 851 01 RC 20.. . 50.. 53.00 51.50 31.77 13.85 2.65 35.30 40.14 16.00 36.89 22 851 01 22.. . 50.. 851 01 RC 22.. . 50.. 53.00 51.50 34.95 13.85 2.65 41.10 43.24 19.30 40.00 24 851 01 24.. . 50.. 851 01 RC 24.. . 50.. 53.00 51.50 38.12 14.70 2.65 42.40 46.44 20.60 43.29 Note : toutes les dimensions sont en mm / all dimensions are in mm 27 851 Prolongateur avec raccord droit pour potting Cable connecting receptacle with straight backshell for potting Prolongateur avec raccord droit intermédiaire Cable connecting receptacle with straight adaptor PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 01 A HE 301 B 01 A 01 RA HE 301 B 01 RA 01 P HE 301 B 01 P MS 3111 P 01 RP HE 301 B 01 RP MS 3121 P PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 P 8.. . 50.. 851 01 RP 8.. . 50 .. 36.20 41.70 12.03 10.60 2.10 15.34 24.24 10.46 20.99 10 851 01 P 10.. . 50.. 851 01 RP 10.. . 50.. 36.20 41.70 15.01 10.60 2.10 17.70 27.44 13.55 24.19 12 851 01 P 12.. . 50.. 851 01 RP 12.. . 50.. 36.20 41.70 19.07 10.60 2.10 21.69 29.79 13.96 26.54 14 851 01 P 14.. . 50.. 851 01 RP 14.. . 50.. 36.20 41.70 22.25 10.60 2.10 23.90 32.10 17.42 28.89 16 851 01 P 16.. . 50.. 851 01 RP 16.. . 50.. 36.20 41.70 25.42 10.60 2.10 27.00 34.59 20.56 31.29 18 851 01 P 18.. . 50.. 851 01 RP 18.. . 50.. 36.91 44.46 28.60 10.60 2.10 30.50 36.94 23.66 33.69 20 851 01 P 20.. . 50.. 851 01 RP 20.. . 50.. 43.80 50.93 31.77 13.85 2.65 33.65 40.15 23.92 36.89 22 851 01 P 22.. . 50.. 851 01 RP 22.. . 50.. 43.80 50.93 34.95 13.85 2.65 37.10 42.24 25.52 40.00 24 851 01 P 24.. . 50.. 851 01 RP 24.. . 50.. 43.80 50.93 38.12 14.70 2.65 40.00 46.44 32.00 43.29 Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max K filetage threading UNEF 2A P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 A 8.. . 50.. 851 01 RA 8.. . 50 .. 41.00 12.03 10.60 2.10 14.50 24.24 9.10 1/2 28 20.99 10 851 01 A 10.. . 50.. 851 01 RA 10.. . 50.. 41.00 15.01 10.60 2.10 18.70 27.44 12.08 5/8 24 24.19 12 851 01 A 12.. . 50.. 851 01 RA 12.. . 50.. 41.00 19.07 10.60 2.10 21.70 29.79 15.25 3/4 20 26.54 14 851 01 A 14.. . 50.. 851 01 RA 14.. . 50.. 41.00 22.25 10.60 2.10 25.10 32.10 18.15 7/8 20 28.89 16 851 01 A 16.. . 50.. 851 01 RA 16.. . 50.. 41.00 25.42 10.60 2.10 28.13 34.59 21.32 1-20 31.29 18 851 01 A 18.. . 50.. 851 01 RA 18.. . 50.. 41.00 28.60 10.60 2.10 31.38 36.94 24.32 1-3/16 18 33.69 20 851 01 A 20.. . 50.. 851 01 RA 20.. . 50.. 44.00 31.77 13.85 2.65 34.30 40.15 26.73 1-3/16 18 36.89 22 851 01 A 22.. . 50.. 851 01 RA 22.. . 50.. 44.00 34.95 13.85 2.65 37.60 42.24 30.67 1-7/16 18 40.00 24 851 01 A 24.. . 50.. 851 01 RA 24.. . 50.. 44.00 38.12 14.70 2.65 40.70 46.44 33.08 1-7/16 18 43.29 PS PS PS PS PS PS PS PS PS Note : toutes les dimensions sont en mm / all dimensions are in mm 28 851 Prolongateur avec raccord droit pour gaine thermorétractable Cable connecting receptacle with straight backshell for heatshrink sleeving 01 T 01 RT PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Prolongateur avec raccord droit démontable pour gaine thermorétractable Cable connecting receptacle with removable straight backshell for heatshrink sleeving PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max P max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp souder solder sertir crimp 8 851 01 T 8.. .50.. 851 01 RT 8.. .50.. 36.70 36.00 12.03 10.60 2.10 15.35 24.24 7.20 6.70 20.99 3.70 10 851 01 T 10.. .50.. 851 01 RT 10.. .50.. 36.70 36.00 15.01 10.60 2.10 18.15 27.44 10.20 9.40 24.19 3.70 12 851 01 T 12.. .50.. 851 01 RT 12.. .50.. 36.70 36.00 19.07 10.60 2.10 23.45 29.70 13.20 11.95 26.54 3.70 14 851 01 T 14.. .50.. 851 01 RT 14.. .50.. 36.70 36.00 22.25 10.60 2.10 24.25 32.10 16.10 15.15 28.89 3.70 16 851 01 T 16.. .50.. 851 01 RT 16.. .50.. 39.00 38.30 25.42 10.60 2.10 29.55 34.59 19.25 18.05 31.29 3.70 18 851 01 T 18.. .50.. 851 01 RT 18.. .50.. 39.00 38.30 28.60 10.60 2.10 31.75 36.94 21.30 19.95 33.69 3.70 20 851 01 T 20.. .50.. 851 01 RT 20.. .50.. 45.30 44.20 31.77 13.85 2.65 35.85 40.15 24.40 23.05 36.89 3.70 22 851 01 T 22.. .50.. 851 01 RT 22.. .50.. 45.30 44.20 34.95 13.85 2.65 38.20 42.24 27.50 25.55 40.00 3.70 24 851 01 T 24.. .50.. 851 01 RT 24.. .50.. 44.00 42.60 38.12 14.70 2.65 41.30 46.44 30.60 28.65 43.29 3.70 01 M 01 RM Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max P max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 M 8.. .50.. 851 01 RM 8.. .50 .. 50.00 12.03 10.60 2.10 13.55 24.24 7.05 20.99 3.50 10 851 01 M 10.. .50.. 851 01 RM 10.. .50.. 50.00 15.01 10.60 2.10 15.35 27.44 9.90 24.19 3.50 12 851 01 M 12.. .50.. 851 01 RM 12.. .50.. 50.00 19.07 10.60 2.10 19.48 29.79 12.60 26.54 3.50 14 851 01 M 14.. .50.. 851 01 RM 14.. .50.. 50.00 22.25 10.60 2.10 21.30 32.10 15.90 28.89 3.50 16 851 01 M 16.. .50.. 851 01 RM 16.. .50.. 50.00 25.42 10.60 2.10 24.50 34.59 18.95 31.29 3.50 18 851 01 M 18.. .50.. 851 01 RM 18.. .50.. 50.00 28.60 10.60 2.10 26.45 36.94 20.90 33.69 3.50 20 851 01 M 20.. .50.. 851 01 RM 20.. .50.. 53.30 31.77 13.85 2.65 30.75 40.15 23.70 36.89 3.50 22 851 01 M 22.. .50.. 851 01 RM 22.. .50.. 53.30 34.95 13.85 2.65 34.24 42.24 26.60 40.00 3.50 24 851 01 M 24.. .50.. 851 01 RM 24.. .50.. 53.30 38.12 14.70 2.65 36.47 46.44 29.30 43.29 3.50 Note : toutes les dimensions sont en mm / all dimensions are in mm 29 851 Prolongateur avec raccord droit démontable pour reprise de tresse et gaine thermorétractable / Cable connecting receptacle with removable straight backshell for screen termination and heatshrink sleeving PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 01 G 01 RG 01 T 01 RT PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max M max P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 G 8.. . 50.. 851 01 RG 8.. . 50 .. 54.00 12.03 10.60 2.10 16.30 24.24 7.45 3.60 20.99 10 851 01 G 10.. . 50.. 851 01 RG 10.. . 50.. 54.00 15.01 10.60 2.10 18.30 27.44 10.30 3.60 24.19 12 851 01 G 12.. . 50.. 851 01 RG 12.. . 50.. 54.00 19.07 10.60 2.10 22.30 29.79 13.20 3.60 26.54 14 851 01 G 14.. . 50.. 851 01 RG 14.. . 50.. 54.00 22.25 10.60 2.10 25.30 32.10 16.50 3.60 28.89 16 851 01 G 16.. . 50.. 851 01 RG 16.. . 50.. 54.00 25.42 10.60 2.10 28.30 34.59 19.35 3.60 31.29 18 851 01 G 18.. . 50.. 851 01 RG 18.. . 50.. 54.00 28.60 10.60 2.10 32.30 36.94 21.60 3.60 33.69 20 851 01 G 20.. . 50.. 851 01 RG 20.. . 50.. 59.30 31.77 13.85 2.65 34.30 40.15 24.80 3.60 36.89 22 851 01 G 22.. . 50.. 851 01 RG 22.. . 50.. 59.30 34.95 13.85 2.65 38.30 42.24 27.90 3.60 40.00 24 851 01 G 24.. . 50.. 851 01 RG 24.. . 50.. 59.30 38.12 14.70 2.65 41.30 46.44 31.00 3.60 43.29 PS PS PS PS PS PS PS PS PS Prolongateur avec raccord droit démontable pour reprise de tresse et gaine thermorétractable (spécifications 38 & 42) / Cable connecting receptacle with removable straight backshell for screen termination and heatshrink sleeving (38 & 42 suffix) Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G max M max P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 01 T 8.. .50 851 01 RT 8.. .50 51.60 12.03 10.60 2.10 18.25 24.24 7.45 3.70 20.99 10 851 01 T 10.. .50 851 01 RT 10.. .50 51.60 15.01 10.60 2.10 20.25 27.44 9.00 3.70 24.19 12 851 01 T 12.. .50 851 01 RT 12.. .50 51.60 19.07 10.60 2.10 24.75 29.79 13.30 3.70 26.54 14 851 01 T 14.. .50 851 01 RT 14.. .50 51.60 22.25 10.60 2.10 27.75 32.10 16.50 3.70 28.89 16 851 01 T 16.. .50 851 01 RT 16.. .50 51.60 25.42 10.60 2.10 30.05 34.59 18.50 3.70 31.29 18 851 01 T 18.. .50 851 01 RT 18.. .50 52.00 28.60 10.60 2.10 34.15 36.94 21.90 3.70 33.69 20 851 01 T 20.. .50 851 01 RT 20.. .50 55.10 31.77 13.85 2.65 37.25 40.15 25.10 3.70 36.89 22 851 01 T 22.. .50 851 01 RT 22.. .50 55.10 34.95 13.85 2.65 40.45 42.24 28.20 3.70 40.00 24 851 01 T 24.. .50 851 01 RT 24.. .50 55.10 38.12 14.70 2.65 43.65 46.44 31.40 3.70 43.29 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 Note : toutes les dimensions sont en mm / all dimensions are in mm 30 851 Prolongateur avec raccord droit à presse-étoupe Cable connecting receptacle with straight sealing gland backshell 01 J HE 301 B 01 J PS PS PS PS PS PS PS PS PS Prolongateur avec raccord droit à presse-étoupe et serre-câbles Cable connecting receptacle with straight sealing gland and cable clamp backshell PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp min max 8 851 01 J 8.. . 50.. - 47.60 - 12.03 10.60 2.10 14.40 24.24 5.02 5.84 20.99 10 851 01 J 10.. . 50.. - 47.60 - 15.01 10.60 2.10 17.60 27.44 5.94 6.76 24.19 12 851 01 J 12.. . 50.. - 48.70 - 19.07 10.60 2.10 21.10 29.79 9.34 10.16 26.54 14 851 01 J 14.. . 50.. - 53.50 - 22.25 10.60 2.10 24.40 32.10 11.32 12.14 28.89 16 851 01 J 16.. . 50.. - 59.00 - 25.42 10.60 2.10 27.60 34.59 14.73 15.55 31.29 18 851 01 J 18.. . 50.. - 65.00 - 28.60 10.60 2.10 30.80 36.94 16.00 16.82 33.69 20 851 01 J 20.. . 50.. - 79.10 - 31.77 13.85 2.65 34.10 40.15 16.89 17.71 36.89 22 851 01 J 22.. . 50.. - 80.00 - 34.95 13.85 2.65 37.30 42.24 17.78 18.60 40.00 24 851 01 J 24.. . 50.. - 90.00 - 38.12 14.70 2.65 40.50 46.44 20.34 21.16 43.29 01 JC MS 3111 J Taille de boîtier Shell size Références / Part numbers L max A B max C max D max F max G P contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp min max 8 851 01 JC 8.. .50.. - 57.68 - 12.03 10.60 2.10 19.90 24.24 5.02 5.84 20.99 10 851 01 JC 10.. .50.. - 57.68 - 15.01 10.60 2.10 21.50 27.44 5.94 6.76 24.19 12 851 01 JC 12.. .50.. - 61.24 - 19.07 10.60 2.10 25.00 29.79 9.34 10.16 26.54 14 851 01 JC 14.. .50.. - 66.01 - 22.25 10.60 2.10 27.80 32.10 11.32 12.14 28.89 16 851 01 JC 16.. .50.. - 74.75 - 25.42 10.60 2.10 29.40 34.59 14.73 15.50 31.29 18 851 01 JC 18.. .50.. - 80.57 - 28.60 10.60 2.10 35.30 36.94 16.00 16.82 33.69 20 851 01 JC 20.. .50.. - 91.69 - 31.77 13.85 2.65 35.30 40.15 16.89 17.71 36.89 22 851 01 JC 22.. .50.. - 95.66 - 34.95 13.85 2.65 41.10 42.24 17.78 18.60 40.00 24 851 01 JC 24.. .50.. - 101.22 - 38.12 14.70 2.65 42.40 46.44 20.34 21.16 43.29 Note : toutes les dimensions sont en mm / all dimensions are in mm 31 851 Fiche avec raccord simple Plug with backnut Fiche avec raccord droit à serre-câbles Plug with straight cable clamp PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 06 EC HE 301 B 06 EC MS 3116 F 06 AC HE 301 B 06 AC 06 RC HE 301 B 06 RC MS 3126 F VG 95328 K 06 E HE 301 B 06 E MS 3116 E 06 R HE 301 B 06 R MS 3126 E PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 06 E 8 .. . 50.. 851 06 R 8 .. . 50 .. 32.54 32.00 19.05 13.50 10 851 06 E 10 .. . 50.. 851 06 R 10 .. . 50.. 32.54 32.00 21.80 16.70 12 851 06 E 12 .. . 50.. 851 06 R 12 .. . 50.. 32.54 32.00 26.15 19.90 14 851 06 E 14 .. . 50.. 851 06 R 14 .. . 50.. 32.54 32.00 29.35 23.40 16 851 06 E 16 .. . 50.. 851 06 R 16 .. . 50.. 32.54 32.00 32.50 26.60 18 851 06 E 18 .. . 50.. 851 06 R 18 .. . 50.. 32.54 32.00 35.30 29.60 20 851 06 E 20 .. . 50.. 851 06 R 20 .. . 50.. 33.30 32.10 38.85 32.70 22 851 06 E 22 .. . 50.. 851 06 R 22 .. . 50.. 33.30 32.10 42.05 36.00 24 851 06 E 24 .. . 50.. 851 06 R 24 .. . 50.. 33.30 32.10 45.10 39.10 PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D max contacts à souder G solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 06 8 .. . 50.. 851 06 RC 8 .. . 50 .. 48.00 47.30 19.05 19.90 3.50 10 851 06 10 .. . 50.. 851 06 RC 10 .. . 50.. 48.00 47.30 21.80 21.50 5.00 12 851 06 12 .. . 50.. 851 06 RC 12 .. . 50.. 48.00 47.30 26.15 25.00 8.20 14 851 06 14 .. . 50.. 851 06 RC 14 .. . 50.. 48.00 47.30 29.35 27.80 10.00 16 851 06 16 .. . 50.. 851 06 RC 16 .. . 50.. 51.00 50.50 32.50 29.40 13.00 18 851 06 18 .. . 50.. 851 06 RC 18 .. . 50.. 51.00 50.50 35.30 35.30 16.00 20 851 06 20 .. . 50.. 851 06 RC 20 .. . 50.. 52.00 50.20 38.85 35.30 16.00 22 851 06 22 .. . 50.. 851 06 RC 22 .. . 50.. 52.00 50.20 42.05 41.10 19.30 24 851 06 24 .. . 50.. 851 06 RC 24 .. . 50.. 52.00 50.20 45.10 42.40 20.60 EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC EC AC Note : toutes les dimensions sont en mm / all dimensions are in mm 32 851 Fiche avec raccord droit pour potting Plug with straight backshell for potting PS PS PS PS PS PS PS PS PS Fiche avec raccord droit intermédiaire Plug with straight adaptor PS PS PS PS PS PS PS PS PS 06 P HE 301 B 06 P MS 3116 P 06 RP HE 301 B 06 RP MS 3126 P Taille de boîtier Shell size Références / Part numbers L max A max D max contacts à souder G solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 06 P 8 .. . 50.. 851 06 RP 8 .. . 50 .. 36.20 42.10 19.05 15.34 10.46 10 851 06 P 10 .. . 50.. 851 06 RP 10 .. . 50.. 36.20 42.10 21.80 17.70 13.55 12 851 06 P 12 .. . 50.. 851 06 RP 12 .. . 50.. 36.20 42.10 26.15 21.69 13.96 14 851 06 P 14 .. . 50.. 851 06 RP 14 .. . 50.. 36.20 42.10 29.35 23.90 17.42 16 851 06 P 16 .. . 50.. 851 06 RP 16 .. . 50.. 36.20 42.10 32.50 27.00 20.56 18 851 06 P 18 .. . 50.. 851 06 RP 18 .. . 50.. 37.70 45.40 35.30 30.50 23.66 20 851 06 P 20 .. . 50.. 851 06 RP 20 .. . 50.. 42.40 50.00 38.85 33.65 23.92 22 851 06 P 22 .. . 50.. 851 06 RP 22 .. . 50.. 42.40 50.00 42.05 37.10 25.52 24 851 06 P 24 .. . 50.. 851 06 RP 24 .. . 50.. 42.85 50.00 45.10 40.00 32.00 PS PS PS PS PS PS PS PS PS 06 A HE 301 B 06 A 06 RA HE 301 B 06 RA Taille de boîtier Shell size Références / Part numbers L max A max D max G max F filetage threading UNEF 2A contacts à souder solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 06 A 8 .. . 50.. 851 06 RA 8 .. . 50 .. 41.00 41.00 19.05 14.50 9.10 1/2 28 10 851 06 A 10 .. . 50.. 851 06 RA 10 .. . 50.. 41.00 41.00 21.80 18.70 12.08 5/8 24 12 851 06 A 12 .. . 50.. 851 06 RA 12 .. . 50.. 41.00 41.00 26.15 21.70 15.25 3/4 20 14 851 06 A 14 .. . 50.. 851 06 RA 14 .. . 50.. 41.00 41.00 29.35 25.10 18.15 7/8 20 16 851 06 A 16 .. . 50.. 851 06 RA 16 .. . 50.. 41.00 41.00 32.50 28.13 21.32 1-20 18 851 06 A 18 .. . 50.. 851 06 RA 18 .. . 50.. 41.00 41.00 35.30 31.38 24.32 1-3/16 18 20 851 06 A 20 .. . 50.. 851 06 RA 20 .. . 50.. 44.00 43.30 38.85 34.30 26.73 1-3/16 18 22 851 06 A 22 .. . 50.. 851 06 RA 22 .. . 50.. 44.00 43.30 42.05 37.60 30.67 1-7/16 18 24 851 06 A 24 .. . 50.. 851 06 RA 24 .. . 50.. 44.00 43.50 45.10 40.70 33.08 1-7/16 18 PS PS PS PS PS PS PS PS PS Note : toutes les dimensions sont en mm / all dimensions are in mm 33 851 Fiche avec raccord droit pour gaine thermorétractable Plug with straight backshell for heatshrink sleeving Fiche avec raccord droit démontable pour gaine thermorétractable Plug with removable straight backshell for heatshrink sleeving PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS 06 M 06 RM 06 T 06 RT VG 95328 J PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D max G max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp souder solder sertir crimp 8 851 06 T 8.. . 50.. 851 06 RT 8.. . 50 .. 36.70 36.00 19.05 15.35 7.20 6.70 3.70 10 851 06 T 10.. . 50.. 851 06 RT 10.. . 50.. 36.70 36.00 21.80 18.15 10.20 9.40 3.70 12 851 06 T 12.. . 50.. 851 06 RT 12.. . 50.. 36.70 36.00 26.15 23.45 13.20 11.95 3.70 14 851 06 T 14.. . 50.. 851 06 RT 14.. . 50.. 36.70 36.00 29.35 24.25 16.10 15.15 3.70 16 851 06 T 16.. . 50.. 851 06 RT 16.. . 50.. 39.00 38.30 32.50 29.55 19.25 18.05 3.70 18 851 06 T 18.. . 50.. 851 06 RT 18.. . 50.. 39.00 38.30 35.30 31.75 21.30 19.95 3.70 20 851 06 T 20.. . 50.. 851 06 RT 20.. . 50.. 44.00 42.90 38.85 35.85 24.40 23.05 3.70 22 851 06 T 22.. . 50.. 851 06 RT 22.. . 50.. 44.00 42.90 42.05 38.20 27.50 25.55 3.70 24 851 06 T 24.. . 50.. 851 06 RT 24.. . 50.. 42.70 41.60 45.10 41.30 30.60 28.65 3.70 Taille de boîtier Shell size Références / Part numbers L max A max D max G max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 06 M 8 .. . 50.. 851 06 RM 8 .. . 50 .. 50.00 19.05 13.55 7.05 3.50 10 851 06 M 10 .. . 50.. 851 06 RM 10 .. . 50.. 50.00 21.80 15.35 9.90 3.50 12 851 06 M 12 .. . 50.. 851 06 RM 12 .. . 50.. 50.00 26.15 19.48 12.60 3.50 14 851 06 M 14 .. . 50.. 851 06 RM 14 .. . 50.. 50.00 29.35 21.30 15.90 3.50 16 851 06 M 16 .. . 50.. 851 06 RM 16 .. . 50.. 50.00 32.50 24.50 18.95 3.50 18 851 06 M 18 .. . 50.. 851 06 RM 18 .. . 50.. 50.00 35.30 26.45 20.90 3.50 20 851 06 M 20 .. . 50.. 851 06 RM 20 .. . 50.. 52.00 38.85 30.73 23.70 3.50 22 851 06 M 22 .. . 50.. 851 06 RM 22 .. . 50.. 52.00 42.05 34.24 26.60 3.50 24 851 06 M 24 .. . 50.. 851 06 RM 24 .. . 50.. 52.00 45.10 36.47 29.30 3.50 Note : toutes les dimensions sont en mm / all dimensions are in mm 34 851 Fiche avec raccord droit à presse-étoupe Plug with straight sealing gland backshell PS PS PS PS PS PS PS PS PS Fiche avec raccord droit à presse-étoupe et serre-câbles Plug with straight sealing gland and cable clamp backshells PS PS PS PS PS PS PS PS PS 06 J HE 301 B 06 J 06 JC MS 3116 J Taille de boîtier Shell size Références / Part numbers L max A max D max G max contacts à souder solder contacts contacts à sertir crimp contacts souder solder sertir crimp min max 8 851 06 J 8 .. . 50.. - 47.60 - 19.05 14.40 5.02 5.84 10 851 06 J 10 .. . 50.. - 47.60 - 21.80 17.60 5.94 6.76 12 851 06 J 12 .. . 50.. - 49.20 - 26.15 21.10 9.34 10.16 14 851 06 J 14 .. . 50.. - 54.00 - 29.35 24.40 11.32 12.14 16 851 06 J 16 .. . 50.. - 59.60 - 32.50 27.60 14.73 15.55 18 851 06 J 18 .. . 50.. - 65.60 - 35.30 30.80 16.00 16.80 20 851 06 J 20 .. . 50.. - 78.00 - 38.85 34.10 16.89 17.71 22 851 06 J 22 .. . 50.. - 79.50 - 42.05 37.30 17.78 18.60 24 851 06 J 24 .. . 50.. - 90.00 - 45.10 40.50 20.34 21.16 Taille de boîtier Shell size Références / Part numbers L max A max D max G max contacts à souder solder contacts contacts à sertir crimp contacts souder solder sertir crimp min max 8 851 06 JC 8 .. . 50.. - 57.68 - 19.05 19.90 5.02 5.84 10 851 06 JC 10 .. . 50.. - 57.68 - 21.80 21.50 5.94 6.76 12 851 06 JC 12 .. . 50.. - 61.24 - 26.15 25.00 9.34 10.16 14 851 06 JC 14 .. . 50.. - 66.01 - 29.35 27.80 11.32 12.14 16 851 06 JC 16 .. . 50.. - 74.75 - 32.50 29.40 14.73 15.50 18 851 06 JC 18 .. . 50.. - 80.57 - 35.30 35.30 16.00 16.82 20 851 06 JC 20 .. . 50.. - 91.69 - 38.85 35.30 16.89 17.71 22 851 06 JC 22 .. . 50.. - 95.66 - 42.05 41.10 17.78 18.60 24 851 06 JC 24 .. . 50.. - 101.22 - 45.10 42.40 20.34 21.16 Note : toutes les dimensions sont en mm / all dimensions are in mm 35 851 Fiche avec raccord coudé à serre-câbles Plug with elbow cable clamp backshell PS PS PS PS PS PS PS PS PS 08 EC HE 301 B 08 EC 08 RC HE 301 B 08 RC PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D max G R contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 08 EC 8 .. . 50.. 851 08 RC 8 .. . 50.. 50.10 19.05 19.70 3.50 16.00 10 851 08 EC 10 .. . 50.. 851 08 RC 10 .. . 50.. 52.60 21.80 21.20 5.00 18.00 12 851 08 EC 12 .. . 50.. 851 08 RC 12 .. . 50.. 54.90 26.15 24.20 8.20 19.50 14 851 08 EC 14 .. . 50.. 851 08 RC 14 .. . 50.. 58.50 29.35 27.50 10.00 22.00 16 851 08 EC 16 .. . 50.. 851 08 RC 16 .. . 50.. 60.80 32.50 29.10 13.00 23.50 18 851 08 EC 18 .. . 50.. 851 08 RC 18 .. . 50.. 65.00 35.30 35.70 16.00 25.00 20 851 08 EC 20 .. . 50.. 851 08 RC 20 .. . 50.. 69.10 38.85 35.70 16.00 26.50 22 851 08 EC 22 .. . 50.. 851 08 RC 22 .. . 50.. 71.00 42.05 39.70 19.30 28.00 24 851 08 EC 24 .. . 50.. 851 08 EC 24 .. . 50.. 75.50 45.10 43.50 20.60 31.00 Fiche avec raccord coudé pour potting Plug with elbow backshell for potting PS PS PS PS PS PS PS PS PS 08 P HE 301 B 08 P 08 RP HE 301 B 08 RP PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max G max R max S contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 08 P 8 .. . 50.. 851 08 RP 8 .. . 50.. 40.70 19.05 8.10 11.70 11.30 10 851 08 P 10 .. . 50.. 851 08 RP 10 .. . 50.. 44.90 21.80 11.30 14.35 14.50 12 851 08 P 12 .. . 50.. 851 08 RP 12 .. . 50.. 46.90 26.15 13.30 15.90 17.70 14 851 08 P 14 .. . 50.. 851 08 RP 14 .. . 50.. 49.20 29.35 16.10 16.30 20.10 16 851 08 P 16 .. . 50.. 851 08 RP 16 .. . 50.. 50.60 32.50 16.90 19.30 22.80 18 851 08 P 18 .. . 50.. 851 08 RP 18 .. . 50.. 51.80 35.30 18.10 20.60 25.60 20 851 08 P 20 .. . 50.. 851 08 RP 20 .. . 50.. 53.70 38.85 19.70 21.90 28.80 22 851 08 P 22 .. . 50.. 851 08 RP 22 .. . 50.. 54.80 42.05 20.80 23.50 31.60 24 851 08 P 24 .. . 50.. 851 08 RP 24 .. . 50.. 58.20 45.10 24.20 30.15 35.20 Note : toutes les dimensions sont en mm / all dimensions are in mm 36 851 Fiche avec bracelet de blindage et raccord intermédiaire Screened plug with straight adaptor PS PS PS PS PS PS PS PS PS 36 A 36 RA VG 95328 N PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D max G max F filetage threading UNEF 2A contacts à souder solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 36 A 8 .. . 50.. 851 36 RA 8 .. . 50.. 41.00 19.05 14.50 9.10 1/2 28 10 851 36 A 10 .. . 50.. 851 36 RA 10 .. . 50.. 41.00 21.80 18.70 12.08 5/8 24 12 851 36 A 12 .. . 50.. 851 36 RA 12 .. . 50.. 41.00 26.15 21.70 15.25 3/4 20 14 851 36 A 14 .. . 50.. 851 36 RA 14 .. . 50.. 41.00 29.35 25.10 18.15 7/8 20 16 851 36 A 16 .. . 50.. 851 36 RA 16 .. . 50.. 41.00 32.50 28.13 21.32 1-20 18 851 36 A 18 .. . 50.. 851 36 RA 18 .. . 50.. 41.00 35.30 31.38 24.32 1-3/16 18 20 851 36 A 20 .. . 50.. 851 36 RA 20 .. . 50.. 43.30 38.85 34.30 26.73 1-3/16 18 22 851 36 A 22 .. . 50.. 851 36 RA 22 .. . 50.. 43.30 42.05 37.60 30.67 1-7/16 18 24 851 36 A 24 .. . 50.. 851 36 RA 24 .. . 50.. 43.50 45.10 40.70 33.08 1-7/16 18 Note : toutes les dimensions sont en mm / all dimensions are in mm PS PS PS PS PS PS PS PS PS 36 T 36 RT PS PS PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D max G max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 36 T 8 .. . 50.. 851 36 RT 8 .. . 50.. 51.60 19.05 18.25 7.45 3.70 10 851 36 T 10 .. . 50.. 851 36 RT 10 .. . 50.. 51.60 21.80 20.25 9.00 3.70 12 851 36 T 12 .. . 50.. 851 36 RT 12 .. . 50.. 51.60 26.15 24.75 13.30 3.70 14 851 36 T 14 .. . 50.. 851 36 RT 14 .. . 50.. 51.60 29.35 27.75 16.50 3.70 16 851 36 T 16 .. . 50.. 851 36 RT 16 .. . 50.. 51.60 32.50 30.05 18.50 3.70 18 851 36 T 18 .. . 50.. 851 36 RT 18 .. . 50.. 52.00 35.30 34.15 21.90 3.70 20 851 36 T 20 .. . 50.. 851 36 RT 20 .. . 50.. 53.90 38.85 37.25 25.10 3.70 22 851 36 T 22 .. . 50.. 851 36 RT 22 .. . 50.. 53.90 42.05 40.45 28.20 3.70 24 851 36 T 24 .. . 50.. 851 36 RT 24 .. . 50.. 53.90 45.10 43.65 31.40 3.70 Fiche avec bague de blindage et raccord droit démontable pour reprise de tresse et gaine thermorétractable (spécifications 38 & 42)/ Screened plug with removable straight backshell for screen termination and heatshrink sleeving (38 & 42 suffix) 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 38 42 37 851 Fiche avec bague de blindage et raccord droit démontable pour reprise de tresse et gaine thermorétractable / Screened plug with removable straight backshell for screen termination and heatshrink sleeving 36 G 36 RG VG 95328 M Taille de boîtier Shell size Références / Part numbers L max A max D max G max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 851 36 G 8 .. . 50.. 851 36 RG 8 .. . 50.. 54.00 19.05 16.30 7.45 3.60 10 851 36 G10 .. . 50.. 851 36 RG 10 .. . 50.. 54.00 21.80 18.30 10.30 3.60 12 851 36 G 12 .. . 50.. 851 36 RG 12 .. . 50.. 54.00 26.15 22.30 13.20 3.60 14 851 36 G 14 .. . 50.. 851 36 RG 14 .. . 50.. 54.00 29.35 25.30 16.50 3.60 16 851 36 G 16 .. . 50.. 851 36 RG 16 .. . 50.. 54.00 32.50 28.30 19.35 3.60 18 851 36 G 18 .. . 50.. 851 36 RG 18 .. . 50.. 54.00 35.30 32.30 21.60 3.60 20 851 36 G 20 .. . 50.. 851 36 RG 20 .. . 50.. 58.00 38.85 34.30 24.80 3.60 22 851 36 G 22 .. . 50.. 851 36 RG 22 .. . 50.. 58.00 42.05 38.30 27.90 3.60 24 851 36 G 24 .. . 50.. 851 36 RG 24 .. . 50.. 58.00 45.10 41.30 31.00 3.60 PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS PS Note : toutes les dimensions sont en mm / all dimensions are in mm PS PS PS PS PS PS PS 06 Z 06 RZ PS PS PS PS PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max B max C max D filetage threading PE contacts à souder solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 10 12 851 06 Z 12 .. . 50.. 851 06 RZ 12 .. . 50.. 43.00 26.15 9.10 24.80 11 14 851 06 Z14 .. . 50.. 851 06 RZ 14 .. . 50.. 45.00 29.35 11.00 28.80 16 16 851 06 Z 16 .. . 50.. 851 06 RZ 16 .. . 50.. 45.00 32.50 11.00 30.80 16 18 851 06 Z 18 .. . 50.. 851 06 RZ 18 .. . 50.. 46.00 35.30 12.00 40.80 21 20 851 06 Z 20 .. . 50.. 851 06 RZ 20 .. . 50.. 46.50 38.85 12.00 40.80 21 22 851 06 Z 22 .. . 50.. 851 06 RZ 22 .. . 50.. 46.50 42.05 12.00 40.80 21 24 851 06 Z24 .. . 50.. 851 06 RZ 24 .. . 50.. 65.50 45.10 31.40 45.00 29 Fiche avec raccord pour adaptation d’accessoires au pas électrique Plug with straight adaptor for electrical pitch access Le manchon intermédiaire spécial de type Z qui équipe la fiche à sertir 851 06 RZ est adapté aux accessoires de câblages. - Raccord à griffes et presse-étoupe - Raccord pour gaine polyflex - Raccord pour tuyau C.N.O.M.O. The Z type special adaptor which equips crimp plug 851 06 RZ fits following accessories. - Packing gland collet backshell - Backshell for polyflex sleeving - Backshell for C.N.O.M.O. tube 38 851 Fiche avec bague de blindage et doigt de verrouillage, avec raccord droit court à reprise de tresse et gaine thermorétractable / Screened plug with lock finger and short backshell for screen termination and heatshrink sleeving PS PS PS 76 U 76 RU PS PS PS Taille de boîtier Shell size Références / Part numbers L max A max D max H max G max E max M contacts à souder max solder contacts contacts à sertir crimp contacts souder solder sertir crimp 8 10 12 851 76 U 12.. . 50.. 851 76 R U 12.. .50.. 35.60 25.00 22.50 32.00 13.20 19.50 3.70 14 851 76 U 14.. . 50.. 851 76 R U 14.. .50.. 35.60 29.00 25.50 32.00 16.10 21.00 3.70 16 851 76 U 16.. . 50.. 851 76 R U 16.. .50.. 35.60 32.00 28.50 32.00 19.25 22.50 3.70 18 20 22 24 Note : toutes les dimensions sont en mm / all dimensions are in mm 39 851 Embase à fixation par écrou Jam nut receptacle PS PS PS PS PS PS PS PS PS 07 H HE 301 B 07 H MS 3114 H VG 95328 F Taille de boîtier Shell size Références / Part numbers A C max D max G L max M max P 8 851 07 H 8 .. . 50.. 12.03 24.07 27.37 14.26 20.53 17.93 13.33 10 851 07 H 10 .. . 50.. 15.01 27.22 30.57 17.43 20.53 17.93 16.51 12 851 07 H 12 .. . 50.. 19.07 32.00 35.32 22.19 20.53 17.93 20.63 14 851 07 H 14 .. . 50.. 22.25 35.17 38.50 25.36 20.53 17.93 23.78 16 851 07 H 16 .. . 50.. 25.42 38.35 41.67 28.54 20.53 17.93 26.93 18 851 07 H 18 .. . 50.. 28.60 41.52 44.85 31.71 20.53 17.93 30.10 20 851 07 H 20 .. . 50.. 31.77 46.27 49.62 34.89 26.10 22.70 33.28 22 851 07 H 22 .. . 50.. 34.95 49.47 52.77 38.06 26.10 22.70 36.45 24 851 07 H 24 .. . 50.. 38.12 52.62 55.97 41.24 26.93 23.54 39.63 Connecteurs hermétiques / Hermetic connectors Embase à collerette carrée Square flange receptacle PS PS PS PS PS PS PS PS PS 02 H HE 301 B 02 H Taille de boîtier Shell size Références / Part numbers A C max D max E F G H max J M max N max 8 851 02 H 8 .. . 50.. 12.03 21.42 27.09 15.09 13.84 14.27 6.97 3.13 11.24 1.67 10 851 02 H 10 .. . 50.. 15.01 24.62 31.87 18.26 13.84 17.06 6.97 3.13 11.24 1.67 12 851 02 H 12 .. . 50.. 19.07 26.98 35.04 20.62 13.84 19.85 6.97 3.13 11.24 1.67 14 851 02 H 14 .. . 50.. 22.25 29.36 38.22 23.00 13.84 23.00 6.97 3.13 11.24 1.67 16 851 02 H 16 .. . 50.. 25.42 31.73 41.39 24.61 13.84 26.18 6.97 3.13 11.24 1.67 18 851 02 H 18 .. . 50.. 28.60 34.12 44.57 26.97 13.84 29.36 6.97 3.13 11.24 1.67 20 851 02 H 20 .. . 50.. 31.77 37.20 47.74 29.36 15.42 31.74 6.99 3.13 12.00 2.48 22 851 02 H 22 .. . 50.. 34.95 40.47 50.92 31.75 16.23 34.92 6.99 3.13 12.00 2.48 24 851 02 H 24 .. . 50.. 38.12 43.66 55.69 34.92 17.04 38.10 6.19 3.81 12.81 2.48 Note : toutes les dimensions sont en mm / all dimensions are in mm 40 851 Connecteurs pour connexions enroulées et à picots droits Wire-wrap and PC tail connectors Embase à collerette ronde, fixation par brasage Solder fixing receptacle PS PS PS PS PS PS PS PS PS IH HE 301 B 1H MS 3113 H VG 95328 G Taille de boîtier Shell size Références / Part numbers A D max H max F G max M max N max 8 851 IH 8 .. . 50.. 12.03 16.40 8.19 13.84 14.27 10.69 0.76 10 851 IH 10 .. . 50.. 15.01 19.40 8.19 13.84 17.06 10.69 0.76 12 851 IH 12 .. . 50.. 19.07 21.80 8.19 13.84 19.83 10.69 0.76 14 851 IH 14 .. . 50.. 22.25 25.00 8.19 13.84 23.00 10.69 0.76 16 851 IH 16 .. . 50.. 25.42 28.10 8.19 13.84 26.18 10.69 0.76 18 851 IH 18 .. . 50.. 28.60 31.30 8.19 13.84 29.36 10.69 0.76 20 851 IH 20 .. . 50.. 31.77 33.70 8.16 15.42 31.74 12.32 0.76 22 851 IH 22 .. . 50.. 34.95 36.90 8.16 16.23 34.92 12.32 0.76 24 851 IH 24 .. . 50.. 38.12 40.10 7.36 17.04 38.10 13.12 0.76 Embase à collerette carrée type 02E Square flange receptacle type 02E PS PS PS PS PS PS PS PS PS Version pour connexions enroulées (WW) Wire-wrap version Version à picots droits PC tail version Taille de boîtier Shell size Références / Part numbers A B max C max Ø D max E F max H +1.63 0 J L max T +1.25 0 version WW WW version version à picots PC tail version 8 851 02 E 8.. .50.. 851 02 E 8.. .50.. 12.03 11.70 1.32 10.84 15.09 20.99 12.42 3.13 20.50 9.46 10 851 02 E 10.. .50.. 851 02 E 10.. .50.. 15.01 11.70 1.32 13.99 18.26 24.19 12.42 3.13 20.50 9.46 12 851 02 E 12.. .50.. 851 02 E 12.. .50.. 19.07 11.70 1.32 17.37 20.62 26.54 12.42 3.13 20.50 9.46 14 851 02 E 14.. .50.. 851 02 E 14.. .50.. 22.25 11.70 1.32 20.57 23.00 28.89 12.42 3.13 20.50 9.46 16 851 02 E 16.. .50.. 851 02 E 16.. .50.. 25.42 11.70 1.32 23.62 24.61 31.29 12.42 3.13 20.50 9.46 18 851 02 E 18.. .50.. 851 02 E 18.. .50.. 28.60 11.70 1.32 26.69 26.97 33.69 12.42 3.13 20.50 9.46 20 851 02 E 20.. .50.. 851 02 E 20.. .50.. 31.77 14.35 2.15 29.89 29.36 36.89 10.69 3.13 23.80 7.76 22 851 02 E 22.. .50.. 851 02 E 22.. .50.. 34.95 14.35 2.15 33.04 31.75 39.99 10.69 3.13 23.80 7.76 24 851 02 E 24.. .50.. 851 02 E 24.. .50.. 38.12 15.20 2.15 36.24 34.92 43.15 10.69 3.81 23.80 7.76 PS PS PS PS PS PS PS PS PS 16 40 16 40 16 40 16 40 16 40 16 40 16 40 16 40 16 40 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A Note : toutes les dimensions sont en mm / all dimensions are in mm 41 851 Perçage cloison Panel cut-out Taille de boîtier Shell size A±0.1 B±0.1 C±0.1 E±0.15 J±0.15 N P±0.1 X min max min 8 15.55 14.60 14.70 15.10 3.15 1.57 3.17 13.75 2.90 10 18.80 17.75 17.50 18.26 3.15 1.57 3.17 16.95 2.90 12 22.15 22.50 20.20 20.62 3.15 1.57 3.17 21.50 2.90 14 25.30 25.70 23.40 23.00 3.15 1.57 3.17 24.20 2.90 16 28.45 28.85 26.60 24.60 3.15 1.57 3.17 27.35 2.90 18 31.65 32.05 29.80 26.97 3.15 1.57 3.17 30.55 2.90 20 34.80 35.20 32.10 29.36 3.15 1.57 6.35 33.70 5.50 22 38.00 38.40 35.30 31.75 3.15 1.57 6.35 36.90 5.50 24 41.20 41.55 38.40 34.92 3.73 1.57 6.35 40.05 5.50 Embase à fixation par écrou type 07A Jam nut receptacle type 07A PS PS PS PS PS PS PS PS PS Version pour connexions enroulées (WW) Wire-wrap version Version à picots droits PC tail version Taille de boîtier Shell size Références / Part numbers A B max C max F max H +1.63 0 L max P max S max T +1.25 0 version WW WW version version à picots PC tail version 8 851 07 A 8.. .50.. 851 07 A 8.. .50.. 12.03 17.90 2.64 26.94 12.42 20.64 19.29 23.94 9.46 10 851 07 A 10.. .50.. 851 07 A 10.. .50.. 15.01 17.90 2.64 30.14 12.42 20.64 22.38 26.95 9.46 12 851 07 A 12.. .50.. 851 07 A 12.. .50.. 19.07 17.90 2.64 34.94 12.42 20.64 27.13 31.74 9.46 14 851 07 A 14.. .50.. 851 07 A 14.. .50.. 22.25 17.90 2.64 38.04 12.42 20.64 30.33 34.94 9.46 16 851 07 A 16.. .50.. 851 07 A 16.. .50.. 25.42 17.90 2.64 41.26 12.42 20.64 33.48 38.24 9.46 18 851 07 A 18.. .50.. 851 07 A 18.. .50.. 28.60 17.90 2.64 44.44 12.42 20.64 36.68 41.34 9.46 20 851 07 A 20.. .50.. 851 07 A 20.. .50.. 31.77 22.45 3.44 49.14 8.64 25.99 39.83 46.04 8.49 22 851 07 A 22.. .50.. 851 07 A 22.. .50.. 34.95 22.45 3.44 52.24 8.64 25.99 43.03 49.24 8.49 24 851 07 A 24.. .50.. 851 07 A 24.. .50.. 38.12 23.30 3.44 55.54 7.79 26.84 46.18 52.74 7.79 PS PS PS PS PS PS PS PS PS 16 40 16 40 16 40 16 40 16 40 16 40 16 40 16 40 16 40 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A 34 34A Embase à collerette carrée Square flange receptacle Embase à fixation par écrou Jam nut receptacle Embase à collerette ronde Solder fixing receptacle Note : toutes les dimensions sont en mm / all dimensions are in mm 42 851 Embase de repos Dummy receptacle Accessoires / Accessories Taille de boîtier Shell size Références Part numbers A C max E J M max N max 8 8500-18 12.03 20.99 15.09 3.13 11.70 1.32 10 8500-19 15.01 24.19 18.26 3.13 11.70 1.32 12 8500-20 19.07 26.54 20.62 3.13 11.70 1.32 14 8500-21 22.25 28.89 23.00 3.13 11.70 1.32 16 8500-26 25.42 31.29 24.61 3.13 11.70 1.32 18 8500-22 28.60 33.69 26.97 3.13 11.70 1.32 20 8500-23 31.77 36.89 29.36 3.13 14.35 2.15 22 8500-24 34.95 39.99 31.75 3.13 14.35 2.15 24 8500-25 38.12 43.15 34.92 3.81 15.20 2.15 Bouchons de protection plastique pour embase & fiche Plastic protective caps for receptacle and plug Taille de boîtier Shell size Bouchons pour embase Caps for receptacles Bouchons pour fiches Caps for plugs 8 8500-5585 A 8500-5594 10 8500-5586 A 8500-5595 12 8500-5587 A 8500-5596 14 8500-5588 A 8500-5597 16 8500-5589 A 8500-5598 18 8500-5590 A 8500-5599 20 8500-5591 A 8500-5600 22 8500-5592 A 8500-5601 24 8500-5593 A 8500-5602 Joint de cloison Gaskets Taille de boîtier Shell size Joints pour embase à collerette carrée / Gaskets for square flange receptacle Joints pour embase à fixation par écrou / Gaskets for jam nut receptacle néoprène fairprène néoprène vitton 8 8500-275 8500-4164 3330102 3330675 10 8500-276 8500-4165 3330103 3330670 12 8500-277 8500-4166 3330104 3330671 14 8500-278 8500-4167 3330105 3330672 16 8500-283 8500-4168 3330106 3331048 18 8500-279 8500-4169 3330107 3331049 20 8500-280 8500-4170 3330108 3331050 22 8500-281 8500-4171 3330109 3331051 24 8500-282 8500-4172 3330110 3331052 Note : toutes les dimensions sont en mm / all dimensions are in mm 43 Notes / Notes 44 851 Type de bouchon Cap type Bouchons pour embase / Receptacle cap Bouchons pour fiche / Plug cap Cadmiage vert olive Olive green cadmium Cadmium incolore White cadmium Oxydation noir Blak anodised Nickelage Nickel Cadmiage vert olive Olive green cadmium Cadmium incolore White cadmium Oxydation noir Blak anodised Nickelage Nickel Bouchon avec chaînette métallique et oeillet de fixation Cap with chain and ring D 02 D 29 D 44 D D 02 D 29 D 44 D Bouchon avec cordonnet nylon et oeillet de fixation Cap with nylon cord and ring B 02 B 29 B 44 B B 02 B 29 B 44 B Bouchon avec cordonnet nylon et rondelle de fixation (boîtier 10, 12, 14, 16 & 18) Cap with nylon cord and washer (shell 10, 12 , 14, 16 & 18) - - - - E - - - Bouchon avec cordonnet nylon et rondelle de fixation Cap with nylon cord and washer H - - 44 H - - - - Bouchon avec chaînette métallique et rondelle de fixation Cap with chain and washer J - - - - - - - Bouchon 500 H brouillard salin Cap 500hr salt spray JQ7 - - - - - - - Bouchon sans cordonnet Cap without chain M - - - M - - - Bouchons / Caps Références / Ordering Information Racine / Basic series 8500 05 - - - Type de boîtier / Shell size Référence pour embase / Part numbers for receptacle Référence pour fiche / Part numbers for plug 8 02 10 10 03 11 12 04 12 14 05 13 16 27 28 18 06 14 20 07 15 22 08 16 24 09 17 Spécifications / Specifications pour type de bouchon & protection, voir tableau ci-dessous / for cap & plating, see table below Types et protections / Type and plating Bouchons pour fiches Caps for plugs Taille de boîtier Shell size Ø A max B max C+6 0 D+2 0 E Ø F 8 16.80 19.84 132 128 - - 10 19.80 19.84 132 128 132 14.00 12 23.90 19.84 148 140 148 17.60 14 27.00 19.84 148 140 148 20.80 16 30.20 19.84 148 140 148 25.60 18 33.40 19.84 148 140 148 28.70 20 36.50 21.44 168 153 - - 22 39.80 21.44 168 153 - - 24 42.90 22.22 168 153 - - « - » nous contacter / consult us D B & M E Note : toutes les dimensions sont en mm / all dimensions are in mm 45 851 Bouchons pour embases Caps for receptacles D J & JQ7 B & M H Taille de boîtier Shell size Ø A max B max C+6 0 D+2 0 J max H+2 0 K+6 0 8 19.00 21.44 84 77 14.80 80 84 10 21.80 21.44 84 77 17.90 80 84 12 26.10 21.44 100 89 22.70 90 100 14 29.30 21.44 100 89 25.90 90 100 16 32.50 21.44 100 89 29.00 90 100 18 35.30 21.44 100 89 32.20 90 100 20 38.80 21.44 116 102 35.40 110 116 22 42.00 21.44 116 102 38.60 110 116 24 45.10 22.22 116 102 41.70 110 116 Note : toutes les dimensions sont en mm / all dimensions are in mm 46 851 Références des raccords / Backshell ordering information Pour les types de protection voir références page 11 / For plating types see part numbers page 11 24 8500-5890 LP 8500-5890 110 8500-5890 202 8500-2477 900 8500-2477 902 8500-2477 903 8500-1567 LP 8500-474 8500-690 8500-456 LP - - 8500-4029 LP 8500-4029 110 - 8500-4053 900 - - 8500-8982 900 - 8500-8982 903 851 T 24-38 851 T 24-42 8500-5881 8500-5908 LP 22 8500-5889 LP 8500-5889 110 8500-5889 202 8500-2476 900 8500-2476 902 8500-2476 903 8500-1566 LP 8500-473 8500-689 8500-3186 LP - - 8500-4028 LP 8500-4028 110 - 8500-4052 900 - - 8500-8981 900 - 8500-8981 903 851 T 22-38 851 T 22-42 8500-5880 8500-5907 LP 20 8500-5888 LP 8500-5888 110 8500-5888 202 8500-2475 900 8500-2475 902 8500-2475 903 8500-1565 LP 8500-472 8500-688 8500-3185 LP - - 8500-4027 LP 8500-4027 110 - 8500-4051 900 - - 8500-8980 900 - 8500-8980 903 851 T 20-38 851 T 20-42 8500-5879 8500-5906 LP 18 8500-5887 LP 8500-5887 110 8500-5887 202 8500-2474 900 8500-2474 902 8500-2474 903 8500-1564 LP 8500-471 8500-687 8500-453 LP - - 8500-4026 LP 8500-4026 110 - 8500-4050 900 - - 8500-8979 900 - 8500-8979 903 851 T 18-38 851 T 18-42 8500-5878 8500-5905 LP 16 8500-5886 LP 8500-5886 110 8500-5886 202 8500-2473 900 8500-2473 902 8500-2473 903 8500-1563 LP 8500-470 8500-686 8500-452 LP - - 8500-4025 LP 8500-4025 110 - 8500-4049 900 - - 8501-0190 900 - 8501-0190 903 851 T 16-38 851 T 16-42 8500-5877 8500-5904 LP 14 8500-5885 LP 8500-5885 110 8500-5885 202 8500-2472 900 8500-2472 902 8500-2472 903 8500-1562 LP 8500-469 8500-685 8500-451 LP - - 8500-4024 LP 8500-4024 110 - 8500-4048 900 - - 8500-8978 900 - 8500-8978 903 851 T 14-38 851 T 14-42 8500-5876 8500-5903 LP 12 8500-5884 LP 8500-5884 110 8500-5884 202 8500-2471 900 8500-2471 902 8500-2471 903 8500-1561 LP 8500-468 8500-684 8500-450 LP - - 8500-4023 LP 8500-4023 110 - 8500-4047 900 - - 8501-0189 900 - 8501-0189 903 851 T 12-38 851 T 12-42 8500-5875 8500-5902 LP 10 8500-5883 LP 8500-5883 110 8500-5883 202 8500-2470 900 8500-2470 902 8500-2470 903 8500-1560 LP 8500-467 8500-683 8500-449 LP - - 8500-4022 LP 8500-4022 110 - 8500-4046 900 - - 8500-8977 900 - 8500-8977 903 851 T 10-38 851 T 10-42 8500-5874 8500-5901 LP 8 8500-5882 LP 8500-5882 110 8500-5882 202 8500-2469 900 8500-2469 902 8500-2469 903 8500-1559 LP 8500-466 8500-682 8500-448 LP - - 8500-4021 LP 8500-4021 110 - 8500-4045 900 - - 8501-0188 900 - 8501-0188 903 851 T 08-38 851 T 08-42 8500-5873 8500-5900 LP taille de boîtier shell size protection plating - 29 ou/or 031 44 - 29 ou/or 031 44 - - - 29 ou/or 031 44 - 29 ou/or 031 44 - 29 ou/or 031 44 - 29 ou/or 031 44 38 42 - E/R /RC écrou nut P/RP P RP A/RA T/RT M/RM G/RG T/RT specification 38 & 42 presseétoupe sealing gland écrou nut désignation designation raccord simple backnut raccord droit à serre-câbles straight cable clamp raccord droit pour potting straight backshell for potting raccord droit intermédiaire straight adaptor raccord droit pour gaine thermorétractable straight backshell for heatshrink sleeving raccord droit démontable pour gaine thermorétractable removable straight backshell for heatshrink sleeving raccord droit démontable pour reprise de tresse et gaine thermorétractable removable straight backshell for screen termination and heatshrink sleeving raccord droit démontable pour reprise de tresse et gaine thermorétractable removable straight backshell for screen termination and heatshrink sleeving J raccord droit à presse-étoupe straight sealing gland backshell EC AC Raccords droits / Straight backshells Potting 47 851 Références des raccords / Backshell ordering information Pour les types de protection voir références page 11 / For plating types see part numbers page 11 Raccords droits / Straight backshells 24 8500-5881 8500-5997 900 - - - 8500-8191A LP - - 22 8500-5880 8500-5996 900 - - - 8500-8190 LP - - 20 8500-5879 8500-5995 900 - - - 8500-8189 LP - - 18 8500-5878 8500-5994 900 - - - 8500-8188 LP - - 16 8500-5877 8500-5993 900 8500-8476 900 - - 8500-8187 LP - - 14 8500-5876 8500-5992 900 8500-8475 900 - - 8500-8186 LP - - 12 8500-5875 8500-5991 900 8500-8474 900 - - 8500-8185 LP - - 10 8500-5874 8500-5990 900 - - - - - - 8 8500-5873 8500-5989 900 - - - - - - taille de boîtier shell size protection plating - 29 ou/or 031 44 - 29 ou/or 031 44 presseétoupe sealing gland écrou nut U/RU Z/RZ désignation designation JC raccord droit court pour reprise de tresse et gaine thermorétractable short backshell for screen termination and heatshrink sleeving raccord pour adaptation d’accessoire au pas électrique straight adaptor for electrical pitch access raccord droit à presse-étoupe et serrecâbles straight sealing gland and cable clamp backshell Raccords droits pour embase 07 / Straight backshells for receptacle 07 8500-381 LP 8500-381 110 8500-381 202 8500-1797 900 - - 8500-474 8500-690 8500-4784 LP 8500-4784 110 - 8500-380 LP 8500-380 110 8500-380 202 8500-1796 900 - - 8500-473 8500-689 8500-4783 LP 8500-4783 110 - 8500-379 LP 8500-379 110 8500-379 202 8500-1795 900 - - 8500-472 8500-688 8500-4782 LP 8500-4782 110 - 8500-378 LP 8500-378 110 8500-378 202 8500-1794 900 - - 8500-471 8500-687 8500-4781 LP 8500-4781 110 - 8500-377 LP 8500-377 110 8500-377 202 8500-1793 900 - - 8500-470 8500-686 8500-4780 LP 8500-4780 110 - 8500-376 LP 8500-376 110 8500-376 202 8500-1792 900 - - 8500-469 8500-685 8500-4779 LP 8500-4779 110 - 8500-375 LP 8500-375 110 8500-375 202 8500-1791 900 - - 8500-468 8500-684 8500-4778 LP 8500-4778 110 - 8500-374 LP 8500-374 110 8500-374 202 8500-1790 900 - - 8500-467 8500-683 8500-4777 LP 8500-4777 110 - 8500-8347 LP 8500-8347 110 8500-8347 202 8500-8351 900 - - 8500-466 8500-682 8500-4776 LP 8500-4776 110 - - 29 ou/or 031 44 - 29 ou/or 031 44 - 29 ou/or 031 44 E/R /RC P RP T/RT raccord simple backnut raccord droit à serre-câbles straight cable clamp raccord droit pour potting straight backshell for potting raccord droit pour gaine thermorétractable straight backshell for heatshrink sleeving EC AC Raccords coudés / Elbow backshells 8500-799 900 8500-799 902 - 8500-3225 900 8500-3225 902 - 8500-3224 900 8500-3224 902 - 8500-796 900 8500-796 902 - 8500-795 900 8500-795 902 - 8500-794 900 8500-794 902 - 8500-793 900 8500-793 902 - 8500-792 900 8500-792 902 - 8500-791 900 8500-791 902 - - 29 ou/or 031 44 EC/RC raccord coudé à serre-câbles elbow cable clamp backshell 48 851 Outillages / Tools Outillage de sertissage Crimping pliers Tailles de contacts Contact sizes Section de câbles / Wire sizes Références / Part numbers mm² AWG pince à sertir / crimping tool positionneur / locator 20 0.93 0.60 0.38 0.21 18 20 22 24 8476-01 (M 22520/2-01) 8365 (M 22520/1-01) 8476-02 (M 22520/2-02) 8365-02 (M 22520/1-02) 16 1.91 1.34 0.93 14 16 18 8365 (M 22520/1-01) 8365-02 (M 22520/1-02) ] ] Outillage d’insertion et d’extraction Insertion and extraction tools Type de contacts Contact types Tailles de contacts Contact sizes Références / Part numbers outil d’insertion / insertion tools outil d’extraction / extraction tools à sertir crimp 20 8500-29B* 8500-36A 16 8500-39 8500-38A pour connexion enroulée for wire-wrap 20 8500-31 8500-31 16 8500-39 ou/or 8500-37 8500-37 Tube de rechange pour outil / Square tube for tool : • 8500-36A : ref. 8500-1163 • 8500-38A : ref. 8500-1486 021 * Sauf arrangements 8-2, 8-3, 8-4, 12-14 : outil 8500-93B * Except 8-2, 8-3, 8-4, 12-14 contact layouts : insertion tool 8500-93B Obturateurs Filler plugs Tailles de contacts Contact sizes Références / part numbers Couleur / Colour Profil / Profile 20 8500-4144 gris / grey 16 8500-479 bleu / blue 20 8500-4144 A (MS 3187 A 20) rouge / red 16 8500-4267 (MS 3187-16) bleu / blue 49 851 Outils de sertissage Crimping pliers 8476-01 (M 22520/2-01) avec / with 8476-02 (M 22520/2-02) 8365 (M 22520/1-01) avec / with 8365-02 (M 22520/1-02) Outils de d’insertion Insertion tools 8500-39 8500-29B 50 851 Outils d’extraction Extraction tools 8500-36 A (Contact à sertir #20 / Crimp contact #20) 8500-38 A (Contact à sertir #16 / Crimp contact #16) 8500-31 (pour connexion enroulée #20 / for wire-wrap #20) 8500-37 (pour connexion enroulée #16 / for wire-wrap #16) Accessoires Accessories 8498-04 Clé à sangle pour serrage des accessoires arrière Strap backshell tightening spanner 8500-30 Support de serrage Tightening support 51 851 Notice de câblage / Wiring instructions Préparation des câbles / cable preparation Contacts à sertir Crimp contacts Dénudage Stripping • Apporter le plus grand soin à cette opération. Utiliser une pince à dénuder appropriée à la section du câble et en parfait état. • Afin de conserver toutes les caractéristiques d’étanchéité du connecteur et permettre un câblage rationnel, les fils doivent avoir les dimensions ci-dessous : • Taux de remplissage conseillé : - 050 % Ø maxi - 050 % Ø mini - 100 % Ø moyen • Contacts de taille 20 pour les câbles de : - Ø sur gaine ≤ à 2 mm, dénuder sur une longueur de 4,5 mm - Ø sur gaine > à 2 mm, dénuder sur une longueur de 7 mm. • Contacts de taille 16, dénuder le câble sur 6 mm. Raccordement câblescontacts • Enfiler le câble dans le fût du contact et s’assurer que les brins du câble sont apparents dans le trou de visite. Utilisation de l’embout réducteur • Contacts de taille 20, si le câble a une section inférieure à 0,21 mm2, il est indispensable d’intercaler un embout réducteur : réf. 8500-781. • Contacts de taille 16, embout réducteur : réf. 8500-1985, si le câble a une section égale à 0,60 mm2. contact / contact embout / sleeve câble / cable • This operation should be carried out with great care. Use stripping pliers which are in good condition and which are designed for use with the size of wire being stripped. • In order to maintain the connector’s excellent sealing characteristics and, at the same time, meet the highest cabling standards the wires should have the following external sheath dimensions : • Recommended loading : - 050 % with max. diam. wires - 050 % with min. diam. wires - 100 % with medium size wires. • Size 20 contacts for cables : - when Ø over insulation ≤ 2 mm strip to a 4.5 mm length - when Ø over insulation > 2 mm strip to a 7‑mm length. • Size 16 contacts, strip the cable to a length of 6 mm. Cable-contact assembly • Insert the wire into the crimp barrel and ensure that it has penetrated correctly by checking that it may be seen through the lateral hole in the barrel. Reducing sleeve • If a wire with a cross sectional area of less than 0.21 mm2 is used with a size 20 contact, it will be necessary to use a reducing sleeve : ref. 8500-781. • Wires of cross sectional area of 0.6 mm2 may be used with size 16 contacts by using a reducing sleeve, ref. 8500-1985. Taille des contacts Ø sur gaine min. max. 20 16 1.20 1.60 2.11 2.80 Contacts size Ø over sheath min. max. 20 16 1.20 1.60 2.11 2.80 52 851 Sertissage des contacts / Contact crimping • Avec pince à sertir MS 22520/1-01 référence Souriau 8365 et tourelle MS 22520/1-02 8365-02: - position «rouge» pour contact taille 20 - position «bleue» pour contact taille 16. • Avec pince à sertir MS 22520/2-01 référence Souriau 8476-01 et positionneur MS 22520/2-02 8476- 02 : - contact taille 20 uniquement. Nota : ne pas utiliser avec embout réducteur. Les pinces doivent être utilisées côté poinçons. • Presser sur les poignées de la pince jusqu’au déclic final, relâcher ; la pince doit s’ouvrir d’elle-même. • Introduire l’ensemble fil et contact, ou fil embout réducteur et contact entre les 4 poinçons jusqu’à venir en butée dans le positionneur. • Presser à fond jusqu’au déclic final, la pince doit s’ouvrir une fois le sertissage effectué. • Extraire fil et contact serti et contrôler l’aspect du sertissage. • With crimping pliers MS 22520/1-01 Souriau part number 8365 and turret MS 22520/1-02 8365-02 : - «red» position for size 20 contacts - «blue» position for size 16 contacts. • With crimping pliers MS 22520/2-01 Souriau part number 8476-01 and locator MS 22520/2-02 8476-02 : - for size 20 contacts only. Note : not be used with reducing sleeve. Squeeze pliers firmly until a click is heard, the pliers should spring open when the ratched mechanism is released. • Hold indentor side up-insert the wire-contact assembly or mire-reducing sleeve-contact assembly between the four indentors, ensuring that the contact bottoms in the locator. • Fully close the jaws, once the contact is crimped the pliers must spring open remove wire + crimped contact, check crimp aspect. 8365 8476-01 53 851 Insertion des contacts / Crimp contact insertion Avant les opérations suivantes, démonter et enfiler sur les câbles l’accessoire arrière du connecteur. Outils d’insertion • Contacts taille 20* : pince 8500-29B • Contacts taille 16 : outil 8500-39. Utilisation des outils d’insertion Engager manuellement le contact dans l’alvéole de l’isolant. • Contacts de taille 20 : prendre le fil entre les 2 becs de la pince en butée sur l’arrière de la jupe du contact. • Contacts de taille 16 : mettre la partie sertie du contact dans le bec de l’outil, l’extrémité de celui-ci venant en butée sur la collerette principale du contact. Introduire chaque contact dans le logement de l’isolant en poussant dans l’axe jusqu’à l’accrochage du contact dans le clip. Obturateurs Lorsque certains contacts ne sont pas câblés, afin de conserver les caractéristiques d’étanchéité, il est indispensable de prévoir un obturateur à l’arrière du contact : le contact doit être monté dans son alvéole avant l’obturateur. * Sauf arrangements 8-2, 8-3, 8-4, 12-14 : outil 8500-93B First disassemble and slide connector rear accessory over cables. Insertion tools • Size 20 contacts* : pliers 8500-29B • Size 16 contacts : tool 8500-39. Use of insertion tools Manually insert the contact into the desired insert cavity. • Size 20 contacts : insert the wire between the pliers jaws, the tip of the jaws butting the contact shoulder. • Size 16 contacts : introduce the contact crimped section in the tool jaws, the tip of the tool butting against the contact main flange. Introduce contacts one by one in insert cavities pushing straight in until the contact snaps into position and the clip ensures contact retention. Filler plugs Where certain contacts are unwired and where it is necessary to fully maintain the connector’s sealing characteristics, a filler plug must be used. Note that the contact must be inserted before the filler plug. * Except 8-2, 8-3, 8-4, 12-14 contact layouts : tool 8500-93B contact / contact fil / wire outil / tool Mise en place du contact dans l’outil Contact position in the tool sens du montage direction of filler plug insertion 54 851 Extraction des contacts à sertir / Crimp contact extraction Outils d’extraction Tous les contacts pour isolants à clips sont démontables à l’aide d’un outil semi-automatique : • contacts taille 20 : outil référence 8500-36A • contacts taille 16 : outil référence 8500-38A. Avant les opérations suivantes, démonter et faire glisser sur les câbles l’accessoire arrière du conducteur. • Ne pas agir sur le poussoir de l’outil. • Introduire par l’avant du connecteur (côté accouplement) le tube de l’outil sur le contact mâle ou femelle jusqu’au 1er repère pour les contacts mâles et au 2ème repère pour les contacts femelles. • Cette opération doit être effectuée délicatement, dans l’axe du contact à l’aide d’un léger mouvement rotatif. • Extraire le contact en actionnant le poussoir, retirer l’outil avec précaution et tirer sur le fil pour dégager l’ensemble fil-contact. Nota : les outils possèdent un système à ressort réglable (par le bouton moleté arrière), permettant ainsi le décrochage automatique du contact. Extraction tools All contacts for use in insulators with clips are extracted using a semi-automatic tool : • size 20 contacts : tool type 8500-36A • size 16 contacts : tool type 8500-38A. First dissassemble and slide connector rear accessory over cables. • Do not operate the tool slide button. • Bring the tool tip over the male or female contact to be removed from connector front (mating face) as far as the first mark for male contacts and the second mark for female contacts. • This operation, should be carried out delicately in a direction parallel to the contact centre line with a light turning action. • Extract contact pushing the slide button fully forward, carefully remove tool and pull wire to release the wire-contact assembly. Note : tools have an adjustable spring system (rear knurled knob) also for automatic contact disengagement. 1er repère first mark 2ème repère second mark 55 851 Schémas d’implantations pour circuits imprimés / Co-ordinates for PC tail contacts Isolant mâle, vue face arrière (côté soudure) Terminations viewed from male rear face (soldering side) Ø trous de perçage 0,90 mm min. (# 20) + trous de perçage 1,3 mm min. (# 16) tolérance de positionnement des trous sur carte Hole size : 0.90 mm min. (# 20) + Hole sizes : 1.3 mm min. (# 16) hole position tolerance. O Ø 0.10 14-5 12-3 12-8 12-10 14-12 14-15 14-18 10-6 10-7 10-98 12-2 8-2 8-4 8-3 8-3A/8-98 8-33 12-14 56 851 16-8 16-23 16-26 18-11 14-19 18-30 18-32 57 851 20-16 20-24 20-25 20-27 20-39 20-41 58 851 22-21 22-32 22-34 22-36 22-55 59 851 24-61 60 851 Prise largable push-pull / Push-pull locking plug Caractéristiques générales • Verrouillage : en poussant sur la bague • Déverrouillage : par traction sur la tirette de largage • Montage : sur toutes les embases 851 • Arrangements et contacts à sertir et à souder : (voir pages 10 et 14/15) • Autres caractéristiques : (voir page 9) Racine / Basic series version à sertir - crimp version 856 version à souder - solder version 856 06 06 R E • • • • • • • • P P • • 50 50 • • • • Type de boîtier / Shell type 06 08 Type de raccord / Backshell type R/E RC/EC RA/A RP/P RT/T RM/M *RT/*T RC/EC Taille de boîtier / Shell size 8 - 10 - 12 - 14 - 16 - 18 - 20 - 22 - 24 Arrangements / Contact layouts Voir tableau des arrangements page 14/15 - See table page 14/15 Type de contact/ Contact type P = mâle / male - S = femelle / female Positionnement / Orientation Normal (n’apparaît pas dans la référence) w, x, y, z - voir tableau page 16 Normal (not included in part number) w, x, y, z - see table page 16 Indice obligatoire / Obligatory suffix Spécification / Specification 07 08 09 General characteristics • Locking : by pushing on the coupling nut • Unlocking : by pulling a lanyard • Mounted : on all 851 receptacles • Layouts and crimp solder contacts : (see pages 10 and 14/15) • Other characteristics : (see page 9) Références / Ordering information fiche droite - plug for use with straight backshell fiche coudée - plug for use with 90° backshell raccord simple / backnut raccord droit à serre-câbles / straight cable clamp raccord droit intermédiaire / straight adaptor raccord droit pour potting / straight backshell for potting raccord droit pour gaine thermorétractable / straight backshell for heatshrink sleeving raccord droit démontable pour gaine thermorétractable straight removable backshell for heatshrink sleeving spécification 38 ou/or 42: raccord droit démontable pour reprise de tresse et gaine thermorétractable / straight removable backshell for screen termination and heatshrink sleeving raccord coudé à serre-câbles / 90° cable clamp protection cadmié vert olive (version à souder) olive-green cadmium plating (solder version) protection cadmié vert olive (version à sertir) olive green cadmium plating (crimp version) protection cadmié blanc (version à sertir et à souder) white cadmium plating (crimp and solder version) 61 851 Taille de boîtier Shell size Dimensions 8 10 12 14 16 18 20 22 24 A 19.50 22.80 27.30 30.80 34.00 37.00 41.00 44.50 49.20 B 24.95 28.25 32.55 36.05 39.05 42.05 45.80 49.20 53.45 06 R E 32.00 32.00 32.00 32.00 32.00 32.00 31.80 31.80 31.80 06 RC E 47.30 47.30 47.30 47.30 50.50 50.50 49.90 49.90 49.90 06 RP E 42.10 42.10 42.10 42.10 42.10 45.40 49.80 49.80 49.80 06 RA E 41.00 41.00 41.00 41.00 41.00 41.00 43.00 43.00 43.20 06 RM E 50.00 50.00 50.00 50.00 50.00 50.00 51.70 51.70 51.70 06 RT spécifications 38 ou/or 42 E 50.00 50.00 50.00 50.00 50.00 50.00 51.70 51.70 51.70 08RC E 50.10 52.60 54.90 58.50 60.80 65.00 68.80 71.20 76.20 D max 16.00 18.00 19.50 22.00 23.50 25.00 26.50 28.00 31.00 Nota : Encombrements des raccords, se reporter aux dimensions des pages précédentes Note : For backshells dimensioning, refer to values given in preceding pages Note : toutes les dimensions sont en mm / all dimensions are in mm 62 851 Connecteurs filtres 8F51 / 8F51 filter connectors Généralités Ces connecteurs sont dérivés des spécifications standards MIL-DTL-26482 G série 1 - NFC 93422 (HE 301 B) - VG 95328. Ils sont interchangeables en fixation et intermariables avec les connecteurs standards. Différents types de filtres peuvent équiper ces connecteurs et permettent ainsi de supprimer les interférences RFI/EMI dans différentes gammes de fréquences. L’utilisation de ces connecteurs à filtres performants incorporés offre les avantages suivants : • Filtrage efficace des parasites à l’entrée ou à la sortie d’un équipement électronique, • Ecran de blindage du coffret conservé, • Encombrement et coût plus réduit par rapport à l’utilisation de filtres individuels câblés à l’arrière du connecteur, • Choix de 4 types de contacts standards - merci de nous consulter pour tout autre valeur de capacitance et type de filtre, • Possibilité de mixage de filtres dans le même arrangement : contacts filtrés, non filtrés et liés à la masse. La version adaptateur, également disponible, permet d’équiper simplement les systèmes existants non filtrés. Caractéristiques électriques • Intensité max. par contact 7.5 A (#20); 13 A (#16) • Tension max. de service 200 Vdc / 120 Vac • Types de filtre standard C, Pi • Valeur de capacitance typ. de 500 pF à 200 nF • Performance filtre Jusqu’à -60dB / -80dB Consulter pour ce produit notre département CONNECTEURS FILTRES. General information These connectors are derived from standard specifications MIL-DTL-26482 G series 1 - NFC 93422 (HE 301 B) - VG 95328. They are intermountable and intermateable with standard connectors. Different types of filters may be fitted in these connectors to eliminate RFI/EMI in different frequency ranges. Using built-in High Performance EMI filters offers the following advantages : • Efficient filtering on interferences at electronic equipment input or output, • Case screen-shielding efficiency is maintained, • Cost and volume saving as compared with the use of discrete filters wired down the line, • 4 types of standard filters are available - Please consult us for other capacitance and filter types, • Combinations of mixed filter in the same layout: filtered, non-filtered and grounded contacts available. An adaptor version is also a simple technique to equip existing systems which do not incorporate filters. Electrical characteristics • Max. current rating per contact 7.5 A (#20); 13 A (#16) • Max. operating voltage 200 Vdc / 120 Vac • Standard filter types C, Pi • Capacitance range typically 500 pF - 200 nF • Filter performance up to -60dB / -80dB For this product, consult our FILTER CONNECTOR department. 63 851 Connecteurs spécifiques et accessoires de connexion SNC SNC specific connectors and connection accessories Désignations Designations Références Part numbers • Traversée de cloison à collerette carrée, broches, douilles Boîtiers 8 à 24 : arrangements 8.03 / 10.06 / 12.10 / 14.19 / 16.26 / 18.32 / 20.41 / 22.55 / 24.61 Positionnements : N & W Protections : 085 cadmiage vert / 112 oxydation anodique noire brillante • Square flange through bulkhead, pins, sockets Shell sizes 8 to 24 : layouts 8.03 / 10.06 / 12.10 / 14.19 / 16.26 / 18.32 / 20.41 / 22.55 / 24.61 Insert rotations : N & W Plating : 085 green cadmium / 112 black anodized EC 52 B • Raccord coudé à serre-câbles à encombrement réduit, pour fiche 08RC Boîtiers 12, 14, 16, 18 et 22 • Short profile 90° backshell with cable clamp for 08 RC plug Shell sizes 12, 14, 16, 18 and 22 SN 556 • Connecteur fiche et embase Boîtier 24 équipé de 3 contacts # 16 - 7 contacts # 20 - 1 contact coaxial 50 Ω (pour câble KX 15) • Plug and receptacle connector Shell size 24 : contact layout = 3 contacts # 16, 7 contacts # 20, 1 coaxial contact 50 Ω (for KX15 cable) SN 775 P SN 775 S • Fiche shunt • Shunt plug SN 901 • Raccord droit en deux parties avec presse-étoupe et brides de serrage Boîtiers 8, 10 et 16 • Straight two-piece backshell with sealing gland and cable strap Shell sizes 8, 10 and 16 SN 946 • Fiche équipée d’une bague de verrouillage à oreilles Boîtiers 20, 22 et 24 • Plug with flanged coupling nut Shell sizes 20, 22 and 24 SN 1167 • Prolongateur de test, broches, douilles Boîtiers 8 à 24, arrangements avec contacts de # 20 • Cable connecting test connector, pins, sockets Shell sizes 8 to 24, arrangements with size contacts # 20 SN 1206 • Bague à oreilles avec vis pointeau adaptable sur fiche 851 Boîtiers 8 à 24 • Ring with lugs with cone-pointed grub screws fitting 851 plug Shell sizes 8 to 24 SN 1277 • Raccord coudé fermé avec cheminée pour reprise de tresse par magnétostriction Boîtiers 8 à 24 • Elbow backshell with closing sleeve for shield termination by magnaforming Shell sizes 8 to 24 SN 1533 • Embase type 07A à picots droits, démontage par l’avant Arrangements : 14.19 (N) / 16.26 (N) / 18.32 (N, X) / 20.41 (N, W, X, Y) / 22.55 (N, W, X, Y, Z) / 24.61 (N) Protection : cadmiage passivé vert • Jam nut receptacle with front release straight PC tails Layouts : 14.19 (N) / 16.26 (N) / 18.32 (N, X) / 20.41 (N, W, X, Y) / 22.55 (N, W, X, Y, Z) / 24.61 (N) Plating : passivated green cadmium SN 0378 Autres arrangements, nous consulter / Other layouts, please consult us 64 Notes / Notes 65 851 RJ45 Présentation / Presentation Le connecteur SOURIAU 851 RJ45 est une solution renforcée pour les applications de téléchargement / chargement de données en environnements sévères. Disponible en taille 18, ce connecteur existe en divers types de boîtiers et avec différentes terminaisons: Fiche avec cordon RJ45, traversée de cloison ou à souder pour les embases à collerette carrée et à fixation par écrou. Les principaux avantages de ce produit : • Une solution Ethernet cat5e - 10 Base T, 100 Base TX, ou 1000 Base T • Excellente résistance aux impacts & aux chocs - Boîtier renforcé • Connexion facile, fiable & sécurisée • Idéal pour les applications intérieures / extérieures - niveau d’étanchéité IP67 SOURIAU 851 RJ45 connector is a ruggedized solution for downloading / uploading data applications in harsh environments. Available in shell size 18, this connector offers multiple configurations and terminations: Cable pig tail for plug, feed through and solder out for both square flange and jam nut receptacle. Main advantages of this product : • A cat5e Ethernet solution - 10 Base T, 100 Base TX, or 1000 Base T capable • High impact & shock resistance - Ruggedized housing • Easy, reliable & secure mating • Suitable for Indoor / Outdoor applications - IP67 sealing level 66 851 RJ45 Mécaniques Matières • Boîtier Alliage d’aluminium • Insert Thermoplastique • Contacts Alliage cuivre Protection • Boîtier Cadmié vert olive Oxydation anodique noire Nickelé • Contacts Or Mécanique • Selon MIL-DTL-26482, 500 manoeuvres Mechanical Material • Shell Aluminium alloy • Insert Thermoplastic • Contacts Copper alloy Plating • Shell Olive drab cadmium Black anodized Nickel • Contacts Gold Mechanical • per MIL-DTL-26482, 500 mating cycles Electriques 10 BaseT, 100 Base TX et 1000 BaseT Cat 5e selon TIA/EIA 568A/B Electrical 10 BaseT, 100 Base TX and 1000 BaseT Cat 5e per TIA/EIA 568A/B Climatiques • Etanchéité IP67 avec un bouchon • Température -40°C à +85°C • Résistance aux fluides : selon MIL-DTL-26482 avec un bouchon Climatic • Sealing IP67 with protective cap • Temperature -40°C to +85°C • Fluid resistance : per MIL-DTL-26482 with protective cap Caractéristiques techniques / Technical characteristics Références / Ordering information Racine / Basic series 851 Ruggedized Receptacle connectors 00 00 8 J C S N OD - - - Type de boîtier / Shell type 00 01 07 06 Type de raccord / Backshell type 00 RC RT Taille de boîtier / Shell size 8 Insert / Insert J Arrangements / Layouts F S CP Style de contact / Contact style SP Orientation / Polarization N Normal W, X, Y, Z autre orientations / other polarizations Protection / Plating OD 031 44 Spécification / Specification Nous consulter pour une configuration personnalisée / Consult factory for custom configuration Embase à collerette carrée (acceptant un raccord) Square flange receptacle (accepting backshell) Prolongateur / Cable connecting receptacle Embase à fixation par écrou / Jam nut receptacle Fiche (acceptant un raccord) / Plug (accepting backshell) Pas de raccord / no backshell Serre câbles droit / Straight cable clamp Raccord droit pour gaine thermorétractable / Straight backshell for heat shrink tubing RJ45 (size 18) RJ45 Traversée de cloison / Feedthrough A souder / Solder Embase avec cordon RJ45 / Pig tail receptacle Fiche avec cordon RJ45 / Pig tail plug Embase / Receptacle Fiche / Plug Protection vert olive cadmiée / Olive drab cadmium Oxydation anodique noire / Black anodized Nickelé / Nicke 67 851 RJ45 Embase RJ45 à collerette carrée à souder Square flange RJ45 feedthrough solder out Shell type ‘A’ ‘B’ Aluminium 22.98 1.32 Encombrements / Dimensions Embase RJ45 à collerette carrée Square flange RJ45 feedthrough Shell type ‘A’ ‘B’ Aluminium 30.91 1.32 Embase RJ45 à fixation par écrou Jam nut RJ45 feedthrough Shell type ‘A’ ‘B’ Aluminium 23.39 2.64 PIN I □ 27.0 44.1 ‘A’ ‘B’ PIN I □ 32.3 PIN I 44.1 ‘A’ ‘B’ PIN I ø 44.2 PIN I □ 27.0 10.7 ‘A’ ‘B’ 30.8 ø 1.4 □ 32.3 Note : toutes les dimensions sont en mm / all dimensions are in mm Fiche avec cordon RJ45 Cable plug RJ45 Shell type ‘A’ Aluminium 304.8 PIN I 76.0±6 ‘A’ 52.4 PIN I 25.4±6.3 Master key Livrée en standard avec un câble de dimension ‘A’ / Come with a cable - dimension ‘A’ - in standard. 68 851 RJ45 Embase à collerette carrée avec cordon RJ45 Square flange RJ45 feedthrough Pig tail Embase à fixation par écrou avec cordon RJ45 Jam nut RJ45 feedthrough Pig tail Shell type ‘A’ ‘B’ ‘C’ Aluminium 30.91 1.32 304.8±25.4 Shell type ‘A’ ‘B’ ‘C’ Aluminium 23.39 2.64 304.8±25.4 PIN I 25.4 ‘A’ ‘B’ End ‘B’ PIN I ‘C’* 25.4 End ‘A’ PIN I 25.4 ‘A’ ‘B’ End ‘B’ PIN I ‘C’* 25.4 End ‘A’ Note : toutes les dimensions sont en mm / all dimensions are in mm * Longueur du câble mesurée à partir de l’avant de la collerette / Cable length is measured from the front face of the flange. Embase RJ45 à fixation par écrou à souder Jam nut RJ45 feedthrough solder out Shell type ‘A’ ‘B’ Aluminium 15.27 2.64 PIN I 10.7 ‘A’ ‘B’ 24.6 ø 44.2 ø 1.4 Livrée en standard avec un câble de dimension ‘C’ Come with a cable - dimension ‘C’ - in standard. Livrée en standard avec un câble de dimension ‘C’ Come with a cable - dimension ‘C’ - in standard. Perçage de cloison Panel cut-out Embase à collerette carrée Square flange receptacle Embase à fixation par écrou Jam nut receptacle Epaisseur maximum du panneau : 4.75 mm Maximum panel thickness : 4.75 mm Epaisseur maximum du panneau : 0.41mm min / 3.18 mm max Maximum panel thickness : 0.41 mm min / 3.18 mm max ø 30.5 □ 27.9 4 x 2.5 Rear mounting ø 32.1 30.55 69 851 USB Présentation / Presentation Le connecteur SOURIAU 851 USB est une solution renforcée pour les applications de téléchargement / chargement de données en environnements sévères. Disponible en taille 16, ce connecteur existe en divers types de boîtiers et avec différentes terminaisons: Fiche avec cordon USB, traversée de cloison ou à souder pour les embases à collerette carrée et à fixation par écrou. Les principaux avantages de ce produit : • Excellente résistance aux impacts & aux chocs - Boîtier renforcé • Connexion facile, fiable & sécurisée • Idéal pour les applications intérieures / extérieures - niveau d’étanchéité IP67 SOURIAU 851 USB connector is a ruggedized solution for downloading / uploading data applications in harsh environments. Available in shell size 16, this connector offers multiple configurations and terminations: Cable pig tail for plug, feed through and solder out for both square flange and jam nut receptacle. Main advantages of this product : • High impact & shock resistance - Ruggedized housing • Easy, reliable & secure mating • Suitable for Indoor / Outdoor applications - IP67 sealing level 70 851 USB Mécaniques Matières • Boîtier Alliage d’aluminium • Insert Thermoplastique • Contacts Alliage cuivre Protection • Boîtier Cadmié vert olive Oxydation anodique noire Nickelé • Contacts Or Mécanique • Selon MIL-C-26484, 500 manoeuvres Mechanical Material • Shell Aluminium alloy • Insert Thermoplastic • Contacts Copper alloy Plating • Shell Olive drab cadmium Black anodized Nickel • Contacts Gold Mechanical • per MIL-C-26484, 500 mating cycles Electriques 10 BaseT, 100 Base TX Cat 5e selon TIA/EIA 568A/B Electrical 10 BaseT, 100 Base TX Cat 5e per TIA/EIA 568A/B Climatiques • Etanchéité IP67 avec bouchon • Température de -40°C à +85°C • Résistance aux fluides : selon MIL-C-26484 avec bouchon Climatic • Sealing IP67 with protective cap • Temperature range : -40°C to +85°C • Fluid resistance : per MIL-C-26484 with protective cap Caractéristiques techniques / Technical characteristics Références / Ordering information Racine / Basic series 851 Ruggedized Receptacle connectors 00 00 6 A C S N OD - - - Type de boîtier / Shell type 00 01 07 06 Type de raccord / Backshell type 00 RC RT Taille de boîtier / Shell size 6 Insert / Insert A B Arrangements / Layouts F S CP Style de contact / Contacts style SP Orientation / Polarization N Normal W, X, Y, Z autres orientations / other polarizations Protection / Plating OD 031 44 Spécification / Specification Nous consulter pour une configuration personnalisée / Consult factory for custom configuration Embase à collerette carrée (acceptant un raccord) Square flange receptacle (accepting backshell) Prolongateur / Cable connecting receptacle Embase à fixation par écrou / Jam nut receptacle Fiche (acceptant un raccord) / Plug (accepting backshell) Pas de raccord / no backshell Serre câbles droit / Straight cable clamp Raccord droit pour gaine thermorétractable / Straight backshell for heat shrink tubing USB (size 16) USB Type A USB Type B Traversée de cloison / Feedthrough A souder / Solder Embase avec cordon USB / Pig tail receptacle Fiche avec cordon USB / Pig tail plug Embase / Receptacle Fiche / Plug Protection vert olive cadmiée / Olive drab cadmium Oxydation anodique noire / Black anodized Nickelé / Nickel 71 851 USB Embase USB à collerette carrée à souder Square flange USB feedthrough solder out Shell type ‘A’ ‘B’ Aluminium 15.16 1.32 Encombrements / Dimensions Embase USB à collerette carrée Square flange USB feedthrough Shell type ‘A’ ‘B’ Aluminium 24.82 1.32 Embase USB à fixation par écrou Jam nut USB feedthrough Shell type ‘A’ ‘B’ Aluminium 17.30 2.64 PIN I □ 24.6 37.8 ‘A’ ‘B’ □ 30.9 PIN I PIN I 37.8 ‘A’ ‘B’ ø 41.0 PIN I PIN I □ 30.9 10.7 ‘A’ ‘B’ 24.5 ø 1.6 □ 24.6 Note : toutes les dimensions sont en mm / all dimensions are in mm Fiche avec cordon USB USB cable plug Shell type ‘A’ Aluminium 304.8 PIN I 12.7±6.35 ‘A’ 38.2 50.8 Master key La fiche USB standard est livrée avec un câble de dimesion ‘A’. Standard USB plug come with a cable - dimension ‘A’. 65.5 USB-A plug USB-A receptacle 72 851 USB Embase USB à fixation par écrou à souder Jam nut USB feedthrough solder out Shell type ‘A’ ‘B’ Aluminium 7.65 2.64 PIN I ø 41.0 ‘A’ ‘B’ 18.3 10.7 Embase à collerette carrée avec cordon USB Square flange USB feedthrough Pig tail Embase à fixation par écrou avec cordon USB Jam nut USB feedthrough Pig tail Shell type ‘A’ ‘B’ ‘C’ Aluminium 24.82 1.32 304.8±25.4 Shell type ‘A’ ‘B’ ‘C’ Aluminium 17.30 2.64 304.8±25.4 PIN I 25.4 ‘A’ ‘B’ PIN I ‘C’* 25.4 □ 30.9 □ 24.6 PIN I 25.4 ‘A’ ‘B’ PIN I ‘C’* 25.4 ø 41.0 Note : toutes les dimensions sont en mm / all dimensions are in mm *Longueur du câble mesurée à partir de l’avant de la collerette / Cable length is measured from the front face of the flange. Perçage de cloison Panel cut-out Embase à collerette carrée Square flange receptacle Embase à fixation par écrou Jam nut receptacle Epaisseur maximum du panneau / Maximum panel thickness : - Montage par l’avant / Front mounting: 3.20 mm - Montage par l’arrière / Rear mounting : 2.49 mm Epaisseur maximum du panneau : 3.20 mm Maximum panel thickness : 2.49 mm ø 28.45 ø 4 x 3.15 □ 24.6 Panel mounting ø 32.1 □ 30.4 Livrée en standard avec un câble de dimension ‘C’ Come with a cable - dimension ‘C’ - in standard. Livrée en standard avec un câble de dimension ‘C’ Come with a cable - dimension ‘C’ - in standard. 73 8XE Présentation / Presentation SOURIAU overmolded 851 connector utilises high impact glass filled plastic offering a great impact & shock resistance as well as an ergonomic shape of the coupling ring. Suitable backshell in same plastic material allows IP68 sealing level. • High impact & shock resistance (drop & crush resistance • Easy, reliable & secure mating • Excellent sealing performance : IP68 (120 hours under 15 m water ) /IP69K • High salt spray resistance • Enhanced cable sealing • Intermateable & interchangeable with MIL-DTL-26482 • Design flexibility Le connecteur 851 surmoulé SOURIAU est en plastique, chargé verre, haute performance offrant une excellente résistance aux impacts & chocs ainsi qu’une forme ergonomique de la bague de verrouillage. Le raccord, utilisant la même matière plastique permet d’obtenir un niveau d’étanchéité IP68. • Excellente résistance aux impacts & aux chocs (aux chutes & à l’écrasement) • Connexion facile, fiable & sécurisée • Excellentes performances d’étanchéité IP68 (120 heures sous 15 m d’eau) / IP69K • Excellente résistance au brouillard salin • Excellente étanchéité sur le câble • Intermariable & interchangeable avec les connecteurs MIL-DTL-26482 • Flexibilité de configuration 74 8XE Mécaniques • Endurance • Boîtier • Insert • Contacts • Enveloppe extérieure Plastique chargé verre haute résistance • Joint bague de verrouillage Teflon sur silicone Mechanical • Durability • Shell • Insert • Contacts • Housing • Coupling ring seal Electriques • Résistance d’isolement 5000 MΩ • Tension de tenue 2300 V • Résistance contact 3 MΩ • Intensité admissible par contact Taille16 : 13 A / Taille 20 : 7.5 A Electrical • Insulation resistance 5000 MΩ • Dielectric withstanding voltage 2300 V • Contact resistance 3 MΩ • Current rating per contact Size 16: 13 A / Size 20: 7.5 A Climatiques • Température d’utilisation -55°C à +125°C • Etanchéité Interface IP68 (jusqu’à 120 heures sous 15 mètres d’eau) • Résistance aux produits chimiques selon MIL-DTL-26482 Série 1 Climatic • Working temperature -55°C to +125°C • Sealing Interfacial IP68 (up to 120 hours under 15 meters of water) • Resistance to chemicals in accordance with MIL-DTL-26482 Series 1 Acceptance câbles • Câble Gauge 14 max. • Diamètre gaine extérieure: Toutes tailles jusqu’à 11.17 mm Cable acceptance • Primaries wire Gauge 14 max. • Outer jacket all popular sizes up to 11.17 mm 500 manoeuvres min. Alliage d’aluminium - anodisé dur Elastomer néoprène Alliage de cuivre - protection or 500 mating min. Aluminium alloy - hard anodized Neoprene elastomer Copper alloy with gold plating High impact glass filled plastic Teflon over silicone Références / Ordering information Racine / Basic series 8XE Connecteur pour environnment EXTREME / connector for EXTREME environment 06 - 16 8 P - BL V8 - - - Type de boîtier / Connector type 01 Prolongateur / Cable connecting receptacle 06 Fiche / Plug Type de contact / Contact type Pas de digit / No digit à souder / to solder R à sertir / to crimp Taille de boîtier / Shell size 10, 12, 14, 16, 20, 22 Arrangements / Layouts Voir page suivante / See next page Sexe du contact / Contact gender P Mâle / male S Femelle / female Orientations / Insert orientations Pas de digit / No digit Normal (n’apparaît pas dans lé référence) / Standard (not included in part number) W, X, Y, Z autres orientations / other orientations Couleur / Color Pas de digit / No digit Gris / Mink (standard) BL Bleu / Blue YE Jaune / Yellow RE Rouge / Red Autres couleurs disponibles / Others available Specification / Design variation V8 Boîtier renforcé en taille 16 & 20 / ruggedized shells in size 16 & 20 AA Boîtier inox renforcé en taille 16 & 20 (Ø câble 8 mm) / ruggedized stainless steel shells in size 16 & 20 (cable Ø 8 mm) Diamètre du câble / Cable diameter Personnalisation possible / Custom available Caractéristiques techniques / Technical characteristics 75 8XE 10 6 6 Ø 1 (#20) 7 7 Ø 1 (#20) 98 6 Ø 1 (#20) 12 3 3 Ø 1.6 (#16) 8 8 Ø 1 (#20) 10 10 Ø 1 (#20) 14 14 Ø 1 (#20) 2 2 Ø 1.6 (#16) 12 8 Ø 1 (#20) 4 Ø 1.6 (#16) 15 14 Ø 1 (#20) 1 Ø 1.6 (#16) 18 18 Ø 1 (#20) 19 19 Ø 1 (#20) 5 5 Ø 1.6 (#16) 16 8 8 Ø 1.6 (#16) 23 22 Ø 1 (#20) 1 Ø 1.6 (#16) 26 26 Ø 1 (#20) 16 16 Ø 1.6 (#16) 39 37 Ø 1 (#20) 2 Ø 1.6 (#1.6) 41 41 Ø 1 (#20) 24 24 Ø 1 (#20) 25 25 Ø 1 (#20) 36 36 Ø 1 (#20) 55 55 Ø 1 (#20) 32 32 Ø 1 (#20) 34 34 Ø 1 (#20) 21 21 Ø 1.6 (#16) 27 27 Ø 1 (#20) 14 20 Arrangements / Contact layouts Vue de face avant isolant mâle / Viewed from front face of male insulator 22 76 8XE Note : toutes les dimensions sont en mm / all dimensions are in mm Encombrements / Dimensions Fiche / Plug Shell sizes Ø A B C 10 24.9 51.2 104.5 12 27.9 51.2 103.7 14 33.0 57.6 110.8 16 36.2 63.9 122.2 20 43.7 108.4 197.1 22 48.8 91.4 184.1 16 specif.V8 41.9 83.4 172 20 specif. V8 47 91.4 184.2 Orientations Viewed from front face of male insulator (receptacle or plug) Shell sizes Layouts Angle in degrees W X Y Z 10 6 90 - - - 7* 90 - - - 98 90 180 240 270 12 3 - - 180 - 8 90 112 203 292 10 60 155 270 295 2 - - - - 14* 45 14 5 40 92 184 273 12 43 90 - - 15 17 110 155 234 18 15 90 180 270 19 30 165 315 - 16 8 54 152 180 331 23 158 270 - - 26 60 - 275 338 20 16 238 318 333 347 39 63 144 252 333 41 45 126 225 - 24 70 145 215 290 25 72 144 216 288 27 72 144 216 288 22 21 16 135 175 349 36 72 144 216 288 55 30 142 226 314 32 72 145 215 288 34 62 142 218 298 Normal W X Y * 10-7 & 12-14 layouts, W non standard orientation C B Ø A Z 77 851 Protection non cadmiée Cadmium free plating SOURIAU propose des connecteurs 851 avec une protection noire non cadmiée. Cette protection zinc-nickel a été développée pour répondre aux nouvelles exigences en matière de respect de l’environnement (directive Européenne 76/769 EEC). Raison : • Réduire le niveau de pollution par métaux lourds produit par le cadmium • Réduire les risques de santé engendrés par les produits cadmiés. Caractéristiques : • Mécaniques - boîtiers : aluminium - protection : zinc-nickel • Electriques - continuité électrique des boîtiers : ≤ 2,5 mΩ • Climatiques - tenue au brouillard salin : 500 heures Références : Exemples* : • Version à souder 851 00 E 8-3A P.54 protection zinc-nickel • Version à sertir 851 00 R 8-3A P.54 protection zinc-nickel * Voir système de référence - page 11 (version à souder et à sertir) - page 13 (version à picots et connexions enroulées) Cette protection est disponible pour les boîtiers de type : - 00: embase à collerette carrée avec possibilité de raccord - 02: embase à collerette carrée sans possibilité de raccord - 07: embase à fixation par écrou avec possibilité de raccord - 07A: embase à fixation par écrou sans possibilité de raccord - 01: prolongateur - 06: fiche droite sans bague de blindage - 36: fiche droite avec bague de blindage Raccords, nous consulter. SOURIAU propose a 851 connector with cadmium free plating black. This zinc-nickel plating has been introduced in accordance with European Herth and Safety requirements (European directive 76/769 EEC). Reason : • Reduction in level of heavy metal pollutants produced by cadmium. • Reduction in health associated with the corrosive by products of cadmium. Characteristics : • Mechanical - shell : aluminium alloy - plating : zinc-nickel • Electrical - shell continuity : ≤ 2.5 mΩ • Climatic - salt spray : 500 hours Part numbers : Examples* : • Solder version 851 00 E 8-3A P.54 zinc-nickel plating • Crimp version 851 00 R 8-3A P.54 zinc-nickel plating * See part numbers system - page 11 (solder and crimp version) - page 13 (straight PC tails and wire-wrap versions) This plating is available for shell type : - 00: square flange receptacle accepting backshells - 02: square flange receptacle not accepting backshells - 07: jam nut receptacle accepting backshells - 07A: jam nut receptacle not accepting backshells - 01: cable connecting receptacle - 06: plug for use without straight backshell - 36: screened plug for use with straight backshells Backshells, please consult us. 78 Notes / Notes IND851CA03ENFRW © SOURIAU - April 2009 - All information in this document presents only general particulars and shall not form part of any contract. All rights reserved to SOURIAU for changes without prior notification or public announcement. Any duplication is prohibited, unless approved in writing. www.souriau.com www.souriau-industrial.com contactindustry@souriau.com 21 UT0 Metal circular connector Description “UT0” industrial circular connectors are a range of multiway connectors available in 8 shell sizes and 8 insert arrangements all intermateable, interchangeable and intermountable with the TRIM TRIO “UTG” and “UTP industrial connector families. “UT0” is equipped with identical shells from military connectors complying to MIL-C-26482 spec. Strong and rugged built to resist every environmental and mechanical requirement for indoor and outdoor applications. Amongst several characteristics, “UT0” offers possibilities on: Shielding, High levels on sealing and salt spray. UT0 is also the perfect solution to connect cat5e Ethernet applications in combination with other signals, using the same TRIM TRIO contacts (consult factory for more info). Features and benefits (see p2) • Suitable for shielding applications • Available in 8 shell sizes and 8 insert arrangements. • Available in plug and receptacle versions for both male and female contacts. • Different insert orientations possible. • Plastic inserts with flammability rating: UL94-V0. • 2 levels of water protection: Dynamic IP67 and IP68 both versions are IP69K • 2 levels of salt spray: 48h and 96h Higher salt spray resistance (200/500h) upon request • Cat5e Ethernet compatible. Can be combined with other signals offering the advantage to use same contacts (consult factory). • UL recognition in process. • Metal bayonet ring: - Metal wave spring loaded - Locks with audible positive “click” - Assures 500 matings and unmatings • RoHS compliant Performance characteristics Operating temp: -40°C to +105°C Insulation resistance: 5000 MΩ min. Test potential: 2000 VAC Durability: 500 matings and unmatings. Vibration Per MIL-STD202 resistance: method 204 Thermal shock: Per MIL-STD202 method 207 Corrosion: Salt spray per MIL-STD 202 method 101 48h (standard version) 96h (black anodised coupling ring) Higher salt spray resistance (200/500h) upon request Shielding effectiveness: 95 dB at 1 Mhz Degree of water protection per DIN 40050: Dynamic IP67 / IP68 / IP69K in mated condition and in combination with sealed back shell. How to order H or H6 – – – – H –– PS 12 12 14 14 06 UT0 UT0 Body variation: 0 : Wall mounting receptacle 6 : Cable plug 7 : Jam nut receptacle for rear panel mounting Shell size: Insert arrangement: Type of contacts: P : Pin contacts S : Socket contacts Insert polarisation: No letter : Standard version W, X, Y, Z: Different orientations (consult factory) Application: H : Standard version, water protected IP 67 & IP 69K H6 : Water protected IP 68 & IP 69K (only needed for wall mounting & jam nut receptacles) Design variation: No letter : Standard version Others : Special versions Plating: No letter : Standard is nickel plating (48h salt spray) 01: Black anodised jam nut (96h salt spray) 02: Black anodised coupling ring (96h salt spray) new Construction Shells: Zinc alloy Backshells and cable glands: Brass Coupling ring: Aluminium alloy Coupling spring: Spring stainless steel Insert: Glass-filled thermoplast UL94-V0 RoHS compliant Contact accommodation • “UT0” connectors accept TRIM TRIO size 16 crimp-type removable snap-lock contacts (see contacts section) • Contacts to be ordered seperately. Dynamic IP68 / IP69K High salt spray resistance RoHS compliant 2 New UT0 - UT0W series New UT0 – UT0W series: • The exclusive new product range in the TRIM TRIO broadline. • Aesthetic and top class performances UT0 – UT0W series major technical features & benefits For detailed information on UT0 and UT0W series offering see pages 21 to 31 • Full metal bayonet connector – Enabling 500 mating-unmating without wear out – Secure locking device: audible “click” when mating • In accordance with following standards – UT0 is Ethernet Cat5e compatible (consult factory) – UTO-UTOW ranges are upgradeable to highspeed solutions • RoHS compliant – Cadmium and lead free materials are used • High salt spray resistance* – Can be used in severe environment * Exists in 48 and 96 hours salt spray version * Higher salt spray resistance (e.g. 200 or 500 hours) upon request • Dynamic IP68* Connector will remain IP68 even when: – Pulling on the cable – Bending the cable * With appropriate back shell * Exists also in IP67 version • Dynamic IP69K* Connector withstands high pressure water cleaning. * With appropriate back shell New UT0-UT0W series 22 UT0 Cable plug for pin contacts (UT06- - - -PH) Part number Shell Ø A ±0.2 B max. Ø C ±0.15 Ø D ±0.15 E ±0.25 size UT06104PH 10 21.80 10.2 20.00 UT06128PH 12 26.10 13.4 23.60 UT061412PH 14 29.30 16.7 26.80 23.25 UT061619PH 16 32.45 33.00 19.7 30.00 UT061823PH 18 35.25 21.7 33.30 UT062028PH 20 38.80 24.9 36.55 UT062235PH 22 42.00 28.1 39.50 25.20 UT062448PH 24 45.05 31.2 42.60 Cable plug for socket contacts (UT06- - - -SH) Part number Shell Ø A ±0.2 B max. Ø C ±0.15 Ø D ±0.15 E ±0.25 size UT06104SH 10 21.80 10.2 20.00 UT06128SH 12 26.10 13.4 23.60 UT061412SH 14 29.30 33.00 16.7 26.80 23.25 UT061619SH 16 32.45 19.7 30.00 UT061823SH 18 35.25 21.7 33.30 UT062028SH 20 38.80 24.9 36.55 UT062235SH 22 42.00 27.30 28.1 39.50 25.20 UT062448SH 24 45.05 31.2 42.60 Part numbers are suitable for both IP67 and IP68 water protection For 96h salt spray version add ”02” behind “H” e.g. UT061412PH02 (only bayonet ring will be black anodised) Part numbers are suitable for both IP67 and IP68 water protection For 96h salt spray version add ”02” behind “H” e.g. UT061412SH02 (only bayonet ring will be black anodised) new E ± 0,25 E ± 0,25 Dynamic IP68 / IP69K High salt spray resistance RoHS compliant 23 UT0 Wall mounting receptacle for pin contacts (UT00----PH/PH6) Wall mounting receptacle for socket contacts (UT00----SH/SH6) Part number IP67 IP68 Shell size A max. B ± 0.3 C ± 0.2 Ø D ± 0.15 E ± 0.25 F ± 0.25 Ø G ± 0.1 Ø H ± 0.1 Ø J ± 0.1 UT00104PH UT00104PH6 10 33.23 1.6 11.35 15.0 18.3 23.8 3.2 17.3 14.2 UT00128PH UT00128PH6 12 19.0 20.6 26.2 21.8 18.4 UT001412PH UT001412PH6 14 22.2 23.0 28.6 25.0 21.5 UT001619PH UT001619PH6 16 25.3 24.6 31.0 28.1 24.6 UT001823PH UT001823PH6 18 28.5 26.9 33.3 31.3 27.8 UT002028PH UT002028PH6 20 34.75 2.4 14.55 31.7 29.4 36.5 34.5 30.9 UT002235PH UT002235PH6 22 34.9 31.8 39.7 37.7 34.1 UT002448PH UT002448PH6 24 15.35 38.0 34.9 42.9 3.9 40.9 37.3 Part numbers are suitable for both 48h and 96h salt spray. A square sealing has to be ordered separately to guarantee a sealing with equipment. Refer to “Circular accessories” section (UTFD--). Part numbers are suitable for both 48h and 96h salt spray. A square sealing has to be ordered separately to guarantee a sealing with equipment. Refer to “Circular accessories” section (UTFD--). Part number IP67 IP68 Shell size A max. B ± 0.3 C ± 0.2 Ø D ± 0.15 E ± 0.25 F ± 0.25 Ø G ± 0.1 Ø H ± 0.1 Ø J ± 0.1 UT00104SH UT00104SH6 10 25.20 1.6 11.35 15.0 18.3 23.8 3.2 17.3 14.2 UT00128SH UT00128SH6 12 19.0 20.6 26.2 21.8 18.4 UT001412SH UT001412SH6 14 22.2 23.0 28.6 25.0 21.5 UT001619SH UT001619SH6 16 25.3 24.6 31.0 28.1 24.6 UT001823SH UT001823SH6 18 28.5 26.9 33.3 31.3 27.8 UT002028SH UT002028SH6 20 29.00 2.4 14.55 31.7 29.4 36.5 34.5 30.9 UT002235SH UT002235SH6 22 34.9 31.8 39.7 37.7 34.1 UT002448SH UT002448SH6 24 15.35 38.0 34.9 42.9 3.9 40.9 37.3 new B ± 0,3 B ± 0,3 Ø G ± 0,1 Dynamic IP68 / IP69K High salt spray resistance RoHS compliant 24 UT0 Jam nut receptacle for pin contacts (UT07----PH/PH6) - suitable for rear panel mounting Jam nut receptacle for socket contacts (UT07---SH/SH6) - suitable for rear panel mounting Part number IP67 IP68 Shell size Ø A ± 0.15 B ± 0.2 D Max. F Max. G ± 0.25 H ± 0.3 K ± 0.25 L ± 0.2 Ø M ± 0.2 UT07104PH UT07104PH6 10 14.9 19.30 33.90 3.2 27.0 22.2 16.6 17.0 17.7 UT07128PH UT07128PH6 12 19.0 31.8 27.0 20.8 21.2 22.5 UT071412PH UT071412PH6 14 22.2 34.9 30.2 23.9 24.3 25.7 UT071619PH UT071619PH6 16 25.3 38.1 33.3 27.1 27.5 28.7 UT071823PH UT071823PH6 18 28.5 41.3 36.5 30.3 30.6 32.0 UT072028PH UT072028PH6 20 31.7 24.70 39.00 6.4 46.1 39.7 33.4 33.8 35.2 UT072235PH UT072235PH6 22 34.9 49.2 42.9 36.6 37.0 38.4 UT072448PH UT072448PH6 24 38.0 25.50 40.50 53.4 46.0 39.8 40.1 41.5 For 96h salt spray version add ”01” at the end of the part number e.g. UT071412PH601 (only jam nut will be black anodised) For 96h salt spray version add ”01” at the end of the part number e.g. UT071412PH601 (only jam nut will be black anodised) Part number IP67 IP68 Shell size Ø A ± 0.15 B ± 0.2 D Max. F Max. G ± 0.25 H ± 0.3 K ± 0.25 L ± 0.2 Ø M ± 0.2 UT07104SH UT07104SH6 10 14.9 19.30 33.00 3.2 27.0 22.2 16.6 17.0 17.7 UT07128SH UT07128SH6 12 19.0 31.8 27.0 20.8 21.2 22.5 UT071412SH UT071412SH6 14 22.2 34.9 30.2 23.9 24.3 25.7 UT071619SH UT071619SH6 16 25.3 38.1 33.3 27.1 27.5 28.7 UT071823SH UT071823SH6 18 28.5 41.3 36.5 30.3 30.6 32.0 UT072028SH UT072028SH6 20 31.7 24.70 39.00 6.4 46.1 39.7 33.4 33.8 35.2 UT072235SH UT072235SH6 22 34.9 49.2 42.9 36.6 37.0 38.4 UT072448SH UT072448SH6 24 38.0 25.50 40.50 53.4 46.0 39.8 40.1 41.5 new Dynamic IP68 / IP69K High salt spray resistance RoHS compliant connectors on request on request on request 41 Circular accessories Plastic cable clamp with strain relief (UTG--AC) Part number Shell Cable range Ø A ± 0.4 L ± 0.5 size Ø UTG10AC 10 3.0 - 8.70 21.0 40.0 UTG12AC 12 3.0 - 12.8 24.0 40.0 UTG14AC 14 4.0 - 13.8 27.0 46.0 UTG16AC 16 5.0 - 17.0 30.2 46.0 UTG18AC 18 5.0 - 19.0 33.3 50.0 UTG20AC 20 5.0 - 21.0 36.5 55.0 UTG22AC 22 5.0 - 23.0 39.7 60.0 UTG24AC 24 8.0 - 27.0 42.9 65.0 Plastic cable clamp with strain relief nut for waterprotected (IP65) applications (UTG--PG) Part number Shell Sealing* L ± 1 A ± 0.5 size outer dia x inner dia’s UTG10PG 10 13.5 x 5 x 8 54 21.0 UTG12PG 12 16 x 7 x 10.5 x 13 x 16 57 24.0 UTG14PG 14 18.5 x 7 x 105 x 13 x 16 62 27.0 UTG16PG 16 20.5 x 8 x 10.5 x 13 x 16 68 30.2 UTG18PG 18 20.5 x 8 x 10.5 x 13 x 16 71 33.3 UTG20PG 20 26 x 11 x 15 x 18 x 22 82 36.5 UTG22PG 22 26 x 11 x 15 x 18 x 22 88 39.7 UTG24PG 24 35 x 19 x 23 x 27 x 31 103 42.9 *In order to accommodate different cable dia’s, the sealing exisits of different layers which can be pulled out easily. Cable clamp has a PG style cable gland. For threading specifications see last page of this section “Circular accessories” For threading specifications see last page of this section “Circular accessories” Suitable for UTP-UTG Suitable for UTP-UTG 42 Circular accessories Plastic cable clamp with strain relief nut for waterprotected (IP65) applications (UTG--ST) Part number Shell Cable range Dia. A ± 0.5 L ± 1 size UTG10ST 10 2 - 6 21.0 64 UTG12ST 12 3 - 7 24.0 64 UTG14ST 14 6 - 9 27.0 69 UTG16ST 16 7 - 12 30.2 72 UTG18ST 18 33.3 76 UTG20ST 20 9 - 16 36.5 80 UTG22ST 22 39.7 86 UTG24ST 24 13 - 20 42.9 91 Metal cable clamp with strain relief (UT0--AC) Cable clamp has a PG style cable gland. For threading specifications see last page of this section “Circular Part number Shell size Max cable dia. Excl. sealing Ø A±0.2 B maxi C maxi UT010AC 10 5.0 16.3 21.6 31.0 UT012AC 12 8.2 19.4 25.0 31.5 UT014AC 14 10.0 22.5 27.4 34.0 UT016AC 16 13.0 25.8 29.4 34.0 UT018AC 18 16.0 29.2 35.2 31.4 UT020AC 20 16.0 32.5 35.2 32.0 UT022AC 22 19.3 35.7 41.1 31.0 UT024AC 24 20.6 38.8 42.4 31.0 For threading specifications see last page of this section “Circular accessories” Suitable for UTP-UTG Suitable for UT0-UT0W 43 Circular accessories Short cable clamp with strain relief nut for waterprotected applications (IP68). (UT0--JCS) Long cable clamp with strain relief nut for waterprotected applications (IP68). (UT0--JC) Part number Shell size Clamping range (Ø en mm) min / max L± 1 Short Thread A version Long version Short version Long version UT010JCS UT010JC 10 03 / 06 48.5 60.5 9/16 – 24 UNEF Class 2A UT012JCS UT012JC 12 06 / 10 49.5 61.5 11/16 – 24 UNEF Class 2A UT014JCS UT014JC 14 06 / 10 53.5 67.5 13/16 – 20 UNEF Class 2A UT016JCS UT016JC 16 9.5 / 14 62.5 73.5 15/16 – 20 UNEF Class 2A UT018JCS UT018JC 18 9.5 / 14 65.5 76.0 1’’ 1/16 – 18 UNEF Class 2A UT020JCS UT020JC 20 11.5 / 18 70.5 84.0 1’’ 3/16 – 18 UNEF Class 2A UT022JCS UT022JC 22 11.5 / 18 76.5 88.0 1’’ 5/16 – 18 UNEF Class 2A UT024JCS UT024JC 24 11.5 / 18 82.0 92.0 1’’ 7/16 – 18 UNEF Class 2A Short cable clamp with large strain relief nut for waterprotected applications (IP68). (UT0--JCSL) Long cable clamp with large strain relief nut for waterprotected applications (IP68). (UT0--JCL) Part number Shell size Clamping range (Ø en mm) min / max L± 1 Short Thread A version Long version Short version Long version UT010JCSL UT010JCL 10 05 / 08 49.5 61.5 9/16 – 24 UNEF Class 2A UT012JCSL UT012JCL 12 08 / 12 49.5 62.5 11/16 – 24 UNEF Class 2A UT014JCSL UT014JCL 14 08 / 12 54.5 68.5 13/16 – 20 UNEF Class 2A UT016JCSL UT016JCL 16 11.5 / 18 68.5 79.5 15/16 – 20 UNEF Class 2A UT018JCSL UT018JCL 18 11.5 / 18 71.5 82.0 1’’ 1/16 – 18 UNEF Class 2A UT020JCSL UT020JCL 20 15 / 24 77.5 91.0 1’’ 3/16 – 18 UNEF Class 2A UT022JCSL UT022JCL 22 15 / 24 83.5 95.0 1’’ 5/16 – 18 UNEF Class 2A UT024JCSL UT024JCL 24 15 / 24 89.0 99.0 1’’ 7/16 – 18 UNEF Class 2A Cable clamp has a Metric style cable gland. For threading specifications see last page of this section “Circular accessories” Cable clamp has a Metric style cable gland. For threading specifications see last page of this section “Circular accessories” Suitable for UT0-UT0W Suitable for UT0-UT0W 44 Circular accessories Short shielded cable clamp with strain relief nut for waterprotected applications (IP68). (UT0S----JCS) Long shielded cable clamp with strain relief nut for waterprotected applications (IP68). (UT0S----JC) Part number Shell size Clamping range (Ø en mm) min / max L± 1 Short Thread A version Long version Short version Long version UT0S10JCS UT0S10JC 10 04 / 6.5 58.5 70.5 9/16 – 24 UNEF Class 2A UT0S12JCS UT0S12JC 12 07 / 10.5 61.5 74.5 11/16 – 24 UNEF Class 2A UT0S14JCS UT0S14JC 14 07 / 10.5 66.5 80.5 13/16 – 20 UNEF Class 2A UT0S16JCS UT0S16JC 16 10 / 14.5 72.5 83.5 15/16 – 20 UNEF Class 2A UT0S18JCS UT0S18JC 18 10 / 14.5 75.5 86.0 1’’ 1/16 – 18 UNEF Class 2A UT0S20JCS UT0S20JC 20 13.5 / 18 84.5 97.5 1’’ 3/16 – 18 UNEF Class 2A UT0S22JCS UT0S22JC 22 13.5 / 18 90.0 101.5 1’’ 5/16 – 18 UNEF Class 2A UT0S24JCS UT0S24JC 24 13.5 / 18 95.5 105.5 1’’ 7/16 – 18 UNEF Class 2A Short shielded cable clamp with large strain relief nut for waterprotected applications (IP68). (UT0S----JCSL) Long shielded cable clamp with large strain relief nut for waterprotected applications (IP68). (UT0S----JCL) Part number Shell size Clamping range (Ø en mm) min / max L± 1 Short Thread A version Long version Short version Long version UT0S10JCSL UT0S10JCL 10 05 / 8.5 59.5 71.5 9/16 – 24 UNEF Class 2A UT0S12JCSL UT0S12JCL 12 08 / 12.5 61.5 74.5 11/16 – 24 UNEF Class 2A UT0S14JCSL UT0S14JCL 14 08 / 12.5 66.5 80.5 13/16 – 20 UNEF Class 2A UT0S16JCSL UT0S16JCL 16 13.5 / 18 82.5 93.5 15/16 – 20 UNEF Class 2A UT0S18JCSL UT0S18JCL 18 13.5 / 18 85.5 96.0 1’’ 1/16 – 18 UNEF Class 2A UT0S20JCSL UT0S20JCL 20 17 / 24 93.0 106.5 1’’ 3/16 – 18 UNEF Class 2A UT0S22JCSL UT0S22JCL 22 17 / 24 99.0 110.5 1’’ 5/16 – 18 UNEF Class 2A UT0S24JCSL UT0S24JCL 24 17 / 24 104.5 114.5 1’’ 7/16 – 18 UNEF Class 2A Cable clamp has a Metric style cable gland. For threading specifications see last page of this section “Circular accessories” Cable clamp has a Metric style cable gland. For threading specifications see last page of this section “Circular accessories” Suitable for UT0-UT0W Suitable for UT0-UT0W 45 Circular accessories Metal right angle cable clamp with strain relief nut (UTG--LPGN / UTO--LPGN) Part number Part number Shell A max B max Cable range For UTP / UTG For UT0 / UT0W size UTG10LPGN UT010LPGN 10 48.0 30.0 13.5 x 5 x 8 UTG12LPGN UT012LPGN 12 50.0 33.5 16 x 7 x 10.5 x 13 UTG14LPGN UT014LPGN 14 52.0 36.5 18.5 x 7 x 10.5 x 13 x 16 UTG16LPGN UT016LPGN 16 55.0 39.5 20.5 x 8 x 10.5 x 13 x 16 UTG18LPGN UT018LPGN 18 60.0 46.0 20.5 x 8 x 10.5 x 13 x 16 UTG20LPGN UT020LPGN 20 58.0 47.0 26 x 11 x 15 x 18 x 22 UTG22LPGN UT022LPGN 22 58.0 48.5 26 x 11 x 15 x 18 x 22 UTG24LPGN UT024LPGN 24 67.0 54.5 35 x 19 x 23 x 27 x 31 Cable clamp has a PG style cable gland. For threading specifications see last page of this section “Circular accessories” Metal shrink boot adaptor (UTG--AD) for UTP and UTG Part number Shell size Ø A±0.2 B UTG10AD 10 21.0 UTG12AD 12 24.0 19.2 UTG14AD 14 27.0 UTG16AD 16 30.0 21.5 UTG18AD 18 33.3 UTG20AD 20 36.5 22.8 UTG22AD 22 39.7 UTG24AD 24 42.9 21.9 Standard plating is anodised black. For tin plating add “T” at the end of the part number e.g. UTG12ADT For threading specifications see last page of this section “Circular accessories” 46 Circular accessories Environmental dustcap for plugs (UTG6--DCG) Part number Shell size A max. B UTG610DCG 10 20.0 UTG612DCG 12 24.0 UTG614DCG 14 27.5 20.8 UTG616DCG 16 30.5 UTG618DCG 18 33.5 UTG620DCG 20 36.5 UTG622DCG 22 40.0 22.5 UTG624DCG 24 43.0 For dustcap without chain skip “G” e.g. UTG612DC Metal shrink boot adaptor for UTO and UTOW Part number Shell size Ø A±0.2 B For threading specifications see last page of this section “Circular accessories” UT010AD 10 21 UT012AD 12 24 24.7 UT014AD 14 27 UT016AD 16 30 UT018AD 18 33.3 UT020AD 20 36.5 27 UT022AD 22 39.7 UT024AD 24 42.9 Suitable for UTP-UTG-UT0-UT0W 47 Circular accessories Plastic environmental dustcap for receptacles (UTP--DCG) Part number Shell size Ø A ±0.2 B max. UTP10DCG 10 26.7 19.3 UTP12DCG 12 31.4 20.0 UTP14DCG 14 34.5 UTP16DCG 16 37.8 20.2 UTP18DCG 18 40.8 UTP20DCG 20 43.9 UTP22DCG 22 47.0 21.8 UTP24DCG 24 50.1 For dustcap without chain skip “G” e.g. UTP12DC For jam dustcap consult factory Metal environmental dustcap for receptacles (UT0--DCG) Part number Shell size A max. UT010DCG 10 20.8 UT012DCG 12 24.9 UT014DCG 14 28.1 UT016DCG 16 31.3 UT018DCG 18 34.4 UT020DCG 20 37.6 UT022DCG 22 40.8 UT024DCG 24 43.9 For dustcap without chain skip “G” e.g. UTG12DC For jam dustcap consult factory Suitable for UTP-UTG-UT0-UT0W Suitable for UTP-UTG-UT0-UT0W 48 Sealing for wall mounting receptacle (UTFD1-B) Part number Shell size Ø F ±0.1 R ±0.25 S ±0.25 Ø V UTFD12B 10 15.9 18.3 23.8 UTFD13B 12 19.0 20.6 26.2 UTFD14B 14 22.2 23.0 28.6 UTFD15B 16 25.4 24.6 31.0 3.3 UTFD16B 18 28.6 27.0 33.3 UTFD17B 20 31.8 29.4 36.5 UTFD18B 22 34.9 31.8 39.7 UTFD19B 24 38.1 34.9 42.9 4.0 Cable gland threadings used on cable clamps Shell size Thread size on connectors PG threading Metric threading 10 9/16 - 24 UNEF PG9 M16 x 1.5 12 11/16 - 24 UNEF PG11 M20 x 1.5 14 13/16 - 20 UNEF PG13.5 M20 x 1.5 16 15/16 - 20 UNEF PG16 M25 x 1.5 18 1-1/16 - 18 UNEF PG16 M25 x 1.5 20 1-3/16 - 18 UNEF PG21 M32 x 1.5 22 1-5/16 - 18 UNEF PG21 M32 x 1.5 24 1-7/16 - 18 UNEF PG29 M32 x 1.5 Circular accessories Adaptors for flexible cable protection systems (conduits) Adaptors for flexible cable protections systems that fit to the TRIM TRIO circular connectors are available from cable protection systems manufacturers (e.g. PMA). 2 solutions are offered: • UNEF Adaptors that fit directly onto the connectors (left picture) • METRIC Adaptors that fit onto the metal cable clamp tubes as indicated on pages 43 and 44 (right picture) These types of adaptors offer extra protection to single wire applications (electrical, coax, Fibre optic … etc.) Note: the adaptors are not available from Souriau. They must be ordered directly from the manufacturers Suitable for UTP-UTG-UT0-UT0W 0,8 ± 0,2 Clipper Industrial Plastic Connectors 2 Clipper Industrial Plastic Connectors Connectors and interconnect systems for harsh environments The company designs, manufactures and markets high performance interconnect solutions for severe environments from industrial broadline and universal ranges to complex system with integrated functions: filtering, high speed data transmission, hermetic seal, separation mechanism, remote handling, underwater mating, … The dedicated end markets for SOURIAU’s products are aeronautical, defense-space and industrial. Industrial Railway Geophysics Manufacturing environment Instrumentation Automation & process Civil & military aircraft Helicopter Weapon delivery system Avionics Military marine Communications Satellites Launcher & missile Aeronautical Equipment & system SOURIAU was established in 1917 and has been created by successive acquisitions of the industrial, aeronautical, defense and space activities of SOURIAU, JUPITER and BURNDY. The Group’s products are engineered and manufactured in the USA and Dominican Republic, Europe and Morocco, Japan and India, and sold by a worldwide sales and marketing organization, and in addition to SOURIAU’s offices, a large network of licensed distributors and agents. SOURIAU complies with most of national and international Quality Assurance Standards, production unit with ISO 14001. 3 Clipper Industrial Plastic Connectors Description/Features/Presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Square flange receptacle and in-line receptacle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Plug and backnut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical thread backshell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Stamped and formed contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Machined contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IP68 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IP67 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Mated and unmated connectors (with backshells) overall dimensions . . . . . . . . . . . . . . . . . . . . . . . 16 Dimensions (receptacle and plug) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Manual crimping tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Automatic crimping tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Panel mounting/panel cut-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Wiring instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Assembly instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General technical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contents Clipper Industrial Plastic Connectors 4 Presentation CLIPPER is a plastic low cost range of industrial connectors, UL & CSA approved. Complementing SOURIAU product range CLIPPER offers : • a high sealing level : - IP67 for the sealed plug (with o’ring and mating seal) - IP68 for the enhanced sealed plug (with o’ring and a special mating seal). This version allows a permanent waterproof level when immersed at depths down to 30 meters. • a retention plate system allowing insertion/extraction of the contacts without the need for tooling, • facilities to use trade backshells with the electrical thread adaptor (PG). CLIPPER range is composed of : • 4 sizes of shell in molded black thermoplastic material (size 1/2/3/4). • 7 contact layouts (4/9/14/18/26/31/40 contacts). • #20, #16 contacts, machined or stamped and formed, crimp, solder or PC tail termination. • An adaptor with electrical PG thread for PG backshells. • Backnut with grommet facilities. Locked, the retention plate holds the contacts firmly in position Unlocked, the retention plate allows the insertion/extraction of contacts without tooling Locked plate Unlocked plate Description Retention plate principle Features Mechanical • Monobloc shell and insulator in thermoplastic material self-extinguishing to UL 94 V0. • 180° screw coupling with positive audible safety latch. • Scoop proof. • Copper alloy contacts, machined or stamped and formed • plating : gold on active part over nickel. • Mechanical endurance : - connector : 250 cycles mating / unmating, - retention plate : 50 cycles mating / unmating. • Retention force : - # 20 → 70 N - # 16 → 90 N. • Vibration : - frequency range : 10-2000 Hz, 20 g - 10 cycles in accordance with CEI 68-2-6 Electrical • Withstand voltage : 1500 Vrms min or in accordance with DIN 57110b. • Contact resistance < 10 mW. • Current rating per contact : - machined contacts : # 20 (7 Amps), # 16 (13 Amps) - stamped and formed contacts : # 20 (5 Amps), # 16 (10 Amps). Environmental • Sealing : - up to IP68 • Working temperature : -40°C to +125°C. (-40°F to +257°F) • Resistance to salt spray : - 48 h min - > 1000 h (sealed mated connectors). • Resistance to fluids : - oil, - petrol, fuel, - lubricants - other fluids : consult us. Clipper Industrial Plastic Connectors 5 CL1M1100 CL1R1100 CL1R1101 CL1R1102 CL1R2102 CL1R3102 CL1R4202 CL1R2101 CL1R3101 CL1R4201 CL1M1101 CL1M1102 CL1C1100 CL1C1101 CL1C1201 CL1C2101 CL1C2201 CL1C3101 CL1C3201 CL1C4101 CL1C1200 CL1C2100 CL1C2200 CL1C3100 CL1C3200 CL1C4100 CL1C4200 CL1M1202 CL1M2102 CL1M2202 CL1M3102 CL1M3202 CL1M4102 CL1M4202 CL1M1201 CL1M2101 CL1M2201 CL1M3101 CL1M3201 CL1M4101 CL1M4201 CL1R2100 CL1R3100 CL1R4200 CL1M1200 CL1M2100 CL1M2200 CL1M3100 CL1M3200 CL1M4100 CL1M4200 Receptacle types without contacts Contacts layouts Unsealed receptacle (without o’ring) for male contacts for female contacts for male contacts for female contacts for male contacts for female contacts unsealed for male contacts sealed for male contacts Sealed receptacle (with o’ring) for use with backshell Sealed receptacle (with o’ring and panel gasket) In-line receptacle Shell sizes 1 2 3 4 4 cts # 16 9 cts # 20 9 cts # 16 14 cts # 20 18 cts # 16 31 cts # 20 26 cts # 16 40 cts # 16 Available Style Square flange receptacle and in-line receptacle Part number CL1C4201 Clipper Industrial Plastic Connectors 6 Part number Grommet Thrust ring O ring CL1P1100 CL1F1100 CL1F1200 CL1F1101 (IP67) CL1F1103 (IP68) CL1F1201 (IP67) CL1F1203 (IP68) CL111101 CL111201 CL112101 CL113101 CL113201 CL114101 CL114201 CL1F2101 (IP67) CL1F2103 (IP68) CL1F2201 (IP67) CL1F2203 (IP68) CL1F3101 (IP67) CL1F3103 (IP68) CL1F3201 (IP67) CL1F3203 (IP68) CL1F4101 (IP67) CL1F4103 (IP68) CL1F4201 (IP67) CL1F4203 (IP68) CL1P1101 CL111102 CL111000 CL112000 CL113000 CL111202 CL112102 CL113102 CL113202 CL114102 CL114202 CL1P2101 CL1P3101 CL1P4201 CL1F2100 CL1F2200 CL1F3100 CL1F3200 CL1F4100 CL1F4200 CL1P2100 CL1P3100 CL1P4200 Plug types without contacts Contact layouts Unsealed plug (without o’ring and mating seal) for male contacts for female contacts for male contacts for female contacts for male contacts for female contacts for male and female contacts Sealed plug (with o’ring and mating seal) Sealed backnut Unsealed backnut Shell sizes 1 2 3 4 4 cts # 16 9 cts # 20 9 cts # 16 14 cts # 20 18 cts # 16 31 cts # 20 26 cts # 16 40 cts # 16 Plug and backnut CL114000 Unsealed (IP40) Clipper Industrial Plastic Connectors 7 Note : Electrical thread backshells are always supplied complete with the adaptor. Part numbers Description 1 2 3 4 (PG 13,5) (PG 16) (PG 21) (PG 36) (PG 36) Straight backshell for flexible CL101040 CL102040 CL103040 CL124040 CL104040 conduit systems Straight cable CL101030 CL102030 CL103030 CL124030 - clamp Sealed Part numbers Description 1 2 3 4 (PG 13,5) (PG 16) (PG 21) (PG 36) (PG 36) Elbow backshell with sealing CL101051 CL102051 CL103051 CL124051 - gland Straight backshell for flexible CL101041 CL102041 CL103041 CL124041 CL104041 conduit systems Antidecoupling sealing CL101021 CL102021 CL103021 CL124021 CL104021 gland backshell Electrical thread backshells (PG) Clipper Industrial Plastic Connectors Shell Part number 1 CL141001 2 CL142001 3 CL143001 4 CL144001 Dim. (inches) / Shell sizes A B C D E 1 .84 .96 1.52 .13 1.15 2 .97 1.10 1.56 .13 1.21 3 1.12 1.20 1.69 .15 1.40 4 1.44 1.55 1.95 .15 1.87 90° sealed adaptors for receptacles Shell 1 to 4 * with panel gasket Shell Part numbers Sealed* 1 CL131001 2 CL132001 3 CL133001 4 CL134001 IP67 Dust cap for receptacle 90° adaptors for receptacles Accessories 8 90° adaptors for receptacles Panel gasket (for square flange receptacle) Shell sizes 1 2 3 4 Part numbers CL191001 CL192001 CL193001 CL194001 Clipper Industrial Plastic Connectors 9 Assembly male 2 mm to 3 mm (0.08" to 0.12") female 16 0.7 to 1.5 mm2 male female CF16PC10RF CF16SC10RF CF16PC18RF CF16SC18RF Bulk Reel 5,000 pcs. male 1.2 mm to 2.1 mm (0.05" to 0.08") female female 20 0.35 to 0.6 mm2 male CF10PC10RF CF10SC10RF CF10PC18RF CF10SC18RF Bulk Reel 5,000 pcs. Filler plug # 16 Part number : 8500 479 CL (for un-used contact cavities) Polarization Contact Part number : CP16SW9700 (instruction for polarizing connector - see page 23) Filler plug # 20 Part number : 8500 4144 (for un-used contact cavities) 18 to 16 22 to 20 CM16PT10LY CM10PT10LY 16 20 male male Bulk Print Circuit (PC) Tail Machined Contact Admissible section mm2 AWG Ø mm over insulation (inches) Part numbers Size Crimp Contact with strain relief Packaging Plating RF : gold flash on active part for standard version (For other platings, consult FCI) Stamped and formed contacts Clipper Industrial Plastic Connectors 10 CM16PC10MQ CM16PC20MQ* CM16SC10MQ CM16SC20MQ* CM16PS10MQ CM16SS10MQ Part numbers CM16PC10MQ CM16SC10MQ CM16PS10MQ CM16SS10MQ CM10PS10MQ male female male female Plating MQ : 0.4μ mm gold on active part (.016μ inches) * Up to 1.91 mm2 Packaging male female male CM16PC20MQ female CM16SC20MQ male CM10PC20MQ female CM10SC20MQ Bulk solder 8501 9641 8501 9642 CL 16 20 male male Bulk Extended ground contact-crimp (Length + .039 inch = +1 mm) 0.08" to 0.12" 18 to 14 0.05" to 0.08" 24 to 18 2 mm to 3 mm 16 (0.08" to 0.12") 0.93 to 1.91 mm2 16 2 to 3 mm (0.08" to 0.12") 20 0.21 to 0.60 mm2 1.2 to 2.1 mm (0.05" to 0.08") 30 to 24 0.06 to 0.21 mm2 20 Contact types Size Ø mm over insulation (inches) Admissible section mm2 male female CM10PC10MQ CM10SC10MQ 20 1.2 mm to 2.1 mm (0.05" to 0.08") 18 to 14 AWG 0.21 to 0.93 mm2 crimp male female CM16PC00MQ CM16SC00MQ 16 2 mm to 3 mm (0.08" to 0.12") 0.93 to 2.60 mm2 crimp solder crimp CM10SS10MQ 14* Max 24 to 18 18 Max 18 to 13 Machined contacts Clipper Industrial Plastic Connectors 11 IP68 Configuration (temporary water tightness down to 100 feet) IP68 Configuration Clipper Industrial Plastic Connectors Part numbers CL1C2201 CL1C4201 CL1C4101 CL1C3201 CL1C3101 CL1C2101 CL1C1201 CL1C1101 CL101021 (pg 13.5) CL1F1103 CL1F1203 CL1F2103 CL1F2203 CL1F3103 CL1F3203 CL1F4103 CL1F4203 CL1M1102 CL1M1202 CL1M2102 CL1M2202 CL1M3102 CL1M3202 CL1M4102 CL1M4202 for male contacts Sealed receptacle (with o’ring and panel gasket) for female contacts Sealed plug (with o’ring and mating seal) Anti-decoupling sealing gland backshell CL102021 (pg 16) CL103021 (pg 21) CL124021 (pg 29) Shell types (without contacts) and Backshell type Contacts layouts Shell sizes 1 2 3 4 4 cts # 16 9 cts # 20 9 cts # 16 14 cts # 20 18 cts # 16 31 cts # 20 26 cts # 16 40 cts # 16 for male contacts o’ring Sealed In-line receptacle IP68 Configuration CL104021 (pg 36) 12 IP67 Configuration (temporary water tightness) Clipper Industrial Plastic Connectors IP67 Configuration 13 Clipper Industrial Plastic Connectors Part numbers CL1F2201 CL1F4101 CL1F3201 CL1F3101 CL1F2101 CL1F1201 CL1F1101 CL1C1101 CL1C1201 CL1C2101 CL1C2201 CL1C3101 CL1C3201 CL1C4101 CL1M1102 CL1M1202 CL1M2102 CL1M2202 CL1M3102 CL1M3202 CL1M4102 Sealed receptacle (with o’ring and panel gasket) for male contacts Sealed plug (with o’ring and mating seal) o’ring Sealed In-line receptacle CL1M1102 CL1R1102 CL1P1101 CL1P2101 CL1P3101 CL1P4201 CL1R2102 CL1R3102 CL1R4202 CL1F4201 CL1M2102 CL1M3102 CL1M4202 Shell types without contacts Contact layouts for male contacts for female contacts Shell sizes 1 2 3 4 4 cts # 16 9 cts # 20 9 cts # 16 14 cts # 20 18 cts # 16 31 cts # 20 26 cts # 16 40 cts # 16 for male contacts for female contacts IP67 Configuration CL1C4201 14 Part numbers Clipper Industrial Plastic Connectors Grommet Thrust ring O ring CL111102 CL111101 CL111201 CL112101 CL113101 CL113201 CL114101 CL114201 CL101051 (pg 13.5) CL101041 (pg 13.5) CL101021 (pg 13.5) CL102021 (pg 16) CL103021 (pg 21) CL124021 (pg 29) CL124051 (pg 29) CL124041 (pg 29) CL111202 CL112102 CL113102 CL113202 CL114102 CL114202 CL102051 (pg 16) CL102041 (pg 16) CL103051 (pg 21) CL103041 (pg 21) CL104041 (pg 36) Backshell types Contact layouts for male contacts for female contacts Elbow backshell with sealing gland Straight backshell for flexible conduit systems Anti-decoupling sealing gland backshell Sealed backnut Shell sizes 1 2 3 4 4 cts # 16 9 cts # 20 9 cts # 16 14 cts # 20 18 cts # 16 31 cts # 20 26 cts # 16 40 cts # 16 IP67 Configuration CL104021 (pg 36) 15 Clipper Industrial Plastic Connectors LD LV A B ADAPTOR BACKNUT C STRAIGHT CABLE CLAMP D J STRAIGHT BACKSHELL FOR CONDUIT SYSTEM F SEALING GLAND BACKSHELL WITH ANTI-DECOUPLING SYSTEM G ELBOW BACKSHELL WITH SEALING GLAND KL R N Q * For other needs, consult FCI. Dimensions 1 2 3 4 (PG 29)(PG 36) LDA 2.01 2.09 2.09 2.17 2.17 LVA 2.29 2.33 2.33 2.41 2.41 LDB 1.81 1.85 1.85 - 1.85 LVB 2.09 2.09 2.09 - 2.09 LDC 2.68 2.85 3.03 3.41 - LVC 2.97 3.09 3.27 3.60 - LDD 3.41 3.50 3.62 3.70 4.25 LVD 3.70 3.74 3.86 3.94 4.47 LDF 3.15 3.27 3.35 3.74 4.02 LVF 3.43 3.50 3.58 3.98 4.25 LDG 3.31 3.46 3.77 4.29 - LVG 3.58 3.70 4.01 4.52 - R Max. 2.24 2.34 2.87 3.58 - Dim. (inches) Shell Cable acceptance* 1 2 3 4 (PG 29) (PG 36) J .24/.55 .24/.63 .31/.83 .39/ - 1.10 Conduit L .67 .67 .91 1.14 1.42 Pmaflex K Max .63 .63 .85 1.08 1.42 N .24/47 .39/.55 .51/.71 .71/.98 .87/ 1.26 Q .24/.47 .39/.55 .51/.71 .71/.98 - Dim. (inches) Shell Mated and unmated connectors with backshells Overall dimensions in inches 16 Clipper Industrial Plastic Connectors 17 Square flange receptacle Plug Dimensions in inches 1 2 3 4 A .8 .8 .8 .8 B 1.15 1.28 1.46 1.92 C .81 .94 1.12 1.57 D 1.52 1.56 1.56 1.56 Dim. (inches) Shell sizes 1 2 3 4 A 1.67 1.67 1.67 1.67 B .83 .96 1.14 1.59 C .71 .71 .71 .71 D .16 .16 .16 .16 E .81 .94 1.12 1.57 F 1.17 1.23 1.42 1.89 G min. .83 .96 1.11 1.43 Max. .92 .98 1.17 1.57 H .13 .13 .15 .15 Dim. (inches) Shell sizes Clipper Industrial Plastic Connectors • Squeeze the plier handles until a final click sounds, release, the pliers should open by themselves. • Fully insert the contact into the locator (corresponding gauge), the contact crimping lugs should be directed upwards, according to the drawing. • Put the stripped wire in the crimping part until it comes in contact with the stopper plate. Make sure that no strands stick out of the crimping part. • Squeeze the plier handles until a final click sounds, release, the pliers should open by themselves. • Check the overall aspect of the crimping. • Push the cable into the contact barrel and make sure the cable strands stick out of the inspection hole. • The pliers must be used on the jaws side. • Squeeze the plier handles until a final click sounds, release, the pliers should open by themselves. • Insert both wire and contact (or wire, reducing sleeve and contact) between the 4 jaws until stopped by the locator. • Fully squeeze until a final click sounds, the pliers should open once the crimping is performed • Extract the wire and crimped contact, then check the overall aspect of the crimping. Stamped and Formed Contacts (#16 and #20) Y16SCMCL3 Machined Crimping Contacts (#16 and #20) 8365 with locator 8365-02 Manual Crimping Tool 18 Crimping Mechanism (left side miniapplicators) Clipper Industrial Plastic Connectors UTM2 Automatic crimping tool for Clipper Description Electromechanical high speed semi automatic press is designed for mass production and is realized totally in assembled steel parts. Voltage: 115VAC - 60 Hz Power.: 700 Watts Weight: 300 lbs. (including one crimp mechanism) Dimensions: 939.8x533.4x711.2 mm (37.0"x21.0"x28.0") Contacts AWG Contact P/N Crimp Mech. P/N 16 16-18 CF16 PS 18RF CM30-R CF16 SC 18RF 20 20-22 CF10 PS 18RF CM31-R CF10 SC 18RF Press and crimping mechanism are rental. Please contact Customer Service. Automatic crimping tool 19 Clipper Industrial Plastic Connectors 20 Panel mounting There are two types of mounting possible: through the front or through the back of the panel. Panel cut-out • For a sealed mounting, the seal gasket shall be used, making sure the surface is in good condition. • Observe the drilling hole diameters indicated below. • Use the recommended screws : M3 (all shells) or # 4.40 (shells 1 and 2) # 6.32 (shells 3 and 4) • Respect the coupling torques indicated M3 (all shells) : 0.70 N.m Max Rear Mounting .157" max (4 mm max) Front Mounting .157" max (4 mm max) Panel mounting / Panel cut-out 1 2 3 4 H .85 .98 1.22 1.61 I .84 .97 1.13 1.44 J .13 .13 .15 .15 Dim. (inches) Shell sizes Wire Stripping Length • With machined crimping contacts • With stamped and formed crimping contacts Clipper Industrial Plastic Connectors 21 Jacketed Cable Stripping Length Make a 90° cut at the cable end. carefully make an incision in order to remove the cable protection on a length LD as described. Caution : This operation should be realized without deterioration of wires insulation. Then, follow the normal stripping instructions : - single wire with machined crimping contacts, - single wire with stamped and formed crimping contacts Stripping Instructions Use the upmost care with stripping operation : • Use stripping pliers appropriate for the cable gauge and which are in perfect condition. • In order to obtain a correct crimping and to maintain all of the connector sealing characteristics, the wires must have the dimensions described below. l Shell size 1 2 3 4 layouts Indifferent 26 40 LD mm 60 65 65 80 100 (inch) (2.36’) (2.56’) (2.56’) (3.15") (3.94") Contact size I = Wire stripping lenght layouts 6 mm (.236") #20 Ø over insulation > 2 mm 􀃖 l = 5 (> .08" 􀃖 l = .20") Ø over insulation > 2 mm 􀃖 l = 7 (> .08" 􀃖 l = .27") Contact diameter I = Wire stripping lenght #16 4 mm (.157") #20 4 mm (.157") Wiring Instruction Clipper Industrial Plastic Connectors 22 Instruction For Assembly Insertion and extraction of contacts Single wires Contact insertion and extraction is performed without a tool thanks to te retainer plate system. Insertion 1) With the thumb and index finger, squeeze the retainer plate flaps and pull backwards : the plate is then in the unlocked position. 2) Fully insert the wired contact in the cavity. 3) Repeat the same procedure for the other contacts. 4) Once again squeeze the retainer plate flaps and push forwards: the plate is then locked and retains the contacts (90 N of retention force for contacts of 1.6 mm dia.) 5) The plate can only be pushed backed if the contacts are correctly engaged (backup security) Extraction 1) With the thumb and index finger, squeeze the retainer plate flaps and pull backwards : the plate is then in the unlocked position. 2) Pull the contact wire: the the contact comes out of the cavity. 3) Repeat the same procedure for the other contacts. Special case of jacketed cables 1) Locate the first contact and the corresponding cavity. 2) The wire should described a buckle as describe below. 3) Unlock the retainer plate as described above. 4) Fully insert the wired contact in the cavity. 5) Respect the same procedure for the other contacts 6) Once again squeeze the retainer plate flaps and push forwards : the plate is then locked Special case of jacketed cables 7) Manually fully screw the adaptor and the backshell on the connector. Caution : In the sealed version don’t forget the O-ring. 8) Push forwards the cable of 10 mm in the backshell. 9) Fully screw on the backshell with a wrench while keeping the adaptor with another wrench. Note : The plate can only be pushed back if the contacts are correctly engaged (backup- security) Adaptor and PG electrical thread backshells The CLIPPER connector must be equipped with an adaptor in order to use a PG electrical thread backshell (e.g.: cable clamp or sealing gland, or flexible conduits system backshells, etc.) 1) Manually, fully screw the adaptor on the connector, the hexagonal nut towards the rear. 2) In the sealed version, cover the O-ring. 3) Manually, fully screw the PG thread backshell of your choice. Note: In the case of an elbow backshell, it is possible to adjust the position according to the angle desired. 1) Position the O-ring at the bottom of the backnut. 2) Run the backnut around the cable. 3) Unlock the retainer plate. 4) Position the grommet in the thrust ring, resting against the retainer plate. 5) Insert the contacts through the grommet and the retainer plate. 6) Lock the retainer plate. 7) Screw the backshell. Instruction For Assembly Clipper Industrial Plastic Connectors 23 When the insert is partially filled with contacts, place polarization contact into selected hole location in the FEMALE INSERT and push in until seated. • Polarization contacts are used to provide keying capabilities for the CLIPPER series. • Polarization contacts are used in the socket-cavities of standard plugs and reverse receptacles. In order to lock the couple of chosen connectors, you have to let free the cavity in front of the polarization contact. To avoid the connection with other connectors, you have to insert a contact in the cavity in front of the polarization contact. Heat shrink boot Shrink sleeve as follows : 1) Use heat gun with an air deflector nozzle. 2) Adjust air deflector opening to accommodate tubing size. Turn switch ON. Wait until full heat output is reached. 3) Position the air deflector over section of tubing to be shrunk. Start at pre-shrunk section and work towards open end. 4) When tubing begins to shrink, move gun so that air is distributed in a band around the tubing circumference causing it to shrink evenly around the cable. 5) Move nozzle to adjacent section and shrink in the same manner. Repeat process on section at a time until entire length is shrunk. Avoid excessive heat. Direct heat away from connector assembly to prevent damage. Instruction for polarizing connector mounting CP16SW9700 Grommet Backshell Assembly Clipper Industrial Plastic Connectors EXAMPLE : IP66-5 means: - Total protection against dust - Proof against temporary flooding - Proof against impact strength of 2 Joule Degree of protection in accordance with CEI 529, DIN 40050, NF EN 60529 General technical information 24 Clipper Industrial Plastic Connectors Conversion Table (mm) (inches) 8.2 0.32308 8.4 0.33096 8.6 0.33884 8.8 0.34672 9.0 0.35460 9.2 0.36248 9.4 0.37036 9.6 0.37824 9.8 0.38612 10.0 0.39400 10.5 0.41370 11.0 0.43340 11.5 0.45310 12.0 0.47280 12.5 0.49250 13.0 0.51220 13.5 0.53190 14.0 0.55160 14.5 0.57130 15.0 0.59100 15.5 0.61070 16.0 0.63040 16.5 0.65010 17.0 0.66980 17.5 0.68950 18.0 0.70920 18.5 0.72890 19.0 0.74860 19.5 0.76830 20.0 0.78800 20.5 0.80770 21.0 0.82740 21.5 0.84710 22.0 0.86680 22.5 0.88650 23.0 0.90620 23.5 0.92590 24.0 0.94560 24.5 0.96530 25.0 0.98500 25.5 1.00470 26.0 1.02440 26.5 1.04410 27.0 1.06380 27.5 1.08350 28.0 1.10320 28.5 1.12290 29.0 1.14260 29.5 1.16230 30.0 1.18200 30.5 1.20170 31.0 1.22140 31.5 1.24110 32.0 1.26080 32.5 1.28050 33.0 1.30020 33.5 1.31990 34.0 1.33960 34.5 1.35930 35.0 1.37900 35.5 1.39870 36.0 1.41840 36.5 1.43810 37.0 1.45780 37.5 1.47750 (°C) (°F) - 70 - 94 - 65 - 85 - 55 - 67 - 50 - 58 - 40 - 40 0 32 37 98.6 80 176 125 257 150 302 170 338 200 392 250 482 (1) 6145DJ - Câbles multipaires (armés, paires blindées) 250 MZH. (2) 6145DJ - Câbles multipaires (armés, paires non blindées) 250 MZH. (mm) (inches) 0.1 0.00394 0.2 0.00788 0.3 0.01182 0.4 0.01576 0.5 0.01970 0.6 0.02364 0.7 0.02758 0.8 0.03152 0.9 0.03546 1.0 0.03940 1.1 0.04334 1.2 0.04728 1.3 0.05122 1.4 0.05516 1.5 0.05910 1.6 0.06304 1.7 0.06698 1.8 0.07092 1.9 0.07486 2.0 0.07880 2.1 0.08274 2.2 0.08668 2.3 0.09062 2.4 0.09456 2.5 0.09850 2.6 0.10244 2.7 0.10638 2.8 0.11032 2.9 0.11426 3.0 0.11820 3.1 0.12214 3.2 0.12608 3.3 0.13002 3.4 0.13396 3.5 0.13790 3.6 0.14184 3.7 0.14578 3.8 0.14972 3.9 0.15366 4.0 0.15760 4.1 0.16154 4.2 0.16548 4.3 0.16942 4.4 0.17336 4.5 0.17730 4.6 0.18124 4.7 0.18518 4.8 0.18912 4.9 0.19306 5.0 0.19700 5.2 0.20488 5.4 0.21276 5.6 0.22064 5.8 0.22852 6.0 0.23640 6.2 0.24428 6.4 0.25216 6.6 0.26004 6.8 0.26792 7.0 0.27580 7.2 0.28368 7.4 0.29156 7.6 0.29944 7.8 0.30732 8.0 0.31520 (mm) (inches) 38.0 1.49720 38.5 1.51690 39.0 1.53660 39.5 1.55630 40.0 1.57600 40.5 1.59570 41.0 1.61540 41.5 1.63510 42.0 1.65480 42.5 1.67450 43.0 1.69420 43.5 1.71390 44.0 1.73360 44.5 1.75330 45.0 1.77300 45.5 1.79270 46.0 1.81240 46.5 1.83210 47.0 1.85180 47.5 1.87150 48.0 1.89120 48.5 1.91090 49.0 1.93060 49.5 1.95030 50.0 1.97000 51.0 2.00940 52.0 2.04880 53.0 2.08820 54.0 2.12760 55.0 2.16700 56.0 2.20640 57.0 2.24580 58.0 2.28520 59.0 2.32460 60.0 2.36400 61.0 2.40340 62.0 2.44280 63.0 2.48220 64.0 2.52160 65.0 2.56100 66.0 2.60040 67.0 2.63980 68.0 2.67920 69.0 2.71860 70.0 2.75800 71.0 2.79740 72.0 2.83680 73.0 2.87620 74.0 2.91560 75.0 2.95500 80.0 3.15200 85.0 3.34900 90.0 3.54600 100.0 3.94000 200.0 7.88000 400.0 15.76000 600.0 23.64000 800.0 31.52000 1000.0 39.40000 1200.0 47.28000 1600.0 63.04000 2000.0 78.80000 3200.0 126.08000 bar psi mmHg (torr) 10 145.0 7600 5 72.5 3800 2 29.0 1520 1 14.5 760 0.5 7.2 380 0.1 1.4 76 mbar psi torr (mmHg) 10 145.0 7600 5 72.5 3800 2 29.0 1520 1 14.5 760 0.5 7.2 380 0.1 1.4 76 25 Clipper Industrial Plastic Connectors 26 Notes Clipper Industrial Plastic Connectors 27 Notes www.souriau.com FSOURIAUCLIPPERJANVIER2007E © Copyright SOURIAU - Réalisation En Toute Transparence. UTS Series Dynamic IP68/69K • UV Resistant • UL/IEC Compliant © 2011 – SOURIAU 3 How to read our catalogue ........................................ 06 UTS range overview ..................................................... 07 General technical characteristics ............................. 10 Cable assembly ............................................................... 14 2 contacts ....................................................................... 20 2 + ground contacts ................................................... 28 3 contacts ........................................................................ 36 3 + ground contacts .................................................... 52 4 contacts ........................................................................ 60 5 contacts ........................................................................ 72 6 contacts ........................................................................ 76 6 + ground contacts .................................................... 88 7 contacts ........................................................................ 92 8 contacts ........................................................................ 96 10 contacts ..................................................................... 104 12 contacts ...................................................................... 108 14 contacts ...................................................................... 116 15 contacts ...................................................................... 120 18 contacts ..................................................................... 124 19 contacts ..................................................................... 128 23 contacts ..................................................................... 132 32 contacts ..................................................................... 136 Contents UTS Series Overview Mechanics Description ...................................................................... 142 Contact plating selector guide .................................. 143 Contact selector guide ................................................ 144 Packaging ........................................................................ 144 Crimp contacts ............................................................... 145 #16 coaxial contacts ................................................... 147 PCB contacts .................................................................. 148 Fibre optic contacts ...................................................... 149 Contacts Tooling .............................................................................. 154 Assembly instruction .................................................... 156 Dimensions overmoulded harnesses ..................... 162 Extraction tools .............................................................. 162 Rated current & working voltage .............................. 163 UV resistance ................................................................. 164 UL94 + UL1977 ............................................................ 165 IEC 61984 with IP code explanation ...................... 168 What is NEMA rating ? ................................................ 170 Ethernet for the layman ............................................... 171 Technical information #16 coaxial contacts - cabling notices .................. 176 Glossary of terms .......................................................... 183 Discrimination/Keying methods ............................... 184 Part number Index.......................................................... 185 Appendices Appendices Technical information Contacts Mechanics Overview UTS Series © 2011 – SOURIAU 5 Overview UTS Series How to read our catalog .............................................................................................................. 06 UTS range overview ...................................................................................................................... 07 General technical characteristics .............................................................................................. 10 6 © 2011 – SOURIAU UTS Series Overview SOURIAU is pleased to announce the arrival of a brand new catalog containing some signifi cant improvements to simplify the connector selection process and provide easy access to key information. In this version you can see all layouts at a glance, download 2D drawings and 3D models. Then, when your choice is made, you can click on the part number and buy online. Step 3 Step 2 Easy access to supporting material such as prints and CAD models. In just two pages you can gather together details of all accessories, contacts, tools etc required for your application. Interactive zones. Clearer understanding of the range. Step 1 © 2011 – SOURIAU 7 UTS range overview The UTS series is a plastic connector range but rugged enough to withstand industrial applications. The philosophy of the UTS series is built around three key elements: Dynamic IP68/69K UV Resistant UL/IEC Compliant In most applications, our connectors are exposed to extreme climatic conditions; it was therefore key for us to select the materials best able to cope with the targeted environment. Part of our product qualifi cation process involved subjecting connectors to a simulated fi ve years of exposure to various elements including Temperature, UV and Humidity. The results were positive in that there were no visible signs of weakness, such as cracking or crazing. The outmost priority for any electrical installation is to protect personnel from any shock hazard. In North America, Underwriters Laboratories insisted that connector manufacturers, depending of the application, respect their standards. The UTS series had thus been qualifi ed and is certifi ed by this organisation. In Europe and in Asia, IEC standards are better known and trusted by end users. Like its American equivalent, the IEC refers to safety rules. The UTS series was obviously designed to respect these rules. UTS series is rated at IP68/69K… even in dynamic conditions. This means that it remain sealed even when used continuously underwater or cleaned using a high pressure hose and cable is moving. This extreme level of performance is achievable with jacketed cable or discrete wires. If this same level of performance is required even when connectors are not mated, we have UTS Hi Seal; a product designed to remain watertight if an environmental cap is not fi tted or if the equipment is likely to get wet when cables have been disconnected. Screw termination version UTS series is a wide range... Based on multiple power & signal connectors and offers everything from box mounted receptacles and cable mounted plugs to cable mounted in-line and PCB mounted receptacles. Almost all ways to accommodate wires exist: Crimp, Solder, Screw termination. UTS Series Overview The bayonet coupling system makes it simple to use. With only a 1/3 twist of the coupling ring, connectors are mated with an audible and sensitive “click”. Overview 8 © 2011 – SOURIAU Just screw the wires to the connector ! No special tools required, use a standard screwdriver UTS screw termination UTS range UTS discrete wire sealing See page 9 Sealed: IP68/69K UV resistant UL/IEC compliant Corrosion-proof Plastic housing UTS Series Plug Corrosion-proof Plastic housing UTS Hi seal Sealed Unmated Sealed unmated: IP68/69K MIL-C-26482 compatible UV resistant UL/IEC compliant Screw termination contact Solder contact Crimp contact • machined • stamped and formed • coaxial • fibre optics UTS Series Overview © 2011 – SOURIAU 9 overview Metal hold down clips - to lock the connector easily on the PCB and to release stress on solder joints - suitable for soldering in a metalised hole Pre-assembled PCB contacts - machined or stamped versions available - different solder tails lengths possible - different plating options Low profi le housing to limit space between panel and PCB Stand-offs to allow cleaning after soldering UTS PCB contacts Receptacle No fi ller plug needed Grommet Containment ring Backnut or Easy handling backshell UTS discrete wire sealing Double Sealing UTS Series Overview Overview 10 © 2011 – SOURIAU General technical Mechanical • Durability: 250 matings & unmatings per MIL-C-26482 • Vibration resistance (all UTS versions except UTS Screw termination contacts): Sinusoidal vibrations per CEI 60512-4 - from 10 to 2000 Hz • Thermal shock: 5 cycles 30 min. from -40°C to 105°C per MIL-STD1344 method 1003 Environmental • Operating temperature: from -40°C to +105°C 40/100/21 per NFF 61-030 • Flammability rating: UL94-V0 (all UTS except the Hi seal) - see page 165 UL94-HB (UTS Hi seal only) - see page 165 I2F3 according to NFF 16101 and NFF 16102 • Salt spray: 500 hours • UV resistant: No mechanical degradation or important variation of colour after 5 years of exposure in natural environment (equivalence exposure to sun and moisture as per ISO4892) • Sealing: - UTS Standard: IP68/IP69K (mated) - UTS Hi seal: IP68/IP69K (mated and unmated) - UTS Discrete wire sealing: IP67/69K (up to IP68 with easy handling backshell) - UTS Screw termination contacts: IP68/IP69K Note: IPx8: 10m underwater during 1 week • Fluid resistance: - Gasoil - Mineral oil - Acid bath - Basic bath 1 2 3 4 5 1 3 UTS Series Overview © 2011 – SOURIAU 11 characteristics Material • Body connector + Backshell: Thermoplastic • Insert: - UTS Standard, UTS Discrete wire sealing, UTS Screw termination contacts: Thermoplastic - UTS Hi seal handsolder & UTS Hi seal with PC tails contacts: Elastomer • Contacts: See page 140 • Nut: Metal • Halogen free • RoHS compliant & conform to the Chinese standard SJ/T1166-2006 (Chinese RoHS equivalent) • In accordance with: - UL 1977: Certifi cat ECBT2 File number: E169916 - CSA C22.2 n°182.3: Certifi cat ECBT8 File number: E169916 Electrical • See each layout page 1 2 4 5 UTS Series Overview Overview UTS Series © 2011 – SOURIAU 13 UTS Series Mechanics Cable assembly ................................................................................................. 14 2 contacts 8E2/8D2: 7A 32V ............................................................................................. 20 12E2/12D2: 16A 150V ............................................................................................ 24 2 contacts + ground 103: 16A 300V ............................................................................................ 28 142G1: 40A 300V ............................................................................................ 32 3 contacts 8E3/8D3: 7A 32V ............................................................................................. 36 8E3A/8E98 8D3A/8D98: 7A 50V ............................................................................................. 40 8E33/8D3.: 7A 50V ............................................................................................. 44 12E3/12D3: 16A 150V ............................................................................................ 48 3 contacts + ground 124 - 12E4/12D4: 16A 300V ............................................................................................ 52 183G1: 32A 300V ............................................................................................ 56 4 contacts 8E4/8D4: 7A 32V ............................................................................................. 60 102W2: 25A 150V ............................................................................................ 64 104: 13A 150V ............................................................................................ 68 5 contacts 14E5/14D5: 16A 150V ............................................................................................ 72 6 contacts 103W3: 5A 32V ............................................................................................. 76 106 - 10E6/10D6: 7A 32V ............................................................................................. 80 10E98/10D98: 7A 50V ............................................................................................. 84 6 contacts + ground 147 - 14E7: 16A 300V ............................................................................................ 88 7 contacts 10E7/10D7: 7A 50V ............................................................................................. 92 8 contacts 128: 10A 80V ............................................................................................. 96 12E8/12D8: 6A 32V ............................................................................................. 100 10 contacts 1210 - 12E10/12D10: 6A 50V ............................................................................................. 104 12 contacts 1412: 10A 63V ............................................................................................. 108 14E12/14D12: 4A 50V ............................................................................................. 112 14 contacts 12E14/12D14: 5A 32V ............................................................................................. 116 15 contacts 14E15/14D15: 4A 50V ............................................................................................. 120 18 contacts 14E18/14D18: 5A 50V ............................................................................................. 124 19 contacts 1419 - 14E19/14D19: 5A 32V ............................................................................................. 128 23 contacts 1823: 9A 63V ............................................................................................. 132 32 contacts 1832: 4A 32V ............................................................................................. 136 14 © 2011 – SOURIAU OUTDOOR (black outer jacket) INDOOR Cable assembly Souriau provides connectors in various applications for more than 90 years in the most extreme environment. Being conscious about the diffi culty to fi nd a quick and a reliable harness manufacturer, we decided years ago to start in house cable assembly production. It allows customers to reduce the number of suppliers, and to take advantage of the "best in class" quality of the Souriau group. Overmoulding is a process that further enhances the sealing properties of the UTS range, especially over many years of use. Overmoulding provides the opportunity to change the cable exit from straight through 90 degrees and avoid any stress on the cable terminated to the connector. Also, as the wires are encapsulated inside the moulding, a barrier is created which prevents from any liquid from entering the equipment through the connector if the cable jacket is breached. UV resistance Ambient temperature PVC PUR PTFE FEP SILICON TPE 70°C Static installation Static installation Static installation Static installation Static installation Static or dynamic installation Wet Cleaner, Immerged chlorine 90°C 180°C 205°C 260°C Chemical agression How to choose the outer jacket material UTS Series Mechanics © 2011 – SOURIAU 15 Overmolding description Discrete connector Overmoulded connector Compound Thermoplastic insert O ring Overmolding adapter PVC or PUR overmolding ...water ingress unhampered, leading to damage. ...prevents water ingress via capillary action. If cable jacket is breached... If cable jacket is breached...   UTS Series Mechanics Mechanics 16 © 2011 – SOURIAU UTS Series Mechanics Harnesses Overmoulded harnesses, straight ending Connector type Number of ways Voltage Current UL Current IEC Harmonised cable part number* Part number (length: 1m.) Male Female UTS standard 2+PE 600 V 44 A 40 A HO5 VV - F 3Gg10 HAUTS0V142G1PST100 HAUTS0V142G1SST100 2+PE 500 V 10 A 16 A HO5 VV - F 3x1.5 HAUTS0V103PST100 HAUTS0V103SST100 3+PE 500 V 10 A 16 A HO5 VV - F 3G1.5 HAUTS0V103PEPST100 HAUTS0V103PESST100 3+PE 250 V 24 A 32 A HO5 VV - F 40G0.5 HAUTS0V183G1PST100 HAUTS0V183G1SST100 3+PE 500 V 10 A 16 A HO5 VV - F 4G1.5 HAUTS0V124PEPST100 HAUTS0V124PESST100 4 500 V 10 A 13 A HO5 VV - F 4x1.5 HAUTS0V104PST100 HAUTS0V104SST100 3 500 V 10 A 5 A HO5 VV - F 7G0.5 HAUTS0V103W3PST100 HAUTS0V103W3SST100 6 250 V 5 A 7 A HO5 VV - F 7x0.5 HAUTS0V106PST100 HAUTS0V106SST100 6+PE 500 V 10 A 16 A HO5 VV - F 7G1.5 HAUTS0V147PEPST100 HAUTS0V147PESST100 8 500 V 10 A 10 A HO5 VV - F 8x1.5 HAUTS0V128PST100 HAUTS0V128SST100 10 250 V 5 A 6 A HO5 VV - F 10G0.5 HAUTS0V1210PST100 HAUTS0V1210SST100 12 500 V 10 A 10 A HO5 VV - F 12x1.5 HAUTS0V1412PST100 HAUTS0V1412SST100 19 250 V 5 A 5 A HO5 VV - F 21G0.5 HAUTS0V1419PST100 HAUTS0V1419SST100 23 500 V 10 A 9 A HO5 VV - F 25G1.5 HAUTS0V1823PST100 HAUTS0V1823SST100 32 250 V 5 A 4 A HO5 VV - F 40G0.5 HAUTS0V1832PST100 HAUTS0V1832SST100 UTS Hi seal 2 250 V 7 A 7 A H05 VV - F 2x0.5 HAUTS0V8E2PST100 HAUTS0V8E2SST100 2 650 V 13 A 16 A HO5 VV - F 2x1.5 HAUTS0V12E2PST100 HAUTS0V12E2SST100 3 250 V 7 A 7 A HO5 VV - F 3x0.5 HAUTS0V8E3PST100 HAUTS0V8E3SST100 3 250 V 7 A 7 A HO5 VV - F 3x0.5 HAUTS0V8E3APST100 HAUTS0V8E3ASST100 3 250 V 7 A 7 A HO5 VV - F 3x0.5 HAUTS0V8E33PST100 HAUTS0V8E33SST100 3 650 V 13 A 16 A HO5 VV - F 3x1.5 HAUTS0V12E3PST100 HAUTS0V12E3SST100 4 250 V 7 A 7 A HO5 VV - F 4x0.5 HAUTS0V8E4PST100 HAUTS0V8E4SST100 5 650 V 12 A 16 A HO5 VV - F 4G1.5 HAUTS0V14E5PST100 HAUTS0V14E5SST100 6 250 V 5 A 7 A HO5 VV - F 7x0.5 HAUTS0V10E6PST100 HAUTS0V10E6SST100 6 250 V 6 A 7 A HO5 VV - F 7x0.5 HAUTS0V10E98PST100 HAUTS0V10E98SST100 6+PE 500 V 10 A 16 A HO5 VV - F 7G1.5 HAUTS0V14E7PEPST100 HAUTS0V14E7PESST100 7 250 V 6 A 7 A HO5 VV - F 7x0.5 HAUTS0V10E7PST100 HAUTS0V10E7SST100 8 250 V 5 A 6 A HO5 VV - F 10G0.5 HAUTS0V12E8PST100 HAUTS0V12E8SST100 10 250 V 5 A 6 A HO5 VV - F 10G0.5 HAUTS0V12E10PST100 HAUTS0V12E10SST100 12 250 V 5 A 4 A HO5 VV - F 12G0.5 HAUTS0V14E12PST100 HAUTS0V14E12SST100 14 250 V 5 A 5 A HO5 VV - F 14G0.5 HAUTS0V12E14PST100 HAUTS0V12E14SST100 15 650 V 12 A 4 A HO5 VV - F 18G0.5 HAUTS0V14E15PST100 HAUTS0V14E15SST100 18 250 V 4 A 4 A HO5 VV - F 18G0.5 HAUTS0V14E18PST100 HAUTS0V14E18SST100 19 250 V 4 A 5 A HO5 VV - F 40G0.5 HAUTS0V14E19PST100 HAUTS0V14E19SST100 * see page 18 3 m & 5 m version available on demand Eg: 3m HAUTS0V...300 5m HAUTS0V...500 © 2011 – SOURIAU 17 UTS Series Mechanics Harnesses Overmoulded harnesses, right angle ending Connector type Number of ways Voltage Current UL Current IEC Harmonised cable part number* Part number (length: 1m.) Male Female UTS standard 2+PE 600 V 44 A 40 A HO5 VV - F 3Gg10 HAUTS0V142G1PRA100 HAUTS0V142G1SRA100 2+PE 500 V 10 A 16 A HO5 VV - F 3x1.5 HAUTS0V103PRA100 HAUTS0V103SRA100 3+PE 500 V 10 A 16 A HO5 VV - F 3G1.5 HAUTS0V183G1PRA100 HAUTS0V183G1SRA100 3+PE 250 V 24 A 32 A HO5 VV - F 40G0.5 HAUTS0V183G1PRA100 HAUTS0V183G1SRA100 3+PE 500 V 10 A 16 A HO5 VV - F 4G1.5 HAUTS0V124PEPRA100 HAUTS0V124PESRA100 4 500 V 10 A 13 A HO5 VV - F 4x1.5 HAUTS0V104PRA100 HAUTS0V104SRA100 3 500 V 10 A 5 A HO5 VV - F 7G0.5 HAUTS0V103W3PRA100 HAUTS0V103W3SRA100 6 250 V 5 A 7 A HO5 VV - F 7x0.5 HAUTS0V106PRA100 HAUTS0V106SRA100 6+PE 500 V 10 A 16 A HO5 VV - F 7G1.5 HAUTS0V147PEPRA100 HAUTS0V147PESRA100 8 500 V 10 A 10 A HO5 VV - F 8x1.5 HAUTS0V128PRA100 HAUTS0V128SRA100 10 250 V 5 A 6 A HO5 VV - F 10G0.5 HAUTS0V1210PRA100 HAUTS0V1210SRA100 12 500 V 10 A 10 A HO5 VV - F 12x1.5 HAUTS0V1412PRA100 HAUTS0V1412SRA100 19 250 V 5 A 5 A HO5 VV - F 21G0.5 HAUTS0V1419PRA100 HAUTS0V1419SRA100 23 500 V 10 A 9 A HO5 VV - F 25G1.5 HAUTS0V1823PRA100 HAUTS0V1823SRA100 32 250 V 5 A 4 A HO5 VV - F 40G0.5 HAUTS0V1832PRA100 HAUTS0V1832SRA100 UTS Hi seal 2 250 V 7 A 7 A H05 VV - F 2x0.5 HAUTS0V8E2PRA100 HAUTS0V8E2SRA100 2 650 V 13 A 16 A HO5 VV - F 2x1.5 HAUTS0V12E2PRA100 HAUTS0V12E2SRA100 3 250 V 7 A 7 A HO5 VV - F 3x0.5 HAUTS0V8E3PRA100 HAUTS0V8E3SRA100 3 250 V 7 A 7 A HO5 VV - F 3x0.5 HAUTS0V8E3APRA100 HAUTS0V8E3ASRA100 3 250 V 7 A 7 A HO5 VV - F 3x0.5 HAUTS0V8E33PRA100 HAUTS0V8E33SRA100 3 650 V 13 A 16 A HO5 VV - F 3x1.5 HAUTS0V12E3PRA100 HAUTS0V12E3SRA100 4 250 V 7 A 7 A HO5 VV - F 4x0.5 HAUTS0V8E4PRA100 HAUTS0V8E4SRA100 5 650 V 12 A 16 A HO5 VV - F 4G1.5 HAUTS0V14E5PRA100 HAUTS0V14E5SRA100 6 250 V 5 A 7 A HO5 VV - F 7x0.5 HAUTS0V10E6PRA100 HAUTS0V10E6SRA100 6 250 V 6 A 7 A HO5 VV - F 7x0.5 HAUTS0V10E98PRA100 HAUTS0V10E98SRA100 6+PE 500 V 10 A 16 A HO5 VV - F 7G1.5 HAUTS0V14E7PEPRA100 HAUTS0V14E7PESRA100 7 250 V 6 A 7 A HO5 VV - F 7x0.5 HAUTS0V10E7PRA100 HAUTS0V10E7SRA100 8 250 V 5 A 6 A HO5 VV - F 10G0.5 HAUTS0V12E8PRA100 HAUTS0V12E8SRA100 10 250 V 5 A 6 A HO5 VV - F 10G0.5 HAUTS0V12E10PRA100 HAUTS0V12E10SRA100 12 250 V 5 A 4 A HO5 VV - F 12G0.5 HAUTS0V14E12PRA100 HAUTS0V14E12SRA100 14 250 V 5 A 5 A HO5 VV - F 14G0.5 HAUTS0V12E14PRA100 HAUTS0V12E14SRA100 15 650 V 12 A 4 A HO5 VV - F 18G0.5 HAUTS0V14E15PRA100 HAUTS0V14E15SRA100 18 250 V 4 A 4 A HO5 VV - F 18G0.5 HAUTS0V14E18PRA100 HAUTS0V14E18SRA100 19 250 V 4 A 5 A HO5 VV - F 40G0.5 HAUTS0V14E19PRA100 HAUTS0V14E19SRA100 * see page 18 3 m & 5 m version available on demand Eg: 3m HAUTS0V...300 5m HAUTS0V...500 Mechanics 18 © 2011 – SOURIAU UTS Series Mechanics Standardization of European cable - DIN VDE 0281/DIN VDE 0282/DIN VDE 0292 1. Basic type 2. Working voltage 3. Insulating 4. Sheathcladding material 5. Special features 6. Conductor types 7. Number of conductors 8. Protective conductor 9. Conductor crosssectional H: Harmonized Type 03: 300/300 V. V: PVC V: PVC H: Ribbon cable, separable U: Single wire X: Without protective conductor Area specifi ed in mm2 A: National Type 05: 300/500 V. R: Rubber R: Rubber H2: Ribbon cable non-separable R: Multi-wire G: With protective conductor 07: 450/750 V. S: Silicone Rubber N: Cloroprene Rubber K: Fine wire (permanently installed) J: Glass-fi lament braiding F: Fine wire (fl exible) T: Textile braiding H: Super fi ne wire Y: Tinsel strand 1 2 3 4 5 6 7 8 9 Harmonized wire coding system Example: Harmonized type, 300/500V, PVC insulating, PVC sheath- cladding, Fine wire, 3x1.5 cross-sectional: H05VVF3x1.5 Cable information Range of temperature: Occasional fl exing: -5°C up to +70°C Fixed installation: -40°C up to +80°C Rated voltage: U0/U: 300/500 V Wire section : Arrangement with #16 contact: wire section 1.5 mm² Arrangement with #20 contact: wire section 0.5 mm² Harmonized reference: H05 VVF XX © 2011 – SOURIAU 19 UTS Series Mechanics Standardization of American cable Nomenclature Key Defi nitions of Cable Types S: Service Grade (also means extra hard service when not followed by J, V, or P) J: Hard Service V: Vacuum cleaner cord (also light duty cable) P: Parallel cord (also known as zip cord) – Always light duty E: Thermoplastic Elastomer (UL/NEC designation ONLY) O: Oil Resistant* T: Thermoplastic W: Outdoor-includes sunlight resistant jacket and wet location rated conductors (formerly "W-A") H: Heater cable VW-1: Flame retardant FT2: Flame retardant SVT: Thermoplastic insulated vacuum cleaner cord, with or without 3rd conductor for grounding purposes; 300V. (PVC) SJT: Junior hard service, thermoplastic insulated conductors and jacket. 300V. (PVC) SJTW: Same as SJT except outdoor rated. (PVC) SJTO: Same as SJT but oil resistant outer jacket. (PVC) SJTOW: Same as SJTO except outdoor rated. (PVC) ST: Hard service cord with all thermoplastic construction, 600V. (PVC) STW: Same as ST except outdoor rated. (PVC) STO: Same as ST but with oil resistant outer jacket. (PVC) STOW: Same as STO except outdoor rated. (PVC) Mechanics 20 © 2011 – SOURIAU OR OR WITH Layout Specifi cations UTS Series 8E2/8D2 Contact type Connector type Backshell Part number Male insert Female insert Handsolder electrical contacts loaded Square fl ange receptacle Without (Fig.1) UTS08E2P UTS08E2S Plug Without (Fig.6) UTS68E2P UTS68E2S Cable gland (Fig.7) UTS6JC8E2P UTS6JC8E2S Jam nut receptacle Without (Fig.3) UTS78E2P UTS78E2S PCB contacts loaded Square fl ange receptacle Without (Fig.2) UTS08D2P UTS08D2S Jam nut receptacle with stand off and with hold down clips Without (Fig.5) UTS78D2P32 UTS78D2S32 Jam nut receptacle with stand off and withouthold down clip Without (Fig.4) UTS78D2P UTS78D2S Sealed unmated © 2011 – SOURIAU 21 Dimensions Note: all dimensions are in mm UTS Series 8E2/8D2 Square fl ange receptacle - UTS0 Front view 11.7 11.7 20.7 Ø12 Ø12 15.3 2.4 2.4 Ø3.2 7.5 7.5 7.8 Fig. 1 Fig. 2 Jam nut receptacle - UTS7 Front view 24.2 24.2 18 Ø12 3.5 3.4 Fig. 3 Fig. 4 Fig. 5 18 4.2 Ø12 3.5 3.4 18 Ø12 3.5 3.4 Plug - UTS6 25.3 54 Fig. 7 Fig. 6 Ø22.5 Mated connector length 61.1 66.6 UTS7 UTS0 Drilling pattern 1.5 Ø13.5 Ø22 Ø17.7 15° 15° Ø4 Ø3.1 1.5 Panel cut out 15.3 15.3 Ø3.3 Square fl ange receptacle - UTS0 Jam nut receptacle - UTS7 13.7 14.6 Front mounting Ø12.5 Rear mounting Ø14.5 Mechanics 2 contacts 7A/32V per IEC 61984 22 © 2011 – SOURIAU Jam nut sealing caps Square fl ange sealing cap Plug protective cap Accessories Electrical characteristics UL 7A 250V UL94 HB CSA 7A 250V UL94 HB IEC 7A 32V 1.5kV 3 UTS 8E2/8D2 derating curves Test conditions Contact used: Machined contacts Wires used: 0.518mm² 0 20 40 60 80 100 120 0 6 10 18 Current (A) Ambient Operating Temperature (°C) 12 14 16 2 4 8 Metal terminal IP40 Part number UTS8DCGE Part number UTS68C Metal terminal Part number UTS8DCG Part number UTS8DCGR UTS Series 8E2/8D2 Part numbers Receptacle cap Plug cap 85005585A 85005594 Plastic protective cap Part numbers / neoprene UTFD11B Gasket Current use Limited use Not recommended use © 2011 – SOURIAU 23 UTS Series 8E2/8D2 Mechanics 24 © 2011 – SOURIAU OR WITH OR Layout UTS Series 12E2/12D2 Specifi cations Contact type Connector type Backshell Part number Male insert Female insert Handsolder electrical contacts loaded Square fl ange receptacle Without (Fig.1) UTS012E2P UTS012E2S Plug Without (Fig.6) UTS612E2P UTS612E2S Cable gland (Fig.7) UTS6JC12E2P UTS6JC12E2S Jam nut receptacle Without (Fig.3) UTS712E2P UTS712E2S PCB contacts loaded Square fl ange receptacle Without (Fig.2) UTS012D2P UTS012D2S Jam nut receptacle with stand off and with hold down clips Without (Fig.5) UTS712D2P32 UTS712D2S32 Jam nut receptacle with stand off and without hold down clip Without (Fig.4) UTS712D2P UTS712D2S Sealed unmated © 2011 – SOURIAU 25 UTS Series 12E2/12D2 Dimensions Note: all dimensions are in mm 2 contacts 16A/150V per IEC 61984 Square fl ange receptacle - UTS0 Front view 11.7 11.7 26.4 Ø19 Ø19 20.8 2.4 2.4 Ø3.2 7.5 7.5 7.8 Fig. 1 Fig. 2 Plug - UTS6 Mated connector length 25.3 66.7 75.3 81.7 Fig. 7 Fig. 6 Ø30.1 UTS7 UTS0 Panel cut out Drilling pattern 20.8 15.3 Ø3.3 Jam nut receptacle - UTS7 21.4 22.7 2.3 Ø22 Ø30.5 Ø26.2 30° 68° 10 Ø3.1 2.3 1.4 Square fl ange receptacle - UTS0 22° Front mounting Ø18.3 Rear mounting Ø22.3 Jam nut receptacle - UTS7 Front view 27.2 31.9 18 18 18 Ø19 Ø19 Ø19 3.5 3.5 3.5 3 3 3 4.2 Fig. 3 Fig. 4 Fig. 5 Mechanics 26 © 2011 – SOURIAU Metal terminal UTS Series 12E2/12D2 Accessories Metal terminal 0 20 40 60 80 100 120 0 10 20 30 Current (A) Ambient Operating Temper