0433751001 Datasheet - Molex - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Autres documentations :

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This document was generated on 01/08/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 43375-1001 Status: Active Overview: Sabre™ Power Connector Description: Sabre™ Crimp Terminal, Female, Double 18 AWG, 4.57mm Max. Insulation Diameter, Reel Packaged, Tin (Sn) Plated Brass Contact with TPA Documents: Drawing (PDF) Product Literature (PDF) RoHS Certificate of Compliance (PDF) General Product Family Crimp Terminals Series 43375 Application Power Comments For double crimping of 18 AWG wire in a side-by-side orientation. Terminal mates to 3.18mm wide x 0.51mm ) thick flat blade PC tab. Allows 44441 receptacle housings to comply with the UL1977 finger proof access requirement Crimp Quality Equipment Yes MolexKits Yes Overview Sabre™ Power Connector Product Literature Order No 987650-5662 Product Name Sabre™ UPC 800754365994 Physical Durability (mating cycles max) 25 Gender Female Material - Metal Brass Material - Plating Mating Tin Material - Plating Termination Tin Net Weight 0.360/g Packaging Type Reel Plating min - Mating 0.508μm Plating min - Termination 0.508μm Termination Interface: Style Crimp or Compression Wire Insulation Diameter 4.57mm max. Wire Size AWG 14, 16, 18+18 Wire Size mm² N/A Electrical Current - Maximum per Contact 18A Voltage - Maximum 600V Material Info Reference - Drawing Numbers Product Specification RPSX-44441-001 Sales Drawing SD-43375-1001 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 43375Series Mates With 43178 Male Crimp Terminals Use With 44441 Receptacle Housings Application Tooling | FAQ Tooling specifications and manuals are found by selecting the products below. Crimp Height Specifications are then contained in the Application Tooling Specification document. Global Description Product # Manual Extraction Tool 0638130500 Terminator Die - Doubles 0638405200 Hand Crimp Tool for Flat Blade Crimp Terminal 0638117300 Extraction Tool 0638132700 Mini-Mac™ Applicator 0638916100 Mini-Mac™ Applicator, For Narrow Insulation Crimp 0638917000 This document was generated on 01/08/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 01/22/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 43031-0002 Status: Active Overview: Micro-Fit 3.0™ Connectors Description: Micro-Fit 3.0™ Crimp Terminal, Male, with Gold (Au) Plated Tin/Brass Alloy Contact, 20-24 AWG, Reel Documents: Drawing (PDF) RoHS Certificate of Compliance (PDF) Product Specification PS-43045 (PDF) Product Literature (PDF) Test Summary TS-43045-002 (PDF) General Product Family Crimp Terminals Series 43031 Application Power Crimp Quality Equipment Yes Overview Micro-Fit 3.0™ Connectors Packaging Alternative 43031-0008 (Loose) Product Literature Order No 987650-5984 Product Name Micro-Fit 3.0™ UPC 800754369411 Physical Gender Male Material - Metal Phosphor Bronze Material - Plating Mating Gold Material - Plating Termination Tin Net Weight 0.061/g Packaging Type Reel Plating min - Mating 0.381μm Plating min - Termination 2.540μm Termination Interface: Style Crimp or Compression Wire Insulation Diameter 1.85mm max. Wire Size AWG 20, 22, 24 Wire Size mm² N/A Material Info Reference - Drawing Numbers Product Specification PS-43045, RPS-43045-003, RPS-43045-004 Sales Drawing SD-43031-**** Test Summary TS-43045-002 Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 43031Series Mates With 43030 Application Tooling | FAQ Tooling specifications and manuals are found by selecting the products below. Crimp Height Specifications are then contained in the Application Tooling Specification document. Global Description Product # Extraction Tool 0011030043 Insertion Tool for Crimp Terminal 0638120800 Hand Crimp Tool 0638190000 FineAdjust™ Applicator for Insulation OD 1.30-1.85mm - 20-24 AWG 0639004500 FineAdjust™ Applicator for 0639018800 Insulation OD 1.10-1.30mm - 20-24 AWG FineAdjust™ Applicator for Insulation OD 0.91-1.09mm - 20-24 AWG 0639018900 T2 Terminator™ for insulation OD 1.30-1.85mm - 20-24 AWG 0639104500 T2 Terminator™ for insulation OD 1.10-1.30mm - 20-24 AWG 0639118800 T2 Terminator™ for insulation OD 0.91-1.09mm - 20-24 AWG 0639118900 This document was generated on 01/22/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION This document was generated on 04/14/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION Part Number: 39-28-8060 Status: Active Overview: Mini-Fit Jr.™ Power Connectors Description: Mini-Fit® Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 6 Circuits, PA Polyamide Nylon 6/6 94V-0, Tin (Sn) Plating, without Drain Holes Documents: 3D Model Packaging Specification PK-5566-003 (PDF) Drawing (PDF) Test Summary TS-5556-002 (PDF) Product Specification PS-5556-001 (PDF) RoHS Certificate of Compliance (PDF) Agency Certification CSA LR19980 UL E29179 General Product Family PCB Headers Series 5566 Application Power, Wire-to-Board Comments The 5566 header should be used with standard Mini- Fit® female terminals. If increased amperage of up to 13A per circuit is needed, please consider using the Mini-Fit® Plus HCS family 45750 terminals with 46015 headers; . See Molex Product specification PS-5666-001 for current de-rating information. Overview Mini-Fit Jr.™ Power Connectors Product Name Mini-Fit Jr.™ UPC 800753580732 Physical Breakaway No Circuits (Loaded) 6 Circuits (maximum) 6 Color - Resin Natural Durability (mating cycles max) 30 First Mate / Last Break No Flammability 94V-0 Glow-Wire Compliant No Guide to Mating Part No Keying to Mating Part None Lock to Mating Part Yes Material - Metal Brass Material - Plating Mating Tin Material - Plating Termination Tin Material - Resin Nylon Net Weight 1.778/g Number of Rows 2 Orientation Vertical PC Tail Length 3.50mm PCB Locator Yes PCB Retention None PCB Thickness - Recommended 1.60mm Packaging Type Bag Pitch - Mating Interface 4.20mm Pitch - Termination Interface 4.20mm Polarized to Mating Part Yes Series image - Reference only EU RoHS China RoHS ELV and RoHS Compliant REACH SVHC Contains SVHC: No Low-Halogen Status Low-Halogen Need more information on product environmental compliance? Email productcompliance@molex.com For a multiple part number RoHS Certificate of Compliance, click here Please visit the Contact Us section for any non-product compliance questions. Search Parts in this Series 5566Series Mates With 5557 Mini-Fit Jr.™ Receptacle Housing Polarized to PCB Yes Shrouded Fully Stackable No Surface Mount Compatible (SMC) No Temperature Range - Operating -40°C to +105°C Termination Interface: Style Through Hole Electrical Current - Maximum per Contact 9A Voltage - Maximum 600V Solder Process Data Duration at Max. Process Temperature (seconds) 5 Lead-free Process Capability Wave Capable (TH only) Max. Cycles at Max. Process Temperature 1 Process Temperature max. C 260 Material Info Old Part Number 5566-06A-210 Reference - Drawing Numbers Packaging Specification PK-5566-003 Product Specification PS-5556-001, RPS-5557-036, RPS-5557-058 Sales Drawing SD-5566-002 Test Summary TS-5556-002 This document was generated on 04/14/2014 PLEASE CHECK WWW.MOLEX.COM FOR LATEST PART INFORMATION 1. General description The UHF EPCglobal Generation 2 standard allows the commercialized provision of mass adoption of UHF RFID technology for passive smart tags and labels. Main fields of applications are supply chain management and logistics for worldwide use with special consideration of European, US and Chinese frequencies to ensure that operating distances of several meters can be realized. The G2X is a dedicated chip for passive, intelligent tags and labels supporting the EPCglobal Class 1 Generation 2 UHF RFID standard. It is especially suited for applications where operating distances of several meters and high anti-collision rates are required. The G2X is a product out of the NXP Semiconductors UCODE product family. The entire UCODE product family offers anti-collision and collision arbitration functionality. This allows a reader to simultaneously operate multiple labels / tags within its antenna field. A UCODE G2X based label/ tag requires no external power supply. Its contact-less interface generates the power supply via the antenna circuit by propagative energy transmission from the interrogator (reader), while the system clock is generated by an on-chip oscillator. Data transmitted from interrogator to label/tag is demodulated by the interface, and it also modulates the interrogator’s electromagnetic field for data transmission from label/tag to interrogator. A label/tag can be operated without the need for line of sight or battery, as long as it is connected to a dedicated antenna for the targeted frequency range. When the label/tag is within the interrogator’s operating range, the high-speed wireless interface allows data transmission in both directions. In addition to the EPC specifications the G2X offers an integrated EAS (Electronic Article Surveillance) feature and read protection of the memory content. On top of the specification of the G2XL the G2XM offers 512-bit of user memory. SL3ICS1002/1202 UCODE G2XM and G2XL Rev. 3.8 — 11 November 2013 139038 Product data sheet COMPANY PUBLIC 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 2 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 2. Features and benefits 2.1 Key features  512-bit user memory (G2XM only)  240-bit of EPC memory  64-bit tag identifier (TID) including 32-bit unique serial number  Memory read protection  EAS (Electronic Article Surveillance) command  Calibrate command  32-bit kill password to permanently disable the tag  32-bit access password to allow a transition into the secured transmission state  Broad international operating frequency: from 840 MHz to 960 MHz  Long read/write ranges due to extremely low power design  Reliable operation of multiple tags due to advanced anti-collision  Forward link: 40-160 kbit/s  Return link: 40-640 kbit/s 2.2 Key benefits  High sensitivity provides long read range  Low Q-factor for consistent performance on different materials  Improved interference suppression for reliable operation in multi-reader environment  Large input capacitance for ease of assembly and high assembly yield  Highly advanced anti-collision resulting in highest identification speed  Reliable and robust RFID technology suitable for dense reader and noisy environments 2.3 Custom commands  EAS Alarm Enables the UHF RFID tag to be used as EAS tag without the need for a backend data base.  Read Protect Protects all memory content including CRC16 from unauthorized reading.  Calibrate Activates permanent back-scatter in order to evaluate the tag-to-reader performance. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 3 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 3. Applications  Supply chain management  Item level tagging  Asset management  Container identification  Pallet and case tracking  Product authentication Outside above mentioned applications, please contact NXP Semiconductors for support. 4. Ordering information Table 1. Ordering information G2XM Type number Package Name Description Version SL3ICS1002FUG/V7AF Wafer Bumped die on sawn wafer - SL3S1002FTB1 XSON3 plastic extremely thin small outline package;3 terminals; body 1 x 1.45 x 0,5 mm SOT1122 Table 2. Ordering information G2XL Type number Package Name Description Version SL3ICS1202FUG/V7AF Wafer Bumped die on sawn wafer - SL3S1202FTB1 XSON3 plastic extremely thin small outline package;3 terminals; body 1 x 1.45 x 0,5 mm SOT1122 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 4 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 5. Block diagram The SL3ICS1002/1202 IC consists of three major blocks: - Analog RF Interface - Digital Controller - EEPROM The analog part provides stable supply voltage and demodulates data received from the reader for being processed by the digital part. Further, the modulation transistor of the analog part transmits data back to the reader. The digital section includes the state machines, processes the protocol and handles communication with the EEPROM, which contains the EPC and the user data. Fig 1. Block diagram of G2X IC 001aai335 MOD DEMOD VREG VDD data in data out R/W ANALOG RF INTERFACE PAD PAD RECT DIGITAL CONTROL ANTENNA ANTICOLLISION READ/WRITE CONTROL ACCESS CONTROL EEPROM INTERFACE CONTROL RF INTERFACE CONTROL EEPROM MEMORY SEQUENCER CHARGE PUMP 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 5 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 6. Wafer layout and pinning information 6.1 Wafer layout (1) X-scribe line width: 56.4 m (2) Y-scribe line width: 56.4 m (3) Chip step, x-length: 488.0 m (4) Chip step, y-length: 470,0 m (5) Bump to bump distance X (TP1 - RFN): 351,0 m (6) Bump to bump distance Y (RFN - RFP): 333,0 m (7) Distance bump to metal sealring X: 40,3 m (8) Distance bump to metal sealring Y: 40,3 m Bump size X x Y: 60 m x 60 m Fig 2. Wafer layout and pinning information not to scale! 001aai346 (1) (7) (2) (8) (5) (6) (4) (3) Y X TP2 TP1 RFN RFP 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 6 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 7. Package outline Fig 3. Package outline SOT1122 Outline References version European projection Issue date IEC JEDEC JEITA SOT1122 MO-252 sot1122_po Unit mm max nom min 0.50 0.04 0.55 0.425 0.30 0.25 0.22 0.35 0.30 0.27 A(1) Dimensions Notes 1. Dimension A is including plating thickness. 2. Can be visible in some manufacturing processes. SOT1122 A1 D 1.50 1.45 1.40 1.05 1.00 0.95 E e e1 0.55 0.50 0.47 0.45 0.40 0.37 b b1 L L1 09-10-09 XSON3: plastic extremely thin small outline package; no leads; 3 terminals; body 1 x 1.45 x 0.5 mm D E e1 e A1 b1 L1 L e1 0 1 2 mm scale 3 1 2 b 4× (2) 4× (2) A pin 1 indication type code terminal 1 index area 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 7 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 3. Pin description of SOT1122 Symbol Pin Description RFP 1 Ungrouded antenna connector RFN 2 Grounded antenna connector n.c. 3 not connected Table 4. SOT1122 Marking Type Type code (Marking) Comment SL3S1202FTB1 UL UCODE G2XL SL3S1002FTB1 UM UCODE G2XM 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 8 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 8. Mechanical specification 8.1 Wafer specification See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**”. 8.1.1 Wafer • Designation: each wafer is scribed with batch number and wafer number • Diameter: 200 mm (8”) • Thickness: 150 m ± 15 m • Number of pads 4 • Pad location: non diagonal/ placed in chip corners • Distance pad to pad RFN-RFP 333.0 μm • Distance pad to pad TP1-RFN: 351.0 μm • Process: CMOS 0.14 μm • Batch size: 25 wafers • Dies per wafer: 120.000 8.1.2 Wafer backside • Material: Si • Treatment: ground and stress release • Roughness: Ra max. 0.5 m, Rt max. 5 m 8.1.3 Chip dimensions • Die size without scribe: 0.414 mm x 0.432 mm = 0.178 mm2 • Scribe line width: x-dimension:56.4 m (width is measured on top metal layer) y-dimension: 56.4 m (width is measured on top metal layer) 8.1.4 Passivation on front • Type Sandwich structure • Material: PE-Nitride (on top) • Thickness: 1.75 m total thickness of passivation 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 9 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 8.1.5 Au bump • Bump material: > 99.9% pure Au • Bump hardness: 35 – 80 HV 0.005 • Bump shear strength: > 70 MPa • Bump height: 18 m • Bump height uniformity: – within a die: ± 2 m – within a wafer: ± 3 m – wafer to wafer: ± 4 m • Bump flatness: ± 1.5 m • Bump size: – RFP, RFN 60 x 60 m – TP1, TP2 60 x 60 m – Bump size variation: ± 5 m • Under bump metallization: sputtered TiW 8.1.6 Fail die identification No inkdots are applied to the wafer. Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of mechanical/visual inspection. See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**” 8.1.7 Map file distribution See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**” 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 10 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 9. Limiting values [1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the Operating Conditions and Electrical Characteristics section of this specification is not implied. [2] This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. [3] For ESD measurement, the die chip has been mounted into a CDIP20 package. Table 5. Limiting values[1][2] In accordance with the Absolute Maximum Rating System (IEC 60134) Voltages are referenced to RFN Symbol Parameter Conditions Min Max Unit Die Tstg storage temperature range -55 +125 C Toper operating temperature -40 +85 C VESD electrostatic discharge voltage Human body model [3] - 2 kV SOT1122 Tstg storage temperature range -55 +125 C Ptot total power dissipation - 30 mW Toper operating temperature -40 +85 C VESD electrostatic discharge voltage Human body model - 2 kV 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 11 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 10. Characteristics 10.1 Wafer characteristics [1] Power to process a Query command [2] Measured with a 50  source impedance [3] At minimum operating power [4] Values measured for a 40 kHz phase reserval command under matched conditions 10.2 Package characteristics [1] Measured with network analyzer at 915 MHz; values at 0.5 dBm after peakmax of on-set of die, measured in the center of the pads. Table 6. Wafer characteristics Symbol Parameter Conditions Min Typ Max Unit Memory characteristics tRET EEPROM data retention Tamb  55 C 50 - - year NWE EEPROM write endurance Tamb  55 C 100000 - - cycle Interface characteristics Ptot total power dissipation - 30 mW foper operating frequency 840 - 960 MHz Pmin minimum operating power supply [1][2] - -15 - dBm Ci input capacitance (parallel) [3] - 0.88 - pF Q quality factor (Im (Zchip) / Re (Zchip)) [3] - 9 - - Z impedance (915 MHz) - 22 - j195 -  - modulated jammer suppression 1.0 MHz [4] - - 4 - dB - unmodulated jammer suppression 1.0 MHz [4] - - 4 - dB Table 7. Package interface characteristics Symbol Parameter Conditions Min Typ Max Unit Interface characteristics SOT1122 Ci input capacitance (parallel) [1] - 1.02 - pF Z SOT1122 impedance (915 MHz) - 18.6 - j171.2 -  139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 12 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 11. Packing information 11.1 Wafer See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**”. 11.2 SOT1122 Part orientation T1. For details please refer to http://www.standardics.nxp.com/packaging/packing/pdf/sot886.t1.t4.pdf. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 13 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 12. Functional description 12.1 Power transfer The interrogator provides an RF field that powers the tag, equipped with a UCODE G2X. The antenna transforms the impedance of free space to the chip input impedance in order to get the maximum possible power for the G2X on the tag. The RF field, which is oscillating on the operating frequency provided by the interrogator, is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC. The antenna that is attached to the chip may use a DC connection between the two antenna pads. Therefore the G2X also enables loop antenna design. Possible examples of supported antenna structures can be found in the reference antenna design guide. 12.2 Data transfer 12.2.1 Reader to G2X Link An interrogator transmits information to the UCODE G2X by modulating an RF signal in the 840 MHz - 960 MHz frequency range. The G2X receives both information and operating energy from this RF signal. Tags are passive, meaning that they receive all of their operating energy from the interrogator's RF waveform. An interrogator is using a fixed modulation and data rate for the duration of at least an inventory round. It communicates to the G2X by modulating an RF carrier using DSB-ASK, SSB-ASK or PR-ASK with PIE encoding. For further details refer to Section 17, Ref. 1, section 6.3.1.2. Interrogator-to-tag (R=>T) communications. 12.2.2 G2X to reader Link An interrogator receives information from the UCODE G2X by transmitting a continuous-wave RF signal to the tag; the G2X responds by modulating the reflection coefficient of its antenna, thereby generating modulated sidebands used to backscatter an information signal to the interrogator. The system is a reader talks first (RTF) system, meaning that a G2X modulates its antenna reflection coefficient with an information signal only after being directed by the interrogator. G2X backscatter is a combination of ASK and PSK modulation depending on the tuning and bias point. The backscattered data is either modulated with FM0 baseband or Miller sub carrier. For further details refer to Section 17, Ref. 1, section 6.3.1.3. tag-to-interrogator (T=>R) communications. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 14 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 12.3 Operating distances RFID tags based on the UCODE G2X silicon may achieve maximum operating distances according the following formula: (1) (2) [1] CEPT/ETSI regulations [CEPT1], [ETSI1]. [2] New CEPT/ETSI regulations. [ETSI3]. [3] FCC 47 part 15 regulation [FCC1]. [4] These read distances are maximum values for general tags and labels. Practical usable values may be lower due to damping by object materials and environmental conditions. A special tag antenna design can help achieve higher values. The typical write range is > 50% of the read range. Table 8. Symbol description Symbol Description Unit Ptag minimum required RF power for the tag W Gtag gain of the tag antenna - EIRP transmitted RF power m  wavelength m Rmax maximum achieved operating distance for a /2-dipole m  loss factor assumed to be 0.5 considering matching and package losses - R distance m Table 9. Operating distances for UCODE G2X based tags and labels in released frequency bands Frequency range Region Available power Calculated read distance single antenna [4] Unit 868.4 to 868.65 MHz (UHF) Europe [1] 0.5 W ERP 3.6 m 865.5 to 867.6 MHz (UHF) Europe [2] 2 W ERP 7.1 m 902 to 928 MHz (UHF) America [3] 4 W EIRP 7.5 m Ptag EIRP Gtag  4R ----------  2 =    Rmax EIRP  Gtag  2 42Ptag = ---------------------------------------   139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 15 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 12.4 Air interface standards The G2X is certified according EPCglobal 1.0.9 and fully supports all parts of the "Specification for RFID Air Interface EPCglobal, EPCTM Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID, Protocol for Communications at 860 MHz - 960 MHz, Version 1.1.0". EPCglobal compliance and interoperability certification 􀀚􀀖􀀑􀀒􀀒􀀑􀀒􀀓􀀗􀀑􀀑􀀑􀀑􀀑􀀑􀀖􀀔􀀘 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 16 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13. Physical layer and signaling 13.1 Reader to G2X communication 13.1.1 Physical layer For interrogator-to-G2X link modulation refer to Section 17, Ref. 1, annex H.1 Baseband waveforms, modulated RF, and detected waveforms. 13.1.2 Modulation An interrogator sends information to one or more G2X by modulating an RF carrier using double-sideband amplitude shift keying (DSB-ASK), single-sideband amplitude shift keying (SSB-ASK) or phase-reversal amplitude shift keying (PR-ASK) using a pulse-interval encoding (PIE) format. The G2X receives the operating energy from this same modulated RF carrier. Section 17, Ref. 1: Annex H, as well as chapter 6.3.1.2.2. The G2X is capable of demodulating all three modulation types. 13.1.3 Data encoding The R=>T link is using PIE. For the definition of the therefore relevant reference time interval for interrogator-to-chip signaling (Tari) refer to Section 17, Ref. 1, chapter 6.3.1.2.3. The Tari is specified as the duration of a data-0. 13.1.4 Data rates Interrogators shall communicate using Tari values between 6.25 s and 25 s, inclusive. For interrogator compliance evaluation the preferred Tari values of 6.25 s, 12.5 s or 25 s should be used. For further details refer to Section 17, Ref. 1, chapter 6.3.1.2.4. 13.1.5 RF envelope for R=>T A specification of the relevant RF envelope parameters can be found in Section 17, Ref. 1, chapter 6.3.1.2.5. 13.1.6 Interrogator power-up/down waveform For a specification of the interrogator power-up and power-down RF envelope and waveform parameters refer to Section 17, Ref. 1, chapters 6.3.1.2.6 and 6.3.1.2.7. 13.1.7 Preamble and frame-sync An interrogator shall begin all R=>T signaling with either a preamble or a frame-sync. A preamble shall precede a Query command and denotes the start of an inventory round. For a definition and explanation of the relevant R=>T preamble and frame-sync refer to Section 17, Ref. 1, chapter 6.3.1.2.8. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 17 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13.2 G2X to reader communication An interrogator receives information from a G2X by transmitting an unmodulated RF carrier and listening for a backscattered reply. The G2X backscatters by switching the reflection coefficient of its antenna between two states in accordance with the data being sent. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.1 Modulation The UCODE G2X communicates information by backscatter-modulating the amplitude and/or phase of the RF carrier. Interrogators shall be capable of demodulating either demodulation type. 13.2.2 Data encoding The encoding format, selected in response to interrogator commands, is either FM0 baseband or Miller-modulated subaltern. The interrogator commands the encoding choice 13.2.2.1 FM0 baseband FM0 inverts the baseband phase at every symbol boundary; a data-0 has an additional mid-symbol phase inversion. For details on FM0 and generator state diagram, FM0 symbols and sequences and how FM0 transmissions should be terminated refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.2.2 FM0 Preamble T=>R FM0 signaling begin with one of two defined preambles, depending on the value of the TRext bit specified in the Query command that initiated the inventory round. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.2.3 Miller-modulated sub carrier Baseband Miller inverts its phase between two data-0s in sequence. Baseband Miller also places a phase inversion in the middle of a data-1 symbol. For details on Miller-modulated sub carrier, generator state diagram, sub carrier sequences and terminating sub carrier transmissions refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.2.4 Miller sub carrier preamble T=>R sub carrier signaling begins with one of the two defined preambles. The choice depends on the value of the TRext bit specified in the Query command that initiated the inventory round. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3. 13.2.3 Data rates The G2X IC supports tag to interrogator data rates and link frequencies as specified in Section 17, Ref. 1, chapter 6.3.1.3. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 18 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13.3 Link timing For the interrogator interacting with a UCODE G2X equipped tag population exact link and response timing requirements must be fulfilled, which can be found in Section 17, Ref. 1, chapter 6.3.1.6. 13.3.1 Regeneration time The regeneration time is the time required if a G2X is to demodulate the interrogator signal, measured from the last falling edge of the last bit of the G2X response to the first falling edge of the interrogator transmission. This time is referred to as T2 and can vary between 3.0 Tpri and 20 Tpri. For a more detailed description refer to Section 17, Ref. 1, chapter 6.3.1.6. 13.3.2 Start-up time For a detailed description refer to Section 17, Ref. 1, chapter 6.3.1.3.4. 13.3.3 Persistence time An interrogator chooses one of four sessions and inventories tags within that session (denoted S0, S1, S2, and S3). The interrogator and associated UCODE G2X population operate in one and only one session for the duration of an inventory round (defined above). For each session, a corresponding inventoried flag is maintained. Sessions allow tags to keep track of their inventoried status separately for each of four possible time-interleaved inventory processes, using an independent inventoried flag for each process. Two or more interrogators can use sessions to independently inventory a common UCODE G2X chip population. A session flag indicates whether a G2X may respond to an interrogator. G2X chips maintain a separate inventoried flag for each of four sessions; each flag has symmetric A and B values. Within any given session, interrogators typically inventory tags from A to B followed by a re-inventory of tags from B back to A (or vice versa). Additionally, the G2X has implemented a selected flag, SL, which an interrogator may assert or deassert using a Select command. For a description of Inventoried flags S0 – S3 refer to Section 17, Ref. 1 chapter 6.3.2.2 and for a description of the Selected flag refer to Section 17, Ref. 1, chapter 6.3.2.3. For tag flags and respective persistence time refer to Section 17, Ref. 1, table 6.14. 13.4 Bit and byte ordering The transmission order for all R=>T and T=>R communications respects the following conventions: • within each message, the most-significant word is transmitted first, and • within each word, the most-significant bit (MSB) is transmitted first, whereas one word is composed of 16 bits. To represent memory addresses and mask lengths EBV-8 values are used. An extensible bit vector (EBV) is a data structure with an extensible data range. For a more detailed explanation refer to Section 17, Ref. 1, Annex A. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 19 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 13.5 Data integrity The G2X ignores invalid commands. In general, "invalid" means a command that (1) is incorrect given the current the G2X state, (2) is unsupported by the G2X, (3) has incorrect parameters, (4) has a CRC error, (5) specifies an incorrect session, or (6) is in any other way not recognized or not executable by the G2X. The actual definition of "invalid" is state-specific and defined, for each G2X state, in n Section 17, Ref. 1 Annex B and Annex C. All UCODE G2X backscatter error codes are summarized in Section 17, Ref. 1 Error codes, Annex I. For a detailed description of the individual backscatter error situations which are command specific please refer to the Section 17, Ref. 1 individual command description section 6.3.2.10. 13.6 CRC A CRC-16 is a cyclic-redundancy check that an interrogator uses when protecting certain R=>T commands, and the G2X uses when protecting certain backscattered T=>R sequences. To generate a CRC-16 an interrogator or the G2X first generates the CRC-16 precursor shown in Section 17, Ref. 1 Table 6.11, then take the ones-complement of the generated precursor to form the CRC-16. For a detailed description of the CRC-16 generation and handling rules refer to Section 17, Ref. 1, chapter 6.3.2.1. The CRC-5 is only used to protect the Query command (out of the mandatory command set). It is calculated out of X5 + X3 + 1. For a more detailed CRC-5 description refer to Section 17, Ref. 1, table 6.12. For exemplary schematic diagrams for CRC-5 and CRC-16 encoder/decoder refer to Section 17, Ref. 1, Annex F. For a CRC calculation example refer to Section 15.1, Table 27 and Table 28. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 20 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14. TAG selection, inventory and access This section contains all information including commands by which a reader selects, inventories, and accesses a G2X population An interrogator manages UCODE G2X equipped tag populations using three basic operations. Each of these operations comprises one or more commands. The operations are defined as follows Select: The process by which an interrogator selects a tag population for inventory and access. Interrogators may use one or more Select commands to select a particular tag population prior to inventory. Inventory: The process by which an interrogator identifies UCODE G2X equipped tags. An interrogator begins an inventory round by transmitting a Query command in one of four sessions. One or more G2X may reply. The interrogator detects a single G2X reply and requests the PC, EPC, and CRC-16 from the chip. An inventory round operates in one and only one session at a time. For an example of an interrogator inventorying and accessing a single G2X refer to Section 17, Ref. 1, Annex E. Access: The process by which an interrogator transacts with (reads from or writes to) individual G2X. An individual G2X must be uniquely identified prior to access. Access comprises multiple commands, some of which employ one-time-pad based cover-coding of the R=>T link. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 21 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.1 G2X Memory For the general memory layout according to the standard Section 17, Ref. 1, refer to Figure 6.17. The tag memory is logically subdivided into four distinct banks. In accordance to the standard Section 17, Ref. 1, section 6.3.2.1. The tag memory of the SL3ICS1002 G2XM is organized in following 4 memory sections: The logical address of all memory banks begin at zero (00h). Table 10. G2X memory sections Name Size Bank Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b EPC (excluding 16 bit CRC-16 and 16 bit PC) 240 bit 01b TID (including unique 32 bit serial number) 64 bit 10b User memory (G2XM only) 512 bit 11b Fig 4. G2X TID memory structure Serial Number Model Number Mask-Designer Identifier Class Identifier TID 0 31 0 11 0 11 0 7 3Fh 20h 1Fh 14h 13h 08h 07h 00h 0 6 0 4 1Fh 19h 18h 14h Version Number Sub Version Number 00000001h to FFFFFFFFh 006h E2h Whenever the 32 bit serial is exceeded the sub version is incremented by 1 Addresses 3Fh 00h Addresses Addresses Bits Bits LS Byte LSBit MSBit LSBit MSBit MS Byte LSBit MSBit LSBit MSBit 0000010b 00000b Sub Version Nr Version (Silicon) Nr Model Nr. Mask ID UCode EPC G2XM 00000b 0000011b 003h 006h UCode EPC G2XL 00000b 0000100b 004h 006h 002h 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 22 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.1.1 Memory map [1] This is the initial memory content when delivered by NXP Semiconductors [2] G2XL: HEX 3005 FB63 AC1F 3841 EC88 0467 G2XM: HEX 3005 FB63 AC1F 3681 EC88 0468 [3] only G2XM Table 11. Memory map Bank address Memory address Type Content Initial [1] Remark Bank 00 00h – 1Fh Reserved kill password: refer to Section 17, Ref. 1, chapter 6.3.2.1.1 all 00h unlocked memory 20h – 3Fh Reserved access password: refer to Section 17, Ref. 1, chapter 6.3.2.1.1 all 00h unlocked memory Bank 01 00h – 0Fh EPC CRC-16: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 memory mapped calculated CRC 10h – 14h EPC Backscatter length: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 00110b unlocked memory 15h EPC Reserved for future use: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 0b unlocked memory 16h EPC Reserved for future use: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 0b hardwired to 0 17h –1Fh EPC Numbering system indicator: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 00h unlocked memory 20h - 10Fh EPC EPC: refer to Section 17, Ref. 1, chapter 6.3.2.1.2 [2] unlocked memory Bank 10 00h – 07h TID allocation class identifier: refer to Section 17, Ref. 1, chapter 6.3.2.1.3 1110 0010b locked memory 08h – 13h TID tag mask designer identifier: refer to Section 17, Ref. 1, chapter 6.3.2.1.3 0000 0000 0110b locked memory 14h – 1Fh TID tag model number: refer to Section 17, Ref. 1, chapter 6.3.2.1.3 TMNR locked memory 20h – 3Fh TID serial number: refer to [Section 17, Ref. 1, chapter 6.3.2.1.3 SNR locked memory Bank 11[3] 00h – 1FFh User user memory: refer to [Section 17, Ref. 1, chapter 6.3.2.1.4 undefined unlocked memory 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 23 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.1.1.1 User memory (only G2XM) The User Memory bank contains a sequential block of 512 bits (32 words of 16 bit) ranging from address 00h to 1Fh. The user memory can be accessed via Select, Read or Write command and it may be write locked, permanently write locked, unlocked or permanently unlocked. In addition reading of not only of the User Memory but of the whole memory including EPC and TID can be protected by using the custom ReadProtect command. 14.1.1.2 Special behavior of user memory address 1Fh WRITE or SELECT of user memory address 1Fh will falsely set an error flag. This will affect the subsequent READ or SELECT. The following commands will falsely set an internal error flag (without actually causing an error): 1) WRITE to user memory with WordPtr=1Fh 2) SELECT to user memory with compare mask ending at bitaddress 1FFh (e.g. Pointer=1FEh, length=1 or Pointer=1FDh, length=2 …) Note: The error flag is set independent of the chip state (also chips in the e.g. Ready state are affected). The falsely set error flag will affect the following sub sequential commands: A) READ command with WordCount=0 falsely responds with "memory overrun" error B) SELECT command with Length<>0  falsely assumes non existing memory location The behavior can be avoided with: • Turning off the RF carrier to reset the chip (This is what readers typically do!). • Using the READ command with WordCount<>0. • Sending other command prior to READ or SELECT (e.g. WRITE to address<>1Fh, ReqRN) or executing READ or SELECT two times. Remark: The WRITE operation itself is not affected by this problem i.e. data is written properly! With commercially available readers this behavior is typically not observed. 14.1.1.3 Supported EPC types The EPC types are defined in the EPC Tag Standards document from EPCglobal. These standards define completely that portion of EPC tag data that is standardized, including how that data is encoded on the EPC tag itself (i.e. the EPC Tag Encodings), as well as how it is encoded for use in the information systems layers of the EPC Systems Network (i.e. the EPC URI or Uniform Resource Identifier Encodings). The EPC Tag Encodings include a Header field followed by one or more Value Fields. The Header field indicates the length of the Values Fields and contains a numbering system identifier (NSI). The Value Fields contain a unique EPC Identifier and optional Filter Value when the latter is judged to be important to encode on the tag itself. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 24 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.2 Sessions, selected and inventoried flags Session, Selected and Inventory Flags are according the EPCglobal standard. For a description refer to Section 17, Ref. 1, section 6.3.2.3. 14.2.1 G2X States and slot counter For a description refer to Section 17, Ref. 1, section 6.3.2.4. 14.2.2 G2X State Diagram The tag state are according the EPCglobal standard please refer to: Section 17, Ref. 1, section 6.3.2.4 Tag states and slot counter. A detailed tag state diagram is shown in Section 17, Ref. 1, figure 6.19. Refer also to Section 17, Ref. 1, Annex B for the associated state-transition tables and to Section 17, Ref. 1, Annex C for the associated command-response tables. 14.3 Managing tag populations For a detailed description on how to manage an UCODE G2X tag populations refer to Section 17, Ref. 1, chapter 6.3.2.6. 14.4 Selecting tag populations For a detailed description of the UCODE G2X tag population selection process refer to Section 17, Ref. 1, section 6.3.2.7. 14.5 Inventorying tag populations For a detailed description on accessing individual tags based on the UCODE G2X refer to Section 17, Ref. 1, section 6.3.2.8. 14.6 Accessing individual tags For a detailed description on accessing individual tags based on the UCODE G2X refer to Section 17, Ref. 1, section 6.3.2.9. An example inventory and access of a single UCODE G2X tag is shown in Section 17, Ref. 1, Annex E.1. 14.7 Interrogator commands and tag replies For a detailed description refer to Section 17, Ref. 1, section 6.3.2.10. 14.7.1 Commands An overview of interrogator to tag commands is located in Section 17, Ref. 1, Table 6.16. Note that all mandatory commands are implemented on the G2X according to the standard. Additionally the optional command Access is supported by the G2X (for details refer to Section 14.11 “Optional Access Command”). Besides also custom commands are implemented on the G2X (for details refer to Section 14.12 “Custom Commands”. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 25 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.7.2 State transition tables The G2X responses to interrogator commands are defined by State Annex B transition tables in Section 17, Ref. 1. Following states are implemented on the G2X: • Ready, for a description refer to Section 17, Ref. 1, Annex B.1. • Arbitrate, for a description refer to Section 17, Ref. 1, Annex B.2. • Reply, for a description refer to Section 17, Ref. 1, Annex B.3. • Acknowledged, for a description refer to Section 17, Ref. 1, Annex B.4. • Open, for a description refer to Section 17, Ref. 1, Annex B.5. • Secured, for a description refer to Section 17, Ref. 1, Annex B.6. • Killed, for a description refer to Section 17, Ref. 1, Annex B.7. 14.7.3 Command response tables The G2X responses to interrogator commands are described in following Annex C sections of Section 17, Ref. 1: • Power-up, for a description refer to Section 17, Ref. 1, Annex C.1. • Query, for a description refer to Section 17, Ref. 1, Annex C.2. • QueryRep, for a description refer to Section 17, Ref. 1, Annex C.3. • QueryAdjust, for a description refer to Section 17, Ref. 1, Annex C.4. • ACK, for a description refer to Section 17, Ref. 1, Annex C.5. • NAK, for a description refer to Section 17, Ref. 1, Annex C.6. • Req_RN, for a description refer to Section 17, Ref. 1, Annex C.7. • Select, for a description refer to Section 17, Ref. 1, Annex C.8. • Read, for a description refer to Section 17, Ref. 1, Annex C.9. • Write, for a description refer to Section 17, Ref. 1, Annex C.10. • Kill, for a description refer to Section 17, Ref. 1, Annex C.11. • Lock, for a description refer to Section 17, Ref. 1, Annex C.12. • Access, for a description refer to Section 17, Ref. 1, Annex C.13. • T2 time-out, for a description refer to Section 17, Ref. 1, Annex C.17. • Invalid command, for a description refer to Section 17, Ref. 1, Annex C.18. 14.7.4 Example data-flow exchange For data flow-exchange examples refer to Section 17, Ref. 1, Annex K: • K.1 Overview of the data-flow exchange • K.2 Tag memory contents and lock-field values • K.3 Data-flow exchange and command sequence 14.8 Mandatory Select Commands Select commands select a particular UCODE G2X tag population based on user-defined criteria. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 26 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.8.1 Select For a detailed description of the mandatory Select command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9 Mandatory Inventory Commands Inventory commands are used to run the collision arbitration protocol. 14.9.1 Query For a detailed description of the mandatory Query command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.2 QueryAdjust For a detailed description of the mandatory QueryAdjust command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.3 QueryRep For a detailed description of the mandatory QueryRep command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.4 ACK For a detailed description of the mandatory ACK command refer to Section 17, Ref. 1, section 6.3.2.10. 14.9.5 NAK For a detailed description of the mandatory NAK command refer to Section 17, Ref. 1, section 6.3.2.10. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 27 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.10 Mandatory Access Commands Access commands are used to read or write data from or to the G2X memory. For a detailed description of the mandatory Access command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.1 REQ_RN Access commands are used to read or write data from or to the G2X memory. For a detailed description of the mandatory Access command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.2 READ For a detailed description of the mandatory Req_RN command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.3 WRITE For a detailed description of the mandatory Write command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.4 KILL For a detailed description of the mandatory Kill command refer to Section 17, Ref. 1, section 6.3.2.10. 14.10.5 LOCK For a detailed description of the mandatory Lock command refer to Section 17, Ref. 1, section 6.3.2.10. 14.11 Optional Access Command 14.11.1 Access For a detailed description of the optional Access command refer to Section 17, Ref. 1, section 6.3.2.10. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 28 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12 Custom Commands 14.12.1 ReadProtect The G2X ReadProtect custom command enables reliable read protection of the entire G2X memory. Executing ReadProtect from the Secured state will set the ReadProtect-bit to '1'. With the ReadProtect-Bit set the G2X will continue to work unaffected but fail its content. Following commands will be disabled: Read, Write, Kill, Lock, Access, ReadProtect, ChangeEAS, EAS Alarm and Calibrate. The G2X will only react upon an anticollision with Select, Query, QueryRep, QueryAdjust, ACK (no truncated reply), NAK, ReqRN but reply with zeros as EPC and CRC-16 content (except PC/password). ACK will return zeros except for the PC. The read protection can be removed by executing Reset ReadProtect. The ReadProtect-Bit will than be cleared. Devices whose access password is zero will ignore the command. A frame-sync must be prepended the command. After sending the ReadProtect command an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect command and the backscattered reply. An interrogator may observe three possible responses after sending a ReadProtect, depending on the success or failure of the operation: • ReadProtect succeeds: After completing the ReadProtect the G2X shall backscatter the reply shown in Table 14 comprising a header (a 0-bit), the tag's handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this reply the G2X will render itself to this ReadProtect mode. If the interrogator observes this reply within 20 ms then the ReadProtect completed successfully. • The G2X encounters an error: The G2X will backscatter an error code during the CW period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code definitions and for the reply format). • ReadProtect does not succeed: If the interrogator does not observe a reply within 20 ms then the ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2X is still in the interrogation zone, and may re-initiate the ReadProtect command. The G2X reply to the ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. Table 12. ReadProtect command Command RN CRC-16 # of bits 16 16 16 description 11100000 00000001 handle - 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 29 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 13. G2X reply to a successful ReadProtect procedure Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 14. ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all - open secured valid handle & invalid access password – arbitrate valid handle & valid non zero access password Backscatter handle, when done secured invalid handle – secured killed all – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 30 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.2 Reset ReadProtect Reset ReadProtect allows an interrogator to resets the ReadProtect-bit and re-enables reading of the G2X memory content according the EPCglobal specification. The G2X will execute Reset ReadProtect from the Open or Secured states. If a G2X in the Open or Secured states receives a Reset ReadProtect with a valid CRC-16 and a valid handle but an incorrect access password, it will not reply and transit to the Arbitrate state. If a G2X in the Open or Secured states receives a Reset ReadProtect with a valid CRC-16 and a valid handle but the ReadProtect-Bit is not set ('0'), it will not change the ReadProtect-Bit but backscatter the reply shown in Table 17. If a G2X in the Open or Secured receives a Reset ReadProtect with a valid CRC-16 but an invalid handle, or it receives a Reset ReadProtect before which the immediately preceding command was not a Req_RN, it will ignore the Reset ReadProtect and remain in its current state. A frame-sync must be prepended the Reset ReadProtect command. After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect command and the G2X backscattered reply. An interrogator may observe three possible responses after sending a Reset ReadProtect, depending on the success or failure of the operation: • Write succeeds: After completing the Reset ReadProtect a G2X will backscatter the reply shown in Table 17 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the Reset ReadProtect completed successfully. • The G2X encounters an error: The G2X will backscatter an error code during the CW period rather than the reply shown in Table 17 (see EPCglobal Spec for error-code definitions and for the reply format). • Write does not succeed: If the interrogator does not observe a reply within 20 ms then the Reset ReadProtect did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2X is still in the interrogation zone, and may reissue the Reset ReadProtect command. The G2X reply to the Reset ReadProtect command will use the extended preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a G2X will reply as if TRext=1 regardless of the TRext value in the Query that initiated the round. The Reset ReadProtect command is structured as following: • 16 bit command • Password: 32 bit Access-Password XOR with 2 times current RN16 • 16 bit handle • CRC-16 calculate over the first command-code bit to the last handle bit 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 31 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 15. Reset ReadProtect command Command Password RN CRC-16 # of bits 16 32 16 16 description 11100000 00000010 (access password)  2*RN16 handle - Table 16. G2X reply to a successful Reset ReadProtect command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 17. Reset ReadProtect command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open ReadProtect bit is set, valid handle & valid access password Backscatter handle, when done open ReadProtect bit is set, valid handle & invalid access password – arbitrate ReadProtect bit is set, invalid handle – open ReadProtect bit is reset – open secured ReadProtect bit is set, valid handle & valid access password Backscatter handle, when done secured ReadProtect bit is set, valid handle & invalid access password – arbitrate ReadProtect bit is set, invalid handle – secured ReadProtect bit is reset – secured killed all – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 32 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.3 ChangeEAS A G2X equipped RFID tag can be enhanced by a stand-alone operating EAS alarm feature. With an EAS-Alarm bit set to '1' the tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the need of a Select or Query. The EAS is a built-in solution so no connection to a backend database is required. As it is a custom command no Select or Query is required to detect the EAS state enabling fast, reliable and offline article surveillance. ChangeEAS can be executed from the Secured state only. The command will be ignored if the Access Password is zero, the command will also be ignored with an invalid CRC-16 or an invalid handle, the G2X will than remain in the current state. The CRC-16 is calculated from the first command-code bit to the last handle bit. A frame-sync must be prepended the command. The G2X reply to a successful ChangeEAS will use the extended preamble, as appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the Query that initiated the round. After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or 20 ms, where TReply is the time between the interrogator's ChangeEAS command and the G2X backscattered reply. An interrogator may observe three possible responses after sending a ChangeEAS, depending on the success or failure of the operation • Write succeeds: After completing the ChangeEAS a G2X will backscatter the reply shown in Table 20 comprising a header (a 0-bit), the handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply within 20 ms then the ChangeEAS completed successfully. • The G2X encounters an error: The G2X will backscatter an error code during the CW period rather than the reply shown in Table 20 (see EPCglobal Spec for error-code definitions and for the reply format). • Write does not succeed: If the interrogator does not observe a reply within 20 ms then the ChangeEAS did not complete successfully. The interrogator may issue a Req_RN command (containing the handle) to verify that the G2X is still in the interrogator's field, and may reissue the ChangeEAS command. Upon receiving a valid ChangeEAS command a G2X will perform the commanded set/reset operation of the EAS_Alarm-Bit. If EAS-Bit is set, the EAS_Alarm command will be available after the next power up and reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be ignored. Table 18. ChangeEAS command Command ChangeEas RN CRC-16 # of bits 16 1 16 16 description 11100000 00000011 1 ... set EAS system bit 0 ... reset EAS system bit handle 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 33 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 19. G2X reply to a successful ChangeEAS command Header RN CRC-16 # of bits 1 16 16 description 0 handle - Table 20. ChangeEAS command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate open all – open secured valid handle Backscatter handle, when done secured invalid handle – secured killed all – killed Starting State Condition Response Next State 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 34 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.4 EAS_Alarm EAS_Alarm is a custom command causing the G2X to immediately backscatter an EAS-Alarmcode, when EAS ALARM bit is set without any delay caused by Select, Query and without the need for a backend database. The EAS feature of the G2X is available after enabling it by sending a ChangeEAS command described in Section 14.12.3 “ChangeEAS”. With an EAS-Alarm bit set to '1' the G2X will reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A G2X will reply to an EAS_Alarm command from the ready state only. If the EAS-Alarm bit is reset ('0') by sending a ChangeEAS command in the password protected Secure state the G2X will not reply to an EAS_Alarm command. The EAS_Alarm command is structured as following: • 16 bit command • 16 bit inverted command • DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec. 6.3.1.2.8 and Table 6.9. • M (cycles per symbol) sets the T=>R data rate and modulation format as shown in EPCglobal Spec. Table 6.10. • TRext chooses whether the T=>R preamble is prepended with a pilot tone as described in EPCglobal Spec. 6.3.1.3. A preamble must be prepended the EAS_Alarm command according EPCglobal Spec, 6.3.1.2.8. Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate the CRC5 over the backscattered 64 bits received to verify the received code. Table 21. EAS_Alarm command Command Inv_Command DR M TRext CRC-16 # of bits 16 16 1 2 1 16 description 11100000 00000100 00011111 11111011 0: DR=8 1: DR=64/3 00: M=1 01: M=2 10: M=4 11: M=8 0: No pilot tone 1: Use pilot tone - Table 22. G2X reply to a successful EAS_Alarm command Header EAS Code # of bits 1 64 description 0 CRC5 (MSB) 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 35 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 23. Eas_Alarm command-response table Starting State Condition Response Next State ready EAS-bit is set and non-zero access password Backscatter Alarm code ready arbitrate, reply, acknowledged EAS-bit is set and non-zero access password – arbitrate open EAS-bit is set and non-zero access password open secured EAS-bit is set and non-zero access password secured killed EAS-bit is set and non-zero access password – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 36 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 14.12.5 Calibrate After execution of the custom Calibrate command the G2X will continuously backscatter the user memory content in an infinite loop. The G2XL will continuously backscatter zeros. This command can be used for frequency spectrum measurements. Calibrate can only be executed from the Secure state with an non-zero Access Password set otherwise the command will be ignored. The Calibrate command includes a CRC-16 calculated over the whole command, the handle and a prepended frame-sync. [1] G2XM [2] G2XL Table 24. Calibrate command Command RN16 CRC-16 # of bits 16 16 16 description 11100000 00000101 handle - Table 25. G2X reply to a successful Calibrate command Header Infinite repeat # of bits 1 512 (looped) description 0 User memory data[1] zeros[2] Table 26. Calibrate command-response table Starting State Condition Response Next State ready all – ready arbitrate, reply, acknowledged all – arbitrate secured nonzero access password Backscatter infinite _ access password is zero – secured killed all – killed 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 37 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 15. Support information 15.1 CRC Calculation EXAMPLE Old RN = 3D5Bh Table 27. Practical example of CRC calculation for a 'Req_RN' command by the reader CRC Calculated @ Reader Cmd Code for Req_RN F F F F 1 F F F E 1 F F F C 0 E F D 9 0 C F 9 3 0 8 F 0 7 0 0 E 2 F 0 1 C 5 E 1 2 8 9 9 First Byte of RN 0 5 1 3 A 0 A 2 7 4 1 4 4 E 8 1 9 9 F 1 1 3 3 E 2 1 7 7 E 5 0 E F C A 1 D F 9 4 Second Byte of RN 0 A F 0 9 1 5 E 1 2 0 B C 2 4 1 7 8 4 8 1 E 0 B 1 0 D 1 4 3 1 A 2 8 6 1 4 5 0 C -> ones complement: B A F 3 => Command-Sequence: C1 3D 5B BA F3 hex 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 38 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Table 28. Practical example of CRC calculation for a 'Req_RN' command by the reader CRC Calculated @ Tag Cmd Code for Req_RN F F F F 1 F F F E 1 F F F C 0 E F D 9 0 C F 9 3 0 8 F 0 7 0 0 E 2 F 0 1 C 5 E 1 2 8 9 9 First Byte of RN 0 5 1 3 A 0 A 2 7 4 1 4 4 E 8 1 9 9 F 1 1 3 3 E 2 1 7 7 E 5 0 E F C A 1 D F 9 4 Second Byte of RN 0 A F 0 9 1 5 E 1 2 0 B C 2 4 1 7 8 4 8 1 E 0 B 1 0 D 1 4 3 1 A 2 8 6 1 4 5 0 C First Byte of CRC 1 9 A 3 9 0 2 4 5 3 1 5 8 8 7 1 A 1 2 F 1 4 2 5 E 0 8 4 B C 1 0 9 7 8 0 1 2 F 0 Second Byte of CRC 1 3 5 C 1 1 7 B A 3 1 E 7 6 7 1 C E C E 0 8 D B D 0 0 B 5 B 1 0 6 9 7 1 1 D 0 F -> Residue OK 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 39 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 16. Abbreviations Table 29. Abbreviations Acronym Description CRC Cyclic redundancy check CW Continuos wave EEPROM Electrically Erasable Programmable Read Only Memory EPC Electronic Product Code (containing Header, Domain Manager, Object Class and Serial Number) FM0 Bi phase space modulation G2 Generation 2 HBM Human Body Model IC Integrated Circuit LSB Least Significant Byte/Bit MSB Most Significant Byte/Bit NRZ Non-Return to Zero coding RF Radio Frequency RTF Reader Talks First Tari Type A Reference Interval (ISO 18000-6) UHF Ultra High Frequency Xxb Value in binary notation xxhex Value in hexadecimal notation 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 40 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 17. References [1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0 (December 17, 2005) [2] EPCglobal: EPC Tag Data Standards [3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft) [4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference (draft) [5] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 1 – Technical characteristics and test methods [6] European Telecommunications Standards Institute (ETSI), EN 302 208: Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency identification equipment operating in the band 865 MHz to 868 MHz with power levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive [7] [CEPT1]: CEPT REC 70-03 Annex 1 [8] [ETSI1]: ETSI EN 330 220-1, 2 [9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1: Technical characteristics and test methods. [10] [FCC1]: FCC 47 Part 15 Section 247 [11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International Standards [12] ISO/IEC 3309: Information technology – Telecommunications and information exchange between systems – High-level data link control (HDLC) procedures – Frame structure [13] ISO/IEC 15961: Information technology, Automatic identification and data capture – Radio frequency identification (RFID) for item management – Data protocol: application interface [14] ISO/IEC 15962: Information technology, Automatic identification and data capture techniques – Radio frequency identification (RFID) for item management – Data protocol: data encoding rules and logical memory functions [15] ISO/IEC 15963: Information technology — Radio frequency identification for item management — Unique identification for RF tags [16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item management — Part 1: Reference architecture and definition of parameters to be standardized [17] ISO/IEC 18000-6: Information technology automatic identification and data capture techniques — Radio frequency identification for item management air interface — Part 6: Parameters for air interface communications at 860–960 MHz [18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary – Part 3: radio-frequency identification (RFID) 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 41 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL [19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15: Radio-frequency devices, U.S. Federal Communications Commission. [20] Data sheet - Delivery type description – General specification for 8” wafer on UV-tape with electronic fail die marking, BL-ID document number: 1093**1 1. ** ... document version number 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 42 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 18. Revision history Table 30. Revision history Document ID Release date Data sheet status Change notice Supersedes SL3ICS1002_1202 v.3.8 20131111 Product data sheet - SL3ICS1002_1202 v.3.7 Modifications: • Update of the delivery form (TSSOP package due to DOD removed) SL3ICS1002_1202 v.3.7 20121009 Product data sheet - 139036 Modifications: • Update of the delivery form 139036 20110310 Product data sheet 139035 Modifications: • Table 4 “TSSOP8 Marking”: added • Section 14.1.1.2 “Special behavior of user memory address 1Fh”: added 139035 20091102 Product data sheet 139034 Modifications: • Type SOT1122 added • Figure 2 “Wafer layout and pinning information”: correction of drawing 139034 20090721 Product data sheet 139033 Modifications: • Table 11 “TSSOP8 characteristics” andTable 7 “Package interface characteristics” :removed “Memory characteristics” 139033 20090605 Product data sheet - 139032 139132 Modifications: • This data sheet is a combination of data sheets SL3ICS1002 and SL3ICS1202 • New type FCS2 Aluminum, SOT1040AB2 added • Section 8.1.6 “Fail die identification”: added • Section 11 “Packing information”: edited 139032 20080716 Product data sheet 139031 Modifications: • rephrasing of Section 2 “Features and benefits” on page 2 • added “calibrate command” in Section 2 “Features and benefits” on page 2 • redesign of Figure 1 “Block diagram of G2X IC” on page 4 • merging of Fig. 2 Pinning and Fig. 3 Wafer layout - see Figure 2 “Wafer layout and pinning information” on page 5 • added type “FCS2 Polymer Strap - SOT1040AA1” in Section 4 “Ordering information”, Section 6 “Wafer layout and pinning information”, Section 7 “Package outline”, Section 8 “Mechanical specification”, Section 9 “Limiting values”, Section 10 “Characteristics” • added Section 11 “Handling information for Flip Chip Strap (FCS2, SOT1040)” on page 19 • added Section 11 “Packing information” on page 12 • added Table 8 “Symbol description” on page 14 • correction of Table 11 “Memory map” on page 22 • removed “ongoing” in 32 bit ongoing in Section 2.1 and Table 10 “G2X memory sections” 139031 20080428 Product data sheet 139030 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 43 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Modifications: • update of Table 1 “Ordering information” on page 3 • added Section 7 “Package outline” on page 6 • added Section 8.1.7 “Map file distribution” on page 9 • added Table 9 “Limiting values TSSOP8 [1][2]” on page 14 • added room temperature in Table 11 “Memory characteristics” on page 15 • added Section 10.2 “TSSOP8 characteristics” on page 17 • update of the “EPCglobal compliance and interoperability certification” in Section 12.4 “Air interface standards” on page 15 • correction of “(excluding 16 bit CRC-16 and 16 bit PC) in Table 10 “G2X memory sections” on page 21 • correction of Initials in “tag mask designer” in Table 11 “Memory map” on page 22 • removed the sentence “The ChangeEAS custom command will toggle the state of the EAS-Alarm bit located in the EEprom” in Section 14.12.3 “ChangeEAS” on page 32. • added description of ChangeEAS in Table 18 “ChangeEAS command” on page 32 139030 20071221 Product data sheet - 139011 Modifications: • change of product status • general update 139011 20070910 Objective data sheet - 139010 Modifications: • removed double section Change EAS, EAS Alarm, Chapter 12.11.7 • changed “Reader” to “Tag” 139010 20070612 Objective data sheet - - • initial version Table 30. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 44 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 19. Legal information 19.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 45 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. UCODE — is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 46 of 48 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 21. Tables Table 1. Ordering information G2XM . . . . . . . . . . . . . . . .3 Table 2. Ordering information G2XL. . . . . . . . . . . . . . . . .3 Table 3. Pin description of SOT1122 . . . . . . . . . . . . . . . .7 Table 4. SOT1122 Marking. . . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Limiting values[1][2] . . . . . . . . . . . . . . . . . . . . . .10 Table 6. Wafer characteristics . . . . . . . . . . . . . . . . . . . . 11 Table 7. Package interface characteristics. . . . . . . . . . . 11 Table 8. Symbol description . . . . . . . . . . . . . . . . . . . . . .14 Table 9. Operating distances for UCODE G2X based tags and labels in released frequency bands . .14 Table 10. G2X memory sections . . . . . . . . . . . . . . . . . . .21 Table 11. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 12. ReadProtect command. . . . . . . . . . . . . . . . . . .28 Table 13. G2X reply to a successful ReadProtect procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Table 14. ReadProtect command-response table . . . . . .29 Table 15. Reset ReadProtect command . . . . . . . . . . . . .31 Table 16. G2X reply to a successful Reset ReadProtect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 17. Reset ReadProtect command-response table 31 Table 18. ChangeEAS command . . . . . . . . . . . . . . . . . . 32 Table 19. G2X reply to a successful ChangeEAS command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 20. ChangeEAS command-response table . . . . . . 33 Table 21. EAS_Alarm command . . . . . . . . . . . . . . . . . . . 34 Table 22. G2X reply to a successful EAS_Alarm command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 23. Eas_Alarm command-response table. . . . . . . 35 Table 24. Calibrate command . . . . . . . . . . . . . . . . . . . . . 36 Table 25. G2X reply to a successful Calibrate command 36 Table 26. Calibrate command-response table . . . . . . . . . 36 Table 27. Practical example of CRC calculation for a 'Req_RN' command by the reader . . . . . . . . . 37 Table 28. Practical example of CRC calculation for a 'Req_RN' command by the reader. . . . . . . . . . 38 Table 29. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 30. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 42 22. Figures Fig 1. Block diagram of G2X IC . . . . . . . . . . . . . . . . . . . .4 Fig 2. Wafer layout and pinning information . . . . . . . . . .5 Fig 3. Package outline SOT1122 . . . . . . . . . . . . . . . . . . .6 Fig 4. G2X TID memory structure . . . . . . . . . . . . . . . . .21 139037 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.8 — 11 November 2013 139038 47 of 48 continued >> NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Wafer layout and pinning information . . . . . . . 5 6.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Mechanical specification . . . . . . . . . . . . . . . . . 8 8.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 8 8.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.2 Wafer backside . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.3 Chip dimensions . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.4 Passivation on front . . . . . . . . . . . . . . . . . . . . . 8 8.1.5 Au bump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1.6 Fail die identification . . . . . . . . . . . . . . . . . . . . 9 8.1.7 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 9 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11 10.1 Wafer characteristics . . . . . . . . . . . . . . . . . . . 11 10.2 Package characteristics . . . . . . . . . . . . . . . . . 11 11 Packing information . . . . . . . . . . . . . . . . . . . . 12 11.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.2 SOT1122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 Functional description . . . . . . . . . . . . . . . . . . 13 12.1 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . 13 12.2 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12.2.1 Reader to G2X Link . . . . . . . . . . . . . . . . . . . . 13 12.2.2 G2X to reader Link . . . . . . . . . . . . . . . . . . . . . 13 12.3 Operating distances . . . . . . . . . . . . . . . . . . . . 14 12.4 Air interface standards . . . . . . . . . . . . . . . . . . 15 13 Physical layer and signaling. . . . . . . . . . . . . . 16 13.1 Reader to G2X communication . . . . . . . . . . . 16 13.1.1 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.2 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.3 Data encoding. . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.4 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13.1.5 RF envelope for R=>T . . . . . . . . . . . . . . . . . . 16 13.1.6 Interrogator power-up/down waveform. . . . . . 16 13.1.7 Preamble and frame-sync . . . . . . . . . . . . . . . 16 13.2 G2X to reader communication . . . . . . . . . . . . 17 13.2.1 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2 Data encoding . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2.1 FM0 baseband . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2.2 FM0 Preamble . . . . . . . . . . . . . . . . . . . . . . . . 17 13.2.2.3 Miller-modulated sub carrier . . . . . . . . . . . . . 17 13.2.2.4 Miller sub carrier preamble . . . . . . . . . . . . . . 17 13.2.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13.3 Link timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3.1 Regeneration time . . . . . . . . . . . . . . . . . . . . . 18 13.3.2 Start-up time. . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3.3 Persistence time . . . . . . . . . . . . . . . . . . . . . . 18 13.4 Bit and byte ordering . . . . . . . . . . . . . . . . . . . 18 13.5 Data integrity . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.6 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14 TAG selection, inventory and access . . . . . . 20 14.1 G2X Memory . . . . . . . . . . . . . . . . . . . . . . . . . 21 14.1.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . 22 14.1.1.1 User memory (only G2XM) . . . . . . . . . . . . . . 23 14.1.1.2 Special behavior of user memory address 1Fh 23 14.1.1.3 Supported EPC types . . . . . . . . . . . . . . . . . . 23 14.2 Sessions, selected and inventoried flags. . . . 24 14.2.1 G2X States and slot counter . . . . . . . . . . . . . 24 14.2.2 G2X State Diagram . . . . . . . . . . . . . . . . . . . . 24 14.3 Managing tag populations . . . . . . . . . . . . . . . 24 14.4 Selecting tag populations. . . . . . . . . . . . . . . . 24 14.5 Inventorying tag populations . . . . . . . . . . . . . 24 14.6 Accessing individual tags. . . . . . . . . . . . . . . . 24 14.7 Interrogator commands and tag replies . . . . . 24 14.7.1 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 14.7.2 State transition tables. . . . . . . . . . . . . . . . . . . 25 14.7.3 Command response tables . . . . . . . . . . . . . . 25 14.7.4 Example data-flow exchange. . . . . . . . . . . . . 25 14.8 Mandatory Select Commands . . . . . . . . . . . . 25 14.8.1 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9 Mandatory Inventory Commands. . . . . . . . . . 26 14.9.1 Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.2 QueryAdjust . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.3 QueryRep. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.4 ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.9.5 NAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.10 Mandatory Access Commands . . . . . . . . . . . 27 14.10.1 REQ_RN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.2 READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.3 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.4 KILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.10.5 LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.11 Optional Access Command . . . . . . . . . . . . . . 27 14.11.1 Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.12 Custom Commands . . . . . . . . . . . . . . . . . . . . 28 NXP Semiconductors SL3ICS1002/1202 UCODE G2XM and G2XL © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 November 2013 139038 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 14.12.1 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14.12.2 Reset ReadProtect . . . . . . . . . . . . . . . . . . . . . 30 14.12.3 ChangeEAS . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14.12.4 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14.12.5 Calibrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15 Support information . . . . . . . . . . . . . . . . . . . . 37 15.1 CRC Calculation EXAMPLE . . . . . . . . . . . . . . 37 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 39 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 42 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 44 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 20 Contact information. . . . . . . . . . . . . . . . . . . . . 45 21 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 22 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1. General description The LPC11U3x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11U3x operate at CPU frequencies of up to 50 MHz. Equipped with a highly flexible and configurable full-speed USB 2.0 device controller, the LPC11U3x brings unparalleled design flexibility and seamless integration to today’s demanding connectivity solutions. The peripheral complement of the LPC11U3x includes up to 128 kB of flash memory, up to 12 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 USART with support for synchronous mode and smart card interface, two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins. The I/O Handler is a software library-supported hardware engine that can be used to add performance, connectivity and flexibility to system designs. It is available on the LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART, I2C, and I2S with no or very low additional CPU load and can off-load the CPU by performing processing-intensive functions like DMA transfers in hardware. Software libraries for multiple I/O Handler applications are available on http://www.LPCware.com. For additional documentation related to the LPC11U3x parts, see Section 15 “References”. 2. Features and benefits  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).  Non-Maskable Interrupt (NMI) input selectable from several input sources.  System tick timer.  Memory:  Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase (256 byte) access.  4 kB on-chip EEPROM data memory; byte erasable and byte programmable; on-chip API support.  Up to 12 kB SRAM data memory. LPC11U3x 32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash; up to 12 kB SRAM and 4 kB EEPROM; USB device; USART Rev. 2.2 — 11 March 2014 Product data sheet LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 2 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller  16 kB boot ROM.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  ROM-based USB drivers. Flash updates via USB supported.  ROM-based 32-bit integer division routines.  Debug options:  Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan Description Language).  Serial Wire Debug.  Digital peripherals:  Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, repeater mode, and open-drain mode.  Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.  Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins.  High-current source output driver (20 mA) on one pin.  High-current sink driver (20 mA) on true open-drain pins.  Four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs.  Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDO).  Analog peripherals:  10-bit ADC with input multiplexing among eight pins.  Serial interfaces:  USB 2.0 full-speed device controller.  USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3).  Two SSP controllers with FIFO and multi-protocol capabilities.  I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.  I/O Handler for hardware emulation of serial interfaces and DMA; supported through software libraries. (LPC11U37HFBD64/401 only.)  Clock generation:  Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).  12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a system clock.  Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output.  PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources.  A second, dedicated PLL is provided for USB.  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.  Power control: LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 3 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller  Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes.  Power profiles residing in boot ROM provide optimized performance and minimized power consumption for any given application through one simple function call.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity.  Processor wake-up from Deep power-down mode using one special function pin.  Power-On Reset (POR).  Brownout detect with up to four separate thresholds for interrupt and forced reset.  Unique device serial number for identification.  Single 3.3 V power supply (1.8 V to 3.6 V).  Temperature range 40 C to +85 C.  Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages. 3. Applications 4. Ordering information  Consumer peripherals  Handheld scanners  Medical  USB audio devices  Industrial control Table 1. Ordering information Type number Package Name Description Version LPC11U34FHN33/311 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC11U34FBD48/311 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U34FHN33/421 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC11U34FBD48/421 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U35FHN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7  7  0.85 mm n/a LPC11U35FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U35FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 LPC11U35FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5  5  0.85 mm n/a LPC11U35FET48/501 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5  4.5  0.7 mm SOT1155-2 LPC11U36FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U36FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 4 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 4.1 Ordering options [1] For general-purpose use. [2] For I/O Handler use only. LPC11U37FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7  7  1.4 mm SOT313-2 LPC11U37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 LPC11U37FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10  10  1.4 mm SOT314-2 Table 1. Ordering information …continued Type number Package Name Description Version Table 2. Ordering options Type number Flash in kB EEPROM in kB SRAM0 in kB USB SRAM in kB SRAM1 in kB Total SRAM in kB[1] I/O Handler USART I2C-bus FM+ SSP USB device ADC channels GPIO pins LPC11U34FHN33/311 40 4 8 - - 8 no 1 1 2 1 8 26 LPC11U34FBD48/311 40 4 8 - - 8 no 1 1 2 1 8 40 LPC11U34FHN33/421 48 4 8 2 - 10 no 1 1 2 1 8 26 LPC11U34FBD48/421 48 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U35FHN33/401 64 4 8 2 - 10 no 1 1 2 1 8 26 LPC11U35FBD48/401 64 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U35FBD64/401 64 4 8 2 - 10 no 1 1 2 1 8 54 LPC11U35FHI33/501 64 4 8 2 2[1] 12 no 1 1 2 1 8 26 LPC11U35FET48/501 64 4 8 2 2[1] 12 no 1 1 2 1 8 40 LPC11U36FBD48/401 96 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U36FBD64/401 96 4 8 2 - 10 no 1 1 2 1 8 54 LPC11U37FBD48/401 128 4 8 2 - 10 no 1 1 2 1 8 40 LPC11U37HFBD64/401 128 4 8 2 2[2] 10 yes 1 1 2 1 8 54 LPC11U37FBD64/501 128 4 8 2 2[1] 12 no 1 1 2 1 8 54 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 5 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 5. Block diagram (1) Not available on HVQFN33 packages. (2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available on TFBGA48, LQFP48, and LQFP64 packages only; CT32B1_CAP1 available in TFBGA48/LQFP64 packages only. (3) LPC11U37HFBD64/401 only. Fig 1. Block diagram SRAM 8/10/12 kB ARM CORTEX-M0 TEST/DEBUG INTERFACE FLASH 40/48/64/96/128 kB HIGH-SPEED GPIO AHB TO APB BRIDGE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS RESET SWD, JTAG LPC11U3x slave slave master slave slave ROM 16 kB slave AHB-LITE BUS GPIO ports 0/1 I/O IOH_[20:0] HANDLER(3) CLKOUT IRC, WDO SYSTEM OSCILLATOR POR PLL0 USB PLL BOD 10-bit ADC USART/ SMARTCARD INTERFACE AD[7:0] RXD TXD CTS, RTS, DTR SCLK GPIO INTERRUPTS 32-bit COUNTER/TIMER 0 CT32B0_MAT[3:0] CT32B0_CAP[1:0](2) 32-bit COUNTER/TIMER 1 CT32B1_MAT[3:0] CT32B1_CAP[1:0](2) DCD, DSR(1), RI(1) 16-bit COUNTER/TIMER 1 WINDOWED WATCHDOG TIMER GPIO GROUP0 INTERRUPTS CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 0 CT16B0_MAT[2:0] CT16B0_CAP[1:0](2) CT16B1_CAP[1:0](2) GPIO pins GPIO pins GPIO pins GPIO GROUP1 INTERRUPTS system bus SSP0 SCK0, SSEL0, MISO0, MOSI0 SSP1 SCK1, SSEL1, MISO1, MOSI1 I2C-BUS IOCON SYSTEM CONTROL PMU SCL, SDA XTALIN XTALOUT USB DEVICE CONTROLLER USB_DP USB_DM USB_VBUS USB_FTOGGLE, USB_CONNECT 002aag345 master slave EEPROM 4 kB LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 6 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning For parts LPC11U34FHN33/311, LPC11U34FHN33/421, LPC11U35FHN33/401, LPC11U35FHI33/501 Fig 2. Pin configuration (HVQFN33) 002aag809 Transparent top view PIO0_8/MISO0/CT16B0_MAT0 PIO0_20/CT16B1_CAP0 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_9/MOSI0/CT16B0_MAT1 VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2 XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1 XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 PIO0_3/USB_VBUS PIO0_4/SCL PIO0_5/SDA PIO0_21/CT16B1_MAT0/MOSI1 USB_DM USB_DP PIO0_6/USB_CONNECT/SCK0 PIO0_7/CTS PIO0_19/TXD/CT32B0_MAT1 PIO0_18/RXD/CT32B0_MAT0 PIO0_17/RTS/CT32B0_CAP0/SCLK VDD PIO1_15/DCD/CT16B0_MAT2/SCK1 PIO0_23/AD7 PIO0_16/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO0_15/AD4/CT32B1_MAT2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 VSS LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 7 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 3. Pin configuration (TFBGA48) 002aag810 LPC11U35FET48/501 Transparent top view H G F D B E C A 1 2 3 4 5 6 7 8 ball A1 index area LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 8 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 4. Pin configuration (LQFP48) LPC11U34FBD48/311 LPC11U34FBD48/421 LPC11U35FBD48/401 LPC11U36FBD48/401 LPC11U37FBD48/401 PIO1_25/CT32B0_MAT1 PIO1_13/DTR/CT16B0_MAT0/TXD PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 VSS TDI/PIO0_11/AD0/CT32B0_MAT3 XTALIN PIO1_29/SCK0/CT32B0_CAP1 XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1 VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_20/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0 PIO1_26/CT32B0_MAT2/RXD PIO1_21/DCD/MISO1 PIO1_27/CT32B0_MAT3/TXD PIO1_31 PIO1_20/DSR/SCK1 PIO1_16/RI/CT16B0_CAP0 PIO0_3/USB_VBUS PIO0_19/TXD/CT32B0_MAT1 PIO0_4/SCL PIO0_18/RXD/CT32B0_MAT0 PIO0_5/SDA PIO0_17/RTS/CT32B0_CAP0/SCLK PIO0_21/CT16B1_MAT0/MOSI1 VDD PIO1_23/CT16B1_MAT1/SSEL1 PIO1_15/DCD/CT16B0_MAT2/SCK1 USB_DM PIO0_23/AD7 USB_DP VSS PIO1_24/CT32B0_MAT0 PIO0_16/AD5/CT32B1_MAT3/WAKEUP PIO0_6/USB_CONNECT/SCK0 SWDIO/PIO0_15/AD4/CT32B1_MAT2 PIO0_7/CTS PIO1_28/CT32B0_CAP0/SCLK PIO1_22/RI/MOSI1 PIO1_14/DSR/CT16B0_MAT1/RXD 002aag811 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 24 37 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 9 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller See Table 3 for the full pin name. Fig 5. Pin configuration (LQFP64) LPC11U35FBD64/401 LPC11U36FBD64/401 LPC11U37HFBD64/401 LPC11U37FBD64/501 PIO1_0 VDD PIO1_25 PIO1_13 PIO1_19 TRST/PIO0_14 RESET/PIO0_0 TDO/PIO0_13 PIO0_1 TMS/PIO0_12 PIO1_7 PIO1_11 VSS TDI/PIO0_11 XTALIN PIO1_29 XTALOUT PIO0_22 VDD PIO1_8 PIO0_20 SWCLK/PIO0_10 PIO1_10 PIO0_9 PIO0_2 PIO0_8 PIO1_26 PIO1_21 PIO1_27 PIO1_2 PIO1_4 VDD PIO1_1 PIO1_6 PIO1_20 PIO1_16 PIO0_3 PIO0_19 PIO0_4 PIO0_18 PIO0_5 PIO0_17 PIO0_21 PIO1_12 PIO1_17 VDD PIO1_23 PIO1_15 USB_DM PIO0_23 USB_DP PIO1_9 PIO1_24 VSS PIO1_18 PIO0_16 PIO0_6 SWDIO/PIO0_15 PIO0_7 PIO1_22 PIO1_28 PIO1_3 PIO1_5 PIO1_14 002aag812 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 10 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO port number. The default function after reset is listed first. All port pins have internal pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and PIO0_5. Every port pin has a corresponding IOCON register for programming the digital or analog function, the pull-up/pull-down configuration, the repeater, and the open-drain modes. The USART, counter/timer, and SSP functions are available on more than one port pin. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description RESET/PIO0_0 2 C1 3 4 [2] I; PU I RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. This pin also serves as the debug select input. LOW level selects the JTAG boundary scan. HIGH level selects the ARM SWD debug mode. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. - I/O PIO0_0 — General purpose digital input/output pin. PIO0_1/CLKOUT/ CT32B0_MAT2/ USB_FTOGGLE 3 C2 4 5 [3] I; PU I/O PIO0_1 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration. - O CLKOUT — Clockout pin. - O CT32B0_MAT2 — Match output 2 for 32-bit timer 0. - O USB_FTOGGLE — USB 1 ms Start-of-Frame signal. PIO0_2/SSEL0/ CT16B0_CAP0/IOH_0 8 F1 10 13 [3] I; PU I/O PIO0_2 — General purpose digital input/output pin. - I/O SSEL0 — Slave select for SSP0. - I CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. - I/O IOH_0 — I/O Handler input/output 0. LPC11U37HFBD64/401 only. PIO0_3/USB_VBUS/ IOH_1 9 H2 14 19 [3] I; PU I/O PIO0_3 — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. A HIGH level during reset starts the USB device enumeration. - I USB_VBUS — Monitors the presence of USB bus power. - I/O IOH_1 — I/O Handler input/output 1. LPC11U37HFBD64/401 only. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 11 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO0_4/SCL/IOH_2 10 G3 15 20 [4] I; IA I/O PIO0_4 — General purpose digital input/output pin (open-drain). - I/O SCL — I2C-bus clock input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. - I/O IOH_2 — I/O Handler input/output 2. LPC11U37HFBD64/401 only. PIO0_5/SDA/IOH_3 11 H3 16 21 [4] I; IA I/O PIO0_5 — General purpose digital input/output pin (open-drain). - I/O SDA — I2C-bus data input/output (open-drain). High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. - I/O IOH_3 — I/O Handler input/output 3. LPC11U37HFBD64/401 only. PIO0_6/USB_CONNECT/ SCK0/IOH_4 15 H6 22 29 [3] I; PU I/O PIO0_6 — General purpose digital input/output pin. - O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. - I/O SCK0 — Serial clock for SSP0. - I/O IOH_4 — I/O Handler input/output 4. LPC11U37HFBD64/401 only. PIO0_7/CTS/IOH_5 16 G7 23 30 [5] I; PU I/O PIO0_7 — General purpose digital input/output pin (high-current output driver). - I CTS — Clear To Send input for USART. - I/O IOH_5 — I/O Handler input/output 5. (LPC11U37HFBD64/401 only.) PIO0_8/MISO0/ CT16B0_MAT0/R/IOH_6 17 F8 27 36 [3] I; PU I/O PIO0_8 — General purpose digital input/output pin. - I/O MISO0 — Master In Slave Out for SSP0. - O CT16B0_MAT0 — Match output 0 for 16-bit timer 0. - - Reserved. - I/O IOH_6 — I/O Handler input/output 6. (LPC11U37HFBD64/401 only.) PIO0_9/MOSI0/ CT16B0_MAT1/R/IOH_7 18 F7 28 37 [3] I; PU I/O PIO0_9 — General purpose digital input/output pin. - I/O MOSI0 — Master Out Slave In for SSP0. - O CT16B0_MAT1 — Match output 1 for 16-bit timer 0. - - Reserved. - I/O IOH_7 — I/O Handler input/output 7. (LPC11U37HFBD64/401 only.) Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 12 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 19 E7 29 38 [3] I; PU I SWCLK — Serial wire clock and test clock TCK for JTAG interface. - I/O PIO0_10 — General purpose digital input/output pin. - O SCK0 — Serial clock for SSP0. - O CT16B0_MAT2 — Match output 2 for 16-bit timer 0. TDI/PIO0_11/AD0/ CT32B0_MAT3 21 D8 32 42 [6] I; PU I TDI — Test Data In for JTAG interface. - I/O PIO0_11 — General purpose digital input/output pin. - I AD0 — A/D converter, input 0. - O CT32B0_MAT3 — Match output 3 for 32-bit timer 0. TMS/PIO0_12/AD1/ CT32B1_CAP0 22 C7 33 44 [6] I; PU I TMS — Test Mode Select for JTAG interface. - I/O PIO_12 — General purpose digital input/output pin. - I AD1 — A/D converter, input 1. - I CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. TDO/PIO0_13/AD2/ CT32B1_MAT0 23 C8 34 45 [6] I; PU O TDO — Test Data Out for JTAG interface. - I/O PIO0_13 — General purpose digital input/output pin. - I AD2 — A/D converter, input 2. - O CT32B1_MAT0 — Match output 0 for 32-bit timer 1. TRST/PIO0_14/AD3/ CT32B1_MAT1 24 B7 35 46 [6] I; PU I TRST — Test Reset for JTAG interface. - I/O PIO0_14 — General purpose digital input/output pin. - I AD3 — A/D converter, input 3. - O CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO0_15/AD4/ CT32B1_MAT2 25 B6 39 52 [6] I; PU I/O SWDIO — Serial wire debug input/output. - I/O PIO0_15 — General purpose digital input/output pin. - I AD4 — A/D converter, input 4. - O CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO0_16/AD5/ CT32B1_MAT3/IOH_8/ WAKEUP 26 A6 40 53 [6] I; PU I/O PIO0_16 — General purpose digital input/output pin. - I AD5 — A/D converter, input 5. - O CT32B1_MAT3 — Match output 3 for 32-bit timer 1. - I/O IOH_8 — I/O Handler input/output 8. (LPC11U37HFBD64/401 only.) - I WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode, then pull LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 13 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO0_17/RTS/ CT32B0_CAP0/SCLK 30 A3 45 60 [3] I; PU I/O PIO0_17 — General purpose digital input/output pin. - O RTS — Request To Send output for USART. - I CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. - I/O SCLK — Serial clock input/output for USART in synchronous mode. PIO0_18/RXD/ CT32B0_MAT0 31 B3 46 61 [3] I; PU I/O PIO0_18 — General purpose digital input/output pin. - I RXD — Receiver input for USART. Used in UART ISP mode. - O CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO0_19/TXD/ CT32B0_MAT1 32 B2 47 62 [3] I; PU I/O PIO0_19 — General purpose digital input/output pin. - O TXD — Transmitter output for USART. Used in UART ISP mode. - O CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO0_20/CT16B1_CAP0 7 F2 9 11 [3] I; PU I/O PIO0_20 — General purpose digital input/output pin. - I CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO0_21/CT16B1_MAT0/ MOSI1 12 G4 17 22 [3] I; PU I/O PIO0_21 — General purpose digital input/output pin. - O CT16B1_MAT0 — Match output 0 for 16-bit timer 1. - I/O MOSI1 — Master Out Slave In for SSP1. PIO0_22/AD6/ CT16B1_MAT1/MISO1 20 E8 30 40 [6] I; PU I/O PIO0_22 — General purpose digital input/output pin. - I AD6 — A/D converter, input 6. - O CT16B1_MAT1 — Match output 1 for 16-bit timer 1. - I/O MISO1 — Master In Slave Out for SSP1. PIO0_23/AD7/IOH_9 27 A5 42 56 [6] I; PU I/O PIO0_23 — General purpose digital input/output pin. - I AD7 — A/D converter, input 7. - I/O IOH_9 — I/O Handler input/output 9. (LPC11U37HFBD64/401 only.) PIO1_0/CT32B1_MAT0/ IOH_10 - - - 1 [3] I; PU I/O PIO1_0 — General purpose digital input/output pin. - O CT32B1_MAT0 — Match output 0 for 32-bit timer 1. - I/O IOH_10 — I/O Handler input/output 10. (LPC11U37HFBD64/401 only.) PIO1_1/CT32B1_MAT1/ IOH_11 - - - 17 [3] I; PU I/O PIO1_1 — General purpose digital input/output pin. - O CT32B1_MAT1 — Match output 1 for 32-bit timer 1. - I/O IOH_11 — I/O Handler input/output 11. (LPC11U37HFBD64/401 only.) PIO1_2/CT32B1_MAT2/ IOH_12 - - - 34 [3] I; PU I/O PIO1_2 — General purpose digital input/output pin. - O CT32B1_MAT2 — Match output 2 for 32-bit timer 1. - I/O IOH_12 — I/O Handler input/output 12. (LPC11U37HFBD64/401 only.) Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 14 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO1_3/CT32B1_MAT3/ IOH_13 - - - 50 [3] I; PU I/O PIO1_3 — General purpose digital input/output pin. - O CT32B1_MAT3 — Match output 3 for 32-bit timer 1. - I/O IOH_13 — I/O Handler input/output 13. (LPC11U37HFBD64/401 only.) PIO1_4/CT32B1_CAP0/ IOH_14 - - - 16 [3] I; PU I/O PIO1_4 — General purpose digital input/output pin. - I CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. - I/O IOH_14 — I/O Handler input/output 14. (LPC11U37HFBD64/401 only.) PIO1_5/CT32B1_CAP1 /IOH_15 - H8 - 32 [3] I; PU I/O PIO1_5 — General purpose digital input/output pin. - I CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. - I/O IOH_15 — I/O Handler input/output 15. (LPC11U37HFBD64/401 only.) PIO1_6/IOH_16 - - - 64 [3] I; PU I/O PIO1_6 — General purpose digital input/output pin. - I/O IOH_16 — I/O Handler input/output 16. (LPC11U37HFBD64/401 only.) PIO1_7/IOH_17 - - - 6 [3] I; PU I/O PIO1_7 — General purpose digital input/output pin. - I/O IOH_17 — I/O Handler input/output 17. (LPC11U37HFBD64/401 only.) PIO1_8/IOH_18 - - - 39 [3] I; PU I/O PIO1_8 — General purpose digital input/output pin. - I/O IOH_18 — I/O Handler input/output 18. (LPC11U37HFBD64/401 only.) PIO1_9 - - - 55 [3] I; PU I/O PIO1_9 — General purpose digital input/output pin. PIO1_10 - - - 12 [3] I; PU I/O PIO1_10 — General purpose digital input/output pin. PIO1_11 - - - 43 [3] I; PU I/O PIO1_11 — General purpose digital input/output pin. PIO1_12 - - - 59 [3] I; PU I/O PIO1_12 — General purpose digital input/output pin. PIO1_13/DTR/ CT16B0_MAT0/TXD - B8 36 47 [3] I; PU I/O PIO1_13 — General purpose digital input/output pin. - O DTR — Data Terminal Ready output for USART. - O CT16B0_MAT0 — Match output 0 for 16-bit timer 0. - O TXD — Transmitter output for USART. PIO1_14/DSR/ CT16B0_MAT1/RXD - A8 37 49 [3] I; PU I/O PIO1_14 — General purpose digital input/output pin. - I DSR — Data Set Ready input for USART. - O CT16B0_MAT1 — Match output 1 for 16-bit timer 0. - I RXD — Receiver input for USART. PIO1_15/DCD/ CT16B0_MAT2/SCK1 28 A4 43 57 [3] I; PU I/O PIO1_15 — General purpose digital input/output pin. I DCD — Data Carrier Detect input for USART. - O CT16B0_MAT2 — Match output 2 for 16-bit timer 0. - I/O SCK1 — Serial clock for SSP1. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 15 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller PIO1_16/RI/ CT16B0_CAP0 - A2 48 63 [3] I; PU I/O PIO1_16 — General purpose digital input/output pin. - I RI — Ring Indicator input for USART. - I CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO1_17/CT16B0_CAP1/ RXD - - - 23 [3] I; PU I/O PIO1_17 — General purpose digital input/output pin. - I CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. - I RXD — Receiver input for USART. PIO1_18/CT16B1_CAP1/ TXD - - - 28 [3] I; PU I/O PIO1_18 — General purpose digital input/output pin. - I CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. - O TXD — Transmitter output for USART. PIO1_19/DTR/SSEL1 1 B1 2 3 [3] I; PU I/O PIO1_19 — General purpose digital input/output pin. - O DTR — Data Terminal Ready output for USART. - I/O SSEL1 — Slave select for SSP1. PIO1_20/DSR/SCK1 - H1 13 18 [3] I; PU I/O PIO1_20 — General purpose digital input/output pin. - I DSR — Data Set Ready input for USART. - I/O SCK1 — Serial clock for SSP1. PIO1_21/DCD/MISO1 - G8 26 35 [3] I; PU I/O PIO1_21 — General purpose digital input/output pin. - I DCD — Data Carrier Detect input for USART. - I/O MISO1 — Master In Slave Out for SSP1. PIO1_22/RI/MOSI1 - A7 38 51 [3] I; PU I/O PIO1_22 — General purpose digital input/output pin. - I RI — Ring Indicator input for USART. - I/O MOSI1 — Master Out Slave In for SSP1. PIO1_23/CT16B1_MAT1/ SSEL1 - H4 18 24 [3] I; PU I/O PIO1_23 — General purpose digital input/output pin. - O CT16B1_MAT1 — Match output 1 for 16-bit timer 1. - I/O SSEL1 — Slave select for SSP1. PIO1_24/CT32B0_MAT0 - G6 21 27 [3] I; PU I/O PIO1_24 — General purpose digital input/output pin. - O CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_25/CT32B0_MAT1 - A1 1 2 [3] I; PU I/O PIO1_25 — General purpose digital input/output pin. - O CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_26/CT32B0_MAT2/ RXD/IOH_19 - G2 11 14 [3] I; PU I/O PIO1_26 — General purpose digital input/output pin. - O CT32B0_MAT2 — Match output 2 for 32-bit timer 0. - I RXD — Receiver input for USART. - I/O IOH_19 — I/O Handler input/output 19. (LPC11U37HFBD64/401 only.) PIO1_27/CT32B0_MAT3/ TXD/IOH_20 - G1 12 15 [3] I; PU I/O PIO1_27 — General purpose digital input/output pin. - O CT32B0_MAT3 — Match output 3 for 32-bit timer 0. - O TXD — Transmitter output for USART. - I/O IOH_20 — I/O Handler input/output 20. (LPC11U37HFBD64/401 only.) Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 16 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F = floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 32 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31). [4] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31); includes high-current output driver. [6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31); includes digital input glitch filter. [7] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [8] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating. PIO1_28/CT32B0_CAP0/ SCLK - H7 24 31 [3] I; PU I/O PIO1_28 — General purpose digital input/output pin. - I CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. - I/O SCLK — Serial clock input/output for USART in synchronous mode. PIO1_29/SCK0/ CT32B0_CAP1 - D7 31 41 [3] I; PU I/O PIO1_29 — General purpose digital input/output pin. - I/O SCK0 — Serial clock for SSP0. - I CT32B0_CAP1 — Capture input 1 for 32-bit timer 0. PIO1_31 - - 25 - [3] I; PU I/O PIO1_31 — General purpose digital input/output pin. USB_DM 13 G5 19 25 [7] F - USB_DM — USB bidirectional D line. USB_DP 14 H5 20 26 [7] F - USB_DP — USB bidirectional D+ line. XTALIN 4 D1 6 8 [8] - - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5 E1 7 9 [8] - - Output from the oscillator amplifier. VDD 6; 29 B4; E2 8; 44 10; 33; 48; 58 - - Supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. VSS 33 B5; D2 5; 41 7; 54 - - Ground. Table 3. Pin description Symbol Pin HVQFN33 Pin TFBGA48 Pin LQFP48 Pin LQFP64 Reset state [1] Type Description LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 17 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 On-chip flash programming memory The LPC11U3x contain up to 128 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages. Individual pages can be erased using the IAP erase page command. 7.2 EEPROM The LPC11U3x contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM data memory. The EEPROM can be programmed using In-Application Programming (IAP) via the on-chip boot loader software. 7.3 SRAM The LPC11U3x contain a total of 8 kB, 10 kB, or 12 kB on-chip static RAM memory. On the LPC11U37HFBD64/401, the 2 kB SRAM1 region at location 0x2000 0000 to 0x2000 07FFF is used for the I/O Handler software library. Do not use this memory location for data or other user code. 7.4 On-chip ROM The on-chip ROM contains the boot loader and the following Application Programming Interfaces (APIs): • In-System Programming (ISP) and In-Application Programming (IAP) support for flash including IAP erase page command. • IAP support for EEPROM • USB API • Power profiles for configuring power consumption and PLL settings • 32-bit integer division routines 7.5 Memory map The LPC11U3x incorporates several distinct memory regions, shown in the following figures. Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This addressing scheme allows simplifying the address decoding for each peripheral. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 18 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.6.1 Features • Controls system exceptions and peripheral interrupts. • In the LPC11U3x, the NVIC supports 24 vectored interrupts. Fig 6. LPC11U3x memory map APB peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4004 C000 0x4005 8000 0x4005 C000 0x4006 0000 0x4006 4000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 0x4000 0000 WWDT 32-bit counter/timer 0 32-bit counter/timer 1 ADC USART/SMART CARD PMU I2C-bus 20 - 21 reserved 10 - 13 reserved reserved reserved 25 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x1000 0000 0x1FFF 0000 0x1FFF 4000 0x2000 0000 0x5000 0000 0x5000 4000 0xFFFF FFFF reserved reserved reserved 2 kB USB RAM (LPC11U34/421 LPC11U35/401/501 LPC11U36/401/501 LPC11U37/401/501, LPC11U37H/401) reserved 0x4000 0000 0x4008 0000 0x4008 4000 APB peripherals USB GPIO 0x2000 4000 0x2000 4800 0x1000 2000 8 kB SRAM0 (LPC11U3x) LPC11U3x 0x0000 A000 40 kB on-chip flash (LPC11U34/311) 0x0000 C000 48 kB on-chip flash (LPC11U34/421) 0x0001 0000 64 kB on-chip flash (LPC11U35) 0x0001 8000 96 kB on-chip flash (LPC11U36) 0x0002 0000 128 kB on-chip flash (LPC11U37/7H) 16 kB boot ROM 0x0000 0000 0x0000 00C0 active interrupt vectors 002aag813 reserved reserved SSP0 SSP1 16-bit counter/timer 1 16-bit counter/timer 0 IOCON system control 19 GPIO interrupts 22 23 GPIO GROUP0 INT 24 GPIO GROUP1 INT flash/EEPROM controller 0xE000 0000 0xE010 0000 private peripheral bus 2 kB SRAM1 (LPC11U35/501 LPC11U37/501) I/O Handler code area for LPC11U37HFBD64/401 0x2000 0800 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 19 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 7.7 IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Connect peripherals to the appropriate pins before activating the peripheral and before enabling any related interrupt. Activity of any enabled peripheral function that is not mapped to a related pin is treated as undefined. 7.7.1 Features • Programmable pull-up, pull-down, or repeater mode. • All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their pull-up resistor is enabled. • Programmable pseudo open-drain mode. • Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to PIO0_16. The glitch filter is turned on by default. • Programmable hysteresis. • Programmable input inverter. 7.8 General-Purpose Input/Output GPIO The GPIO registers control device pin functions that are not connected to a specific peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC11U3x use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • Entire port value can be written in one instruction. Any GPIO pin providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. The GPIO block consists of three parts: 1. The GPIO ports. 2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts. 3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO pins. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 20 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.8.1 Features • GPIO pins can be configured as input or output by software. • All GPIO pins default to inputs with interrupt disabled at reset. • Pin registers allow pins to be sensed and set individually. • Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request. • Any pin or pins in each port can trigger a port interrupt. 7.9 USB interface The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of the devices. The host controller initiates all transactions. The LPC11U3x USB interface consists of a full-speed device controller with on-chip PHY (PHYsical layer) for device functions. Remark: Configure the LPC11U3x in default power mode with the power profiles before using the USB (see Section 7.18.5.1). Do not use the USB with the part in performance, efficiency, or low-power mode. 7.9.1 Full-speed USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. If enabled, an interrupt is generated. 7.9.1.1 Features • Dedicated USB PLL available. • Fully compliant with USB 2.0 specification (full speed). • Supports 10 physical (5 logical) endpoints including one control endpoint. • Single and double buffering supported. • Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. • Supports wake-up from Deep-sleep mode and Power-down mode on USB activity and remote wake-up. • Supports SoftConnect. 7.10 I/O Handler (LPC11U37HFBD64/401 only) The I/O Handler is a software library-supported hardware engine for emulating serial interfaces and off-loading the CPU for processing-intensive functions. The I/O Handler can emulate, among others, DMA and serial interfaces such as UART, I2C, or I2S with no or very low additional CPU load. The software libraries are available with supporting LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 21 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller application notes from NXP (see http://www.LPCware.com.) LPCXpresso, Keil, and IAR IDEs are supported. I/O Handler library code must be executed from the memory area 0x2000 0000 to 0x2000 07FF. This memory is not available for other use. For application examples, see Section 11.8 “I/O Handler software library applications”. Each I/O Handler library uses a specific subset of I/O Handler pins and in some cases other pins and peripherals such as the counter/timers. 7.11 USART The LPC11U3x contains one USART. The USART includes full modem control, support for synchronous mode, and a smart card interface. The RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The USART uses a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.11.1 Features • Maximum USART data bit rate of 3.125 Mbit/s. • 16 byte receive and transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode. • Support for modem control. • Support for synchronous mode. • Includes smart card interface. 7.12 SSP serial I/O controller The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. The controller can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.12.1 Features • Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) • Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 22 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 7.13 I2C-bus serial I/O controller The LPC11U3x contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, and more than one bus master connected to the interface can be controlled the bus. 7.13.1 Features • The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.14 10-bit ADC The LPC11U3x contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.14.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range 0 V to VDD. • 10-bit conversion time  2.44 s (up to 400 kSamples/s). • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 23 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.15 General purpose external event counter/timers The LPC11U3x includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.15.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • Up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event can also generate an interrupt. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • The timer and prescaler can be configured to be cleared on a designated capture event. This feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. 7.16 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.17 Windowed WatchDog Timer (WWDT) The purpose of the WWDT is to prevent an unresponsive system state. If software fails to update the watchdog within a programmable time window, the watchdog resets the microcontroller 7.17.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time before watchdog time-out. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 24 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller • Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is required to disable the WWDT. • Incorrect feed sequence causes reset or interrupt, if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). The clock source selection provides a wide range of potential timing choices of watchdog operation under different power conditions. 7.18 Clocking and power control 7.18.1 Integrated oscillators The LPC11U3x include three independent oscillators: the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11U3x operates from the internal RC oscillator until software switches to a different clock source. The IRC allows the system to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 7 for an overview of the LPC11U3x clock generation. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 25 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.18.1.1 Internal RC oscillator The IRC can be used as the clock source for the WDT, and/or as the clock that drives the system PLL and then the CPU. The nominal IRC frequency is 12 MHz. Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U3x use the IRC as the clock source. Software can later switch to one of the other available clock sources. Fig 7. LPC11U3x clocking generation block diagram system oscillator watchdog oscillator IRC oscillator USB PLL USBPLLCLKSEL (USB clock select) SYSTEM CLOCK DIVIDER SYSAHBCLKCTRLn (AHB clock enable) CPU, system control, PMU memories, peripheral clocks SSP0 PERIPHERAL CLOCK DIVIDER SSP0 SSP1 PERIPHERAL CLOCK DIVIDER SSP1 USART PERIPHERAL CLOCK DIVIDER UART WDT WDCLKSEL (WDT clock select) USB 48 MHz CLOCK DIVIDER USB USBUEN (USB clock update enable) watchdog oscillator IRC oscillator system oscillator CLKOUT PIN CLOCK DIVIDER CLKOUT pin CLKOUTUEN (CLKOUT update enable) 002aaf892 system clock SYSTEM PLL IRC oscillator system oscillator watchdog oscillator MAINCLKSEL (main clock select) SYSPLLCLKSEL (system PLL clock select) main clock IRC oscillator n LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 26 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.18.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. On the LPC11U3x, use the system oscillator to provide the clock source to USB. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 7.18.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and temperature is 40 % (see also Table 13). 7.18.2 System PLL and USB PLL The LPC11U3x contain a system PLL and a dedicated PLL for generating the 48 MHz USB clock. The system and USB PLLs are identical. The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz. To support this frequency range, an additional divider keeps the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset. Software can enable the PLL later. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.18.3 Clock output The LPC11U3x feature a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.18.4 Wake-up process The LPC11U3x begin operation by using the 12 MHz IRC oscillator as the clock source at power-up and when awakened from Deep power-down mode . This mechanism allows chip operation to resume quickly. If the application uses the main oscillator or the PLL, software must enable these components and wait for them to stabilize. Only then can the system use the PLL and main oscillator as a clock source. 7.18.5 Power control The LPC11U3x support various power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate can also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This power control mechanism allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals. This register allows fine-tuning of power LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 27 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.18.5.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC11U3x for one of the following power modes: • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. Remark: When using the USB, configure the LPC11U3x in Default mode. 7.18.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, by memory systems and related controllers, and by internal buses. 7.18.5.3 Deep-sleep mode In Deep-sleep mode, the LPC11U3x is in Sleep-mode and all peripheral clocks and all clock sources are off except for the IRC. The IRC output is disabled unless the IRC is selected as input to the watchdog timer. In addition all analog blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC11U3x can wake up from Deep-sleep mode via reset, selected GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity. Deep-sleep mode saves power and allows for short wake-up times. 7.18.5.4 Power-down mode In Power-down mode, the LPC11U3x is in Sleep-mode and all peripheral clocks and all clock sources are off except for watchdog oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the application can keep the BOD circuit running for BOD protection. The LPC11U3x can wake up from Power-down mode via reset, selected GPIO pins, a watchdog timer interrupt, or an interrupt generating USB port activity. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 28 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 7.18.5.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin. The LPC11U3x can wake up from Deep power-down mode via the WAKEUP pin. The LPC11U3x can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block. Locking out Deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 7.18.6 System control 7.18.6.1 Reset Reset has four sources on the LPC11U3x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In Deep power-down mode, an external pull-up resistor is required on the RESET pin. 7.18.6.2 Brownout detection The LPC11U3x includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. 7.18.6.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details, see the LPC11Uxx user manual. There are three levels of Code Read Protection: LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 29 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details, see the LPC11Uxx user manual. 7.18.6.4 APB interface The APB peripherals are located on one APB bus. 7.18.6.5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the ROM. 7.18.6.6 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 30 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 7.19 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC11U3x is in reset. To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 31 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 8. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 5. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 5) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 6 for maximum operating voltage. [4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [5] Including voltage on outputs in 3-state mode. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD supply voltage (core and external rail) [2] 0.5 +4.6 V VI input voltage 5 V tolerant digital I/O pins; VDD  1.8 V [5][2] 0.5 +5.5 V VDD = 0 V 0.5 +3.6 V 5 V tolerant open-drain pins PIO0_4 and PIO0_5 [2][4] 0.5 +5.5 VIA analog input voltage pin configured as analog input [2] [3] 0.5 4.6 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); Tj < 125 C - 100 mA Tstg storage temperature non-operating [6] 65 +150 C Tj(max) maximum junction temperature - 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7]- +6500 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 32 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD supply voltage (core and external rail) [2] 1.8 3.3 3.6 V IDD supply current Active mode; VDD = 3.3 V; Tamb = 25 C; code while(1){} executed from flash; system clock = 12 MHz [3][4][5] [6][7][8] - 2 - mA system clock = 50 MHz [4][5][6] [7][8][9] - 7 - mA Sleep mode; VDD = 3.3 V; Tamb = 25 C; system clock = 12 MHz [3][4][5] [6][7][8] - 1 - mA Deep-sleep mode; VDD = 3.3 V; Tamb = 25 C [4][7]- 300 - A Power-down mode; VDD = 3.3 V; Tamb = 25 C - 2 - A Deep power-down mode; VDD = 3.3 V; Tamb = 25 C [10]- 220 - nA Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function; VDD  1.8 V [11] [12] 0 - 5.0 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 2.0 V  VDD  3.6 V; IOH = 4 mA VDD  0.4- - V 1.8 V  VDD < 2.0 V; IOH = 3 mA VDD  0.4- - V VOL LOW-level output voltage 2.0 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.0 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.0 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.0 V 3 - - mA LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 33 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller IOL LOW-level output current VOL = 0.4 V 2.0 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.0 V 3 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [13]- - 45 mA IOLS LOW-level short-circuit output current VOL = VDD [13]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 2.0 V  VDD  3.6 V 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A High-drive output pin (PIO0_7) IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function; VDD  1.8 V [11] [12] 0 - 5.0 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4- - V 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4- - V VOL LOW-level output voltage 2.0 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.0 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 12 - - mA IOL LOW-level output current VOL = 0.4 V 2.0 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.0 V 3 - - mA IOLS LOW-level short-circuit output current VOL = VDD [13]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 34 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Ipu pull-up current VI = 0 V 2.0 V  VDD  3.6 V 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as standard mode pins 2.0 V  VDD  3.6 V 3.5 - - mA 1.8 V  VDD < 2.0 V 3 - - IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins 2.0 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.0 V 16 - - ILI input leakage current VI = VDD [14]- 2 4 A VI = 5 V - 10 22 A Oscillator pins Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V USB pins IOZ OFF-state output current 0 V < VI < 3.3 V [2]- - 10 A VBUS bus supply voltage [2]- - 5.25 V VDI differential input sensitivity voltage (D+)  (D) [2] 0.2 - - V VCM differential common mode voltage range includes VDI range [2] 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage [2] 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed; RL of 1.5 k to 3.6 V [2]- - 0.18 V VOH HIGH-level output voltage driven; for low-/full-speed; RL of 15 k to GND [2] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [2]- - 20 pF ZDRV driver output impedance for driver which is not high-speed capable with 33  series resistor; steady state drive [15][2] 36 - 44.1  Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 35 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  VDD  3.6 V. Guaranteed by design. [3] IRC enabled; system oscillator disabled; system PLL disabled. [4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [5] BOD disabled. [6] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the SYSCON block. [7] USB_DP and USB_DM pulled LOW externally. [8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [9] IRC disabled; system oscillator enabled; system PLL enabled. [10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. [11] Including voltage on outputs in 3-state mode. [12] 3-state outputs go into 3-state mode in Deep power-down mode. [13] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [14] To VSS. [15] Includes external resistors of 33   1 % on USB_DP and USB_DM. Pin capacitance Cio input/output capacitance pins configured for analog function - - 7.1 pF I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF pins configured as GPIO - - 2.8 pF Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 36 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8. [3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 8. [4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 8. [5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 8. [6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 8. [7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). Table 6. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2]- - 1 LSB EL(adj) integral non-linearity [3]- - 1.5 LSB EO offset error [4]- - 3.5 LSB EG gain error [5]- - 0.6 % ET absolute error [6]- - 4 LSB Rvsi voltage source interface resistance - - 40 k Ri input resistance [7][8]- - 2.5 M LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 37 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 8. ADC characteristics 002aaf426 1023 1022 1021 1020 1019 (2) (1) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 LSB (ideal) code out VDD − VSS 1024 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 38 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the LPC11Uxx user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see the LPC11Uxx user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage interrupt level 1 assertion - 2.22 - V de-assertion - 2.35 - V interrupt level 2 assertion - 2.52 - V de-assertion - 2.66 - V interrupt level 3 assertion - 2.80 - V de-assertion - 2.90 - V reset level 0 assertion - 1.46 - V de-assertion - 1.63 - V reset level 1 assertion - 2.06 - V de-assertion - 2.15 - V reset level 2 assertion - 2.35 - V de-assertion - 2.43 - V reset level 3 assertion - 2.63 - V de-assertion - 2.71 - V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 39 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: Tamb = 25 C; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. Typical supply current versus regulator supply voltage VDD in active mode Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 10. Typical supply current versus temperature in Active mode VDD (V) 1.8 2.4 3.0 3.6 002aag749 3 6 9 IDD (mA) 0 12 MHz(1) 24 MHz(2) 36 MHz(2) 48 MHz(2) temperature (°C) -40 -15 10 35 60 85 002aag750 3 6 9 IDD (mA) 0 12 MHz(1) 24 MHz(2) 36 MHz(2) 48 MHz(2) LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 40 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 11. Typical supply current versus temperature in Sleep mode Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally. Fig 12. Typical supply current versus temperature in Deep-sleep mode 002aag751 temperature (°C) -40 -15 10 35 60 85 1 3 2 4 IDD (mA) 0 12 MHz(1) 36 MHz(2) 48 MHz(2) 24 MHz(2) 002aag745 temperature (°C) -40 -15 10 35 60 85 355 375 365 385 IDD (μA) 345 VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 41 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG register; USB_DP and USB_DM pulled LOW externally. Fig 13. Typical supply current versus temperature in Power-down mode Fig 14. Typical supply current versus temperature in Deep power-down mode 002aag746 temperature (°C) -40 -15 10 35 60 85 5 15 10 20 IDD (μA) 0 VDD = 3.6 V, 3.3 V VDD = 2.0 V VDD = 1.8 V 002aag747 temperature (°C) -40 -15 10 35 60 85 0.2 0.6 0.4 0.8 IDD (μA) 0 VDD = 3.6 V VDD = 3.3 V VDD = 2.0 V VDD = 1.8 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 42 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Table 8. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.22 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.004 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.051 - - Independent of main clock frequency. Main PLL - 0.21 - - ADC - 0.08 0.29 - CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV register. CT16B0 - 0.02 0.06 - CT16B1 - 0.02 0.06 - CT32B0 - 0.02 0.07 - CT32B1 - 0.02 0.06 - GPIO - 0.23 0.88 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. IOCONFIG - 0.03 0.10 - I2C - 0.04 0.13 - ROM - 0.04 0.15 - SPI0 - 0.12 0.45 - SPI1 - 0.12 0.45 - UART - 0.22 0.82 - WWDT - 0.02 0.06 Main clock selected as clock source for the WDT. USB - - 1.2 - LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 43 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 9.4 Electrical pin characteristics Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 15. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 16. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL IOH (mA) 0 10 20 30 40 50 60 002aae990 2.8 2.4 3.2 3.6 VOH (V) 2 T = 85 °C 25 °C −40 °C VOL (V) 0 0.2 0.4 0.6 002aaf019 20 40 60 IOL (mA) 0 T = 85 °C 25 °C −40 °C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 44 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL Conditions: VDD = 3.3 V; standard port pins. Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH VOL (V) 0 0.2 0.4 0.6 002aae991 5 10 15 IOL (mA) 0 T = 85 °C 25 °C −40 °C IOH (mA) 0 8 16 24 002aae992 2.8 2.4 3.2 3.6 VOH (V) 2 T = 85 °C 25 °C −40 °C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 45 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Conditions: VDD = 3.3 V; standard port pins. Fig 19. Typical pull-up current Ipu versus input voltage VI Conditions: VDD = 3.3 V; standard port pins. Fig 20. Typical pull-down current Ipd versus input voltage VI VI (V) 0 1 2 3 4 5 002aae988 −30 −50 −10 10 Ipu (μA) −70 T = 85 °C 25 °C −40 °C VI (V) 0 1 2 3 4 5 002aae989 40 20 60 80 Ipd (μA) 0 T = 85 °C 25 °C −40 °C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 46 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 10. EEPROM characteristics Tamb = 40 C to +85C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 100000 1000000 - cycles tret retention time powered 100 200 - years unpowered 150 300 - years tprog programming time 64 bytes - 2.9 - ms Table 11. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 47 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. Fig 21. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 Table 12. Dynamic characteristics: IRC Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 22. Internal RC oscillator frequency versus temperature Table 13. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions Min Typ[1] Max Unit fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; [2][3]- 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz 002aaf403 11.95 12.05 12.15 f (MHz) 11.85 temperature (°C) −40 −15 10 35 60 85 VDD = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V 2.0 V LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 48 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +85 C) is 40 %. [3] See the LPC11Uxx user manual. 10.4 I/O pins [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. Table 14. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns Table 15. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [4][5][6][7] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s tHD;DAT data hold time [3][4][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 49 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Fig 23. I2C-bus pins clock timing 002aaf425 tf 70 % SDA 30 % tf 70 % 30 % S 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 70 % 30 % 70 % 30 % tVD;DAT tHIGH tLOW tSU;DAT LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 50 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10.6 SSP interface [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = 40 C to 85 C. [3] Tcy(clk) = 12  Tcy(PCLK). [4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V. Table 16. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master (in SPI mode) Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns when only transmitting [1] 40 ns tDS data set-up time in SPI mode 2.4 V  VDD  3.6 V [2] 15 - - ns 2.0 V  VDD < 2.4 V [2] 20 ns 1.8 V  VDD < 2.0 V [2] 24 - - ns tDH data hold time in SPI mode [2] 0 - - ns tv(Q) data output valid time in SPI mode [2] - - 10 ns th(Q) data output hold time in SPI mode [2] 0 - - ns SPI slave (in SPI mode) Tcy(PCLK) PCLK cycle time 20 - - ns tDS data set-up time in SPI mode [3][4] 0 - - ns tDH data hold time in SPI mode [3][4] 3  Tcy(PCLK) + 4 - - ns tv(Q) data output valid time in SPI mode [3][4] - - 3  Tcy(PCLK) + 11 ns th(Q) data output hold time in SPI mode [3][4] - - 2  Tcy(PCLK) + 5 ns LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 51 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 24. SSP master timing in SPI mode SCK (CPOL = 0) MOSI MISO Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH DATA VALID DATA VALID th(Q) DATA VALID DATA VALID tv(Q) CPHA = 1 CPHA = 0 002aae829 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 52 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 25. SSP slave timing in SPI mode SCK (CPOL = 0) MOSI MISO Tcy(clk) tDS tDH tv(Q) DATA VALID DATA VALID th(Q) SCK (CPOL = 1) DATA VALID DATA VALID MOSI MISO tDS tDH tv(Q) DATA VALID DATA VALID th(Q) DATA VALID DATA VALID CPHA = 1 CPHA = 0 002aae830 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 53 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 10.7 USB interface [1] Characterized but not implemented as production test. Guaranteed by design. Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 26 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 26 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR EOP width at receiver must accept as EOP; see Figure 26 [1] 82 - - ns Fig 26. Differential data-to-EOP transition skew and EOP width aaa-009330 TPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR crossover point extended differential data to SE0/EOP skew n TPERIOD + tFDEOP LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 54 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 Suggested USB interface solutions The USB device can be connected to the USB as self-powered device (see Figure 27) or bus-powered device (see Figure 28). On the LPC11U3x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level. Therefore, if the USB_VBUS function is connected to the USB connector and the device is self-powered, the USB_VBUS pin must be protected for situations when VDD = 0 V. If VDD is always greater than 0 V while VBUS = 5 V, the USB_VBUS pin can be connected directly to the VBUS pin on the USB connector. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum allowable voltage on the USB_VBUS pin in this case. One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. For the following operating conditions VBUSmax = 5.25 V VDD = 3.6 V, the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V. Fig 27. USB interface on a self-powered device where USB_VBUS = 5 V LPC1xxx USB-B connector USB_DP USB_CONNECT soft-connect switch USB_DM USB_VBUS VSS VDD R1 1.5 kΩ RS = 33 Ω aaa-010178 RS = 33 Ω R2 R3 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 55 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller For a bus-powered device, the VBUS signal does not need to be connected to the USB_VBUS pin (see Figure 28). The USB_CONNECT function can additionally be connected as shown in Figure 27 to prevent the USB from timing out when there is a significant delay between power-up and handling USB traffic. Remark: When a bus-powered circuit as shown in Figure 28 is used, configure the PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block to ensure that the USB_CONNECT signal can still be controlled by software. For details on the soft-connect feature, see the LPC11U3x user manual (Ref. 1). Remark: When a self-powered circuit is used without connecting VBUS, configure the PIO0_3/USB_VBUS pin for GPIO (PIO0_3) and provide software that can detect the host presence through some other mechanism before enabling USB_CONNECT and the soft-connect feature. Enabling the soft-connect without host presence will lead to USB compliance failure. Fig 28. USB interface on a bus-powered device LPC1xxx VDD R1 1.5 kΩ aaa-010179 USB-B connector USB_DP USB_DM VSS RS = 33 Ω RS = 33 Ω REGULATOR VBUS LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 56 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV (RMS) is needed. In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 29), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 30 and in Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (L, CL and RS represent the fundamental frequency). Capacitance CP in Figure 30 represents the parallel package capacitance and must not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. Fig 29. Slave mode operation of the on-chip oscillator Fig 30. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation LPC1xxx XTALIN Ci 100 pF Cg 002aae788 002aaf424 LPC1xxx XTALIN XTALOUT CX1 CX2 XTAL = CL CP RS L LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 57 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines Follow these guidelines for PCB layout: • Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip. • Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal use have a common ground plane. • Connect the external components to the ground plain. • To keep parasitics and the noise coupled in via the PCB as small as possible, keep loops as small as possible. • Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase. Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 19. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 58 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.4 Standard I/O pad configuration Figure 31 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input Fig 31. Standard I/O pad configuration PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns RC GLITCH FILTER LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 59 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.5 Reset pad configuration 11.6 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 33. The effective input impedance, Rin, seen by the external voltage source, VEXT, is the parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculated using Equation 1 with fs = sampling frequency Cia = ADC analog input capacitance Rmux = analog mux resistance Rsw = switch resistance Cio = pin capacitance (1) Fig 32. Reset pad configuration VSS reset 002aaf274 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN Fig 33. ADC input channel Cia Rs VSS VEXT 002aah615 ADC COMPARATOR ADC Block Rin Cio Rmux Rsw Source <2 kΩ <1.3 kΩ Rin 1 fs  Cia ----------------- + Rmux + Rsw   1 fs  Cio ----------------- =    LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 60 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Under nominal operating condition VDD = 3.3 V and with the maximum sampling frequency fs = 400 kHz, the parameters assume the following values: Cia = 1 pF (max) Rmux = 2 kΩ (max) Rsw = 1.3 kΩ (max) Cio = 7.1 pF (max) The effective input impedance with these parameters is Rin = 308 kΩ. 11.7 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6: • The ADC input trace must be short and as close as possible to the LPC11U3x chip. • Shield The ADC input traces from fast switching digital signals and noisy power supply lines. • The ADC and the digital core share the same power supply. Therefore, filter the power supply line adequately. • To improve the ADC performance in a noisy environment, put the device in Sleep mode during the ADC conversion. 11.8 I/O Handler software library applications The following sections provide application examples for the I/O Handler software library. All library examples make use of the I/O Handler hardware to extend the functionality of the part through software library calls. The libraries are available on http://www.LPCware.com. 11.8.1 I/O Handler I2S The I/O Handler software library provides functions to emulate an I2S master transmit interface using the I/O Handler hardware block. The emulated I2S interface loops over a 1 kB buffer, transmitting the datawords according to the I2S protocol. Interrupts are generated every time when the first 512 bytes have been transmitted and when the last 512 bytes have been transmitted. This allows the ARM core to load the free portion of the buffer with new data, thereby enabling streaming audio. Two channels with 16-bit per channel are supported. The code size of the software library is 1 kB and code must be executed from the SRAM1 memory area reserved for the I/O Handler code. 11.8.2 I/O Handler UART The I/O Handler UART library emulates one additional full-duplex UART. The emulated UART can be configured for 7 or 8 data bits, no parity, and 1 or 2 stop bits. The baud rate is configurable up to 115200 baud. The RXD signal is available on three I/O Handler pins (IOH_6, IOH_16, IOH_20), while TXD and CTS are available on all 21 I/O Handler pins. The code size of the software library is about 1.2 kB and code must be executed from the SRAM1 memory area reserved for the I/O Handler code. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 61 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 11.8.3 I/O Handler I2C The I/O Handler I2C library allows to have an additional I2C-bus master. I2C read, I2C write and combined I2C read/write are supported. Data is automatically read from and written to user-defined buffers. The I/O Handler I2C library combined with the on-chip I2C module allows to have two distinct I2C buses, allowing to separate low-speed from high-speed devices or bridging two I2C buses. 11.8.4 I/O Handler DMA The I/O Handler DMA library offers DMA-like functionality. Four types of transfer are supported: memory to memory, memory to peripheral, peripheral to memory and peripheral to peripheral. Supported peripherals are USART, SSP0/1, ADC and GPIO. DMA transfers can be triggered by the source/target peripheral, software, counter/timer module CT16B1, or I/O Handler pin PIO1_6/IOH_16. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 62 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 12. Package outline Fig 34. Package outline HVQFN33 (5 x 5 x 0.85 mm) Outline References version European projection Issue date IEC JEDEC JEITA MO-220 hvqfn33f_po 11-10-11 11-10-17 Unit(1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 A1 Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm b c 0.30 0.18 A(1) D(1) Dh E(1) Eh e e1 e2 L 3.5 v w 0.1 0.1 y 0.05 0.5 0.3 y1 0.05 0 2.5 5 mm scale 1/2 e v C A B w C terminal 1 index area A A1 c detail X y1 C y e L Eh Dh e e1 b 9 16 32 25 24 8 17 1 X D E C B A e2 terminal 1 index area 1/2 e LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 63 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 35. Package outline HVQFN33 (7 x 7 x 0.85 mm) Outline References version European projection Issue date IEC JEDEC JEITA - - - hvqfn33_po 09-03-17 09-03-23 Unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 A(1) Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm A1 b 0.35 0.28 0.23 c D(1) Dh E(1) Eh 4.85 4.70 4.55 e e1 e2 4.55 L v 0.1 w 0.05 y 0.08 y1 0 2.5 5 mm scale terminal 1 index area D B A E C y1 C y X detail X A1 A c b e2 e1 e e v C A B w C terminal 1 index area Dh Eh L 9 16 32 33 25 17 24 8 1 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 64 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 36. Package outline TFBGA48 (SOT1155-2) Outline References version European projection Issue date IEC JEDEC JEITA SOT1155-2 - - - sot1155-2_po 13-06-17 13-06-19 Unit mm max nom min 1.10 0.95 0.85 0.30 0.25 0.20 0.35 0.30 0.25 4.6 4.5 4.4 4.6 4.5 4.4 0.5 3.5 0.15 0.08 A Dimensions TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2 A1 A2 0.80 0.70 0.65 b D E e e1 3.5 e2 v w 0.05 y y1 0.1 0 5 mm scale ball A1 index area D B A E A B C D E F H G 1 2 3 4 5 6 7 8 b e2 e1 e e 1/2 e 1/2 e ball A1 index area solder mask open area not for solder ball C y1 C y X detail X A A2 A1 Ø v C A B Ø w C LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 65 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 37. Package outline LQFP48 (SOT313-2) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o 1 0.2 0.12 0.1 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT313-2 136E05 MS-026 00-01-19 03-02-25 D(1) (1) (1) 7.1 6.9 HD 9.15 8.85 Z E 0.95 0.55 D bp e E B 12 HD bp HE v M B D ZD A ZE e v M A 1 48 37 36 25 24 13 θ A1 A Lp detail X L (A 3 ) A2 X y c w M w M 0 2.5 5 mm scale pin 1 index LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 66 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 38. Package outline LQFP64 (SOT314-2) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o 1 0.2 0.12 0.1 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT314-2 136E10 MS-026 00-01-19 03-02-25 D(1) (1) (1) 10.1 9.9 HD 12.15 11.85 Z E 1.45 1.05 D bp e θ E A1 A Lp detail X L (A 3 ) B 16 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 64 49 48 33 32 17 y pin 1 index w M w M 0 2.5 5 mm scale LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 67 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 13. Soldering Fig 39. Reflow soldering for the HVQFN33 (5x5) package Footprint information for reflow soldering of HVQFN33 package occupied area solder paste solder land Dimensions in mm P 0.5 Issue date 002aag766 11-11-15 11-11-20 Ax Ay Bx C D 5.95 5.95 4.25 0.85 By 4.25 0.27 Gx 5.25 Gy 5.25 Hy 6.2 Hx 6.2 SLx SLy nSPx nSPy 3.75 3.75 3 3 0.30 0.60 detail X C SLy D SLx Bx Ay P nSPy nSPx see detail X Gx Hx Hy Gy By Ax LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 68 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 40. Reflow soldering for the HVQFN33 (7x7) package Footprint information for reflow soldering of HVQFN33 package occupied area 001aao134 solder land solder resist solder land plus solder paste solder paste deposit Dimensions in mm Remark: Stencil thickness: 0.125 mm e = 0.65 evia = 4.25 OwDtot = 5.10 OA PID = 7.25 PA+OA OID = 8.20 OA 0.20 SR chamfer (4×) 0.45 DM evia = 1.05 W = 0.30 CU evia = 4.25 evia = 2.40 LbE = 5.80 CU LbD = 5.80 CU PIE = 7.25 PA+OA LaE = 7.95 CU LaD = 7.95 CU OIE = 8.20 OA OwEtot = 5.10 OA EHS = 4.85 CU DHS = 4.85 CU 4.55 SR 4.55 SR B-side (A-side fully covered) number of vias: 20 Solder resist covered via 0.30 PH 0.60 SR cover 0.60 CU SEhtot = 2.70 SP SDhtot = 2.70 SP GapE = 0.70 SP SPE = 1.00 SP SPD = 1.00 SP 0.45 DM GapD = 0.70 SP LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 69 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 41. Reflow soldering for the TFBGA48 package DIMENSIONS in mm P SL SP SR Hx Hy Hx Hy SOT1155-2 solder land plus solder paste occupied area Footprint information for reflow soldering of TFBGA48 package solder land solder paste deposit solder resist P P SL SP SR detail X see detail X 0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_fr LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 70 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 42. Reflow soldering for the LQFP48 package SOT313-2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP48 package Ax Bx Gx Hy Gy Hx By Ay P1 D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 10.350 P2 0.560 10.350 7.350 7.350 P1 0.500 0.280 C 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout P2 LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 71 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Fig 43. Reflow soldering for the LQFP64 package SOT314-2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP64 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) Ax Ay Bx By D1 D2 Gx Gy Hx Hy 13.300 13.300 10.300 10.300 P1 0.500 P2 0.560 0.280 C 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land C Generic footprint pattern Refer to the package outline drawing for actual layout LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 72 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations 15. References [1] LPC11U3x User manual UM10462: http://www.nxp.com/documents/user_manual/UM10462.pdf [2] LPC11U3x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC11U3X.pdf Table 20. Abbreviations Acronym Description A/D Analog-to-Digital ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input/Output JTAG Joint Test Action Group PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TAP Test Access Port USART Universal Synchronous Asynchronous Receiver/Transmitter LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 73 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 16. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11U3X v.2.2 20140311 Product data sheet - LPC11U3X v.2.1 Modifications: • Use of USB_CONNECT signal explained in Section 11.1 “Suggested USB interface solutions”. • Open-drain I2C-bus and RESET pin descriptions clarified. See Table 3. LPC11U3X v.2.1 20131230 Product data sheet - LPC11U3X v.2 Modifications: Add reserved function to pins PIO0_8/MISO0/CT16B0_MAT0/R/IOH_6 and PIO0_9/MOSI0/CT16B0_MAT1/R/IOH_7. LPC11U3X v.2 20131125 Product data sheet - LPC11U3X v.1.1 Modifications: • Part LPC11U37HFBD64/401 with I/O handler added. • Additional I/O Handler pin functions added in Table 3. • Typical range of watchdog oscillator frequency changed to 9.4 kHz to 2.3 MHz.See Table 13. • Section 11.8 “I/O Handler software library applications” added. • Updated Section 11.1 “Suggested USB interface solutions” for clarity. • Condition VDD = 0 V added to Parameter VI in Table 5 for clarity. LPC11U3X v.1.1 20130924 Product data sheet - LPC11U3X v.1 Modifications: • Removed the footnote “The peak current is limited to 25 times the corresponding maximum current.” in Table 4. • Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note. • Table 7: Removed BOD interrupt level 0. • Programmable glitch filter is enabled by default. See Section 7.7.1. • Added Section 11.6 “ADC effective input impedance”. • Table 5 “Static characteristics” added Pin capacitance section. • Updated Section 11.1 “Suggested USB interface solutions”. • Table 4 “Limiting values”: – Updated VDD min and max. – Updated VI conditions. • Table 10 “EEPROM characteristics”: – Removed fclk and ter; the user does not have control over these parameters. – Changed the tprog from 1.1 ms to 2.9 ms; the EEPROM IAP always does an erase and program, thus the total program time is ter + tprog. • Changed title of Figure 29 from “USB interface on a self-powered device” to “USB interface with soft-connect”. • Section 10.7 “USB interface” added. Parameter tEOPR1 and tEOPR2 renamed to tEOPR. LPC11U3X v.1 20120420 Product data sheet - - LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 74 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 17. Legal information 17.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 75 of 77 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC11U3X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 2.2 — 11 March 2014 76 of 77 continued >> NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 17 7.1 On-chip flash programming memory . . . . . . . 17 7.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19 7.7 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.8 General-Purpose Input/Output GPIO . . . . . . . 19 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.9 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 20 7.9.1 Full-speed USB device controller . . . . . . . . . . 20 7.9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 I/O Handler (LPC11U37HFBD64/401 only) . . . . . . . . . . . . 20 7.11 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12 SSP serial I/O controller . . . . . . . . . . . . . . . . . 21 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 I2C-bus serial I/O controller . . . . . . . . . . . . . . 22 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.14 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15 General purpose external event counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 23 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.16 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23 7.17 Windowed WatchDog Timer (WWDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.18 Clocking and power control . . . . . . . . . . . . . . 24 7.18.1 Integrated oscillators . . . . . . . . . . . . . . . . . . . 24 7.18.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 25 7.18.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 26 7.18.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 26 7.18.2 System PLL and USB PLL. . . . . . . . . . . . . . . 26 7.18.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26 7.18.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.18.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27 7.18.5.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 27 7.18.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 28 7.18.6 System control . . . . . . . . . . . . . . . . . . . . . . . . 28 7.18.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.18.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 28 7.18.6.3 Code security (Code Read Protection - CRP) . . . . . . . . . . . 28 7.18.6.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.18.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.18.6.6 External interrupt inputs . . . . . . . . . . . . . . . . . 29 7.19 Emulation and debugging . . . . . . . . . . . . . . . 30 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 9 Static characteristics . . . . . . . . . . . . . . . . . . . 32 9.1 BOD static characteristics . . . . . . . . . . . . . . . 38 9.2 Power consumption . . . . . . . . . . . . . . . . . . . 38 9.3 Peripheral power consumption . . . . . . . . . . . 41 9.4 Electrical pin characteristics. . . . . . . . . . . . . . 43 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 46 10.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47 10.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.7 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 53 11 Application information . . . . . . . . . . . . . . . . . 54 11.1 Suggested USB interface solutions . . . . . . . . 54 11.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.3 XTAL Printed-Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 57 11.4 Standard I/O pad configuration . . . . . . . . . . . 58 11.5 Reset pad configuration . . . . . . . . . . . . . . . . . 59 11.6 ADC effective input impedance . . . . . . . . . . . 59 11.7 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 60 11.8 I/O Handler software library applications . . . . 60 11.8.1 I/O Handler I2S. . . . . . . . . . . . . . . . . . . . . . . . 60 11.8.2 I/O Handler UART . . . . . . . . . . . . . . . . . . . . . 60 11.8.3 I/O Handler I2C. . . . . . . . . . . . . . . . . . . . . . . . 61 11.8.4 I/O Handler DMA . . . . . . . . . . . . . . . . . . . . . . 61 NXP Semiconductors LPC11U3x 32-bit ARM Cortex-M0 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 March 2014 Document identifier: LPC11U3X Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 72 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 73 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 74 17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 74 17.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18 Contact information. . . . . . . . . . . . . . . . . . . . . 75 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1. General description The PCA9545A/45B/45C is a quad bidirectional translating switch controlled via the I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of the four interrupt inputs. An active LOW reset input allows the PCA9545A/45B/45C to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected as does the internal power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which is passed by the PCA9545A/45B/45C. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. The PCA9545A, PCA9545B and PCA9545C are identical except for the fixed portion of the slave address. 2. Features and benefits  1-of-4 bidirectional translating switches  I2C-bus interface logic; compatible with SMBus standards  4 active LOW interrupt inputs  Active LOW interrupt output  Active LOW reset input  2 address pins allowing up to 4 devices on the I2C-bus  Alternate address versions A, B and C allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts  Channel selection via I2C-bus, in any combination  Power-up with all switch channels deselected  Low Ron switches  Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses  No glitch on power-up  Supports hot insertion  Low standby current  Operating power supply voltage range of 2.3 V to 5.5 V PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Rev. 9 — 5 May 2014 Product data sheet PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 2 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset  5 V tolerant Inputs  0 Hz to 400 kHz clock frequency  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up protection exceeds 100 mA per JESD78  Three packages offered: SO20, TSSOP20, and HVQFN20 3. Ordering information 3.1 Ordering options Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9545ABS 9545A HVQFN20 plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5  5  0.85 mm SOT662-1 PCA9545AD PCA9545AD SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 PCA9545APW PA9545A TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 PCA9545BPW PA9545B PCA9545CPW PA9545C Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature range PCA9545ABS PCA9545ABS,118 HVQFN20 Reel 13” Q1/T1 *standard mark SMD 6000 Tamb = 40 C to +85 C PCA9545AD PCA9545AD,112 SO20 Standard marking * IC’s tube - DSC bulk pack 1520 Tamb = 40 C to +85 C PCA9545AD,118 SO20 Reel 13” Q1/T1 *standard mark SMD 2000 Tamb = 40 C to +85 C PCA9545APW PCA9545APW,112 TSSOP20 Standard marking * IC’s tube - DSC bulk pack 1875 Tamb = 40 C to +85 C PCA9545APW,118 TSSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9545BPW PCA9545BPW,118 TSSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9545CPW PCA9545CPW,118 TSSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 3 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 4. Block diagram Fig 1. Block diagram of PCA9545A/45B/45C SWITCH CONTROL LOGIC PCA9545A/PCA9545B/PCA9545C POWER-ON RESET 002aab168 SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 VSS VDD RESET I2C-BUS CONTROL INPUT FILTER SCL SDA A0 A1 INTERRUPT LOGIC INT0 to INT3 INT PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 4 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for SO20 Fig 3. Pin configuration for TSSOP20 Fig 4. Pin configuration for HVQFN20 (transparent top view) PCA9545AD A0 VDD A1 SDA RESET SCL INT0 INT SD0 SC3 SC0 SD3 INT1 INT3 SD1 SC2 SC1 SD2 VSS INT2 002aab165 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD SDA SCL INT SC3 SD3 INT3 SC2 SD2 INT2 A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 VSS PCA9545APW PCA9545BPW PCA9545CPW 002aab166 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD SDA SCL INT SC3 SD3 INT3 SC2 A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 VSS 002aab167 PCA9545ABS Transparent top view 5 11 4 12 3 13 2 14 1 15 6 7 8 9 10 20 19 18 17 16 terminal 1 index area SD2 INT2 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 5 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 5.2 Pin description [1] HVQFN20 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias must be incorporated in the PCB in the thermal pad region. Table 3. Pin description Symbol Pin Description SO20, TSSOP20 HVQFN20 A0 1 19 address input 0 A1 2 20 address input 1 RESET 3 1 active LOW reset input INT0 4 2 active LOW interrupt input 0 SD0 5 3 serial data 0 SC0 6 4 serial clock 0 INT1 7 5 active LOW interrupt input 1 SD1 8 6 serial data 1 SC1 9 7 serial clock 1 VSS 10 8[1] supply ground INT2 11 9 active LOW interrupt input 2 SD2 12 10 serial data 2 SC2 13 11 serial clock 2 INT3 14 12 active LOW interrupt input 3 SD3 15 13 serial data 3 SC3 16 14 serial clock 3 INT 17 15 active LOW interrupt output SCL 18 16 serial clock line SDA 19 17 serial data line VDD 20 18 supply voltage PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 6 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9545A/45B/45C”. 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9545A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation. The PCA9545BPW and PCA9545CPW are alternate address versions if needed for larger systems or to resolve conflicts. The data sheet references the PCA9545A, but the PCA9545B and PCA9545C function identically except for the slave address. Fig 5. Slave address PCA9545A Fig 6. Slave address PCA9545B Fig 7. Slave address PCA9545C 002aab169 1 1 1 0 0 A1 A0 R/W fixed hardware selectable 002aab835 1 1 0 1 0 A1 A0 R/W fixed hardware selectable 002aab836 1 0 1 1 0 A1 A0 R/W fixed hardware selectable PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 7 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6.2 Control register Following the successful acknowledgement of the slave address, the bus master sends a byte to the PCA9545A/45B/45C, which is stored in the control register. If multiple bytes are received by the PCA9545A/45B/45C, it saves the last byte received. This register can be written and read via the I2C-bus. 6.2.1 Control register definition One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9545A/45B/45C has been addressed. The 4 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines are in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and channel 2 are enabled. Care should be taken not to exceed the maximum bus capacity. Fig 8. Control register 002aab170 INT 3 INT 2 INT 1 INT 0 B3 B2 B1 B0 channel selection bits (read/write) 7 6 5 4 3 2 1 0 interrupt bits (read only) channel 0 channel 1 channel 2 channel 3 INT0 INT1 INT2 INT3 Table 4. Control register: write (channel selection); read (channel status) INT3 INT2 INT1 INT0 B3 B2 B1 B0 Command X X X X X X X 0 channel 0 disabled 1 channel 0 enabled X X X X X X 0 X channel 1 disabled 1 channel 1 enabled X X X X X 0 X X channel 2 disabled 1 channel 2 enabled X X X X 0 X X X channel 3 disabled 1 channel 3 enabled 0 0 0 0 0 0 0 0 no channel selected; power-up/reset default state PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 8 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6.2.2 Interrupt handling The PCA9545A/45B/45C provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it is detected by the PCA9545A/45B/45C and the interrupt output is driven LOW. The channel does not need to be active for detection of the interrupt. A bit is also set in the control register. Bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of the PCA9545A/45B/45C, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9545A/45B/45C and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9545A/45B/45C to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. If the interrupt function is not required, the interrupt inputs may be used as general-purpose inputs. If unused, interrupt inputs must be connected to VDD through a pull-up resistor. Remark: Several interrupts can be active at the same time. Example: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and channel 3, and there is interrupt on channel 1 and channel 2. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9545A/45B/45C resets its registers and I2C-bus state machine and deselects all channels. The RESET input must be connected to VDD through a pull-up resistor. Table 5. Control register: Read — interrupt INT3 INT2 INT1 INT0 B3 B2 B1 B0 Command X X X 0 X X X X no interrupt on channel 0 1 interrupt on channel 0 X X 0 X X X X X no interrupt on channel 1 1 interrupt on channel 1 X 0 X X X X X X no interrupt on channel 2 1 interrupt on channel 2 0 X X X X X X X no interrupt on channel 3 1 interrupt on channel 3 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 9 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9545A/45B/45C in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9545A/45B/45C registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device. 6.5 Voltage translation The pass gate transistors of the PCA9545A/45B/45C are constructed such that the VDD voltage can be used to limit the maximum voltage that is passed from one I2C-bus to another. Figure 9 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 11 “Static characteristics” of this data sheet). In order for the PCA9545A/45B/45C to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to clamp the downstream bus voltages effectively. Looking at Figure 9, we see that Vo(sw)(max) is at 2.7 V when the PCA9545A/45B/45C supply voltage is 3.5 V or lower, so the PCA9545A/45B/45C supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 16). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. (1) maximum (2) typical (3) minimum Fig 9. Pass gate voltage versus supply voltage VDD (V) 2.0 3.0 4.0 4.5 5.5 002aaa964 3.0 2.0 4.0 5.0 Vo(sw) (V) 1.0 2.5 3.5 5.0 (1) (2) (3) PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 10 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 10). 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 11). Fig 10. Bit transfer 􀁐􀁅􀁄􀀙􀀓􀀚 􀁇􀁄􀁗􀁄􀀃􀁏􀁌􀁑􀁈􀀃 􀁖􀁗􀁄􀁅􀁏􀁈􀀞􀀃 􀁇􀁄􀁗􀁄􀀃􀁙􀁄􀁏􀁌􀁇 􀁆􀁋􀁄􀁑􀁊􀁈􀀃 􀁒􀁉􀀃􀁇􀁄􀁗􀁄􀀃 􀁄􀁏􀁏􀁒􀁚􀁈􀁇 􀀶􀀧􀀤 􀀶􀀦􀀯 Fig 11. Definition of START and STOP conditions 􀁐􀁅􀁄􀀙􀀓􀀛􀀃 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀳 􀀶􀀷􀀲􀀳􀀃􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀶 􀀶􀀷􀀤􀀵􀀷􀀃􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 11 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 12). 7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Fig 12. System configuration 􀀓􀀓􀀕􀁄􀁄􀁄􀀜􀀙􀀙 􀀰􀀤􀀶􀀷􀀨􀀵􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵􀀒􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀶􀀯􀀤􀀹􀀨􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀶􀀯􀀤􀀹􀀨􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵􀀒􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀰􀀤􀀶􀀷􀀨􀀵􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵 􀀰􀀤􀀶􀀷􀀨􀀵􀀃 􀀷􀀵􀀤􀀱􀀶􀀰􀀬􀀷􀀷􀀨􀀵􀀒􀀃 􀀵􀀨􀀦􀀨􀀬􀀹􀀨􀀵 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀬􀀕􀀦􀀐􀀥􀀸􀀶􀀃 􀀰􀀸􀀯􀀷􀀬􀀳􀀯􀀨􀀻􀀨􀀵 􀀶􀀯􀀤􀀹􀀨 Fig 13. Acknowledgement on the I2C-bus 􀀓􀀓􀀕􀁄􀁄􀁄􀀜􀀛􀀚 􀀶 􀀶􀀷􀀤􀀵􀀷􀀃 􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀔 􀀕 􀀛 􀀜 􀁆􀁏􀁒􀁆􀁎􀀃􀁓􀁘􀁏􀁖􀁈􀀃􀁉􀁒􀁕􀀃 􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈􀁐􀁈􀁑􀁗 􀁑􀁒􀁗􀀃􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈􀀃 􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈 􀁇􀁄􀁗􀁄􀀃􀁒􀁘􀁗􀁓􀁘􀁗􀀃 􀁅􀁜􀀃􀁗􀁕􀁄􀁑􀁖􀁐􀁌􀁗􀁗􀁈􀁕 􀁇􀁄􀁗􀁄􀀃􀁒􀁘􀁗􀁓􀁘􀁗􀀃 􀁅􀁜􀀃􀁕􀁈􀁆􀁈􀁌􀁙􀁈􀁕 􀀶􀀦􀀯􀀃􀁉􀁕􀁒􀁐􀀃􀁐􀁄􀁖􀁗􀁈􀁕 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 12 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 7.5 Bus transactions Data is transmitted to the PCA9545A/45B/45C control register using the Write mode as shown in Figure 14. Data is read from PCA9545A/45B/45C using the Read mode as shown in Figure 15. Fig 14. Write control register Fig 15. Read control register 002aab172 S 1 1 1 0 0 A1 A0 0 A X X X X B3 B2 B1 B0 A P slave address START condition R/W acknowledge from slave acknowledge from slave control register SDA STOP condition 002aab173 S 1 1 1 0 0 A1 A0 1 A INT3 INT2 INT1 INT0 B3 B2 B1 B0 NA P slave address START condition R/W acknowledge from slave no acknowledge from master control register SDA STOP condition last byte PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 13 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 8. Application design-in information (1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pull-up resistor is not required. The interrupt inputs should not be left floating. Fig 16. Typical application PCA9545A SD0 SC0 A1 A0 VSS SDA SCL RESET VDD = 2.7 V to 5.5 V VDD = 3.3 V I2C-bus/SMBus master 002aab171 SDA SCL channel 0 V = 2.7 V to 5.5 V INT INT0 see note (1) SD1 SC1 channel 1 V = 2.7 V to 5.5 V INT1 see note (1) SD2 SC2 channel 2 V = 2.7 V to 5.5 V INT2 see note (1) SD3 SC3 channel 3 V = 2.7 V to 5.5 V INT3 see note (1) PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 14 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 9. Limiting values [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C. 10. Thermal characteristics Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +7.0 V VI input voltage 0.5 +7.0 V II input current - 20 mA IO output current - 25 mA IDD supply current - 100 mA ISS ground supply current - 100 mA Ptot total power dissipation - 400 mW Tj(max) maximum junction temperature [1] - 125 C Tstg storage temperature 60 +150 C Tamb ambient temperature operating 40 +85 C Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient HVQFN20 package 32 C/W SO20 package 90 C/W TSSOP20 package 146 C/W PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 15 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 11. Static characteristics [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. Table 8. Static characteristics at VDD = 2.3 V to 3.6 V VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 9 on page 16 for VDD = 4.5 V to 5.5 V[1]. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.3 - 3.6 V IDD supply current Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 10 30 A Istb standby current Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS - 0.1 1 A VPOR power-on reset voltage no load; VI = VDD or VSS [2]- 1.6 2.1 V Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 7 - mA VOL = 0.6 V 6 10 - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 10 13 pF Select inputs A0, A1, INT0 to INT3, RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V ILI input leakage current pin at VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 1.6 3 pF Pass gate Ron ON-state resistance VDD = 3.6 V; VO = 0.4 V; IO = 15 mA 5 11 30  VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA 7 16 55  Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A - 1.9 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = 100 A 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A - 1.5 - V Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = 100 A 1.1 - 2.0 V IL leakage current VI = VDD or VSS 1 - +1 A Cio input/output capacitance VI = VSS - 3 5 pF INT output IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +10 A PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 16 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. Table 9. Static characteristics at VDD = 4.5 V to 5.5 V VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 2.3 V to 3.6 V[1]. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 4.5 - 5.5 V IDD supply current Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 25 100 A Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS - 0.3 1 A VPOR power-on reset voltage no load; VI = VDD or VSS [2]- 1.7 2.1 V Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA IL leakage current VI = VSS 1 - +1 A Ci input capacitance VI = VSS - 10 13 pF Select inputs A0, A1, INT0 to INT3, RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V ILI input leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 2 5 pF Pass gate Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 9 24  Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = 100 A - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = 100 A 2.6 - 4.5 V IL leakage current VI = VDD or VSS 1 - +1 A Cio input/output capacitance VI = VSS - 3 5 pF INT output IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +10 A PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 17 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 12. Dynamic characteristics [1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] Measurements taken with 1 k pull-up resistor and 50 pF load. Table 10. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Unit Min Max Min Max tPD propagation delay from SDA to SDx, or SCL to SCx - 0.3[1] - 0.3[1] ns fSCL SCL clock frequency 0 100 0 400 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - s tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - s tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [5] - 1 - 1 s LOW-to-HIGH [5] - 0.6 - 0.6 s tVD;ACK data valid acknowledge time - 1 - 1 s INT tv(INTnN-INTN) valid time from INTn to INT signal - 4 - 4 s td(INTnN-INTN) delay time from INTn to INT inactive - 2 - 2 s tw(rej)L LOW-level rejection time INTn inputs 1 - 1 - s tw(rej)H HIGH-level rejection time INTn inputs 0.5 - 0.5 - s RESET tw(rst)L LOW-level reset time 4 - 4 - ns trst reset time SDA clear 500 - 500 - ns tREC;STA recovery time to START condition 0 - 0 - ns PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 18 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 17. Definition of timing on the I2C-bus 􀁗􀀥􀀸􀀩 􀁗􀀶􀀳 􀁗􀀫􀀧􀀞􀀶􀀷􀀤 􀀳 􀀶 􀀳 􀁗􀀯􀀲􀀺 􀁗􀁕 􀁗􀀫􀀧􀀞􀀧􀀤􀀷 􀁗􀁉 􀁗􀀫􀀬􀀪􀀫 􀁗􀀶􀀸􀀞􀀧􀀤􀀷 􀁗􀀶􀀸􀀞􀀶􀀷􀀤 􀀶􀁕 􀁗􀀫􀀧􀀞􀀶􀀷􀀤 􀁗􀀶􀀸􀀞􀀶􀀷􀀲 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀓􀀓􀀕􀁄􀁄􀁄􀀜􀀛􀀙 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 Fig 18. Definition of RESET timing SDA SCL 002aac549 50 % 30 % 50 % 50 % tREC;STA tw(rst)L RESET START trst ACK or read cycle Rise and fall times refer to VIL and VIH. Fig 19. I2C-bus timing diagram 􀀓􀀓􀀕􀁄􀁄􀁅􀀔􀀚􀀘 􀁓􀁕􀁒􀁗􀁒􀁆􀁒􀁏 􀀶􀀷􀀤􀀵􀀷 􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀋􀀶􀀌 􀁅􀁌􀁗􀀃􀀚 􀀰􀀶􀀥 􀀋􀀤􀀚􀀌 􀁅􀁌􀁗􀀃􀀙 􀀋􀀤􀀙􀀌 􀁅􀁌􀁗􀀃􀀓 􀀋􀀵􀀒􀀺􀀌 􀁄􀁆􀁎􀁑􀁒􀁚􀁏􀁈􀁇􀁊􀁈 􀀋􀀤􀀌 􀀶􀀷􀀲􀀳 􀁆􀁒􀁑􀁇􀁌􀁗􀁌􀁒􀁑 􀀋􀀳􀀌 􀀶􀀦􀀯 􀀶􀀧􀀤 􀁗􀀫􀀧􀀞􀀶􀀷􀀤 􀁗􀀶􀀸􀀞􀀧􀀤􀀷 􀁗􀀫􀀧􀀞􀀧􀀤􀀷 􀁗􀀥􀀸􀀩 􀁗􀁉 􀁗􀀶􀀸􀀞􀀶􀀷􀀤 􀁗􀀯􀀲􀀺 􀁗􀀫􀀬􀀪􀀫 􀁗􀀹􀀧􀀞􀀤􀀦􀀮 􀁗􀀶􀀸􀀞􀀶􀀷􀀲 􀀔􀀃􀀒􀀃􀁉􀀶􀀦􀀯 􀁗􀁕 􀁗􀀹􀀧􀀞􀀧􀀤􀀷 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀖􀀃􀃮􀀃􀀹􀀧􀀧 􀀓􀀑􀀚􀀃􀃮􀀃􀀹􀀧􀀧 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 19 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 13. Test information Fig 20. Expanded view of read input port register SCL 002aab176 2 1 0 A P 70 % 30 % SDA INPUT 50 % INT tv(INTnN−INTN) td(INTnN−INTN) Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 21. Test circuitry for switching times PULSE GENERATOR VO CL 50 pF RL 500 Ω 002aab177 RT VI VDD VDD D.U.T. PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 20 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 14. Package outline Fig 22. Package outline SOT163-1 (SO20) 􀀸􀀱􀀬􀀷􀀃 􀀤􀀃 􀁐􀁄􀁛􀀑􀀃 􀀤􀀃􀀔􀀃 􀀤􀀃􀀕􀀃 􀀤􀀃􀀖􀀃 􀁅􀀃􀁓􀀃 􀁆􀀃 􀀧􀀃􀀋􀀔􀀌􀀃 􀀨􀀃􀀋􀀔􀀌􀀃 􀁈􀀃 􀀫􀀃􀀨􀀃 􀀯􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀁙􀀃 􀁚􀀃 􀁜􀀃 􀀽􀀃􀀋􀀔􀀌􀀃 􀈙􀀃 􀀲􀀸􀀷􀀯􀀬􀀱􀀨􀀃 􀀃􀀵􀀨􀀩􀀨􀀵􀀨􀀱􀀦􀀨􀀶􀀃 􀀹􀀨􀀵􀀶􀀬􀀲􀀱􀀃 􀀨􀀸􀀵􀀲􀀳􀀨􀀤􀀱􀀃 􀀳􀀵􀀲􀀭􀀨􀀦􀀷􀀬􀀲􀀱􀀃 􀀬􀀶􀀶􀀸􀀨􀀃􀀧􀀤􀀷􀀨􀀃 􀀃􀀬􀀨􀀦􀀃 􀀃􀀭􀀨􀀧􀀨􀀦􀀃 􀀃􀀭􀀨􀀬􀀷􀀤􀀃 􀁐􀁐􀀃 􀁌􀁑􀁆􀁋􀁈􀁖􀀃 􀀕􀀑􀀙􀀘􀀃 􀀓􀀑􀀖􀀃 􀀓􀀑􀀔􀀃 􀀕􀀑􀀗􀀘􀀃 􀀕􀀑􀀕􀀘􀀃 􀀓􀀑􀀗􀀜􀀃 􀀓􀀑􀀖􀀙􀀃 􀀓􀀑􀀖􀀕􀀃 􀀓􀀑􀀕􀀖􀀃 􀀔􀀖􀀑􀀓􀀃 􀀔􀀕􀀑􀀙􀀃 􀀚􀀑􀀙􀀃 􀀚􀀑􀀗􀀃 􀀔􀀑􀀕􀀚􀀃 􀀔􀀓􀀑􀀙􀀘􀀃 􀀔􀀓􀀑􀀓􀀓􀀃 􀀔􀀑􀀔􀀃 􀀔􀀑􀀓􀀃 􀀓􀀑􀀜􀀃 􀀓􀀑􀀗􀀃 􀀛􀀃 􀀓􀀃 􀁒􀀃 􀁒􀀃 􀀓􀀑􀀕􀀘􀀃 􀀓􀀑􀀔􀀃 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀀋􀁌􀁑􀁆􀁋􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁄􀁕􀁈􀀃􀁇􀁈􀁕􀁌􀁙􀁈􀁇􀀃􀁉􀁕􀁒􀁐􀀃􀁗􀁋􀁈􀀃􀁒􀁕􀁌􀁊􀁌􀁑􀁄􀁏􀀃􀁐􀁐􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀌􀀃 􀀱􀁒􀁗􀁈􀀃 􀀔􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁒􀁕􀀃􀁐􀁈􀁗􀁄􀁏􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀔􀀘􀀃􀁐􀁐􀀃􀀋􀀓􀀑􀀓􀀓􀀙􀀃􀁌􀁑􀁆􀁋􀀌􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃􀀃􀀃 􀀔􀀑􀀔􀀃 􀀓􀀑􀀗􀀃 􀀃􀀶􀀲􀀷􀀔􀀙􀀖􀀐􀀔􀀃 􀀔􀀓􀀃 􀀕􀀓􀀃 􀁚􀀃 􀀰􀀃 􀁅􀀃􀁓􀀃 􀁇􀁈􀁗􀁄􀁌􀁏􀀃􀀻􀀃 􀀽􀀃 􀁈􀀃 􀀔􀀔􀀃 􀀔􀀃 􀀧􀀃 􀁜􀀃 􀀓􀀑􀀕􀀘􀀃 􀀃􀀓􀀚􀀘􀀨􀀓􀀗􀀃 􀀃􀀰􀀶􀀐􀀓􀀔􀀖􀀃 􀁓􀁌􀁑􀀃􀀔􀀃􀁌􀁑􀁇􀁈􀁛􀀃 􀀓􀀑􀀔􀀃 􀀓􀀑􀀓􀀔􀀕􀀃 􀀓􀀑􀀓􀀓􀀗􀀃 􀀓􀀑􀀓􀀜􀀙􀀃 􀀓􀀑􀀓􀀛􀀜􀀃 􀀓􀀑􀀓􀀔􀀜􀀃 􀀓􀀑􀀓􀀔􀀗􀀃 􀀓􀀑􀀓􀀔􀀖􀀃 􀀓􀀑􀀓􀀓􀀜􀀃 􀀓􀀑􀀘􀀔􀀃 􀀓􀀑􀀗􀀜􀀃 􀀓􀀑􀀖􀀓􀀃 􀀓􀀑􀀕􀀜􀀃 􀀓􀀑􀀓􀀘􀀃 􀀔􀀑􀀗􀀃 􀀓􀀑􀀗􀀔􀀜􀀃 􀀓􀀑􀀓􀀘􀀘􀀃 􀀓􀀑􀀖􀀜􀀗􀀃 􀀓􀀑􀀓􀀗􀀖􀀃 􀀓􀀑􀀓􀀖􀀜􀀃 􀀓􀀑􀀓􀀖􀀘􀀃 􀀓􀀑􀀓􀀔􀀃 􀀓􀀑􀀓􀀔􀀙􀀃 􀀓􀀑􀀕􀀘􀀃 􀀓􀀑􀀓􀀗􀀖􀀃 􀀓􀀑􀀓􀀔􀀃 􀀓􀀑􀀓􀀓􀀗􀀃 􀀓􀀑􀀓􀀔􀀃 􀀓􀀑􀀓􀀔􀀙􀀃 􀀓􀀃 􀀘􀀃 􀀔􀀓􀀃􀁐􀁐􀀃 􀁖􀁆􀁄􀁏􀁈􀀃 􀀻􀀃 􀈙􀀃 􀀤􀀃 􀀤􀀃􀀔􀀃 􀀤􀀃􀀕􀀃 􀀫􀀃􀀨􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀀨􀀃 􀁆􀀃 􀀯􀀃 􀁙􀀃 􀀰􀀃 􀀤􀀃 􀀋􀀤􀀃􀀖􀀃􀀃􀀌􀀃 􀀤􀀃 􀀶􀀲􀀕􀀓􀀝􀀃􀁓􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁖􀁐􀁄􀁏􀁏􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀞􀀃􀀕􀀓􀀃􀁏􀁈􀁄􀁇􀁖􀀞􀀃􀁅􀁒􀁇􀁜􀀃􀁚􀁌􀁇􀁗􀁋􀀃􀀚􀀑􀀘􀀃􀁐􀁐􀀃 􀀶􀀲􀀷􀀔􀀙􀀖􀀐􀀔􀀃 􀀜􀀜􀀐􀀔􀀕􀀐􀀕􀀚􀀃 􀀓􀀖􀀐􀀓􀀕􀀐􀀔􀀜􀀃 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 21 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 23. Package outline SOT360-1 (TSSOP20) 􀀸􀀱􀀬􀀷􀀃 􀀤􀀃􀀔􀀃 􀀤􀀃􀀕􀀃 􀀤􀀃􀀖􀀃 􀁅􀀃􀁓􀀃 􀁆􀀃 􀀧􀀃􀀋􀀔􀀌􀀃 􀀨􀀃􀀋􀀕􀀌􀀃 􀁈􀀃 􀀫􀀃􀀨􀀃 􀀯􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀁙􀀃 􀁚􀀃 􀁜􀀃 􀀽􀀃􀀋􀀔􀀌􀀃 􀈙􀀃 􀀲􀀸􀀷􀀯􀀬􀀱􀀨􀀃 􀀃􀀵􀀨􀀩􀀨􀀵􀀨􀀱􀀦􀀨􀀶􀀃 􀀹􀀨􀀵􀀶􀀬􀀲􀀱􀀃 􀀨􀀸􀀵􀀲􀀳􀀨􀀤􀀱􀀃 􀀳􀀵􀀲􀀭􀀨􀀦􀀷􀀬􀀲􀀱􀀃 􀀬􀀶􀀶􀀸􀀨􀀃􀀧􀀤􀀷􀀨􀀃 􀀃􀀬􀀨􀀦􀀃 􀀃􀀭􀀨􀀧􀀨􀀦􀀃 􀀃􀀭􀀨􀀬􀀷􀀤􀀃 􀁐􀁐􀀃 􀀓􀀑􀀔􀀘􀀃 􀀓􀀑􀀓􀀘􀀃 􀀓􀀑􀀜􀀘􀀃 􀀓􀀑􀀛􀀓􀀃 􀀓􀀑􀀖􀀓􀀃 􀀓􀀑􀀔􀀜􀀃 􀀓􀀑􀀕􀀃 􀀓􀀑􀀔􀀃 􀀙􀀑􀀙􀀃 􀀙􀀑􀀗􀀃 􀀗􀀑􀀘􀀃 􀀗􀀑􀀖􀀃 􀀓􀀑􀀙􀀘􀀃 􀀙􀀑􀀙􀀃 􀀙􀀑􀀕􀀃 􀀓􀀑􀀗􀀃 􀀓􀀑􀀖􀀃 􀀓􀀑􀀘􀀃 􀀓􀀑􀀕􀀃 􀀛􀀃 􀀓􀀃 􀁒􀀃 􀀔􀀃 􀀓􀀑􀀕􀀃 􀀓􀀑􀀔􀀖􀀃 􀀓􀀑􀀔􀀃 􀁒􀀃 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀀋􀁐􀁐􀀃􀁄􀁕􀁈􀀃􀁗􀁋􀁈􀀃􀁒􀁕􀁌􀁊􀁌􀁑􀁄􀁏􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀌􀀃 􀀱􀁒􀁗􀁈􀁖􀀃 􀀔􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁒􀁕􀀃􀁐􀁈􀁗􀁄􀁏􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀔􀀘􀀃􀁐􀁐􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃 􀀕􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁌􀁑􀁗􀁈􀁕􀁏􀁈􀁄􀁇􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀕􀀘􀀃􀁐􀁐􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃 􀀓􀀑􀀚􀀘􀀃 􀀓􀀑􀀘􀀓􀀃 􀀃􀀶􀀲􀀷􀀖􀀙􀀓􀀐􀀔􀀃 􀀃􀀰􀀲􀀐􀀔􀀘􀀖􀀃 􀀜􀀜􀀐􀀔􀀕􀀐􀀕􀀚􀀃 􀀓􀀖􀀐􀀓􀀕􀀐􀀔􀀜􀀃 􀁚􀀃 􀀰􀀃 􀁅􀀃􀁓􀀃 􀀧􀀃 􀀽􀀃 􀁈􀀃 􀀓􀀑􀀕􀀘􀀃 􀀔􀀃 􀀔􀀓􀀃 􀀕􀀓􀀃 􀀔􀀔􀀃 􀁓􀁌􀁑􀀃􀀔􀀃􀁌􀁑􀁇􀁈􀁛􀀃 􀈙􀀃 􀀤􀀃 􀀤􀀃 􀀔􀀃 􀀤􀀃􀀕􀀃 􀀯􀀃􀁓􀀃 􀀴􀀃 􀁇􀁈􀁗􀁄􀁌􀁏􀀃􀀻􀀃 􀀯􀀃 􀀋􀀤􀀃􀀖􀀃􀀃􀀌􀀃 􀀫􀀃􀀨􀀃 􀀨􀀃 􀁆􀀃 􀁙􀀃 􀀰􀀃 􀀤􀀃 􀀻􀀃 􀀤􀀃 􀁜􀀃 􀀓􀀃 􀀕􀀑􀀘􀀃 􀀘􀀃􀁐􀁐􀀃 􀁖􀁆􀁄􀁏􀁈􀀃 􀀷􀀶􀀶􀀲􀀳􀀕􀀓􀀝􀀃􀁓􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁗􀁋􀁌􀁑􀀃􀁖􀁋􀁕􀁌􀁑􀁎􀀃􀁖􀁐􀁄􀁏􀁏􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀞􀀃􀀕􀀓􀀃􀁏􀁈􀁄􀁇􀁖􀀞􀀃􀁅􀁒􀁇􀁜􀀃􀁚􀁌􀁇􀁗􀁋􀀃􀀗􀀑􀀗􀀃􀁐􀁐􀀃 􀀶􀀲􀀷􀀖􀀙􀀓􀀐􀀔􀀃 􀀤􀀃 􀁐􀁄􀁛􀀑􀀃 􀀔􀀑􀀔􀀃 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 22 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 24. Package outline SOT662-1 (HVQFN20) 􀀔􀀃 􀀓􀀑􀀙􀀘􀀃 􀀸􀀱􀀬􀀷􀀃 􀀤􀀔􀀃 􀁅􀀃 􀀨􀁋􀀃 􀁈􀀃 􀁜􀀃 􀀓􀀑􀀕􀀃 􀁆􀀃 􀀲􀀸􀀷􀀯􀀬􀀱􀀨􀀃 􀀃􀀵􀀨􀀩􀀨􀀵􀀨􀀱􀀦􀀨􀀶􀀃 􀀹􀀨􀀵􀀶􀀬􀀲􀀱􀀃 􀀨􀀸􀀵􀀲􀀳􀀨􀀤􀀱􀀃 􀀳􀀵􀀲􀀭􀀨􀀦􀀷􀀬􀀲􀀱􀀃 􀀬􀀶􀀶􀀸􀀨􀀃􀀧􀀤􀀷􀀨􀀃 􀀃􀀬􀀨􀀦􀀃 􀀃􀀭􀀨􀀧􀀨􀀦􀀃 􀀃􀀭􀀨􀀬􀀷􀀤􀀃 􀁐􀁐􀀃 􀀘􀀑􀀔􀀃 􀀗􀀑􀀜􀀃 􀀧􀁋􀀃 􀀖􀀑􀀕􀀘􀀃 􀀕􀀑􀀜􀀘􀀃 􀁜􀀔􀀃 􀀘􀀑􀀔􀀃 􀀗􀀑􀀜􀀃 􀀖􀀑􀀕􀀘􀀃 􀀕􀀑􀀜􀀘􀀃 􀁈􀀔􀀃 􀀕􀀑􀀙􀀃 􀁈􀀕􀀃 􀀓􀀑􀀖􀀛􀀃 􀀕􀀑􀀙􀀃 􀀓􀀑􀀕􀀖􀀃 􀀓􀀑􀀓􀀘􀀃 􀀓􀀑􀀓􀀓􀀃 􀀓􀀑􀀓􀀘􀀃 􀀓􀀑􀀔􀀃 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀀋􀁐􀁐􀀃􀁄􀁕􀁈􀀃􀁗􀁋􀁈􀀃􀁒􀁕􀁌􀁊􀁌􀁑􀁄􀁏􀀃􀁇􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀌􀀃 􀀃􀀶􀀲􀀷􀀙􀀙􀀕􀀐􀀔􀀃 􀀐􀀃􀀐􀀃􀀐􀀃 􀀰􀀲􀀐􀀕􀀕􀀓􀀃 􀀐􀀃􀀐􀀃􀀐􀀃 􀀓􀀑􀀚􀀘􀀃 􀀓􀀑􀀘􀀓􀀃 􀀯􀀃 􀀓􀀑􀀔􀀃 􀁙􀀃 􀀓􀀑􀀓􀀘􀀃 􀁚􀀃 􀀓􀀃 􀀕􀀑􀀘􀀃 􀀘􀀃􀁐􀁐􀀃 􀁖􀁆􀁄􀁏􀁈􀀃 􀀶􀀲􀀷􀀙􀀙􀀕􀀐􀀔􀀃 􀀫􀀹􀀴􀀩􀀱􀀕􀀓􀀝􀀃􀁓􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁗􀁋􀁈􀁕􀁐􀁄􀁏􀀃􀁈􀁑􀁋􀁄􀁑􀁆􀁈􀁇􀀃􀁙􀁈􀁕􀁜􀀃􀁗􀁋􀁌􀁑􀀃􀁔􀁘􀁄􀁇􀀃􀁉􀁏􀁄􀁗􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀞􀀃􀁑􀁒􀀃􀁏􀁈􀁄􀁇􀁖􀀞􀀃 􀀕􀀓􀀃􀁗􀁈􀁕􀁐􀁌􀁑􀁄􀁏􀁖􀀞􀀃􀁅􀁒􀁇􀁜􀀃􀀘􀀃􀁛􀀃􀀘􀀃􀁛􀀃􀀓􀀑􀀛􀀘􀀃􀁐􀁐􀀃 􀀤􀀋􀀔􀀌􀀃 􀁐􀁄􀁛􀀑􀀃 􀀤􀀃 􀀤􀀔􀀃 􀁆􀀃 􀁇􀁈􀁗􀁄􀁌􀁏􀀃􀀻􀀃 􀁈􀀃 􀁜􀀔􀀃 􀀦􀀃 􀁜􀀃 􀀯􀀃 􀀨􀁋􀀃 􀀧􀁋􀀃 􀁈􀀃 􀁈􀀔􀀃 􀁅􀀃 􀀙􀀃 􀀔􀀓􀀃 􀀕􀀓􀀃 􀀔􀀙􀀃 􀀔􀀘􀀃 􀀘􀀃 􀀔􀀔􀀃 􀀔􀀃 􀀻􀀃 􀀧􀀃 􀀨􀀃 􀀦􀀃 􀀥􀀃 􀀤􀀃 􀁈􀀕􀀃 􀁗􀁈􀁕􀁐􀁌􀁑􀁄􀁏􀀃􀀔􀀃 􀁌􀁑􀁇􀁈􀁛􀀃􀁄􀁕􀁈􀁄􀀃 􀁗􀁈􀁕􀁐􀁌􀁑􀁄􀁏􀀃􀀔􀀃 􀁌􀁑􀁇􀁈􀁛􀀃􀁄􀁕􀁈􀁄􀀃 􀀓􀀔􀀐􀀓􀀛􀀐􀀓􀀛􀀃 􀀓􀀕􀀐􀀔􀀓􀀐􀀕􀀕􀀃 􀀦􀀃 􀀤􀀃 􀀦􀀃 􀁙􀀃 􀀰􀀃 􀀥􀀃 􀁚􀀃 􀀰􀀃 􀀧􀀋􀀔􀀌􀀃 􀀨􀀋􀀔􀀌􀀃 􀀱􀁒􀁗􀁈􀀃 􀀔􀀑􀀃􀀳􀁏􀁄􀁖􀁗􀁌􀁆􀀃􀁒􀁕􀀃􀁐􀁈􀁗􀁄􀁏􀀃􀁓􀁕􀁒􀁗􀁕􀁘􀁖􀁌􀁒􀁑􀁖􀀃􀁒􀁉􀀃􀀓􀀑􀀓􀀚􀀘􀀃􀁐􀁐􀀃􀁐􀁄􀁛􀁌􀁐􀁘􀁐􀀃􀁓􀁈􀁕􀀃􀁖􀁌􀁇􀁈􀀃􀁄􀁕􀁈􀀃􀁑􀁒􀁗􀀃􀁌􀁑􀁆􀁏􀁘􀁇􀁈􀁇􀀑􀀃􀀃 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 23 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 24 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. Table 11. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 12. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 25 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 26 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 16. Soldering: PCB footprints Fig 26. PCB footprint for SOT163-1 (SO20); reflow soldering Fig 27. PCB footprint for SOT163-1 (SO20); wave soldering 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀁖􀁒􀁗􀀔􀀙􀀖􀀐􀀔􀁂􀁉􀁕 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀁖 􀁓􀁏􀁄􀁆􀁈􀁐􀁈􀁑􀁗􀀃􀁄􀁆􀁆􀁘􀁕􀁄􀁆􀁜􀀃􀂓􀀃􀀓􀀑􀀕􀀘 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀀔􀀑􀀘􀀓 􀀓􀀑􀀙􀀓􀀃􀀋􀀕􀀓􀃮􀀌 􀀔􀀑􀀕􀀚􀀃􀀋􀀔􀀛􀃮􀀌 􀀛􀀑􀀓􀀓 􀀔􀀔􀀑􀀓􀀓 􀀔􀀖􀀑􀀗􀀓 􀀔􀀔􀀑􀀗􀀓 􀁖􀁒􀁗􀀔􀀙􀀖􀀐􀀔􀁂􀁉􀁚 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁕􀁈􀁖􀁌􀁖􀁗 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀁖 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀁅􀁒􀁄􀁕􀁇􀀃􀁇􀁌􀁕􀁈􀁆􀁗􀁌􀁒􀁑 􀁓􀁏􀁄􀁆􀁈􀁐􀁈􀁑􀁗􀀃􀁄􀁆􀁆􀁘􀁕􀁕􀁄􀁆􀁜􀀃􀂓􀀃􀀓􀀑􀀕􀀘 􀀛􀀑􀀓􀀓 􀀔􀀖􀀑􀀗􀀓 􀀔􀀑􀀘􀀓 􀀓􀀑􀀖􀀃􀀋􀀕􀃮􀀌 􀀓􀀑􀀙􀀓􀀃􀀋􀀔􀀛􀃮􀀌 􀀔􀀑􀀕􀀓􀀃􀀋􀀕􀃮􀀌 􀀔􀀑􀀕􀀚􀀃􀀋􀀔􀀛􀃮􀀌 􀀔􀀔􀀑􀀓􀀓 􀀔􀀔􀀑􀀗􀀓 􀁈􀁑􀁏􀁄􀁕􀁊􀁈􀁇􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 27 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 28. PCB footprint for SOT360-1 (TSSOP20); reflow soldering 􀀧􀀬􀀰􀀨􀀱􀀶􀀬􀀲􀀱􀀶􀀃􀁌􀁑􀀃􀁐􀁐 􀀳􀀔 􀀤􀁜 􀀥􀁜 􀀦 􀀧􀀔 􀀧􀀕 􀀪􀁛 􀀪􀁜 􀀫􀁜 􀁖􀁒􀁗􀀖􀀙􀀓􀀐􀀔􀁂􀁉􀁕 􀀫􀁛 􀀶􀀲􀀷􀀖􀀙􀀓􀀐􀀔 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀀩􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁌􀁑􀁉􀁒􀁕􀁐􀁄􀁗􀁌􀁒􀁑􀀃􀁉􀁒􀁕􀀃􀁕􀁈􀁉􀁏􀁒􀁚􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀁌􀁑􀁊􀀃􀁒􀁉􀀃􀀷􀀶􀀶􀀲􀀳􀀕􀀓􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈 􀀪􀁜 􀀥􀁜 􀀤􀁜 􀀦 􀀫􀁜 􀀫􀁛 􀀪􀁛 􀀳􀀔 􀀪􀁈􀁑􀁈􀁕􀁌􀁆􀀃􀁉􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁓􀁄􀁗􀁗􀁈􀁕􀁑􀀃 􀀵􀁈􀁉􀁈􀁕􀀃􀁗􀁒􀀃􀁗􀁋􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁇􀁕􀁄􀁚􀁌􀁑􀁊􀀃􀁉􀁒􀁕􀀃􀁄􀁆􀁗􀁘􀁄􀁏􀀃􀁏􀁄􀁜􀁒􀁘􀁗 􀀳􀀕 􀀋􀀓􀀑􀀔􀀕􀀘􀀌 􀀋􀀓􀀑􀀔􀀕􀀘􀀌 􀀧􀀕􀀃􀀋􀀗􀁛􀀌 􀀧􀀔 􀀳􀀕 􀀓􀀑􀀙􀀘􀀓 􀀓􀀑􀀚􀀘􀀓 􀀚􀀑􀀕􀀓􀀓 􀀗􀀑􀀘􀀓􀀓 􀀔􀀑􀀖􀀘􀀓 􀀓􀀑􀀗􀀓􀀓 􀀓􀀑􀀙􀀓􀀓 􀀙􀀑􀀜􀀓􀀓 􀀘􀀑􀀖􀀓􀀓 􀀚􀀑􀀖􀀓􀀓 􀀚􀀑􀀗􀀘􀀓 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 28 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Fig 29. PCB footprint for SOT662-1 (HVQFN20); reflow soldering 􀀩􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁌􀁑􀁉􀁒􀁕􀁐􀁄􀁗􀁌􀁒􀁑􀀃􀁉􀁒􀁕􀀃􀁕􀁈􀁉􀁏􀁒􀁚􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀁌􀁑􀁊􀀃􀁒􀁉􀀃􀀫􀀹􀀴􀀩􀀱􀀕􀀓􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈 􀀶􀀲􀀷􀀙􀀙􀀕􀀐􀀔 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀀤􀁛 􀀤􀁜 􀀥􀁛 􀀥􀁜 􀀧 􀀶􀀯􀁛 􀀶􀀯􀁜 􀀶􀀳􀁛􀀃􀁗􀁒􀁗 􀀶􀀳􀁜􀀃􀁗􀁒􀁗 􀀶􀀳􀁛 􀀶􀀳􀁜 􀀪􀁛 􀀪􀁜 􀀫􀁛 􀀫􀁜 􀀙􀀑􀀓􀀓􀀓 􀀙􀀑􀀓􀀓􀀓 􀀖􀀑􀀛􀀓􀀓 􀀖􀀑􀀛􀀓􀀓 􀀳 􀀓􀀑􀀙􀀘􀀓 􀀓􀀑􀀖􀀘􀀓 􀀦 􀀔􀀑􀀔􀀓􀀓 􀀖􀀑􀀓􀀓􀀓 􀀖􀀑􀀓􀀓􀀓 􀀔􀀑􀀛􀀓􀀓 􀀔􀀑􀀛􀀓􀀓 􀀓􀀑􀀙􀀘􀀓 􀀓􀀑􀀙􀀘􀀓 􀀘􀀑􀀖􀀓􀀓 􀀘􀀑􀀖􀀓􀀓 􀀙􀀑􀀕􀀘􀀓 􀀙􀀑􀀕􀀘􀀓 􀁑􀀶􀀳􀁛 􀁑􀀶􀀳􀁜 􀀕 􀀕 􀁖􀁒􀁗􀀙􀀙􀀕􀀐􀀔􀁂􀁉􀁕 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀀤􀁛 􀀥􀁛 􀀶􀀯􀁛 􀀪􀁛 􀀫􀁜 􀀪􀁜 􀀫􀁛 􀀶􀀯􀁜 􀀥􀁜 􀀤􀁜 􀀧 􀀳 􀀓􀀑􀀓􀀕􀀘 􀀓􀀑􀀓􀀕􀀘 􀀋􀀓􀀑􀀔􀀓􀀘􀀌 􀀶􀀳􀁛􀀃􀁗􀁒􀁗 􀀶􀀳􀁜􀀃􀁗􀁒􀁗 􀁑􀀶􀀳􀁛 􀁑􀀶􀀳􀁜 􀀶􀀳􀁛 􀀶􀀳􀁜 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀀃􀁓􀁏􀁘􀁖􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁓􀁄􀁖􀁗􀁈 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁓􀁄􀁖􀁗􀁈􀀃􀁇􀁈􀁓􀁒􀁖􀁌􀁗 􀀦 􀀪􀁈􀁑􀁈􀁕􀁌􀁆􀀃􀁉􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁓􀁄􀁗􀁗􀁈􀁕􀁑􀀃 􀀵􀁈􀁉􀁈􀁕􀀃􀁗􀁒􀀃􀁗􀁋􀁈􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀃􀁒􀁘􀁗􀁏􀁌􀁑􀁈􀀃􀁇􀁕􀁄􀁚􀁌􀁑􀁊􀀃􀁉􀁒􀁕􀀃􀁄􀁆􀁗􀁘􀁄􀁏􀀃􀁏􀁄􀁜􀁒􀁘􀁗 􀀬􀁖􀁖􀁘􀁈􀀃􀁇􀁄􀁗􀁈 􀀓􀀚􀀐􀀓􀀘􀀐􀀓􀀚􀀃 􀀓􀀜􀀐􀀓􀀙􀀐􀀔􀀘 PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 29 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 17. Abbreviations 18. Revision history Table 13. Abbreviations Acronym Description CDM Charged-Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit I2C-bus Inter-Integrated Circuit bus LSB Least Significant Bit MSB Most Significant Bit PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9545A_45B_45C v.9 20140505 Product data sheet - PCA9545A_45B_45C v.8 Modifications: • Section 6.4 “Power-on reset”, first paragraph, third sentence corrected from “Thereafter, VDD must be lowered below 0.2 V to reset the device.” to “Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device.” (this is a correction to documentation only; no change to device) • Table 8 “Static characteristics at VDD = 2.3 V to 3.6 V”: Table note [2] corrected by inserting phrase “for at least 5 s” (this is a correction to documentation only; no change to device) • Table 9 “Static characteristics at VDD = 4.5 V to 5.5 V”: Table note [2] corrected by inserting phrase “for at least 5 s” (this is a correction to documentation only; no change to device) PCA9545A_45B_45C v.8 20130514 Product data sheet - PCA9545A_45B_45C v.7 PCA9545A_45B_45C v.7 20090619 Product data sheet - PCA9545A_45B_45C v.6 PCA9545A_45B_45C v.6 20070319 Product data sheet - PCA9545A_45B_45C v.5 PCA9545A_45B_45C v.5 20061017 Product data sheet - PCA9545A v.4 PCA9545A v.4 20060925 Product data sheet - PCA9545A v.3 PCA9545A v.3 20050303 Product data sheet - PCA9545A v.2 PCA9545A v.2 20040929 Objective data sheet - PCA9545A v.1 PCA9545A v.1 20040728 Objective data sheet - - PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 30 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset 19. Legal information 19.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PCA9545A_45B_45C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 5 May 2014 31 of 32 NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors PCA9545A/45B/45C 4-channel I2C-bus switch with interrupt logic and reset © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 May 2014 Document identifier: PCA9545A_45B_45C Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 7 6.2.2 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 9 7 Characteristics of the I2C-bus . . . . . . . . . . . . 10 7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 START and STOP conditions . . . . . . . . . . . . . 10 7.3 System configuration . . . . . . . . . . . . . . . . . . . 11 7.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 12 8 Application design-in information . . . . . . . . . 13 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 10 Thermal characteristics . . . . . . . . . . . . . . . . . 14 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 13 Test information. . . . . . . . . . . . . . . . . . . . . . . . 19 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 15 Soldering of SMD packages . . . . . . . . . . . . . . 23 15.1 Introduction to soldering . . . . . . . . . . . . . . . . . 23 15.2 Wave and reflow soldering . . . . . . . . . . . . . . . 23 15.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 23 15.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24 16 Soldering: PCB footprints. . . . . . . . . . . . . . . . 26 17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29 18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 20 Contact information. . . . . . . . . . . . . . . . . . . . . 31 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1. General description The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high performance applications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz. The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations, and hardware based native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB instruction cache and a 32 kB data cache. For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management. The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices. In addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option. 2. Features and benefits  ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.  Vector Floating Point (VFP) coprocessor.  32 kB instruction cache and 32 kB data cache.  Up to 256 kB of Internal SRAM (IRAM).  Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory.  Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time. LPC3220/30/40/50 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface Rev. 2 — 20 October 2011 Product data sheet LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 2 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers  External memory controller for DDR and SDR SDRAM as well as for static devices.  Two NAND flash controllers: One for single-level NAND flash devices and the other for multi-level NAND flash devices.  Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting 74 interrupt sources.  Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be used with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPI interfaces, as well as memory-to-memory transfers.  Serial interfaces:  10/100 Ethernet MAC with dedicated DMA Controller.  USB interface supporting either device, host (OHCI compliant), or On-The-Go (OTG) with an integral DMA controller and dedicated PLL to generate the required 48 MHz USB clock.  Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One of the standard UARTs supports IrDA.  Three additional high-speed UARTs intended for on-board communications that support baud rates up to 921 600 when using a 13 MHz main oscillator. All high-speed UARTs provide 64 byte FIFOs.  Two SPI controllers.  Two SSP controllers.  Two I2C-bus interfaces with standard open-drain pins. The I2C-bus interfaces support single master, slave, and multi-master I2C-bus configurations.  Two I2S-bus interfaces, each with separate input and output channels. Each channel can be operated independently on three pins, or both input and output channels can be used with only four pins and a shared clock.  Additional peripherals:  LCD controller supporting both STN and TFT panels, with dedicated DMA controller. Programmable display resolution up to 1024  768.  Secure Digital (SD) memory card interface, which conforms to the SD Memory Card Specification Version 1.01.  General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24 GP output pins, and 51 GP I/O pins.  10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from three pins. Optionally, the ADC can operate as a touch screen controller.  Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator. NXP implemented the RTC in an independent on-chip power domain so it can remain active while the rest of the chip is not powered. The RTC also includes a 32-byte scratch pad memory.  32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer includes one external capture input pin and a capture connection to the RTC clock. Interrupts may be generated using three match registers.  Six enhanced timer/counters which are architecturally identical except for the peripheral base address. Two capture inputs and two match outputs are pinned out to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all four match outputs, timer 4 has one match output, and timer 5 has no inputs or outputs.  32-bit millisecond timer driven from the RTC clock. This timer can generate interrupts using two match registers. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 3 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers  WatchDog timer clocked by the peripheral clock.  Two single-output PWM blocks.  Motor control PWM.  Keyboard scanner function allows automatic scanning of an up to 8  8 key matrix.  Up to 18 external interrupts.  Standard ARM test/debug interface for compatibility with existing tools.  Emulation Trace Buffer (ETB) with 2048  24 bit RAM allows trace via JTAG.  Stop mode saves power while allowing many peripheral functions to restart CPU activity.  On-chip crystal oscillator.  An on-chip PLL allows CPU operation up to the maximum CPU rate without the requirement for a high frequency crystal. Another PLL allows operation from the 32 kHz RTC clock rather than the external crystal.  Boundary scan for simplified board testing.  User-accessible unique serial ID number for each chip.  TFBGA296 package with a 15 mm  15 mm  0.7 mm body. 3. Applications  Consumer  Medical  Industrial  Network control LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 4 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 4. Ordering information [1] F = 40 C to +85 C temperature range. Note that Revision “A” parts with and without the /01 suffix are identical. For example, LPC3220FET296 Revision “A” is identical to LPC3220FET296/01 Revision “A”. [2] Available starting with Revision “A”. 4.1 Ordering options Table 1. Ordering information Type number[1] Package Name Description Version LPC3220FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 LPC3230FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 LPC3240FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 LPC3250FET296/01[2] TFBGA296 plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1 Table 2. Part options Type number SRAM (kB) 10/100 Ethernet LCD controller Temperature range (C) Package LPC3220FET296/01 128 0 0 40 to +85 TFBGA296 LPC3230FET296/01 256 0 1 40 to +85 TFBGA296 LPC3240FET296/01 256 1 0 40 to +85 TFBGA296 LPC3250FET296/01 256 1 1 40 to +85 TFBGA296 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 5 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 5. Block diagram Fig 1. Block diagram of LPC3220/30/40/50 ARM 9EJS D-CACHE 32 kB I-CACHE 32 kB DATA INSTRUCTION ethernet PHY interface USB transceiver interface LCD panel interface EXTERNAL MEMORY CONTROLLER ROM 16 kB SRAM 256 kB DMA USB SDRAM ETB STANDARD UART × 4 I2C × 2 TIMERS × 6 WATCHDOG TIMER DEBUG SYSTEM CONTROL HS UART × 3 KEY SCANNER 10-BIT ADC/TS UART CONTROL RTC PWM × 2 GPIO M0 M1 AHB TO APB BRIDGE AHB TO APB BRIDGE AHB TO APB BRIDGE master layer 0 1 2 3 4 5 6 slave port 0 1 7 6 5 3 2 = Master/Slave connection supported by the multilayer AHB matrix 32-bit AHB matrix APB slaves FAB slaves AHB slaves APB slaves port 3 port 4 port 0 32-bit wide external memory VFP9 ETB ETM 9 ETHERNET LCD MOTOR CONTROL PWM 002aae397 MMU D-SIDE CONTROLLER I-SIDE CONTROLLER DMA CONTROLLER ETHERNET 10/100 MAC USB OTG CONTROLLER LCD CONTROLLER MLC NAND SLC NAND SD CARD SPI × 2 I2S × 2 SSP × 2 INTERRUPT CONTROL register interfaces LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 6 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for SOT1048-1 (TFBGA296) 002aae398 Transparent top view V U T R P N L J M K H G F E D B C A 2 4 6 8 10 12 13 14 15 17 16 18 1 3 5 7 9 11 ball A1 index area Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol Row A A3 I2C2_SCL A4 I2S1TX_CLK/MAT3[0] A5 I2C1_SCL A6 MS_BS/MAT2[1] A7 MS_DIO1/MAT0[1] A8 MS_DIO0/MAT0[0] A9 SPI2_DATIO/MOSI1/LCDVD[20][1] A10 SPI2_DATIN/MISO1/ LCDVD[21][1]/GPI_27 A11 GPIO_1 A12 GPIO_0 A13 GPO_21/U4_TX/LCDVD[3][1] A14 GPO_15/MCOA1/LCDFP[1] A15 GPO_7/LCDVD[2][1] A16 GPO_6/LCDVD[18][1] Row B B2 GPO_20 B3 GPO_5 B4 I2S1TX_WS/CAP3[0] B5 P0[0]/I2S1RX_CLK B6 I2C1_SDA B7 MS_SCLK/MAT2[0] B8 MS_DIO2/MAT0[2] B9 SPI1_DATIO/MOSI0/MCI2 B10 SPI2_CLK/SCK1/LCDVD[23][1] B11 GPIO_4/SSEL1/LCDVD[22][1] B12 GPO_12/MCOA2/LCDLE[1] B13 GPO_13/MCOB1/LCDDCLK[1] B14 GPO_2/MAT1[0]/LCDVD[0][1] B15 GPI_19/U4_RX B16 GPI_8/KEY_COL6/ SPI2_BUSY/ENET_RX_DV[2] B17 n.c. Row C C1 FLASH_RD C2 GPO_19 C3 GPO_0/TST_CLK1 C4 USB_ATX_INT C5 USB_SE0_VM/U5_TX C6 TST_CLK2 C7 GPI_6/HSTIM_CAP/ ENET_RXD2[2] C8 MS_DIO3/MAT0[3] C9 SPI1_CLK/SCK0 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 7 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers C10 SPI1_DATIN/MISO0/GPI_25/ MCI1 C11 GPIO_3/KEY_ROW7/ ENET_MDIO[2] C12 GPO_9/LCDVD[9][1] C13 GPO_8/LCDVD[8][1] C14 GPI_2/CAP2[0]/ ENET_RXD3[2] C15 GPI_1/SERVICE C16 GPI_0/I2S1RX_SDA C17 KEY_ROW4/ENET_TXD0[2] C18 KEY_ROW5/ENET_TXD1[2] Row D D1 FLASH_RDY D2 FLASH_ALE D3 GPO_14 D4 GPO_1 D5 USB_DAT_VP/U5_RX D6 USB_OE_TP D7 P0[1]/I2S1RX_WS D8 GPO_4 D9 GPIO_2/KEY_ROW6/ENET_MDC[2] D10 GPO_16/MCOB0/LCDENAB[1]/ LCDM[1] D11 GPO_18/MCOA0/LCDLP[1] D12 GPO_3/LCDVD[1][1] D13 GPI_7/CAP4[0]/MCABORT D14 PWM_OUT1/LCDVD[16][1] D15 PWM_OUT2/INTSTAT/LCDVD[19][1] D16 KEY_ROW3/ENET_TX_EN[2] D17 KEY_COL2/ENET_RX_ER[2] D18 KEY_COL3/ENET_CRS[2] Row E E1 FLASH_IO[3] E2 FLASH_IO[7] E3 FLASH_CE E4 I2C2_SDA E5 USB_I2C_SCL E6 USB_I2C_SDA E7 I2S1TX_SDA/MAT3[1] E8 GPO_11 E9 GPIO_5/SSEL0/MCI0 E10 GPO_22/U7_HRTS/ LCDVD[14][1] E11 GPO_10/MCOB2/LCDPWR[1] E12 GPI_9/KEY_COL7/ENET_COL[2] E13 GPI_4/SPI1_BUSY E14 KEY_ROW1/ENET_TXD2[2] E15 KEY_ROW0/ENET_TX_ER[2] E16 KEY_COL1/ENET_RX_CLK[2]/ ENET_REF_CLK[2] E17 U7_RX/CAP0[0]/ LCDVD[10][1]/GPI_23 E18 U7_TX/MAT1[1]/LCDVD[11][1] Row F F1 FLASH_IO[2] F2 FLASH_WR F3 FLASH_CLE F4 GPI_3 F5 VSS_IOC F6 VSS_IOB F7 VDD_IOC F8 VDD_IOB F9 VDD_IOD F10 VSS_IOD F11 VSS_IOD F12 VSS_IOD F13 VDD_IOD F14 KEY_ROW2/ENET_TXD3[2] F15 KEY_COL0/ENET_TX_CLK[2] F16 KEY_COL5/ENET_RXD1[2] F17 U6_IRRX/GPI_21 F18 U5_RX/GPI_20 Row G G1 EMC_DYCS1 G2 FLASH_IO[5] G3 FLASH_IO[6] G4 RESOUT G5 VSS_IOC G6 VDD_IOC G7 VDD_CORE G8 VSS_CORE G9 VDD_CORE G10 VSS_CORE G11 VDD_CORE G12 VSS_CORE G13 U7_HCTS/CAP0[1]/ LCDCLKIN[1]/GPI_22 G14 DBGEN G15 KEY_COL4/ENET_RXD0[2] G16 U6_IRTX G17 SYSCLKEN/LCDVD[15][1] G18 JTAG_TMS Row H H1 EMC_OE H2 FLASH_IO[0] H3 FLASH_IO[1] H4 FLASH_IO[4] H5 VSS_IOC H6 VDD_IOC H7 VSS_CORE H12 VSS_IOD H13 VDD_IOA H14 JTAG_TCK H15 U5_TX Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 8 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers H16 HIGHCORE/LCDVD[17][1] H17 JTAG_NTRST H18 JTAG_RTCK Row J J1 EMC_A[20]/P1[20] J2 EMC_A[21]/P1[21] J3 EMC_A[22]/P1[22] J4 EMC_A[23]/P1[23] J5 VDD_IOC J6 VDD_EMC J7 VDD_CORE J12 VDD_CORE J13 VDD_IOA J14 U3_RX/GPI_18 J15 JTAG_TDO J16 JTAG_TDI J17 U3_TX J18 U2_HCTS/U3_CTS/GPI_16 Row K K1 EMC_A[19]/P1[19] K2 EMC_A[18]/P1[18] K3 EMC_A[16]/P1[16] K4 EMC_A[17]/P1[17] K5 VSS_EMC K6 VDD_EMC K7 VDD_EMC K12 VSS_CORE K13 VSS_IOA K14 VDD_RTC K15 U1_RX/CAP1[0]/GPI_15 K16 U1_TX K17 U2_TX/U3_DTR K18 U2_RX/U3_DSR/GPI_17 Row L L1 EMC_A[15]/P1[15] L2 EMC_CKE1 L3 EMC_A[0]/P1[0] L4 EMC_A[1]/P1[1] L5 VSS_EMC L6 VDD_EMC L7 VSS_CORE L12 VDD_COREFXD L13 VDD_RTCCORE L14 VSS_RTCCORE L15 P0[4]/I2S0RX_WS/LCDVD[6][1] L16 P0[5]/I2S0TX_SDA/LCDVD[7][1] L17 P0[6]/I2S0TX_CLK/ LCDVD[12][1] L18 P0[7]/I2S0TX_WS/LCDVD[13][1] Row M M1 EMC_A[2]/P1[2] M2 EMC_A[3]/P1[3] M3 EMC_A[4]/P1[4] M4 EMC_A[8]/P1[8] M5 VSS_EMC M6 VDD_EMC M7 VDD_CORE M8 VDD_EMC M9 VSS_CORE M10 VSS_CORE M11 VDD_CORE M12 VSS_CORE M13 VDD_COREFXD M14 RESET M15 ONSW M16 GPO_23/U2_HRTS/U3_RTS M17 P0[2]/I2S0RX_SDA/ LCDVD[4][1] M18 P0[3]/I2S0RX_CLK/LCDVD[5][1] Row N N1 EMC_A[5]/P1[5] N2 EMC_A[6]/P1[6] N3 EMC_A[7/P1[7] N4 EMC_A[12]/P1[12] N5 VSS_EMC N6 VSS_EMC N7 VDD_EMC N8 VDD_EMC N9 VDD_EMC N10 VDD_EMC N11 VDD_EMC N12 VDD_AD N13 VDD_AD N14 VDD_FUSE N15 VDD_RTCOSC N16 GPI_5/U3_DCD N17 GPI_28/U3_RI N18 GPO_17 Row P P1 EMC_A[9]/P1[9] P2 EMC_A[10]/P1[10] P3 EMC_A[11]/P1[11] P4 EMC_DQM[1] P5 EMC_DQM[3] P6 VSS_EMC Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 9 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] LCD on LPC3230 and LPC3250 only. [2] Ethernet on LPC3240 and LPC3250 only. P7 VSS_EMC P8 VSS_EMC P9 VSS_EMC P10 VSS_EMC P11 VSS_EMC P12 EMC_BLS[3] P13 VSS_AD P14 VSS_OSC P15 VDD_PLLUSB P16 RTCX_IN P17 RTCX_OUT P18 VSS_RTCOSC Row R R1 EMC_A[13]/P1[13] R2 EMC_A[14]/P1[14] R3 EMC_DQM[0] R4 EMC_WR R5 EMC_CAS R6 EMC_DYCS0 R7 EMC_D[1] R8 EMC_D[7] R9 EMC_D[17]/EMC_DQS1 R10 EMC_D[24]/P2[5] R11 EMC_CS1 R12 EMC_BLS[2] R13 TS_XP R14 PLL397_LOOP R15 SYSX_OUT R16 VSS_PLLUSB R17 VDD_PLLHCLK R18 VSS_PLLHCLK Row T T1 EMC_DQM[2] T2 EMC_RAS T3 EMC_CLK T4 EMC_CLKIN T5 EMC_D[2] T6 EMC_D[6] T7 EMC_D[11] T8 EMC_D[14] T9 EMC_D[20]/P2[1] T10 EMC_D[23]/P2[4] T11 EMC_D[27]/P2[8] T12 EMC_CS2 T13 EMC_BLS[1] T14 ADIN1/TS_XM T15 VSS_PLL397 T16 VDD_PLL397 T17 SYSX_IN T18 VDD_OSC Row U U2 n.c. U3 EMC_CKE0 U4 EMC_D[0] U5 EMC_D[3] U6 EMC_D[9] U7 EMC_D[12] U8 EMC_D[15] U9 EMC_D[19]/P2[0] U10 EMC_D[22]/P2[3] U11 EMC_D[26]/P2[7] U12 EMC_D[30]/P2[11] U13 EMC_CS0 U14 EMC_BLS[0] U15 ADIN0/TS_YM U16 TS_YP U17 n.c. Row V V3 EMC_D[4] V4 EMC_D[5] V5 EMC_D[8] V6 EMC_D[10] V7 EMC_D[13] V8 EMC_D[16]/EMC_DQS0 V9 EMC_D[18]/EMC_CLK V10 EMC_D[21]/P2[2] V11 EMC_D[25]/P2[6] V12 EMC_D[28]/P2[9] V13 EMC_D[29]/P2[10] V14 EMC_D[31]/P2[12] V15 EMC_CS3 V16 ADIN2/TS_AUX_IN Table 3. Pin allocation table (TFBGA296) Pin Symbol Pin Symbol Pin Symbol LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 10 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 6.2 Pin description Table 4. Pin description Symbol Pin Power supply domain Type Description ADIN0/TS_YM U15 VDD_AD analog in ADC input 0/touch screen Y minus ADIN1/TS_XM T14 VDD_AD analog in ADC input 0/touch screen X minus ADIN2/TS_AUX_IN V16 VDD_AD analog in ADC input 2/touch screen AUX input DBGEN G14 VDD_IOD I: PD Device test input LOW = JTAG in-circuit debug available; normal operation. HIGH = I/O cell boundary scan test; for board assembly BSDL test. EMC_A[0]/P1[0] L3 VDD_EMC I/O EMC address bit 0 I/O Port 1 GPIO bit 0 EMC_A[1]/P1[1] L4 VDD_EMC I/O EMC address bit 1 I/O Port 1 GPIO bit 1 EMC_A[2]/P1[2] M1 VDD_EMC I/O EMC address bit 2 I/O Port 1 GPIO bit 2 EMC_A[3]/P1[3] M2 VDD_EMC I/O EMC address bit 3 I/O Port 1 GPIO bit 3 EMC_A[4]/P1[4] M3 VDD_EMC I/O EMC address bit 4 I/O Port 1 GPIO bit 4 EMC_A[5]/P1[5] N1 VDD_EMC I/O EMC address bit 5 I/O Port 1 GPIO bit 5 EMC_A[6]/P1[6] N2 VDD_EMC I/O EMC address bit 6 I/O Port 1 GPIO bit 6 EMC_A[7/P1[7] N3 VDD_EMC I/O EMC address bit 7 I/O Port 1 GPIO bit 7 EMC_A[8]/P1[8] M4 VDD_EMC I/O EMC address bit 8 I/O Port 1 GPIO bit 8 EMC_A[9]/P1[9] P1 VDD_EMC I/O EMC address bit 9 I/O Port 1 GPIO bit 9 EMC_A[10]/P1[10] P2 VDD_EMC I/O EMC address bit 10 I/O Port 1 GPIO bit 10 EMC_A[11]/P1[11] P3 VDD_EMC I/O EMC address bit 11 I/O Port 1 GPIO bit 11 EMC_A[12]/P1[12] N4 VDD_EMC I/O EMC address bit 12 I/O Port 1 GPIO bit 12 EMC_A[13]/P1[13] R1 VDD_EMC I/O EMC address bit 13 I/O Port 1 GPIO bit 13 EMC_A[14]/P1[14] R2 VDD_EMC I/O EMC address bit 14 I/O Port 1 GPIO bit 14 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 11 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_A[15]/P1[15] L1 VDD_EMC I/O EMC address bit 15 I/O Port 1 GPIO bit 15 EMC_A[16]/P1[16] K3 VDD_EMC I/O EMC address bit 16 I/O Port 1 GPIO bit 16 EMC_A[17]/P1[17] K4 VDD_EMC I/O EMC address bit 17 I/O Port 1 GPIO bit 17 EMC_A[18]/P1[18] K2 VDD_EMC I/O EMC address bit 18 I/O Port 1 GPIO bit 18 EMC_A[19]/P1[19] K1 VDD_EMC I/O EMC address bit 19 I/O Port 1 GPIO bit 19 EMC_A[20]/P1[20] J1 VDD_EMC I/O EMC address bit 20 I/O Port 1 GPIO bit 20 EMC_A[21]/P1[21] J2 VDD_EMC I/O EMC address bit 21 I/O Port 1 GPIO bit 21 EMC_A[22]/P1[22] J3 VDD_EMC I/O EMC address bit 22 I/O Port 1 GPIO bit 22 EMC_A[23]/P1[23] J4 VDD_EMC I/O EMC address bit 23 I/O Port 1 GPIO bit 23 EMC_BLS[0] U14 VDD_EMC O Static memory byte lane 0 select EMC_BLS[1] T13 VDD_EMC O Static memory byte lane 1 select EMC_BLS[2] R12 VDD_EMC O Static memory byte lane 2 select EMC_BLS[3] P12 VDD_EMC O Static memory byte lane 3 select EMC_CAS R5 VDD_EMC O SDRAM column address strobe out, active LOW EMC_CKE0 U3 VDD_EMC O Clock enable out for SDRAM bank 0 EMC_CKE1 L2 VDD_EMC O Clock enable out for SDRAM bank 1 EMC_CLK T3 VDD_EMC O SDRAM clock out EMC_CLKIN T4 VDD_EMC I SDRAM clock feedback EMC_CS0 U13 VDD_EMC O EMC static memory chip select 0 EMC_CS1 R11 VDD_EMC O EMC static memory chip select 1 EMC_CS2 T12 VDD_EMC O EMC static memory chip select 2 EMC_CS3 V15 VDD_EMC O EMC static memory chip select 3 EMC_D[0] U4 VDD_EMC I/O: BK EMC data bit 0 EMC_D[1] R7 VDD_EMC I/O: BK EMC data bit 1 EMC_D[2] T5 VDD_EMC I/O: BK EMC data bit 2 EMC_D[3] U5 VDD_EMC I/O: BK EMC data bit 3 EMC_D[4] V3 VDD_EMC I/O: BK EMC data bit 4 EMC_D[5] V4 VDD_EMC I/O: BK EMC data bit 5 EMC_D[6] T6 VDD_EMC I/O: BK EMC data bit 6 EMC_D[7] R8 VDD_EMC I/O: BK EMC data bit 7 EMC_D[8] V5 VDD_EMC I/O: BK EMC data bit 8 Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 12 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_D[9] U6 VDD_EMC I/O: BK EMC data bit 9 EMC_D[10] V6 VDD_EMC I/O: BK EMC data bit 10 EMC_D[11] T7 VDD_EMC I/O: BK EMC data bit 11 EMC_D[12] U7 VDD_EMC I/O: BK EMC data bit 12 EMC_D[13] V7 VDD_EMC I/O: BK EMC data bit 13 EMC_D[14] T8 VDD_EMC I/O: BK EMC data bit 14 EMC_D[15] U8 VDD_EMC I/O: BK EMC data bit 15 EMC_D[16]/ EMC_DQS0 V8 VDD_EMC I/O: BK EMC data bit 16 I/O: BK DDR data strobe 0 EMC_D[17]/ EMC_DQS1 R9 VDD_EMC I/O: BK EMC data bit 17 I/O: BK DDR data strobe 1 EMC_D[18]/ EMC_CLK V9 VDD_EMC I/O: P EMC data bit 18 I/O: P DDR inverted clock output EMC_D[19]/P2[0] U9 VDD_EMC I/O: P EMC data bit 19 I/O: P Port 2 GPIO bit 0 EMC_D[20]/P2[1] T9 VDD_EMC I/O: P EMC data bit 20 I/O: P Port 2 GPIO bit 1 EMC_D[21]/P2[2] V10 VDD_EMC I/O: P EMC data bit 21 I/O: P Port 2 GPIO bit 2 EMC_D[22]/P2[3] U10 VDD_EMC I/O: P EMC data bit 22 I/O: P Port 2 GPIO bit 3 EMC_D[23]/P2[4] T10 VDD_EMC I/O: P EMC data bit 23 I/O: P Port 2 GPIO bit 4 EMC_D[24]/P2[5] R10 VDD_EMC I/O: P EMC data bit 24 I/O: P Port 2 GPIO bit 5 EMC_D[25]/P2[6] V11 VDD_EMC I/O: P EMC data bit 25 I/O: P Port 2 GPIO bit 6 EMC_D[26]/P2[7] U11 VDD_EMC I/O: P EMC data bit 26 I/O: P Port 2 GPIO bit 7 EMC_D[27]/P2[8] T11 VDD_EMC I/O: P EMC data bit 27 I/O: P Port 2 GPIO bit 8 EMC_D[28]/P2[9] V12 VDD_EMC I/O: P EMC data bit 28 I/O: P Port 2 GPIO bit 9 EMC_D[29]/P2[10] V13 VDD_EMC I/O: P EMC data bit 29 I/O: P Port 2 GPIO bit 10 EMC_D[30]/P2[11] U12 VDD_EMC I/O: P EMC data bit 30 I/O: P Port 2 GPIO bit 11 EMC_D[31]/P2[12] V14 VDD_EMC I/O: P EMC data bit 31 I/O: P Port 2 GPIO bit 12 EMC_DQM[0] R3 VDD_EMC O SDRAM data mask 0 out Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 13 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers EMC_DQM[1] P4 VDD_EMC O SDRAM data mask 1 out EMC_DQM[2] T1 VDD_EMC O SDRAM data mask 2 out EMC_DQM[3] P5 VDD_EMC O SDRAM data mask 3 out EMC_DYCS0 R6 VDD_EMC O SDRAM active LOW chip select 0 EMC_DYCS1 G1 VDD_EMC O SDRAM active LOW chip select 1 EMC_OE H1 VDD_EMC O EMC static memory output enable EMC_RAS T2 VDD_EMC O SDRAM row address strobe, active LOW EMC_WR R4 VDD_EMC O EMC write strobe, active LOW FLASH_ALE D2 VDD_IOC O Flash address latch enable FLASH_CE E3 VDD_IOC O Flash chip enable FLASH_CLE F3 VDD_IOC O Flash command latch enable FLASH_IO[0] H2 VDD_IOC I/O: BK Flash data bus, bit 0 FLASH_IO[1] H3 VDD_IOC I/O: BK Flash data bus, bit 1 FLASH_IO[2] F1 VDD_IOC I/O: BK Flash data bus, bit 2 FLASH_IO[3] E1 VDD_IOC I/O: BK Flash data bus, bit 3 FLASH_IO[4] H4 VDD_IOC I/O: BK Flash data bus, bit 4 FLASH_IO[5] G2 VDD_IOC I/O: BK Flash data bus, bit 5 FLASH_IO[6] G3 VDD_IOC I/O: BK Flash data bus, bit 6 FLASH_IO[7] E2 VDD_IOC I/O: BK Flash data bus, bit 7 FLASH_RD C1 VDD_IOC O Flash read enable FLASH_RDY D1 VDD_IOC I Flash ready (from flash device) FLASH_WR F2 VDD_IOC O Flash write enable GPI_0/I2S1RX_SDA C16 VDD_IOD I General purpose input 0 I I2S1 Receive data GPI_1/SERVICE C15 VDD_IOD I General purpose input 1 I Boot select input GPI_2/CAP2[0]/ ENET_RXD3 C14 VDD_IOD I General purpose input 2 I Timer 2 capture input 0 I Ethernet receive data 3 (LPC3240 and LPC3250 only) GPI_3 F4 VDD_IOC I General purpose input 3 GPI_4/SPI1_BUSY E13 VDD_IOD I General purpose input 4 I SPI1 busy input GPI_5/U3_DCD N16 VDD_IOA I General purpose input 5 I UART 3 data carrier detect input GPI_6/ HSTIM_CAP/ ENET_RXD2 C7 VDD_IOB I: BK General purpose input 6 I: BK High-speed timer capture input I : BK Ethernet receive data 2 (LPC3240 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 14 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers GPI_7/CAP4[0]/ MCABORT D13 VDD_IOD I General purpose input 7 I Timer 4 capture input 0 I Motor control PWM LOW-active fast abort input GPI_8/KEY_COL6/ SPI2_BUSY/ ENET_RX_DV B16 VDD_IOD I General purpose input 8 I Keyscan column 6 input I SPI2 busy input I Ethernet receive data valid input (LPC3240 and LPC3250 only) GPI_9/KEY_COL7/ ENET_COL E12 VDD_IOD I General purpose input 9 I Keyscan column 7 input I Ethernet collision input (LPC3240 and LPC3250 only) GPI_19/U4_RX B15 VDD_IOD I General purpose input 19 I UART 4 receive GPI_28/U3_RI N17 VDD_IOA I General purpose input 28 I UART 3 ring indicator input GPIO_0 A12 VDD_IOD I/O General purpose input/output 0 GPIO_1 A11 VDD_IOD I/O General purpose input/output 1 GPIO_2/ KEY_ROW6/ ENET_MDC D9 VDD_IOD I/O General purpose input/output 2 O Keyscan row 6 output O Ethernet PHY interface clock (LPC3240 and LPC3250 only) GPIO_3/ KEY_ROW7/ ENET_MDIO C11 VDD_IOD I/O General purpose input/output 3 I/O Keyscan row 7 output I/O Ethernet PHY interface data (LPC3240 and LPC3250 only) GPIO_4/ SSEL1/ LCDVD[22] B11 VDD_IOD I/O General purpose input/output 4 I/O SSP1 Slave Select I/O LCD data bit 22 (LPC3230 and LPC3250 only) GPIO_5/ SSEL0/ MCI0 E9 VDD_IOD I/O General purpose input/output 5 I/O SSP0 Slave Select I/O Motor control channel 0 input GPO_0/ TST_CLK1 C3 VDD_IOC O General purpose output 0 O Test clock 1 out GPO_1 D4 VDD_IOC O General purpose output 1 GPO_2/ MAT1[0]/ LCDVD[0] B14 VDD_IOD O General purpose output 2 O Timer 1 match output 0 O LCD data bit 0 (LPC3230 and LPC3250 only) GPO_3/ LCDVD[1] D12 VDD_IOD O General purpose output 3 O LCD data bit 1 (LPC3230 and LPC3250 only) GPO_4 D8 VDD_IOB O General purpose output 4 Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 15 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers GPO_5 B3 VDD_IOC O General purpose output 5 GPO_6/ LCDVD[18] A16 VDD_IOD O General purpose output 6 O LCD data bit 18 (LPC3230 and LPC3250 only) GPO_7/ LCDVD[2] A15 VDD_IOD O General purpose output 7 O LCD data bit 2 (LPC3230 and LPC3250 only) GPO_8/ LCDVD[8] C13 VDD_IOD O General purpose output 8 O LCD data bit 8 (LPC3230 and LPC3250 only) GPO_9/ LCDVD[9] C12 VDD_IOD O General purpose output 9 O LCD data bit 9 (LPC3230 and LPC3250 only) GPO_10/ MCOB2/ LCDPWR E11 VDD_IOD O General purpose output 10 O Motor control PWM channel 2, output B O LCD panel power enable (LPC3230 and LPC3250 only) GPO_11 E8 VDD_IOB O General purpose output 11 GPO_12/ MCOA2/ LCDLE B12 VDD_IOD O General purpose output 12 O Motor control PWM channel 2, output A O LCD line end signal (LPC3230 and LPC3250 only) GPO_13/ MCOB1/ LCDDCLK B13 VDD_IOD O General purpose output 13 O Motor control PWM channel 1, output B O LCD clock output (LPC3230 and LPC3250 only) GPO_14 D3 VDD_IOC O General purpose output 14 GPO_15/ MCOA1/ LCDFP A14 VDD_IOD O General purpose output 15 O Motor control PWM channel 1, output A O LCD frame/sync pulse (LPC3230 and LPC3250 only) GPO_16/ MCOB0/ LCDENAB/LCDM D10 VDD_IOD O General purpose output 16 O Motor control PWM channel 0, output B O LCD STN AC bias/TFT data enable (LPC3230 and LPC3250 only) GPO_17 N18 VDD_IOA O General purpose output 17 GPO_18/ MCOA0/ LCDLP D11 VDD_IOD O General purpose output 18 O Motor control PWM channel 0, output A O LCD line sync/horizontal sync (LPC3230 and LPC3250 only) GPO_19 C2 VDD_IOC O General purpose output 19 GPO_20 B2 VDD_IOC O General purpose output 20 GPO_21/ U4_TX/ LCDVD[3] A13 VDD_IOD O General purpose output 21 O UART 4 transmit O LCD data bit 3 (LPC3230 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 16 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers GPO_22/ U7_HRTS/ LCDVD[14] E10 VDD_IOD O General purpose output 22 O HS UART 7 RTS out O LCD data bit 14 (LPC3230 and LPC3250 only) GPO_23/ U2_HRTS/ U3_RTS M16 VDD_IOA O General purpose output 23 O HS U ART 2 RTS out O UART 3 RTS out HIGHCORE/ LCDVD[17] H16 VDD_IOD O Core voltage control out O LCD data bit 17 (LPC3230 and LPC3250 only) I2C1_SCL A5 VDD_IOB I/O T I2C1 serial clock input/output I2C1_SDA B6 VDD_IOB I/O T I2C1 serial data input/output I2C2_SCL A3 VDD_IOC I/O T I2C2 serial clock input/output I2C2_SDA E4 VDD_IOC I/O T I2C2 serial data input/output I2S1TX_CLK/ MAT3[0] A4 VDD_IOB I/O I2S1 transmit clock O Timer 3 match output 0 I2S1TX_SDA/ MAT3[1] E7 VDD_IOB I/O I2S1 transmit data O Timer 3 match output 1 I2S1TX_WS/ CAP3[0] B4 VDD_IOB I/O I2S1 transmit word select I/O Timer 3 capture input 0 JTAG_NTRST H17 VDD_IOD I: PU JTAG1 reset input. Must be LOW during power-on reset. JTAG_RTCK H18 VDD_IOD O JTAG1 return clock out JTAG_TCK H14 VDD_IOD I JTAG1 clock input JTAG_TDI J16 VDD_IOD I: PU JTAG1 data input JTAG_TDO J15 VDD_IOD O JTAG1 data out JTAG_TMS G18 VDD_IOD I: PU TAG1 test mode select input KEY_COL0/ ENET_TX_CLK F15 VDD_IOD I Keyscan column 0 input I Ethernet transmit clock (LPC3240 and LPC3250 only) KEY_COL1/ ENET_RX_CLK/ ENET_REF_CLK E16 VDD_IOD I Keyscan column 1 input I Ethernet receive clock (MII mode, LPC3240 and LPC3250 only) I Ethernet reference clock (RMII mode, LPC3240 and LPC3250 only) KEY_COL2/ ENET_RX_ER D17 VDD_IOD I Keyscan column 2 input I Ethernet receive error input (LPC3240 and LPC3250 only) KEY_COL3/ ENET_CRS D18 VDD_IOD I Keyscan column 3 input I Ethernet carrier sense input (LPC3240 and LPC3250 only) KEY_COL4/ ENET_RXD0 G15 VDD_IOD I Keyscan column 4 input I Ethernet receive data 0 (LPC3240 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 17 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers KEY_COL5/ ENET_RXD1 F16 VDD_IOD I Keyscan column 5 input I Ethernet receive data 1 (LPC3240 and LPC3250 only) KEY_ROW0/ ENET_TX_ER E15 VDD_IOD I/O T Keyscan row 0 out I/O T Ethernet transmit error (LPC3240 and LPC3250 only) KEY_ROW1/ ENET_TXD2 E14 VDD_IOD I/O T Keyscan row 1 out I/O T Ethernet transmit data 2 (LPC3240 and LPC3250 only) KEY_ROW2/ ENET_TXD3 F14 VDD_IOD I/O T Keyscan row 2 out I/O T Ethernet transmit data 3 (LPC3240 and LPC3250 only) KEY_ROW3/ ENET_TX_EN D16 VDD_IOD I/O T Keyscan row 3 out I/O T Ethernet transmit enable (LPC3240 and LPC3250 only) KEY_ROW4/ ENET_TXD0 C17 VDD_IOD I/O T Keyscan row 4 out I/O T Ethernet transmit data 0 (LPC3240 and LPC3250 only) KEY_ROW5/ ENET_TXD1 C18 VDD_IOD I/O T Keyscan row 5 out I/O T Ethernet transmit data 1 (LPC3240 and LPC3250 only) MS_BS/MAT2[1] A6 VDD_IOD I/O: P MS/SD card command out O Timer 2 match output 1 MS_DIO0/MAT0[0] A8 VDD_IOD I/O: P MS/SD card data 0 O Timer 0 match output 0 MS_DIO1/ MAT0[1] A7 VDD_IOD I/O: P MS/SD card data 1 O Timer 0 match output 1 MS_DIO2/ MAT0[2] B8 VDD_IOD I/O: P MS/SD card data 2 O Timer 0 match output 2 MS_DIO3/ MAT0[3] C8 VDD_IOD I/O: P MS/SD card data 3 O Timer 0 match output 3 MS_SCLK/ MAT2[0] B7 VDD_IOD I/O MS/SD card clock output O Timer 2 match output 0 n.c. B17, U17, U2 - - not connected ONSW M15 VDD_RTC O RTC match output for external power control P0[0]/ I2S1RX_CLK B5 VDD_IOB I/O Port 0 GPIO bit 0 I/O I2S1 receive clock P0[1]/ I2S1RX_WS D7 VDD_IOB I/O Port 0 GPIO bit 1 I/O I2S1 receive word select Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 18 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers P0[2]/ I2S0RX_SDA/ LCDVD[4] M17 VDD_IOA I/O Port 0 GPIO bit 2 I/O I2S0 receive data I/O LCD data bit 4 (LPC3230 and LPC3250 only) P0[3]/ I2S0RX_CLK/ LCDVD[5] M18 VDD_IOA I/O Port 0 GPIO bit 3 I/O I2S0 receive clock I/O LCD data bit 5 (LPC3230 and LPC3250 only) P0[4]/ I2S0RX_WS/ LCDVD[6] L15 VDD_IOA I/O Port 0 GPIO bit 4 I/O I2S0 receive word select I/O LCD data bit 6 (LPC3230 and LPC3250 only) P0[5]/ I2S0TX_SDA/ LCDVD[7] L16 VDD_IOA I/O Port 0 GPIO bit 5 I/O I2S0 transmit data I/O LCD data bit 7 (LPC3230 and LPC3250 only) P0[6]/ I2S0TX_CLK/ LCDVD[12] L17 VDD_IOA I/O Port 0 GPIO bit 6 I/O I2S0 transmit clock I/O LCD data bit 12 (LPC3230 and LPC3250 only) P0[7]/ I2S0TX_WS/ LCDVD[13] L18 VDD_IOA I/O Port 0 GPIO bit 7 I/O I2S0 transmit word select I/O LCD data bit 13 (LPC3230 and LPC3250 only) PLL397_LOOP R14 VDD_PLL397 analog filter PLL397 loop filter (for external components) PWM_OUT1/ LCDVD[16] D14 VDD_IOD O PWM1 out O LCD data bit 16 (LPC3230 and LPC3250 only) PWM_OUT2/INTSTAT/ LCDVD[19] D15 VDD_IOD O PWM2 output/internal interrupt status[1] O LCD data bit 19 (LPC3230 and LPC3250 only) RESET M14 VDD_RTC I Reset input, active LOW RESOUT G4 VDD_IOC O Reset out. Reflects external and WDT reset RTCX_IN P16 VDD_RTC analog in RTC oscillator input RTCX_OUT P17 VDD_RTC analog out RTC oscillator output SPI1_CLK/ SCK0 C9 VDD_IOD O SPI1 clock out O SSP0 clock out SPI1_DATIN/ MISO0/ GPI_25/ MCI1 C10 VDD_IOD I/O SPI1 data in I/O SSP0 MISO I/O General purpose input bit 25 I Motor control channel 1 input SPI1_DATIO/ MOSI0/ MCI2 B9 VDD_IOD I/O SPI1 data out (and optional input) I/O SSP0 MOSI I Motor control channel 2 input SPI2_CLK/ SCK1/ LCDVD[23] B10 VDD_IOD I/O SPI2 clock out I/O SSP1 clock out I/O LCD data bit 23 (LPC3230 and LPC3250 only) Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 19 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers SPI2_DATIO/ MOSI1/ LCDVD[20] A9 VDD_IOD I/O SPI2 data out (and optional input) I/O SSP1 MOSI I/O LCD data bit 20 (LPC3230 and LPC3250 only) SPI2_DATIN/ MISO1/ LCDVD[21]/ GPI_27 A10 VDD_IOD I/O SPI2 data in I/O SSP1 MISO I/O LCD data 21 (LPC3230 and LPC3250 only) I/O General purpose input bit 27 SYSCLKEN/ LCDVD[15] G17 VDD_IOD I/O T Clock request out for external clock source I/O T LCD data bit 15 (LPC3230 and LPC3250 only) SYSX_IN T17 VDD_OSC analog in System clock oscillator input SYSX_OUT R15 VDD_OSC analog out System clock oscillator output TS_XP R13 VDD_AD I/O Touchscreen X output TS_YP U16 VDD_AD I/O Touchscreen Y output TST_CLK2 C6 VDD_IOB O Test clock 2 out U1_RX/CAP1[0]/ GPI_15 K15 VDD_IOA I/O HS UART 1 receive I/O Timer 1 capture input 0 I/O General purpose input bit 15 U1_TX K16 VDD_IOA O HS UART 1 transmit U2_HCTS/ U3_CTS/GPI_16 J18 VDD_IOA I/O HS UART 2 Clear to Send input I UART 3 Clear to Send I/O General purpose input bit 16 U2_RX/ U3_DSR/GPI_17 K18 VDD_IOA I/O HS UART 2 receive I/O UART 3 data set ready I/O General purpose input bit 17 U2_TX/U3_DTR K17 VDD_IOA O HS UART 2 transmit O UART 3 data terminal ready out U3_RX/ GPI_18 J14 VDD_IOD I/O UART 3 receive I/O General purpose input bit 18 U3_TX J17 VDD_IOD O UART 3 transmit U5_RX/ GPI_20 F18 VDD_IOD I/O UART 5 receive I General purpose input bit 20 U5_TX H15 VDD_IOD O UART 5 transmit U6_IRRX/ GPI_21 F17 VDD_IOD I/O UART 6 receive (with IrDA) I General purpose input bit 21 U6_IRTX G16 VDD_IOD O UART 6 transmit (with IrDA) U7_HCTS/ CAP0[1]/ LCDCLKIN/ GPI_22 G13 VDD_IOD I HS UART 7 CTS in I Timer 0 capture input 1 I LCD panel clock in (LPC3230 and LPC3250 only) I General purpose input bit 22 Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 20 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers U7_RX/ CAP0[0]/ LCDVD[10]/ GPI_23 E17 VDD_IOD I/O HS UART 7 receive I/O Timer 0 capture input 0 I/O LCD data bit 10 (LPC3230 and LPC3250 only) I/O General purpose input bit 23 U7_TX/ MAT1[1]/ LCDVD[11] E18 VDD_IOD O HS UART 7 transmit O Timer 1 match output 1 O LCD data bit 11 (LPC3230 and LPC3250 only) USB_ATX_INT C4 VDD_IOC I Interrupt from USB ATX USB_DAT_VP/ U5_RX D5 VDD_IOC I/O: P USB transmit data, D+ receive I/O: P UART 5 receive USB_I2C_SCL E5 VDD_IOC I/O T I2C clock for USB ATX interface USB_I2C_SDA E6 VDD_IOC I/O T I2C data for USB ATX interface USB_OE_TP D6 VDD_IOC I/O USB transmit enable for DAT/SE0 USB_SE0_VM/ U5_TX C5 VDD_IOC I/O: P USB single ended zero transmit, D Receive I/O: P UART 5 transmit VDD_AD N12, N13 VDD_AD power 3.3 V supply for ADC/touch screen VDD_CORE G7, G9, G11, J7, J12, M7, M11 VDD_CORE power 1.2 V or 0.9 V supply for core VDD_COREFXD L12, M13 VDD_COREFXD power Fixed 1.2 V supply for digital portion of the analog block VDD_EMC J6, K6, K7, L6, M6, M8, N7, N8, N9, N10, N11 VDD_EMC power 1.8 V or 2.5 V or 3.3 V supply for External Memory Controller (EMC) VDD_IOA H13, J13 VDD_IOA power 1.8 V or 3.3 V supply for IOA domain VDD_IOB F8 VDD_IOB power 1.8 V or 3.3 V supply for IOB domain VDD_IOC F7, G6, H6, J5 VDD_IOC power 1.8 V or 3.3 V supply for IOC domain VDD_IOD F13, F9 VDD_IOD power 1.8 V to 3.3 V supply for IOD domain VDD_OSC T18 VDD_OSC power 1.2 V supply for main oscillator Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 21 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] The PWM2_CTRL register controls this pin function (see LPC32x0 User manual). VDD_PLL397 T16 VDD_PLL397 power 1.2 V supply for 397x PLL VDD_PLLHCLK R17 VDD_PLLHCLK power 1.2 V supply for HCLK PLL VDD_PLLUSB P15 VDD_PLLUSB power 1.2 V supply for USB PLL VDD_FUSE N14 VDD_FUSE power 1.2 V supply VDD_RTC K14 VDD_RTC power 1.2 V supply for RTC I/O VDD_RTCCORE L13 VDD_RTCCORE power 1.2 V supply for RTC VDD_RTCOSC N15 VDD_RTCOSC power 1.2 V supply for RTC oscillator VSS_AD P13 - power Ground for ADC/touch screen VSS_CORE G8, G10, G12, H7, K12, L7, M9, M10, M12 - power Ground for core VSS_EMC K5, L5, M5, N5, N6, P6, P7, P8, P9, P10, P11 - power Ground for EMC VSS_IOA K13 - power Ground VDD_IOA domain VSS_IOB F6 - power Ground VDD_IOB domain VSS_IOC F5, G5, H5 - power Ground VDD_IOC domain VSS_IOD F10, F11, F12, H12 - power Ground VDD_IOD domain VSS_OSC P14 - power Ground for main oscillator VSS_PLL397 T15 - power Ground for 397x PLL VSS_PLLHCLK R18 - power Ground for HCLK PLL VSS_PLLUSB R16 - power Ground for USB PLL VSS_RTCCORE L14 - power Ground for RTC VSS_RTCOSC P18 - power Ground for RTC oscillator Table 4. Pin description …continued Symbol Pin Power supply domain Type Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 22 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] See LPC32x0 User manual for details. Table 5. Digital I/O pad types[1] Parameter Abbreviation I/O type I = input. O = output. I/O = bidirectional. I/O T = bidirectional or high impedance. Pin detail BK: pin has a bus keeper function that weakly retains the last logic level driven on an I/O pin. Bus keeper current for different I/O pin voltages: 0 V= 1 A (max) VDD_x = 1 A (max) 2/3  VDD_x = 55 A (max) 1/3  VDD_x = 60 A (max) PU: pin has a nominal 50 A internal pull-up connected. PD: pin has a nominal 50 A internal pull-down connected. P: pin has programmable input characteristics. Table 6. Supply domains Supply domain Voltage range Related supply pins Description VDD_CORE 0.9 V to 1.39 V VDD_CORE Core power domain. VDD_COREFXD 1.2 V VDD_COREFXD Fixed 1.2 V supply for digital portion of the analog block. other core domains 1.2 V VDD_PLL397, VDD_PLLHCLK, VDD_PLLUSB, VDD_FUSE, VDD_OSC 1.2 V supplies, tied to VDD_COREFXD. VDD_RTC 0.9 V to 1.39 V VDD_RTC, VDD_RTCCORE, VDD_RTCOSC RTC supply domain. Can be connected to a battery backed-up power source. VDD_AD 2.7 V to 3.6 V VDD_AD 3.3 V supply for ADC and touch screen. VDD_EMC 1.7 V to 1.95 V 2.3 V to 2.7 V 2.7 V to 3.6 V VDD_EMC External memory interface IO pins in 1.8 V range, 2.5 V range, or 3.3 V range. VDD_IOA[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOA Peripheral supply. VDD_IOB[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOB Peripheral supply. VDD_IOC[1] 1.7 V to 1.95 V or 2.3 V to 3.6 V VDD_IOC Peripheral supply. VDD_IOD[1] 1.7 V to 1.95 V or 2.7 V to 3.6 V VDD_IOD Peripheral supply. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 23 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] The VDD_IOA, VDD_IOB, VDD_IOC, and VDD_IOD supply domains can be operated at a voltage independent of the other domains as long as all pins connected to the same peripheral are at the same voltage level. There are two special cases for determining supply domain voltages (for details see application note AN10777): a) Ethernet configured in MII mode: VDD_IOD must be the same as VDD_IOB. b) UART 3 when used with hardware flow control or when sharing an RS-232 transceiver with another UART: VDD_IOA must be the same as VDD_IOD. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 24 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7. Functional description 7.1 CPU and subsystems 7.1.1 CPU NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor. The ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the virtual memory capabilities required to support the multi-programming demands of modern operating systems. The basic ARM926EJ-S core V5TE instruction set includes DSP instruction extensions for native Jazelle Java Byte-code execution in hardware. The LPC3220/30/40/50 operates at CPU frequencies up to 266 MHz. 7.1.2 Vector Floating Point (VFP) coprocessor The LPC3220/30/40/50 includes a VFP co-processor providing full support for single-precision and double-precision add, subtract, multiply, divide, and multiply-accumulate operations at CPU clock speeds. It is compliant with the IEEE 754 standard for binary Floating-Point Arithmetic. This hardware floating point capability makes the microcontroller suitable for advanced motor control and DSP applications. The VFP has 3 separate pipelines for floating-point MAC operations, divide or square root operations, and Load/Store operations. These pipelines operate in parallel and can complete execution out of order. All single-precision instructions execute in one cycle, except the divide and square root instructions. All double-precision multiply and multiply-accumulate instructions take two cycles. The VFP also provides format conversions between floating-point and integer word formats. 7.1.3 Emulation and debugging The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application. 7.1.3.1 Embedded ICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an Embedded ICE protocol converter. The Embedded ICE protocol converter converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel (DCC) function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or entering the debug state. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 25 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.1.3.2 Embedded trace buffer The Embedded Trace Module (ETM) is connected directly to the ARM core. It compresses the trace information and exports it through a narrow trace port. An internal Embedded Trace Buffer (ETB) of 2048  24 bits captures the trace information under software debugger control. Data from the ETB is recovered by the debug software through the JTAG port. The trace contains information about when the ARM core switches between states. Instruction shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. For data accesses either data or address or both can be traced. 7.2 AHB matrix The LPC3220/30/40/50 has a multi-layer AHB matrix for inter-block communication. AHB is an ARM defined high-speed bus, which is part of the ARM bus architecture. AHB is a high-bandwidth low-latency bus that supports multi-master arbitration and a bus grant/request mechanism. For systems that have only one (CPU), or two (CPU and DMA) bus masters a simple AHB works well. However, if a system requires multiple bus masters and the CPU needs access to external memory, a single AHB bus can cause a bottleneck. To increase performance, the LPC3220/30/40/50 uses an expanded AHB architecture known as Multi-layer AHB. A Multi-layer AHB replaces the request/grant and arbitration mechanism used in a simple AHB with an interconnect matrix that moves arbitration out toward the slave devices. Thus, if a CPU and a DMA controller want access to the same memory, the interconnect matrix arbitrates between the two when granting access to the memory. This advanced architecture allows simultaneous access by bus masters to different resources with an increase in arbitration complexity. In this architectural implementation, removing guaranteed central arbitration and allowing more than one bus master to be active at the same time provides better overall microcontroller performance. In the LPC3220/30/40/50, the multi-Layer AHB system has a separate bus for each of seven AHB Masters: • CPU data bus • CPU instruction bus • General purpose DMA Master 0 • General purpose DMA Master 1 • Ethernet controller • USB controller • LCD controller There are no arbitration delays unless two masters attempt to access the same slave at the same time. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 26 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions. A write access to FAB peripherals takes a single AHB clock and a read access to FAB peripherals takes two AHB clocks. 7.3 Physical memory map The physical memory map incorporates several distinct regions, as shown in Figure 3. When an application is running, the CPU interrupt vectors are re-mapped to allow them to reside in on-chip SRAM (IRAM). LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 27 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 3. LPC3220/30/40/50 memory map on-chip memory 0x4000 0000 0x0000 0000 0.0 GB 768 MB 1.0 GB 4.0 GB peripherals on AHB matrix slave port 5 0x0FFF FFFF 0x2000 0000 0x3000 0000 0x2FFF FFFF 0x1FFF FFFF 0x8000 0000 0xFFFF FFFF 0x1000 0000 0x3FFF FFFF 0x4FFF FFFF 0x5000 0000 0x7FFF FFFF peripherals on AHB matrix slave port 6 peripherals on AHB matrix slave port 7 off-chip memory IROM or IRAM 0x0000 0000 to 0x03FF FFFF dummy space for DMA 0x0400 0000 to 0x07FF FFFF IRAM 0x0800 0000 to 0x0BFF FFFF IROM 0x0C00 0000 to 0x0FFF FFFF AHB peripherals 0x2000 0000 to 0x2007 FFFF AHB peripherals 0x200A 0000 to 0x200B FFFF APB peripherals 0x2008 0000 to 0x2009 FFFF RESERVED AHB peripherals 0x3000 0000 to 0x31FF FFFF RESERVED FAB peripherals 0x4000 0000 to 0x4007 FFFF APB peripherals 0x4008 0000 to 0x400F FFFF RESERVED RESERVED RESERVED RESERVED RESERVED 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xE0FF FFFF 0xE100 0000 0xE1FF FFFF 0xE200 0000 0xE2FF FFFF 0xE300 0000 0xE3FF FFFF 0xE400 0000 2.0 GB EMC_DYCS0 EMC_DYCS1 EMC_CS0 EMC_CS1 EMC_CS2 EMC_CS3 002aae468 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 28 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.4 Internal memory 7.4.1 On-chip ROM The built-in 16 kB ROM contains a program which runs a boot procedure to load code from one of four external sources, UART 5, SSP0 (SPI mode), EMC Static CS0 memory, or NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot and can download a program over serial link UART 5 to IRAM and transfer execution to the downloaded code. If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot process first tests SPI memory for boot information if present it uploads the boot code and transfers execution to the uploaded software. If the SPI is not present or no software is loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code and if present boots from static memory, If this test fails the boot loader will test external NAND flash for boot code and boot if code is present. The boot loader consumes no user memory space because it is in ROM. 7.4.2 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM. 7.5 External memory interfaces The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash controllers, Secure Digital Memory Controller, and an external memory controller for SDRAM, DDR SDRAM, and Static Memory devices. 7.5.1 NAND flash controllers The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell NAND flash devices and one for single-level cell NAND flash devices. The two NAND flash controllers use the same pins to interface to external NAND flash devices, so only one interface is active at a time. 7.5.1.1 Multi-Level Cell (MLC) NAND flash controller The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash devices. An external NAND flash device is used to allow the bootloader to automatically load a portion of the application code into internal SRAM for execution following reset. The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages. Programmable NAND timing parameters allow support for a variety of NAND flash devices. A built-in Reed-Solomon encoder/decoder provides error detection and correction capability. A 528 byte data buffer reduces the need for CPU supervision during loading. The MLC NAND flash controller also provides DMA support. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 29 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.5.1.2 Single-Level Cell (SLC) NAND flash controller The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error. 7.5.2 SD card controller The SD interface allows access to external SD memory cards. The SD card interface conforms to the SD Memory Card Specification Version 1.01. 7.5.2.1 Features • 1-bit and 4-bit data line interface support. • DMA is supported through the system DMA controller. • Provides all functions specific to the SD memory card. These include the clock generation unit, power management control, command and data transfer. 7.5.3 External memory controller The LPC3220/30/40/50 includes a memory controller that supports data bus SDRAM, DDR SDRAM, and static memory devices. The memory controller provides an interface between the system bus and external (off-chip) memory devices. The controller supports 16-bit and 32-bit wide SDR SDRAM devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes, as well as 16-bit wide data bus DDR SDRAM devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes. Two dynamic memory chip selects are supplied, supporting two groups of SDRAM: • DYCS0 in the address range 0x8000 0000 to 0x9FFF FFFF • DYCS1 in the address range 0xA000 0000 to 0xBFFF FFFF The memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static memory devices, including RAM, ROM, and flash, with or without asynchronous page mode. Four static memory chip selects are supplied for SRAM devices: • CS0 in the address range 0xE000 0000 to 0xE0FF FFFF • CS1 in the address range 0xE100 0000 to 0xE1FF FFFF • CS2 in the address range 0xE200 0000 to 0xE2FF FFFF • CS3 in the address range 0xE300 0000 to 0xE3FF FFFF The SDRAM controller uses three data ports to allow simultaneous requests from multiple on-chip AHB bus masters and has the following features. • Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants. • Read and write buffers to reduce latency and improve performance. • Static memory features include – asynchronous page mode read – programmable wait states – bus turnaround cycles – output enable and write enable delays LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 30 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers – extended wait • Power-saving modes dynamically control EMC_CKE[1:0] and EMC_CLK. • Dynamic memory self-refresh mode supported by software. • Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is, typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per device. • Two reset domains enable dynamic memory contents to be preserved over a soft reset. • This controller does not support synchronous static memory devices (burst mode devices). 7.6 AHB master peripherals The LPC3220/30/40/50 implements four AHB master peripherals, which include a General Purpose Direct Memory Access (GPDMA) controller, a 10/100 Ethernet Media Access Controller (MAC), a Universal Serial Bus (USB) controller, and an LCD controller. Each of these four peripherals contain an integral DMA controller optimized to support the performance demands of the peripheral. 7.6.1 General Purpose DMA (GPDMA) controller The GPDMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the same AHB master, or one area by each master. The DMA controller supports the following peripheral device transfers. • Secure Digital (SD) Memory interface • High-speed UARTs • I2S0 and I2S1 ports • SPI1 and SPI2 interfaces • SSP0 and SSP1 interfaces • Memory The DMA controls eight DMA channels with hardware prioritization. The DMA controller interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian. Incrementing or non-incrementing addressing for source and destination are supported, as well as programmable DMA burst size. Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. 7.6.2 Ethernet MAC The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 31 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.6.2.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. Wake-on-LAN power management support allows system wake-up using the receive filters or a magic frame detection filter. • Physical interface – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. 7.6.3 USB interface The LPC3220/30/40/50 supports USB in either device, host, or OTG configuration. 7.6.3.1 USB device controller The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 32 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. Features • Fully compliant with USB 2.0 full-speed specification. • Supports 32 physical (16 logical) endpoints. • Supports control, bulk, interrupt and isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. • RAM message buffer size based on endpoint realization and maximum packet size. • Supports bus-powered capability with low suspend current. • Supports DMA transfer on all non-control endpoints. • One duplex DMA channel serves all endpoints. • Allows dynamic switching between CPU controlled and DMA modes. • Double buffer implementation for bulk and isochronous endpoints. 7.6.3.2 USB host controller The host controller enables data exchange with various USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies to the OHCI specification. Features • OHCI compliant. • OHCI specifies the operation and interface of the USB host controller and software driver. • The host controller has four USB states visible to the software driver: – USBOperational: Process lists and generate SOF tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wake-up activity. – USBResume: Forces resume signaling on the bus. • HCCA register points to interrupt and isochronous descriptors list. • ControlHeadED and BulkHeadED registers point to control and bulk descriptors list. 7.6.3.3 USB OTG controller USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. Features • Fully compliant with On-The-Go supplement to the USB Specification 2.0 Revision 1.0. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 33 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers • Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices under software control. HNP is partially implemented in hardware. • Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. • Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG specification compliant ATX. 7.6.4 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.6.4.1 Features • AHB bus master interface to access frame buffer. • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320  200, 320  240, 640  200, 640  240, 640  480, 800  600, and 1024  768. • Hardware cursor support for single-panel displays. • 15 gray-level monochrome, 3375 color STN, and 32 k color palettized TFT support. • 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. • 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. • 16 bpp true-color non-palettized, for color STN and TFT. • 24 bpp true-color non-palettized, for color TFT. • Programmable timing for different display panels. • 256 entry, 16-bit palette RAM, arranged as a 128  32 bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. • LCD panel clock may be generated from the peripheral clock or from a clock input pin. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 34 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.7 System functions To enhance the performance of the LPC3220/30/40/50 incorporates the following system functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and several power control features. These functions are described in the following sections 7.7.1 Interrupt controller The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled and configured for high or low level triggering, or rising or falling edge triggering. Each interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt status and masked interrupt status registers allow versatile condition evaluation. In addition to peripheral functions, each of the six general purpose input/output pins and 12 of the 22 general purpose input pins are connected directly to the interrupt controller. 7.7.2 Watchdog timer The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit counter. A match register is compared to the Timer. When configured for watchdog functionality, a match drives the match output low. The match output is gated with an enable signal that gives the opportunity to generate two type of reset signal: one that only resets chip internally, and another that goes through a programmable pulse generator before it goes to the external pin RESOUT and to the internal chip reset. 7.7.2.1 Features • Programmable 32-bit timer. • Internally resets the device if not periodically reloaded. • Flag to indicate that a watchdog reset has occurred. • Programmable watchdog pulse output on RESOUT pin. • Can be used as a standard timer if watchdog is not used. • Pause control to stop counting when core is in debug state. 7.7.3 Millisecond timer The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to obtain a lower count rate. The millisecond timer includes three match registers that are compared to the Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter either continue to run, stop, or be reset. 7.7.3.1 Features • 32-bit Timer/Counter, running from the 32 kHz RTC clock. • Counter or Timer operation. • Three 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Pause control to stop counting when core is in debug state. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 35 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.7.4 Clocking and power control features 7.7.4.1 Clocking Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed and some peripherals do this automatically. The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct run mode, and Stop mode.These three operational modes give control over processing speed and power consumption. In addition, clock rates to different functional blocks may be changed by switching clock sources, changing PLL values, or altering clock divider configurations. This allows a trade-off of power versus processing speed based on application requirements. 7.7.4.2 Crystal oscillator The main oscillator is the basis for the clocks most chip functions use by default. Optionally, many functions can be clocked instead by the output of a PLL (with a fixed 397x rate multiplication) which runs from the RTC oscillator. In this mode, the main oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency other than 13 MHz is required in the application, or if the USB block is not used, the main oscillator may be used with a frequency of between 1 MHz and 20 MHz. 7.7.4.3 PLLs The LPC3220/30/40/50 includes three PLLs: The 397x PLL allows boosting the RTC frequency to 13.008896 MHz for use as the primary system clock. The USB PLL provides the 48 MHz clock required by the USB block, and the HCLK PLL provides the basis for the CPU clock, the AHB bus clock, and the main peripheral clock. The 397x PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz clock. The 397x PLL is designed for low power operation and low jitter. This PLL requires an external RC loop filter for proper operation. The HCLK PLL accepts an input clock from either the main oscillator or the output of the 397x PLL. The USB PLL only accepts an input clock from the main oscillator.The USB input clock runs through a divide-by-N pre-divider before entering the USB PLL. The input to the HCLK and USB PLLs may initially be divided down by a pre-divider value ‘N’, which may have the values 1, 2, 3, or 4. This pre-divider can allow a greater number of possibilities for the output frequency. Following the PLL input divider is the PLL multiplier. This can multiply the pre-divider output by a value ‘M’, in the range of 1 through 256. The resulting frequency must be in the range of 156 MHz to 320 MHz. The multiplier works by dividing the output of a Current Controlled Oscillator (CCO) by the value of M, then using a phase detector to compare the divided CCO output to the pre-divider output. The error value is used to adjust the CCO frequency. At the PLL output, there is a post-divider that can be used to bring the CCO frequency down to the desired PLL output frequency. The post-divider value can divide the CCO output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 36 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers output to be used directly. The maximum PLL output frequency supported by the CPU is 266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock has strict requirements for nominal frequency (500 ppm) and jitter (500 ps). 7.7.4.4 Power control modes The LPC3220/30/40/50 supports three operational modes, two of which are specifically designed to reduce power consumption. The modes are: Run mode, Direct Run mode, and Stop mode. Run mode is the normal operating mode for applications that require the CPU, AHB bus, or any peripheral function other than the USB block to run faster than the main oscillator frequency. In Run mode, the CPU can run at up to 266 MHz and the AHB bus can run at up to 133 MHz. Direct Run mode allows reducing the CPU and AHB bus rates in order to save power. Direct Run mode can also be the normal operating mode for applications that do not require the CPU, AHB bus, or any peripheral function other than the USB block to run faster than the main oscillator frequency. Direct Run mode is the default mode following chip reset. Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals other than the USB block. 7.7.4.5 Reset Reset is accomplished by an active LOW signal on the RESET input pin. A reset pulse with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the oscillator to start up and stabilize after VDD reaches operational voltage. An internal reset with a minimum duration of 10 clock pulses will also be applied if the watchdog timer generates an internal device reset. The RESET pin is located in the RTC power domain. This means that the RTC power must be present for an external reset to have any effect. The RTC power domain nominally runs from 1.2 V, but the RESET pin can be driven as high as 1.95 V. 7.8 Communication peripheral interfaces In addition to the Ethernet MAC and USB interfaces there are many more serial communication peripheral interfaces available on the LPC3220/30/40/50. Here is a list of the serial communication interfaces: • Seven UARTs; four standard UARTs and three high-speed UARTs • Two SPI serial I/O controllers • Two SSP serial I/O controllers • Two I2C serial I/O controllers • Two I2S audio controllers A short functional description of each of these peripherals is provided in the following sections. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 37 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.8.1 UARTs The LPC3220/30/40/50 contains seven UARTs. Four are standard UARTs, and three are high-speed UARTs. 7.8.1.1 Standard UARTs The four standard UARTs are compatible with the INS16Cx50. These UARTs support rates up to 460800 bit/s from a 13 MHz peripheral clock. Features • Each standard UART has 64 byte Receive and Transmit FIFOs. • Receiver FIFO trigger points at 16, 32, 48, and 60 Bytes. • Transmitter FIFO trigger points at 0, 4, 8, and 16 Bytes. • Register locations conform to the “550” industry standard. • Each standard UART has a fractional rate pre-divider and an internal baud rate generator. • The standard UARTs support three clocking modes: on, off, and auto-clock. The auto-clock mode shuts off the clock to the UART when it is idle. • UART 6 includes an IrDA mode to support infrared communication. • The standard UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800) bit/s. • Each UART includes an internal loopback mode. 7.8.1.2 High-speed UARTs The three high-speed UARTs are designed to support rates up to 921600 bit/s from a 13 MHz peripheral clock for on-board communication in low noise conditions. This is accomplished by changing the over sampling from 16 to 14 and altering the rate generation logic. Features • Each high-speed UART has 64-byte Receive and Transmit FIFOs. • Receiver FIFO trigger points at 1, 4, 8, 16, 32, and 48 B. • Transmitter FIFO trigger points at 0, 4, and 8 B. • Each high-speed UART has an internal baud rate generator. • The high-speed UARTs are designed to support data rates of (2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600) bit/s. • The three high speed UARTs only support (8N1) 8-bit data word length, 1-stop bit, no parity, and no flow control as a the communications protocol. • Each UART includes an internal loopback mode. 7.8.2 SPI serial I/O controller The LPC3220/30/40/50 has two Serial Peripheral Interfaces (SPI). The SPI is a 3-wire serial interface that is able to interface with a large range of serial peripheral or memory devices (SPI mode 0 to 3 compatible slave devices). LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 38 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. The SPI implementation on the LPC3220/30/40/50 does not support operation as a slave. 7.8.2.1 Features • Supports slaves compatible with SPI modes 0 to 3. • Half duplex synchronous transfers. • DMA support for data transmit and receive. • 1-bit to 16-bit word length. • Choice of LSB or MSB first data transmission. • 64  16-bit input or output FIFO. • Bit rates up to 52 Mbit/s. • Busy input function. • DMA time out interrupt to allow detection of end of reception when using DMA. • Timed interrupt to facilitate emptying the FIFO at the end of a transmission. • SPI clock and data pins may be used as general purpose pins if the SPI is not used. • Slave selects can be supported using GPO or GPIO pins 7.8.3 SSP serial I/O controller The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.8.3.1 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • Maximum SPI bus data bit rate of 1⁄2 (Master mode) and 1⁄2 (Slave mode) of the input clock rate • DMA transfers supported by GPDMA 7.8.4 I2C-bus serial I/O controller There are two I2C-bus interfaces in the LPC32x0 family of controllers. These I2C blocks can be configured as a master, multi-master or slave supporting up to 400 kHz. The I2C blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit and receive. An interrupt signal is available from each block. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 39 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are only available when the controller is configured as a Master/Slave device and is operating in a multi-master environment. Separate TX FIFOs are needed in a multi-master because a controller might have a message queued for transmission when an external master addresses it to be come a slave-transmitter, a second source of data is needed. Note that the I2C clock must be enabled in the I2CCLK_CTRL register before using the I2C. The I2C clock can be disabled between communications, if used as a single master I2C-bus interface, software has full control of when I2C communication is taking place on the bus. 7.8.4.1 Features • The two I2C-bus blocks are standard I2C-bus compliant interfaces that may be used in Single-master, Multi-master or Slave modes. • Programmable clock to allow adjustment of I2C-bus transfer rates. • Bidirectional data transfer. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. 7.8.5 I2S-bus audio controller The I2S-bus provides a standard communication interface for digital audio applications The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. Each I2S connection can act as a master or a slave. The master connection determines the frequency of the clock line and all other slaves are driven by this clock source. The two I2S-bus interfaces on the LPC3220/30/40/50 provides a separate transmit and receive channel, providing a total of two transmit channels and two receive channels. Each I2S channel supports monaural or stereo formatted data. 7.8.5.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz, 32 kHz, 44.1 kHz, 48 kHz, 96 kHz). • Word select period can be configured in master mode (separately for I2S input and output). • Two eight-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop, and mute options separately for I2S input and I2S output. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 40 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.9 Other peripherals In addition to the communication peripherals there are many general purpose peripherals available in the LPC3220/30/40/50. Here is a list of the general purpose peripherals. • GPI/O • Keyboard scanner • Touch screen controller and 10-bit Analog-to-Digital-Converter • Real-time clock • High-speed timer • Four general purpose 32-bit timer/external event counters • Two simple PWMs • One motor control PWM A short functional description of each of these peripherals is provided in the following sections. 7.9.1 General purpose parallel I/O Some device pins that are not dedicated to a specific peripheral function have been designed to be general purpose inputs, outputs, or input/outputs. Also, some pins may be configured either as a specific peripheral function or a general purpose input, output, or input/output. A total of 51 pins can potentially be used as general purpose input/outputs, 24 as general purpose outputs, and 22 as general purpose inputs. GPIO pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of GPIO and GPO outputs controlled by that register simultaneously. The value of the output register for standard GPIOs and GPO pins may be read back, as well as the current actual state of the port pins. In addition to GPIO pins on port 0, port 1, and port 2, there are 22 GPI, 24 GPO, and six GPIO pins. When the SDRAM bus is configured for 16 data bits, 13 of the remaining SDRAM data pins may be used as GPIOs. 7.9.1.1 Features • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • A single register selects direction for pins that support both input and output modes. • Direction control of individual bits. • For input/output pins, both the programmed output state and the actual pin state can be read. • There are a total of 12 general purpose inputs, 24 general purpose outputs, and six general purpose input/outputs. • Additionally, 13 SDRAM data lines may be used as GPIOs if a 16-bit SDRAM interface is used (rather than a 32-bit interface). LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 41 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 7.9.2 Keyboard scanner The keyboard scanner function can automatically scan a keyboard of up to 64 keys in an 8  8 matrix. In operation, the keyboard scanner’s internal state machine will normally be in an idle state, with all KEY_ROWn pins set high, waiting for a change in the column inputs to indicate that one or more keys have been pressed. When a keypress is detected, the matrix is scanned by setting one output pin high at a time and reading the column inputs. After de-bouncing, the keypad state is stored and an interrupt is generated. The keypad is then continuously scanned waiting for ‘extra key pressed’ or ‘key released’. Any new keypad state is scanned and stored into the matrix registers followed by a new interrupt request to the interrupt controller. It is possible to detect and separate up to 64 multiple keys pressed. 7.9.2.1 Features • Supports up to 64 keys in 8  8 matrix. • Programmable de-bounce period. • A key press can wake up the CPU from Stop mode. 7.9.3 Touch screen controller and 10-bit ADC The LPC3220/30/40/50 microcontrollers includes Touch Screen Controller (TSC) hardware, which automatically measures and determines the X and Y coordinates where a touch screen is pressed. In addition, the TSC can measure an analog input signal on the AUX_IN pin. Optionally, the TSC can operate as an Analog-to-Digital Converter (ADC). The ADC supports three channels and uses 10-bit successive approximation to produce results with a resolution of 10 bits in 11 clock cycles. The analog portion of the ADC has its own power supply to enhance the low noise characteristics of the converter. This voltage is only supplied internally when the core has voltage. However, the ADC block is not affected by any difference in ramp-up time for VDD_AD and VDD_CORE voltage supplies. 7.9.3.1 Features • Measurement range of 0 V to VDD_AD (nominally 3.3 V). • Low-noise ADC. • 10-bit resolution. • Three input channels. • Uses 32 kHz RTC clock or peripheral clock. 7.9.4 Real-Time Clock (RTC) and battery RAM The RTC runs at 32768 Hz using a very low power oscillator. The RTC counts seconds and can generate alarm interrupts that can wake up the device from Stop mode. The RTC clock can also clock the 397x PLL, the Millisecond Timer, the ADC, the Keyboard Scanner and the PWMs. The RTC up-counter value represents a number of seconds elapsed since second 0, which is an application determined time. The RTC counter will reach maximum value after about 136 years. The RTC down-counter is initiated with all ones. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 42 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event and cause an external power supply to turn on all of the operating voltages, as a way to startup after power has been removed. The RTC block is implemented in a separate voltage domain. The block is supplied via a separate supply pin from a battery or other power source. The RTC block also contains 32 words (128 bytes) of very low voltage SRAM. This SRAM is able to hold its contents down to the minimum RTC operating voltage. 7.9.4.1 Features • Measures the passage of time in seconds. • 32-bit up and down seconds counters. • Ultra-low power design to support battery powered systems. • Dedicated 32 kHz oscillator. • An output pin is included to assist in waking up when the chip has had power removed to all functions except the RTC. • Two 32-bit match registers with interrupt option. • 32 words (128 bytes) of very low voltage SRAM. • The RTC and battery RAM power have an independent power domain and dedicated supply pins, which can be powered from a battery or power supply. Remark: The LPC3220/30/40/50 will run at voltages down to 0.9 V at frequencies below 14 MHz. However, the ARM core cannot access the RTC registers and battery RAM when the core supply voltage is at 0.9 V and the RTC supply is at 1.2 V. 7.9.5 Enhanced 32-bit timers/external event counters The LPC3220/30/40/50 includes six 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.9.5.1 Features • A 32-bit Timer/Counter with a programmable 32-bit pre-scaler. • Counter or Timer operation. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – continuous operation with optional interrupt generation on match – stop timer on match with optional interrupt generation – reset timer on match with optional interrupt generation • Up to four external outputs corresponding to match registers, with the following capabilities: LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 43 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers – set LOW on match – set HIGH on match – toggle on match – do nothing on match 7.9.6 High-speed timer The high-speed timer block is clocked by the main peripheral clock. The clock is first divided down in a 16-bit programmable pre-scale counter which clocks a 32-bit timer/counter. The high-speed timer includes three match registers that are compared to the timer/counter value. A match can generate an interrupt and cause the timer/counter to either continue to run, stop, or be reset. The high-speed timer also includes two capture registers that can take a snapshot of the timer/counter value when an input signal transitions. A capture event may also generate an interrupt. 7.9.6.1 Features • 32-bit timer/counter with programmable 16-bit pre-scaler. • Counter or timer operation. • Two 32-bit capture registers. • Three 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Pause control to stop counting when core is in debug state. 7.9.7 Pulse Width Modulators (PWMs) The LPC3220/30/40/50 provides two simple PWMs. They are clocked separately by either the main peripheral clock or the 32 kHz RTC clock. Both PWMs have a duty cycle programmable in 255 steps. 7.9.7.1 Features • Clocked by the main peripheral clock or the 32 kHz RTC clock. • Programmable 4-bit pre-scaler. • Duty cycle programmable in 255 steps. • Output frequency up to 50 kHz when using a 13 MHz peripheral clock. 7.9.8 Motor control pulse width modulator The Motor Control PWM (MCPWM) provides a set of features for three-phase AC and DC motor control applications in a single peripheral. The MCPWM can also be configured for use in other generalized timing, counting, capture, and compare applications. 7.9.8.1 Features • 32-bit timer • 32-bit period register LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 44 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers • 32-bit pulse-width (match) register • 10-bit dead-time register and an associated 10-bit dead-time counter • 32-bit capture register • Two PWM (match) outputs (pins MCOA0/1/2 and MCOB0/1/2) with opposite polarities • Period interrupt, pulse-width interrupt, and capture interrupt 8. Basic architecture The LPC3220/30/40/50 is a general purpose ARM926EJ-S 32-bit microprocessor with a 32 kB instruction cache and a 32 kB data cache. The microcontroller offers high performance and very low power consumption. The ARM architecture is based on RISC principles, which results in the instruction set and related decode mechanism being much simpler than equivalent micro programmed CISCs. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. The ARM926EJ-S core employs a 5-stage pipeline so processing and memory system accesses can occur continuously. At any one point in time, several operations are in progress: subsequent instruction fetch, next instruction decode, instruction execution, memory access, and write-back. The combination of architectural enhancements gives the ARM9 about 30 % better performance than an ARM7 running at the same clock rate: • Approximately 1.3 clocks per instruction for the ARM926EJ-S compared to 1.9 clocks per instruction for ARM7TDMI. • Approximately 1.1 Dhrystone MIPS/MHz for the ARM926EJ-S compared to 0.9 Dhrystone MIPS/MHz for ARM7TDMI. The ARM926EJ-S processor also employs an operational state known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb state is the use of a super-reduced instruction set. Essentially, the ARM926EJ-S processor core has two instruction sets: 1. The standard 32-bit ARM set 2. The 16-bit Thumb set The Thumb set’s smaller 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining many of ARM’s 32-bit performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates using the same 32-bit register set as ARM code. Thumb code size is up to 65 % smaller than ARM code size, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. Additionally, the ARM926EJ-S core includes enhanced DSP instructions and multiplier, as well as an enhanced 32-bit MAC block. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 45 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 9. Limiting values [1] The following applies to Table 7: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Core, PLL, oscillator, and RTC supplies; applies to pins VDD_CORE, VDD_COREFXD, VDD_OSC, VDD_PLL397, VDD_PLLHCLK, VDD_PLLUSB, VDD_RTC, VDD_RTCCORE, and VDD_RTCOSC. [3] I/O pad supply; applies to domains VDD_EMC. [4] Applies to VDD_AD pins. [5] Applies to pins in the following domains VDD_IOA, VDD_IOB, VDD_IOC, and VDD_IOD. [6] Including voltage on outputs in 3-state mode. [7] Based on package heat transfer, not device power consumption. Calculated package thermal resistance (ThetaJA): 35.766 C/W (with JEDEC Test Board and 0 m/s airflow, 15 % accuracy). [8] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [9] Charge device model per AEC-Q100-011. Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Notes Min Max Unit VDD(1V2) supply voltage (1.2 V) [2] 0.5 +1.4 V VDD(EMC) external memory controller supply voltage [3] 0.5 +4.6 V VDDA(3V3) analog supply voltage (3.3 V) [4] 0.5 +4.6 V VDD(IO) input/output supply voltage [5] 0.5 +4.6 V VIA analog input voltage 0.5 +4.6 V VI input voltage 1.8 V pins [6] 0.5 +2.4 V 3.3 V pins [6] 0.5 +4.6 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Tstg storage temperature 65 +150 C Ptot(pack) total power dissipation (per package) max. junction temp 125 C max. ambient temp 85 C [7]- 1.12 W VESD electrostatic discharge voltage HBM [8] - 2500 V CDM [9] - 1000 V LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 46 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(1V2) supply voltage (1.2 V) core supply voltage for full performance; 266 MHz (see Figure 4); VDD_CORE supply domain [2] 1.31 1.35 1.39 V core supply voltage for normal performance; 208 MHz (see Figure 4); VDD_CORE supply domain [2] 1.1 1.2 1.39 V core supply voltage for reduced power; up to 14 MHz CPU; VDD_CORE supply domain [2] 0.9 - 1.39 V RTC supply voltage; VDD_RTC supply domain [3] 0.9 - 1.39 V PLL and oscillator supply voltage [4] 1.1 1.2 1.39 V VDD(EMC) external memory controller supply voltage in 1.8 V range [5] 1.7 1.8 1.95 V in 2.5 V range [6] 2.3 2.5 2.7 V in 3.3 V range [7] 2.7 3.3 3.6 V VDD(IO) input/output supply voltage VDD_IOA, VDD_IOB, and VDD_IOD supply domain in 1.8 V range 1.7 1.8 1.95 V in 3.3 V range 2.7 3.3 3.6 V VDD_IOC supply domain in 1.8 V range 1.7 1.8 1.95 V in 3.3 V range 2.3 3.3 3.6 V VDDA(3V3) analog supply voltage (3.3 V) applies to pins in VDD_AD power domain 2.7 3.3 3.6 V LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 47 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Power consumption in Run, direct Run, and Stop modes IDD(run) Run mode supply current Tamb = 25 C; code while(1){} executed from IRAM; all peripherals enabled I-cache/D-cache, MMU enabled; CPU clock = 208 MHz; VDD_CORE = 1.2 V - 150 - mA I-cache/D-cache, MMU enabled; CPU clock = 266 MHz; VDD_CORE = 1.35 V - 218 - mA I-cache/D-cache, MMU disabled; CPU clock = 208 MHz; VDD_CORE = 1.2 V - 78 - mA I-cache/D-cache, MMU disabled; CPU clock = 266 MHz; VDD_CORE = 1.35 V - 111 - mA IDD(drun) direct Run mode supply current Tamb = 25 C; CPU clock = 13 MHz; code while(1){} executed from IRAM; all peripherals disabled I-cache/D-cache, MMU enabled; VDD_CORE = 1.2 V - 7.8 - mA I-cache/D-cache, MMU enabled; VDD_CORE = 0.9 V - 5.6 - mA I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V - 5 - mA I-cache/D-cache, MMU disabled; VDD_CORE = 0.9 V - 3.5 - mA IDD(stop) Stop mode supply current Tamb = 25 C; CPU clock stopped internally; all peripherals disabled VDD_CORE = 1.2 V - 400 - A VDD_CORE = 0.9 V - 400 - A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 48 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers IDD(RTC) RTC supply current normal operation; VDD_RTC = VDD_RTCCORE = VDD_RTCOSC = 1.2 V; Tamb = 25 C [8]- 13 - A RTC back up operation; Rev “-” silicon [9]- 30 - A Rev “A” silicon [9]- 4 - IDD supply current for HCLK; PLL output frequency = 266 MHz; VDD_PLLHCLK = 1.2 V - 2 - mA for USB; VDD_PLLUSB = 1.2 V - 2 - mA for ADC; interrupt driven loop converting ADIN[2:0]; VDD_AD = 3.3 V -  1 - mA Input pins and I/O pins configured as input VI input voltage [10][12]0 - VDD(IO) V VIH HIGH-level input voltage 1.8 V inputs 0.7  VDD(IO) - - V 3.3 V inputs 0.7  VDD(IO) - - V VIL LOW-level input voltage 1.8 V inputs - - 0.3  VDD(IO) V 3.3 V inputs - - 0.3  VDD(IO) V Vhys hysteresis voltage 1.8 V inputs 0.1  VDD(IO) - - V 3.3 V inputs 0.1  VDD(IO) - - V IIL LOW-level input current VI = 0 V; no pull-up - - 1 A IIH HIGH-level input current VI = VDD(IO); no pull-down [10]- - 1 A Ilatch I/O latch-up current (1.5VDD(IO)) < VI < (1.5VDD(IO)) [10]- - 100 mA Ipu pull-up current 1.8 V inputs with pull-up; VI = 0 V 6 12 22 A 3.3 V inputs with pull-up; VI = 0 V 25 50 80 A Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(IO) 5 12 22 A 3.3 V inputs with pull-down; VI = VDD(IO) 25 50 85 A II input current bus keeper inputs; VI = VDD - - 1 A VI = 0.67  VDD - - 55 A VI = 0.33  VDD - - 60 A VI = 0 V - - 1 A Ci input capacitance Excluding bonding pad capacitance - - 3.3 pF Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 49 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Output pins and I/O pins configured as output VO output voltage [10][11] [12][13] 0 - VDD(IO) V VOH HIGH-level output voltage 1.8 V outputs; IOH = 1 mA [14] VDD(IO)  0.4 - - V 3.3 V outputs; IOH = 4 mA [14] VDD(IO)  0.4 - - V VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14]- - 0.4 V 3.3 V outputs; IOL = 4 mA [14]- - 0.4 V IOH HIGH-level output current VDD(IO) = 1.8 V; VOH = VDD(IO)  0.4 V [10][14] 3.3 - - mA VDD(IO) = 3.3 V; VOH = VDD(IO)  0.4 V 6.5 - - mA IOL LOW-level output current VDD(IO) = 1.8 V; VOL = 0.4 V [10][14] 1.5 - - mA VDD(IO) = 3.3 V; VOL = 0.4 V 3 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(IO); no pull-up/down [10]- - 1 A IOHS HIGH-level short-circuit output current VDD(IO) = 1.8 V; VOH = 0 V [15]- - 66 mA VDD(IO) = 3.3 V; VOH = 0 V - - 183 mA IOLS LOW-level short-circuit output current VDD(IO) = 1.8 V; VOL = VDD(IO) [10][15]- - 34 mA VDD(IO) = 3.3 V; VOL = VDD(IO) - - 105 mA Zo output impedance VDD(IO) = 1.8 V 40 - 60  VDD(IO) = 3.3 V 40 - 60  EMC pins VI input voltage [12]0 - VDD(EMC) V VIH HIGH-level input voltage 1.8 V inputs 0.7  VDD(EMC) - - V 3.3 V inputs 0.7  VDD(EMC) - - V VIL LOW-level input voltage 1.8 V inputs - - 0.3  VDD(EMC) V 3.3 V inputs - - 0.3  VDD(EMC) V Vhys hysteresis voltage 1.8 V inputs 0.4 - 0.6 V 3.3 V inputs 0.55 - 0.85 V IIL LOW-level input current VI = 0 V; no pull-up - - 0.3 A IIH HIGH-level input current VI = VDD(EMC); no pull-down - - 0.3 A Ilatch I/O latch-up current (1.5VDD(EMC)) < VI < (1.5VDD(EMC)) - - 100 mA Ipu pull-up current 1.8 V inputs with pull-up; VI = 0 34 62 107 A 3.3 V inputs with pull-up; VI = 0 97 169 271 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 50 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Ipd pull-down current 1.8 V inputs with pull-down; VI = VDD(EMC) 23 51 93 A 3.3 V inputs with pull-down; VI = VDD(EMC) 73 155 266 A Ci input capacitance Excluding bonding pad capacitance - - 2.1 pF VO output voltage [11] [12][13] 0 - VDD(EMC) V VOH HIGH-level output voltage 1.8 V outputs; IOH = 1 mA [14] VDD(EMC)  0.3 - - V 3.3 V outputs; IOH = 4 mA [14] VDD(EMC)  0.3 - - V VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14]- - 0.3 V 3.3 V outputs; IOL = 4 mA [14]- - 0.3 V IOH HIGH-level output current VDD(EMC) = 1.8 V; VOH = VDD(EMC)  0.4 V [14] 6 - - mA VDD(EMC) = 3.3 V; VOH = VDD(EMC)  0.4 V 6 - - mA IOL LOW-level output current VDD(EMC) = 1.8 V; VOL = 0.4 V [14]6 - - mA VDD(EMC) = 3.3 V; VOL = 0.4 V 6 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(EMC); no pull-up/down - - 0.3 A IOHS HIGH-level short-circuit output current VDD(EMC) = 1.8 V; VOH = 0 V [15]- - 49 mA VDD(EMC) = 3.3 V; VOH = 0 V - - 81 mA IOLS LOW-level short-circuit output current VDD(EMC) = 1.8 V; VOL = VDD(EMC) [14]- - 49 mA VDD(EMC) = 3.3 V; VOL = VDD(EMC) - - 86 mA Zo output impedance VDD(EMC) = 1.8 V 35 40 58  VDD(EMC) = 3.3 V 32 35 45  I2C pins VI input voltage [10] [12] 0 - 5.5 V VIH HIGH-level input voltage 1.8 V inputs 0.7  VDD(IO) - - V 3.3 V inputs 0.7  VDD(IO) - - V VIL LOW-level input voltage 1.8 V inputs - - 0.3  VDD(IO) V 3.3 V inputs - - 0.3  VDD(IO) V IIL LOW-level input current VI = 0 V; no pull-up - - 10 A IIH HIGH-level input current VI = VDD(IO); no pull-down [10]- - 10 A Ilatch I/O latch-up current (1.5VDD(IO)) < VI < (1.5VDD(IO)) [10]- - 100 mA Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 51 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Ci input capacitance Excluding bonding pad capacitance - - 1.6 pF VOL LOW-level output voltage 1.8 V outputs; IOL = 4 mA [14]- - 0.4 V 3.3 V outputs; IOL = 4 mA [14]- - 0.4 V IOL LOW-level output current VDD(IO) = 1.8 V; VOL = 0.4 V [10][14]3 - - mA VDD(IO) = 3.3 V; VOL = 0.4 V 3 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(IO); no pull-up/down [10]- - 10 A IOLS LOW-level short-circuit output current VDD(IO) = 1.8 V; VOL = VDD(IO) [10][15]- - 40 mA VDD(IO) = 3.3 V; VOL = VDD(IO) - - 40 mA ONSW pin VO output voltage [10][11] [12][13] 0 - VDD(1V2) V VOH HIGH-level output voltage 1.2 V outputs; IOH = 1 mA [14] VDD(1V2)  0.4 - - V VOL LOW-level output voltage 1.2 V outputs; IOL = 4 mA [14]- - 0.4 V IOH HIGH-level output current VOH = VDD(1V2)  0.4 V [10][14] 4 - - mA IOL LOW-level output current VOL = 0.4 V [10][14]3 - - mA IOZ OFF-state output current VO = 0 V; VO = VDD(1V2); no pull-up/down [10]- - 1.5 A IOHS HIGH-level short-circuit output current VDD(1V2) = 1.8 V; VOH = 0 V [15]- - 135 mA IOLS LOW-level short-circuit output current VOL = VDD(1V2) [10][15]- - 135 mA Zo output impedance VDD(1V2) = 1.2 V 40 - 60  Oscillator input/output pins Vi(xtal) crystal input voltage on pins RTCX_IN and SYSX_IN 0.5 - +1.3 V Vo(xtal) crystal output voltage on pins RTCX_OUT and SYSX_OUT 0.5 - +1.3 V RESET pin VI input voltage [10] [12] 0 - 1.95 V VIH HIGH-level input voltage 1.2 V inputs 0.7  VDD(1V2) - - V VIL LOW-level input voltage 1.2 V inputs - - 0.3  VDD(1V2) V IIL LOW-level input current VI = 0 V; no pull-up - - 1 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 52 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Applies to VDD_CORE pins. [3] Applies to pins VDD_RTC, VDD_RTCCORE, and VDD_RTCOSC. [4] Applies to pins VDD_COREFXD, VDD_OSC, VDD_PLL397, VDD_PLLHCLK, and VDD_PLLUSB. [5] Applies when using 1.8 V Mobile DDR or Mobile SDR SDRAM. [6] Applies when using 2.5 V DDR memory. [7] Applies when using 3.3 V SDR SDRAM and SRAM. [8] Specifies current on combined VDD_RTCx during normal chip operation: VDD_RTC, VDD_CORE, VDD_OSC = 1.2 V and VDD_CORE, VDD_IOx at typical voltage. [9] Specifies current on combined VDD_RTCx during backup operation: VDD_RTC, VDD_CORE, VDD_OSC = 1.2 V and all other VDD_x at 0 V. [10] Referenced to the applicable VDD for the pin. [11] Including voltage on outputs in 3-state mode. [12] The applicable VDD voltage for the pin must be present. [13] 3-state outputs go into 3-state mode when the applicable VDD voltage for the pin is grounded. [14] Accounts for 100 mV voltage drop in all supply lines. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. IIH HIGH-level input current VI = VDD; no pull-down [10]- - 1 A IOZ OFF-state output current VO = 0 V; VO = VDD; no pull-up/down [10]- - 1 A Ilatch I/O latch-up current (1.5VDD) < VI < (1.5VDD) [10]- - 100 mA Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 53 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.1 Minimum core voltage requirements Figure 4 shows the minimum core supply voltage that should be applied for a given core frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50. 10.2 Power supply sequencing The LPC32x0 has no power sequencing requirements, that is, VDD(1V2), VDD(EMC), VDD(IO), and VDDA(3V3) can be switched on or off independent of each other. An internal circuit ensures that the system correctly powers up in the absence of core power. During IO power-up this circuit takes care that the system is powered in a defined mode. The same is valid for core power-down. 10.3 Power consumption per peripheral [1] All three Ethernet clocks are in enabled in the MAC_CLK_CTRL register (see LPC32x0 User manual). Fig 4. Minimum required core supply voltage for different core frequencies core frequency (MHz) 160 200 240 280 002aae872 1.0 1.2 1.4 0.8 VDD_CORE (V) Table 9. Power consumption per peripheral Tamb = 25 C; CPU clock = 208 MHz; I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V; VDD(IO) = 1.8 V; USB AHB, IRAM, and IROM clocks always on; all peripherals are at their default state at reset. Peripheral clocks are disabled except for peripheral measured. Peripheral IDD(run) / mA High-speed UART (set to 115 200 Bd (8N1)) 0.3 I2C-bus 0.3 SSP 0.6 I2S 0.5 DMA 6.3 EMC 7.3 Multi-level NAND controller 1.4 Single-level NAND controller 0.3 LCD 5.6 Ethernet MAC[1] 2.9 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 54 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.4 Power consumption in Run mode Power consumption is shown in Figure 5 for WinCE applications running under typical conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on but not used. I2S-interface (channel 1), LCD, SLC NAND controller, I2C1-bus, SD card, touchscreen ADC, and UART 3 are turned on. All other peripherals are turned off. The AHB clock HCLK is identical to the core clock for frequencies up to 133 MHz, which is the maximum allowed HCLK frequency. For higher core frequencies, the HCLK PLL output must be divided by 2 to obtain an HCLK frequency lower than or equal to 133 MHz resulting in correspondingly lower power consumption by the AHB peripherals. Conditions: Tamb = 25 C; VDD_CORE = 1.2 V for core frequencies  208 MHz; VDD_CORE = 1.35 V for core frequencies > 208 MHz; VDD(IO) = 1.8 V. (1) WinCE running from SDRAM; playing wmv file at 20 frames/s, 32 kHz mono. (2) WinCE running from SDRAM; playing mp3 file at 128 kbit/s, stereo. (3) WinCE running from SDRAM; no application running. Fig 5. Core current versus core frequency for WinCE applications core frequency (MHz) 40 120 200 280 002aae762 80 40 120 160 IDD(run) (mA) 0 (1) (2) (3) HCLK = 133 MHz HCLK = 72 MHz VDD_CORE = 1.2 V VDD_CORE = 1.35 V LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 55 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 10.5 ADC static characteristics [1] Conditions: VSSA = 0 V (on pin VSS_AD); VDDA(3V3) = 3.3 V (on pin VDD_AD). [2] The ADC is monotonic; there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 6. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 6. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 6. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 6. [7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 6. Table 10. ADC static characteristics VDDA(3V3) = 3.3 V; Tamb = 25C unless otherwise specified; ADC clock frequency 4.5 MHz. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA(3V3) V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2][3] - 0.5 1 LSB EL(adj) integral non-linearity [1][4] - 0.6 1 LSB EO offset error [1][5] - 1 3 LSB EG gain error [1][6] - 0.3 0.6 % ET absolute error [1][7] - 4 LSB Rvsi voltage source interface resistance - - 40 k LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 56 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 6. ADC characteristics 002aae434 1023 1022 1021 1020 1019 (2) (1) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 LSB (ideal) code out VDDA(3V3) − VSSA 1024 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 57 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11. Dynamic characteristics 11.1 Clocking and I/O port pins [1] Parameters are valid over operating temperature range unless otherwise specified. [2] After supply voltages are stable [3] Supplied by an external crystal. 11.2 Static memory controller Table 11. Dynamic characteristics Tamb = 40 C to +85 C, unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Reset tw(RESET)ext external RESET pulse width [2] 10 - - ms External clock fext external clock frequency [3]1 13 20 MHz Port pins tr rise time - 5 - ns tf fall time - 5 - ns Table 12. Dynamic characteristics: static external memory interface CL = 25 pF, Tamb = 20C, VDD(EMC) = 1.8 V, 2.5 V, or 3.3 V. Symbol Parameter Notes Min Typ Max Unit Common to read and write cycles TCLCL clock cycle time [1] 7.5 9.6 - ns tCSLAV CS LOW to address valid time - 0 - ns Read cycle parameters tOELAV OE LOW to address valid time [2]- 0 WAITOEN  TCLCL - ns tBLSLAV BLS LOW to address valid time [2]- 0 WAITOEN  TCLCL - ns tCSLOEL CS LOW to OE LOW time - 0 + WAITOEN  TCLCL - ns tCSLBLSL CS LOW to BLS LOW time [2] - 0 + WAITOEN  TCLCL - ns tOELOEH OE LOW to OE HIGH time [2][3]- (WAITRD WAITOEN + 1)  TCLCL - ns tBLSLBLSH BLS LOW to BLS HIGH time [2][3]- (WAITRD WAITOEN + 1)  TCLCL - ns tsu(DQ) data input/output set-up time [6]- 8.4 - ns th(DQ) data input/output hold time [6]- 0 - ns tCSHOEH CS HIGH to OE HIGH time - 0 - ns tCSHBLSH CS HIGH to BLS HIGH time - 0 - ns tOEHANV OE HIGH to address invalid time - 1  TCLCL - ns tBLSHANV BLS HIGH to address invalid time - 1  TCLCL - ns Write cycle parameters tCSLDV CS LOW to data valid time - 0 - ns tCSLWEL CS LOW to WE LOW time [4]- (WAITWEN+1) TCLCL - ns tCSLBLSL CS LOW to BLS LOW time [4]- (WAITWEN+ 1)  TCLCL - ns tWELDV WE LOW to data valid time [4]- 0 (WAITWEN + 1)  TCLCL - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 58 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] TCLCL = 1/HCLK [2] Refer to the LPC32x0 User manual EMCStaticWaitOen0-3 register for the programming of WAITOEN value. [3] Refer to the LPC32x0 User manual EMCStaticWaitRd0-3 register for the programming of WAITRD value. [4] Refer to the LPC32x0 User manual EMCStaticWaitWen0-3 register for the programming of WAITWEN value. [5] Refer to the LPC32x0 User manual EMCStaticWaitWr0-3 register for the programming of WAITWR value. [6] Earliest of CS HIGH, OE HIGH, address change to data invalid. tWELWEH WE LOW to WE HIGH time [4][5]- (WAITWR WAITWEN + 1)  TCLCL - ns tBLSLBLSH BLS LOW to BLS HIGH time [4][5]- (WAITWR WAITWEN + 1)  TCLCL - ns tWEHANV WE HIGH to address invalid time - 1  TCLCL - ns tWEHDNV WE HIGH to data invalid time - 1  TCLCL - ns tBLSHANV BLS HIGH to address invalid time - 1  TCLCL - ns tBLSHDNV BLS HIGH to data invalid time - 1  TCLCL - ns Table 12. Dynamic characteristics: static external memory interface …continued CL = 25 pF, Tamb = 20C, VDD(EMC) = 1.8 V, 2.5 V, or 3.3 V. Symbol Parameter Notes Min Typ Max Unit Fig 7. External memory read access EMC_CS[3:0] EMC_A[23:0] EMC_D[31:0] EMC_OE EMC_BLS[3:0] tCSLAV tOELAV tOELOEH tCSLOEL tsu(DQ) th(DQ) tCSHOEH tOEHANV 002aae402 tBLSLAV tCSHBLSH tBLSLBLSH tCSLBLSL tBLSHANV LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 59 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 8. External memory write access EMC_A[23:0] EMC_D[31:0] tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tWEHANV tBLSHANV tWEHDNV tBLSHDNV 002aae469 tCSLAV EMC_CS[3:0] tBLSLBLSH EMC_BLS[3:0] EMC_WR LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 60 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.3 SDR SDRAM Controller [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V, VDD_CORE = 1.2 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual). [3] All min or max values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V, VDD_CORE = 1.2 V. [4] foper = 1/tCK. [5] Applies to signals: EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0]. [6] CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in LPC32x0 User manual. Table 13. EMC SDR SDRAM memory interface dynamic characteristics CL = 25 pF, Tamb = 40 C to +85 C, unless otherwise specified.[1][3] Symbol Parameter Min Typical[2] Max Unit foper operating frequency [4] 104 133 MHz tCK clock cycle time 7.5 9.6 - ns tCL CK LOW-level width - 4.8 - ns tCH CK HIGH-level width - 4.8 - ns td(V)ctrl control valid delay time [5][6] - (CMD_DLY  0.25) + 2.7 ns th(ctrl) control hold time [5][6] (CMD_DLY  0.25) + 1.2 - ns td(AV) address valid delay time [6] - (CMD_DLY  0.25) + 3.2 ns th(A) address hold time [6] (CMD_DLY  0.25) + 1.2 - ns td(QV) data output valid delay time [6] - (CMD_DLY  0.25) + 3.5 ns th(Q) data output hold time [6] (CMD_DLY  0.25) + 1.2 - ns tsu(D) data input set-up time - 0.6 - ns th(D) data input hold time - 0.9 - ns tQZ data output high-impedance time - -  tCK ns Fig 9. SDR SDRAM signal timing 002aae420 EMC_CLK output signal (O) input signal (I) td(V)ctrl, td(AV), td(QV) th(ctrl), th(Q), th(A) tsu(D) th(D) tCK tCH tCL tQZ LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 61 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.4 DDR SDRAM controller [1] All values valid for EMC pads set to fast slew rate at 1.8 V unless otherwise specified (see SDRAMCLK_CTRL register in the LPC32x0 User manual). [2] CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External Memory Controller (EMC) chapter in LPC32x0 User manual. [3] Applies to signals EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0]. [4] DQS_DELAY, see LPC32x0 User manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on configuring this value. [5] Test conditions for measurements: Tamb = 40 C to +85 C; operating frequency range foper = 52 MHz to 133 MHz; EMC_DQM[3:0] and EMC_D[31:0] driving 2 inches of 50  characteristic impedance trace with 10 pF capacitive load; no external source series termination resistors used. EMC pads set to fast slew rate at 1.8 V or 2.5 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual). Table 14. EMC DDR SDRAM memory interface dynamic characteristics[1] CL = 25 pF, Tamb = 25C, unless otherwise specified. Symbol Parameter Conditions Min Typical Max Unit foper operating frequency - 104 133 MHz tCK clock cycle time 7.5 9.6 - ns tCL CK LOW-level width - 0.5  tCK - ns tCH CK HIGH-level width - 0.5  tCK - ns td(V)ctrl control valid delay time [2][3] - (CMD_DLY  0.25) + 1.5 - ns th(ctrl) control hold time [2][3] - (CMD_DLY  0.25)  1.5 - ns td(AV) address valid delay time [2] - (CMD_DLY  0.25) + 1.5 - ns th(A) address hold time [2] - (CMD_DLY  0.25)  1.5 - ns tsu(Q) data output set-up time EMC_D[31:0] and EMC_DQM[3:0] to EMC_DQS[1:0] out [5] 0.08  tCK 0.15  tCK 0.25  tCK ns th(Q) data output hold time EMC_D[31:0] and EMC_DQM[3:0] to EMC_DQS[1:0] out [5] 0.25  tCK 0.35  tCK 0.42  tCK ns tDQSH DQS HIGH time for WRITE command - 0.5  tCK - ns tDQSL DQS LOW time for WRITE command - 0.5  tCK - ns tDQSS WRITE command to first DQS latching transition time for DQS out - tCK + 0.7 - ns tDSS DQS falling edge to CK set-up time for DQS in - 0.5  tCK - ns tDSH DQS falling edge hold time from CK for DQS in - 0.5  tCK - ns td(DQS) DQS delay time for DQS in [4] - DQS_DELAY - ns tsu(D) data input set-up time - 0.3 - ns th(D) data input hold time - 0.5 - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 62 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 10. DDR control timing parameters EMC_CLK EMC control and address signals 002aae436 tCK tCH tCL td(AV); td(V)ctrl th(A); th(ctl) valid Fig 11. DDR write timing parameters command EMC_D[31:0], EMC_DQM[3:0] tDQSS tDQSL tDQSH th(Q) EMC_DQS[1:0] EMC_CLK 002aae437 WRITE tsu(Q) tDSS tDSH (1) The delay of the EMC_DQS[1:0] signal is determined by the DQS_DELAY settings. See LPC32x0 User manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value. Fig 12. DDR read timing parameters EMC_CLK command EMC_D[31:0] tsu(D) EMC_DQS[1:0] 002aae438 th(D) READ delayed EMC_DQS[1:0](1) td(DQS) LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 63 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.5 USB controller [1] Parameters are valid over operating temperature range unless otherwise specified. 11.6 Secure Digital (SD) card interface [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 15. Dynamic characteristics USB digital I/O pins VDD(IO) = 3.3 V; Tamb = 40 C to +85 C, unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit tTIO bus turnaround time (I/O) OE_N/INT_N to DAT/VP and SE0/VM - 7 - ns tTOI bus turnaround time (O/I) OE_N/INT_N to DAT/VP and SE0/VM - 0 - ns Fig 13. USB bus turnaround time 002aae440 USB_DAT_VP tTIO tTOI USB_OE_TP USB_SE0_VM input output input Table 16. Dynamic characteristics: SD card pin interface Tamb = 40 C to +85 C for industrial applications; VDD(IO) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit Tcy(clk) clock cycle time on pin MS_SCLK; Data transfer mode - - 25 MHz on pin MS_SCLK; Identification mode - - 400 kHz tsu(D) data input set-up time on pins MS_BS, MS_DIO[3:0] as inputs - 2.7 - ns th(D) data input hold time on pins MS_BS, MS_DIO[3:0] as inputs - 0 - ns td(QV) data output valid delay time on pins MS_BS, MS_DIO[3:0] as outputs - 9.7 - ns th(Q) data output hold time on pins MS_BS, MS_DIO[3:0] as outputs - 7.7 - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 64 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.7 MLC NAND flash memory controller [1] THCLK = 1/HCLK [2] CEAD = bitfield TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24] [3] WL = bitfield WR_LOW[3:0] in register MLC_TIME_REG[3:0] [4] WH = bitfield WR_HIGH[3:0] in register MLC_TIME_REG[7:4] [5] RL = bitfield RD_LOW[3:0] in register MLC_TIME_REG[11:8] [6] RH = bitfield RD_HIGH [3:0] in register MLC_TIME_REG[15:12] [7] RHZ = bitfield NAND_TA[2:0] in register MLC_TIME_REG[18:16] [8] BD = bitfield BUSY_DELAY[4:0] in register MLC_TIME_REG[23:19] Fig 14. SD card pin interface timing 002aae441 MS_SCLK MS_DIO[3:0](O) MS_DIO[3:0] (I) td(QV) tsu(D) th(D) Tcy(clk) th(Q) MS_BS (O) MS_BS (I) Table 17. Dynamic characteristics of the MLC NAND flash memory controller Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit tCELREL CE LOW to RE LOW time [1][2] - THCLK  CEAD - ns tRC RE cycle time [1][5][6] - THCLK  (RL + 1) + THCLK  (RH  RL) - ns tREH RE HIGH hold time [1][5][6] - THCLK  (RH  RL) - ns tRHZ RE HIGH to output high-impedance time [1][5][7] - THCLK  (RH  RL) + THCLK  RHZ - ns tRP RE pulse width [1][5] - THCLK  (RL + 1) - ns tREHRBL RE HIGH to R/B LOW time [1][8] - THCLK  BD - ns tWB WE HIGH to R/B LOW time [1][8] - THCLK  BD - ns tWC WE cycle time [1][3][4] - THCLK  (WL + 1) + THCLK  (WH  WL) - ns tWH WE HIGH hold time [1][3][4] - THCLK  (WH  WL) - ns tWP WE pulse width [1][3] - THCLK  (WL + 1) - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 65 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.8 SLC NAND flash memory controller Fig 15. MLC NAND flash controller write timing (writing to NAND flash) Fig 16. MLC NAND flash controller read timing (reading from NAND flash) tWB FLASH_IO[7:0] FLASH_WR tWP tWC FLASH_RDY (R/B) FLASH_CE D0 D1 Dn 10h tWH 002aae442 FLASH_IO[7:0] tRP tREH tRC FLASH_RD FLASH_CE tCELREL D0 D1 D2 D3 tRHZ 002aae443 Table 18. Dynamic characteristics of SLC NAND flash memory controller Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit tALS ALE set-up time read [1][2][4][6] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tALH ALE hold time read [1][7] - THCLK  Rh - ns write - THCLK  Wh - ns tAR ALE to RE delay time read [1][2][6] - THCLK  Rsu - ns write - THCLK  Wsu - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 66 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers tCEA CE access time read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tCS CE set-up time read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tCH CE hold time read [1][3] - THCLK  Rh - ns write - THCLK  Wh - ns tCLS CLE set-up time read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns write - THCLK  (Wsu + Ww) - ns tCLH CLE hold time read [1][3] - THCLK  Rh - ns write - THCLK  Wh - ns tCLR CLE to RE delay time read [1][2][6] - THCLK  Rsu - ns write - THCLK  Wsu - ns tDH data hold time output from NAND controller; read [1][3][7] - THCLK  Rh - ns output from NAND controller; write - THCLK  Wh - ns tDS data set-up time output from NAND controller; read [1][2][4][6][8] - THCLK  (Rsu + Rw) - ns output from NAND controller; write - THCLK  (Wsu + Ww) - tIR output high-impedance to RE LOW time read [1][2][6] - THCLK  Rsu - ns write - THCLK  Wsu - ns tRC RE cycle time read [1][2] - THCLK  (Rsu + Rw + Rh) - ns tREA RE access time read [1][4] - THCLK  Rw - ns tREH RE high hold time read [1][2][3] - THCLK  (Rsu + Rh) - ns tRHOH RE HIGH to output hold time input hold for flash controller; read - 0 - - input hold for flash controller; write - 0 - - tRHZ RE HIGH to output high-impedance time read [1] - THCLK  Rh - ns tRP RE pulse width read [1][4] - THCLK  Rw - ns tRR ready to RE LOW time read [1][2][3] - THCLK  Rsu - ns tWB WE HIGH to R/B LOW time write [1][7][9] - (THCLK  Wh) + (2  THCLK  Wb) - ns tWC WE cycle time write [1][6][7][8] - THCLK  (Wsu + Ww + Wh) - ns Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 67 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers [1] THCLK = 1/HCLK [2] Rsu = bitfield R_SETUP[3:0] in register SLC_TAC[3:0] for reads [3] Rh = bitfield R_HOLD[3:0] in register SLC_TAC[7:4] for reads [4] Rw = bitfield R_WIDTH[3:0] in register SLC_TAC[11:8] for reads [5] Rb = bitfield R_RDY[3:0] in register SLC_TAC[15:12] for reads [6] Wsu = bitfield W_SETUP[3:0] in register SLC_TAC[19:16] for writes [7] Wh = bitfield W_HOLD[3:0] in register SLC_TAC[23:20] for writes [8] Ww = bitfield W_WIDTH[3:0] in register SLC_TAC[27:24] for writes [9] Wb = bitfield W_RDY[3:0] in register SLC_TAC[31:28] for writes tWH WE HIGH hold time write [1][6][7] - THCLK  (Wsu + Wh) - ns tWHR WE HIGH to RE LOW time write [1][7][9] - (THCLK  Wh) + (2  THCLK  Wb) - ns tWP WE pulse width write [1][8] - THCLK  Ww - ns tREHRBL RE HIGH to R/B LOW time write [1][3][5] - (THCLK  Rh) + (2  THCLK  Rb) - ns Table 18. Dynamic characteristics of SLC NAND flash memory controller …continued Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit Fig 17. MLC NAND flash memory write timing (writing to NAND flash) command tDS tDH tWB FLASH_IO[7:0] address tDS tDH tALS tALH tDS tDH tWP tWH tWC tCS tCH tCH tCLS tCLH command address data D0 D1 Dn tALS tCLH tALS tALH tWP tWP tWH tCLS tCS 002aae444 FLASH_CE FLASH_CLE FLASH_WR FLASH_ALE FLASH_RDY LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 68 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 18. MLC NAND Flash memory read timing (reading from NAND flash) command tDS tDH tWB FLASH_IO[7:0] address tDS tDH tALS tALH tDS tDH tRP tREH tRC tRR tAR tCS tCH tCEA tCLR tCLS tCLH command address data tCOH tREA D0 D1 D2 D3 tRHZ tRHOH tALS tALH tCLS tCS tWP tWP tWH 002aae445 FLASH_ALE FLASH_CLE FLASH_RDY FLASH_WR FLASH_RD FLASH_CE LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 69 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.9 SPI and SSP Controller 11.9.1 SPI [1] THCLK = period time of SPI IP block input clock (HCLK) Fig 19. MLC NAND flash memory status timing tCS tCH tCEA 70 h tDS tDH status tRHOH tCLS tCLH command data tCLR tCOH tREA tIR FLASH_IO[7:0] tWHR tWP tRHZ FLASH_CLE FLASH_WR FLASH_CE FLASH_RD 002aae446 Table 19. Dynamic characteristics of SPI pins on SPI master controller Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit Common to SPI1 and SPI2 TSPICYC SPI cycle time [1] 2  THCLK - 256  THCLK ns SPI1 tSPIDSU SPI data set-up time - 6 - ns tSPIDH SPI data hold time - 0 - ns tSPIDV SPI enable to output data valid time - 2 - ns tSPIOH SPI output data hold time - 0 - ns SPI2 tSPIDSU SPI data set-up time - 10 - ns tSPIDH SPI data hold time - 0 - ns tSPIDV SPI enable to output data valid time - 2 - ns tSPIOH SPI output data hold time - 0 - ns LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 70 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) Fig 20. SPI master timing (CPHA = 0) Fig 21. SPI master timing (CPHA = 1) 002aae457 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID tSPIQV SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 002aae454 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 71 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Fig 22. SPI slave timing (CPHA = 0) Fig 23. SPI slave timing (CPHA = 1) 002aae458 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 002aae459 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH DATA VALID DATA VALID SPI1/2_CLK or SCK0/1 (CPOL = 0) SPI1/2_CLK or SCK0/1 (CPOL = 1) SPI1/2_DATAIO or MOSI0/1 SPI1/2_DATAIN or MISO0/1 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 72 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 12. Package outline Fig 24. Package outline SOT1048-1 (TFBGA296) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT1048-1 MO-216 SOT1048-1 07-10-19 07-11-02 UNIT A max mm 1.2 0.4 0.3 0.80 0.65 15.1 14.9 15.1 14.9 0.8 13.6 0.15 0.08 0.1 A1 DIMENSIONS (mm are the original dimensions) TFBGA296: plastic thin fine-pitch ball grid array package; 296 balls 0 5 10 mm scale A2 b 0.5 0.4 D E e e1 e2 13.6 v w y 0.12 y1 C y1 C y X A B C D E F H K G L J M N P R T U 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 18 17 b e2 e1 e e 1/2 e 1/2 e ∅ v M C A B ∅ w M C ball A1 index area V B A ball A1 index area D E detail X A A2 A1 LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 73 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 13. Abbreviations Table 20. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BSDL Boundary Scan Description Language CISC Complex Instruction Set Computer DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory DMA Direct Memory Access DSP Digital Signal Processing ETM Embedded Trace Macrocell FAB Fast Access Bus FIFO First In, First Out FIQ Fast Interrupt Request GPIO General Purpose Input/Output I/O Input/Output IRQ Interrupt Request HS High-Speed IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop PWM Pulse Width Modulator RAM Random Access Memory RMII Reduced Media Independent Interface SE0 Single Ended Zero SDR SDRAM Single Data Rate Synchronous Dynamic Random Access Memory SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TFT Thin Film Transistor TTL Transistor-Transistor Logic STN Super Twisted Nematic LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 74 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus VFP Vector Floating Point processor Table 20. Abbreviations …continued Acronym Description LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 75 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 14. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC3220_30_40_50 v.2 20111020 Product data sheet - LPC3220_30_40_50 v.1 Modifications: • Corrected pin functions for pin T14 (ADIN1/TS_XM) and pin U15 (ADIN0/TS_YM) in Table 3 and Table 4. • Power domain for pin PLL397_LOOP corrected in Table 4. • Power supply domain for pins SYSX_IN and SYSX_OUT pins corrected in Table 4. • Power supply domain for pin VDD_OSC corrected in Table 4. • Description of DEBUG pin updated in Table 4. • Added Table 6 “Supply domains”. • Changed VESD to 2500 V (HBM) and 1000 V (CDM) in Table 7. • Power consumption for HCLK, USB, and ADC added in Table 8. • Parameter IDD(RTC) updated in Table 8. • Parameter VDD(EMC) table notes updated in Table 8. • Input current for bus keeper inputs added in Table 8. • Added power consumption data (Table 8, Table 9, and Figure 5). • Static memory controller: added tsu(DQ) value in Table 12. • DDR SDRAM controller: updated tDQSS value in Table 14. • Minimum and maximum characterization data added for parameters tsu(Q) and th(Q) over temperature range 40 C to +85 C (see Table 14). • DDR SDRAM characteristics extended to maximum operating frequency foper = 133 MHz (see Table 14). • Parameters tWB, tWHR, and tREHRBL updated in Table 18. • Changed data sheet status to Product data sheet. • Parts LPC3220FET296/01, LPC3230FET296/01, LPC3240FET296/01, LPC3250FET296/01 added. LPC3220_30_40_50 v.1 20090206 Preliminary data sheet - - LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 76 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 15. Legal information 15.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 77 of 79 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC3220_30_40_50 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 20 October 2011 78 of 79 continued >> NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Functional description . . . . . . . . . . . . . . . . . . 24 7.1 CPU and subsystems . . . . . . . . . . . . . . . . . . . 24 7.1.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.2 Vector Floating Point (VFP) coprocessor . . . . 24 7.1.3 Emulation and debugging. . . . . . . . . . . . . . . . 24 7.1.3.1 Embedded ICE . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1.3.2 Embedded trace buffer . . . . . . . . . . . . . . . . . . 25 7.2 AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.1 APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2.2 FAB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 Physical memory map . . . . . . . . . . . . . . . . . . 26 7.4 Internal memory . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.1 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 External memory interfaces . . . . . . . . . . . . . . 28 7.5.1 NAND flash controllers . . . . . . . . . . . . . . . . . . 28 7.5.1.1 Multi-Level Cell (MLC) NAND flash controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5.1.2 Single-Level Cell (SLC) NAND flash controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5.2 SD card controller. . . . . . . . . . . . . . . . . . . . . . 29 7.5.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5.3 External memory controller. . . . . . . . . . . . . . . 29 7.6 AHB master peripherals . . . . . . . . . . . . . . . . . 30 7.6.1 General Purpose DMA (GPDMA) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6.2 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.6.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.3 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.6.3.1 USB device controller . . . . . . . . . . . . . . . . . . . 31 7.6.3.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 32 7.6.3.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 32 7.6.4 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.7 System functions . . . . . . . . . . . . . . . . . . . . . . 34 7.7.1 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 34 7.7.2 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.3 Millisecond timer . . . . . . . . . . . . . . . . . . . . . . 34 7.7.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.4 Clocking and power control features . . . . . . . 35 7.7.4.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.2 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.3 PLLs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7.4.4 Power control modes . . . . . . . . . . . . . . . . . . . 36 7.7.4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.8 Communication peripheral interfaces . . . . . . 36 7.8.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.8.1.1 Standard UARTs. . . . . . . . . . . . . . . . . . . . . . . 37 7.8.1.2 High-speed UARTs . . . . . . . . . . . . . . . . . . . . 37 7.8.2 SPI serial I/O controller . . . . . . . . . . . . . . . . . 37 7.8.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.3 SSP serial I/O controller. . . . . . . . . . . . . . . . . 38 7.8.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8.4 I2C-bus serial I/O controller . . . . . . . . . . . . . . 38 7.8.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.8.5 I2S-bus audio controller . . . . . . . . . . . . . . . . . 39 7.8.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.9 Other peripherals . . . . . . . . . . . . . . . . . . . . . . 40 7.9.1 General purpose parallel I/O . . . . . . . . . . . . . 40 7.9.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.9.2 Keyboard scanner . . . . . . . . . . . . . . . . . . . . . 41 7.9.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.3 Touch screen controller and 10-bit ADC . . . . 41 7.9.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.9.4 Real-Time Clock (RTC) and battery RAM . . . . . . . . . . . . . . . . . . . . . . 41 7.9.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.5 Enhanced 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.9.6 High-speed timer . . . . . . . . . . . . . . . . . . . . . . 43 7.9.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.7 Pulse Width Modulators (PWMs) . . . . . . . . . . 43 7.9.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9.8 Motor control pulse width modulator . . . . . . . 43 7.9.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 44 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Static characteristics . . . . . . . . . . . . . . . . . . . 46 10.1 Minimum core voltage requirements . . . . . . . 53 10.2 Power supply sequencing . . . . . . . . . . . . . . . 53 10.3 Power consumption per peripheral . . . . . . . . 53 10.4 Power consumption in Run mode . . . . . . . . . 54 10.5 ADC static characteristics . . . . . . . . . . . . . . . 55 NXP Semiconductors LPC3220/30/40/50 16/32-bit ARM microcontrollers © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 October 2011 Document identifier: LPC3220_30_40_50 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 57 11.1 Clocking and I/O port pins . . . . . . . . . . . . . . . 57 11.2 Static memory controller . . . . . . . . . . . . . . . . . 57 11.3 SDR SDRAM Controller . . . . . . . . . . . . . . . . . 60 11.4 DDR SDRAM controller . . . . . . . . . . . . . . . . . 61 11.5 USB controller . . . . . . . . . . . . . . . . . . . . . . . . 63 11.6 Secure Digital (SD) card interface . . . . . . . . . 63 11.7 MLC NAND flash memory controller. . . . . . . . 64 11.8 SLC NAND flash memory controller . . . . . . . . 65 11.9 SPI and SSP Controller . . . . . . . . . . . . . . . . . 69 11.9.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) . . . . . . . . . . . . . . . . . . . . . . . . . 70 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 72 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 73 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 75 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 76 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 76 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 77 16 Contact information. . . . . . . . . . . . . . . . . . . . . 77 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1. General description The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM. The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. 2. Features and benefits  System:  ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port.  ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  Serial Wire Debug (SWD) and JTAG boundary scan modes supported.  Micro Trace Buffer (MTB) supported.  Memory:  Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.  Up to 4 kB SRAM.  ROM API support:  Boot loader.  USART drivers.  I2C drivers.  Power profiles.  Flash In-Application Programming (IAP) and In-System Programming (ISP).  Digital peripherals:  High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and glitch filter.  High-current source output driver (20 mA) on four pins.  High-current sink driver (20 mA) on two true open-drain pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function. LPC81xM 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM Rev. 4.3 — 22 April 2014 Product data sheet LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 2 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller  State Configurable Timer/PWM (SCTimer/PWM) with input and output functions (including capture and match) assigned to pins through the switch matrix.  Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.  CRC engine.  Windowed Watchdog timer (WWDT).  Analog peripherals:  Comparator with internal and external voltage references with pin functions assigned or enabled through the switch matrix.  Serial interfaces:  Three USART interfaces with pin functions assigned through the switch matrix.  Two SPI controllers with pin functions assigned through the switch matrix.  One I2C-bus interface with pin functions assigned through the switch matrix.  Clock generation:  12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  10 kHz low-power oscillator for the WKT.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input CLKIN, or the internal RC oscillator.  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator.  Power control:  Integrated PMU (Power Management Unit) to minimize power consumption.  Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.  Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and I2C peripherals.  Timer-controlled self wake-up from Deep power-down mode.  Power-On Reset (POR).  Brownout detect.  Unique device serial number for identification.  Single power supply.  Operating temperature range 40 °C to 105 °C except for the DIP8 package, which is available for a temperature range of 40 °C to 85 °C.  Available as DIP8, TSSOP16, SO20, TSSOP20, and XSON16 package. 3. Applications  8/16-bit applications  Lighting  Consumer  Motor control  Climate control  Fire and security applications LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 3 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 4. Ordering information 4.1 Ordering options Table 1. Ordering information Type number Package Name Description Version LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2 LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC812M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 LPC812M101JTB16 XSON16 plastic extremely thin small outline package; no leads; 16 terminals; body 2.5  3.2  0.5 mm SOT1341-1 Table 2. Ordering options Type number Flash/kB SRAM/kB USART I2C-bus SPI Comparator GPIO Package LPC810M021FN8 4 1 2 1 1 1 6 DIP8 LPC811M001JDH16 8 2 2 1 1 1 14 TSSOP16 LPC812M101JDH16 16 4 3 1 2 1 14 TSSOP16 LPC812M101JD20 16 4 2 1 1 1 18 SO20 LPC812M101JDH20 16 4 3 1 2 1 18 TSSOP20 LPC812M101JTB16 16 4 3 1 2 1 14 XSON16 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 4 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 5. Marking The LPC81xM devices typically have the following top-side marking: LPC81x xxxxx xxxxxxxx xxYWWxR[x] The last two letters in the last line (field ‘xR’) identify the boot code version and device revision. Field ‘Y’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Remark: On the TSSOP16 package, the last line includes only the date code xxYWW. Table 3. Device revision table Revision identifier (xR) Revision description ‘1A’ Initial device revision with boot code version 13.1 ‘2A’ Device revision with boot code version 13.2 ’4C’ Device revision with boot code version 13.4 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 5 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 6. Block diagram Fig 1. LPC81xM block diagram 􀀶􀀵􀀤􀀰 􀀔􀀒􀀕􀀒􀀗􀀃􀁎􀀥 􀀤􀀵􀀰 􀀦􀀲􀀵􀀷􀀨􀀻􀀐􀀰􀀓􀀎 􀀷􀀨􀀶􀀷􀀒􀀧􀀨􀀥􀀸􀀪 􀀬􀀱􀀷􀀨􀀵􀀩􀀤􀀦􀀨 􀀩􀀯􀀤􀀶􀀫 􀀗􀀒􀀛􀀒􀀔􀀙􀀃􀁎􀀥 􀀫􀀬􀀪􀀫􀀐􀀶􀀳􀀨􀀨􀀧 􀀪􀀳􀀬􀀲 􀀤􀀫􀀥􀀃􀀷􀀲􀀃􀀤􀀳􀀥 􀀥􀀵􀀬􀀧􀀪􀀨􀀃 􀀦􀀯􀀲􀀦􀀮 􀀪􀀨􀀱􀀨􀀵􀀤􀀷􀀬􀀲􀀱􀀏 􀀳􀀲􀀺􀀨􀀵􀀃􀀦􀀲􀀱􀀷􀀵􀀲􀀯􀀏 􀀶􀀼􀀶􀀷􀀨􀀰􀀃 􀀩􀀸􀀱􀀦􀀷􀀬􀀲􀀱􀀶 􀀵􀀨􀀶􀀨􀀷􀀏􀀃􀀦􀀯􀀮􀀬􀀱 􀁆􀁏􀁒􀁆􀁎􀁖􀀃􀁄􀁑􀁇􀀃 􀁆􀁒􀁑􀁗􀁕􀁒􀁏􀁖 􀀯􀀳􀀦􀀛􀀔􀁛􀀰 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀙 􀁖􀁏􀁄􀁙􀁈 􀁖􀁏􀁄􀁙􀁈 􀁖􀁏􀁄􀁙􀁈 􀀵􀀲􀀰 􀁖􀁏􀁄􀁙􀁈 􀀦􀀵􀀦 􀁖􀁏􀁄􀁙􀁈 􀀳􀀬􀀱􀀃􀀬􀀱􀀷􀀨􀀵􀀵􀀸􀀳􀀷􀀶􀀒 􀀳􀀤􀀷􀀷􀀨􀀵􀀱􀀃􀀰􀀤􀀷􀀦􀀫 􀀤􀀫􀀥􀀐􀀯􀀬􀀷􀀨􀀃􀀃􀀥􀀸􀀶 􀀬􀀵􀀦 􀀺􀀧􀀲􀁖􀁆 􀀥􀀲􀀧 􀀳􀀲􀀵 􀀶􀀳􀀬􀀓 􀀸􀀶􀀤􀀵􀀷􀀓 􀀶􀀧􀀤 􀀶􀀦􀀯 􀀦􀀷􀀬􀀱􀁂􀀾􀀖􀀝􀀓􀁀 􀀦􀀷􀀲􀀸􀀷􀁂􀀾􀀖􀀝􀀓􀁀 􀀔􀀛􀀃􀁛􀀃 􀀳􀀬􀀲􀀓 􀀔􀀛􀀃􀁛􀀃 􀀺􀀺􀀧􀀷 􀀬􀀲􀀦􀀲􀀱 􀀳􀀰􀀸 􀀶􀀨􀀯􀀩 􀀺􀀤􀀮􀀨􀀐􀀸􀀳􀀃􀀷􀀬􀀰􀀨􀀵 􀀰􀀸􀀯􀀷􀀬􀀐􀀵􀀤􀀷􀀨􀀃􀀷􀀬􀀰􀀨􀀵 􀀶􀀳􀀬􀀔 􀀬􀀕􀀦􀀐􀀥􀀸􀀶 􀀶􀀦􀀷􀀬􀀰􀀨􀀵􀀒 􀀳􀀺􀀰 􀀶􀀺􀀬􀀷􀀦􀀫 􀀰􀀤􀀷􀀵􀀬􀀻 􀀦􀀲􀀰􀀳􀀤􀀵􀀤􀀷􀀲􀀵 􀀻􀀷􀀤􀀯􀀬􀀱 􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀤􀀦􀀰􀀳􀁂􀀲 􀀶􀀼􀀶􀀦􀀲􀀱 􀀵􀀻􀀧􀀏􀀃􀀦􀀷􀀶 􀀷􀀻􀀧􀀏􀀃􀀵􀀷􀀶 􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀕 􀀹􀀧􀀧􀀦􀀰􀀳 􀀶􀀦􀀮􀀏􀀃􀀶􀀶􀀨􀀯 􀀰􀀬􀀶􀀲􀀏􀀃􀀰􀀲􀀶􀀬 􀀶􀀦􀀮􀀏􀀃􀀶􀀶􀀨􀀯 􀀰􀀬􀀶􀀲􀀏􀀃􀀰􀀲􀀶􀀬 􀀤􀀯􀀺􀀤􀀼􀀶􀀐􀀲􀀱􀀃􀀳􀀲􀀺􀀨􀀵􀀃􀀧􀀲􀀰􀀤􀀬􀀱 􀀻􀀷􀀤􀀯 􀀶􀀦􀀯􀀮 􀀸􀀶􀀤􀀵􀀷􀀔 􀀵􀀻􀀧􀀏􀀃􀀦􀀷􀀶 􀀷􀀻􀀧􀀏􀀃􀀵􀀷􀀶 􀀶􀀦􀀯􀀮 􀀸􀀶􀀤􀀵􀀷􀀕 􀀵􀀻􀀧􀀏􀀃􀀦􀀷􀀶 􀀷􀀻􀀧􀀏􀀃􀀵􀀷􀀶 􀀶􀀦􀀯􀀮 􀀦􀀯􀀮􀀲􀀸􀀷 􀀶􀀺􀀦􀀯􀀮􀀏􀀃􀀶􀀺􀀧 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 6 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration DIP8 package (LPC810M021JN8) 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀚 􀀔 􀀕 􀀖 􀀗 􀀙 􀀘 􀀛 􀀚 􀀧􀀬􀀳􀀛 Fig 3. Pin configuration TSSOP16 package (LPC811M001JDH16 and LPC812M101JDH16) 􀀷􀀶􀀶􀀲􀀳􀀔􀀙 􀀳􀀬􀀲􀀓􀁂􀀔􀀖 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀔􀀕 􀀳􀀬􀀲􀀓􀁂􀀙􀀒􀀹􀀧􀀧􀀦􀀰􀀳 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀚 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀛􀀒􀀻􀀷􀀤􀀯􀀬􀀱 􀀳􀀬􀀲􀀓􀁂􀀔􀀔 􀀳􀀬􀀲􀀓􀁂􀀜􀀒􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀳􀀬􀀲􀀓􀁂􀀔􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀁄􀁄􀁄􀀐􀀓􀀓􀀖􀀚􀀓􀀚 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀔􀀓 􀀜 􀀔􀀕 􀀔􀀔 􀀔􀀗 􀀔􀀖 􀀔􀀙 􀀔􀀘 Fig 4. Pin configuration SO20 package (LPC812M101JD20) 􀀶􀀲􀀕􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀚 􀀳􀀬􀀲􀀓􀁂􀀔􀀗 􀀳􀀬􀀲􀀓􀁂􀀔􀀖 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀔􀀕 􀀳􀀬􀀲􀀓􀁂􀀙􀀒􀀹􀀧􀀧􀀦􀀰􀀳 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀚 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀛􀀒􀀻􀀷􀀤􀀯􀀬􀀱 􀀳􀀬􀀲􀀓􀁂􀀔􀀔 􀀳􀀬􀀲􀀓􀁂􀀜􀀒􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀳􀀬􀀲􀀓􀁂􀀔􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀀳􀀬􀀲􀀓􀁂􀀔􀀙 􀀳􀀬􀀲􀀓􀁂􀀔􀀘 􀁄􀁄􀁄􀀐􀀓􀀓􀀖􀀚􀀘􀀙 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀜 􀀔􀀓 􀀔􀀕 􀀔􀀔 􀀔􀀗 􀀔􀀖 􀀔􀀙 􀀔􀀘 􀀔􀀛 􀀔􀀚 􀀕􀀓 􀀔􀀜 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 7 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 5. Pin configuration TSSOP20 package (LPC812M101JDH20) 􀀷􀀶􀀶􀀲􀀳􀀕􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀚 􀀳􀀬􀀲􀀓􀁂􀀔􀀗 􀀳􀀬􀀲􀀓􀁂􀀔􀀖 􀀳􀀬􀀲􀀓􀁂􀀓􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀔􀀒􀀷􀀧􀀲 􀀳􀀬􀀲􀀓􀁂􀀔􀀕 􀀳􀀬􀀲􀀓􀁂􀀙􀀒􀀹􀀧􀀧􀀦􀀰􀀳 􀀵􀀨􀀶􀀨􀀷􀀒􀀳􀀬􀀲􀀓􀁂􀀘 􀀳􀀬􀀲􀀓􀁂􀀚 􀀳􀀬􀀲􀀓􀁂􀀗􀀒􀀺􀀤􀀮􀀨􀀸􀀳􀀒􀀷􀀵􀀶􀀷 􀀹􀀶􀀶 􀀶􀀺􀀦􀀯􀀮􀀒􀀳􀀬􀀲􀀓􀁂􀀖􀀒􀀷􀀦􀀮 􀀹􀀧􀀧 􀀶􀀺􀀧􀀬􀀲􀀒􀀳􀀬􀀲􀀓􀁂􀀕􀀒􀀷􀀰􀀶 􀀳􀀬􀀲􀀓􀁂􀀛􀀒􀀻􀀷􀀤􀀯􀀬􀀱 􀀳􀀬􀀲􀀓􀁂􀀔􀀔 􀀳􀀬􀀲􀀓􀁂􀀜􀀒􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀳􀀬􀀲􀀓􀁂􀀔􀀓 􀀳􀀬􀀲􀀓􀁂􀀔􀀒􀀤􀀦􀀰􀀳􀁂􀀬􀀕􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀷􀀧􀀬 􀀳􀀬􀀲􀀓􀁂􀀔􀀙 􀀳􀀬􀀲􀀓􀁂􀀔􀀘 􀁄􀁄􀁄􀀐􀀓􀀓􀀖􀀚􀀚􀀘 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀜 􀀔􀀓 􀀔􀀕 􀀔􀀔 􀀔􀀗 􀀔􀀖 􀀔􀀙 􀀔􀀘 􀀔􀀛 􀀔􀀚 􀀕􀀓 􀀔􀀜 Fig 6. Pin configuration XSON16 package (LPC812M101JTB16) terminal 1 index area XSON16 16 aaa-009570 Transparent top view 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 PIO0_13 PIO0_12 RESET/PIO0_5 PIO0_4/WAKEUP/TRST SWCLK/PIO0_3/TCK SWDIO/PIO0_2/TMS PIO0_11 PIO0_10 PIO0_0/ACMP_I1/TDO PIO0_6/VDDCMP PIO0_7 VSS VDD PIO0_8/XTALIN PIO0_9/XTALOUT PIO0_1/ACMP_I2/CLKIN/TDI LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 8 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description The pin description consists of two parts showing pin functions that are fixed to a certain package pin (see Table 4) and showing pin functions that can be assigned to any pin on the package through the switch matrix (see Table 5). The pin description table in Table 4 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable between GPIO and the comparator inputs, SWD, RESET, and the XTAL pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Table 5 shows the the I2C, USART, SPI, and SCT pin functions, which can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: For full I2C-bus compatibility, assign the I2C functions to the open-drain pins PIO0_11 and PIO0_10. Do not assign more than one output to any pin. However, more than one input can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled. Pin PIO0_4 triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. Table 4. Pin description table (fixed pins) Symbol SO20/ TSSOP20 TSSOP16 XSON16 DIP8 Type Reset state [1] Description PIO0_0/ACMP_I1/ TDO 19 16 16 8 [5] I/O I; PU PIO0_0 — General purpose digital input/output port 0 pin 0. In ISP mode, this is the USART0 receive pin U0_RXD. In boundary scan mode: TDO (Test Data Out). AI - ACMP_I1 — Analog comparator input 1. PIO0_1/ACMP_I2/ CLKIN/TDI 12 9 9 5 [5] I/O I; PU PIO0_1 — General purpose digital input/output pin. In boundary scan mode: TDI (Test Data In). ISP entry pin on chip versions 1A and 2A and on the DIP8 package (see Table 6). For these chip versions and packages, a LOW level on this pin during reset starts the ISP command handler. See PIO0_12 for all other packages. AI - ACMP_I2 — Analog comparator input 2. I - CLKIN — External clock input. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 9 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller SWDIO/PIO0_2/TMS 7 6 6 4 [2] I/O I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O - PIO0_2 — General purpose digital input/output pin. SWCLK/PIO0_3/ TCK 6 5 5 3 [2] I/O I; PU SWCLK — Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). I/O - PIO0_3 — General purpose digital input/output pin. PIO0_4/WAKEUP/ TRST 5 4 4 2 [6] I/O I; PU PIO0_4 — General purpose digital input/output pin. In ISP mode, this is the USART0 transmit pin U0_TXD. In boundary scan mode: TRST (Test Reset). This pin triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. This pin should be pulled HIGH externally before entering Deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit Deep power-down mode and wakes up the part. RESET/PIO0_5 4 3 3 1 [4] I/O I; PU RESET — External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed and the Deep power-down mode is not used. I - PIO0_5 — General purpose digital input/output pin. PIO0_6/VDDCMP 18 15 15 - [9] I/O I; PU PIO0_6 — General purpose digital input/output pin. AI - VDDCMP — Alternate reference voltage for the analog comparator. PIO0_7 17 14 14 - [2] I/O I; PU PIO0_7 — General purpose digital input/output pin. PIO0_8/XTALIN 14 11 11 - [8] I/O I; PU PIO0_8 — General purpose digital input/output pin. I - XTALIN — Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.95 V. PIO0_9/XTALOUT 13 10 10 - [8] I/O I; PU PIO0_9 — General purpose digital input/output pin. O - XTALOUT — Output from the oscillator circuit. PIO0_10 9 8 8 - [3]I IA PIO0_10 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. PIO0_11 8 7 7 - [3]I IA PIO0_11 — General purpose digital input/output pin. Assign I2C functions to this pin when true open-drain pins are needed for a signal compliant with the full I2C specification. Table 4. Pin description table (fixed pins) Symbol SO20/ TSSOP20 TSSOP16 XSON16 DIP8 Type Reset state [1] Description LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 10 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. Remark: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0 register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally. [4] See Figure 11 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. [5] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep power-down mode, pulling this pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other purposes, if the WKT low power oscillator is enabled for waking up the part from Deep power-down mode. [7] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [9] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled. PIO0_12 3 2 2 - [2] I/O I; PU PIO0_12 — General purpose digital input/output pin. ISP entry pin on the SO20/TSSOP20/TSSOP16/XSON16 packages starting with chip version 4C (see Table 6). A LOW level on this pin during reset starts the ISP command handler. See pin PIO0_1 for the DIP8 package and chip versions 1A and 2A. PIO0_13 2 1 1 - [2] I/O I; PU PIO0_13 — General purpose digital input/output pin. PIO0_14 20 - - - [7] I/O I; PU PIO0_14 — General purpose digital input/output pin. PIO0_15 11 - - - [7] I/O I; PU PIO0_15 — General purpose digital input/output pin. PIO0_16 10 - - - [7] I/O I; PU PIO0_16 — General purpose digital input/output pin. PIO0_17 1 - - - [7] I/O I; PU PIO0_17 — General purpose digital input/output pin. VDD 15 12 12 6 - - 3.3 V supply voltage. VSS 16 13 13 7 - - Ground. Table 4. Pin description table (fixed pins) Symbol SO20/ TSSOP20 TSSOP16 XSON16 DIP8 Type Reset state [1] Description Table 5. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description U0_TXD O Transmitter output for USART0. U0_RXD I Receiver input for USART0. U0_RTS O Request To Send output for USART0. U0_CTS I Clear To Send input for USART0. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 11 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. U1_TXD O Transmitter output for USART1. U1_RXD I Receiver input for USART1. U1_RTS O Request To Send output for USART1. U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode. U2_TXD O Transmitter output for USART2. U2_RXD I Receiver input for USART2. U2_RTS O Request To Send output for USART2. U2_CTS I Clear To Send input for USART2. U2_SCLK I/O Serial clock input/output for USART2 in synchronous mode. SPI0_SCK I/O Serial clock for SPI0. SPI0_MOSI I/O Master Out Slave In for SPI0. SPI0_MISO I/O Master In Slave Out for SPI0. SPI0_SSEL I/O Slave select for SPI0. SPI1_SCK I/O Serial clock for SPI1. SPI1_MOSI I/O Master Out Slave In for SPI1. SPI1_MISO I/O Master In Slave Out for SPI1. SPI1_SSEL I/O Slave select for SPI1. CTIN_0 I SCT input 0. CTIN_1 I SCT input 1. CTIN_2 I SCT input 2. CTIN_3 I SCT input 3. CTOUT_0 O SCT output 0. CTOUT_1 O SCT output 1. CTOUT_2 O SCT output 2. CTOUT_3 O SCT output 3. I2C0_SCL I/O I2C-bus clock input/output (open-drain if assigned to pin PIO0_10). High-current sink only if assigned to PIO0_10 and if I2C Fast-mode Plus is selected in the I/O configuration register. I2C0_SDA I/O I2C-bus data input/output (open-drain if assigned to pin PIO0_11). High-current sink only if assigned to pin PIO0_11 and if I2C Fast-mode Plus is selected in the I/O configuration register. ACMP_O O Analog comparator digital output. CLKOUT O Clock output. GPIO_INT_BMAT O Output of the pattern match engine. Table 5. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 12 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Table 6. Pin location in ISP mode ISP entry pin USART RXD USART TXD Marking Boot loader version Package PIO0_1 PIO0_0 PIO0_4 1A v 13.1 TSSOP20; SO20; TSSOP16; DIP8; XSON16 PIO0_1 PIO0_0 PIO0_4 2A v 13.2 TSSOP20; SO20; TSSOP16; DIP8; XSON16 PIO0_1 PIO0_0 PIO0_4 4C and later v 13.4 and later DIP8 PIO0_12 PIO0_0 PIO0_4 4C and later v 13.4 and later TSSOP20; SO20; TSSOP16; XSON16 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 13 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.2 On-chip flash program memory The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory supports a 64 Byte page size with page write and erase. 8.3 On-chip SRAM The LPC81xM contain a total of up to 4 kB on-chip static RAM data memory. 8.4 On-chip ROM The 8 kB on-chip ROM contains the boot loader and the following Application Programming Interfaces (API): • In-System Programming (ISP) and In-Application Programming (IAP) support for flash programming • Power profiles for configuring power consumption and PLL settings • USART driver API routines • I2C-bus driver API routines 8.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.5.1 Features • Controls system exceptions and peripheral interrupts. • On the LPC81xM, the NVIC supports 32 vectored interrupts including up to 8 external interrupt inputs selectable from all GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation using the ARM exceptions SVCall and PendSV. • Relocatable interrupt vector table using vector table offset register. 8.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 14 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Up to eight pins, regardless of the selected function, can be programmed to generate an interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block controls the edge or level detection mechanism. 8.6 System tick timer The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to generate a dedicated SysTick exception at a fixed time interval (typically 10 ms). 8.7 Memory map The LPC81xM incorporates several distinct memory regions. Figure 7 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The ARM private peripheral bus includes the ARM core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 15 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.8 I/O configuration The IOCON block controls the configuration of the I/O pins. Each digital or mixed digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10 and PIO0_11) in Table 4 can be configured as follows: • Enable or disable the weak internal pull-up and pull-down resistors. • Select a pseudo open-drain mode. The input cannot be pulled up above VDD. This pin is not 5 V tolerant when VDD = 0. Fig 7. LPC81xM Memory map 􀀤􀀳􀀥􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀁖 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀗􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀛􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀦􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀔􀀃􀀗􀀓􀀓􀀓 􀀺􀀺􀀧􀀷 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀰􀀵􀀷 􀀃􀁖􀁈􀁏􀁉􀀃􀁚􀁄􀁎􀁈􀀐􀁘􀁓􀀃􀁗􀁌􀁐􀁈􀁕 􀀳􀀰􀀸 􀀖􀀔􀀃􀀐􀀃􀀕􀀛􀀃􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁆􀁒􀁐􀁓􀁄􀁕􀁄􀁗􀁒􀁕 􀀓􀁛􀀗􀀓􀀓􀀕􀀃􀀦􀀓􀀓􀀓 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀖􀀃􀀗􀀓􀀓􀀓 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀀙 􀀚 􀀛 􀀜 􀀔􀀙 􀀔􀀘 􀀔􀀗 􀀔􀀚 􀀔􀀛 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀓􀀃􀀪􀀥 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀀑􀀘􀀃􀀪􀀥 􀀗􀀃􀀪􀀥 􀀔􀀃􀀪􀀥 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀔􀀩􀀩􀀩􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀔􀀩􀀩􀀩􀀃􀀕􀀓􀀓􀀓 􀀓􀁛􀀕􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀘􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀘􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀓􀁛􀀩􀀩􀀩􀀩􀀃􀀩􀀩􀀩􀀩 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀓􀁛􀀗􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀛􀀃􀀓􀀓􀀓􀀓 􀀤􀀳􀀥􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀁖 􀀓􀁛􀀘􀀓􀀓􀀓􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀤􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀤􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀦􀀵􀀦 􀀶􀀦􀀷􀁌􀁐􀁈􀁕􀀒􀀳􀀺􀀰 􀀪􀀳􀀬􀀲 􀀓􀁛􀀤􀀓􀀓􀀓􀀃􀀛􀀓􀀓􀀓 􀁓􀁌􀁑􀀃􀁌􀁑􀁗􀁈􀁕􀁕􀁘􀁓􀁗􀁖􀀒􀁓􀁄􀁗􀁗􀁈􀁕􀁑􀀃􀁐􀁄􀁗􀁆􀁋 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀓􀀛􀀓􀀓 􀀕􀀃􀁎􀀥􀀃􀀃􀀶􀀵􀀤􀀰􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀔􀀌 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀓􀀗􀀓􀀓 􀀔􀀃􀁎􀀥􀀃􀀃􀀶􀀵􀀤􀀰􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀓􀀌 􀀓􀁛􀀔􀀓􀀓􀀓􀀃􀀔􀀓􀀓􀀓 􀀗􀀃􀁎􀀥􀀃􀀃􀀶􀀵􀀤􀀰􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀕􀀌 􀀓􀁛􀀔􀀗􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀔􀀗􀀓􀀓􀀃􀀓􀀗􀀓􀀓 􀀔􀀃􀁎􀀥􀀃􀀰􀀷􀀥􀀃􀁕􀁈􀁊􀁌􀁖􀁗􀁈􀁕􀁖 􀀯􀀳􀀦􀀛􀀔􀁛􀀰 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀗􀀓􀀓􀀓 􀀔􀀙􀀃􀁎􀀥􀀃􀁒􀁑􀀐􀁆􀁋􀁌􀁓􀀃􀁉􀁏􀁄􀁖􀁋􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀕􀀌 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀕􀀓􀀓􀀓 􀀛􀀃􀁎􀀥􀀃􀁒􀁑􀀐􀁆􀁋􀁌􀁓􀀃􀁉􀁏􀁄􀁖􀁋􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀔􀀌 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀔􀀓􀀓􀀓 􀀗􀀃􀁎􀀥􀀃􀁒􀁑􀀐􀁆􀁋􀁌􀁓􀀃􀁉􀁏􀁄􀁖􀁋􀀃􀀋􀀯􀀳􀀦􀀛􀀔􀀓􀀌 􀀛􀀃􀁎􀀥􀀃􀁅􀁒􀁒􀁗􀀃􀀵􀀲􀀰 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀓􀀓􀀓􀀓􀀃􀀓􀀓􀀦􀀓 􀁄􀁆􀁗􀁌􀁙􀁈􀀃􀁌􀁑􀁗􀁈􀁕􀁕􀁘􀁓􀁗􀀃􀁙􀁈􀁆􀁗􀁒􀁕􀁖 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀛 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁉􀁏􀁄􀁖􀁋􀀃􀁆􀁒􀁑􀁗􀁕􀁒􀁏􀁏􀁈􀁕 􀀶􀀳􀀬􀀓 􀁖􀁚􀁌􀁗􀁆􀁋􀀃􀁐􀁄􀁗􀁕􀁌􀁛 􀀬􀀲􀀦􀀲􀀱 􀀶􀀼􀀶􀀦􀀲􀀱 􀀓􀁛􀀗􀀓􀀓􀀘􀀃􀀗􀀓􀀓􀀓 􀀔􀀜 􀀕􀀕 􀀕􀀖 􀀶􀀳􀀬􀀔 􀀸􀀶􀀤􀀵􀀷􀀓 􀀸􀀶􀀤􀀵􀀷􀀔 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀛􀀓􀀓􀀓 􀀓􀁛􀀗􀀓􀀓􀀙􀀃􀀦􀀓􀀓􀀓 􀀸􀀶􀀤􀀵􀀷􀀕 􀀓􀁛􀀗􀀓􀀓􀀚􀀃􀀓􀀓􀀓􀀓 􀀕􀀗 􀀓􀁛􀀨􀀓􀀓􀀓􀀃􀀓􀀓􀀓􀀓 􀀓􀁛􀀨􀀓􀀔􀀓􀀃􀀓􀀓􀀓􀀓 􀁓􀁕􀁌􀁙􀁄􀁗􀁈􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀀃􀁅􀁘􀁖 􀀕􀀓 􀀬􀀕􀀦 􀀕􀀔 􀀕􀀘 􀀕􀀙 􀀕􀀚 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀁕􀁈􀁖􀁈􀁕􀁙􀁈􀁇 􀀔􀀓 􀀔􀀔 􀀔􀀕 􀀔􀀖 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 16 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see Figure 10 “LPC81xM clock generation”). You can also bypass the glitch filter. • Invert the input signal. • Hysteresis can be enabled or disabled. • For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard digital operation, for I2C standard and fast modes, or for I2C Fast mode+. • On mixed digital/analog pins, enable the analog input mode. Enabling the analog mode disconnects the digital functionality. Remark: The functionality of each I/O pin is flexible and is determined entirely through the switch matrix. See Section 8.9 for details. 8.8.1 Standard I/O pad configuration Figure 8 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver with configurable open-drain output • Digital input: Weak pull-up resistor (PMOS device) enabled/disabled • Digital input: Weak pull-down resistor (NMOS device) enabled/disabled • Digital input: Repeater mode enabled/disabled • Digital input: Input glitch filter selectable on all pins • Analog input LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 17 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.9 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, SCT, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 5. Functions that need specialized pads like the oscillator pins XTALIN and XTALOUT can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Table 4. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. 8.10 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC81xM use accelerated GPIO functions: • GPIO registers are located on the ARM Cortex M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 15 MHz. Fig 8. Standard I/O pad configuration 􀀳􀀬􀀱 􀀹􀀧􀀧 􀀹􀀧􀀧 􀀨􀀶􀀧 􀀹􀀶􀀶 􀀨􀀶􀀧 􀁖􀁗􀁕􀁒􀁑􀁊 􀁓􀁘􀁏􀁏􀀐􀁘􀁓 􀁖􀁗􀁕􀁒􀁑􀁊 􀁓􀁘􀁏􀁏􀀐􀁇􀁒􀁚􀁑 􀀹􀀧􀀧 􀁚􀁈􀁄􀁎 􀁓􀁘􀁏􀁏􀀐􀁘􀁓 􀁚􀁈􀁄􀁎 􀁓􀁘􀁏􀁏􀀐􀁇􀁒􀁚􀁑 􀁒􀁓􀁈􀁑􀀐􀁇􀁕􀁄􀁌􀁑􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁒􀁘􀁗􀁓􀁘􀁗􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁕􀁈􀁓􀁈􀁄􀁗􀁈􀁕􀀃􀁐􀁒􀁇􀁈 􀁈􀁑􀁄􀁅􀁏􀁈 􀁓􀁘􀁏􀁏􀀐􀁘􀁓􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁓􀁘􀁏􀁏􀀐􀁇􀁒􀁚􀁑􀀃􀁈􀁑􀁄􀁅􀁏􀁈 􀁖􀁈􀁏􀁈􀁆􀁗􀀃􀁇􀁄􀁗􀁄 􀁌􀁑􀁙􀁈􀁕􀁗􀁈􀁕 􀁇􀁄􀁗􀁄􀀃􀁒􀁘􀁗􀁓􀁘􀁗 􀁇􀁄􀁗􀁄􀀃􀁌􀁑􀁓􀁘􀁗 􀁖􀁈􀁏􀁈􀁆􀁗􀀃􀁊􀁏􀁌􀁗􀁆􀁋 􀁉􀁌􀁏􀁗􀁈􀁕 􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁌􀁑􀁓􀁘􀁗 􀁖􀁈􀁏􀁈􀁆􀁗􀀃􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁌􀁑􀁓􀁘􀁗 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀖􀀚􀀚 􀁓􀁌􀁑􀀃􀁆􀁒􀁑􀁉􀁌􀁊􀁘􀁕􀁈􀁇 􀁄􀁖􀀃􀁇􀁌􀁊􀁌􀁗􀁄􀁏􀀃􀁒􀁘􀁗􀁓􀁘􀁗 􀁇􀁕􀁌􀁙􀁈􀁕 􀁓􀁌􀁑􀀃􀁆􀁒􀁑􀁉􀁌􀁊􀁘􀁕􀁈􀁇 􀁄􀁖􀀃􀁇􀁌􀁊􀁌􀁗􀁄􀁏􀀃􀁌􀁑􀁓􀁘􀁗 􀁓􀁌􀁑􀀃􀁆􀁒􀁑􀁉􀁌􀁊􀁘􀁕􀁈􀁇 􀁄􀁖􀀃􀁄􀁑􀁄􀁏􀁒􀁊􀀃􀁌􀁑􀁓􀁘􀁗 􀀳􀀵􀀲􀀪􀀵􀀤􀀰􀀰􀀤􀀥􀀯􀀨 􀀪􀀯􀀬􀀷􀀦􀀫􀀃􀀩􀀬􀀯􀀷􀀨􀀵 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 18 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default. 8.10.1 Features • Bit level port registers allow a single instruction to set and clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to inputs with internal pull-up resistors enabled after reset - except for the I2C-bus true open-drain pins PIO0_2 and PIO0_3. • Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin (see Figure 8). • 8.11 Pin interrupt/pattern match engine The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. The pattern match engine can be used, in conjunction with software, to create complex state machines based on pin inputs. Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are located on the IO+ bus for fast single-cycle access. 8.11.1 Features • Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. – Pin interrupts can wake up the LPC81xM from sleep mode, deep-sleep mode, and power-down mode. • Pin interrupt pattern match engine – Up to eight pins can be selected from all digital pins to contribute to a boolean expression. The boolean expression consists of specified levels and/or transitions on various combinations of these pins. – Each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. – Any occurrence of a pattern match can be programmed to also generate an RXEV notification to the ARM CPU. The RXEV signal can be connected to a pin. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 19 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller – The pattern match engine does not facilitate wake-up. 8.12 USART0/1/2 Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only. All USART functions are movable functions and are assigned to pins through the switch matrix. 8.12.1 Features • Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins except PIO0_10 and PIO0_11. • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer. • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. • Received data and status can optionally be read from a single register • Break generation and detection. • Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. • Built-in Baud Rate Generator. • A fractional rate divider is shared among all UARTs. • Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. • Separate data and flow control loopback modes for testing. • Supported by on-chip ROM API. 8.13 SPI0/1 Remark: SPI0 is available on all LPC800 parts. SPI1 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only. All SPI functions are movable functions and are assigned to pins through the switch matrix. 8.13.1 Features • Maximum data rates of 30 Mbit/s in master mode and 25 Mbit/s in slave mode for SPI functions connected to all digital pins except PIO0_10 and PIO0_11. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 20 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory. • Control information can optionally be written along with data. This allows very versatile operation, including “any length” frames. • One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported. 8.14 I2C-bus interface The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. The I2C-bus functions are movable functions and can be assigned through the switch matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the electrical characteristics to support the full I2C-bus specification (see Ref. 1). 8.14.1 Features • Supports standard and fast mode with data rates of up to 400 kbit/s. • Independent Master, Slave, and Monitor functions. • Supports both Multi-master and Multi-master with Slave functions. • Multiple I2C slave addresses supported in hardware. • One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses. • 10-bit addressing supported with software assist. • Supports SMBus. • Supported by on-chip ROM API. • If the I2C functions are connected to the true open-drain pins (PIO0_10 and PIO0_11), the I2C supports the full I2C-bus specification: – Fail-safe operation: When the power to an I2C-bus device is switched off, the SDA and SCL pins connected to the I2C-bus are floating and do not disturb the bus. – Supports Fast-mode Plus with bit rates up to 1 Mbit/s. 8.15 State-Configurable Timer/PWM (SCTimer/PWM) The state configurable timer (SCTimer/PWM or SCT) can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and internal capture inputs. In addition, the SCTimer/PWM can employ up to two different programmable states, which can change under the control of events, to provide complex timing patterns. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 21 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller All inputs and outputs of the SCTimer/PWM are movable functions and are assigned to pins through the switch matrix. 8.15.1 Features • Two 16-bit counters or one 32-bit counter. • Counters clocked by bus clock or selected input. • Up counters or up-down counters. • State variable allows sequencing across multiple counter cycles. • The following conditions define an event: a counter match condition, an input (or output) condition, a combination of a match and/or and input/output condition in a specified state, and the count direction. • Events control outputs, interrupts, and the SCT states. – Match register 0 can be used as an automatic limit. – In bi-directional mode, events can be enabled based on the count direction. – Match events can be held until another qualifying event occurs. • Selected events can limit, halt, start, or stop a counter. • Supports: – 4 inputs – 4 outputs – 5 match/capture registers – 6 events – 2 states 8.16 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 8.16.1 Features • 31-bit interrupt timer • Four channels independently counting down from individually set values • Bus stall, repeat and one-shot interrupt modes 8.17 Windowed WatchDog Timer (WWDT) The watchdog timer resets the controller if software fails to periodically service it within a programmable time window. 8.17.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 22 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect feed sequence causes reset or interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK)is generated by a the dedicated watchdog oscillator (WDOSC). 8.18 Self Wake-up Timer (WKT) The self wake-up timer is a 32-bit, loadable down-counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is used as a wake-up timer, this write can occur just prior to entering a reduced power mode. 8.18.1 Features • 32-bit loadable down-counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request. • The WKT resides in a separate, always-on power domain. • The WKT supports two clock sources: the low-power oscillator and the IRC. The low-power oscillator is located in the always-on power domain, so it can be used as the clock source in Deep power-down mode. • The WKT can be used for waking up the part from any reduced power mode, including Deep power-down mode, or for general-purpose timing. 8.19 Analog comparator (ACMP) The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages. After power-up and after switching the input channels of the comparator, the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. Settling times are given in Table 22. The analog comparator output is a movable function and is assigned to a pin through the switch matrix. The comparator inputs and the voltage reference are enabled or disabled on pins PIO0_0 and PIO0_1 through the switch matrix. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 23 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.19.1 Features • Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis. • Two selectable external voltages (VDD or VDDCMP on pin PIO0_6); fully configurable on either positive or negative input channel. • Internal voltage reference from band gap selectable on either positive or negative input channel. • 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. • Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail. • Voltage ladder can be separately powered down for applications only requiring the comparator function. • Interrupt output is connected to NVIC. • Comparator level output is connected to output pin ACMP_O. • The comparator output can be routed internally to the SCT input through the switch matrix. Fig 9. Comparator block diagram 􀀕 􀀖􀀕 􀀕 􀀤􀀦􀀰􀀳􀁂􀀬􀀾􀀕􀀝􀀔􀁀 􀀹􀀧􀀧 􀀹􀀧􀀧􀀦􀀰􀀳 􀁌􀁑􀁗􀁈􀁕􀁑􀁄􀁏 􀁙􀁒􀁏􀁗􀁄􀁊􀁈 􀁕􀁈􀁉􀁈􀁕􀁈􀁑􀁆􀁈 􀁈􀁇􀁊􀁈􀀃􀁇􀁈􀁗􀁈􀁆􀁗 􀁖􀁜􀁑􀁆 􀁆􀁒􀁐􀁓􀁄􀁕􀁄􀁗􀁒􀁕 􀁏􀁈􀁙􀁈􀁏􀀃􀀤􀀦􀀰􀀳􀁂􀀲 􀁆􀁒􀁐􀁓􀁄􀁕􀁄􀁗􀁒􀁕 􀁈􀁇􀁊􀁈􀀃􀀱􀀹􀀬􀀦 􀀦􀀲􀀰􀀳􀀤􀀵􀀤􀀷􀀲􀀵􀀃􀀤􀀱􀀤􀀯􀀲􀀪􀀃􀀥􀀯􀀲􀀦􀀮 􀀦􀀲􀀰􀀳􀀤􀀵􀀤􀀷􀀲􀀵􀀃􀀧􀀬􀀪􀀬􀀷􀀤􀀯􀀃􀀥􀀯􀀲􀀦􀀮 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀘􀀓􀀛 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 24 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.20 Clocking and power control 8.20.1 Crystal and internal oscillators The LPC81xM include four independent oscillators: 1. The crystal oscillator (SysOsc) operating at frequencies between 1 MHz and 25 MHz. 2. The internal RC Oscillator (IRC) with a fixed frequency of 12 MHz, trimmed to 1% accuracy. 3. The internal low-power, low-frequency Oscillator with a nominal frequency of 10 kHz with 40% accuracy for use with the self wake-up timer. 4. The dedicated Watchdog Oscillator (WDOsc) with a programmable nominal frequency between 9.4 kHz and 2.3 MHz with 40% accuracy. Fig 10. LPC81xM clock generation 􀀶􀀼􀀶􀀷􀀨􀀰􀀃􀀃􀀳􀀯􀀯 􀁚􀁄􀁗􀁆􀁋􀁇􀁒􀁊􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀁚􀁄􀁗􀁆􀁋􀁇􀁒􀁊􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀶􀀼􀀶􀀷􀀨􀀰 􀀲􀀶􀀦􀀬􀀯􀀯􀀤􀀷􀀲􀀵 􀀰􀀤􀀬􀀱􀀦􀀯􀀮􀀶􀀨􀀯 􀀋􀁐􀁄􀁌􀁑􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁖􀁈􀁏􀁈􀁆􀁗􀀌 􀀶􀀼􀀶􀀳􀀯􀀯􀀦􀀯􀀮􀀶􀀨􀀯 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀀳􀀯􀀯􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁖􀁈􀁏􀁈􀁆􀁗 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀶􀀼􀀶􀀤􀀫􀀥􀀦􀀯􀀮􀀧􀀬􀀹 􀀤􀀫􀀥􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀀓 􀀋􀁆􀁒􀁕􀁈􀀏􀀃􀁖􀁜􀁖􀁗􀁈􀁐􀀞􀀃 􀁄􀁏􀁚􀁄􀁜􀁖􀀐􀁒􀁑􀀌 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀸􀀤􀀵􀀷􀀦􀀯􀀮􀀧􀀬􀀹 􀀸􀀶􀀤􀀵􀀷􀀓 􀀸􀀶􀀤􀀵􀀷􀀔 􀀸􀀶􀀤􀀵􀀷􀀕 􀀺􀀺􀀧􀀷 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀺􀀮􀀷 􀁏􀁒􀁚􀀐􀁓􀁒􀁚􀁈􀁕􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀺􀀮􀀷 􀁚􀁄􀁗􀁆􀁋􀁇􀁒􀁊􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀬􀀵􀀦􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁒􀁖􀁆􀁌􀁏􀁏􀁄􀁗􀁒􀁕 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀦􀀯􀀮􀀲􀀸􀀷􀀧􀀬􀀹 􀀦􀀯􀀮􀀲􀀸􀀷􀀃􀁓􀁌􀁑 􀀦􀀯􀀮􀀲􀀸􀀷􀀶􀀨􀀯 􀀋􀀦􀀯􀀮􀀲􀀸􀀷􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁖􀁈􀁏􀁈􀁆􀁗􀀌 􀁐􀁄􀁌􀁑􀀃􀁆􀁏􀁒􀁆􀁎 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎 􀀶􀀼􀀶􀀤􀀫􀀥􀀦􀀯􀀮􀀦􀀷􀀵􀀯􀀾􀀔􀀝􀀔􀀜􀁀 􀀋􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁈􀁑􀁄􀁅􀁏􀁈􀀌 􀁐􀁈􀁐􀁒􀁕􀁌􀁈􀁖 􀁄􀁑􀁇􀀃􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀁖􀀏 􀁓􀁈􀁕􀁌􀁓􀁋􀁈􀁕􀁄􀁏􀀃􀁆􀁏􀁒􀁆􀁎􀁖 􀀔􀀜 􀁄􀁄􀁄􀀐􀀓􀀓􀀘􀀚􀀗􀀜 􀀬􀀲􀀦􀀲􀀱􀀦􀀯􀀮􀀧􀀬􀀹 􀀦􀀯􀀲􀀦􀀮􀀃􀀧􀀬􀀹􀀬􀀧􀀨􀀵 􀀬􀀲􀀦􀀲􀀱􀀃 􀁊􀁏􀁌􀁗􀁆􀁋􀀃􀁉􀁌􀁏􀁗􀁈􀁕 􀀚 􀀻􀀷􀀤􀀯􀀬􀀱 􀀦􀀯􀀮􀀬􀀱 􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀶􀀼􀀶􀀦􀀲􀀱 􀀳􀀰􀀸 􀀩􀀵􀀤􀀦􀀷􀀬􀀲􀀱􀀤􀀯􀀃􀀵􀀤􀀷􀀨 􀀪􀀨􀀱􀀨􀀵􀀤􀀷􀀲􀀵 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 25 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. Following reset, the LPC81xM will operate from the IRC until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 10 for an overview of the LPC81xM clock generation. 8.20.1.1 Internal RC Oscillator (IRC) The IRC may be used as the clock source for the WWDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1.5 % accuracy over the entire voltage and temperature range. The IRC can be used as a clock source for the CPU with or without using the PLL. The IRC frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. Upon power-up or any chip reset, the LPC81xM use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.20.1.2 Crystal Oscillator (SysOsc) The crystal oscillator can be used as the clock source for the CPU, with or without using the PLL. The SysOsc operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 8.20.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc) The nominal frequency of the WDOsc is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over silicon process variations is  40%. The WDOsc is a dedicated oscillator for the windowed WWDT. The internal low-power 10 kHz (  40% accuracy) oscillator serves a the clock input to the WKT. This oscillator can be configured to run in all low power modes. 8.20.2 Clock input An external clock source can be supplied on the selected CLKIN pin. When selecting a clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 9 “Static characteristics” and Table 15 “Dynamic characteristics: I/O pins[1]”. An 1.8 V external clock source can be supplied on the XTALIN pins to the system oscillator limiting the voltage of this signal ((see Section 14.2). The maximum frequency for both clock signals is 25 MHz. 8.20.3 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 26 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is nominally 100 s. 8.20.4 Clock output The LPC81xM features a clock output function that routes the IRC, the SysOsc, the watchdog oscillator, or the main clock to the CLKOUT function. The CLKOUT function can be connected to any digital pin through the switch matrix. 8.20.5 Wake-up process The LPC81xM begin operation at power-up by using the IRC as the clock source. This allows chip operation to resume quickly. If the SysOsc, the external clock source, or the PLL is needed by the application, software must enable these features and wait for them to stabilize before they are used as a clock source. 8.20.6 Power control The LPC81xM supports the ARM Cortex-M0 Sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 8.20.6.1 Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile API. The API is accessible through the on-chip ROM. The power configuration routine configures the LPC81xM for one of the following power modes: • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 8.20.6.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 27 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.20.6.3 Deep-sleep mode In Deep-sleep mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all clock sources are off except for the IRC and watchdog oscillator or low-power oscillator if selected. The IRC output is disabled. In addition all analog blocks are shut down and the flash is in stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC81xM can wake up from Deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Deep-sleep mode saves power and allows for short wake-up times. 8.20.6.4 Power-down mode In Power-down mode, the LPC81xM is in Sleep-mode and all peripheral clocks and all clock sources are off except for watchdog oscillator or low-power oscillator if selected. In addition all analog blocks and the flash are shut down. In Power-down mode, the application can keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. The LPC81xM can wake up from Power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI, or the I2C blocks (in slave mode). Any interrupt used for waking up from Power-down mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Power-down mode reduces power consumption compared to Deep-sleep mode at the expense of longer wake-up times. 8.20.6.5 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin and the self wake-up timer if enabled. Four general-purpose registers are available to store information during Deep power-down mode. The LPC81xM can wake up from Deep power-down mode via the WAKEUP pin, or without an external signal by using the time-out of the self wake-up timer (see Section 8.18). The LPC81xM can be prevented from entering Deep power-down mode by setting a lock bit in the PMU block. Locking out Deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 28 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 8.21 System control 8.21.1 Reset Reset has four sources on the LPC81xM: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. In Deep power-down mode, an external pull-up resistor is required on the RESET pin. 8.21.2 Brownout detection The LPC81xM includes up to four levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. Fig 11. Reset pad configuration 􀀹􀀶􀀶 􀁕􀁈􀁖􀁈􀁗 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀔􀀖 􀀹􀀧􀀧 􀀹􀀧􀀧 􀀹􀀧􀀧 􀀵􀁓􀁘 􀀨􀀶􀀧 􀀨􀀶􀀧 􀀕􀀓􀀃􀁑􀁖􀀃􀀵􀀦 􀀪􀀯􀀬􀀷􀀦􀀫􀀃􀀩􀀬􀀯􀀷􀀨􀀵 􀀳􀀬􀀱 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 29 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.21.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For details, see the LPC800 user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using the ISP entry pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can be disabled. For details, see the LPC800 user manual. 8.21.4 APB interface The APB peripherals are located on one APB bus. 8.21.5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0+ to the flash memory, the main static RAM, the CRC, and the ROM. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 30 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 8.22 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC81xM. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the LPC81xM is in reset. The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode on pins PIO0_0 to PIO0_3 (see Table 4). To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. Fig 12. Connecting the SWD pins to a standard SWD connector 􀀵􀀨􀀶􀀨􀀷 􀀶􀀺􀀧􀀬􀀲 􀀶􀀺􀀦􀀯􀀮 􀀹􀀧􀀧 􀀯􀀳􀀦􀀛􀀓􀀓 􀀬􀀶􀀳􀀃􀁈􀁑􀁗􀁕􀁜 􀀳􀀬􀀲􀀓􀁂􀀔􀀕􀀃 􀀃􀀃 􀀹􀀷􀀵􀀨􀀩 􀀶􀀺􀀧􀀬􀀲 􀀶􀀺􀀦􀀯􀀮 􀁑􀀵􀀨􀀶􀀨􀀷 􀀪􀀱􀀧 􀁄􀁄􀁄􀀐􀀓􀀓􀀙􀀓􀀛􀀙 􀁉􀁕􀁒􀁐􀀃􀀶􀀺􀀧 􀁆􀁒􀁑􀁑􀁈􀁆􀁗􀁒􀁕 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 31 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended and proper operation is not guaranteed. The conditions for functional operation are specified in Table 9. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 9) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Including voltage on outputs in tri-state mode. Does not apply to pin PIO0_6. [4] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [5] VDD present or not present. [6] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below VDD without affecting the hysteresis range of the comparator function. [7] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [8] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [9] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD supply voltage (core and external rail) [2] 0.5 +4.6 V VI input voltage 5 V tolerant I/O pins; VDD  1.8 V [3] 0.5 +5.5 V 5 V tolerant open-drain pins PIO0_10 and PIO0_11 [4] 0.5 +5.5 V 3 V tolerant I/O pin PIO0_6 [5] 0.5 +3.6 V VIA analog input voltage [6] [7] 0.5 4.6 V Vi(xtal) crystal input voltage [2] 0.5 +2.5 V IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); Tj < 125 C - 100 mA Tstg storage temperature non-operating [8] 65 +150 C Tj(max) maximum junction temperature - 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [9] - 5500 V charged device model; TSSOP20 and SOP20 packages - 1200 V charged device model; TSSOP16 package - 1000 V charged device model; XSON16 package - 800 V LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 32 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 8. Thermal resistance Symbol Parameter Conditions Max/Min Unit DIP8 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 60 ± 15 % C/W Single-layer (4.5 in  3 in); still air 81 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 38 ± 15 % C/W TSSOP16 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 133 ± 15 % C/W Single-layer (4.5 in  3 in); still air 182 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 33 ± 15 % C/W TSSOP20 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 110 ± 15 % C/W Single-layer (4.5 in  3 in); still air 153 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 23 ± 15 % C/W SO20 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 87 ± 15 % C/W Single-layer (4.5 in  3 in); still air 112 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 50 ± 15 % C/W XSON16 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 92 ± 15 % C/W Single-layer (4.5 in  3 in); still air 180 ± 15 % C/W Rth(j-c) thermal resistance from junction to case 27 ± 15 % C/W Tj = Tamb + PD  Rthj – a LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 33 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11. Static characteristics Table 9. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD supply voltage (core and external rail) 1.8 3.3 3.6 V IDD supply current Active mode; code while(1){} executed from flash; system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4][5]- 1.4 - mA system clock = 12 MHz; low-current mode; VDD = 3.3 V [2][3][4][5] [6] - 1.0 - mA system clock = 24 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [7] - 2.2 - mA system clock = 30 MHz; default mode; VDD = 3.3 V [2][4][5][8]- 3.3 - mA system clock = 30 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [8] - 3 - mA Sleep mode system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4][5]- 0.8 - mA system clock = 12 MHz; low-current mode; VDD = 3.3 V [2][3][4][5] [6] - 0.7 - mA system clock = 24 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [7] - 1.3 - mA system clock = 30 MHz; default mode; VDD = 3.3 V [2][4][5][8]- 1.8 - mA system clock = 30 MHz; low-current mode; VDD = 3.3 V [2][4][5][6] [8] - 1.7 - mA Deep-sleep mode VDD = 3.3 V, Tamb = 25 °C [2][9] - 150 300 A VDD = 3.3 V, Tamb = 105 °C [2][9] - - 400 A Power-down mode VDD = 3.3 V, Tamb = 25 °C [2][9]- 0.9 5 A VDD = 3.3 V, Tamb = 105 °C [2][9]- - 40 A Deep power-down mode; Low-power oscillator and self wakeup timer (WKT) disabled VDD = 3.3 V, Tamb = 25 °C [10] - 170 1000 nA VDD = 3.3 V, Tamb = 105 °C [10] - - 4 A Deep power-down mode; Low-power oscillator and self wakeup timer (WKT) enabled - 1 - A LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 34 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Standard port pins configured as digital pins, RESET; see Figure 13 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage VDD  1.8 V; 5 V tolerant pins except PIO0_6 [11] [12] 0 - 5.0 V VDD  1.8 V; on 3 V tolerant pin PIO0_6 0 - 3.6 VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 4 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 3 mA VDD  0.4 - - V VOL LOW-level output voltage 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.5 V 3 - - mA IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.5 V 3 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [13] - - 45 mA IOLS LOW-level short-circuit output current VOL = VDD [13] - - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V; 2.0 V  VDD  3.6 V 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A High-drive output pins configured as digital pins (PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13); see Figure 13 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10 nA Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 35 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller VI input voltage VDD  1.8 V [11] [12] 0 - 5.0 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V  VDD  3.6 V; IOH = 20 mA VDD  0.4 - - V 1.8 V  VDD < 2.5 V; IOH = 12 mA VDD  0.4 - - V VOL LOW-level output voltage 2.5 V  VDD  3.6 V; IOL = 4 mA - - 0.4 V 1.8 V  VDD < 2.5 V; IOL = 3 mA - - 0.4 V IOH HIGH-level output current VOH = VDD  0.4 V; 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 12 - - mA IOL LOW-level output current VOL = 0.4 V 2.5 V  VDD  3.6 V 4 - - mA 1.8 V  VDD < 2.5 V 3 - - mA IOLS LOW-level short-circuit output current VOL = VDD [13] - - 50 mA Ipd pull-down current VI = 5 V [14] 10 50 150 A Ipu pull-up current VI = 0 V 2.0 V  VDD  3.6 V [14] 15 50 85 A 1.8 V  VDD < 2.0 V 10 50 85 A VDD < VI < 5 V 0 0 0 A I2C-bus pins (PIO0_10 and PIO0_11); see Figure 13 VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as standard mode pins 2.5 V  VDD  3.6 V 3.5 - - mA 1.8 V  VDD < 2.5 V 3 - - IOL LOW-level output current VOL = 0.4 V; I2C-bus pins configured as Fast-mode Plus pins 2.5 V  VDD  3.6 V 20 - - mA 1.8 V  VDD < 2.5 V 16 - - ILI input leakage current VI = VDD [15]- 2 4 A VI = 5 V - 10 22 A Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 36 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [3] IRC enabled; system oscillator disabled; system PLL disabled. [4] BOD disabled. [5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system configuration block. [6] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [7] IRC enabled; system oscillator disabled; system PLL enabled. [8] IRC disabled; system oscillator enabled; system PLL enabled. [9] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [10] WAKEUP pin pulled HIGH externally. [11] Including voltage on outputs in tri-state mode. [12] 3-state outputs go into tri-state mode in Deep power-down mode. [13] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [14] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 8. [15] To VSS. Oscillator input pins (PIO0_8 and PIO0_9) Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Fig 13. Pin input/output current measurement 􀀯􀀳􀀦􀀛􀀓􀀓 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀓 􀀎 􀀐 􀁓􀁌􀁑􀀃􀀳􀀬􀀲􀀓􀁂􀁑 􀀬􀀲􀀫 􀀬􀁓􀁘 􀀐 􀀎 􀁓􀁌􀁑􀀃􀀳􀀬􀀲􀀓􀁂􀁑 􀀬􀀲􀀯 􀀬􀁓􀁇 􀀹􀀧􀀧 􀀤 􀀤 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 37 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.1 Power consumption Power measurements in Active, Sleep, Deep-sleep,and Power-down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 14. Active mode: Typical supply current IDD versus supply voltage VDD 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀗 􀀔􀀑􀀛 􀀕􀀑􀀔􀀙 􀀕􀀑􀀘􀀕 􀀕􀀑􀀛􀀛 􀀖􀀑􀀕􀀗 􀀖􀀑􀀙 􀀓 􀀓􀀑􀀙 􀀔􀀑􀀕 􀀔􀀑􀀛 􀀕􀀑􀀗 􀀖 􀀹􀀧􀀧􀀃􀀋􀀹􀀌 􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀓􀀓􀀓􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀙􀀙􀀙􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀖􀀖􀀖􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 38 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 15. Active mode: Typical supply current IDD versus temperature 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀖 􀀐􀀗􀀓 􀀐􀀔􀀔 􀀔􀀛 􀀗􀀚 􀀚􀀙 􀀔􀀓􀀘 􀀓 􀀓􀀑􀀙 􀀔􀀑􀀕 􀀔􀀑􀀛 􀀕􀀑􀀗 􀀖 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀓􀀓􀀓􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀙􀀙􀀙􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀖􀀖􀀖􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 39 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 16. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀘 􀀐􀀗􀀓 􀀐􀀔􀀔 􀀔􀀛 􀀗􀀚 􀀚􀀙 􀀔􀀓􀀘 􀀓 􀀓􀀑􀀗 􀀓􀀑􀀛 􀀔􀀑􀀕 􀀔􀀑􀀙 􀀕 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀓􀀓􀀓􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀙􀀙􀀙􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀗􀀗􀀗􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀖􀀖􀀖􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀕􀀕􀀕􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀀔􀀔􀀔􀀃􀀃􀀃􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀙􀀗 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀔􀀓􀀓 􀀔􀀕􀀓 􀀔􀀗􀀓 􀀔􀀙􀀓 􀀔􀀛􀀓 􀀕􀀓􀀓 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀃􀀦􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀈝􀈝􀈝􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀓􀀓􀀓􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 40 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 18. Power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD WKT not running. Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀙􀀖 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀓 􀀚 􀀔􀀗 􀀕􀀔 􀀕􀀛 􀀖􀀘 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀃􀀦􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀈝􀈝􀈝􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀙􀀕 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀓 􀀓􀀑􀀘 􀀔 􀀔􀀑􀀘 􀀕 􀀕􀀑􀀘 􀀖 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀃􀀦􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀈝􀈝􀈝􀀤􀀤􀀤􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀓􀀓􀀓􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 41 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.2 CoreMark data Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7. Fig 20. Active mode: CoreMark power consumption IDD Conditions: VDD = 3.3 V; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7. Fig 21. CoreMark score 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀙 􀀓 􀀗 􀀛 􀀔􀀕 􀀔􀀙 􀀕􀀓 􀀕􀀗 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁉􀁕􀁈􀁔􀁘􀁈􀁑􀁆􀁜􀀃􀀋􀀰􀀫􀁝􀀌 􀀬􀀬􀀬􀀧􀀧􀀧􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀧􀀧􀀧􀁈􀁈􀁈􀁉􀁉􀁉􀁄􀁄􀁄􀁘􀁘􀁘􀁏􀁏􀁏􀁗􀁗􀁗 􀀦􀀦􀀦􀀳􀀳􀀳􀀸􀀸􀀸􀀒􀀒􀀒􀁈􀁈􀁈􀁉􀁉􀁉􀁉􀁉􀁉􀁌􀁌􀁌􀁆􀁆􀁆􀁌􀁌􀁌􀁈􀁈􀁈􀁑􀁑􀁑􀁆􀁆􀁆􀁜􀁜􀁜 􀀯􀀯􀀯􀁒􀁒􀁒􀁚􀁚􀁚􀀐􀀐􀀐􀁆􀁆􀁆􀁘􀁘􀁘􀁕􀁕􀁕􀁕􀁕􀁕􀁈􀁈􀁈􀁑􀁑􀁑􀁗􀁗􀁗 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀛􀀚 􀀓 􀀗 􀀛 􀀔􀀕 􀀔􀀙 􀀕􀀓 􀀕􀀗 􀀓 􀀓􀀑􀀘 􀀔 􀀔􀀑􀀘 􀀕 􀀕􀀑􀀘 􀁖􀁜􀁖􀁗􀁈􀁐􀀃􀁆􀁏􀁒􀁆􀁎􀀃􀁉􀁕􀁈􀁔􀁘􀁈􀁑􀁆􀁜􀀃􀀋􀀰􀀫􀁝􀀌 􀀋􀀋􀁐􀁐􀀤􀀤􀀌􀀌 􀀧􀀧􀀧􀁈􀁈􀁈􀁉􀁉􀁉􀁄􀁄􀁄􀁘􀁘􀁘􀁏􀁏􀁏􀁗􀁗􀁗 􀀦􀀦􀀦􀀳􀀳􀀳􀀸􀀸􀀸􀀒􀀒􀀒􀁈􀁈􀁈􀁉􀁉􀁉􀁉􀁉􀁉􀁌􀁌􀁌􀁆􀁆􀁆􀁌􀁌􀁌􀁈􀁈􀁈􀁑􀁑􀁑􀁆􀁆􀁆􀁜􀁜􀁜 􀀯􀀯􀀯􀁒􀁒􀁒􀁚􀁚􀁚􀀐􀀐􀀐􀁆􀁆􀁆􀁘􀁘􀁘􀁕􀁕􀁕􀁕􀁕􀁕􀁈􀁈􀁈􀁑􀁑􀁑􀁗􀁗􀁗 􀀦􀀰 􀀋􀀋􀁌􀁗􀁈􀁕􀁄􀁗􀁌􀁒􀁑􀁖􀀒􀁖􀀌􀀒􀀰􀀫􀁝􀀌􀀌 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 42 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C. Unless noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 30 MHz. Table 10. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA Notes n/a 12 MHz 30 MHz IRC 0.21 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator at 12 MHz 0.28 - - IRC running; PLL off; independent of main clock frequency. Watchdog oscillator at 500 kHz/2 0.002 - - System oscillator running; PLL off; independent of main clock frequency. BOD 0.05 - - Independent of main clock frequency. Main PLL - 0.31 - - CLKOUT - 0.06 0.09 Main clock divided by 4 in the CLKOUTDIV register. ROM - 0.08 0.19 - I2C - 0.06 0.15 - GPIO + pin interrupt/pattern match - 0.09 0.23 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. SWM - 0.03 0.07 - SCT - 0.17 0.42 - WKT - 0.01 0.03 - MRT - 0.09 0.21 - SPI0 - 0.05 0.13 - SPI1 - 0.06 0.14 - CRC - 0.03 0.07 - USART0 - 0.04 0.10 - USART1 - 0.04 0.11 - USART2 - 0.04 0.10 - WWDT - 0.04 0.10 Main clock selected as clock source for the WDT. IOCON - 0.03 0.08 - Comparator - 0.04 0.09 - LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 43 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 11.4 Electrical pin characteristics Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13. Fig 22. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_10 and PIO0_11. Fig 23. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus LOW-level output voltage VOL 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀙􀀓 􀀓 􀀔􀀓 􀀕􀀓 􀀖􀀓 􀀗􀀓 􀀘􀀓 􀀙􀀓 􀀚􀀓 􀀛􀀓 􀀔􀀑􀀕 􀀔􀀑􀀙 􀀕 􀀕􀀑􀀗 􀀕􀀑􀀛 􀀖􀀑􀀕 􀀖􀀑􀀙 􀀬􀀲􀀫􀀃􀀋􀁐􀀤􀀌 􀀹􀀹􀀹􀀲􀀲􀀲􀀫􀀫􀀫 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀁙􀁙 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀁙􀁙 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀘􀀜 􀀓 􀀓􀀑􀀔 􀀓􀀑􀀕 􀀓􀀑􀀖 􀀓􀀑􀀗 􀀓􀀑􀀘 􀀓􀀑􀀙 􀀓 􀀔􀀘 􀀖􀀓 􀀗􀀘 􀀙􀀓 􀀹􀀲􀀯􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀀲􀀲􀀲􀀯􀀯􀀯 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂃􀀢􀀢􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 44 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins and high-drive pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13. Fig 24. Typical LOW-level output current IOL versus LOW-level output voltage VOL Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 25. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀘􀀛 􀀓 􀀓􀀑􀀔 􀀓􀀑􀀕 􀀓􀀑􀀖 􀀓􀀑􀀗 􀀓􀀑􀀘 􀀓􀀑􀀙 􀀓 􀀖 􀀙 􀀜 􀀔􀀕 􀀔􀀘 􀀹􀀲􀀯􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀀲􀀲􀀲􀀯􀀯􀀯 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀃􀀃􀀃􀀔􀀖􀀖􀀑􀀑􀀑􀀛􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀚􀀜􀀖 􀀓 􀀖 􀀙 􀀜 􀀔􀀕 􀀔􀀘 􀀔􀀛 􀀕􀀔 􀀔􀀑􀀕 􀀔􀀑􀀙 􀀕 􀀕􀀑􀀗 􀀕􀀑􀀛 􀀖􀀑􀀕 􀀖􀀑􀀙 􀀬􀀲􀀫􀀃􀀋􀁐􀀤􀀌 􀀹􀀹􀀹􀀲􀀲􀀲􀀫􀀫􀀫 􀀋􀀋􀀋􀀹􀀹􀀹􀀌􀀌􀀌 􀀹􀀧􀀧􀀃􀀠􀀃􀀖􀀑􀀖􀀃􀀹􀀞 􀀷􀀃􀀠􀀃􀀃􀀐􀀗􀀓􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀕􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀛􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀔􀀓􀀘􀀃􀂃􀀦 􀀹􀀧􀀧􀀃􀀠􀀃􀀔􀀑􀀛􀀃􀀹􀀞 􀀷􀀃􀀠􀀃􀀃􀀐􀀗􀀓􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀕􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀛􀀘􀀃􀂃􀀦 􀀷􀀃􀀠􀀃􀀔􀀓􀀘􀀃􀂃􀀦 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 45 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 26. Typical pull-up current Ipu versus input voltage VI Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 27. Typical pull-down current Ipd versus input voltage VI 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀛􀀙 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀀐􀀓􀀑􀀓􀀚 􀀐􀀓􀀑􀀓􀀙 􀀐􀀓􀀑􀀓􀀗 􀀐􀀓􀀑􀀓􀀖 􀀐􀀓􀀑􀀓􀀕 􀀓 􀀓􀀑􀀓􀀔 􀀹􀀬􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀁓􀁓􀁓􀁘􀁘􀁘 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀜􀀜􀀜􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀜􀀜􀀜􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦 􀀹􀀧􀀧􀀃􀀠􀀃􀀔􀀑􀀛􀀃􀀹 􀀹􀀧􀀧􀀃􀀠􀀃􀀖􀀑􀀖􀀃􀀹 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀛􀀙􀀔 􀀓 􀀔 􀀕 􀀖 􀀗 􀀘 􀀓 􀀓􀀑􀀓􀀕 􀀓􀀑􀀓􀀗 􀀓􀀑􀀓􀀙 􀀓􀀑􀀓􀀛 􀀹􀀬􀀃􀀋􀀹􀀌 􀀬􀀬􀀬􀀳􀀳􀀳􀀧􀀧􀀧 􀀋􀀋􀀋􀁐􀁐􀁐􀀤􀀤􀀤􀀌􀀌􀀌 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀐􀀐􀀐􀀗􀀗􀀗􀀓􀀓􀀓􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀛􀀛􀀛􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀓􀀓􀀓􀀘􀀘􀀘􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀀃􀂡􀀀􀀀􀀦􀀦􀀦􀀒􀀒􀀒􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 46 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12. Dynamic characteristics 12.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 64 bytes to the flash. Tamb  +85 C. Flash programming with IAP calls (see LPC800 user manual). 12.2 External clock for the oscillator in slave mode Remark: The input voltage on the XTAL1/2 pins must be  1.95 V (see Table 9). For connecting the oscillator to the XTAL pins, also see Section 14.2. [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. Table 11. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 20 - years unpowered 20 40 - years ter erase time page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 12. Dynamic characteristic: external clock (XTALIN inputs) Tamb = 40 C to +105 C; VDD over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Fig 28. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) 􀁗􀀦􀀫􀀦􀀯 􀁗􀀦􀀯􀀦􀀻 􀁗􀀦􀀫􀀦􀀻 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀀦􀀯􀀦􀀫 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀛 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 47 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. [3] See the LPC81xM user manual. Table 13. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency Tamb = 40 C to +105 C 11.82 12 12.18 MHz Conditions: Frequency values are typical values. 12 MHz  1.5 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb = 40 C to +105 C. Variations between parts may cause the IRC to fall outside the 12 MHz  1.5 % accuracy specification for voltages below 2.7 V. Fig 29. Typical Internal RC oscillator frequency versus temperature Table 14. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions Min Typ[1] Max Unit fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; [2][3]- 9.4 - kHz DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register [2][3] - 2300 - kHz 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀚􀀘 􀀐􀀗􀀓 􀀐􀀔􀀓 􀀕􀀓 􀀘􀀓 􀀛􀀓 􀀔􀀔􀀓 􀀔􀀔􀀑􀀛􀀛 􀀔􀀔􀀑􀀜􀀕 􀀔􀀔􀀑􀀜􀀙 􀀔􀀕 􀀔􀀕􀀑􀀓􀀗 􀀔􀀕􀀑􀀓􀀛 􀀔􀀕􀀑􀀔􀀕 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀁉 􀀋􀀋􀀋􀀰􀀰􀀰􀀫􀀫􀀫􀁝􀁝􀁝􀀌􀀌􀀌 􀀖􀀖􀀖􀀑􀀑􀀑􀀙􀀙􀀙􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀖􀀖􀀖􀀃􀀃􀀃􀀹􀀹􀀹 􀀖􀀖􀀖􀀑􀀑􀀑􀀓􀀓􀀓􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀑􀀑􀀑􀀚􀀚􀀚􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀑􀀑􀀑􀀗􀀗􀀗􀀃􀀃􀀃􀀹􀀹􀀹 􀀕􀀕􀀕􀀑􀀑􀀑􀀔􀀔􀀔􀀃􀀃􀀃􀀹􀀹􀀹 􀀔􀀔􀀔􀀑􀀑􀀑􀀛􀀛􀀛􀀃􀀃􀀃􀀹􀀹􀀹 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 48 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.4 I/O pins [1] Applies to standard port pins and RESET pin. 12.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. Table 15. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus; on pins PIO0_10 and PIO0_11 0 1 MHz tf fall time [4][5][6][7] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus; on pins PIO0_10 and PIO0_11 - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0.26 - s tHD;DAT data hold time [3][4][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus; on pins PIO0_10 and PIO0_11 50 - ns LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 49 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF. [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Fig 30. I2C-bus pins clock timing 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀖 􀁗􀁉 􀀚􀀓􀀃􀀈 􀀶􀀧􀀤 􀀖􀀓􀀃􀀈 􀁗􀁉 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀀶 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀁗􀀫􀀧􀀞􀀧􀀤􀀷 􀀶􀀦􀀯 􀀔􀀃􀀒􀀃􀁉􀀶􀀦􀀯 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀀚􀀓􀀃􀀈 􀀖􀀓􀀃􀀈 􀁗􀀹􀀧􀀞􀀧􀀤􀀷 􀁗􀀫􀀬􀀪􀀫 􀁗􀀯􀀲􀀺 􀁗􀀶􀀸􀀞􀀧􀀤􀀷 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 50 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.6 SPI interfaces The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode. Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. [1] Capacitance on pin SPIn_SCK CSCK < 5 pF. [2] Tcy(clk) = DIVVAL/CCLK with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC800 User manual UM10601. Table 17. SPI dynamic characteristics Tamb = 40 C to 105 C; 1.8 V  VDD  3.6 V. Simulated parameters sampled at the 50 % level of the rising or falling edge; values guaranteed by design. Symbol Parameter Conditions Min Max Unit SPI master[1] Tcy(clk) clock cycle time [2] 33 - ns tDS data set-up time 0 - ns tDH data hold time 16 - ns tv(Q) data output valid time CL = 10 pF - 0.5 ns th(Q) data output hold time CL = 10 pF 0.5 - ns SPI slave Tcy(clk) 40 ns tDS data set-up time 0 - ns tDH data hold time 16 - ns tv(Q) data output valid time CL = 10 pF - 10 ns th(Q) data output hold time CL = 10 pF 10 - ns LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 51 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 31. SPI master timing 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀓􀀌 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀀧􀀶 􀁗􀀧􀀫 􀁗􀁙􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀔􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀁗􀀧􀀶 􀁗􀀧􀀫 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁙􀀋􀀴􀀌 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀔 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀓 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀗 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 52 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 32. SPI slave timing 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀓􀀌 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀀧􀀶 􀁗􀀧􀀫 􀁗􀁙􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀶􀀦􀀮􀀃􀀋􀀦􀀳􀀲􀀯􀀃􀀠􀀃􀀔􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀰􀀲􀀶􀀬 􀀰􀀬􀀶􀀲 􀁗􀀧􀀶 􀁗􀀧􀀫 􀁗􀁙􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀁗􀁋􀀋􀀴􀀌 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀧􀀤􀀷􀀤􀀃􀀹􀀤􀀯􀀬􀀧 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀔 􀀦􀀳􀀫􀀤􀀃􀀠􀀃􀀓 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀘 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 53 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 12.7 USART interface The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode slave and master mode. Remark: USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V, typical samples. [2] Tcy(clk) = U_PCLK/BRGVAL. See the LPC800 User manual UM10601. [3] Capacitance on pin Un_SCLK CSCLK < 5 pF. Table 18. USART dynamic characteristics Tamb = 40 C to 105 C; 1.8 V  VDD  3.6 V. Simulated parameters sampled at the 50 % level of the falling or rising edge; values guaranteed by design. Symbol Parameter Conditions Min Max Unit Tcy(clk) clock cycle time [2] 100 - ns USART master (in synchronous mode)[3] tsu(D) data input set-up time 44 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time - -8 ns th(Q) data output hold time -8 - ns USART slave (in synchronous mode) tsu(D) data input set-up time 5 - ns th(D) data input hold time 0 - ns tv(Q) data output valid time CL = 10 pF - 40 ns th(Q) data output hold time CL = 10 pF 40 - ns Fig 33. USART timing 􀀸􀁑􀁂􀀶􀀦􀀯􀀮􀀃􀀋􀀦􀀯􀀮􀀳􀀲􀀯􀀃􀀠􀀃􀀓􀀌 􀀷􀀻􀀧 􀀵􀀻􀀧 􀀷􀁆􀁜􀀋􀁆􀁏􀁎􀀌 􀁗􀁖􀁘􀀋􀀧􀀌 􀁗􀁋􀀋􀀧􀀌 􀁗􀁙􀀋􀀴􀀌 􀀶􀀷􀀤􀀵􀀷 􀀥􀀬􀀷􀀓 􀁗􀁋􀀋􀀴􀀌 􀀸􀁑􀁂􀀶􀀦􀀯􀀮􀀃􀀋􀀦􀀯􀀮􀀳􀀲􀀯􀀃􀀠􀀃􀀔􀀌 􀀶􀀷􀀤􀀵􀀷 􀀥􀀬􀀷􀀓 􀀥􀀬􀀷􀀔 􀀥􀀬􀀷􀀔 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀓􀀓􀀔 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 54 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 13. Analog characteristics 13.1 BOD [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL. [2] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V, typical samples. 13.2 Internal voltage reference [1] Characterized through simulation. [2] Characterized on a typical silicon sample. Table 19. BOD static characteristics[1] Tamb = 40 C to +105 C. Symbol Parameter Conditions Typ[2] Unit Vth threshold voltage interrupt level 1 assertion 2.3 V de-assertion 2.4 V interrupt level 2 assertion 2.6 V de-assertion 2.7 V interrupt level 3 assertion 2.8 V de-assertion 2.9 V reset level 1 assertion 2.1 V de-assertion 2.2 V reset level 2 assertion 2.4 V de-assertion 2.5 V reset level 3 assertion 2.6 V de-assertion 2.8 V Table 20. Internal voltage reference static and dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit VO output voltage Tamb = 40 C to +105 C [1] 0.855 0.900 0.945 V Tamb = 70 C to 105 C [2] - 0.906 - V Tamb = 50 C [2] - 0.905 - V Tamb = 25 C [4] 0.893 0.903 0.913 V Tamb = 0 C [2] - 0.902 - V Tamb = 20 C [2] - 0.899 - V Tamb = 40 C [2] - 0.896 - V ts(pu) power-up settling time to 99% of VO [3] - 155 195 s LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 55 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [3] Typical values are derived from nominal simulation (VDD = 3.3 V; Tamb = 27 C; nominal process models). Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process models). [4] Maximum and minimum values are measured on samples from the corners of the process matrix lot. 13.3 Comparator VDD = 3.3 V Fig 34. Typical internal voltage reference output voltage 􀁄􀁄􀁄􀀐􀀓􀀓􀀚􀀜􀀔􀀖 􀀐􀀗􀀓 􀀐􀀔􀀘 􀀔􀀓 􀀖􀀘 􀀙􀀓 􀀛􀀘 􀀔􀀔􀀓 􀀛􀀜􀀓 􀀛􀀜􀀘 􀀜􀀓􀀓 􀀜􀀓􀀘 􀀜􀀔􀀓 􀁗􀁈􀁐􀁓􀁈􀁕􀁄􀁗􀁘􀁕􀁈􀀃􀀋􀂃􀀦􀀌 􀀹􀀹􀀹􀀲􀀲􀀲 􀀋􀀋􀀋􀁐􀁐􀁐􀀹􀀹􀀹􀀌􀀌􀀌 Table 21. Comparator characteristics VDD = 3.0 V and Tamb = 27 C unless noted otherwise. Symbol Parameter Conditions Min Typ Max Unit Static characteristics Vref(cmp) comparator reference voltage pin PIO0_6/VDDCMP configured for function VDDCMP 1.5 - 3.6 V IDD supply current - 55 - A VIC common-mode input voltage 0 - VDD V DVO output voltage variation 0 - VDD V Voffset offset voltage VIC = 0.1 V - 1.9 - mV VIC = 1.5 V - 2.1 - mV VIC = 2.8 V - 2.0 mV Dynamic characteristics tstartup start-up time nominal process - 4 - s LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 56 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] CL = 10 pF; results from measurements on silicon samples over process corners and over the full temperature range Tamb = 40 C to +105 C. Typical data are for Tamb = 27 C. [2] Input hysteresis is relative to the reference input channel and is software programmable to three levels. [1] Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process models). [2] Settling time applies to switching between comparator channels. tPD propagation delay HIGH to LOW; VDD = 3.0 V; VIC = 0.1 V; 50 mV overdrive input [1] - 109 121 ns VIC = 0.1 V; rail-to-rail input [1] - 155 164 ns VIC = 1.5 V; 50 mV overdrive input [1] - 95 105 ns VIC = 1.5 V; rail-to-rail input [1] - 101 108 ns VIC = 2.9 V; 50 mV overdrive input [1] - 122 129 ns VIC = 2.9 V; rail-to-rail input [1] - 74 82 ns tPD propagation delay LOW to HIGH; VDD = 3.0 V; VIC = 0.1 V; 50 mV overdrive input [1] - 246 260 ns VIC = 0.1 V; rail-to-rail input [1] - 57 59 ns VIC = 1.5 V; 50 mV overdrive input [1] - 218 ns VIC = 1.5 V; rail-to-rail input [1] - 146 155 ns VIC = 2.9 V; 50 mV overdrive input [1] - 184 206 ns VIC = 2.9 V; rail-to-rail input [1] - 250 286 ns Vhys hysteresis voltage positive hysteresis; VDD = 3.0 V; VIC = 1.5 V [2] - 6, 11, 21 - mV Vhys hysteresis voltage negative hysteresis; VDD = 3.0 V; VIC = 1.5 V [2][2] - 4, 9, 19 - mV Rlad ladder resistance - - 1.034 - M Table 21. Comparator characteristics …continued VDD = 3.0 V and Tamb = 27 C unless noted otherwise. Symbol Parameter Conditions Min Typ Max Unit Table 22. Comparator voltage ladder dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit ts(pu) power-up settling time to 99% of voltage ladder output value [1]- - 30 s ts(sw) switching settling time to 99% of voltage ladder output value [1] [2] - - 15 s LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 57 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller [1] Measured over a polyresistor matrix lot with a 2 kHz input signal and overdrive < 100 V. [2] All peripherals except comparator and IRC turned off. Table 23. Comparator voltage ladder reference static characteristics VDD = 3.3 V; Tamb = 40 C to + 105C. Symbol Parameter Conditions Min Typ Max[1] Unit EV(O) output voltage error Internal VDD supply decimal code = 00 [2]- 0 0 % decimal code = 08 - 0 0.4 % decimal code = 16 - 0.2 0.2 % decimal code = 24 - 0.2 0.2 % decimal code = 30 - 0.1 0.1 % decimal code = 31 - 0.1 0.1 % EV(O) output voltage error External VDDCMP supply decimal code = 00 - 0 0 % decimal code = 08 - 0.1 0.5 % decimal code = 16 - 0.2 0.4 % decimal code = 24 - 0.2 0.3 % decimal code = 30 - 0.2 0.2 % decimal code = 31 - 0.1 0.1 % LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 58 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 14. Application information 14.1 Typical wake-up times [1] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR) wake-up handler. [2] IRC enabled, all peripherals off. [3] Watchdog oscillator disabled, Brown-Out Detect (BOD) disabled. [4] Self wakeup-timer disabled. Wake-up from deep power-down causes the LPC800 to go through entire reset process. The wake-up time measured is the time between when a wake-up pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the reset handler. 14.2 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 35), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 36 and in Table 25 and Table 26. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and Table 24. Typical wake-up times (3.3 V, Temp = 25 °C) Power modes VDD current Wake-up time Sleep mode (12 MHz)[1][2] 0.7 mA 2.6 s Deep-sleep mode[1][3] 150 A 4 s Power-down mode[1][3] 0.9 A 50 s Deep Power-down mode[4] 170 nA 215 s Fig 35. Slave mode operation of the on-chip oscillator 􀀯􀀳􀀦􀀛􀀓􀀓 􀀻􀀷􀀤􀀯􀀬􀀱 􀀦􀁌 􀀔􀀓􀀓􀀃􀁓􀀩 􀀦􀁊 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀙 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 59 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller RS). Capacitance CP in Figure 36 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 25). Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 25. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 26. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters) high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 􀁄􀁄􀁄􀀐􀀓􀀓􀀗􀀙􀀗􀀚 􀀯􀀳􀀦􀀛􀀓􀀓 􀀻􀀷􀀤􀀯􀀬􀀱 􀀻􀀷􀀤􀀯􀀲􀀸􀀷 􀀦􀀻􀀔 􀀦􀀻􀀕 􀀻􀀷􀀤􀀯 􀀠 􀀦􀀯 􀀦􀀳 􀀵􀀶 􀀯 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 60 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 14.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 61 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 15. Package outline Fig 37. Package outline SOT097-2 (DIP8) Outline References version European projection Issue date IEC JEDEC JEITA SOT97-2 MO-001 sot097-2_po 10-10-15 10-10-18 Unit(1) mm max nom min 4.2 0.51 0.53 0.38 1.07 0.89 0.38 0.20 6.48 6.20 9.8 9.2 2.54 7.62 A Dimensions (inch dimensions are derived from the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-2 A1 b 1.73 1.14 b1 b2 c D(1) E(1) e e1 L ME MH w 0.254 Z(1) 1.15 inches max nom min 0.17 0.02 3.43 A2 0.14 0.021 0.015 0.042 0.035 0.015 0.008 9.40 7.88 0.37 0.31 7.88 7.62 0.31 0.30 0.26 0.24 0.39 0.36 3.60 3.05 0.14 0.12 0.1 0.3 0.068 0.045 0.01 0.045 0 2.5 5 mm scale Z e w b1 D seating plane A2 A1 A L pin 1 index b b2 E 1 4 8 5 (e1) MH ME c - - - - - - LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 62 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 38. Package outline SOT403-1 (TSSOP16) UNIT A1 A2 A3 bp c D(1) E (2) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o 1 0.2 0.13 0.1 o DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT403-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 1 8 16 9 θ A A1 A2 Lp Q detail X L (A 3 ) HE E c v M A X A y 0 2.5 5 mm scale TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 A max. 1.1 pin 1 index LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 63 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 39. Package outline SOT163-1 (SO20) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT163-1 10 20 w M bp detail X Z e 11 1 D y 0.25 075E04 MS-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale X θ A A1 A2 HE Lp Q E c L v M A (A 3 ) A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 99-12-27 03-02-19 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 64 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 40. Package outline SOT360-1 (TSSOP20) UNIT A1 A2 A3 bp c D(1) E (2) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o 1 0.2 0.13 0.1 o DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT360-1 MO-153 99-12-27 03-02-19 w M bp D Z e 0.25 1 10 20 11 pin 1 index θ A A1 A2 Lp Q detail X L (A 3 ) HE E c v M A X A y 0 2.5 5 mm scale TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 A max. 1.1 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 65 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 41. Package outline SOT1341-1 (XSON16) Outline References version European projection Issue date IEC JEDEC JEITA SOT1341-1 MO-252 sot1341-1_po 12-09-05 13-02-13 Unit(1) mm max nom min 0.5 0.05 0.00 A Dimensions (mm are the original dimensions) XSON16: plastic extremely thin small outline package; no leads; 16 terminals; body 2.5 x 3.2 x 0.5 mm S OT1341-1 A1 0.25 0.20 0.15 2.6 2.5 2.4 0.9 0.8 0.7 3.3 3.2 3.1 0.4 2.8 0.2 b c 0.152 0.050 D E e e1 k L 1.0 0.9 0.8 L1 v 0.1 0.05 w y 0.05 y1 0.05 0 1 2 3 mm scale Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. e1 e terminal 1 index area terminal 1 index area D B A E detail X c A A1 L1 k L - - - - - - X C b y1 C y v C A B w C 1 8 16 9 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 66 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 16. Soldering Fig 42. Reflow soldering of the TSSOP16 package DIMENSIONS in mm P1 Ay By C D1 D2 Gx Gy Hy sot403-1_fr Hx SOT403-1 solder land occupied area Footprint information for reflow soldering of TSSOP16 package Gy By Ay C Hy Hx Gx P1 Generic footprint pattern Refer to the package outline drawing for actual layout P2 (0.125) (0.125) D2 (4x) D1 P2 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 67 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 43. Reflow soldering of the SO20 package occupied area sot163-1_fr solder lands placement accuracy ± 0.25 Dimensions in mm 1.50 0.60 (20×) 1.27 (18×) 8.00 11.00 13.40 11.40 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 68 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 44. Reflow soldering of the TSSOP20 package DIMENSIONS in mm P1 Ay By C D1 D2 Gx Gy Hy sot360-1_fr Hx SOT360-1 solder land occupied area Footprint information for reflow soldering of TSSOP20 package Gy By Ay C Hy Hx Gx P1 Generic footprint pattern Refer to the package outline drawing for actual layout P2 (0.125) (0.125) D2 (4x) D1 P2 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 69 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Fig 45. Reflow soldering of the XSON16 package 􀀩􀁒􀁒􀁗􀁓􀁕􀁌􀁑􀁗􀀃􀁌􀁑􀁉􀁒􀁕􀁐􀁄􀁗􀁌􀁒􀁑􀀃􀁉􀁒􀁕􀀃􀁕􀁈􀁉􀁏􀁒􀁚􀀃􀁖􀁒􀁏􀁇􀁈􀁕􀁌􀁑􀁊􀀃􀁒􀁉􀀃􀀻􀀶􀀲􀀱􀀔􀀙􀀃􀁓􀁄􀁆􀁎􀁄􀁊􀁈􀀃 􀀶􀀲􀀷􀀔􀀖􀀗􀀔􀀐􀀔 􀁖􀁒􀁗􀀔􀀖􀀗􀀔􀀐􀀔􀁂􀁉􀁕 􀁒􀁆􀁆􀁘􀁓􀁌􀁈􀁇􀀃􀁄􀁕􀁈􀁄 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁓􀁄􀁖􀁗􀁈 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁕􀁈􀁖􀁌􀁖􀁗 􀁖􀁒􀁏􀁇􀁈􀁕􀀃􀁏􀁄􀁑􀁇􀁖 􀀬􀁖􀁖􀁘􀁈􀀃􀁇􀁄􀁗􀁈 􀀧􀁌􀁐􀁈􀁑􀁖􀁌􀁒􀁑􀁖􀀃􀁌􀁑􀀃􀁐􀁐 􀀔􀀗􀀐􀀓􀀕􀀐􀀕􀀛 􀀔􀀗􀀐􀀓􀀖􀀐􀀓􀀚 􀀓􀀑􀀚 􀀔􀀑􀀔􀀚 􀀔􀀑􀀓􀀚 􀀖􀀑􀀔􀀗 􀀓􀀑􀀗 􀀓􀀑􀀕􀀕 􀀓􀀑􀀔􀀛 􀀖􀀑􀀓􀀕 􀀖􀀑􀀔􀀕 􀀖􀀑􀀘 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 70 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 17. Abbreviations 18. References [1] I2C-bus specification UM10204. Table 27. Abbreviations Acronym Description AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General-Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 71 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 19. Revision history Table 28. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC81XM v.4.3 20140422 Product data sheet - LPC81XM v.4.2 Modifications: • Section 8.20.2 “Clock input” updated for clarity. • CLKIN signal removed from Table 12 “Dynamic characteristic: external clock (XTALIN inputs)”. • Name “SCT” changed to “SCTimer/PWM” for clarity. • Remove slew rate control from GPIO features for clarity. • MRT bus stall mode added. • WWDT clock source corrected in Section 8.17.1. • Pin description table updated for clarification (I2C-bus pins, WAKEUP, RESET). • Added reflow solder diagram and thermal resistance numbers for XSON16 (SOT1341-1). • Table 21: Added Vref(cmp) spec for PIO0_6/VDDCMP. LPC81XM v.4.2 20131210 Product data sheet - LPC81XM v.4.1 Modifications: Corrected vertical axis marker in Figure 21 “CoreMark score”. LPC81XM v.4.1 20131112 Product data sheet - LPC81XM v.4 Modifications: • Corrected XSON16 pin information in Figure 6 and Table 4. LPC81XM v.4 20131025 Product data sheet - LPC81XM v.3.1 Modifications: • Added Section 14.1 “Typical wake-up times”. • Added LPC812M101JTB16 and XSON16 package. LPC81XM v.3.1 20130916 Product data sheet - LPC81XM v.3 Modifications: • Correct the pin interrupt features: Pin interrupts can wake up the part from Sleep mode, Deep-sleep mode, and Power-down mode. See Section 8.11.1. • Table 9 “Static characteristics”: Updated power numbers for Deep-sleep, Power-down, and Deep power-down. • Added 30 MHz data to Figure 13 “Active mode: Typical supply current IDD versus supply voltage VDD”, Figure 14 “Active mode: Typical supply current IDD versus temperature”, and Figure 15 “Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies”. LPC81XM v.3 20130729 Product data sheet - LPC81XM v.2.1 • Operating temperature range changed to 40 °C to 105 °C. • Type numbers updated to reflect the new operating temperature range. See Table 1 “Ordering information” and Table 2 “Ordering options”. • ISP entry pin moved from PIO0_1 to PIO0_12 for TSSOP, and SSOP packages. See Table 4 and Table 6. • Propagation delay values updated in Table 21 “Comparator characteristics”. • SPI characteristics updated. See Section 12.6. • IRC characteristics updated. See Section 12.3. • CoreMark data updated. See Figure 19 and Figure 20. • IRC frequency changed to 12 MHz +/- 1.5 %. See Table 13. • Data sheet status updated to Product data sheet. LPC81XM v.2.1 20130325 Preliminary data sheet - LPC81XM v.2 LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 72 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller • Editorial updates (temperature sensor removed). • CoreMark data added. See Figure 19 “Active mode: CoreMark power consumption IDD” and Figure 20 “CoreMark score”. • IDD in Deep power-down mode added for condition Low-power oscillator on/WKT wake-up enabled. See Table 10. • Table note 3 updated for Table 4 “Pin description table (fixed pins)”. • Conditions for ter and tprog updated in Table 12 “Flash characteristics”. • Section 13.3 “Internal voltage reference” added. • Typical timing data added for SPI. See Section 12.6. • Typical timing data added for USART in synchronous mode. See Section 12.7. • BOD characterization added. See Section 13.1. • IRC characterization added. See Section 12.3. • Internal voltage reference characteristics added. See Section 13.3. • Data sheet status changed to Preliminary data sheet. LPC81XM v.2 20130128 Objective data sheet - LPC81XM v.1 Modifications: • MTB memory space changed to 1 kB in Figure 6. • Electrical pin characteristics added in Table 10. • Figure 11 “Connecting the SWD pins to a standard SWD connector” added. • Peripheral power consumption added in Table 11. • Table 7 updated. • MRT implementation changed to 31-bit timer. • Power consumption data in active and sleep mode with IRC added. See Figure 13 to Figure 15. • Power consumption (parameter IDD) in active and sleep mode for low-power mode at 12 MHz corrected in Table 10. • Power consumption (parameter IDD) in active and sleep mode at 24 MHz added in Table 10. • Maximum USART speed in synchronous mode changed to 10 Mbit/s. • Section 5 “Marking” added. LPC81XM v.1 20121112 Objective data sheet - - Table 28. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 73 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 74 of 76 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 4.3 — 22 April 2014 75 of 76 continued >> NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 Functional description . . . . . . . . . . . . . . . . . . 13 8.1 ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . 13 8.2 On-chip flash program memory . . . . . . . . . . . 13 8.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 Nested Vectored Interrupt Controller (NVIC) . 13 8.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 8.6 System tick timer . . . . . . . . . . . . . . . . . . . . . . 14 8.7 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.8 I/O configuration . . . . . . . . . . . . . . . . . . . . . . . 15 8.8.1 Standard I/O pad configuration . . . . . . . . . . . . 16 8.9 Switch Matrix (SWM) . . . . . . . . . . . . . . . . . . . 17 8.10 Fast General-Purpose parallel I/O (GPIO) . . . 17 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.11 Pin interrupt/pattern match engine . . . . . . . . . 18 8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.12 USART0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.13 SPI0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.14 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 20 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.15 State-Configurable Timer/PWM (SCTimer/PWM) . . . . . . . . . . . . . . . . . . . . . . . 20 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.16 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 21 8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.17 Windowed WatchDog Timer (WWDT) . . . . . . 21 8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.18 Self Wake-up Timer (WKT). . . . . . . . . . . . . . . 22 8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.19 Analog comparator (ACMP) . . . . . . . . . . . . . . 22 8.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.20 Clocking and power control . . . . . . . . . . . . . . 24 8.20.1 Crystal and internal oscillators . . . . . . . . . . . . 24 8.20.1.1 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . 25 8.20.1.2 Crystal Oscillator (SysOsc) . . . . . . . . . . . . . . 25 8.20.1.3 Internal Low-power Oscillator and Watchdog Oscillator (WDOsc) . . . . . . . . . . . . . . . . . . . . 25 8.20.2 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.20.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.20.4 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.5 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.20.6.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27 8.20.6.4 Power-down mode. . . . . . . . . . . . . . . . . . . . . 27 8.20.6.5 Deep power-down mode . . . . . . . . . . . . . . . . 27 8.21 System control . . . . . . . . . . . . . . . . . . . . . . . . 28 8.21.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.21.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 28 8.21.3 Code security (Code Read Protection - CRP) 29 8.21.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.21.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.22 Emulation and debugging . . . . . . . . . . . . . . . 30 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Thermal characteristics . . . . . . . . . . . . . . . . . 32 11 Static characteristics . . . . . . . . . . . . . . . . . . . 33 11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 37 11.2 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 41 11.3 Peripheral power consumption . . . . . . . . . . . 42 11.4 Electrical pin characteristics. . . . . . . . . . . . . . 43 12 Dynamic characteristics. . . . . . . . . . . . . . . . . 46 12.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2 External clock for the oscillator in slave mode 46 12.3 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 47 12.4 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.5 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 50 12.7 USART interface . . . . . . . . . . . . . . . . . . . . . . 53 13 Analog characteristics . . . . . . . . . . . . . . . . . . 54 13.1 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.2 Internal voltage reference . . . . . . . . . . . . . . . 54 13.3 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14 Application information . . . . . . . . . . . . . . . . . 58 14.1 Typical wake-up times . . . . . . . . . . . . . . . . . . 58 14.2 XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.3 XTAL Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 61 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 April 2014 Document identifier: LPC81XM Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 70 18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 71 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 73 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 73 20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 74 21 Contact information. . . . . . . . . . . . . . . . . . . . . 74 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series. 2. Features and benefits  ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included.  ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).  Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states.  In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.  On-chip SRAM includes:  32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.4 — 4 April 2014 Product data sheet LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 2 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller  Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.  Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers.  Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays.  Split APB bus allows high throughput with few stalls between the CPU and DMA.  Serial interfaces:  Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.)  USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.)  Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support.  CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)  SPI controller with synchronous, serial, full duplex communication and programmable data length.  Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller.  Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode.  I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.)  Other peripherals:  70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller.  12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller.  10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2)  Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests.  One motor control PWM with support for three-phase motor control. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 3 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller  Quadrature encoder interface that can monitor one external quadrature encoder.  One standard PWM/timer block with external count input.  RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers.  WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock.  ARM Cortex-M3 system tick timer, including an external clock input option.  Repetitive interrupt timer provides programmable and repeating timed interrupts.  Each peripheral has its own clock divider for further power savings.  Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options.  Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution.  Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes.  Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.  Single 3.3 V power supply (2.4 V to 3.6 V).  Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources.  Non-maskable Interrupt (NMI) input.  Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock.  The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes.  Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).  Brownout detect with separate threshold for interrupt and forced reset.  Power-On Reset (POR).  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.  USB PLL for added flexibility.  Code Read Protection (CRP) with different security levels.  Unique device serial number for identification purposes.  Available as LQFP100 (14 mm  14 mm  1.4 mm), TFBGA1001 (9 mm  9 mm  0.7 mm), and WLCSP100 (5.074  5.074  0.6 mm) package. 1. LPC1768/65 only. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 4 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 3. Applications 4. Ordering information 4.1 Ordering options  eMetering  Alarm systems  Lighting  White goods  Industrial networking  Motor control Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074  5.074  0.6 mm - LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14  14  1.4 mm SOT407-1 Table 2. Ordering options Type number Flash SRAM in kB Ethernet USB CAN I2S DAC Maximum CPU operating frequency CPU AHB SRAM0 AHB SRAM1 Total LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768UK 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 5 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Table 3. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘B’ Third device revision LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 6 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 6. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 32/64 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128 kB DMA CONTROLLER ETHERNET CONTROLLER WITH DMA(1) USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS XTAL1 XTAL2 RESET clocks and controls JTAG interface debug port USB PHY SSP0 UART2/3 I2S(1) I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM QUADRATURE ENCODER SSP1 UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT PWM1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS 32 kHz OSCILLATOR APB slave group 0 APB slave group 1 DAC(1) RTC POWER DOMAIN LPC1769/68/67/ 66/65/64/63 master master master 002aad944 slave slave slave slave slave ROM slave MULTILAYER AHB MATRIX P0 to P4 SDA2 SCL2 SCK0 SSEL0 MISO0 MOSI0 SCK1 SSEL1 MISO1 MOSI1 RXD2/3 TXD2/3 PHA, PHB INDEX EINT[3:0] AOUT MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT 4 × MAT2 2 × MAT3 2 × CAP2 2 × CAP3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1 RTCX2 VBAT PWM1[7:0] 2 × MAT0/1 2 × CAP0/1 RD1/2 TD1/2 SDA0/1 SCL0/1 AD0[7:0] SCK/SSEL MOSI/MISO 8 × UART1 RXD0/TXD0 P0, P2 PCAP1[1:0] RMII pins USB pins CLKOUT MPU = connected to DMA LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 7 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package LPC176xFBD100 50 1 25 75 51 26 76 100 002aad945 002aaf723 LPC1768/65FET100 Transparent top view J G K H F E D C B A 1 2 3 4 5 6 7 8 9 10 ball A1 index area LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 8 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 4. Pin configuration WLCSP100 package Transparent top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 LPC1768UK bump A1 index area aaa-009522 Table 4. Pin allocation table TFBGA100 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 11 - 12 - Row B 1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - Row D 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] 11 - 12 - Row E 1 VSSA 2 VDDA 3 VREFP 4 n.c. 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 7 P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/ RI1/TRACECLK LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 9 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ RXD2 8 P0[16]/RXD1/ SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 10 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Row J 1 P0[28]/SCL0/ USB_SCL 2 P0[27]/SDA0/ USB_SDA 3 P0[29]/USB_D+ 4 P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 5 P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 6 VSS 7 P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 8 P0[1]/TD1/RXD3/SCL1 9 P2[13]/EINT3/ I2STX_SDA 10 P2[10]/EINT0/NMI 11 - 12 - Row K 1 P3[26]/STCLK/ MAT0[1]/PWM1[3] 2 VDD(3V3) 3 VSS 4 P1[20]/MCI0/ PWM1[2]/SCK0 5 P1[23]/MCI1/ PWM1[4]/MISO0 6 P1[26]/MCOB1/ PWM1[6]/CAP0[0] 7 P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 8 P0[0]/RD1/TXD3/SDA1 9 P0[11]/RXD2/ SCL2/MAT3[1] 10 P2[12]/EINT2/ I2STX_WS 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 5. Pin description Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ SDA1 46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ SCL1 47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 11 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). I CAP2[1] — Capture input for Timer 2, channel 1. P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ I2STX_WS/ MISO1/MAT2[2] 77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ SDA2/MAT3[0] 48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 12 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[11]/RXD2/ SCL2/MAT3[1] 49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ SSEL0/SSEL 63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ MISO0/MISO 61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ MOSI0/MOSI 60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ SDA1 59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I/O SDA1 — I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 13 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] 8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ AOUT/RXD3 6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output (LPC1769/68/67/66/65/63 only). I RXD3 — Receiver input for UART3. P0[27]/SDA0/ USB_SDA 25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O USB_SDA — USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28]/SCL0/ USB_SCL 24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). I/O USB_SCL — USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 14 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ ENET_TXD0 95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1]/ ENET_TXD1 94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4]/ ENET_TX_EN 93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8]/ ENET_CRS 92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only). P1[9]/ ENET_RXD0 91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[10]/ ENET_RXD1 90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[14]/ ENET_RX_ER 89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15]/ ENET_REF_CLK 88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16]/ ENET_MDC 87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17]/ ENET_MDIO 86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 15 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0] 32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. (LPC1769/68/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1769/68/66/65 only). I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/MCI0/ PWM1[2]/SCK0 34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/MCABORT/ PWM1[3]/ SSEL0 35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ PWM1[4]/MISO0 37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ PWM1[5]/MOSI0 38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 16 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[25]/MCOA1/ MAT1[1] 39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/MCOB1/ PWM1[6]/CAP0[0] 40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin. O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65 only). I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ PCAP1[1]/ MAT0[1] 45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ TXD1 75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ RXD1 74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 17 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3] 73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2] 70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1] 69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0] 68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ RI1/TRACECLK 67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). O TXD2 — Transmitter output for UART2. P2[9]/ USB_CONNECT/ RXD2 64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 18 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[11]/EINT1/ I2STX_CLK 52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12]/EINT2/ I2STX_WS 51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13]/EINT3/ I2STX_SDA 50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin. I EINT3 — External interrupt 3 input. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25]/MAT0[0]/ PWM1[2] 27 H3 D8 [1] I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/STCLK/ MAT0[1]/PWM1[3] 26 K1 A10 [1] I/O P3[26] — General purpose digital input/output pin. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28]/RX_MCLK/ MAT2[0]/TXD3 82 C7 G1 [1] I/O P4[28] — General purpose digital input/output pin. O RX_MCLK — I2S receive master clock. (LPC1769/68/67/66/65 only). O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/TX_MCLK/ MAT2[1]/RXD3 85 E6 F1 [1] I/O P4[29] — General purpose digital input/output pin. O TX_MCLK — I2S transmit master clock. (LPC1769/68/67/66/65 only). O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 19 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller TDO/SWO 1 A1 A1 [1][7] O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. TDI 2 C3 C4 [1][8] I TDI — Test Data in for JTAG interface. TMS/SWDIO 3 B1 B3 [1][8] I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 4 C2 A2 [1][8] I TRST — Test Reset for JTAG interface. TCK/SWDCLK 5 C1 D4 [1][7] I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RTCK 100 B2 B2 [1][7] O RTCK — JTAG interface control signal. RSTOUT 14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. RESET 17 F3 C6 [9] I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22 H2 D7 [10][11] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23 G3 A9 [10][11] O Output from the oscillator amplifier. RTCX1 16 F2 A7 [10][11] I Input to the RTC oscillator circuit. RTCX2 18 G1 B7 [10] O Output from the RTC oscillator circuit. VSS 31, 41, 55, 72, 83, 97 B3, B7, C9, G7, J6, K3 E5, F5, F6, G5, G6, G7 [10] I ground: 0 V reference. VSSA 11 E1 B5 [10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, 71, 96 K2, H9, C10 , A3 E4, E6, F7, G4 [10] I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(REG)(3V3) 42, 84 H6, A7 F4, F0 [10] I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. VDDA 10 E2 A4 [10] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFP 12 E3 A5 [10] I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 20 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. VREFN 15 F1 A6 I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19 G2 A8 [10][12] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. n.c. 13 D4, E4 B6, D6 - not connected. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 21 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 8.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 8.3 On-chip flash program memory The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 8.4 On-chip SRAM The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 8.5 Memory Protection Unit (MPU) The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 22 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 8.6 Memory map The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 23 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2. Fig 5. LPC17xx memory map 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 C000 0x5020 0000 0x5001 0000 AHB peripherals Ethernet controller(1) USB controller(1) reserved 127- 4 reserved GPDMA controller 0 1 2 3 APB0 peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 WDT 0x4000 0000 timer 0 timer 1 UART0 UART1 reserved reserved SPI RTC + backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM(1) CAN AF registers(1) CAN common(1) CAN1(1) CAN2(1) 22 - 19 reserved I2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 reserved reserved 32 kB local SRAM (LPC1769/8/7/6/5/3) 16 kB local SRAM (LPC1764) reserved reserved private peripheral bus 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x0004 0000 0x0002 0000 0x0008 0000 0x1000 4000 0x1000 0000 0x1000 8000 0x1FFF 0000 0x1FFF 2000 0x2008 0000 0x2007 C000 0x2008 4000 0x2200 0000 0x200A 0000 0x2009 C000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved GPIO reserved reserved reserved reserved APB0 peripherals AHB peripherals APB1 peripherals AHB SRAM bit-band alias addressing peripheral bit-band alias addressing 16 kB AHB SRAM1 (LPC1769/8/7/6/5) 16 kB AHB SRAM0 256 kB on-chip flash (LPC1766/65/63) 128 kB on-chip flash (LPC1764) 512 kB on-chip flash (LPC1769/8/7) PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aad946 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC(1) timer 2 timer 3 UART2 UART3 reserved I2S(1) I2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 reserved repetitive interrupt timer 11 12 reserved motor control PWM 30 - 16 reserved 13 14 15 31 system control QEI LPC1769/68/67/66/65/64/63 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 24 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC17xx, the NVIC supports 33 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • Non-Maskable Interrupt (NMI) • Software interrupt generation 8.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 8.8 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 8.9 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers. Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 25 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 8.10 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 26 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 8.11 Ethernet Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 8.11.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 27 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 8.12 USB interface Remark: The USB controller is available as device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 15.1. 8.12.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. 8.12.1.1 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 28 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 8.12.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification. 8.12.2.1 Features • OHCI compliant. • One downstream port. • Supports port power switching. 8.12.3 USB OTG controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver. 8.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 8.13 CAN controller and acceptance filters Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 29 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 8.14 12-bit ADC The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support. 8.14.1 Features • 12-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range VREFN to VREFP. • 12-bit conversion rate: 200 kHz. • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 8.15 10-bit DAC The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. 8.15.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA support LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 30 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 8.16.1 Features • Maximum UART data bit rate of 6.25 Mbit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • Support for RS-485/9-bit/EIA-485 mode (UART1). • UART3 includes an IrDA mode to support infrared communication. • All UARTs have DMA support. 8.17 SPI serial I/O controller The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 8.17.1 Features • Maximum SPI data bit rate of 12.5 Mbit/s • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 8.18 SSP serial I/O controller The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 31 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.1 Features • Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 8.19 I2C-bus serial I/O controllers The LPC17xx each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 8.19.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 32 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.20 I2S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 8.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 8.21 General purpose 32-bit timers/external event counters The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.21.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 33 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 8.22.1 Features • One PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 34 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 8.23 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 8.24 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 8.24.1 Features • Tracks encoder position. • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 35 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.25.1 Features • 32-bit counter running from PCLK. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.26 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be clocked from the internal AHB clock or from a device pin. 8.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 8.27.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  232  4) in multiples of Tcy(WDCLK)  4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC) oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 36 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC17xx is powered off. The RTC includes an alarm function that can wake up the LPC17xx from all reduced power modes with a time resolution of 1 s. 8.28.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 8.29 Clocking and power control 8.29.1 Crystal oscillators The LPC17xx include three independent oscillators. These are the main oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 37 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller See Figure 6 for an overview of the LPC17xx clock generation. 8.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.29.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 8.29.2 for additional information. 8.29.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU. Fig 6. LPC17xx clocking generation block diagram MAIN OSCILLATOR INTERNAL RC OSCILLATOR RTC OSCILLATOR MAIN PLL WATCHDOG TIMER REAL-TIME CLOCK CPU CLOCK DIVIDER PERIPHERAL CLOCK GENERATOR USB BLOCK ARM CORTEX-M3 ETHERNET BLOCK DMA GPIO NVIC USB CLOCK DIVIDER system clock select (CLKSRCSEL) USB clock config (USBCLKCFG) CPU clock config (CCLKCFG) pllclk CCLK/8 CCLK/6 CCLK/4 CCLK/2 CCLK pclkWDT rtclk = 1Hz usbclk (48 MHz) cclk USB PLL USB PLL enable main PLL enable 32 kHz APB peripherals LPC17xx 002aad947 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 38 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 8.29.3 USB PLL (PLL1) The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle. 8.29.4 RTC clock output The LPC17xx feature a clock output function intended for synchronizing with external devices and for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results. 8.29.5 Wake-up timer The LPC17xx begin operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 39 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 8.29.6 Power control The LPC17xx support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC17xx also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 8.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 40 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 8.29.6.3 Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 8.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 8.29.6.5 Wake-up interrupt controller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 8.29.7 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 41 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC17xx application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 42 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30 System control 8.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 8.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 7. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aad978 RTCX1 VBAT VDD(REG)(3V3) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VREFN VSSA LPC17xx ULTRA LOW-POWER REGULATOR POWER SELECTOR LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 43 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 8.30.3 Code security (Code Read Protection - CRP) This feature of the LPC17xx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. 8.30.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 44 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 8.30.6 External interrupt inputs The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 8.30.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC17xx is configured for 128 total interrupts. 8.31 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 45 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 8. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 19 for maximum operating voltage. [4] Including voltage on outputs in 3-state mode. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD  2.4 V [2][4] 0.5 +5.5 VI VDD = 0 V 0.5 +3.6 5 V tolerant open-drain pins PIO0_27 and PIO0_28 [2][5] 0.5 +5.5 IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature [6] 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 46 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C) • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal resistance (15 %) Symbol Parameter Conditions Max/Min Unit LQFP100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 38.01 C/W Single-layer (4.5 in  3 in); still air 55.09 C/W Rth(j-c) thermal resistance from junction to case 9.065 C/W TFBGA100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in  4 in); still air 55.2 C/W Single-layer (4.5 in  3 in); still air 45.6 C/W Rth(j-c) thermal resistance from junction to case 9.5 C/W Tj = Tamb + PD  Rthj – a LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 47 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3][4] 2.5 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled; PCLK = CCLK⁄8 CCLK = 12 MHz; PLL disabled [6][7]- 7 - mA CCLK = 100 MHz; PLL enabled [6][7]- 42 - mA CCLK = 100 MHz; PLL enabled (LPC1769) [6][8]- 50 - mA CCLK = 120 MHz; PLL enabled (LPC1769) [6][8]- 67 - mA sleep mode [6][9]- 2 - mA deep sleep mode [6][10]- 240 - A power-down mode [6][10]- 31 - A deep power-down mode; RTC running [11]- 630 - nA IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present [12]- 530 - nA VDD(REG)(3V3) not present [13] - 1.1 - A IDD(IO) I/O supply current deep sleep mode [14][15]- 40 - nA power-down mode [14][15]- 40 - nA deep power-down mode [14]- 10 - nA LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 48 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller IDD(ADC) ADC supply current active mode; ADC powered [16][17]- 1.95 - mA ADC in Power-down mode [16][18]- <0.2 - A deep sleep mode [16]- 38 - nA power-down mode [16]- 38 - nA deep power-down mode [16]- 24 - nA II(ADC) ADC input current on pin VREFP deep sleep mode [19]- 100 - nA power-down mode [19]- 100 - nA deep power-down mode [19]- 100 - nA Standard port pins, RESET, RTCK IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [20][21] [22] 0 - 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3)  0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(3V3)  0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4 - - mA IOHS HIGH-level short-circuit output current VOH = 0 V [23]- - 45 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [23]- - 50 mA Ipd pull-down current VI = 5 V 10 50 150 A Ipu pull-up current VI = 0 V 15 50 85 A VDD(3V3) < VI < 5 V 0 0 0 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 49 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V  VDD((3V3)  3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] VDDA for DAC specs are from 2.7 V to 3.6 V. I2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3)- - V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05  VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA - - 0.4 V ILI input leakage current VI = VDD(3V3) [24]- 2 4 A VI = 5 V - 10 22 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V USB pins (LPC1769/68/66/65/64 only) IOZ OFF-state output current 0 V < VI < 3.3 V [2]- - 10 A VBUS bus supply voltage [2]- - 5.25 V VDI differential input sensitivity voltage (D+)  (D) [2] 0.2 - - V VCM differential common mode voltage range includes VDI range [2] 0.8 - 2.5 V Vth(rs)se single-ended receiver switching threshold voltage [2] 0.8 - 2.0 V VOL LOW-level output voltage for low-/full-speed RL of 1.5 k to 3.6 V [2]- - 0.18 V VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND [2] 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND [2]- - 20 pF ZDRV driver output impedance for driver which is not high-speed capable with 33  series resistor; steady state drive [2][25] 36 - 44.1  Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 50 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [5] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [6] VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements. [7] Applies to LPC1768/67/66/65/64/63. [8] Applies to LPC1769 only. [9] IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK⁄8. [10] BOD disabled. [11] On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [12] On pin VBAT; IDD(REG)(3V3) = 630 nA; VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [13] On pin VBAT; VBAT = 3.0 V; Tamb = 25 C. [14] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C. [15] TCK/SWDCLK pin needs to be externally pulled LOW. [16] On pin VDDA; VDDA = 3.3 V; Tamb = 25 C. The ADC is powered if the PDN bit in the AD0CR register is set to 1 and in Power-down mode of the PDN bit is set to 0. [17] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360_1. [18] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360_1. [19] Vi(VREFP) = 3.3 V; Tamb = 25 C. [20] Including voltage on outputs in 3-state mode. [21] VDD(3V3) supply voltages must be present. [22] 3-state outputs go into 3-state mode in Deep power-down mode. [23] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [24] To VSS. [25] Includes external resistors of 33   1 % on D+ and D. 11.1 Power consumption Conditions: BOD disabled. Fig 8. Deep-sleep mode: typical regulator supply current IDD(Reg)(3V3) versus temperature 002aaf568 temperature (°C) −40 −15 10 35 60 85 250 350 300 400 IDD(Reg)(3V3) (μA) 200 3.6 V 3.3 V 2.4 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 51 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: BOD disabled. Fig 9. Power-down mode: Typical regulator supply current IDD(Reg)(3V3) versus temperature Conditions: VDD(REG)(3V3) floating; RTC running. Fig 10. Deep power-down mode: Typical battery supply current IBAT versus temperature 002aaf569 40 80 120 0 temperature (°C) −40 −15 10 35 60 85 IDD(Reg)(3V3) (μA) 3.6 V 3.3 V 2.4 V 002aag119 1.0 1.4 1.8 0.6 temperature (°C) -40 -15 10 35 60 85 IBAT) (μA) Vi(VBAT) = 3.6 V 3.3 V 3.0 V 2.4 V LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 52 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running. Fig 11. Deep power-down mode: Typical regulator supply current IDD(REG)(3V3) and battery supply current IBAT versus temperature 002aag120 temperature (°C) -40 -15 10 35 60 85 0.8 1.6 0.4 1.2 2.0 0 IDD(REG)(3V3) IBAT IDD(REG)(3V3)/IBAT (μA) LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 53 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11.2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock PCLK = CCLK/4. [1] The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately. Table 9. Power consumption for individual analog and digital blocks Peripheral Conditions Typical supply current in mA; CCLK = Notes 12 MHz 48 MHz 100 MHz Timer 0.03 0.11 0.23 Average current per timer UART 0.07 0.26 0.53 Average current per UART PWM 0.05 0.20 0.41 Motor control PWM 0.05 0.21 0.42 I2C 0.02 0.08 0.16 Average current per I2C SPI 0.02 0.06 0.13 SSP1 0.04 0.16 0.32 ADC PCLK = 12 MHz for CCLK = 12 MHz and 48 MHz; PCLK = 12.5 MHz for CCLK = 100 MHz 2.12 2.09 2.07 CAN PCLK = CCLK/6 0.13 0.49 1.00 Average current per CAN CAN0, CAN1, acceptance filter PCLK = CCLK/6 0.22 0.85 1.73 Both CAN blocks and acceptance filter[1] DMA PCLK = CCLK 1.33 5.10 10.36 QEI 0.05 0.20 0.41 GPIO 0.33 1.27 2.58 I2S 0.09 0.34 0.70 USB and PLL1 0.94 1.32 1.94 Ethernet Ethernet block enabled in the PCONP register; Ethernet not connected. 0.49 1.87 3.79 Ethernet connected Ethernet initialized, connected to network, and running web server example. - - 5.19 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 54 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11.3 Electrical pin characteristics Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 13. Typical LOW-level output current IOL versus LOW-level output voltage VOL IOH (mA) 0 8 16 24 002aaf112 2.8 2.4 3.2 3.6 VOH (V) 2.0 T = 85 °C 25 °C −40 °C VOL (V) 0 0.2 0.4 0.6 002aaf111 5 10 15 IOL (mA) 0 T = 85 °C 25 °C −40 °C LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 55 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 14. Typical pull-up current Ipu versus input voltage VI Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins. Fig 15. Typical pull-down current Ipd versus input voltage VI 0 1 2 3 4 5 002aaf108 −30 −50 −10 10 Ipu (μA) −70 T = 85 °C 25 °C −40 °C VI (V) 002aaf109 VI (V) 0 1 2 3 4 5 10 70 50 30 90 Ipd (μA) −10 T = 85 °C 25 °C −40 °C LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 56 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12. Dynamic characteristics 12.1 Flash memory [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 12.2 External clock [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Table 10. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 10000 100000 - cycles tret retention time powered 10 - - years unpowered 20 - - years ter erase time sector or multiple consecutive sectors 95 100 105 ms tprog programming time [2] 0.95 1 1.05 ms Table 11. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Fig 16. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) tCHCL tCLCX tCHCX Tcy(clk) tCLCH 002aaa907 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 57 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.3 Internal oscillators [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. 12.4 I/O pins [1] Applies to standard I/O pins. Table 12. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz fi(RTC) RTC input frequency - - 32.768 - kHz Conditions: Frequency values are typical values. 4 MHz  1 % accuracy is guaranteed for 2.7 V  VDD(REG)(3V3)  3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 4 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 17. Internal RC oscillator frequency versus temperature 002aaf107 temperature (°C) -40 -15 10 35 60 85 4.024 4.032 4.020 4.028 4.036 fosc(RC) (MHz) 4.016 VDD(REG)(3V3) = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V Table 13. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 58 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.5 I2C-bus [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [7] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see the I2C-bus specification UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. Table 14. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz tf fall time [3][4][5][6] of both SDA and SCL signals Standard-mode - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns tLOW LOW period of the SCL clock Standard-mode 4.7 - s Fast-mode 1.3 - s Fast-mode Plus 0.5 - s tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus 0.26 - s tHD;DAT data hold time [3][7][8] Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus 0 - s tSU;DAT data set-up time [9][10] Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus 50 - ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 59 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.6 I2S-bus interface Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. [1] CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK⁄4; I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification. Fig 18. I2C-bus pins clock timing 002aaf425 tf 70 % SDA 30 % tf 70 % 30 % S 70 % 30 % 70 % 30 % tHD;DAT SCL 1 / fSCL 70 % 30 % 70 % 30 % tVD;DAT tHIGH tLOW tSU;DAT Table 15. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to +85 C. Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time [1] - - 35 ns tf fall time [1] - - 35 ns tWH pulse width HIGH on pins I2STX_CLK and I2SRX_CLK [1] 0.495  Tcy(clk) - - - tWL pulse width LOW on pins I2STX_CLK and I2SRX_CLK [1] - - 0.505  Tcy(clk) ns output tv(Q) data output valid time on pin I2STX_SDA [1] - - 30 ns on pin I2STX_WS [1] - - 30 ns input tsu(D) data input set-up time on pin I2SRX_SDA [1] 3.5 - - ns th(D) data input hold time on pin I2SRX_SDA [1] 4.0 - - ns LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 60 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 19. I2S-bus timing (output) Fig 20. I2S-bus timing (input) 002aad992 I2STX_CLK I2STX_SDA I2STX_WS Tcy(clk) tf tr tWH tWL tv(Q) tv(Q) 002aae159 Tcy(clk) tf tr tWH tsu(D) th(D) tsu(D) tsu(D) tWL I2SRX_CLK I2SRX_SDA I2SRX_WS LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 61 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.7 SSP interface [1] The peripheral clock for SSP is PCLK = CCLK = 20 MHz. Table 16. Dynamic characteristic: SSP interface Tamb = 25C; VDD(3V3) over specified ranges. Symbol Parameter Conditions Min Typ Max Unit SSP interface tsu(SPI_MISO) SPI_MISO set-up time measured in SPI Master mode; see Figure 21 [1] 30 - ns Fig 21. MISO line set-up time in SSP Master mode tsu(SPI_MISO) SCK shifting edges MOSI MISO 002aad326 sampling edges LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 62 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.8 USB interface Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. [1] Characterized but not implemented as production test. Guaranteed by design. Table 17. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V  VDD(3V3)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 22 160 - 175 ns tFDEOP source jitter for differential transition to SE0 transition see Figure 22 2 - +5 ns tJR1 receiver jitter to next transition 18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns tEOPR1 EOP width at receiver must reject as EOP; see Figure 22 [1] 40 - - ns tEOPR2 EOP width at receiver must accept as EOP; see Figure 22 [1] 82 - - ns Fig 22. Differential data-to-EOP transition skew and EOP width 002aab561 TPERIOD differential data lines crossover point source EOP width: tFEOPT receiver EOP width: tEOPR1, tEOPR2 crossover point extended differential data to SE0/EOP skew n × TPERIOD + tFDEOP LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 63 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 12.9 SPI [1] TSPICYC = (Tcy(PCLK)  n)  0.5 %, n is the SPI clock divider value (n  8); PCLK is derived from the processor clock CCLK. [2] Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %) edge of the data signal (MOSI or MISO). Table 18. Dynamic characteristics of SPI pins Tamb = 40 C to +85 C. Symbol Parameter Min Typ Max Unit Tcy(PCLK) PCLK cycle time 10 - - ns TSPICYC SPI cycle time [1] 79.6 - - ns tSPICLKH SPICLK HIGH time 0.485  TSPICYC - - ns tSPICLKL SPICLK LOW time - 0.515  TSPICYC ns SPI master tSPIDSU SPI data set-up time [2] 0 - - ns tSPIDH SPI data hold time [2] 2  Tcy(PCLK)  5 - - ns tSPIQV SPI data output valid time [2] 2  Tcy(PCLK) + 30 - - ns tSPIOH SPI output data hold time [2] 2  Tcy(PCLK) + 5 - - ns SPI slave tSPIDSU SPI data set-up time [2] 0 - - ns tSPIDH SPI data hold time [2] 2  Tcy(PCLK) + 5 - - ns tSPIQV SPI data output valid time [2] 2  Tcy(PCLK) + 35 - - ns tSPIOH SPI output data hold time [2] 2  Tcy(PCLK) + 15 - - ns Fig 23. SPI master timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad986 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 64 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 24. SPI master timing (CPHA = 0) Fig 25. SPI slave timing (CPHA = 1) SCK (CPOL = 0) MOSI MISO 002aad987 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID tSPIQV SCK (CPOL = 0) MOSI MISO 002aad988 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 65 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 13. ADC electrical characteristics [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 27. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 27. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 27. [6] ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 27. [8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 27. [9] See Figure 28. [10] The conversion frequency corresponds to the number of samples per second. Fig 26. SPI slave timing (CPHA = 0) SCK (CPOL = 0) MOSI MISO 002aad989 TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPIQV DATA VALID DATA VALID tSPIOH SCK (CPOL = 1) DATA VALID DATA VALID Table 19. ADC characteristics (full resolution) VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution.[1] Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA V Cia analog input capacitance - - 15 pF ED differential linearity error [2][3]- - 1 LSB EL(adj) integral non-linearity [4]- - 3 LSB EO offset error [5][6]- - 2 LSB EG gain error [7]- - 0.5 % ET absolute error [8]- - 4 LSB Rvsi voltage source interface resistance [9]- - 7.5 k fclk(ADC) ADC clock frequency - - 13 MHz fc(ADC) ADC conversion frequency [10]- - 200 kHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 66 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 27. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 27. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 27. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 27. [7] The conversion frequency corresponds to the number of samples per second. Table 20. ADC characteristics (lower resolution) Tamb = 40 C to +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC.[1] Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error [2][3] - 1 - LSB EL(adj) integral non-linearity [4] - 1.5 - LSB EO offset error [5] - 2 - LSB EG gain error [6] - 2 - LSB fclk(ADC) ADC clock frequency 3.0 V  VDDA  3.6 V - - 33 MHz 2.7 V  VDDA < 3.0 V - - 25 MHz fc(ADC) ADC conversion frequency 3 V  VDDA  3.6 V [7]- - 500 kHz 2.7 V  VDDA < 3.0 V [7]- - 400 kHz LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 67 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 27. 12-bit ADC characteristics 002aad948 4095 4094 4093 4092 4091 (2) (1) 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 LSB (ideal) code out VREFP − VREFN 4096 offset error EO gain error EG offset error EO VIA (LSBideal) 1 LSB = LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 68 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 14. DAC electrical characteristics Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent (see Table 21). Parasitic resistance and capacitance from the pad are not included in this figure. Fig 28. ADC interface to pins AD0[n] Table 21. ADC interface components Component Range Description Ri1 2 k to 5.2 k Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. Ri2 100  to 600  Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. C1 750 fF Parasitic capacitance from the ADC block level. C2 65 fF Parasitic capacitance from the ADC block level. C3 2.2 pF Sampling capacitor. LPC17xx AD0[n] 750 fF 65 fF Cia 2.2 pF Rvsi Ri2 100 Ω - 600 Ω Ri1 2 kΩ - 5.2 kΩ VSS VEXT 002aaf197 ADC COMPARATOR BLOCK C1 C3 C2 Table 22. DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit ED differential linearity error - 1 - LSB EL(adj) integral non-linearity - 1.5 - LSB EO offset error - 0.6 - % EG gain error - 0.6 - % CL load capacitance - 200 - pF RL load resistance 1 - - k LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 69 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15. Application information 15.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. If the LPC1769/68/67/66/65/64/63 VDD is always greater than 0 V while VBUS = 5 V, the VBUS pin can be connected directly to the VBUS pin on the USB connector. This applies to bus powered devices where the USB cable supplies the system power. For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin, precautions must be taken to reduce the voltage to below 3.6 V. The maximum allowable voltage on the VBUS pin is 3.6 V. One method is to use a voltage divider to connect the VBUS pin to the VBUS on the USB connector. The voltage divider ratio should be such that the VBUS pin will be greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum voltage. Use the following operating conditions: VBUSmax = 5.25 V VDD = 3.6 V The voltage divider would need to provide a reduction of 3.6 V/5.25 V or ~0.686 V. Fig 29. USB interface on a bus-powered device LPC17xx VDD(3V3) R1 1.5 kΩ R2 USB_UP_LED 002aad940 USB-B connector USB_D+ USB_D− VBUS VSS RS = 33 Ω RS = 33 Ω LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 70 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 30. USB interface on a bus-powered device where VBUS = 5 V, VDD not present LPC17xx VDD R1 1.5 kΩ R2 R3 USB-B connector USB_D+ USB_DUSB_ VBUS VSS RS = 33 Ω RS = 33 Ω aaa-008962 R2 USB_UP_LED Fig 31. USB interface with soft-connect LPC17xx USB-B connector USB_D+ USB_CONNECT SoftConnect switch USB_D− VBUS VSS VDD(3V3) R1 1.5 kΩ RS = 33 Ω 002aad939 RS = 33 Ω USB_UP_LED LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 71 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 32. USB OTG port configuration USB_D+ USB_D− USB_SDA USB_SCL RSTOUT LPC17xx Mini-AB connector 33 Ω 33 Ω VDD VDD 002aad941 EINTn RESET_N ADR/PSW SPEED SUSPEND OE_N/INT_N SCL SDA INT_N VBUS ID DP DM ISP1302 VSS USB_UP_LED VDD Fig 33. USB host port configuration USB_UP_LED USB_D+ USB_D− USB_PWRD LPC17xx 15 kΩ 15 kΩ USB-A connector 33 Ω 33 Ω 002aad942 VDD USB_OVRCR USB_PPWR LM3526-L ENA IN 5 V FLAGA OUTA VDD D+ D− VBUS VSS LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 72 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 35), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 36 and in Table 23 and Table 24. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 36 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer. Fig 34. USB device port configuration LPC17xx USB-B connector 33 Ω 33 Ω 002aad943 USB_UP_LED USB_CONNECT VDD VDD D+ D− USB_D+ USB_D− VBUS VBUS VSS Fig 35. Slave mode operation of the on-chip oscillator LPC1xxx XTAL1 Ci 100 pF Cg 002aae835 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 73 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 23. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1/CX2 1 MHz to 5 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 300  39 pF, 39 pF 30 pF < 300  57 pF, 57 pF 5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF 20 pF < 200  39 pF, 39 pF 30 pF < 100  57 pF, 57 pF 10 MHz to 15 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 60  39 pF, 39 pF 15 MHz to 20 MHz 10 pF < 80  18 pF, 18 pF Table 24. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Fundamental oscillation frequency FOSC Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1, CX2 15 MHz to 20 MHz 10 pF < 180  18 pF, 18 pF 20 pF < 100  39 pF, 39 pF 20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF 20 pF < 80  39 pF, 39 pF 002aaf424 LPC1xxx XTALIN XTALOUT CX1 CX2 XTAL = CL CP RS L LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 74 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 15.4 Standard I/O pin configuration Figure 37 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver: Open-drain mode enabled/disabled • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. Fig 37. Standard I/O pin configuration with analog input PIN VDD VDD ESD VSS ESD strong pull-up strong pull-down VDD weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable data output data input analog input select analog input 002aaf272 pin configured as digital output driver pin configured as digital input pin configured as analog input LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 75 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.5 Reset pin configuration Fig 38. Reset pin configuration VSS reset 002aaf274 VDD VDD VDD Rpu ESD ESD 20 ns RC GLITCH FILTER PIN LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 76 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 15.6 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for part LPC1768. [1] IEC levels refer to Appendix D in the IEC61967-2 Specification. Table 25. ElectroMagnetic Compatibility (EMC) for part LPC1768 (TEM-cell method) VDD = 3.3 V; Tamb = 25 C. Parameter Frequency band System clock = Unit 12 MHz 24 MHz 48 MHz 72 MHz 100 MHz Input clock: IRC (4 MHz) maximum peak level 150 kHz to 30 MHz 7 6 4 7 7 dBV 30 MHz to 150 MHz +1 +5 +11 +16 +9 dBV 150 MHz to 1 GHz 2 +4 +11 +12 +19 dBV IEC level[1] - O O N M L - Input clock: crystal oscillator (12 MHz) maximum peak level 150 kHz to 30 MHz 5 4 4 7 8 dBV 30 MHz to 150 MHz 1 +5 +10 +15 +7 dBV 150 MHz to 1 GHz 1 +6 +11 +10 +16 dBV IEC level[1] - O O N M M - LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 77 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 16. Package outline Fig 39. Package outline SOT407-1 (LQFP100) UNIT A max. A1 A2 A3 bp c E(1) e HE L Lp v w y Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o 1 0.2 0.08 0.08 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT407-1 136E20 MS-026 00-02-01 03-02-20 D(1) (1) (1) 14.1 13.9 HD 16.25 15.75 Z E 1.15 0.85 D bp e θ E A1 A Lp detail X L (A 3 ) B 25 c HD bp HE A2 v M B D ZD A ZE e v M A X 1 100 76 75 51 50 26 y pin 1 index w M w M 0 5 10 mm scale LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 78 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 40. Package outline SOT926-1 (TFBGA100) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT926-1 - - - - - - - - - SOT926-1 05-12-09 05-12-22 UNIT A max mm 1.2 0.4 0.3 0.8 0.65 0.5 0.4 9.1 8.9 9.1 8.9 A1 DIMENSIONS (mm are the original dimensions) TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm A2 b D E e2 7.2 e 0.8 e1 7.2 v 0.15 w 0.05 y 0.08 y1 0.1 0 2.5 5 mm scale b e2 e1 e e 1/2 e 1/2 e ∅ v M C A B ∅ w M C ball A1 index area A B C D E F H K G J 1 2 3 4 5 6 7 8 9 10 ball A1 index area B A E D C y1 C y X detail X A A1 A2 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 79 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 41. Package outline LPC1768UK (WLCSP100) Outline References version European projection Issue date IEC JEDEC JEITA wlcsp100_lpc1768uk_po Unit mm max nom min 0.65 0.60 0.55 0.27 0.24 0.21 0.35 0.32 0.29 5.104 5.074 5.044 5.104 5.074 5.044 4.5 4.5 0.15 A Dimensions (mm are the original dimensions) A1 A2 0.385 0.360 0.335 b D E 0.05 e y 0.5 e1 e2 v 0.05 w ball A1 index area X detail X C y A A2 A1 ball A1 index area LPC1768UK 11-10-19 13-11-04 WLCSP100: wafer level chip-scale package; 100 balls; 5.074 x 5.074 x 0.6 mm LPC1768UK 0 scale 3 mm D B E A 1 K J H G F E D C B A 2 3 4 5 6 7 8 9 10 e1 e b Ø v C A B Ø w C 1/2 e e2 e 1/2 e LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 80 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 17. Soldering Fig 42. Reflow soldering for the LQFP100 package SOT407-1 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP100 package Ax Bx Gx Hy Gy Hx By Ay P2 P1 D2 (8×) D1 (0.125) P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy sot407-1 solder land C Generic footprint pattern Refer to the package outline drawing for actual layout 0.500 0.560 17.300 17.300 14.300 14.300 1.500 0.280 0.400 14.500 14.500 17.550 17.550 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 81 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 43. Reflow soldering of the TFBGA100 package DIMENSIONS in mm P SL SP SR Hx Hy Hx Hy SOT926-1 solder land plus solder paste occupied area Footprint information for reflow soldering of TFBGA100 package solder land solder paste deposit solder resist P P SL SP SR Generic footprint pattern Refer to the package outline drawing for actual layout detail X see detail X sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 82 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 18. Abbreviations Table 26. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DMA Direct Memory Access EOP End Of Packet GPIO General Purpose Input/Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop PWM Pulse Width Modulator RIT Repetitive Interrupt Timer RMII Reduced Media Independent Interface SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TCM Tightly Coupled Memory TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 83 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 19. Revision history Table 27. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1769_68_67_66_65_64_63 v.9.4 20140404 Product data sheet - LPC1769_68_67_66_65_64 v.9.3 Modifications: • Added LPC1768UK. • Table 5 “Pin description”: Changed RX_MCLK and TX_MCLK type from INPUT to OUTPUT. LPC1769_68_67_66_65_64_63 v.9.3 20140108 Product data sheet - LPC1769_68_67_66_65_64 v.9.2 Modifications: • Table 7 “Thermal resistance (±15 %)”: – Added TFBGA100. – Added 15 % to table title. LPC1769_68_67_66_65_64_63 v.9.2 20131021 Product data sheet - LPC1769_68_67_66_65_64 v.9.1 Modifications: • Table 8 “Static characteristics”: – Added Table note 3 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” – Added Table note 4 “VDDA for DAC specs are from 2.7 V to 3.6 V.” – VDDA/VREFP spec changed from 2.7 V to 2.5 V. • Table 19 “ADC characteristics (full resolution)”: – Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” – VDDA changed from 2.7 V to 2.5 V. • Table 20 “ADC characteristics (lower resolution)”: Added Table note 1 “VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.” LPC1769_68_67_66_65_64_63 v.9.1 20130916 Product data sheet - LPC1769_68_67_66_65_64 v.9 Modifications: • Added Table 7 “Thermal resistance”. • Table 6 “Limiting values”: – Updated min/max values for VDD(3V3) and VDD(REG)(3V3). – Updated conditions for VI. – Updated table notes. • Table 8 “Static characteristics”: Added Table note 15 “TCK/SWDCLK pin needs to be externally pulled LOW.” • Updated Section 15.1 “Suggested USB interface solutions”. • Added Section 5 “Marking”. • Changed title of Figure 31 from “USB interface on a self-powered device” to “USB interface with soft-connect”. LPC1769_68_67_66_65_64_63 v.9 20120810 Product data sheet - LPC1769_68_67_66_65_64 v.8 Modifications: • Remove table note “The peak current is limited to 25 times the corresponding maximum current.” from Table 5 “Limiting values”. • Change VDD(3V3) to VDD(REG)(3V3) in Section 11.3 “Internal oscillators”. • Glitch filter constant changed to 10 ns in Table note 6 in Table 4. • Description of RESET function updated in Table 4. • Pull-up value added for GPIO pins in Table 4. • Pin configuration diagram for LQFP100 package corrected (Figure 2). LPC1769_68_67_66_65_64_63 v.8 20111114 Product data sheet - LPC1769_68_67_66_65_64 v.7 LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 84 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Modifications: • Pin description of USB_UP_LED pin updated in Table 4. • Ri1 and Ri2 labels in Figure 27 updated. • Part LPC1765FET100 added. • Table note 10 updated in Table 4. • Table note 1 updated in Table 12. • Pin description of STCLK pin updated in Table 4. • Electromagnetic compatibility data added in Section 14.6. • Section 16 added. LPC1769_68_67_66_65_64_63 v.7 20110405 Product data sheet - LPC1769_68_67_66_65_64 v.6 Modifications: • Pin description of pins P0[29] and P0[30] updated in Table note 5 of Table 4. Pins are not 5 V tolerant. • Typical value for Parameter Nendu added in Table 9. • Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD(3V3) in Table 7. • Condition 3.0 V  VDD(3V3)  3.6 V added in Table 16. • Typical values for parameters IDD(REG)(3V3) and IBAT with condition Deep power-down mode corrected in Table 7 and Table note 9, Table note 10, and Table note 11 updated. • For Deep power-down mode, Figure 9 updated and Figure 10 added. LPC1769_68_67_66_65_64_63 v.6 20100825 Product data sheet - LPC1769_68_67_66_65_64 v.5 Modifications: • Part LPC1768TFBGA added. • Section 7.30.2; BOD level corrected. • Added Section 10.2. LPC1769_68_67_66_65_64_63 v.5 20100716 Product data sheet - LPC1769_68_67_66_65_64 v.4 LPC1769_68_67_66_65_64 v.4 20100201 Product data sheet - LPC1768_67_66_65_64 v.3 LPC1768_67_66_65_64 v.3 20091119 Product data sheet - LPC1768_66_65_64 v.2 LPC1768_66_65_64 v.2 20090211 Objective data sheet - LPC1768_66_65_64 v.1 LPC1768_66_65_64 v.1 20090115 Objective data sheet - - Table 27. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 85 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 86 of 88 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.4 — 4 April 2014 87 of 88 continued >> NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Functional description . . . . . . . . . . . . . . . . . . 21 8.1 Architectural overview . . . . . . . . . . . . . . . . . . 21 8.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 21 8.3 On-chip flash program memory . . . . . . . . . . . 21 8.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 Memory Protection Unit (MPU). . . . . . . . . . . . 21 8.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24 8.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24 8.9 General purpose DMA controller . . . . . . . . . . 24 8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10 Fast general purpose parallel I/O . . . . . . . . . . 25 8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 27 8.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 28 8.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 28 8.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 CAN controller and acceptance filters . . . . . . 28 8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 30 8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 30 8.18.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . 31 8.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 32 8.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 32 8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 33 8.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 34 8.24 Quadrature Encoder Interface (QEI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 35 8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.26 ARM Cortex-M3 system tick timer . . . . . . . . . 35 8.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 35 8.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.28 RTC and backup registers . . . . . . . . . . . . . . . 36 8.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.29 Clocking and power control . . . . . . . . . . . . . . 36 8.29.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36 8.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 37 8.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37 8.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 38 8.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 38 8.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 38 8.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 39 8.29.6.3 Power-down mode. . . . . . . . . . . . . . . . . . . . . 40 8.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 40 8.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 40 8.29.7 Peripheral power control . . . . . . . . . . . . . . . . 40 8.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 41 8.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 43 8.30.3 Code security (Code Read Protection - CRP) . . . . . . . . . . . 43 8.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 44 8.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 44 8.30.7 Memory mapping control . . . . . . . . . . . . . . . . 44 8.31 Emulation and debugging . . . . . . . . . . . . . . . 44 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 April 2014 Document identifier: LPC1769_68_67_66_65_64_63 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Thermal characteristics . . . . . . . . . . . . . . . . . 46 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 47 11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 50 11.2 Peripheral power consumption . . . . . . . . . . . . 53 11.3 Electrical pin characteristics . . . . . . . . . . . . . . 54 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 56 12.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 57 12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.6 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 59 12.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 62 12.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13 ADC electrical characteristics . . . . . . . . . . . . 65 14 DAC electrical characteristics . . . . . . . . . . . . 68 15 Application information. . . . . . . . . . . . . . . . . . 69 15.1 Suggested USB interface solutions . . . . . . . . 69 15.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . 73 15.4 Standard I/O pin configuration . . . . . . . . . . . . 74 15.5 Reset pin configuration. . . . . . . . . . . . . . . . . . 75 15.6 ElectroMagnetic Compatibility (EMC) . . . . . . . 76 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 77 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 82 19 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 83 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 85 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 85 20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 21 Contact information. . . . . . . . . . . . . . . . . . . . . 86 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1. General description The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I2C-bus (serial clock (SCL), serial data (SDA)). The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three hardware address inputs and interrupt output operating between 2.5 V and 6 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. System master can read from the input port or write to the output port through a single register. The low current consumption of 2.5 A (typical, static) is great for mobile applications and the latched output ports directly drive LEDs. The PCF8574 and PCF8574A are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I2C-bus, so there can be up to 16 of these I/O expanders PCF8574/74A together on the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs). The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic of the microcontroller and is activated when any input state differs from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogated without the microcontroller continuously polling the input register via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source. 2. Features and benefits  I2C-bus to parallel port expander  100 kHz I2C-bus interface (Standard-mode I2C-bus)  Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD with 100 A current source  8-bit remote I/O pins that default to inputs at power-up  Latched outputs directly drive LEDs  Total package sink capability of 80 mA  Active LOW open-drain interrupt output  Eight programmable slave addresses using three address pins  Low standby current (2.5 A typical)  40 C to +85 C operation  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Rev. 5 — 27 May 2013 Product data sheet PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 2 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt  Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA  Packages offered: DIP16, SO16, SSOP20 3. Applications  LED signs and displays  Servers  Key pads  Industrial control  Medical equipment  PLC  Cellular telephones  Mobile devices  Gaming machines  Instrumentation and test measurement 4. Ordering information 4.1 Ordering options Table 1. Ordering information Type number Topside mark Package Name Description Version PCF8574P PCF8574P DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 PCF8574AP PCF8574AP PCF8574T/3 PCF8574T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 PCF8574AT/3 PCF8574AT PCF8574TS/3 8574TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 PCF8574ATS/3 8574A Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature range PCF8574P PCF8574P,112 DIP16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCF8574AP PCF8574AP,112 DIP16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCF8574T/3 PCF8574T/3,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCF8574T/3,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCF8574AT/3 PCF8574AT/3,512 SO16 Standard marking * tube dry pack 1920 Tamb = 40 C to +85 C PCF8574AT/3,518 SO16 Reel 13” Q1/T1 *standard mark SMD dry pack 1000 Tamb = 40 C to +85 C PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 3 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 5. Block diagram PCF8574TS/3 PCF8574TS/3,112 SSOP20 Standard marking * IC’s tube - DSC bulk pack 1350 Tamb = 40 C to +85 C PCF8574TS/3,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C PCF8574ATS/3 PCF8574ATS/3,118 SSOP20 Reel 13” Q1/T1 *standard mark SMD 2500 Tamb = 40 C to +85 C Table 2. Ordering options …continued Type number Orderable part number Package Packing method Minimum order quantity Temperature range Fig 1. Block diagram Fig 2. Simplified schematic diagram of P0 to P7 002aad624 INT I2C-BUS CONTROL LP FILTER PCF8574 PCF8574A INTERRUPT LOGIC A0 A1 A2 INPUT FILTER SHIFT REGISTER SDA SCL 8 bits write pulse read pulse POWER-ON VDD RESET VSS I/O PORT P0 P1 P2 P3 P4 P5 P6 P7 002aac109 write pulse read pulse D CI S FF Q power-on reset data from Shift Register Itrt(pu) 100 μA IOH IOL VDD P0 to P7 VSS D CI S FF Q data to Shift Register to interrupt logic PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 4 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration for DIP16 Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for SSOP20 PCF8574P PCF8574AP A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 002aad625 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 A0 VDD A1 SDA A2 SCL P0 INT P1 P7 P2 P6 P3 P5 VSS P4 PCF8574T/3 PCF8574AT/3 002aad626 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 PCF8574TS/3 PCF8574ATS/3 P7 SCL P6 n.c. n.c. SDA P5 P4 A0 A1 P3 n.c. n.c. A2 P2 P0 P1 002aad627 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 VDD INT VSS Table 3. Pin description Symbol Pin Description DIP16, SO16 SSOP20 A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 VSS 8 15 supply ground P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line VDD 16 5 supply voltage n.c. - 3, 8, 13, 18 not connected PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 5 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 7. Functional description Refer to Figure 1 “Block diagram”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address format of the PCF8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or LOW to choose one of eight slave addresses. To conserve power, no internal pull-up resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW. The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors. The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation (write operation is shown in Figure 6). 7.1.1 Address maps The PCF8574 and PCF8574A are functionally the same, but have a different fixed portion (A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the PCF8574A to be on the same I2C-bus without address conflict. a. PCF8574 b. PCF8574A Fig 6. PCF8574 and PCF8574A slave addresses R/W 002aad628 0 1 0 0 A2 A1 A0 hardware selectable slave address 0 fixed R/W 002aad629 0 1 1 1 A2 A1 A0 hardware selectable slave address 0 fixed Table 4. PCF8574 address map Pin connectivity Address of PCF8574 Address byte value 7-bit hexadecimal address without R/W A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read VSS VSS VSS 0 1 0 0 0 0 0 - 40h 41h 20h VSS VSS VDD 0 1 0 0 0 0 1 - 42h 43h 21h VSS VDD VSS 0 1 0 0 0 1 0 - 44h 45h 22h VSS VDD VDD 0 1 0 0 0 1 1 - 46h 47h 23h VDD VSS VSS 0 1 0 0 1 0 0 - 48h 49h 24h VDD VSS VDD 0 1 0 0 1 0 1 - 4Ah 4Bh 25h VDD VDD VSS 0 1 0 0 1 1 0 - 4Ch 4Dh 26h VDD VDD VDD 0 1 0 0 1 1 1 - 4Eh 4Fh 27h PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 6 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8. I/O programming 8.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O is an input or output port without using a direction control register. Whenever the master reads the register, the value returned to master depends on the actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte. Advantages of the quasi-bidirectional I/O over totem pole I/O include: • Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O have both n-channel and p-channel transistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels. • Simpler architecture — only a single register and the I/O can be both input and output at the same time. Totem pole I/O have a direction register that specifies the port pin direction and it is always in that configuration unless the direction is explicitly changed. • Does not require a command byte. The simplicity of one register (no need for the pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations. Table 5. PCF8574A address map Pin connectivity Address of PCF8574A Address byte value 7-bit hexadecimal address without R/W A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W Write Read VSS VSS VSS 0 1 1 1 0 0 0 - 70h 71h 38h VSS VSS VDD 0 1 1 1 0 0 1 - 72h 73h 39h VSS VDD VSS 0 1 1 1 0 1 0 - 74h 75h 3Ah VSS VDD VDD 0 1 1 1 0 1 1 - 76h 77h 3Bh VDD VSS VSS 0 1 1 1 1 0 0 - 78h 79h 3Ch VDD VSS VDD 0 1 1 1 1 0 1 - 7Ah 7Bh 3Dh VDD VDD VSS 0 1 1 1 1 1 0 - 7Ch 7Dh 3Eh VDD VDD VDD 0 1 1 1 1 1 1 - 7Eh 7Fh 3Fh PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 7 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW. Input HIGH: The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1. Input LOW: The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100 A current source, then the master will read the value of 0. Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH. Output LOW: The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time. Fig 7. Simple quasi-bidirectional I/O 002aah683 VDD weak 100 μA current source (inactive when output LOW) output HIGH VSS output LOW accelerator P port pull-up P7 - P0 pull-down with resistor to VSS or external drive LOW input LOW pull-up with resistor to VDD or external drive HIGH input HIGH PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 8 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8.2 Writing to the port (Output mode) The master (microcontroller) sends the START condition and slave address setting the last bit of the address byte to logic 0 for the write mode. The PCF8574/74A acknowledges and the master then sends the data byte for P7 to P0 to the port register. As the clock line goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by the PCF8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is written, the strong pull-up turns on for 1⁄2 of the clock cycle, then the line is held HIGH by the weak current source. The master can then send a STOP or ReSTART condition or continue sending data. The number of data bytes that can be sent successively is not limited and the previous data is overwritten every time a data byte has been sent and acknowledged. Ensure a logic 1 is written for any port that is being used as an input to ensure the strong external pull-down is turned off. Simple code WRITE mode: ...

Remark: Bold type = generated by slave device. Fig 8. Write mode (output) S A6 A5 A4 A3 A2 A1 A0 0 A slave address START condition R/W acknowledge from slave 002aah349 P7 P6 1 data 1 A acknowledge from slave SCL 1 2 3 4 5 6 7 8 9 SDA A acknowledge from slave write to port data output from port tv(Q) P5 data 2 DATA 2 VALID P4 P3 P2 P1 P0 P7 P6 P4 P3 P2 P1 P0 P5 0 tv(Q) DATA 1 VALID P5 output voltage Itrt(pu) IOH P5 pull-up output current td(rst) INT PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 9 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8.3 Reading from a port (Input mode) The port must have been previously written to logic 1, which is the condition after power-on reset. To enter the Read mode the master (microcontroller) addresses the slave device and sets the last bit of the address byte to logic 1 (address byte read). The slave will acknowledge and then send the data byte to the master. The master will NACK and then send the STOP condition or ACK and read the input register again. The read of any pin being used as an output will indicate HIGH or LOW depending on the actual state of the pin. If the data on the input port changes faster than the master can read, this data may be lost. The DATA 2 and DATA3 are lost because these data did not meet the setup time and hold time (see Figure 9). Simple code for Read mode: ...

Remark: Bold type = generated by slave device. 8.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCF8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCF8574/74A registers and I2C-bus/SMBus state machine will initialize to their default states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be lowered below VPOR and back up to the operation voltage for power-on reset cycle. A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Fig 9. Read mode (input) S A6 A5 A4 A3 A2 A1 A0 1 A slave address START condition R/W acknowledge from slave 002aah383 data from port A acknowledge from master SDA 1 no acknowledge from master read from port data at port data from port DATA 1 DATA 4 INT DATA 4 DATA 2 DATA 3 P STOP condition tv(INT) trst(INT) th(D) tsu(D) trst(INT) DATA 1 PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 10 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8.5 Interrupt output (INT) The PCF8574/74A provides an open-drain output (INT) which can be fed to a corresponding input of the microcontroller (see Figure 10). As soon as a port input is changed, the INT will be active (LOW) and notify the microcontroller. An interrupt is generated at any rising or falling edge of the port inputs. After time tv(Q), the signal INT is valid. The interrupt will reset to HIGH when data on the port is changed to the original setting or data is read or written by the master. In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the acknowledge bit of the address byte and also on the rising edge of the write to port pulse. The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see Figure 8). The interrupt is reset (HIGH) in the Read mode on the rising edge of the read from port pulse (see Figure 9). During the interrupt reset, any I/O change close to the read or write pulse may not generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is reset, any change in I/Os will be detected and transmitted as an INT. At power-on reset all ports are in Input mode and the initial state of the ports is HIGH, therefore, for any port pin that is pulled LOW or driven LOW by external source, the interrupt output will be active (output LOW). Fig 10. Application of multiple PCF8574/74As with interrupt 002aad634 VDD MICROCONTROLLER INT PCF8574 INT PCF8574 INT device 1 device 2 PCF8574A INT device 16 PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 11 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-wire communication between different ICs or modules. The two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11). 9.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 12). 9.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 13). Fig 11. Bit transfer mba607 data line stable; data valid change of data allowed SDA SCL Fig 12. Definition of START and STOP conditions mba608 SDA SCL P STOP condition S START condition PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 12 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated by the receiving device) that indicates to the transmitter that the data transfer was successful. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that wants to issue an acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge bit related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Fig 13. System configuration 002aaa966 MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL I2C-BUS MULTIPLEXER SLAVE Fig 14. Acknowledgement on the I2C-bus 002aaa987 S START condition 1 2 8 9 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver SCL from master PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 13 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 10. Application design-in information 10.1 Bidirectional I/O expander applications In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to P7). If 10 A internal output HIGH is not enough current source, the port needs external pull-up resistor. During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there has been a change of data on its ports without having to communicate via the I2C-bus. 10.2 How to read and write to I/O expander (example) In the application example of PCF8574 shown in Figure 15, the microcontroller wants to control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes. 1. When the system power on: Core Processor needs to issue an initial command to set P0 and P1 as inputs and P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off, switch off and latch off). 2. Operation: When the temperature changes above the threshold, the temperature sensor signal will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core processor’ that there have been changes on the input pins. Read the input register. If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch. 3. Software code: //System Power on // write to PCF8574 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs <0100 0000> <1010 0011>

//Initial setting for PCF9574 Fig 15. Bidirectional I/O expander application 002aah384 VDD temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3 P0 P1 P2 P3 P4 P5 P6 P7 VDD SDA SCL INT A0 A1 A2 CORE PROCESSOR VDD PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 14 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt while (INT == 1); //Monitor the interrupt pin. If INT = 1 do nothing //When INT = 0 then read input ports <1010 0010>

//Read PCF8574 data If (P0 == 0) //Temperature sensor activated { // write to PCF8574 with data 0010 1011b to turn on LED (P7), on Switch (P3) and keep P[1:0] as input ports. <0100 0000> <0010 1011>

// Write to PCF8574 } 10.3 High current-drive load applications The GPIO has a minimum guaranteed sinking current of 10 mA per bit at 5 V. In applications requiring additional drive, two port pins may be connected together to sink up to 20 mA current. Both bits must then always be turned on or off together. Up to five pins can be connected together to drive 80 mA, which is the device recommended total limit. Each pin needs its own limiting resistor as shown in Figure 16 to prevent damage to the device should all ports not be turned on at the same time. 10.4 Migration path NXP offers newer, more capable drop-in replacements for the PCF8574/74A in newer space-saving packages. PCA9670 replaces the interrupt output of the PCA9674 with hardware reset input to retain the maximum number of addresses and the PCA9672 replaces address A2 of the PCA9674 with hardware reset input to retain the interrupt but limit the number of addresses. Fig 16. High current-drive load application 002aah385 VDD P0 P1 P2 P3 P4 P5 P6 P7 VDD SDA SCL INT A0 A1 A2 CORE PROCESSOR VDD LOAD Table 6. Migration path Type number I2C-bus frequency Voltage range Number of addresses per device Interrupt Reset Total package sink current PCF8574/74A 100 kHz 2.5 V to 6 V 8 yes no 80 mA PCA8574/74A 400 kHz 2.3 V to 5.5 V 8 yes no 200 mA PCA9674/74A 1 MHz Fm+ 2.3 V to 5.5 V 64 yes no 200 mA PCA9670 1 MHz Fm+ 2.3 V to 5.5 V 64 no yes 200 mA PCA9672 1 MHz Fm+ 2.3 V to 5.5 V 16 yes yes 200 mA PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 15 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 11. Limiting values 12. Thermal characteristics Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +7 V IDD supply current - 100 mA ISS ground supply current - 100 mA VI input voltage VSS  0.5 VDD + 0.5 V II input current - 20 mA IO output current - 25 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW Tj(max) maximum junction temperature - 125 C Tstg storage temperature 65 +150 C Tamb ambient temperature operating 40 +85 C Table 8. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient SO16 package 115 C/W SSOP20 package 136 C/W PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 16 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 13. Static characteristics [1] The power-on reset circuit resets the I2C-bus logic at VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD). Table 9. Static characteristics VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.5 - 6.0 V IDD supply current operating mode; VDD = 6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 40 100 A Istb standby current standby mode; VDD = 6 V; no load; VI = VDD or VSS - 2.5 10 A VPOR power-on reset voltage VDD = 6 V; no load; VI = VDD or VSS [1]- 1.3 2.4 V Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V IOL LOW-level output current VOL = 0.4 V 3 - - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - - 7 pF I/Os; P0 to P7 VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V IIHL(max) maximum allowed input current through protection diode VI  VDD or VI  VSS - - 400 A IOL LOW-level output current VOL = 1 V; VDD = 5 V 10 25 - mA IOH HIGH-level output current VOH = VSS 30 - 300 A Itrt(pu) transient boosted pull-up current HIGH during acknowledge (see Figure 8); VOH = VSS; VDD = 2.5 V - 1 - mA Ci input capacitance - - 10 pF Co output capacitance - - 10 pF Interrupt INT (see Figure 8) IOL LOW-level output current VOL = 0.4 V 1.6 - - mA IL leakage current VI = VDD or VSS 1 - +1 A Select inputs A0, A1, A2 VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current pin at VDD or VSS 250 - +250 nA PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 17 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 14. Dynamic characteristics [1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. Table 10. Dynamic characteristics VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit I2C-bus timing[1] (see Figure 17) fSCL SCL clock frequency - - 100 kHz tBUF bus free time between a STOP and START condition 4.7 - - s tHD;STA hold time (repeated) START condition 4 - - s tSU;STA set-up time for a repeated START condition 4.7 - - s tSU;STO set-up time for STOP condition 4 - - s tHD;DAT data hold time 0 - - ns tVD;DAT data valid time - - 3.4 s tSU;DAT data set-up time 250 - - ns tLOW LOW period of the SCL clock 4.7 - - s tHIGH HIGH period of the SCL clock 4 - - s tr rise time of both SDA and SCL signals - - 1 s tf fall time of both SDA and SCL signals - - 0.3 s Port timing (see Figure 8 and Figure 9) tv(Q) data output valid time CL  100 pF - - 4 s tsu(D) data input set-up time CL  100 pF 0 - - s th(D) data input hold time CL  100 pF 4 - - s Interrupt INT timing (see Figure 9) tv(INT) valid time on pin INT from port to INT; CL  100 pF - - 4 s trst(INT) reset time on pin INT from SCL to INT; CL  100 pF - - 4 s PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 18 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Rise and fall times refer to VIL and VIH. Fig 17. I2C-bus timing diagram 002aab175 protocol START condition (S) bit 7 MSB (A7) bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) SCL SDA tHD;STA tSU;DAT tHD;DAT tBUF tf tSU;STA tLOW tHIGH tVD;ACK tSU;STO 1 / fSCL tr tVD;DAT 0.3 × VDD 0.7 × VDD 0.3 × VDD 0.7 × VDD PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 19 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 15. Package outline Fig 18. Package outline SOT38-4 (DIP16) OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT38-4 95-01-14 03-02-13 MH c (e 1 ) ME A L seating plane A1 w M b1 b2 e D A2 Z 16 1 9 8 E pin 1 index b 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. UNIT A max. 1 2 b1 (1) (1) (1) b2 c D E e M Z L H mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A min. A max. b max. e1 ME w 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 2.54 7.62 0.254 8.25 7.80 10.0 8.3 4.2 0.51 3.2 0.76 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.12 0.1 0.3 0.01 0.32 0.31 0.39 0.33 0.17 0.02 0.13 0.03 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 20 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Fig 19. Package outline SOT162-1 (SO16) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT162-1 8 16 w M bp D detail X Z e 9 1 y 0.25 075E03 MS-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.41 0.40 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 X θ A A1 A2 HE Lp Q E c L v M A (A 3 ) A 0 5 10 mm scale SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 99-12-27 03-02-19 PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 21 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt Fig 20. Package outline SOT266-1 (SSOP20) UNIT A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z (1) θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0 1.4 1.2 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 1 0.2 6.6 6.2 0.65 0.45 0.48 0.18 10 0 o 0.13 0.1 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. 0.75 0.45 SOT266-1 MO-152 99-12-27 03-02-19 w M θ A A1 A2 bp D HE Lp Q detail X E Z e c L v M A X (A 3 ) A y 0.25 1 10 20 11 pin 1 index 0 2.5 5 mm scale SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 A max. 1.5 PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 22 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 17.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • Board specifications, including the board finish, solder masks and vias • Package footprints, including solder thieves and orientation • The moisture sensitivity level of the packages • Package placement • Inspection and repair • Lead-free soldering versus SnPb soldering 17.3 Wave soldering Key characteristics in wave soldering are: PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 23 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21. Table 11. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 12. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 5 — 27 May 2013 24 of 33 NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Soldering of through-hole mount packages 18.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 18.2 Soldering by dipping or by solder wave Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds