Farnell PDF LUMINARY MICRO - Stellaris LM3S2965 Microcontroller Data Sheet (Rev. F) - Farnell Element 14

LUMINARY MICRO - Stellaris LM3S2965 Microcontroller Data Sheet (Rev. F) - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

Miniature

Everything You Need To Know About Arduino

Miniature

Tutorial 01 for Arduino: Getting Acquainted with Arduino

Miniature

The Cube® 3D Printer

Miniature

What's easier- DIY Dentistry or our new our website features?

 

Miniature

Ben Heck's Getting Started with the BeagleBone Black Trailer

Miniature

Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

Miniature

Get Started with Pi Episode 3 - Online with Raspberry Pi

Miniature

Discover Simulink Promo -- Exclusive element14 Webinar

Miniature

Ben Heck's TV Proximity Sensor Trailer

Miniature

Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

Miniature

Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

Miniature

Ben Heck Anti-Pickpocket Wallet Trailer

Miniature

Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

Miniature

Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

Miniature

Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

Miniature

Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

Miniature

3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

Miniature

3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

Miniature

Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

Miniature

Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

Miniature

Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

Miniature

Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

Miniature

Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

Miniature

Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

Miniature

Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

Miniature

3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

Miniature

Innovative LPS Resistor Features Very High Power Dissipation

Miniature

Charge Injection Evaluation Board for DG508B Multiplexer Demo

Miniature

Ben Heck The Great Glue Gun Trailer Part 2

Miniature

Introducing element14 TV

Miniature

Ben Heck Time to Meet Your Maker Trailer

Miniature

Détecteur de composants

Miniature

Recherche intégrée

Miniature

Ben Builds an Accessibility Guitar Trailer Part 1

Miniature

Ben Builds an Accessibility Guitar - Part 2 Trailer

Miniature

PiFace Control and Display Introduction

Miniature

Flashmob Farnell

Miniature

Express Yourself in 3D with Cube 3D Printers from Newark element14

Miniature

Farnell YouTube Channel Move

Miniature

Farnell: Design with the best

Miniature

French Farnell Quest

Miniature

Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

Miniature

Cy-Net3 Network Module

Miniature

MC AT - Professional and Precision Series Thin Film Chip Resistors

Miniature

Solderless LED Connector

Miniature

PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

Miniature

3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

Miniature

Voltage Level Translation

Puce électronique / Microchip :

Miniature

Microchip - 8-bit Wireless Development Kit

Miniature

Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

Miniature

Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

Miniature

Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

Miniature

Microchip - 8-bit Wireless Development Kit

Miniature

Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

Miniature

Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

Miniature

Texas Instruments - Automotive LED Headlights

Miniature

Texas Instruments - Digital Power Solutions

Miniature

Texas Instruments - Industrial Sensor Solutions

Miniature

Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

Miniature

Texas Instruments - Industrial Automation System Components

Miniature

Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

Miniature

Texas Instruments - TMS320C66x KeyStone Multicore Architecture

Miniature

Texas Instruments - Industrial Interfaces

Miniature

Texas Instruments - Concerto™ MCUs - Connectivity without compromise

Miniature

Texas Instruments - Stellaris Robot Chronos

Miniature

Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

Miniature

Ask Ben Heck - Connect Raspberry Pi to Car Computer

Miniature

Ben's Portable Raspberry Pi Computer Trailer

Miniature

Ben's Raspberry Pi Portable Computer Trailer 2

Miniature

Ben Heck's Pocket Computer Trailer

Miniature

Ask Ben Heck - Atari Computer

Miniature

Ask Ben Heck - Using Computer Monitors for External Displays

Miniature

Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

Miniature

Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

Miniature

Raspberry Pi Served - Joey Hudy

Miniature

Happy Birthday Raspberry Pi

Miniature

Raspberry Pi board B product overview

Logiciels :

Miniature

Ask Ben Heck - Best Opensource or Free CAD Software

Miniature

Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

Miniature

Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

Miniature

Introduction to Cadsoft EAGLE PCB Design Software in Chinese

Miniature

Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

Miniature

Ben Heck The Great Glue Gun Trailer Part 1

Miniature

the knode tutorial - element14

Miniature

Ben's Autodesk 123D Tutorial Trailer

Miniature

Ben's CadSoft EAGLE Tutorial Trailer

Miniature

Ben Heck's Soldering Tutorial Trailer

Miniature

Ben Heck's AVR Dev Board tutorial

Miniature

Ben Heck's Pinball Tutorial Trailer

Miniature

Ben Heck's Interface Tutorial Trailer

Miniature

First Stage with Python and PiFace Digital

Miniature

Cypress - Getting Started with PSoC® 3 - Part 2

Miniature

Energy Harvesting Challenge

Miniature

New Features of CadSoft EAGLE v6

Autres documentations :

 [TXT] Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K  

[TXT]

 Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06  959K  

[TXT]

 Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06  969K  

[TXT]

 Farnell-Datasheet-NX..> 15-Jul-2014 17:06  1.0M  

[TXT]

 Farnell-Datasheet-Fa..> 15-Jul-2014 17:05  1.0M  

[TXT]

 Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05  1.0M  

[TXT]

 Farnell-SERIAL-TFT-M..> 15-Jul-2014 17:05  1.0M  

[TXT]

 Farnell-MCOC1-Farnel..> 15-Jul-2014 17:05  1.0M

[TXT]

 Farnell-TMR-2-series..> 15-Jul-2014 16:48  787K  

[TXT]

 Farnell-DC-DC-Conver..> 15-Jul-2014 16:48  781K  

[TXT]

 Farnell-Full-Datashe..> 15-Jul-2014 16:47  803K  

[TXT]

 Farnell-TMLM-Series-..> 15-Jul-2014 16:47  810K  

[TXT]

 Farnell-TEL-5-Series..> 15-Jul-2014 16:47  814K  

[TXT]

 Farnell-TXL-series-t..> 15-Jul-2014 16:47  829K  

[TXT]

 Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47  837K  

[TXT]

 Farnell-AC-DC-Power-..> 15-Jul-2014 16:47  845K  

[TXT]

 Farnell-TIS-Instruct..> 15-Jul-2014 16:47  845K  

[TXT]

 Farnell-TOS-tracopow..> 15-Jul-2014 16:47  852K  

[TXT]

 Farnell-TCL-DC-traco..> 15-Jul-2014 16:46  858K  

[TXT]

 Farnell-TIS-series-t..> 15-Jul-2014 16:46  875K  

[TXT]

 Farnell-TMR-2-Series..> 15-Jul-2014 16:46  897K  

[TXT]

 Farnell-TMR-3-WI-Ser..> 15-Jul-2014 16:46  939K  

[TXT]

 Farnell-TEN-8-WI-Ser..> 15-Jul-2014 16:46  939K  

[TXT]

 Farnell-Full-Datashe..> 15-Jul-2014 16:46  947K
[TXT]

 Farnell-HIP4081A-Int..> 07-Jul-2014 19:47  1.0M  

[TXT]

 Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47  1.1M  

[TXT]

 Farnell-DG411-DG412-..> 07-Jul-2014 19:47  1.0M  

[TXT]

 Farnell-3367-ARALDIT..> 07-Jul-2014 19:46  1.2M  

[TXT]

 Farnell-ICM7228-Inte..> 07-Jul-2014 19:46  1.1M  

[TXT]

 Farnell-Data-Sheet-K..> 07-Jul-2014 19:46  1.2M  

[TXT]

 Farnell-Silica-Gel-M..> 07-Jul-2014 19:46  1.2M  

[TXT]

 Farnell-TKC2-Dusters..> 07-Jul-2014 19:46  1.2M  

[TXT]

 Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46  1.2M  

[TXT]

 Farnell-760G-French-..> 07-Jul-2014 19:45  1.2M  

[TXT]

 Farnell-Decapant-KF-..> 07-Jul-2014 19:45  1.2M  

[TXT]

 Farnell-1734-ARALDIT..> 07-Jul-2014 19:45  1.2M  

[TXT]

 Farnell-Araldite-Fus..> 07-Jul-2014 19:45  1.2M  

[TXT]

 Farnell-fiche-de-don..> 07-Jul-2014 19:44  1.4M  

[TXT]

 Farnell-safety-data-..> 07-Jul-2014 19:44  1.4M  

[TXT]

 Farnell-A-4-Hardener..> 07-Jul-2014 19:44  1.4M  

[TXT]

 Farnell-CC-Debugger-..> 07-Jul-2014 19:44  1.5M  

[TXT]

 Farnell-MSP430-Hardw..> 07-Jul-2014 19:43  1.8M  

[TXT]

 Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43  1.6M  

[TXT]

 Farnell-CC2531-USB-H..> 07-Jul-2014 19:43  1.8M  

[TXT]

 Farnell-Alimentation..> 07-Jul-2014 19:43  1.8M  

[TXT]

 Farnell-BK889B-PONT-..> 07-Jul-2014 19:42  1.8M  

[TXT]

 Farnell-User-Guide-M..> 07-Jul-2014 19:41  2.0M  

[TXT]

 Farnell-T672-3000-Se..> 07-Jul-2014 19:41  2.0M

 [TXT]Farnell-0050375063-D..> 18-Jul-2014 17:03 2.5M  

[TXT]

 Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03  2.5M  

[TXT]

 Farnell-43031-0002-M..> 18-Jul-2014 17:03  2.5M  

[TXT]

 Farnell-0433751001-D..> 18-Jul-2014 17:02  2.5M  

[TXT]

 Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02  2.5M  

[TXT]

 Farnell-MTX-Compact-..> 18-Jul-2014 17:01  2.5M  

[TXT]

 Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01  2.5M  

[TXT]

 Farnell-ATtiny26-L-A..> 18-Jul-2014 17:00  2.6M  

[TXT]

 Farnell-MCP3421-Micr..> 18-Jul-2014 17:00  1.2M  

[TXT]

 Farnell-LM19-Texas-I..> 18-Jul-2014 17:00  1.2M  

[TXT]

 Farnell-Data-Sheet-S..> 18-Jul-2014 17:00  1.2M  

[TXT]

 Farnell-LMH6518-Texa..> 18-Jul-2014 16:59  1.3M  

[TXT]

 Farnell-AD7719-Low-V..> 18-Jul-2014 16:59  1.4M  

[TXT]

 Farnell-DAC8143-Data..> 18-Jul-2014 16:59  1.5M  

[TXT]

 Farnell-BGA7124-400-..> 18-Jul-2014 16:59  1.5M  

[TXT]

 Farnell-SICK-OPTIC-E..> 18-Jul-2014 16:58  1.5M  

[TXT]

 Farnell-LT3757-Linea..> 18-Jul-2014 16:58  1.6M  

[TXT]

 Farnell-LT1961-Linea..> 18-Jul-2014 16:58  1.6M  

[TXT]

 Farnell-PIC18F2420-2..> 18-Jul-2014 16:57  2.5M  

[TXT]

 Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57  2.5M  

[TXT]

 Farnell-RDS-80-PDF.htm  18-Jul-2014 16:57  1.3M  

[TXT]

 Farnell-AD8300-Data-..> 18-Jul-2014 16:56  1.3M  

[TXT]

 Farnell-LT6233-Linea..> 18-Jul-2014 16:56  1.3M  

[TXT]

 Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56  1.4M  

[TXT]

 Farnell-XPSAF5130-PD..> 18-Jul-2014 16:56  1.4M  

[TXT]

 Farnell-DP83846A-DsP..> 18-Jul-2014 16:55  1.5M  

[TXT]

 Farnell-Dremel-Exper..> 18-Jul-2014 16:55  1.6M

[TXT]

 Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04  1.0M  

[TXT]

 Farnell-SL3S1203_121..> 16-Jul-2014 09:04  1.1M  

[TXT]

 Farnell-PN512-Full-N..> 16-Jul-2014 09:03  1.4M  

[TXT]

 Farnell-SL3S4011_402..> 16-Jul-2014 09:03  1.1M  

[TXT]

 Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03  1.6M  

[TXT]

 Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03  1.7M  

[TXT]

 Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02  2.0M  

[TXT]

 Farnell-LPC1769-68-6..> 16-Jul-2014 09:02  1.9M  

[TXT]

 Farnell-Download-dat..> 16-Jul-2014 09:02  2.2M  

[TXT]

 Farnell-LPC3220-30-4..> 16-Jul-2014 09:02  2.2M  

[TXT]

 Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01  2.4M  

[TXT]

 Farnell-SL3ICS1002-1..> 16-Jul-2014 09:01  2.5M

[TXT]

 Farnell-T672-3000-Se..> 08-Jul-2014 18:59  2.0M  

[TXT]

 Farnell-tesa®pack63..> 08-Jul-2014 18:56  2.0M  

[TXT]

 Farnell-Encodeur-USB..> 08-Jul-2014 18:56  2.0M  

[TXT]

 Farnell-CC2530ZDK-Us..> 08-Jul-2014 18:55  2.1M  

[TXT]

 Farnell-2020-Manuel-..> 08-Jul-2014 18:55  2.1M  

[TXT]

 Farnell-Synchronous-..> 08-Jul-2014 18:54  2.1M  

[TXT]

 Farnell-Arithmetic-L..> 08-Jul-2014 18:54  2.1M  

[TXT]

 Farnell-NA555-NE555-..> 08-Jul-2014 18:53  2.2M  

[TXT]

 Farnell-4-Bit-Magnit..> 08-Jul-2014 18:53  2.2M  

[TXT]

 Farnell-LM555-Timer-..> 08-Jul-2014 18:53  2.2M  

[TXT]

 Farnell-L293d-Texas-..> 08-Jul-2014 18:53  2.2M  

[TXT]

 Farnell-SN54HC244-SN..> 08-Jul-2014 18:52  2.3M  

[TXT]

 Farnell-MAX232-MAX23..> 08-Jul-2014 18:52  2.3M  

[TXT]

 Farnell-High-precisi..> 08-Jul-2014 18:51  2.3M  

[TXT]

 Farnell-SMU-Instrume..> 08-Jul-2014 18:51  2.3M  

[TXT]

 Farnell-900-Series-B..> 08-Jul-2014 18:50  2.3M  

[TXT]

 Farnell-BA-Series-Oh..> 08-Jul-2014 18:50  2.3M  

[TXT]

 Farnell-UTS-Series-S..> 08-Jul-2014 18:49  2.5M  

[TXT]

 Farnell-270-Series-O..> 08-Jul-2014 18:49  2.3M  

[TXT]

 Farnell-UTS-Series-S..> 08-Jul-2014 18:49  2.8M  

[TXT]

 Farnell-Tiva-C-Serie..> 08-Jul-2014 18:49  2.6M  

[TXT]

 Farnell-UTO-Souriau-..> 08-Jul-2014 18:48  2.8M  

[TXT]

 Farnell-Clipper-Seri..> 08-Jul-2014 18:48  2.8M  

[TXT]

 Farnell-SOURIAU-Cont..> 08-Jul-2014 18:47  3.0M  

[TXT]

 Farnell-851-Series-P..> 08-Jul-2014 18:47  3.0M

 [TXT] Farnell-SL59830-Inte..> 06-Jul-2014 10:07 1.0M  

[TXT]

 Farnell-ALF1210-PDF.htm 06-Jul-2014 10:06  4.0M  

[TXT]

 Farnell-AD7171-16-Bi..> 06-Jul-2014 10:06  1.0M  

[TXT]

 Farnell-Low-Noise-24..> 06-Jul-2014 10:05  1.0M  

[TXT]

 Farnell-ESCON-Featur..> 06-Jul-2014 10:05  938K  

[TXT]

 Farnell-74LCX573-Fai..> 06-Jul-2014 10:05  1.9M  

[TXT]

 Farnell-1N4148WS-Fai..> 06-Jul-2014 10:04  1.9M  

[TXT]

 Farnell-FAN6756-Fair..> 06-Jul-2014 10:04  850K  

[TXT]

 Farnell-Datasheet-Fa..> 06-Jul-2014 10:04  861K  

[TXT]

 Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04  867K  

[TXT]

 Farnell-QRE1113-Fair..> 06-Jul-2014 10:03  879K  

[TXT]

 Farnell-2N7002DW-Fai..> 06-Jul-2014 10:03  886K  

[TXT]

 Farnell-FDC2512-Fair..> 06-Jul-2014 10:03  886K  

[TXT]

 Farnell-FDV301N-Digi..> 06-Jul-2014 10:03  886K  

[TXT]

 Farnell-S1A-Fairchil..> 06-Jul-2014 10:03  896K  

[TXT]

 Farnell-BAV99-Fairch..> 06-Jul-2014 10:03  896K  

[TXT]

 Farnell-74AC00-74ACT..> 06-Jul-2014 10:03  911K  

[TXT]

 Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02  911K  

[TXT]

 Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02  924K  

[TXT]

 Farnell-ev-relays-ae..> 06-Jul-2014 10:02  926K  

[TXT]

 Farnell-ESCON-Featur..> 06-Jul-2014 10:02  931K  

[TXT]

 Farnell-Amplifier-In..> 06-Jul-2014 10:02  940K  

[TXT]

 Farnell-Serial-File-..> 06-Jul-2014 10:02  941K  

[TXT]

 Farnell-Both-the-Del..> 06-Jul-2014 10:01  948K  

[TXT]

 Farnell-Videk-PDF.htm   06-Jul-2014 10:01  948K  

[TXT]

 Farnell-EPCOS-173438..> 04-Jul-2014 10:43  3.3M  

[TXT]

 Farnell-Sensorless-C..> 04-Jul-2014 10:42  3.3M  

[TXT]

 Farnell-197.31-KB-Te..> 04-Jul-2014 10:42  3.3M  

[TXT]

 Farnell-PIC12F609-61..> 04-Jul-2014 10:41  3.7M  

[TXT]

 Farnell-PADO-semi-au..> 04-Jul-2014 10:41  3.7M  

[TXT]

 Farnell-03-iec-runds..> 04-Jul-2014 10:40  3.7M  

[TXT]

 Farnell-ACC-Silicone..> 04-Jul-2014 10:40  3.7M  

[TXT]

 Farnell-Series-TDS10..> 04-Jul-2014 10:39  4.0M 

[TXT]

 Farnell-03-iec-runds..> 04-Jul-2014 10:40  3.7M  

[TXT]

 Farnell-0430300011-D..> 14-Jun-2014 18:13  2.0M  

[TXT]

 Farnell-06-6544-8-PD..> 26-Mar-2014 17:56  2.7M  

[TXT]

 Farnell-3M-Polyimide..> 21-Mar-2014 08:09  3.9M  

[TXT]

 Farnell-3M-VolitionT..> 25-Mar-2014 08:18  3.3M  

[TXT]

 Farnell-10BQ060-PDF.htm 14-Jun-2014 09:50  2.4M  

[TXT]

 Farnell-10TPB47M-End..> 14-Jun-2014 18:16  3.4M  

[TXT]

 Farnell-12mm-Size-In..> 14-Jun-2014 09:50  2.4M  

[TXT]

 Farnell-24AA024-24LC..> 23-Jun-2014 10:26  3.1M  

[TXT]

 Farnell-50A-High-Pow..> 20-Mar-2014 17:31  2.9M  

[TXT]

 Farnell-197.31-KB-Te..> 04-Jul-2014 10:42  3.3M  

[TXT]

 Farnell-1907-2006-PD..> 26-Mar-2014 17:56  2.7M  

[TXT]

 Farnell-5910-PDF.htm    25-Mar-2014 08:15  3.0M  

[TXT]

 Farnell-6517b-Electr..> 29-Mar-2014 11:12  3.3M  

[TXT]

 Farnell-A-True-Syste..> 29-Mar-2014 11:13  3.3M  

[TXT]

 Farnell-ACC-Silicone..> 04-Jul-2014 10:40  3.7M  

[TXT]

 Farnell-AD524-PDF.htm   20-Mar-2014 17:33  2.8M  

[TXT]

 Farnell-ADL6507-PDF.htm 14-Jun-2014 18:19  3.4M  

[TXT]

 Farnell-ADSP-21362-A..> 20-Mar-2014 17:34  2.8M  

[TXT]

 Farnell-ALF1210-PDF.htm 04-Jul-2014 10:39  4.0M  

[TXT]

 Farnell-ALF1225-12-V..> 01-Apr-2014 07:40  3.4M  

[TXT]

 Farnell-ALF2412-24-V..> 01-Apr-2014 07:39  3.4M  

[TXT]

 Farnell-AN10361-Phil..> 23-Jun-2014 10:29  2.1M  

[TXT]

 Farnell-ARADUR-HY-13..> 26-Mar-2014 17:55  2.8M  

[TXT]

 Farnell-ARALDITE-201..> 21-Mar-2014 08:12  3.7M  

[TXT]

 Farnell-ARALDITE-CW-..> 26-Mar-2014 17:56  2.7M  

[TXT]

 Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04  2.1M  

[TXT]

 Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55  2.1M  

[TXT]

 Farnell-ATmega640-VA..> 14-Jun-2014 09:49  2.5M  

[TXT]

 Farnell-ATtiny20-PDF..> 25-Mar-2014 08:19  3.6M  

[TXT]

 Farnell-ATtiny26-L-A..> 13-Jun-2014 18:40  1.8M  

[TXT]

 Farnell-Alimentation..> 14-Jun-2014 18:24  2.5M  

[TXT]

 Farnell-Alimentation..> 01-Apr-2014 07:42  3.4M  

[TXT]

 Farnell-Amplificateu..> 29-Mar-2014 11:11  3.3M  

[TXT]

 Farnell-An-Improved-..> 14-Jun-2014 09:49  2.5M  

[TXT]

 Farnell-Atmel-ATmega..> 19-Mar-2014 18:03  2.2M  

[TXT]

 Farnell-Avvertenze-e..> 14-Jun-2014 18:20  3.3M  

[TXT]

 Farnell-BC846DS-NXP-..> 13-Jun-2014 18:42  1.6M  

[TXT]

 Farnell-BC847DS-NXP-..> 23-Jun-2014 10:24  3.3M  

[TXT]

 Farnell-BF545A-BF545..> 23-Jun-2014 10:28  2.1M  

[TXT]

 Farnell-BK2650A-BK26..> 29-Mar-2014 11:10  3.3M  

[TXT]

 Farnell-BT151-650R-N..> 13-Jun-2014 18:40  1.7M  

[TXT]

 Farnell-BTA204-800C-..> 13-Jun-2014 18:42  1.6M  

[TXT]

 Farnell-BUJD203AX-NX..> 13-Jun-2014 18:41  1.7M  

[TXT]

 Farnell-BYV29F-600-N..> 13-Jun-2014 18:42  1.6M  

[TXT]

 Farnell-BYV79E-serie..> 10-Mar-2014 16:19  1.6M  

[TXT]

 Farnell-BZX384-serie..> 23-Jun-2014 10:29  2.1M  

[TXT]

 Farnell-Battery-GBA-..> 14-Jun-2014 18:13  2.0M  

[TXT]

 Farnell-C.A-6150-C.A..> 14-Jun-2014 18:24  2.5M  

[TXT]

 Farnell-C.A 8332B-C...> 01-Apr-2014 07:40  3.4M  

[TXT]

 Farnell-CC2560-Bluet..> 29-Mar-2014 11:14  2.8M  

[TXT]

 Farnell-CD4536B-Type..> 14-Jun-2014 18:13  2.0M  

[TXT]

 Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20  2.1M  

[TXT]

 Farnell-CS5532-34-BS..> 01-Apr-2014 07:39  3.5M  

[TXT]

 Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13  2.8M  

[TXT]

 Farnell-Ceramic-tran..> 14-Jun-2014 18:19  3.4M  

[TXT]

 Farnell-Circuit-Note..> 26-Mar-2014 18:00  2.8M  

[TXT]

 Farnell-Circuit-Note..> 26-Mar-2014 18:00  2.8M  

[TXT]

 Farnell-Cles-electro..> 21-Mar-2014 08:13  3.9M  

[TXT]

 Farnell-Conception-d..> 11-Mar-2014 07:49  2.4M  

[TXT]

 Farnell-Connectors-N..> 14-Jun-2014 18:12  2.1M  

[TXT]

 Farnell-Construction..> 14-Jun-2014 18:25  2.5M  

[TXT]

 Farnell-Controle-de-..> 11-Mar-2014 08:16  2.8M  

[TXT]

 Farnell-Cordless-dri..> 14-Jun-2014 18:13  2.0M  

[TXT]

 Farnell-Current-Tran..> 26-Mar-2014 17:58  2.7M  

[TXT]

 Farnell-Current-Tran..> 26-Mar-2014 17:58  2.7M  

[TXT]

 Farnell-Current-Tran..> 26-Mar-2014 17:59  2.7M  

[TXT]

 Farnell-Current-Tran..> 26-Mar-2014 17:59  2.7M  

[TXT]

 Farnell-DC-Fan-type-..> 14-Jun-2014 09:48  2.5M  

[TXT]

 Farnell-DC-Fan-type-..> 14-Jun-2014 09:51  1.8M  

[TXT]

 Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27  2.4M  

[TXT]

 Farnell-De-la-puissa..> 29-Mar-2014 11:10  3.3M  

[TXT]

 Farnell-Directive-re..> 25-Mar-2014 08:16  3.0M  

[TXT]

 Farnell-Documentatio..> 14-Jun-2014 18:26  2.5M  

[TXT]

 Farnell-Download-dat..> 13-Jun-2014 18:40  1.8M  

[TXT]

 Farnell-ECO-Series-T..> 20-Mar-2014 08:14  2.5M  

[TXT]

 Farnell-ELMA-PDF.htm    29-Mar-2014 11:13  3.3M  

[TXT]

 Farnell-EMC1182-PDF.htm 25-Mar-2014 08:17  3.0M  

[TXT]

 Farnell-EPCOS-173438..> 04-Jul-2014 10:43  3.3M  

[TXT]

 Farnell-EPCOS-Sample..> 11-Mar-2014 07:53  2.2M  

[TXT]

 Farnell-ES2333-PDF.htm  11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-Ed.081002-DA..> 19-Mar-2014 18:02  2.5M  

[TXT]

 Farnell-F28069-Picco..> 14-Jun-2014 18:14  2.0M  

[TXT]

 Farnell-F42202-PDF.htm  19-Mar-2014 18:00  2.5M  

[TXT]

 Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22  3.3M  

[TXT]

 Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17  1.6M  

[TXT]

 Farnell-Fastrack-Sup..> 23-Jun-2014 10:25  3.3M  

[TXT]

 Farnell-Ferric-Chlor..> 29-Mar-2014 11:14  2.8M  

[TXT]

 Farnell-Fiche-de-don..> 14-Jun-2014 09:47  2.5M  

[TXT]

 Farnell-Fiche-de-don..> 14-Jun-2014 18:26  2.5M  

[TXT]

 Farnell-Fluke-1730-E..> 14-Jun-2014 18:23  2.5M  

[TXT]

 Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56  2.7M  

[TXT]

 Farnell-GALVA-MAT-Re..> 26-Mar-2014 17:57  2.7M  

[TXT]

 Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11  2.6M  

[TXT]

 Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20  3.3M  

[TXT]

 Farnell-HFE1600-Data..> 14-Jun-2014 18:22  3.3M  

[TXT]

 Farnell-HI-70300-Sol..> 14-Jun-2014 18:27  2.4M  

[TXT]

 Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17  1.7M  

[TXT]

 Farnell-Haute-vitess..> 11-Mar-2014 08:17  2.4M  

[TXT]

 Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41  1.7M  

[TXT]

 Farnell-Instructions..> 19-Mar-2014 18:01  2.5M  

[TXT]

 Farnell-KSZ8851SNL-S..> 23-Jun-2014 10:28  2.1M  

[TXT]

 Farnell-L-efficacite..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-LCW-CQ7P.CC-..> 25-Mar-2014 08:19  3.2M  

[TXT]

 Farnell-LME49725-Pow..> 14-Jun-2014 09:49  2.5M  

[TXT]

 Farnell-LOCTITE-542-..> 25-Mar-2014 08:15  3.0M  

[TXT]

 Farnell-LOCTITE-3463..> 25-Mar-2014 08:19  3.0M  

[TXT]

 Farnell-LUXEON-Guide..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-Leaded-Trans..> 23-Jun-2014 10:26  3.2M  

[TXT]

 Farnell-Les-derniers..> 11-Mar-2014 07:50  2.3M  

[TXT]

 Farnell-Loctite3455-..> 25-Mar-2014 08:16  3.0M  

[TXT]

 Farnell-Low-cost-Enc..> 13-Jun-2014 18:42  1.7M  

[TXT]

 Farnell-Lubrifiant-a..> 26-Mar-2014 18:00  2.7M  

[TXT]

 Farnell-MC3510-PDF.htm  25-Mar-2014 08:17  3.0M  

[TXT]

 Farnell-MC21605-PDF.htm 11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14  2.8M  

[TXT]

 Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54  2.2M  

[TXT]

 Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02  2.5M  

[TXT]

 Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19  1.9M  

[TXT]

 Farnell-MOLEX-43020-..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-MOLEX-43160-..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-MOLEX-87439-..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-MPXV7002-Rev..> 20-Mar-2014 17:33  2.8M  

[TXT]

 Farnell-MX670-MX675-..> 14-Jun-2014 09:46  2.5M  

[TXT]

 Farnell-Microchip-MC..> 13-Jun-2014 18:27  1.8M  

[TXT]

 Farnell-Microship-PI..> 11-Mar-2014 07:53  2.2M  

[TXT]

 Farnell-Midas-Active..> 14-Jun-2014 18:17  3.4M  

[TXT]

 Farnell-Midas-MCCOG4..> 14-Jun-2014 18:11  2.1M  

[TXT]

 Farnell-Miniature-Ci..> 26-Mar-2014 17:55  2.8M  

[TXT]

 Farnell-Mistral-PDF.htm 14-Jun-2014 18:12  2.1M  

[TXT]

 Farnell-Molex-83421-..> 14-Jun-2014 18:17  3.4M  

[TXT]

 Farnell-Molex-COMMER..> 14-Jun-2014 18:16  3.4M  

[TXT]

 Farnell-Molex-Crimp-..> 10-Mar-2014 16:27  1.7M  

[TXT]

 Farnell-Multi-Functi..> 20-Mar-2014 17:38  3.0M  

[TXT]

 Farnell-NTE_SEMICOND..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-NXP-74VHC126..> 10-Mar-2014 16:17  1.6M  

[TXT]

 Farnell-NXP-BT136-60..> 11-Mar-2014 07:52  2.3M  

[TXT]

 Farnell-NXP-PBSS9110..> 10-Mar-2014 17:21  1.9M  

[TXT]

 Farnell-NXP-PCA9555 ..> 11-Mar-2014 07:54  2.2M  

[TXT]

 Farnell-NXP-PMBFJ620..> 10-Mar-2014 16:16  1.7M  

[TXT]

 Farnell-NXP-PSMN1R7-..> 10-Mar-2014 16:17  1.6M  

[TXT]

 Farnell-NXP-PSMN7R0-..> 10-Mar-2014 17:19  2.1M  

[TXT]

 Farnell-NXP-TEA1703T..> 11-Mar-2014 08:15  2.8M  

[TXT]

 Farnell-Nilfi-sk-E-..> 14-Jun-2014 09:47  2.5M  

[TXT]

 Farnell-Novembre-201..> 20-Mar-2014 17:38  3.3M  

[TXT]

 Farnell-OMRON-Master..> 10-Mar-2014 16:26  1.8M  

[TXT]

 Farnell-OSLON-SSL-Ce..> 19-Mar-2014 18:03  2.1M  

[TXT]

 Farnell-OXPCIE958-FB..> 13-Jun-2014 18:40  1.8M  

[TXT]

 Farnell-PADO-semi-au..> 04-Jul-2014 10:41  3.7M  

[TXT]

 Farnell-PBSS5160T-60..> 19-Mar-2014 18:03  2.1M  

[TXT]

 Farnell-PDTA143X-ser..> 20-Mar-2014 08:12  2.6M  

[TXT]

 Farnell-PDTB123TT-NX..> 13-Jun-2014 18:43  1.5M  

[TXT]

 Farnell-PESD5V0F1BL-..> 13-Jun-2014 18:43  1.5M  

[TXT]

 Farnell-PESD9X5.0L-P..> 13-Jun-2014 18:43  1.6M  

[TXT]

 Farnell-PIC12F609-61..> 04-Jul-2014 10:41  3.7M  

[TXT]

 Farnell-PIC18F2455-2..> 23-Jun-2014 10:27  3.1M  

[TXT]

 Farnell-PIC24FJ256GB..> 14-Jun-2014 09:51  2.4M  

[TXT]

 Farnell-PMBT3906-PNP..> 13-Jun-2014 18:44  1.5M  

[TXT]

 Farnell-PMBT4403-PNP..> 23-Jun-2014 10:27  3.1M  

[TXT]

 Farnell-PMEG4002EL-N..> 14-Jun-2014 18:18  3.4M  

[TXT]

 Farnell-PMEG4010CEH-..> 13-Jun-2014 18:43  1.6M  

[TXT]

 Farnell-Panasonic-15..> 23-Jun-2014 10:29  2.1M  

[TXT]

 Farnell-Panasonic-EC..> 20-Mar-2014 17:36  2.6M  

[TXT]

 Farnell-Panasonic-EZ..> 20-Mar-2014 08:10  2.6M  

[TXT]

 Farnell-Panasonic-Id..> 20-Mar-2014 17:35  2.6M  

[TXT]

 Farnell-Panasonic-Ne..> 20-Mar-2014 17:36  2.6M  

[TXT]

 Farnell-Panasonic-Ra..> 20-Mar-2014 17:37  2.6M  

[TXT]

 Farnell-Panasonic-TS..> 20-Mar-2014 08:12  2.6M  

[TXT]

 Farnell-Panasonic-Y3..> 20-Mar-2014 08:11  2.6M  

[TXT]

 Farnell-Pico-Spox-Wi..> 10-Mar-2014 16:16  1.7M  

[TXT]

 Farnell-Pompes-Charg..> 24-Apr-2014 20:23  3.3M  

[TXT]

 Farnell-Ponts-RLC-po..> 14-Jun-2014 18:23  3.3M  

[TXT]

 Farnell-Portable-Ana..> 29-Mar-2014 11:16  2.8M  

[TXT]

 Farnell-Premier-Farn..> 21-Mar-2014 08:11  3.8M  

[TXT]

 Farnell-Produit-3430..> 14-Jun-2014 09:48  2.5M  

[TXT]

 Farnell-Proskit-SS-3..> 10-Mar-2014 16:26  1.8M  

[TXT]

 Farnell-Puissance-ut..> 11-Mar-2014 07:49  2.4M  

[TXT]

 Farnell-Q48-PDF.htm     23-Jun-2014 10:29  2.1M  

[TXT]

 Farnell-Radial-Lead-..> 20-Mar-2014 08:12  2.6M  

[TXT]

 Farnell-Realiser-un-..> 11-Mar-2014 07:51  2.3M  

[TXT]

 Farnell-Reglement-RE..> 21-Mar-2014 08:08  3.9M  

[TXT]

 Farnell-Repartiteurs..> 14-Jun-2014 18:26  2.5M  

[TXT]

 Farnell-S-TRI-SWT860..> 21-Mar-2014 08:11  3.8M  

[TXT]

 Farnell-SB175-Connec..> 11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-SMBJ-Transil..> 29-Mar-2014 11:12  3.3M  

[TXT]

 Farnell-SOT-23-Multi..> 11-Mar-2014 07:51  2.3M  

[TXT]

 Farnell-SPLC780A1-16..> 14-Jun-2014 18:25  2.5M  

[TXT]

 Farnell-SSC7102-Micr..> 23-Jun-2014 10:25  3.2M  

[TXT]

 Farnell-SVPE-series-..> 14-Jun-2014 18:15  2.0M  

[TXT]

 Farnell-Sensorless-C..> 04-Jul-2014 10:42  3.3M  

[TXT]

 Farnell-Septembre-20..> 20-Mar-2014 17:46  3.7M  

[TXT]

 Farnell-Serie-PicoSc..> 19-Mar-2014 18:01  2.5M  

[TXT]

 Farnell-Serie-Standa..> 14-Jun-2014 18:23  3.3M  

[TXT]

 Farnell-Series-2600B..> 20-Mar-2014 17:30  3.0M  

[TXT]

 Farnell-Series-TDS10..> 04-Jul-2014 10:39  4.0M  

[TXT]

 Farnell-Signal-PCB-R..> 14-Jun-2014 18:11  2.1M  

[TXT]

 Farnell-Strangkuhlko..> 21-Mar-2014 08:09  3.9M  

[TXT]

 Farnell-Supercapacit..> 26-Mar-2014 17:57  2.7M  

[TXT]

 Farnell-TDK-Lambda-H..> 14-Jun-2014 18:21  3.3M  

[TXT]

 Farnell-TEKTRONIX-DP..> 10-Mar-2014 17:20  2.0M  

[TXT]

 Farnell-Tektronix-AC..> 13-Jun-2014 18:44  1.5M  

[TXT]

 Farnell-Telemetres-l..> 20-Mar-2014 17:46  3.7M  

[TXT]

 Farnell-Termometros-..> 14-Jun-2014 18:14  2.0M  

[TXT]

 Farnell-The-essentia..> 10-Mar-2014 16:27  1.7M  

[TXT]

 Farnell-U2270B-PDF.htm  14-Jun-2014 18:15  3.4M  

[TXT]

 Farnell-USB-Buccanee..> 14-Jun-2014 09:48  2.5M  

[TXT]

 Farnell-USB1T11A-PDF..> 19-Mar-2014 18:03  2.1M  

[TXT]

 Farnell-V4N-PDF.htm     14-Jun-2014 18:11  2.1M  

[TXT]

 Farnell-WetTantalum-..> 11-Mar-2014 08:14  2.8M  

[TXT]

 Farnell-XPS-AC-Octop..> 14-Jun-2014 18:11  2.1M  

[TXT]

 Farnell-XPS-MC16-XPS..> 11-Mar-2014 08:15  2.8M  

[TXT]

 Farnell-YAGEO-DATA-S..> 11-Mar-2014 08:13  2.8M  

[TXT]

 Farnell-ZigBee-ou-le..> 11-Mar-2014 07:50  2.4M  

[TXT]

 Farnell-celpac-SUL84..> 21-Mar-2014 08:11  3.8M  

[TXT]

 Farnell-china_rohs_o..> 21-Mar-2014 10:04  3.9M  

[TXT]

 Farnell-cree-Xlamp-X..> 20-Mar-2014 17:34  2.8M  

[TXT]

 Farnell-cree-Xlamp-X..> 20-Mar-2014 17:35  2.7M  

[TXT]

 Farnell-cree-Xlamp-X..> 20-Mar-2014 17:31  2.9M  

[TXT]

 Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32  2.9M  

[TXT]

 Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32  2.9M  

[TXT]

 Farnell-ir1150s_fr.p..> 29-Mar-2014 11:11  3.3M  

[TXT]

 Farnell-manual-bus-p..> 10-Mar-2014 16:29  1.9M  

[TXT]

 Farnell-propose-plus..> 11-Mar-2014 08:19  2.8M  

[TXT]

 Farnell-techfirst_se..> 21-Mar-2014 08:08  3.9M  

[TXT]

 Farnell-testo-205-20..> 20-Mar-2014 17:37  3.0M  

[TXT]

 Farnell-testo-470-Fo..> 20-Mar-2014 17:38  3.0M  

[TXT]

 Farnell-uC-OS-III-Br..> 10-Mar-2014 17:20  2.0M  

[TXT]

 Sefram-7866HD.pdf-PD..> 29-Mar-2014 11:46  472K  

[TXT]

 Sefram-CAT_ENREGISTR..> 29-Mar-2014 11:46  461K  

[TXT]

 Sefram-CAT_MESUREURS..> 29-Mar-2014 11:46  435K  

[TXT]

 Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46  481K  

[TXT]

 Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46  442K  

[TXT]

 Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46  422K  

[TXT]

 Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46  464K
Stellaris® LM3S2965 Microcontroller DATA SHEET Copyright © 2007-2011 Texas Instruments Incorporated DS-LM3S2965-9102 TEXAS INSTRUMENTS-PRODUCTION DATA Copyright Copyright © 2007-2011 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Texas Instruments Incorporated 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm 2 January 08, 2011 Texas Instruments-Production Data Table of Contents Revision History ............................................................................................................................. 25 About This Document .................................................................................................................... 31 Audience .............................................................................................................................................. 31 About This Manual ................................................................................................................................ 31 Related Documents ............................................................................................................................... 31 Documentation Conventions .................................................................................................................. 32 1 Architectural Overview .......................................................................................... 34 1.1 Product Features .......................................................................................................... 34 1.2 Target Applications ........................................................................................................ 43 1.3 High-Level Block Diagram ............................................................................................. 43 1.4 Functional Overview ...................................................................................................... 45 1.4.1 ARM Cortex™-M3 ......................................................................................................... 45 1.4.2 Motor Control Peripherals .............................................................................................. 46 1.4.3 Analog Peripherals ........................................................................................................ 47 1.4.4 Serial Communications Peripherals ................................................................................ 47 1.4.5 System Peripherals ....................................................................................................... 49 1.4.6 Memory Peripherals ...................................................................................................... 50 1.4.7 Additional Features ....................................................................................................... 50 1.4.8 Hardware Details .......................................................................................................... 51 2 The Cortex-M3 Processor ...................................................................................... 52 2.1 Block Diagram .............................................................................................................. 53 2.2 Overview ...................................................................................................................... 54 2.2.1 System-Level Interface .................................................................................................. 54 2.2.2 Integrated Configurable Debug ...................................................................................... 54 2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 55 2.2.4 Cortex-M3 System Component Details ........................................................................... 55 2.3 Programming Model ...................................................................................................... 56 2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 56 2.3.2 Stacks .......................................................................................................................... 56 2.3.3 Register Map ................................................................................................................ 57 2.3.4 Register Descriptions .................................................................................................... 58 2.3.5 Exceptions and Interrupts .............................................................................................. 71 2.3.6 Data Types ................................................................................................................... 71 2.4 Memory Model .............................................................................................................. 71 2.4.1 Memory Regions, Types and Attributes ........................................................................... 73 2.4.2 Memory System Ordering of Memory Accesses .............................................................. 73 2.4.3 Behavior of Memory Accesses ....................................................................................... 73 2.4.4 Software Ordering of Memory Accesses ......................................................................... 74 2.4.5 Bit-Banding ................................................................................................................... 75 2.4.6 Data Storage ................................................................................................................ 77 2.4.7 Synchronization Primitives ............................................................................................. 78 2.5 Exception Model ........................................................................................................... 79 2.5.1 Exception States ........................................................................................................... 80 2.5.2 Exception Types ............................................................................................................ 80 2.5.3 Exception Handlers ....................................................................................................... 83 January 08, 2011 3 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 2.5.4 Vector Table .................................................................................................................. 83 2.5.5 Exception Priorities ....................................................................................................... 84 2.5.6 Interrupt Priority Grouping .............................................................................................. 85 2.5.7 Exception Entry and Return ........................................................................................... 85 2.6 Fault Handling .............................................................................................................. 87 2.6.1 Fault Types ................................................................................................................... 87 2.6.2 Fault Escalation and Hard Faults .................................................................................... 88 2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 89 2.6.4 Lockup ......................................................................................................................... 89 2.7 Power Management ...................................................................................................... 89 2.7.1 Entering Sleep Modes ................................................................................................... 90 2.7.2 Wake Up from Sleep Mode ............................................................................................ 90 2.8 Instruction Set Summary ............................................................................................... 91 3 Cortex-M3 Peripherals ........................................................................................... 94 3.1 Functional Description ................................................................................................... 94 3.1.1 System Timer (SysTick) ................................................................................................. 94 3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 95 3.1.3 System Control Block (SCB) .......................................................................................... 97 3.1.4 Memory Protection Unit (MPU) ....................................................................................... 97 3.2 Register Map .............................................................................................................. 102 3.3 System Timer (SysTick) Register Descriptions .............................................................. 104 3.4 NVIC Register Descriptions .......................................................................................... 108 3.5 System Control Block (SCB) Register Descriptions ........................................................ 121 3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 148 4 JTAG Interface ...................................................................................................... 158 4.1 Block Diagram ............................................................................................................ 159 4.2 Functional Description ................................................................................................. 159 4.2.1 JTAG Interface Pins ..................................................................................................... 159 4.2.2 JTAG TAP Controller ................................................................................................... 161 4.2.3 Shift Registers ............................................................................................................ 162 4.2.4 Operational Considerations .......................................................................................... 162 4.3 Initialization and Configuration ..................................................................................... 165 4.4 Register Descriptions .................................................................................................. 165 4.4.1 Instruction Register (IR) ............................................................................................... 165 4.4.2 Data Registers ............................................................................................................ 167 5 System Control ..................................................................................................... 170 5.1 Functional Description ................................................................................................. 170 5.1.1 Device Identification .................................................................................................... 170 5.1.2 Reset Control .............................................................................................................. 170 5.1.3 Power Control ............................................................................................................. 174 5.1.4 Clock Control .............................................................................................................. 175 5.1.5 System Control ........................................................................................................... 180 5.2 Initialization and Configuration ..................................................................................... 181 5.3 Register Map .............................................................................................................. 181 5.4 Register Descriptions .................................................................................................. 183 6 Hibernation Module .............................................................................................. 236 6.1 Block Diagram ............................................................................................................ 237 4 January 08, 2011 Texas Instruments-Production Data Table of Contents 6.2 Functional Description ................................................................................................. 237 6.2.1 Register Access Timing ............................................................................................... 237 6.2.2 Clock Source .............................................................................................................. 238 6.2.3 Battery Management ................................................................................................... 239 6.2.4 Real-Time Clock .......................................................................................................... 240 6.2.5 Non-Volatile Memory ................................................................................................... 240 6.2.6 Power Control ............................................................................................................. 240 6.2.7 Initiating Hibernate ...................................................................................................... 241 6.2.8 Interrupts and Status ................................................................................................... 241 6.3 Initialization and Configuration ..................................................................................... 241 6.3.1 Initialization ................................................................................................................. 242 6.3.2 RTC Match Functionality (No Hibernation) .................................................................... 242 6.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 242 6.3.4 External Wake-Up from Hibernation .............................................................................. 242 6.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 243 6.4 Register Map .............................................................................................................. 243 6.5 Register Descriptions .................................................................................................. 243 7 Internal Memory ................................................................................................... 256 7.1 Block Diagram ............................................................................................................ 256 7.2 Functional Description ................................................................................................. 256 7.2.1 SRAM Memory ............................................................................................................ 256 7.2.2 Flash Memory ............................................................................................................. 257 7.3 Flash Memory Initialization and Configuration ............................................................... 258 7.3.1 Flash Programming ..................................................................................................... 258 7.3.2 Nonvolatile Register Programming ............................................................................... 259 7.4 Register Map .............................................................................................................. 260 7.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 261 7.6 Flash Register Descriptions (System Control Offset) ...................................................... 269 8 General-Purpose Input/Outputs (GPIOs) ........................................................... 282 8.1 Functional Description ................................................................................................. 282 8.1.1 Data Control ............................................................................................................... 283 8.1.2 Interrupt Control .......................................................................................................... 284 8.1.3 Mode Control .............................................................................................................. 285 8.1.4 Commit Control ........................................................................................................... 285 8.1.5 Pad Control ................................................................................................................. 285 8.1.6 Identification ............................................................................................................... 286 8.2 Initialization and Configuration ..................................................................................... 286 8.3 Register Map .............................................................................................................. 287 8.4 Register Descriptions .................................................................................................. 289 9 General-Purpose Timers ...................................................................................... 324 9.1 Block Diagram ............................................................................................................ 325 9.2 Functional Description ................................................................................................. 326 9.2.1 GPTM Reset Conditions .............................................................................................. 326 9.2.2 32-Bit Timer Operating Modes ...................................................................................... 326 9.2.3 16-Bit Timer Operating Modes ...................................................................................... 327 9.3 Initialization and Configuration ..................................................................................... 331 9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 331 9.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 332 January 08, 2011 5 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 9.3.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 332 9.3.4 16-Bit Input Edge Count Mode ..................................................................................... 333 9.3.5 16-Bit Input Edge Timing Mode .................................................................................... 333 9.3.6 16-Bit PWM Mode ....................................................................................................... 334 9.4 Register Map .............................................................................................................. 334 9.5 Register Descriptions .................................................................................................. 335 10 Watchdog Timer ................................................................................................... 360 10.1 Block Diagram ............................................................................................................ 361 10.2 Functional Description ................................................................................................. 361 10.3 Initialization and Configuration ..................................................................................... 362 10.4 Register Map .............................................................................................................. 362 10.5 Register Descriptions .................................................................................................. 363 11 Analog-to-Digital Converter (ADC) ..................................................................... 384 11.1 Block Diagram ............................................................................................................ 384 11.2 Functional Description ................................................................................................. 385 11.2.1 Sample Sequencers .................................................................................................... 385 11.2.2 Module Control ............................................................................................................ 386 11.2.3 Hardware Sample Averaging Circuit ............................................................................. 387 11.2.4 Analog-to-Digital Converter .......................................................................................... 387 11.2.5 Differential Sampling ................................................................................................... 387 11.2.6 Test Modes ................................................................................................................. 389 11.2.7 Internal Temperature Sensor ........................................................................................ 390 11.3 Initialization and Configuration ..................................................................................... 390 11.3.1 Module Initialization ..................................................................................................... 390 11.3.2 Sample Sequencer Configuration ................................................................................. 391 11.4 Register Map .............................................................................................................. 391 11.5 Register Descriptions .................................................................................................. 392 12 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 420 12.1 Block Diagram ............................................................................................................ 421 12.2 Functional Description ................................................................................................. 421 12.2.1 Transmit/Receive Logic ............................................................................................... 421 12.2.2 Baud-Rate Generation ................................................................................................. 422 12.2.3 Data Transmission ...................................................................................................... 423 12.2.4 Serial IR (SIR) ............................................................................................................. 423 12.2.5 FIFO Operation ........................................................................................................... 424 12.2.6 Interrupts .................................................................................................................... 424 12.2.7 Loopback Operation .................................................................................................... 425 12.2.8 IrDA SIR block ............................................................................................................ 425 12.3 Initialization and Configuration ..................................................................................... 425 12.4 Register Map .............................................................................................................. 426 12.5 Register Descriptions .................................................................................................. 427 13 Synchronous Serial Interface (SSI) .................................................................... 461 13.1 Block Diagram ............................................................................................................ 461 13.2 Functional Description ................................................................................................. 462 13.2.1 Bit Rate Generation ..................................................................................................... 462 13.2.2 FIFO Operation ........................................................................................................... 462 13.2.3 Interrupts .................................................................................................................... 462 6 January 08, 2011 Texas Instruments-Production Data Table of Contents 13.2.4 Frame Formats ........................................................................................................... 463 13.3 Initialization and Configuration ..................................................................................... 470 13.4 Register Map .............................................................................................................. 471 13.5 Register Descriptions .................................................................................................. 472 14 Inter-Integrated Circuit (I2C) Interface ................................................................ 498 14.1 Block Diagram ............................................................................................................ 499 14.2 Functional Description ................................................................................................. 499 14.2.1 I2C Bus Functional Overview ........................................................................................ 499 14.2.2 Available Speed Modes ............................................................................................... 501 14.2.3 Interrupts .................................................................................................................... 502 14.2.4 Loopback Operation .................................................................................................... 503 14.2.5 Command Sequence Flow Charts ................................................................................ 503 14.3 Initialization and Configuration ..................................................................................... 510 14.4 Register Map .............................................................................................................. 511 14.5 Register Descriptions (I2C Master) ............................................................................... 512 14.6 Register Descriptions (I2C Slave) ................................................................................. 525 15 Controller Area Network (CAN) Module ............................................................. 534 15.1 Block Diagram ............................................................................................................ 535 15.2 Functional Description ................................................................................................. 535 15.2.1 Initialization ................................................................................................................. 536 15.2.2 Operation ................................................................................................................... 537 15.2.3 Transmitting Message Objects ..................................................................................... 538 15.2.4 Configuring a Transmit Message Object ........................................................................ 538 15.2.5 Updating a Transmit Message Object ........................................................................... 539 15.2.6 Accepting Received Message Objects .......................................................................... 540 15.2.7 Receiving a Data Frame .............................................................................................. 540 15.2.8 Receiving a Remote Frame .......................................................................................... 540 15.2.9 Receive/Transmit Priority ............................................................................................. 541 15.2.10 Configuring a Receive Message Object ........................................................................ 541 15.2.11 Handling of Received Message Objects ........................................................................ 542 15.2.12 Handling of Interrupts .................................................................................................. 545 15.2.13 Test Mode ................................................................................................................... 545 15.2.14 Bit Timing Configuration Error Considerations ............................................................... 547 15.2.15 Bit Time and Bit Rate ................................................................................................... 547 15.2.16 Calculating the Bit Timing Parameters .......................................................................... 549 15.3 Register Map .............................................................................................................. 552 15.4 CAN Register Descriptions .......................................................................................... 553 16 Analog Comparators ............................................................................................ 579 16.1 Block Diagram ............................................................................................................ 580 16.2 Functional Description ................................................................................................. 580 16.2.1 Internal Reference Programming .................................................................................. 581 16.3 Initialization and Configuration ..................................................................................... 582 16.4 Register Map .............................................................................................................. 582 16.5 Register Descriptions .................................................................................................. 583 17 Pulse Width Modulator (PWM) ............................................................................ 591 17.1 Block Diagram ............................................................................................................ 592 17.2 Functional Description ................................................................................................. 593 January 08, 2011 7 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 17.2.1 PWM Timer ................................................................................................................. 593 17.2.2 PWM Comparators ...................................................................................................... 593 17.2.3 PWM Signal Generator ................................................................................................ 594 17.2.4 Dead-Band Generator ................................................................................................. 595 17.2.5 Interrupt/ADC-Trigger Selector ..................................................................................... 595 17.2.6 Synchronization Methods ............................................................................................ 596 17.2.7 Fault Conditions .......................................................................................................... 596 17.2.8 Output Control Block ................................................................................................... 596 17.3 Initialization and Configuration ..................................................................................... 596 17.4 Register Map .............................................................................................................. 597 17.5 Register Descriptions .................................................................................................. 599 18 Quadrature Encoder Interface (QEI) ................................................................... 629 18.1 Block Diagram ............................................................................................................ 629 18.2 Functional Description ................................................................................................. 630 18.3 Initialization and Configuration ..................................................................................... 632 18.4 Register Map .............................................................................................................. 633 18.5 Register Descriptions .................................................................................................. 633 19 Pin Diagram .......................................................................................................... 646 20 Signal Tables ........................................................................................................ 648 20.1 100-Pin LQFP Package Pin Tables ............................................................................... 648 20.2 108-Pin BGA Package Pin Tables ................................................................................ 662 20.3 Connections for Unused Signals ................................................................................... 676 21 Operating Characteristics ................................................................................... 678 22 Electrical Characteristics .................................................................................... 679 22.1 DC Characteristics ...................................................................................................... 679 22.1.1 Maximum Ratings ....................................................................................................... 679 22.1.2 Recommended DC Operating Conditions ...................................................................... 679 22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 680 22.1.4 GPIO Module Characteristics ....................................................................................... 680 22.1.5 Power Specifications ................................................................................................... 680 22.1.6 Flash Memory Characteristics ...................................................................................... 682 22.1.7 Hibernation ................................................................................................................. 682 22.2 AC Characteristics ....................................................................................................... 682 22.2.1 Load Conditions .......................................................................................................... 682 22.2.2 Clocks ........................................................................................................................ 682 22.2.3 JTAG and Boundary Scan ............................................................................................ 684 22.2.4 Reset ......................................................................................................................... 685 22.2.5 Sleep Modes ............................................................................................................... 687 22.2.6 Hibernation Module ..................................................................................................... 687 22.2.7 General-Purpose I/O (GPIO) ........................................................................................ 688 22.2.8 Analog-to-Digital Converter .......................................................................................... 688 22.2.9 Synchronous Serial Interface (SSI) ............................................................................... 690 22.2.10 Inter-Integrated Circuit (I2C) Interface ........................................................................... 691 22.2.11 Analog Comparator ..................................................................................................... 692 A Serial Flash Loader .............................................................................................. 693 A.1 Serial Flash Loader ..................................................................................................... 693 A.2 Interfaces ................................................................................................................... 693 8 January 08, 2011 Texas Instruments-Production Data Table of Contents A.2.1 UART ......................................................................................................................... 693 A.2.2 SSI ............................................................................................................................. 693 A.3 Packet Handling .......................................................................................................... 694 A.3.1 Packet Format ............................................................................................................ 694 A.3.2 Sending Packets ......................................................................................................... 694 A.3.3 Receiving Packets ....................................................................................................... 694 A.4 Commands ................................................................................................................. 695 A.4.1 COMMAND_PING (0X20) ............................................................................................ 695 A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 695 A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 695 A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 696 A.4.5 COMMAND_RUN (0x22) ............................................................................................. 696 A.4.6 COMMAND_RESET (0x25) ......................................................................................... 696 B Register Quick Reference ................................................................................... 698 C Ordering and Contact Information ..................................................................... 723 C.1 Ordering Information .................................................................................................... 723 C.2 Part Markings .............................................................................................................. 723 C.3 Kits ............................................................................................................................. 724 C.4 Support Information ..................................................................................................... 724 D Package Information ............................................................................................ 725 D.1 100-Pin LQFP Package ............................................................................................... 725 D.1.1 Package Dimensions ................................................................................................... 725 D.1.2 Tray Dimensions ......................................................................................................... 727 D.1.3 Tape and Reel Dimensions .......................................................................................... 727 D.2 108-Ball BGA Package ................................................................................................ 729 D.2.1 Package Dimensions ................................................................................................... 729 D.2.2 Tray Dimensions ......................................................................................................... 731 D.2.3 Tape and Reel Dimensions .......................................................................................... 732 January 08, 2011 9 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller List of Figures Figure 1-1. Stellaris LM3S2965 Microcontroller High-Level Block Diagram .............................. 44 Figure 2-1. CPU Block Diagram ............................................................................................. 54 Figure 2-2. TPIU Block Diagram ............................................................................................ 55 Figure 2-3. Cortex-M3 Register Set ........................................................................................ 57 Figure 2-4. Bit-Band Mapping ................................................................................................ 77 Figure 2-5. Data Storage ....................................................................................................... 78 Figure 2-6. Vector table ......................................................................................................... 84 Figure 2-7. Exception Stack Frame ........................................................................................ 86 Figure 3-1. SRD Use Example ............................................................................................. 100 Figure 4-1. JTAG Module Block Diagram .............................................................................. 159 Figure 4-2. Test Access Port State Machine ......................................................................... 162 Figure 4-3. IDCODE Register Format ................................................................................... 168 Figure 4-4. BYPASS Register Format ................................................................................... 168 Figure 4-5. Boundary Scan Register Format ......................................................................... 169 Figure 5-1. Basic RST Configuration .................................................................................... 172 Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 172 Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 173 Figure 5-4. Power Architecture ............................................................................................ 175 Figure 5-5. Main Clock Tree ................................................................................................ 177 Figure 6-1. Hibernation Module Block Diagram ..................................................................... 237 Figure 6-2. Clock Source Using Crystal ................................................................................ 239 Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 239 Figure 7-1. Flash Block Diagram .......................................................................................... 256 Figure 8-1. GPIO Port Block Diagram ................................................................................... 283 Figure 8-2. GPIODATA Write Example ................................................................................. 284 Figure 8-3. GPIODATA Read Example ................................................................................. 284 Figure 9-1. GPTM Module Block Diagram ............................................................................ 325 Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 329 Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 330 Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 331 Figure 10-1. WDT Module Block Diagram .............................................................................. 361 Figure 11-1. ADC Module Block Diagram ............................................................................... 385 Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 388 Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 389 Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 389 Figure 11-5. Internal Temperature Sensor Characteristic ......................................................... 390 Figure 12-1. UART Module Block Diagram ............................................................................. 421 Figure 12-2. UART Character Frame ..................................................................................... 422 Figure 12-3. IrDA Data Modulation ......................................................................................... 424 Figure 13-1. SSI Module Block Diagram ................................................................................. 461 Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 464 Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 464 Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 465 Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 465 Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 466 Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 467 10 January 08, 2011 Texas Instruments-Production Data Table of Contents Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 467 Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 468 Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 469 Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 470 Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 470 Figure 14-1. I2C Block Diagram ............................................................................................. 499 Figure 14-2. I2C Bus Configuration ........................................................................................ 499 Figure 14-3. START and STOP Conditions ............................................................................. 500 Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 500 Figure 14-5. R/S Bit in First Byte ............................................................................................ 500 Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 501 Figure 14-7. Master Single SEND .......................................................................................... 504 Figure 14-8. Master Single RECEIVE ..................................................................................... 505 Figure 14-9. Master Burst SEND ........................................................................................... 506 Figure 14-10. Master Burst RECEIVE ...................................................................................... 507 Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 508 Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 509 Figure 14-13. Slave Command Sequence ................................................................................ 510 Figure 15-1. CAN Controller Block Diagram ............................................................................ 535 Figure 15-2. CAN Data/Remote Frame .................................................................................. 536 Figure 15-3. Message Objects in a FIFO Buffer ...................................................................... 544 Figure 15-4. CAN Bit Time .................................................................................................... 548 Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 580 Figure 16-2. Structure of Comparator Unit .............................................................................. 581 Figure 16-3. Comparator Internal Reference Structure ............................................................ 581 Figure 17-1. PWM Unit Diagram ............................................................................................ 592 Figure 17-2. PWM Module Block Diagram .............................................................................. 593 Figure 17-3. PWM Count-Down Mode .................................................................................... 594 Figure 17-4. PWM Count-Up/Down Mode .............................................................................. 594 Figure 17-5. PWM Generation Example In Count-Up/Down Mode ........................................... 595 Figure 17-6. PWM Dead-Band Generator ............................................................................... 595 Figure 18-1. QEI Block Diagram ............................................................................................ 630 Figure 18-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 631 Figure 19-1. 100-Pin LQFP Package Pin Diagram .................................................................. 646 Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 647 Figure 22-1. Load Conditions ................................................................................................ 682 Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 685 Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 685 Figure 22-4. JTAG TRST Timing ............................................................................................ 685 Figure 22-5. External Reset Timing (RST) .............................................................................. 686 Figure 22-6. Power-On Reset Timing ..................................................................................... 686 Figure 22-7. Brown-Out Reset Timing .................................................................................... 686 Figure 22-8. Software Reset Timing ....................................................................................... 687 Figure 22-9. Watchdog Reset Timing ..................................................................................... 687 Figure 22-10. Hibernation Module Timing ................................................................................. 688 Figure 22-11. ADC Input Equivalency Diagram ......................................................................... 689 Figure 22-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 690 January 08, 2011 11 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 22-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 691 Figure 22-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 691 Figure 22-15. I2C Timing ......................................................................................................... 692 Figure D-1. 100-Pin LQFP Package Dimensions ................................................................... 725 Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 727 Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 728 Figure D-4. 108-Ball BGA Package Dimensions .................................................................... 729 Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 731 Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 732 12 January 08, 2011 Texas Instruments-Production Data Table of Contents List of Tables Table 1. Revision History .................................................................................................. 25 Table 2. Documentation Conventions ................................................................................ 32 Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 57 Table 2-2. Processor Register Map ....................................................................................... 58 Table 2-3. PSR Register Combinations ................................................................................. 63 Table 2-4. Memory Map ....................................................................................................... 71 Table 2-5. Memory Access Behavior ..................................................................................... 74 Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 76 Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 76 Table 2-8. Exception Types .................................................................................................. 81 Table 2-9. Interrupts ............................................................................................................ 82 Table 2-10. Exception Return Behavior ................................................................................... 87 Table 2-11. Faults ................................................................................................................. 88 Table 2-12. Fault Status and Fault Address Registers .............................................................. 89 Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 91 Table 3-1. Core Peripheral Register Regions ......................................................................... 94 Table 3-2. Memory Attributes Summary ................................................................................ 97 Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 100 Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 101 Table 3-5. AP Bit Field Encoding ........................................................................................ 101 Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 101 Table 3-7. Peripherals Register Map ................................................................................... 102 Table 3-8. Interrupt Priority Levels ...................................................................................... 127 Table 3-9. Example SIZE Field Values ................................................................................ 155 Table 4-1. JTAG Port Pins Reset State ............................................................................... 160 Table 4-2. JTAG Instruction Register Commands ................................................................. 165 Table 5-1. Reset Sources ................................................................................................... 170 Table 5-2. Clock Source Options ........................................................................................ 176 Table 5-3. Possible System Clock Frequencies Using the SYSDIV Field ............................... 178 Table 5-4. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 178 Table 5-5. System Control Register Map ............................................................................. 182 Table 5-6. RCC2 Fields that Override RCC fields ................................................................. 197 Table 6-1. Hibernation Module Register Map ....................................................................... 243 Table 7-1. Flash Protection Policy Combinations ................................................................. 257 Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 259 Table 7-3. Flash Register Map ............................................................................................ 260 Table 8-1. GPIO Pad Configuration Examples ..................................................................... 286 Table 8-2. GPIO Interrupt Configuration Example ................................................................ 286 Table 8-3. GPIO Register Map ........................................................................................... 288 Table 9-1. Available CCP Pins ............................................................................................ 325 Table 9-2. 16-Bit Timer With Prescaler Configurations ......................................................... 328 Table 9-3. Timers Register Map .......................................................................................... 334 Table 10-1. Watchdog Timer Register Map ............................................................................ 362 Table 11-1. Samples and FIFO Depth of Sequencers ............................................................ 385 Table 11-2. Differential Sampling Pairs ................................................................................. 387 Table 11-3. ADC Register Map ............................................................................................. 391 January 08, 2011 13 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 12-1. UART Register Map ........................................................................................... 427 Table 13-1. SSI Register Map .............................................................................................. 472 Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ................................... 502 Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 511 Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 516 Table 15-1. CAN Protocol Ranges ........................................................................................ 548 Table 15-2. CANBIT Register Values .................................................................................... 548 Table 15-3. CAN Register Map ............................................................................................. 552 Table 16-1. Internal Reference Voltage and ACREFCTL Field Values ..................................... 581 Table 16-2. Analog Comparators Register Map ..................................................................... 583 Table 17-1. PWM Register Map ............................................................................................ 598 Table 18-1. QEI Register Map .............................................................................................. 633 Table 20-1. Signals by Pin Number ....................................................................................... 648 Table 20-2. Signals by Signal Name ..................................................................................... 652 Table 20-3. Signals by Function, Except for GPIO ................................................................. 657 Table 20-4. GPIO Pins and Alternate Functions ..................................................................... 660 Table 20-5. Signals by Pin Number ....................................................................................... 662 Table 20-6. Signals by Signal Name ..................................................................................... 666 Table 20-7. Signals by Function, Except for GPIO ................................................................. 671 Table 20-8. GPIO Pins and Alternate Functions ..................................................................... 674 Table 20-9. Connections for Unused Signals (100-pin LQFP) ................................................. 676 Table 20-10. Connections for Unused Signals, 108-pin BGA .................................................... 676 Table 21-1. Temperature Characteristics ............................................................................... 678 Table 21-2. Thermal Characteristics ..................................................................................... 678 Table 21-3. ESD Absolute Maximum Ratings ........................................................................ 678 Table 22-1. Maximum Ratings .............................................................................................. 679 Table 22-2. Recommended DC Operating Conditions ............................................................ 679 Table 22-3. LDO Regulator Characteristics ........................................................................... 680 Table 22-4. GPIO Module DC Characteristics ........................................................................ 680 Table 22-5. Detailed Power Specifications ............................................................................ 681 Table 22-6. Flash Memory Characteristics ............................................................................ 682 Table 22-7. Hibernation Module DC Characteristics ............................................................... 682 Table 22-8. Phase Locked Loop (PLL) Characteristics ........................................................... 682 Table 22-9. Actual PLL Frequency ........................................................................................ 683 Table 22-10. Clock Characteristics ......................................................................................... 683 Table 22-11. Crystal Characteristics ....................................................................................... 683 Table 22-12. System Clock Characteristics with ADC Operation ............................................... 684 Table 22-13. JTAG Characteristics ......................................................................................... 684 Table 22-14. Reset Characteristics ......................................................................................... 685 Table 22-15. Sleep Modes AC Characteristics ......................................................................... 687 Table 22-16. Hibernation Module AC Characteristics ............................................................... 687 Table 22-17. GPIO Characteristics ......................................................................................... 688 Table 22-18. ADC Characteristics ........................................................................................... 688 Table 22-19. ADC Module Internal Reference Characteristics .................................................. 689 Table 22-20. SSI Characteristics ............................................................................................ 690 Table 22-21. I2C Characteristics ............................................................................................. 691 Table 22-22. Analog Comparator Characteristics ..................................................................... 692 Table 22-23. Analog Comparator Voltage Reference Characteristics ........................................ 692 14 January 08, 2011 Texas Instruments-Production Data Table of Contents Table C-1. Part Ordering Information ................................................................................... 723 January 08, 2011 15 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller List of Registers The Cortex-M3 Processor ............................................................................................................. 52 Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 59 Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 59 Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 59 Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 59 Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 59 Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 59 Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 59 Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 59 Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 59 Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 59 Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 59 Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 59 Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 59 Register 14: Stack Pointer (SP) ........................................................................................................... 60 Register 15: Link Register (LR) ............................................................................................................ 61 Register 16: Program Counter (PC) ..................................................................................................... 62 Register 17: Program Status Register (PSR) ........................................................................................ 63 Register 18: Priority Mask Register (PRIMASK) .................................................................................... 67 Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 68 Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 69 Register 21: Control Register (CONTROL) ........................................................................................... 70 Cortex-M3 Peripherals ................................................................................................................... 94 Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 105 Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 107 Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 108 Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 109 Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................ 110 Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 111 Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................ 112 Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 113 Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 114 Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 115 Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 116 Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 117 Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 118 Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 119 Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 119 Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 119 Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 119 Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 119 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 119 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 119 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 119 Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 119 16 January 08, 2011 Texas Instruments-Production Data Table of Contents Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 119 Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 119 Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 121 Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 122 Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 123 Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 126 Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 127 Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 129 Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 131 Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 133 Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 134 Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 135 Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 136 Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 140 Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 146 Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 147 Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 148 Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 149 Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 150 Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 152 Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 153 Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 153 Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 153 Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 153 Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 155 Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 155 Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 155 Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 155 System Control ............................................................................................................................ 170 Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 184 Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 186 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 187 Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 188 Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 189 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 190 Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 191 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 192 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 196 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 197 Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 199 Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 200 Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 202 Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 203 Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 205 Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 207 Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 209 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 210 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 212 January 08, 2011 17 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 214 Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 216 Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 219 Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 222 Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 225 Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 227 Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 229 Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 231 Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 233 Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 235 Hibernation Module ..................................................................................................................... 236 Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 244 Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 245 Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 246 Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 247 Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 248 Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 250 Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 251 Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 252 Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 253 Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 254 Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 255 Internal Memory ........................................................................................................................... 256 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 262 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 263 Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 264 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 266 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 267 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 268 Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 270 Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 271 Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 272 Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 273 Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 274 Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 275 Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 276 Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 277 Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 278 Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 279 Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 280 Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 281 General-Purpose Input/Outputs (GPIOs) ................................................................................... 282 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 290 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 291 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 292 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 293 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 294 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 295 18 January 08, 2011 Texas Instruments-Production Data Table of Contents Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 296 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 297 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 298 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 299 Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 301 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 302 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 303 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 304 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 305 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 306 Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 307 Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 308 Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 309 Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 310 Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 312 Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 313 Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 314 Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 315 Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 316 Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 317 Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 318 Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 319 Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 320 Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 321 Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 322 Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 323 General-Purpose Timers ............................................................................................................. 324 Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 336 Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 337 Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 339 Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 341 Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 344 Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 346 Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 347 Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 348 Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 350 Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 351 Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 352 Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 353 Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 354 Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 355 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 356 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 357 Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 358 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 359 Watchdog Timer ........................................................................................................................... 360 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 364 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 365 January 08, 2011 19 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 366 Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 367 Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 368 Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 369 Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 370 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 371 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 372 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 373 Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 374 Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 375 Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 376 Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 377 Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 378 Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 379 Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 380 Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 381 Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 382 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 383 Analog-to-Digital Converter (ADC) ............................................................................................. 384 Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 393 Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 394 Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 395 Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 396 Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 397 Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 398 Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 402 Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 403 Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 405 Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 406 Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 407 Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 409 Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 412 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 412 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 412 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 412 Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 413 Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 413 Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 413 Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 413 Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 414 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 414 Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 415 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 415 Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 417 Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 418 Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 419 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 420 Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 428 20 January 08, 2011 Texas Instruments-Production Data Table of Contents Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 430 Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 432 Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 434 Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 435 Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 436 Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 437 Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 439 Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 441 Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 443 Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 445 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 446 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 447 Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 449 Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 450 Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 451 Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 452 Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 453 Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 454 Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 455 Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 456 Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 457 Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 458 Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 459 Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 460 Synchronous Serial Interface (SSI) ............................................................................................ 461 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 473 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 475 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 477 Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 478 Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 480 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 481 Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 483 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 484 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 485 Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 486 Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 487 Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 488 Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 489 Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 490 Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 491 Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 492 Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 493 Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 494 Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 495 Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 496 Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 497 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 498 Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 513 January 08, 2011 21 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 514 Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 518 Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 519 Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 520 Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 521 Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 522 Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 523 Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 524 Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 526 Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 527 Register 12: I2C Slave Data (I2CSDR), offset 0x808 ........................................................................... 529 Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 530 Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 531 Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 532 Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 533 Controller Area Network (CAN) Module ..................................................................................... 534 Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 555 Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 557 Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 559 Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 560 Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 561 Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 562 Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 564 Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 565 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 565 Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 566 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 566 Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 568 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 568 Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 569 Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 569 Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 570 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 570 Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 571 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 571 Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 572 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 572 Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 574 Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 574 Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 574 Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 574 Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 574 Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 574 Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 574 Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 574 Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 575 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 575 22 January 08, 2011 Texas Instruments-Production Data Table of Contents Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 576 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 576 Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 577 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 577 Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 578 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 578 Analog Comparators ................................................................................................................... 579 Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 584 Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 585 Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 586 Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 587 Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 588 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 588 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 588 Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 589 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 589 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 589 Pulse Width Modulator (PWM) .................................................................................................... 591 Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 600 Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 601 Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 602 Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 603 Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 604 Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 605 Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 606 Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 607 Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 608 Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 609 Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 609 Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 609 Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 611 Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 611 Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 611 Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 614 Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 614 Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 614 Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 615 Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 615 Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 615 Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 616 Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 616 Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 616 Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 617 Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 617 Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 617 Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 618 Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 618 Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 618 January 08, 2011 23 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 619 Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 619 Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 619 Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 620 Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 620 Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 620 Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 623 Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 623 Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 623 Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 626 Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 626 Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 626 Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 627 Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 627 Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 627 Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 628 Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 628 Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 628 Quadrature Encoder Interface (QEI) .......................................................................................... 629 Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 634 Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 636 Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 637 Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 638 Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 639 Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 640 Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 641 Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 642 Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 643 Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 644 Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 645 24 January 08, 2011 Texas Instruments-Production Data Table of Contents Revision History The revision history table notes changes made between the indicated revisions of the LM3S2965 data sheet. Table 1. Revision History Date Revision Description ■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ to SYSRESREQ. ■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register. ■ Added "Reset Sources" table to System Control chapter. ■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported. ■ Added note that specific module clocks must be enabled before that module's registers can be programmed. There must be a delay of 3 system clocks after the module clock is enabled before any of that module's registers are accessed. ■ Changed I2C slave register base addresses and offsets to be relative to the I2C module base address of 0x4002.0000 and 0x4002.1000, so register bases and offsets were changed for all I2C slave registers. Note that the hw_i2c.h file in the StellarisWare Driver Library uses a base address of 0x4002.0800 and 0x4002.1800 for the I2C slave registers. Be aware when using registers with offsets between 0x800 and 0x818 that StellarisWare uses the old slave base address for these offsets. ■ Added GNDPHY and VCCPHY to Connections for Unused Signals tables. ■ Corrected nonlinearity and offset error parameters (EL, ED and EO) in ADC Characteristics table. ■ Added specification for maximum input voltage on a non-power pin when the microcontroller is unpowered (VNON parameter in Maximum Ratings table). ■ Additional minor data sheet clarifications and corrections. January 2011 9102 January 08, 2011 25 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 1. Revision History (continued) Date Revision Description ■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was added, including all the Cortex-M3 registers. ■ Changed register names to be consistent with StellarisWare® names: the Cortex-M3 Interrupt Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0) register. ■ Added clarification of instruction execution during Flash operations. ■ Modified Figure 8-1 on page 283 to clarify operation of the GPIO inputs when used as an alternate function. ■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits wide, bits[7:0]. ■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes the JTAG controller to be reset, resulting in a loss of JTAG communication. ■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode. ■ In Electrical Characteristics chapter: – Added ILKG parameter (GPIO input leakage current) to Table 22-4 on page 680. – Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 22-20 on page 690. ■ Added dimensions for Tray and Tape and Reel shipping mediums. September 2010 7787 ■ Corrected base address for SRAM in architectural overview chapter. ■ Clarified system clock operation, adding content to “Clock Control” on page 175. ■ Clarified CAN bit timing examples. ■ In Signal Tables chapter, added table "Connections for Unused Signals." ■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32. ■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time. ■ Additional minor data sheet clarifications and corrections. June 2010 7393 ■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed field width to 7 bits. ■ Removed erroneous text about restoring the Flash Protection registers. ■ Added note about RST signal routing. ■ Clarified the function of the TnSTALL bit in the GPTMCTL register. ■ Additional minor data sheet clarifications and corrections. April 2010 7007 26 January 08, 2011 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision Description ■ In "System Control" section, clarified Debug Access Port operation after Sleep modes. ■ Clarified wording on Flash memory access errors. ■ Added section on Flash interrupts. ■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers to be indeterminate. ■ Clarified operation of SSI transmit FIFO. ■ Made these changes to the Operating Characteristics chapter: – Added storage temperature ratings to "Temperature Characteristics" table – Added "ESD Absolute Maximum Ratings" table ■ Made these changes to the Electrical Characteristics chapter: – In "Flash Memory Characteristics" table, corrected Mass erase time – Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table) – In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time January 2010 6712 ■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode. ■ Removed erroneous reference to the WRC bit in the Hibernation chapter. ■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers because the module resets in 32-bit mode. ■ Clarified PWM source for ADC triggering. ■ Clarified CAN bit timing and corrected examples. ■ Made these changes to the Electrical Characteristics chapter: – Removed VSIH and VSIL parameters from Operating Conditions table. – Added table showing actual PLL frequency depending on input crystal. – Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS. – Revised ADC electrical specifications to clarify, including reorganizing and adding new data. – Changed SSI set up and hold times to be expressed in system clocks, not ns. October 2009 6462 July 2009 5920 Corrected ordering numbers. January 08, 2011 27 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 1. Revision History (continued) Date Revision Description ■ Clarified Power-on reset and RST pin operation; added new diagrams. ■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL) registers. ■ Clarified explanation of nonvolatile register programming in Internal Memory chapter. ■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1 registers. ■ Changed buffer type for WAKE pin to TTL and HIB pin to OD. ■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR (Internal voltage reference error) parameter. ■ Additional minor data sheet clarifications and corrections. July 2009 5902 ■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 164). ■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. ■ Added "GPIO Module DC Characteristics" table (see Table 22-4 on page 680). ■ Additional minor data sheet clarifications and corrections. April 2009 5367 ■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W. ■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO. ■ Corrected bit timing examples in CAN chapter. ■ Additional minor data sheet clarifications and corrections. January 2009 4660 ■ Revised High-Level Block Diagram. ■ Additional minor data sheet clarifications and corrections were made. November 2008 4283 ■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG) register. ■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the Internal Memory chapter. The correct value is 0x0000.0006. ■ In the CAN chapter, major improvements were made including a rewrite of the conceptual information and the addition of new figures to clarify how to use the Controller Area Network (CAN) module. ■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter. October 2008 4149 ■ Added note on clearing interrupts to Interrupts chapter. ■ Added Power Architecture diagram to System Control chapter. ■ Additional minor data sheet clarifications and corrections. August 2008 3447 July 2008 3108 ■ Additional minor data sheet clarifications and corrections. 28 January 08, 2011 Texas Instruments-Production Data Revision History Table 1. Revision History (continued) Date Revision Description ■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously indicated as available and have now been changed to a No Connect (NC): – Ball C1: Changed PE7 to NC – Ball C2: Changed PE6 to NC – Ball D2: Changed PE5 to NC – Ball D1: Changed PE4 to NC ■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use the LDO output as the source of VDD25 input. ■ Additional minor data sheet clarifications and corrections. May 2008 2972 April 2008 2881 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating Characteristics chapter. ■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock. ■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter. ■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter. ■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter was changed from a max of 100 to 250. ■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical Characteristics" chapter was changed from 4 to 3. ■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data sheets incorrectly noted it as 30 kHz ± 30%). ■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value. ■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC). ■ Two figures on clock source were added to the "Hibernation Module": – Clock Source Using Crystal – Clock Source Using Dedicated Oscillator ■ The following notes on battery management were added to the "Hibernation Module" chapter: – Battery voltage is not measured while in Hibernate mode. – System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. ■ A note on high-current applications was added to the GPIO chapter: For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only January 08, 2011 29 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 1. Revision History (continued) Date Revision Description a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. ■ A note on Schmitt inputs was added to the GPIO chapter: Pins configured as digital inputs are Schmitt-triggered. ■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables. ■ The "Differential Sampling Range" figures in the ADC chapter were clarified. ■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected: – The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins. – The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams. ■ Additional minor data sheet clarifications and corrections. March 2008 2550 Started tracking revision history. 30 January 08, 2011 Texas Instruments-Production Data Revision History About This Document This data sheet provides reference information for the LM3S2965 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following related documents are available on the Stellaris® web site at www.ti.com/stellaris: ■ Stellaris® Errata ■ ARM® Cortex™-M3 Errata ■ Cortex™-M3 Instruction Set Technical User's Manual ■ Stellaris® Graphics Library User's Guide ■ Stellaris® Peripheral Driver Library User's Guide The following related documents are also referenced: ■ ARM® Debug Interface V5 Architecture Specification ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers. January 08, 2011 31 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Documentation Conventions This document uses the conventions shown in Table 2 on page 32. Table 2. Documentation Conventions Notation Meaning General Register Notation APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. REGISTER bit A single bit in a register. bit field Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in Table 2-4 on page 71. offset 0xnnn Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register N Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. yy:xx This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Register Bit/Field Types RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. R/WC Software can read or write this field. Writing to it with any value clears the register. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1C Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. R/W1S Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. W1C WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted. Reset Value 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. 32 January 08, 2011 Texas Instruments-Production Data About This Document Table 2. Documentation Conventions (continued) Notation Meaning Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). assert a signal deassert a signal Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. SIGNAL Numbers An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. X Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x January 08, 2011 33 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 1 Architectural Overview The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. The Stellaris LM3S2000 series also marks the first integration of CAN capabilities with the revolutionary Cortex-M3 core. The LM3S2965 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S2965 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S2965 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S2965 microcontroller perfectly for battery applications. In addition, the LM3S2965 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S2965 microcontroller is code-compatible to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page 723 for ordering information for Stellaris family devices. 1.1 Product Features The LM3S2965 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication 34 January 08, 2011 Texas Instruments-Production Data Architectural Overview – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 42 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ ARM® Cortex™-M3 Processor Core – Compact core. – Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. – Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. – Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. – Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining – Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. – Migration from the ARM7™ processor family for better performance and power efficiency. – Full-featured debug solution • Serial Wire JTAG Debug Port (SWJ-DP) • Flash Patch and Breakpoint (FPB) unit for implementing breakpoints • Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling • Instrumentation Trace Macrocell (ITM) for support of printf style debugging • Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer – Optimized for single-cycle flash usage – Three sleep modes with clock gating for low power – Single-cycle multiply instruction and hardware divide – Atomic operations – ARM Thumb2 mixed 16-/32-bit instruction set January 08, 2011 35 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller – 1.25 DMIPS/MHz ■ JTAG – IEEE 1149.1-1990 compatible Test Access Port (TAP) controller – Four-bit Instruction Register (IR) chain for storing JTAG instructions – IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST – ARM additional instructions: APACC, DPACC and ABORT – Integrated ARM Serial Wire Debug (SWD) ■ Hibernation – System power control using discrete external regulator – Dedicated pin for waking from an external signal – Low-battery detection, signaling, and interrupt generation – 32-bit real-time clock (RTC) – Two 32-bit RTC match registers for timed wake-up and interrupt generation – Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal – RTC predivider trim for making fine adjustments to the clock rate – 64 32-bit words of non-volatile memory – Programmable interrupts for RTC match, external wake, and low battery events ■ Internal Memory – 256 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 64 KB single-cycle SRAM ■ GPIOs – 3-56 GPIOs, depending on configuration – 5-V-tolerant in input configuration – Programmable control for GPIO interrupts • Interrupt generation masking • Edge-triggered on rising, falling, or both 36 January 08, 2011 Texas Instruments-Production Data Architectural Overview • Level-sensitive on High or Low values – Bit masking in both read and write operations through address lines – Can initiate an ADC sample sequence – Pins configured as digital inputs are Schmitt-triggered. – Programmable control for GPIO pad configuration • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ General-Purpose Timers – Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: • As a single 32-bit timer • As one 32-bit Real-Time Clock (RTC) to event capture • For Pulse Width Modulation (PWM) • To trigger analog-to-digital conversions – 32-bit Timer modes • Programmable one-shot timer • Programmable periodic timer • Real-Time Clock when using an external 32.768-KHz clock as the input • User-enabled stalling when the controller asserts CPU Halt flag during debug • ADC event trigger – 16-bit Timer modes • General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) • Programmable one-shot timer • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug January 08, 2011 37 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller • ADC event trigger – 16-bit Input Capture modes • Input edge count capture • Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ ADC – Four analog input channels – Single-ended and differential-input configurations – On-chip internal temperature sensor – Sample rate of one million samples/second – Flexible, configurable analog-to-digital conversion – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs – Flexible trigger control • Controller (software) • Timers • Analog Comparators • PWM • GPIO – Hardware averaging of up to 64 samples for improved accuracy – Converter uses an internal 3-V reference 38 January 08, 2011 Texas Instruments-Production Data Architectural Overview – Power and ground for the analog circuitry is separate from the digital power and ground ■ UART – Three fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator allowing speeds up to 3.125 Mbps – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – Line-break generation and detection – Fully programmable serial interface characteristics • 5, 6, 7, or 8 data bits • Even, odd, stick, or no-parity bit generation/detection • 1 or 2 stop bit generation – IrDA serial-IR (SIR) encoder/decoder providing • Programmable use of IrDA Serial Infrared (SIR) or UART input/output • Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex • Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations • Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ■ Synchronous Serial Interface (SSI) – Two SSI modules, each with the following features: – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ I2C January 08, 2011 39 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller – Two I2C modules, each with the following features: – Devices on the I2C bus can be designated as either a master or a slave • Supports both sending and receiving data as either a master or a slave • Supports simultaneous master and slave operation – Four I2C modes • Master transmit • Master receive • Slave transmit • Slave receive – Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps) – Master and slave interrupt generation • Master generates interrupts when a transmit or receive operation completes (or aborts due to an error) • Slave generates interrupts when data has been sent or requested by a master – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ Controller Area Network (CAN) – Two CAN modules, each with the following features: – CAN protocol version 2.0 part A/B – Bit rates up to 1 Mbps – 32 message objects with individual identifier masks – Maskable interrupt – Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications – Programmable Loopback mode for self-test operation – Programmable FIFO mode enables storage of multiple message objects – Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals ■ Analog Comparators – Three independent integrated analog comparators – Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample sequence 40 January 08, 2011 Texas Instruments-Production Data Architectural Overview – Compare external pin input to external pin input or to internal programmable voltage reference – Compare a test voltage against any one of these voltages • An individual external reference voltage • A shared single external reference voltage • A shared internal reference voltage ■ PWM – Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector – One fault input in hardware to promote low-latency shutdown – One 16-bit counter • Runs in Down or Up/Down mode • Output frequency controlled by a 16-bit load value • Load value updates can be synchronized • Produces output signals at zero and load value – Two PWM comparators • Comparator value updates can be synchronized • Produces output signals on match – PWM generator • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals • Produces two independent PWM signals – Dead-band generator • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge • Can be bypassed, leaving input PWM signals unmodified – Flexible output control block with PWM output enable of each PWM signal • PWM output enable of each PWM signal • Optional output inversion of each PWM signal (polarity control) • Optional fault handling for each PWM signal • Synchronization of timers in the PWM generator blocks January 08, 2011 41 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller • Synchronization of timer/comparator updates across the PWM generator blocks • Interrupt status summary of the PWM generator blocks – Can initiate an ADC sample sequence ■ QEI – Two QEI modules, each with the following features: – Position integrator that tracks the encoder position – Velocity capture using built-in timer – The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system) – Interrupt generation on: • Index pulse • Velocity-timer expiration • Direction change • Quadrature error detection ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package 42 January 08, 2011 Texas Instruments-Production Data Architectural Overview ■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 44 depicts the features on the Stellaris LM3S2965 microcontroller. January 08, 2011 43 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 1-1. Stellaris LM3S2965 Microcontroller High-Level Block Diagram LM3S2965 ARM® Cortex™-M3 (50 MHz) NVIC MPU Flash (256 KB) DCode bus ICode bus JTAG/SWD System Control and Clocks Bus Matrix System Bus SRAM (64 KB) SYSTEM PERIPHERALS Watchdog Timer (1) Hibernation Module General- Purpose Timers (4) GPIOs (3-56) SERIAL PERIPHERALS UARTs (3) I2C (2) SSI (2) CAN Controllers (2) ANALOG PERIPHERALS ADC Channels (4) Analog Comparators (3) MOTION CONTROL PERIPHERALS QEI (2) PWM (6) Advanced Peripheral Bus (APB) 44 January 08, 2011 Texas Instruments-Production Data Architectural Overview 1.4 Functional Overview The following sections provide an overview of the features of the LM3S2965 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 723. 1.4.1 ARM Cortex™-M3 1.4.1.1 Processor Core (see page 52) All members of the Stellaris product family, including the LM3S2965 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. 1.4.1.2 Memory Map (see page 71) A memory map lists the location of instructions and data in memory. The memory map for the LM3S2965 controller can be found in Table 2-4 on page 71. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. 1.4.1.3 System Timer (SysTick) (see page 94) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 95) The LM3S2965 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 42 interrupts. January 08, 2011 45 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 1.4.1.5 System Control Block (SCB) (see page 97) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.4.1.6 Memory Protection Unit (MPU) (see page 97) The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S2965 controller features Pulse Width Modulation (PWM) outputs and the Quadrature Encoder Interface (QEI). 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S2965, PWM motion control functionality can be achieved through: ■ Dedicated, flexible motion control hardware using the PWM pins ■ The motion control features of the general-purpose timers using the CCP pins PWM Pins (see page 591) The LM3S2965 PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. CCP Pins (see page 330) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. Fault Pin (see page 596) The LM3S2965 PWM module includes one fault-condition handling input to quickly provide low-latency shutdown and prevent damage to the motor being controlled. 1.4.2.2 QEI (see page 629) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In 46 January 08, 2011 Texas Instruments-Production Data Architectural Overview addition, it can capture a running estimate of the velocity of the encoder wheel. The LM3S2965 microcontroller includes two QEI modules, which enables control of two motors at the same time. 1.4.3 Analog Peripherals To handle analog signals, the LM3S2965 microcontroller offers an Analog-to-Digital Converter (ADC). For support of analog signals, the LM3S2965 microcontroller offers three analog comparators. 1.4.3.1 ADC (see page 384) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The LM3S2965 ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 1.4.3.2 Analog Comparators (see page 579) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S2965 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 1.4.4 Serial Communications Peripherals The LM3S2965 controller supports both asynchronous and synchronous serial communications with: ■ Three fully programmable 16C550-type UARTs ■ Two SSI modules ■ Two I2C modules ■ Two CAN units January 08, 2011 47 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 1.4.4.1 UART (see page 420) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S2965 controller includes three fully programmable 16C550-type UARTs that support data transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 461) Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications interface. The LM3S2965 controller includes two SSI modules that provide the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. Each SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. Each SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 498) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S2965 controller includes two I2C modules that provide the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). 48 January 08, 2011 Texas Instruments-Production Data Architectural Overview Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.4.4 Controller Area Network (see page 534) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, now it is used in many embedded control applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The LM3S2965 includes two CAN units. 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 282) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is comprised of eight physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 3-56 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 648 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. Pins configured as digital inputs are Schmitt-triggered. 1.4.5.2 Four Programmable Timers (see page 324) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 360) A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. January 08, 2011 49 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S2965 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 256) The LM3S2965 static random access memory (SRAM) controller supports 64 KB SRAM. The internal SRAM of the Stellaris devices starts at base address 0x2000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 257) The LM3S2965 Flash controller supports 256 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 Additional Features 1.4.7.1 JTAG TAP Controller (see page 158) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. 1.4.7.2 System Control and Clocks (see page 170) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 50 January 08, 2011 Texas Instruments-Production Data Architectural Overview 1.4.7.3 Hibernation Module (see page 236) The Hibernation module provides logic to switch power off to the main processor and peripherals, and to wake on external or time-based events. The Hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 646 ■ “Signal Tables” on page 648 ■ “Operating Characteristics” on page 678 ■ “Electrical Characteristics” on page 679 ■ “Package Information” on page 725 January 08, 2011 51 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 2 The Cortex-M3 Processor The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer ■ Optimized for single-cycle flash usage ■ Three sleep modes with clock gating for low power ■ Single-cycle multiply instruction and hardware divide ■ Atomic operations ■ ARM Thumb2 mixed 16-/32-bit instruction set ■ 1.25 DMIPS/MHz The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motor control. 52 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.1 Block Diagram The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction set, ensuring high code density and reduced program memory requirements. The Cortex-M3 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver industry-leading interrupt performance. The Stellaris NVIC includes a non-maskable interrupt (NMI) and provides eight interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency. The hardware stacking of registers and the ability to suspend load-multiple and store-multiple operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be rapidly powered down. January 08, 2011 53 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 2-1. CPU Block Diagram Private Peripheral Bus (internal) Data Watchpoint and Trace Interrupts Debug Sleep Instrumentation Trace Macrocell Trace Port Interface Unit CM3 Core Instructions Data Flash Patch and Breakpoint Memory Protection Unit Debug Access Port Nested Vectored Interrupt Controller Serial Wire JTAG Debug Port Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus ROM Table Serial Wire Output Trace Port (SWO) ARM Cortex-M3 2.2 Overview 2.2.1 System-Level Interface The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide high-speed, low-latency memory accesses. The core supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and thread-safe Boolean data handling. The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory control, enabling applications to implement security privilege levels and separate code, data and stack on a task-by-task basis. 2.2.2 Integrated Configurable Debug The Cortex-M3 processor implements a complete hardware debug solution, providing high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification for details on SWJ-DP. For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin. 54 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory. If a patch is required, the application programs the FPB to remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table specified in the FPB configuration. For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5 Architecture Specification. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer, as shown in Figure 2-2 on page 55. Figure 2-2. TPIU Block Diagram ATB Interface Asynchronous FIFO APB Interface Trace Out (serializer) Debug ATB Slave Port APB Slave Port Serial Wire Trace Port (SWO) 2.2.4 Cortex-M3 System Component Details The Cortex-M3 includes the following system components: ■ SysTick A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer or as a simple counter (see “System Timer (SysTick)” on page 94). ■ Nested Vectored Interrupt Controller (NVIC) An embedded interrupt controller that supports low latency interrupt processing (see “Nested Vectored Interrupt Controller (NVIC)” on page 95). ■ System Control Block (SCB) January 08, 2011 55 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions( see “System Control Block (SCB)” on page 97). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions. The MPU provides up to eight different regions and an optional predefined background region (see “Memory Protection Unit (MPU)” on page 97). 2.3 Programming Model This section describes the Cortex-M3 programming model. In addition to the individual core register descriptions, information about the processor modes and privilege levels for software execution and stacks is included. 2.3.1 Processor Mode and Privilege Levels for Software Execution The Cortex-M3 has two modes of operation: ■ Thread mode Used to execute application software. The processor enters Thread mode when it comes out of reset. ■ Handler mode Used to handle exceptions. When the processor has finished exception processing, it returns to Thread mode. In addition, the Cortex-M3 has two privilege levels: ■ Unprivileged In this mode, software has the following restrictions: – Limited access to the MSR and MRS instructions and no use of the CPS instruction – No access to the system timer, NVIC, or system control block – Possibly restricted access to memory or peripherals ■ Privileged In this mode, software can use all the instructions and has access to all resources. In Thread mode, the CONTROL register (see page 70) controls whether software execution is privileged or unprivileged. In Handler mode, software execution is always privileged. Only privileged software can write to the CONTROL register to change the privilege level for software execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to privileged software. 2.3.2 Stacks The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked item on the stack memory. When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item to the new memory location. The processor implements 56 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor two stacks: the main stack and the process stack, with independent copies of the stack pointer (see the SP register on page 60). In Thread mode, the CONTROL register (see page 70) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 57. Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use Processor Mode Use Privilege Level Stack Used Thread Applications Privileged or unprivileged a Main stack or process stack a Handler Exception handlers Always privileged Main stack a. See CONTROL (page 70). 2.3.3 Register Map Figure 2-3 on page 57 shows the Cortex-M3 register set. Table 2-2 on page 58 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset. Figure 2-3. Cortex-M3 Register Set SP (R13) LR (R14) PC (R15) R5 R6 R7 R0 R1 R3 R4 R2 R10 R11 R12 R8 R9 Low registers High registers PSP‡ MSP‡ PSR PRIMASK FAULTMASK BASEPRI CONTROL General-purpose registers Stack Pointer Link Register Program Counter Program status register Exception mask registers CONTROL register Special registers ‡Banked version of SP January 08, 2011 57 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-2. Processor Register Map See Offset Name Type Reset Description page - R0 R/W - Cortex General-Purpose Register 0 59 - R1 R/W - Cortex General-Purpose Register 1 59 - R2 R/W - Cortex General-Purpose Register 2 59 - R3 R/W - Cortex General-Purpose Register 3 59 - R4 R/W - Cortex General-Purpose Register 4 59 - R5 R/W - Cortex General-Purpose Register 5 59 - R6 R/W - Cortex General-Purpose Register 6 59 - R7 R/W - Cortex General-Purpose Register 7 59 - R8 R/W - Cortex General-Purpose Register 8 59 - R9 R/W - Cortex General-Purpose Register 9 59 - R10 R/W - Cortex General-Purpose Register 10 59 - R11 R/W - Cortex General-Purpose Register 11 59 - R12 R/W - Cortex General-Purpose Register 12 59 - SP R/W - Stack Pointer 60 - LR R/W 0xFFFF.FFFF Link Register 61 - PC R/W - Program Counter 62 - PSR R/W 0x0100.0000 Program Status Register 63 - PRIMASK R/W 0x0000.0000 Priority Mask Register 67 - FAULTMASK R/W 0x0000.0000 Fault Mask Register 68 - BASEPRI R/W 0x0000.0000 Base Priority Mask Register 69 - CONTROL R/W 0x0000.0000 Control Register 70 2.3.4 Register Descriptions This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 57. The core registers are not memory mapped and are accessed by register name rather than offset. Note: The register type shown in the register descriptions refers to type during program execution in Thread mode and Handler mode. Debug access can differ. 58 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Register 1: Cortex General-Purpose Register 0 (R0) Register 2: Cortex General-Purpose Register 1 (R1) Register 3: Cortex General-Purpose Register 2 (R2) Register 4: Cortex General-Purpose Register 3 (R3) Register 5: Cortex General-Purpose Register 4 (R4) Register 6: Cortex General-Purpose Register 5 (R5) Register 7: Cortex General-Purpose Register 6 (R6) Register 8: Cortex General-Purpose Register 7 (R7) Register 9: Cortex General-Purpose Register 8 (R8) Register 10: Cortex General-Purpose Register 9 (R9) Register 11: Cortex General-Purpose Register 10 (R10) Register 12: Cortex General-Purpose Register 11 (R11) Register 13: Cortex General-Purpose Register 12 (R12) The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from either privileged or unprivileged mode. Cortex General-Purpose Register 0 (R0) Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 DATA R/W - Register data. January 08, 2011 59 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode. Stack Pointer (SP) Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SP Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SP Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 SP R/W - This field is the address of the stack pointer. 60 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 87 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LINK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LINK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description 31:0 LINK R/W 0xFFFF.FFFF This field is the return address. January 08, 2011 61 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode. Program Counter (PC) Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PC Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PC Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 PC R/W - This field is the current program address. 62 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR. The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions: ■ Application Program Status Register (APSR), bits 31:27, ■ Execution Program Status Register (EPSR), bits 26:24, 15:10 ■ Interrupt Program Status Register (IPSR), bits 5:0 The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags from previous instruction executions. EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see “Exception Entry and Return” on page 85). IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. page 63 shows the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual for more information about how to access the program status registers. Table 2-3. PSR Register Combinations Register Type Combination PSR R/Wa, b APSR, EPSR, and IPSR IEPSR RO EPSR and IPSR IAPSR R/Wa APSR and IPSR EAPSR R/Wb APSR and EPSR a. The processor ignores writes to the IPSR bits. b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. Program Status Register (PSR) Type R/W, reset 0x0100.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 N Z C V Q ICI / IT THUMB reserved Type R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICI / IT reserved ISRNUM Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 January 08, 2011 63 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. The previous operation result was positive, zero, greater than, or equal. 0 The value of this bit is only meaningful when accessing PSR or APSR. 31 N R/W 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z R/W 0 APSR Carry or Borrow Flag Value Description The previous add operation resulted in a carry bit or the previous subtract operation did not result in a borrow bit. 1 The previous add operation did not result in a carry bit or the previous subtract operation resulted in a borrow bit. 0 The value of this bit is only meaningful when accessing PSR or APSR. 29 C R/W 0 APSR Overflow Flag Value Description 1 The previous operation resulted in an overflow. 0 The previous operation did not result in an overflow. The value of this bit is only meaningful when accessing PSR or APSR. 28 V R/W 0 APSR DSP Overflow and Saturation Flag Value Description 1 DSP Overflow or saturation has occurred. DSP overflow or saturation has not occurred since reset or since the bit was last cleared. 0 The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. 27 Q R/W 0 64 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Bit/Field Name Type Reset Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 26:25 ICI / IT RO 0x0 EPSR Thumb State This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit: ■ The BLX, BX and POP{PC} instructions ■ Restoration from the stacked xPSR value on an exception return ■ Bit 0 of the vector value on an exception entry Attempting to execute instructions when this bit is clear results in a fault or lockup. See “Lockup” on page 89 for more information. The value of this bit is only meaningful when accessing PSR or EPSR. 24 THUMB RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:16 reserved RO 0x00 EPSR ICI / IT status These bits, along with bits 26:25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH or POP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15:12. After servicing the interrupt, the processor returns to the register pointed to by bits 15:12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11:10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. The value of this field is only meaningful when accessing PSR or EPSR. 15:10 ICI / IT RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:6 reserved RO 0x0 January 08, 2011 65 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR). Value Description 0x00 Thread mode 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3B Interrupt Vector 43 0x3C-0x3F Reserved See “Exception Types” on page 80 for more information. The value of this field is only meaningful when accessing PSR or IPSR. 5:0 ISRNUM RO 0x00 66 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 80. Priority Mask Register (PRIMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x0000.000 Priority Mask Value Description Prevents the activation of all exceptions with configurable priority. 1 0 No effect. 0 PRIMASK R/W 0 January 08, 2011 67 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on these instructions. For more information on exception priority levels, see “Exception Types” on page 80. Fault Mask Register (FAULTMASK) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FAULTMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x0000.000 Fault Mask Value Description 1 Prevents the activation of all exceptions except for NMI. 0 No effect. The processor clears the FAULTMASK bit on exit from any exception handler except the NMI handler. 0 FAULTMASK R/W 0 68 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. For more information on exception priority levels, see “Exception Types” on page 80. Base Priority Mask Register (BASEPRI) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BASEPRI reserved Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0000.00 Base Priority Any exception that has a programmable priority level with the same or lower priority as the value of this field is masked. The PRIMASK register can be used to mask all exceptions with programmable priority levels. Higher priority exceptions have lower priority levels. Value Description 0x0 All exceptions are unmasked. 0x1 All exceptions with priority level 1-7 are masked. 0x2 All exceptions with priority level 2-7 are masked. 0x3 All exceptions with priority level 3-7 are masked. 0x4 All exceptions with priority level 4-7 are masked. 0x5 All exceptions with priority level 5-7 are masked. 0x6 All exceptions with priority level 6-7 are masked. 0x7 All exceptions with priority level 7 are masked. 7:5 BASEPRI R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 reserved RO 0x0 January 08, 2011 69 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 87). In an OS environment, threads running in Thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex™-M3 Instruction Set Technical User's Manual, or perform an exception return to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 87. Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex™-M3 Instruction Set Technical User's Manual. Control Register (CONTROL) Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ASP TMPL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0000.000 Active Stack Pointer Value Description 1 PSP is the current stack pointer. 0 MSP is the current stack pointer In Handler mode, this bit reads as zero and ignores writes. The Cortex-M3 updates this bit automatically on exception return. 1 ASP R/W 0 Thread Mode Privilege Level Value Description 1 Unprivileged software can be executed in Thread mode. 0 Only privileged software can be executed in Thread mode. 0 TMPL R/W 0 70 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor 2.3.5 Exceptions and Interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 85 for more information. The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” on page 95 for more information. 2.3.6 Data Types The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports 64-bit data transfer instructions. All instruction and data memory accesses are little endian. See “Memory Regions, Types and Attributes” on page 73 for more information. 2.4 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory. The memory map for the LM3S2965 controller is provided in Table 2-4 on page 71. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data (see “Bit-Banding” on page 75). The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers (see “Cortex-M3 Peripherals” on page 94). Note: Within the memory map, all reserved space returns a bus fault when read or written. Table 2-4. Memory Map For details, see page ... Start End Description Memory 0x0000.0000 0x0003.FFFF On-chip Flash 257 0x0004.0000 0x1FFF.FFFF Reserved - 0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAM 256 0x2001.0000 0x21FF.FFFF Reserved - 0x2200.0000 0x221F.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 256 0x2220.0000 0x3FFF.FFFF Reserved - FiRM Peripherals 0x4000.0000 0x4000.0FFF Watchdog timer 0 363 0x4000.1000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 289 0x4000.5000 0x4000.5FFF GPIO Port B 289 0x4000.6000 0x4000.6FFF GPIO Port C 289 0x4000.7000 0x4000.7FFF GPIO Port D 289 0x4000.8000 0x4000.8FFF SSI0 472 January 08, 2011 71 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-4. Memory Map (continued) For details, see page ... Start End Description 0x4000.9000 0x4000.9FFF SSI1 472 0x4000.A000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 427 0x4000.D000 0x4000.DFFF UART1 427 0x4000.E000 0x4000.EFFF UART2 427 0x4000.F000 0x4001.FFFF Reserved - Peripherals 0x4002.0000 0x4002.0FFF I2C 0 512 0x4002.1000 0x4002.1FFF I2C 1 512 0x4002.2000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 289 0x4002.5000 0x4002.5FFF GPIO Port F 289 0x4002.6000 0x4002.6FFF GPIO Port G 289 0x4002.7000 0x4002.7FFF GPIO Port H 289 0x4002.8000 0x4002.8FFF PWM 599 0x4002.9000 0x4002.BFFF Reserved - 0x4002.C000 0x4002.CFFF QEI0 633 0x4002.D000 0x4002.DFFF QEI1 633 0x4002.E000 0x4002.FFFF Reserved - 0x4003.0000 0x4003.0FFF Timer 0 335 0x4003.1000 0x4003.1FFF Timer 1 335 0x4003.2000 0x4003.2FFF Timer 2 335 0x4003.3000 0x4003.3FFF Timer 3 335 0x4003.4000 0x4003.7FFF Reserved - 0x4003.8000 0x4003.8FFF ADC0 392 0x4003.9000 0x4003.BFFF Reserved - 0x4003.C000 0x4003.CFFF Analog Comparators 579 0x4003.D000 0x4003.FFFF Reserved - 0x4004.0000 0x4004.0FFF CAN0 Controller 553 0x4004.1000 0x4004.1FFF CAN1 Controller 553 0x4004.2000 0x400F.BFFF Reserved - 0x400F.C000 0x400F.CFFF Hibernation Module 243 0x400F.D000 0x400F.DFFF Flash memory control 261 0x400F.E000 0x400F.EFFF System control 183 0x400F.F000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0xDFFF.FFFF Reserved - Private Peripheral Bus 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 54 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 54 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 54 72 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-4. Memory Map (continued) For details, see page ... Start End Description 0xE000.3000 0xE000.DFFF Reserved - 0xE000.E000 0xE000.EFFF Cortex-M3 Peripherals (SysTick, NVIC, SCB, and MPU) 79 0xE000.F000 0xE003.FFFF Reserved - 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 55 0xE004.1000 0xFFFF.FFFF Reserved - 2.4.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region. The memory types are: ■ Normal: The processor can re-order transactions for efficiency and perform speculative reads. ■ Device: The processor preserves transaction order relative to other transactions to Device or Strongly Ordered memory. ■ Strongly Ordered: The processor preserves transaction order relative to all other transactions. The different ordering requirements for Device and Strongly Ordered memory mean that the memory system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory. An additional memory attribute is Execute Never (XN), which means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. 2.4.2 Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing the order does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions (see “Software Ordering of Memory Accesses” on page 74). However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before A2. 2.4.3 Behavior of Memory Accesses Table 2-5 on page 74 shows the behavior of accesses to each region in the memory map. See “Memory Regions, Types and Attributes” on page 73 for more information on memory types and the XN attribute. Stellaris devices may have reserved memory areas within the address ranges shown below (refer to Table 2-4 on page 71 for more information). January 08, 2011 73 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-5. Memory Access Behavior Execute Description Never (XN) Address Range Memory Region Memory Type This executable region is for program code. Data can also be stored here. 0x0000.0000 - 0x1FFF.FFFF Code Normal - This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 76). 0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This region includes bit band and bit band alias areas (see Table 2-7 on page 76). 0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN 0x6000.0000 - 0x9FFF.FFFF External RAM Normal - This executable region is for data. 0xA000.0000 - 0xDFFF.FFFF External device Device XN This region is for external device memory. This region includes the NVIC, system timer, and system control block. Strongly XN Ordered Private peripheral bus 0xE000.0000- 0xE00F.FFFF 0xE010.0000- 0xFFFF.FFFF Reserved - - - The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that programs always use the Code region because the Cortex-M3 has separate buses that can perform instruction fetches and data accesses simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit (MPU)” on page 97. The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch target addresses. 2.4.4 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions for the following reasons: ■ The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. ■ The processor has multiple bus interfaces. ■ Memory or devices in the memory map have different wait states. ■ Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” on page 73 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The Cortex-M3 has the following memory barrier instructions: ■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions. ■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before subsequent instructions execute. ■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. 74 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Memory barrier instructions can be used in the following situations: ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU configuration code is entered using exception mechanisms, then an ISB instruction is not required. ■ Vector table If the program changes an entry in the vector table and then enables the corresponding exception, use a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken immediately after being enabled, the processor uses the new exception vector. ■ Self-modifying code If a program contains self-modifying code, use an ISB instruction immediately after the code modification in the program. The ISB instruction ensures subsequent instruction execution uses the updated program. ■ Memory map switching If the system contains a memory map switching mechanism, use a DSB instruction after switching the memory map in the program. The DSB instruction ensures subsequent instruction execution uses the updated memory map. ■ Dynamic exception priority change When an exception priority has to change when the exception is pending or active, use DSB instructions after the change. The change then takes effect on completion of the DSB instruction. Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use of DMB instructions. For more information on the memory barrier instructions, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.4.5 Bit-Banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table 2-6 on page 76. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band region, as shown in Table 2-7 on page 76. For the specific address range of the bit-band regions, see Table 2-4 on page 71. Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in the SRAM or peripheral bit-band region. A word access to a bit band address results in a word access to the underlying memory, and similarly for halfword and byte accesses. This allows bit band accesses to match the access requirements of the underlying peripheral. January 08, 2011 75 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-6. SRAM Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 0x2000.0000 - 0x200F.FFFF SRAM bit-band region Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not remapped. 0x2200.0000 - 0x23FF.FFFF SRAM bit-band alias Table 2-7. Peripheral Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bit addressable through bit-band alias. 0x4000.0000 - 0x400F.FFFF Peripheral bit-band region Data accesses to this region are remapped to bit band region. A write operation is performed as read-modify-write. Instruction accesses are not permitted. 0x4200.0000 - 0x43FF.FFFF Peripheral bit-band alias The following formula shows how the alias region maps onto the bit-band region: bit_word_offset = (byte_offset x 32) + (bit_number x 4) bit_word_addr = bit_band_base + bit_word_offset where: bit_word_offset The position of the target bit in the bit-band memory region. bit_word_addr The address of the word in the alias memory region that maps to the targeted bit. bit_band_base The starting address of the alias region. byte_offset The number of the byte in the bit-band region that contains the targeted bit. bit_number The bit position, 0-7, of the targeted bit. Figure 2-4 on page 77 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: ■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4) ■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF: 0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4) 76 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) Figure 2-4. Bit-Band Mapping 0x23FF.FFE4 0x2200.0004 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE0 0x2200.001C 0x2200.0018 0x2200.0014 0x2200.0010 0x2200.000C 0x2200.0008 0x2200.0000 32-MB Alias Region 0 7 0 7 0 0x2000.0003 0x2000.0002 0x2000.0001 0x2000.0000 6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0x200F.FFFF 0x200F.FFFE 0x200F.FFFD 0x200F.FFFC 1-MB SRAM Bit-Band Region 2.4.5.1 Directly Accessing an Alias Region Writing to a word in the alias region updates a single bit in the bit-band region. Bit 0 of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a value with bit 0 clear writes a 0 to the bit-band bit. Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as writing 0xFF. Writing 0x00 has the same effect as writing 0x0E. When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set. 2.4.5.2 Directly Accessing a Bit-Band Region “Behavior of Memory Accesses” on page 73 describes the behavior of direct byte, halfword, or word accesses to the bit-band regions. 2.4.6 Data Storage The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the January 08, 2011 77 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 78 illustrates how data is stored. Figure 2-5. Data Storage Memory Register Address A A+1 lsbyte msbyte A+2 A+3 7 0 B3 B2 B1 B0 31 24 23 16 15 8 7 0 B0 B1 B2 B3 2.4.7 Synchronization Primitives The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory location. Software can use these primitives to perform a guaranteed read-modify-write memory update sequence or for a semaphore mechanism. A pair of synchronization primitives consists of: ■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests exclusive access to that location. ■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and returns a status bit to a register. If this status bit is clear, it indicates that the thread or process gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates that the thread or process did not gain exclusive access to the memory and no write is performed. The pairs of Load-Exclusive and Store-Exclusive instructions are: ■ The word instructions LDREX and STREX ■ The halfword instructions LDREXH and STREXH ■ The byte instructions LDREXB and STREXB Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction. To perform a guaranteed read-modify-write of a memory location, software must: 1. Use a Load-Exclusive instruction to read the value of the location. 2. Update the value, as required. 3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location, and test the returned status bit. If the status bit is clear, the read-modify-write completed successfully; if the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 78 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor 1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free. 2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore address. 3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the software has claimed the semaphore. However, if the Store-Exclusive failed, another process might have claimed the semaphore after the software performed step 1. The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has executed a Load-Exclusive instruction. The processor removes its exclusive access tag if: ■ It executes a CLREX instruction. ■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds. ■ An exception occurs, which means the processor can resolve semaphore conflicts between different threads. For more information about the synchronization primitive instructions, see the Cortex™-M3 Instruction Set Technical User's Manual. 2.5 Exception Model The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on an exception and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 2-8 on page 81 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 42 interrupts (listed in Table 2-9 on page 82). Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn) registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting priority levels into preemption priorities and subpriorities. All the interrupt registers are described in “Nested Vectored Interrupt Controller (NVIC)” on page 95. Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset, Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for all the programmable priorities. Important: After a write to clear an interrupt source, it may take several processor cycles for the NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the last action in an interrupt handler, it is possible for the interrupt handler to complete while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 95 for more information on exceptions and interrupts. January 08, 2011 79 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 2.5.1 Exception States Each exception is in one of the following states: ■ Inactive. The exception is not active and not pending. ■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending. ■ Active. An exception that is being serviced by the processor but has not completed. Note: An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state. ■ Active and Pending. The exception is being serviced by the processor, and there is a pending exception from the same source. 2.5.2 Exception Types The exception types are: ■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. ■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by software using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs cannot be masked or prevented from activation by any other exception or preempted by any exception other than reset. ■ Hard Fault. A hard fault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority. ■ Memory Management Fault. A memory management fault is an exception that occurs because of a memory protection related fault, including access violation and no match. The MPU or the fixed memory protection constraints determine this fault, for both instruction and data memory transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled. ■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction such as a prefetch fault or a memory access fault. This fault can be enabled or disabled. ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution 80 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers. ■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception is only active when enabled. This exception does not activate if it is a lower priority than the current activation. ■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active. PendSV is triggered using the Interrupt Control and State (INTCTRL) register. ■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor can use this exception as system tick. ■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-9 on page 82 lists the interrupts on the LM3S2965 controller. For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Privileged software can disable the exceptions that Table 2-8 on page 81 shows as having configurable priority (see the SYSHNDCTRL register on page 136 and the DIS0 register on page 111). For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” on page 87. Table 2-8. Exception Types Vector Address or Activation Offsetb Vector Prioritya Number Exception Type Stack top is loaded from the first entry of the vector table on reset. - 0 - 0x0000.0000 Reset 1 -3 (highest) 0x0000.0004 Asynchronous Non-Maskable Interrupt 2 -2 0x0000.0008 Asynchronous (NMI) Hard Fault 3 -1 0x0000.000C - Memory Management 4 programmablec 0x0000.0010 Synchronous Synchronous when precise and asynchronous when imprecise Bus Fault 5 programmablec 0x0000.0014 Usage Fault 6 programmablec 0x0000.0018 Synchronous - 7-10 - - Reserved SVCall 11 programmablec 0x0000.002C Synchronous Debug Monitor 12 programmablec 0x0000.0030 Synchronous - 13 - - Reserved January 08, 2011 81 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-8. Exception Types (continued) Vector Address or Activation Offsetb Vector Prioritya Number Exception Type PendSV 14 programmablec 0x0000.0038 Asynchronous SysTick 15 programmablec 0x0000.003C Asynchronous Interrupts 16 and above programmabled 0x0000.0040 and above Asynchronous a. 0 is the default priority for all the programmable priorities. b. See “Vector Table” on page 83. c. See SYSPRI1 on page 133. d. See PRIn registers on page 119. Table 2-9. Interrupts Vector Address or Description Offset Interrupt Number (Bit in Interrupt Registers) Vector Number 0x0000.0000 - Processor exceptions 0x0000.003C 0-15 - 16 0 0x0000.0040 GPIO Port A 17 1 0x0000.0044 GPIO Port B 18 2 0x0000.0048 GPIO Port C 19 3 0x0000.004C GPIO Port D 20 4 0x0000.0050 GPIO Port E 21 5 0x0000.0054 UART0 22 6 0x0000.0058 UART1 23 7 0x0000.005C SSI0 24 8 0x0000.0060 I2C0 25 9 - Reserved 26 10 0x0000.0068 PWM Generator 0 27 11 0x0000.006C PWM Generator 1 28 12 0x0000.0070 PWM Generator 2 29 13 0x0000.0074 QEI0 30 14 0x0000.0078 ADC0 Sequence 0 31 15 0x0000.007C ADC0 Sequence 1 32 16 0x0000.0080 ADC0 Sequence 2 33 17 0x0000.0084 ADC0 Sequence 3 34 18 0x0000.0088 Watchdog Timer 0 35 19 0x0000.008C Timer 0A 36 20 0x0000.0090 Timer 0B 37 21 0x0000.0094 Timer 1A 38 22 0x0000.0098 Timer 1B 39 23 0x0000.009C Timer 2A 40 24 0x0000.00A0 Timer 2B 41 25 0x0000.00A4 Analog Comparator 0 42 26 0x0000.00A8 Analog Comparator 1 43 27 0x0000.00AC Analog Comparator 2 44 28 0x0000.00B0 System Control 82 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-9. Interrupts (continued) Vector Address or Description Offset Interrupt Number (Bit in Interrupt Registers) Vector Number 45 29 0x0000.00B4 Flash Memory Control 46 30 0x0000.00B8 GPIO Port F 47 31 0x0000.00BC GPIO Port G 48 32 0x0000.00C0 GPIO Port H 49 33 0x0000.00C4 UART2 50 34 0x0000.00C8 SSI1 51 35 0x0000.00CC Timer 3A 52 36 0x0000.00D0 Timer 3B 53 37 0x0000.00D4 I2C1 54 38 0x0000.00D8 QEI1 55 39 0x0000.00DC CAN0 56 40 0x0000.00E0 CAN1 57-58 41-42 - Reserved 59 43 0x0000.00EC Hibernation Module 2.5.3 Exception Handlers The processor handles exceptions using: ■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs. ■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault exceptions handled by the fault handlers. ■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system exceptions that are handled by system handlers. 2.5.4 Vector Table The vector table contains the reset value of the stack pointer and the start addresses, also called exception vectors, for all exception handlers. The vector table is constructed using the vector address or offset shown in Table 2-8 on page 81. Figure 2-6 on page 84 shows the order of the exception vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the exception handler is Thumb code January 08, 2011 83 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 2-6. Vector table Initial SP value Reset Hard fault NMI Memory management fault Usage fault Bus fault 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 Reserved SVCall PendSV Reserved for Debug Systick IRQ0 Reserved 0x002C 0x0038 0x003C 0x0040 Exception number Offset 2 3 4 5 6 11 12 14 15 16 18 13 7 10 1 Vector ... 8 9 IRQ1 IRQ2 0x0044 IRQ43 17 0x0048 0x004C 59 ... ... 0x00EC IRQ number -14 -13 -12 -11 -10 -5 -2 -1 0 2 1 43 On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 83). Note that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary. 2.5.5 Exception Priorities As Table 2-8 on page 81 shows, all exceptions have an associated priority, with a lower priority value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For information about configuring exception priorities, see page 133 and page 119. Note: Configurable priority values for the Stellaris implementation are in the range 0-7. This means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values, always have higher priority than any other exception. For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0]. 84 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending. 2.5.6 Interrupt Priority Grouping To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping divides each interrupt priority register entry into two fields: ■ An upper field that defines the group priority ■ A lower field that defines a subpriority within the group Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the handler. If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ number is processed first. For information about splitting the interrupt priority fields into group priority and subpriority, see page 127. 2.5.7 Exception Entry and Return Descriptions of exception handling use the following terms: ■ Preemption. When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is higher than the priority of the exception being handled. See “Interrupt Priority Grouping” on page 85 for more information about preemption by an interrupt. When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” on page 86 more information. ■ Return. Return occurs when the exception handler is completed, and there is no pending exception with sufficient priority to be serviced and the completed exception handler was not handling a late-arriving exception. The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See “Exception Return” on page 87 for more information. ■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception handler. ■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception, the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore, the state saving continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception handler of the original exception enters the execute stage of the processor. On January 08, 2011 85 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception. When one exception preempts another, the exceptions are nested. Sufficient priority means the exception has more priority than any limits set by the mask registers (see PRIMASK on page 67, FAULTMASK on page 68, and BASEPRI on page 69). An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack. This operation is referred to as stacking and the structure of eight data words is referred to as stack frame. Figure 2-7. Exception Stack Frame Pre-IRQ top of stack xPSR PC LR R12 R3 R2 R1 R0 {aligner} IRQ top of stack ... Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during stacking. The stack frame includes the return address, which is the address of the next instruction in the interrupted program. This value is restored to the PC at exception return so that the interrupted program resumes. In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR, indicating which stack pointer corresponds to the stack frame and what operation mode the processor was in before the entry occurred. If no higher-priority exception occurs during exception entry, the processor starts executing the exception handler and automatically changes the status of the corresponding pending interrupt to active. If another higher-priority exception occurs during exception entry, known as late arrival, the processor starts executing the exception handler for this exception and does not change the pending status of the earlier exception. 86 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor 2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest four bits of this value provide information on the return stack and processor mode. Table 2-10 on page 87 shows the EXC_RETURN values with a description of the exception return behavior. EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence. Table 2-10. Exception Return Behavior EXC_RETURN[31:0] Description 0xFFFF.FFF0 Reserved Return to Handler mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFF1 0xFFFF.FFF2 - 0xFFFF.FFF8 Reserved Return to Thread mode. Exception return uses state from MSP. Execution uses MSP after return. 0xFFFF.FFF9 0xFFFF.FFFA - 0xFFFF.FFFC Reserved Return to Thread mode. Exception return uses state from PSP. Execution uses PSP after return. 0xFFFF.FFFD 0xFFFF.FFFE - 0xFFFF.FFFF Reserved 2.6 Fault Handling Faults are a subset of the exceptions (see “Exception Model” on page 79). The following conditions generate a fault: ■ A bus error on an instruction fetch or vector table load or a data access. ■ An internally detected error such as an undefined instruction or an attempt to change state with a BX instruction. ■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN). ■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region. 2.6.1 Fault Types Table 2-11 on page 88 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 140 for more information about the fault status registers. January 08, 2011 87 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-11. Faults Fault Handler Fault Status Register Bit Name Bus error on a vector read Hard fault Hard Fault Status (HFAULTSTAT) VECT Fault escalated to a hard fault Hard fault Hard Fault Status (HFAULTSTAT) FORCED Memory Management Fault Status IERR a (MFAULTSTAT) Memory management fault MPU or default memory mismatch on instruction access Memory Management Fault Status DERR (MFAULTSTAT) Memory management fault MPU or default memory mismatch on data access Memory Management Fault Status MSTKE (MFAULTSTAT) Memory management fault MPU or default memory mismatch on exception stacking Memory Management Fault Status MUSTKE (MFAULTSTAT) Memory management fault MPU or default memory mismatch on exception unstacking Bus error during exception stacking Bus fault Bus Fault Status (BFAULTSTAT) BSTKE Bus error during exception unstacking Bus fault Bus Fault Status (BFAULTSTAT) BUSTKE Bus error during instruction prefetch Bus fault Bus Fault Status (BFAULTSTAT) IBUS Precise data bus error Bus fault Bus Fault Status (BFAULTSTAT) PRECISE Imprecise data bus error Bus fault Bus Fault Status (BFAULTSTAT) IMPRE Attempt to access a coprocessor Usage fault Usage Fault Status (UFAULTSTAT) NOCP Undefined instruction Usage fault Usage Fault Status (UFAULTSTAT) UNDEF Attempt to enter an invalid instruction Usage fault Usage Fault Status (UFAULTSTAT) INVSTAT set state b Invalid EXC_RETURN value Usage fault Usage Fault Status (UFAULTSTAT) INVPC Illegal unaligned load or store Usage fault Usage Fault Status (UFAULTSTAT) UNALIGN Divide by 0 Usage fault Usage Fault Status (UFAULTSTAT) DIV0 a. Occurs on an access to an XN region even if the MPU is disabled. b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction with ICI continuation. 2.6.2 Fault Escalation and Hard Faults All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on page 133). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on page 136). Usually, the exception priority, together with the values of the exception mask registers, determines whether the processor enters the fault handler, and whether a fault handler can preempt another fault handler as described in “Exception Model” on page 79. In some situations, a fault with configurable priority is treated as a hard fault. This process is called priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault occurs when: ■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because a fault handler cannot preempt itself because it must have the same priority as the current priority level. ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. 88 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled. If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than Reset, NMI, or another hard fault. 2.6.3 Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address register indicates the address accessed by the operation that caused the fault, as shown in Table 2-12 on page 89. Table 2-12. Fault Status and Fault Address Registers Handler Status Register Name Address Register Name Register Description Hard fault Hard Fault Status (HFAULTSTAT) - page 146 page 140 page 147 Memory Management Fault Address (MMADDR) Memory Management Fault Status (MFAULTSTAT) Memory management fault page 140 page 148 Bus Fault Address (FAULTADDR) Bus fault Bus Fault Status (BFAULTSTAT) Usage fault Usage Fault Status (UFAULTSTAT) - page 140 2.6.4 Lockup The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the processor is in the lockup state, it does not execute any instructions. The processor remains in lockup state until it is reset or an NMI occurs. Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the lockup state. 2.7 Power Management The Cortex-M3 processor sleep modes reduce power consumption: ■ Sleep mode stops the processor clock. ■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory. The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used (see page 129). For more information about the behavior of the sleep modes, see “System Control” on page 180. This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. January 08, 2011 89 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 2.7.1 Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor. Therefore, software must be able to put the processor back into sleep mode after such an event. A program might have an idle loop to put the processor back to sleep mode. 2.7.1.1 Wait for Interrupt The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 90). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. 2.7.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit event register. When the processor executes a WFE instruction, it checks the event register. If the register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1, the processor clears the register and continues executing instructions without entering sleep mode. If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction. Typically, this situation occurs if an SEV instruction has been executed. Software cannot access this register directly. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. 2.7.1.3 Sleep-on-Exit If the SLEEPEXIT bit of the SYSCTRL register is set, when the processor completes the execution of an exception handler, it returns to Thread mode and immediately enters sleep mode. This mechanism can be used in applications that only require the processor to run when an exception occurs. 2.7.2 Wake Up from Sleep Mode The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode. 2.7.2.1 Wake Up from WFI or Sleep-on-Exit Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry. Some embedded systems might have to execute system restore tasks after the processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that is enabled and has a higher priority than current exception priority, the processor wakes up but does not execute the interrupt handler until the processor clears PRIMASK. For more information about PRIMASK and FAULTMASK, see page 67 and page 68. 2.7.2.2 Wake Up from WFE The processor wakes up if it detects an exception with sufficient priority to cause exception entry. In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 129. 90 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 91 lists the supported instructions. Note: In Table 2-13 on page 91: ■ Angle brackets, <>, enclose alternative forms of the operand ■ Braces, {}, enclose optional operands ■ The Operands column is not exhaustive ■ Op2 is a flexible second operand that can be either a register or a constant ■ Most instructions can use an optional condition code suffix For more information on the instructions and operands, see the instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual. Table 2-13. Cortex-M3 Instruction Summary Mnemonic Operands Brief Description Flags ADC, ADCS {Rd,} Rn , Op2 Add with carry N,Z,C,V ADD, ADDS {Rd,} Rn , Op2 Add N,Z,C,V ADD, ADDW {Rd,} Rn , #imm12 Add N,Z,C,V ADR Rd , label Load PC-relative address - AND, ANDS {Rd ,} Rn , Op2 Logical AND N,Z,C ASR, ASRS Rd , Rm , Arithmetic shift right N,Z,C B label Branch - BFC Rd , #lsb , #width Bit field clear - BFI Rd , Rn , #lsb , #width Bit field insert - BIC, BICS {Rd ,} Rn , Op2 Bit clear N,Z,C BKPT #imm Breakpoint - BL label Branch with link - BLX Rm Branch indirect with link - BX Rm Branch indirect - CBNZ Rn , label Compare and branch if non-zero - CBZ Rn , label Compare and branch if zero - CLREX - Clear exclusive - CLZ Rd , Rm Count leading zeros - CMN Rn , Op2 Compare negative N,Z,C,V CMP Rn , Op2 Compare N,Z,C,V Change processor state, disable - interrupts CPSID iflags Change processor state, enable - interrupts CPSIE iflags DMB - Data memory barrier - DSB - Data synchronization barrier - EOR, EORS {Rd ,} Rn , Op2 Exclusive OR N,Z,C ISB - Instruction synchronization barrier - IT - If-Then condition block - January 08, 2011 91 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags LDM Rn{!} , reglist Load multiple registers, increment after - Load multiple registers, decrement - before LDMDB, LDMEA Rn{!} , reglist LDMFD, LDMIA Rn{!} , reglist Load multiple registers, increment after - LDR Rt , [ Rn {, #offset}] Load register with word - LDRB, LDRBT Rt , [ Rn {, #offset}] Load register with byte - LDRD Rt , Rt2 , [ Rn {, #offset}] Load register with two words - LDREX Rt , [ Rn , #offset ] Load register exclusive - LDREXB Rt, [Rn] Load register exclusive with byte - LDREXH Rt , [Rn] Load register exclusive with halfword - LDRH, LDRHT Rt , [ Rn{ , #offset}] Load register with halfword - LDRSB, LDRSBT Rt , [ Rn{ , #offset}] Load register with signed byte - LDRSH, LDRSHT Rt , [ Rn {, #offset}] Load register with signed halfword - LDRT Rt , [ Rn {, #offset}] Load register with word - LSL, LSLS Rd , Rm , Logical shift left N,Z,C LSR, LSRS Rd , Rm , Logical shift right N,Z,C MLA Rd , Rn , Rm, Ra Multiply with accumulate, 32-bit result - MLS Rd , Rn , Rm, Ra Multiply and subtract, 32-bit result - MOV, MOVS Rd , Op2 Move N,Z,C MOV, MOVW Rd , #imm16 Move 16-bit constant N,Z,C MOVT Rd , #imm16 Move top - Move from special register to general - register MRS Rd , spec_reg Move from general register to special N,Z,C,V register MSR spec_reg , Rn MUL, MULS {Rd,}Rn , Rm Multiply, 32-bit result N,Z MVN, MVNS Rd , Op2 Move NOT N,Z,C NOP - No operation - ORN, ORNS {Rd,} Rn , Op2 Logical OR NOT N,Z,C ORR, ORRS {Rd,} Rn , Op2 Logical OR N,Z,C POP reglist Pop registers from stack - PUSH reglist Push registers onto stack - RBIT Rd , Rn Reverse bits - REV Rd , Rn Reverse byte order in a word - REV16 Rd , Rn Reverse byte order in each halfword - Reverse byte order in bottom halfword - and sign extend REVSH Rd , Rn ROR, RORS Rd , Rm , Rotate right N,Z,C RRX, RRXS Rd , Rm Rotate right with extend N,Z,C RSB, RSBS {Rd,} Rn , Op2 Reverse subtract N,Z,C,V SBC, SBCS {Rd,} Rn , Op2 Subtract with carry N,Z,C,V SBFX Rd , Rn , #lsb , #width Signed bit field extract - 92 January 08, 2011 Texas Instruments-Production Data The Cortex-M3 Processor Table 2-13. Cortex-M3 Instruction Summary (continued) Mnemonic Operands Brief Description Flags SDIV {Rd ,} Rn , Rm Signed divide - SEV - Send event - Signed multiply with accumulate - (32x32+64), 64-bit result SMLAL RdLo, RdHi, Rn, Rm SMULL RdLo, RdHi, Rn, Rm Signed multiply (32x32), 64-bit result - SSAT Rd, #n, Rm {,shift #s} Signed saturate Q STM Rn{!} , reglist Store multiple registers, increment after - Store multiple registers, decrement - before STMDB, STMEA Rn{!} , reglist STMFD, STMIA Rn{!} , reglist Store multiple registers, increment after - STR Rt , [ Rn {, #offset}] Store register word - STRB, STRBT Rt , [ Rn {, #offset}] Store register byte - STRD Rt , Rt2 , [ Rn {, #offset}] Store register two words - STREX Rd , Rt , [ Rn , #offset ] Store register exclusive - STREXB Rd , Rt , [Rn] Store register exclusive byte - STREXH Rd , Rt , [Rn] Store register exclusive halfword - STRH, STRHT Rt , [ Rn {, #offset}] Store register halfword - STRSB, STRSBT Rt , [ Rn {, #offset}] Store register signed byte - STRSH, STRSHT Rt , [ Rn {, #offset}] Store register signed halfword - STRT Rt , [ Rn {, #offset}] Store register word - SUB, SUBS {Rd,} Rn , Op2 Subtract N,Z,C,V SUB, SUBW {Rd,} Rn , #imm12 Subtract 12-bit constant N,Z,C,V SVC #imm Supervisor call - SXTB {Rd,} Rm {,ROR #n} Sign extend a byte - SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword - TBB [Rn, Rm] Table branch byte - TBH [Rn, Rm, LSL #1] Table branch halfword - TEQ Rn, Op2 Test equivalence N,Z,C TST Rn, Op2 Test N,Z,C UBFX Rd , Rn , #lsb , #width Unsigned bit field extract - UDIV {Rd,} Rn , Rm Unsigned divide - Unsigned multiply with accumulate - (32x32+32+32), 64-bit result UMLAL RdLo, RdHi, Rn, Rm UMULL RdLo, RdHi, Rn, Rm Unsigned multiply (32x 2), 64-bit result - USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q UXTB {Rd,} Rm {,ROR #n} Zero extend a byte - UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword - WFE - Wait for event - WFI - Wait for interrupt - January 08, 2011 93 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 3 Cortex-M3 Peripherals This chapter provides information on the Stellaris® implementation of the Cortex-M3 processor peripherals, including: ■ SysTick (see page 94) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. ■ Nested Vectored Interrupt Controller (NVIC) (see page 95) – Facilitates low-latency exception and interrupt handling – Controls power management – Implements system control registers ■ System Control Block (SCB) (see page 97) Provides system implementation information and system control, including configuration, control, and reporting of system exceptions. ■ Memory Protection Unit (MPU) (see page 97) Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. Table 3-1 on page 94 shows the address map of the Private Peripheral Bus (PPB). Some peripheral register regions are split into two address regions, as indicated by two addresses listed. Table 3-1. Core Peripheral Register Regions Address Core Peripheral Description (see page ...) 0xE000.E010-0xE000.E01F System Timer 94 0xE000.E100-0xE000.E4EF Nested Vectored Interrupt Controller 95 0xE000.EF00-0xE000.EF03 0xE000.ED00-0xE000.ED3F System Control Block 97 0xE000.ED90-0xE000.EDB8 Memory Protection Unit 97 3.1 Functional Description This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals: SysTick, NVIC, SCB and MPU. 3.1.1 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example as: ■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. 94 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNT bit in the STCTRL control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. The timer consists of three registers: ■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the counter's wrap value. ■ SysTick Current Value (STCURRENT): The current value of the counter. When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the value in the STRELOAD register on the next clock edge, then decrements on subsequent clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter reaches zero, the COUNT status bit is set. The COUNT bit clears on reads. Writing to the STCURRENT register clears the register and the COUNT status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick registers. Note: When the processor is halted for debugging, the counter does not decrement. 3.1.2 Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 42 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority. ■ Low-latency exception and interrupt handling. ■ Level and pulse detection of interrupt signals. ■ Dynamic reprioritization of interrupts. ■ Grouping of priority values into group priority and subpriority fields. ■ Interrupt tail-chaining. ■ An external Non-maskable interrupt (NMI). January 08, 2011 95 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt. When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and Software Control of Interrupts” on page 96 for more information). For a level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. As a result, the peripheral can hold the interrupt signal asserted until it no longer needs servicing. 3.1.2.2 Hardware and Software Control of Interrupts The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons: ■ The NVIC detects that the interrupt signal is High and the interrupt is not active. ■ The NVIC detects a rising edge on the interrupt signal. ■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit in the PEND0 register on page 113 or SWTRIG on page 121. A pending interrupt remains pending until one of the following: ■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to active. Then: – For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive. – For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR. If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from the ISR the state of the interrupt changes to inactive. ■ Software writes to the corresponding interrupt clear-pending register bit – For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change. Otherwise, the state of the interrupt changes to inactive. 96 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.4 Memory Protection Unit (MPU) This section describes the Memory protection unit (MPU). The MPU divides the memory map into a number of regions and defines the location, size, access permissions, and memory attributes of each region. The MPU supports independent attribute settings for each region, overlapping regions, and export of memory attributes to the system. The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines eight separate memory regions, 0-7, and a background region. When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have the same region settings. If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management fault, causing a fault exception and possibly causing termination of the process in an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection. Configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” on page 73 for more information). Table 3-2 on page 97 shows the possible MPU region attributes. See the section called “MPU Configuration for a Stellaris Microcontroller” on page 101 for guidelines for programming a microcontroller implementation. Table 3-2. Memory Attributes Summary Memory Type Description Strongly Ordered All accesses to Strongly Ordered memory occur in program order. Device Memory-mapped peripherals Normal Normal memory To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers might access. Ensure software uses aligned accesses of the correct size to access MPU registers: ■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must be accessed with aligned word accesses. ■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses. January 08, 2011 97 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 3.1.4.1 Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can be programmed separately or with a multiple-word write to program all of these registers. You can use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using an STM instruction. Updating an MPU Region Using Separate Words This example simple code configures one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R4, [R0, #0x4] ; Region Base Address STRH R2, [R0, #0x8] ; Region Size and Enable STRH R3, [R0, #0xA] ; Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number BIC R2, R2, #1 ; Disable STRH R2, [R0, #0x8] ; Region Size and Enable STR R4, [R0, #0x4] ; Region Base Address STRH R3, [R0, #0xA] ; Region Attribute ORR R2, #1 ; Enable STRH R2, [R0, #0x8] ; Region Size and Enable Software must use memory barrier instructions: ■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be affected by the change in MPU settings. ■ After MPU setup, if it includes memory transfers that must use the new MPU settings. However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler, or is followed by an exception return, because the exception entry and exception return mechanism cause memory barrier behavior. Software does not need any memory barrier instructions during MPU setup, because it accesses the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region. 98 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then an ISB is not required. Updating an MPU Region Using Multi-Word Writes The MPU can be programmed directly using multi-word writes, depending how the information is divided. Consider the following reprogramming: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STR R1, [R0, #0x0] ; Region Number STR R2, [R0, #0x4] ; Region Base Address STR R3, [R0, #0x8] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = region number ; R2 = address ; R3 = size, attributes in one LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register STM R0, {R1-R3} ; Region number, address, attribute, size and enable This operation can be done in two words for pre-packed information, meaning that the MPU Region Base Address (MPUBASE) register (see page 153) contains the required region number and has the VALID bit set. This method can be used when the data is statically packed, for example in a boot loader: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and region number combined ; with VALID (bit 4) set STR R2, [R0, #0x4] ; Region Attribute, Size and Enable An STM instruction can be used to optimize this: ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0,=MPUBASE ; 0xE000ED9C, MPU Region Base register STM R0, {R1-R2} ; Region base address, region number and VALID bit, ; and Region Attribute, Size and Enable Subregions Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 155) to disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the most-significant bit controls the last subregion. Disabling a subregion means another region January 08, 2011 99 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller overlapping the disabled range matches instead. If no other enabled region overlaps the disabled subregion, the MPU issues a fault. Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be configured to 0x00, otherwise the MPU behavior is unpredictable. Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 100 shows. Figure 3-1. SRD Use Example Region 1 Disabled subregion Disabled subregion Region 2, with subregions Base address of both regions Offset from base address 0 64KB 128KB 192KB 256KB 320KB 384KB 448KB 512KB 3.1.4.2 MPU Access Permission Attributes The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. Table 3-3 on page 100 shows the encodings for the TEX, C, B, and S access permission bits. All encodings are shown for completeness, however the current implementation of the Cortex-M3 does not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration for a Stellaris Microcontroller” on page 101 for information on programming the MPU for Stellaris implementations. Table 3-3. TEX, S, C, and B Bit Field Encoding TEX S C B Memory Type Shareability Other Attributes 000b xa 0 0 Strongly Ordered Shareable - 000 xa 0 1 Device Shareable - Outer and inner write-through. No write allocate. 000 0 1 0 Normal Not shareable 000 1 1 0 Normal Shareable 000 0 1 1 Normal Not shareable 000 1 1 1 Normal Shareable Outer and inner noncacheable. 001 0 0 0 Normal Not shareable 001 1 0 0 Normal Shareable 001 xa 0 1 Reserved encoding - - 001 xa 1 0 Reserved encoding - - Outer and inner write-back. Write and read allocate. 001 0 1 1 Normal Not shareable 001 1 1 1 Normal Shareable 100 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S C B Memory Type Shareability Other Attributes 010 xa 0 0 Device Not shareable Nonshared Device. 010 xa 0 1 Reserved encoding - - 010 xa 1 xa Reserved encoding - - Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable a. The MPU ignores the value of this bit. Table 3-4 on page 101 shows the cache policy for memory attribute encodings with a TEX value in the range of 0x4-0x7. Table 3-4. Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding Cache Policy 00 Non-cacheable 01 Write back, write and read allocate 10 Write through, no write allocate 11 Write back, no write allocate Table 3-5 on page 101 shows the AP encodings in the MPUATTR register that define the access permissions for privileged and unprivileged software. Table 3-5. AP Bit Field Encoding Unprivileged Description Permissions Privileged Permissions AP Bit Field 000 No access No access All accesses generate a permission fault. 001 R/W No access Access from privileged software only. Writes by unprivileged software generate a permission fault. 010 R/W RO 011 R/W R/W Full access. 100 Unpredictable Unpredictable Reserved. 101 RO No access Reads by privileged software only. 110 RO RO Read-only, by privileged or unprivileged software. 111 RO RO Read-only, by privileged or unprivileged software. MPU Configuration for a Stellaris Microcontroller Stellaris microcontrollers have only a single processor and no caches. As a result, the MPU should be programmed as shown in Table 3-6 on page 101. Table 3-6. Memory Region Attributes for Stellaris Microcontrollers Memory Region TEX S C B Memory Type and Attributes Flash memory 000b 0 1 0 Normal memory, non-shareable, write-through Internal SRAM 000b 1 1 0 Normal memory, shareable, write-through January 08, 2011 101 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 3-6. Memory Region Attributes for Stellaris Microcontrollers (continued) Memory Region TEX S C B Memory Type and Attributes Normal memory, shareable, write-back, write-allocate External SRAM 000b 1 1 1 Peripherals 000b 1 0 1 Device memory, shareable In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. 3.1.4.3 MPU Mismatch When an access violates the MPU permissions, the processor generates a memory management fault (see “Exceptions and Interrupts” on page 71 for more information). The MFAULTSTAT register indicates the cause of the fault. See page 140 for more information. 3.2 Register Map Table 3-7 on page 102 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB, and MPU registers. The offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base address of 0xE000.E000. Note: Register spaces that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 3-7. Peripherals Register Map See Offset Name Type Reset Description page System Timer (SysTick) Registers 0x010 STCTRL R/W 0x0000.0000 SysTick Control and Status Register 105 0x014 STRELOAD R/W 0x0000.0000 SysTick Reload Value Register 107 0x018 STCURRENT R/WC 0x0000.0000 SysTick Current Value Register 108 Nested Vectored Interrupt Controller (NVIC) Registers 0x100 EN0 R/W 0x0000.0000 Interrupt 0-31 Set Enable 109 0x104 EN1 R/W 0x0000.0000 Interrupt 32-43 Set Enable 110 0x180 DIS0 R/W 0x0000.0000 Interrupt 0-31 Clear Enable 111 0x184 DIS1 R/W 0x0000.0000 Interrupt 32-43 Clear Enable 112 0x200 PEND0 R/W 0x0000.0000 Interrupt 0-31 Set Pending 113 0x204 PEND1 R/W 0x0000.0000 Interrupt 32-43 Set Pending 114 0x280 UNPEND0 R/W 0x0000.0000 Interrupt 0-31 Clear Pending 115 0x284 UNPEND1 R/W 0x0000.0000 Interrupt 32-43 Clear Pending 116 0x300 ACTIVE0 RO 0x0000.0000 Interrupt 0-31 Active Bit 117 0x304 ACTIVE1 RO 0x0000.0000 Interrupt 32-43 Active Bit 118 0x400 PRI0 R/W 0x0000.0000 Interrupt 0-3 Priority 119 102 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Table 3-7. Peripherals Register Map (continued) See Offset Name Type Reset Description page 0x404 PRI1 R/W 0x0000.0000 Interrupt 4-7 Priority 119 0x408 PRI2 R/W 0x0000.0000 Interrupt 8-11 Priority 119 0x40C PRI3 R/W 0x0000.0000 Interrupt 12-15 Priority 119 0x410 PRI4 R/W 0x0000.0000 Interrupt 16-19 Priority 119 0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 119 0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 119 0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 119 0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 119 0x424 PRI9 R/W 0x0000.0000 Interrupt 36-39 Priority 119 0x428 PRI10 R/W 0x0000.0000 Interrupt 40-43 Priority 119 0xF00 SWTRIG WO 0x0000.0000 Software Trigger Interrupt 121 System Control Block (SCB) Registers 0xD00 CPUID RO 0x411F.C231 CPU ID Base 122 0xD04 INTCTRL R/W 0x0000.0000 Interrupt Control and State 123 0xD08 VTABLE R/W 0x0000.0000 Vector Table Offset 126 0xD0C APINT R/W 0xFA05.0000 Application Interrupt and Reset Control 127 0xD10 SYSCTRL R/W 0x0000.0000 System Control 129 0xD14 CFGCTRL R/W 0x0000.0000 Configuration and Control 131 0xD18 SYSPRI1 R/W 0x0000.0000 System Handler Priority 1 133 0xD1C SYSPRI2 R/W 0x0000.0000 System Handler Priority 2 134 0xD20 SYSPRI3 R/W 0x0000.0000 System Handler Priority 3 135 0xD24 SYSHNDCTRL R/W 0x0000.0000 System Handler Control and State 136 0xD28 FAULTSTAT R/W1C 0x0000.0000 Configurable Fault Status 140 0xD2C HFAULTSTAT R/W1C 0x0000.0000 Hard Fault Status 146 0xD34 MMADDR R/W - Memory Management Fault Address 147 0xD38 FAULTADDR R/W - Bus Fault Address 148 Memory Protection Unit (MPU) Registers 0xD90 MPUTYPE RO 0x0000.0800 MPU Type 149 0xD94 MPUCTRL R/W 0x0000.0000 MPU Control 150 0xD98 MPUNUMBER R/W 0x0000.0000 MPU Region Number 152 0xD9C MPUBASE R/W 0x0000.0000 MPU Region Base Address 153 0xDA0 MPUATTR R/W 0x0000.0000 MPU Region Attribute and Size 155 January 08, 2011 103 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 3-7. Peripherals Register Map (continued) See Offset Name Type Reset Description page 0xDA4 MPUBASE1 R/W 0x0000.0000 MPU Region Base Address Alias 1 153 0xDA8 MPUATTR1 R/W 0x0000.0000 MPU Region Attribute and Size Alias 1 155 0xDAC MPUBASE2 R/W 0x0000.0000 MPU Region Base Address Alias 2 153 0xDB0 MPUATTR2 R/W 0x0000.0000 MPU Region Attribute and Size Alias 2 155 0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 153 0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 155 3.3 System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset. 104 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COUNT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CLK_SRC INTEN ENABLE Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0x000 Count Flag Value Description The SysTick timer has not counted to 0 since the last time this bit was read. 0 The SysTick timer has counted to 0 since the last time this bit was read. 1 This bit is cleared by a read of the register or if the STCURRENT register is written with any value. If read by the debugger using the DAP, this bit is cleared only if the MasterType bit in the AHB-AP Control Register is clear. Otherwise, the COUNT bit is not changed by the debugger read. See the ARM® Debug Interface V5 Architecture Specification for more information on MasterType. 16 COUNT RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:3 reserved RO 0x000 Clock Source Value Description External reference clock. (Not implemented for Stellaris microcontrollers.) 0 1 System clock Because an external reference clock is not implemented, this bit must be set in order for SysTick to operate. 2 CLK_SRC R/W 0 January 08, 2011 105 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Interrupt Enable Value Description Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 0 An interrupt is generated to the NVIC when SysTick counts to 0. 1 1 INTEN R/W 0 Enable Value Description 0 The counter is disabled. Enables SysTick to operate in a multi-shot way. That is, the counter loads the RELOAD value and begins counting down. On reaching 0, the COUNT bit is set and an interrupt is generated if enabled by INTEN. The counter then loads the RELOAD value again and begins counting. 1 0 ENABLE R/W 0 106 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the COUNT bit are activated when counting from 1 to 0. SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD field. SysTick Reload Value Register (STRELOAD) Base 0xE000.E000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved RELOAD Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RELOAD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0x00 Reload Value Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. 23:0 RELOAD R/W 0x00.0000 January 08, 2011 107 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CURRENT Type RO RO RO RO RO RO RO RO R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CURRENT Type R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0x00 Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register. 23:0 CURRENT R/WC 0x00.0000 3.4 NVIC Register Descriptions This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such as interrupts. For more information, see page 126. 108 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Note: This register can only be accessed from privileged mode. The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 82 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 0-31 Set Enable (EN0) Base 0xE000.E000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Interrupt Enable Value Description On a read, indicates the interrupt is disabled. On a write, no effect. 0 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. 1 A bit can only be cleared by setting the corresponding INT[n] bit in the DISn register. 31:0 INT R/W 0x0000.0000 January 08, 2011 109 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 Note: This register can only be accessed from privileged mode. The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. Interrupt 32-43 Set Enable (EN1) Base 0xE000.E000 Offset 0x104 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x0000.0 Interrupt Enable Value Description On a read, indicates the interrupt is disabled. On a write, no effect. 0 On a read, indicates the interrupt is enabled. On a write, enables the interrupt. 1 A bit can only be cleared by setting the corresponding INT[n] bit in the DIS1 register. 11:0 INT R/W 0x000 110 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Note: This register can only be accessed from privileged mode. The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 82 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Interrupt Disable Value Description On a read, indicates the interrupt is disabled. On a write, no effect. 0 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN0 register, disabling interrupt [n]. 1 31:0 INT R/W 0x0000.0000 January 08, 2011 111 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 Note: This register can only be accessed from privileged mode. The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments. Interrupt 32-43 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x0000.0 Interrupt Disable Value Description On a read, indicates the interrupt is disabled. On a write, no effect. 0 On a read, indicates the interrupt is enabled. On a write, clears the corresponding INT[n] bit in the EN1 register, disabling interrupt [n]. 1 11:0 INT R/W 0x000 112 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Note: This register can only be accessed from privileged mode. The PEND0 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 82 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.E000 Offset 0x200 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Interrupt Set Pending Value Description On a read, indicates that the interrupt is not pending. On a write, no effect. 0 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. 1 If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND0 register. 31:0 INT R/W 0x0000.0000 January 08, 2011 113 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 Note: This register can only be accessed from privileged mode. The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments. Interrupt 32-43 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x0000.0 Interrupt Set Pending Value Description On a read, indicates that the interrupt is not pending. On a write, no effect. 0 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to pending even if it is disabled. 1 If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be cleared by setting the corresponding INT[n] bit in the UNPEND1 register. 11:0 INT R/W 0x000 114 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Note: This register can only be accessed from privileged mode. The UNPEND0 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 82 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.E000 Offset 0x280 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Interrupt Clear Pending Value Description On a read, indicates that the interrupt is not pending. On a write, no effect. 0 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 1 31:0 INT R/W 0x0000.0000 January 08, 2011 115 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 Note: This register can only be accessed from privileged mode. The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments. Interrupt 32-43 Clear Pending (UNPEND1) Base 0xE000.E000 Offset 0x284 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x0000.0 Interrupt Clear Pending Value Description On a read, indicates that the interrupt is not pending. On a write, no effect. 0 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in the PEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active state of the corresponding interrupt. 1 11:0 INT R/W 0x000 116 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Note: This register can only be accessed from privileged mode. The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 82 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.E000 Offset 0x300 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 31:0 INT RO 0x0000.0000 January 08, 2011 117 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 82 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 32-43 Active Bit (ACTIVE1) Base 0xE000.E000 Offset 0x304 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0x0000.0 Interrupt Active Value Description 0 The corresponding interrupt is not active. 1 The corresponding interrupt is active, or active and pending. 11:0 INT RO 0x000 118 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 Note: This register can only be accessed from privileged mode. The PRIn registers provide 3-bit priority fields for each interrupt. These registers are byte accessible. Each register holds four priority fields that are assigned to interrupts as follows: PRIn Register Bit Field Interrupt Bits 31:29 Interrupt [4n+3] Bits 23:21 Interrupt [4n+2] Bits 15:13 Interrupt [4n+1] Bits 7:5 Interrupt [4n] See Table 2-9 on page 82 for interrupt assignments. Each priority level can be split into separate group priority and subpriority fields. The PRIGROUP field in the Application Interrupt and Reset Control (APINT) register (see page 127) indicates the position of the binary point that splits the priority and subpriority fields . These registers can only be accessed from privileged mode. Interrupt 0-3 Priority (PRI0) Base 0xE000.E000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTD reserved INTC reserved Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTB reserved INTA reserved Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 January 08, 2011 119 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 31:29 INTD R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28:24 reserved RO 0x0 Interrupt Priority for Interrupt [4n+2] This field holds a priority value, 0-7, for the interrupt with the number [4n+2], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 23:21 INTC R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20:16 reserved RO 0x0 Interrupt Priority for Interrupt [4n+1] This field holds a priority value, 0-7, for the interrupt with the number [4n+1], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 15:13 INTB R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:8 reserved RO 0x0 Interrupt Priority for Interrupt [4n] This field holds a priority value, 0-7, for the interrupt with the number [4n], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 7:5 INTA R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 reserved RO 0x0 120 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 82 for interrupt assignments. When the MAINPEND bit in the Configuration and Control (CFGCTRL) register (see page 131) is set, unprivileged software can access the SWTRIG register. Software Trigger Interrupt (SWTRIG) Base 0xE000.E000 Offset 0xF00 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INTID Type RO RO RO RO RO RO RO RO RO RO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x0000.00 Interrupt ID This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3. 5:0 INTID WO 0x00 3.5 System Control Block (SCB) Register Descriptions This section lists and describes the System Control Block (SCB) registers, in numerical order by address offset. The SCB registers can only be accessed from privileged mode. All registers must be accessed with aligned word accesses except for the FAULTSTAT and SYSPRI1-SYSPRI3 registers, which can be accessed with byte or aligned halfword or word accesses. The processor does not support unaligned accesses to system control block registers. January 08, 2011 121 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 26: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x411F.C231 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IMP VAR CON Type R0 R0 R0 R0 R0 R0 R0 R0 RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PARTNO REV Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 0 0 0 0 1 0 0 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Implementer Code Value Description 0x41 ARM 31:24 IMP R0 0x41 Variant Number Value Description The rn value in the rnpn product revision identifier, for example, the 1 in r1p1. 0x1 23:20 VAR RO 0x1 Constant Value Description 0xF Always reads as 0xF. 19:16 CON RO 0xF Part Number Value Description 0xC23 Cortex-M3 processor. 15:4 PARTNO RO 0xC23 Revision Number Value Description The pn value in the rnpn product revision identifier, for example, the 1 in r1p1. 0x1 3:0 REV RO 0x1 122 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions. In addition, bits in this register indicate the exception number of the exception being processed, whether there are preempted active exceptions, the exception number of the highest priority pending exception, and whether any interrupts are pending. When writing to INCTRL, the effect is unpredictable when writing a 1 to both the PENDSV and UNPENDSV bits, or writing a 1 to both the PENDSTSET and PENDSTCLR bits. Interrupt Control and State (INTCTRL) Base 0xE000.E000 Offset 0xD04 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NMISET reserved PENDSV UNPENDSV PENDSTSET PENDSTCLR reserved ISRPRE ISRPEND reserved VECPEND Type R/W RO RO R/W WO R/W WO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VECPEND RETBASE reserved VECACT Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description NMI Set Pending Value Description On a read, indicates an NMI exception is not pending. On a write, no effect. 0 On a read, indicates an NMI exception is pending. On a write, changes the NMI exception state to pending. 1 Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. 31 NMISET R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30:29 reserved RO 0x0 PendSV Set Pending Value Description On a read, indicates a PendSV exception is not pending. On a write, no effect. 0 On a read, indicates a PendSV exception is pending. On a write, changes the PendSV exception state to pending. 1 Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit. 28 PENDSV R/W 0 January 08, 2011 123 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description PendSV Clear Pending Value Description 0 On a write, no effect. On a write, removes the pending state from the PendSV exception. 1 This bit is write only; on a register read, its value is unknown. 27 UNPENDSV WO 0 SysTick Set Pending Value Description On a read, indicates a SysTick exception is not pending. On a write, no effect. 0 On a read, indicates a SysTick exception is pending. On a write, changes the SysTick exception state to pending. 1 This bit is cleared by writing a 1 to the PENDSTCLR bit. 26 PENDSTSET R/W 0 SysTick Clear Pending Value Description 0 On a write, no effect. On a write, removes the pending state from the SysTick exception. 1 This bit is write only; on a register read, its value is unknown. 25 PENDSTCLR WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 24 reserved RO 0 Debug Interrupt Handling Value Description 0 The release from halt does not take an interrupt. 1 The release from halt takes an interrupt. This bit is only meaningful in Debug mode and reads as zero when the processor is not in Debug mode. 23 ISRPRE RO 0 Interrupt Pending Value Description 0 No interrupt is pending. 1 An interrupt is pending. This bit provides status for all interrupts excluding NMI and Faults. 22 ISRPEND RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21:18 reserved RO 0x0 124 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register. Value Description 0x00 No exceptions are pending 0x01 Reserved 0x02 NMI 0x03 Hard fault 0x04 Memory management fault 0x05 Bus fault 0x06 Usage fault 0x07-0x0A Reserved 0x0B SVCall 0x0C Reserved for Debug 0x0D Reserved 0x0E PendSV 0x0F SysTick 0x10 Interrupt Vector 0 0x11 Interrupt Vector 1 ... ... 0x3B Interrupt Vector 43 0x3C-0x3F Reserved 17:12 VECPEND RO 0x00 Return to Base Value Description 0 There are preempted active exceptions to execute. There are no active exceptions, or the currently executing exception is the only active exception. 1 This bit provides status for all interrupts excluding NMI and Faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero). 11 RETBASE RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:6 reserved RO 0x0 Interrupt Pending Vector Number This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode. This field contains the same value as the ISRNUM field in the IPSR register. Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers (see page 63). 5:0 VECACT RO 0x00 January 08, 2011 125 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 28: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved BASE OFFSET Type RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET reserved Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:30 reserved RO 0x0 Vector Table Base Value Description 0 The vector table is in the code memory region. 1 The vector table is in the SRAM memory region. 29 BASE R/W 0 Vector Table Offset When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 43 interrupts, the minimum alignment is 64 words. 28:8 OFFSET R/W 0x000.00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 0x00 126 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored. The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table 3-8 on page 127 shows how the PRIGROUP value controls this split. The bit numbers in the Group Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29. Note: Determining preemption of an exception uses only the group priority field. Table 3-8. Interrupt Priority Levels Group Subpriorities Priorities PRIGROUP Bit Field Binary Pointa Group Priority Field Subpriority Field 0x0 - 0x4 bxxx. [7:5] None 8 1 0x5 bxx.y [7:6] [5] 4 2 0x6 bx.yy [7] [6:5] 2 4 0x7 b.yyy None [7:5] 1 8 a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit. Application Interrupt and Reset Control (APINT) Base 0xE000.E000 Offset 0xD0C Type R/W, reset 0xFA05.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VECTKEY Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ENDIANESS reserved PRIGROUP reserved SYSRESREQVECTCLRACT VECTRESET Type RO RO RO RO RO R/W R/W R/W RO RO RO RO RO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Register Key This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned. 31:16 VECTKEY R/W 0xFA05 Data Endianess The Stellaris implementation uses only little-endian mode so this is cleared to 0. 15 ENDIANESS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14:11 reserved RO 0x0 January 08, 2011 127 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 127 for more information). 10:8 PRIGROUP R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:3 reserved RO 0x0 System Reset Request Value Description 0 No effect. Resets the core and all on-chip peripherals except the Debug interface. 1 This bit is automatically cleared during the reset of the core and reads as 0. 2 SYSRESREQ WO 0 Clear Active NMI / Fault This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 1 VECTCLRACT WO 0 System Reset This bit is reserved for Debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable. 0 VECTRESET WO 0 128 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 30: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SEVONPEND reserved SLEEPDEEP SLEEPEXIT reserved Type RO RO RO RO RO RO RO RO RO RO RO R/W RO R/W R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0x0000.00 Wake Up on Pending Value Description Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded. 0 Enabled events and all interrupts, including disabled interrupts, can wake up the processor. 1 When an event or interrupt enters the pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of a SEV instruction or an external event. 4 SEVONPEND R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 Deep Sleep Enable Value Description 0 Use Sleep mode as the low power mode. 1 Use Deep-sleep mode as the low power mode. 2 SLEEPDEEP R/W 0 January 08, 2011 129 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Sleep on ISR Exit Value Description When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 0 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. 1 Setting this bit enables an interrupt-driven application to avoid returning to an empty main application. 1 SLEEPEXIT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 130 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 31: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 121). Configuration and Control (CFGCTRL) Base 0xE000.E000 Offset 0xD14 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved STKALIGN BFHFNMIGN reserved DIV0 UNALIGNED reserved MAINPEND BASETHR Type RO RO RO RO RO RO R/W R/W RO RO RO R/W R/W RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0x0000.00 Stack Alignment on Exception Entry Value Description 0 The stack is 4-byte aligned. 1 The stack is 8-byte aligned. On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment. 9 STKALIGN R/W 0 Ignore Bus Fault in NMI and Fault This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK escalated handlers. Value Description Data bus faults caused by load and store instructions cause a lock-up. 0 Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. 1 Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them. 8 BFHFNMIGN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 reserved RO 0x0 January 08, 2011 131 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description Do not trap on divide by 0. A divide by zero returns a quotient of 0. 0 1 Trap on divide by 0. 4 DIV0 R/W 0 Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses. Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault. 1 Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set. 3 UNALIGNED R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0 Allow Main Interrupt Trigger Value Description 0 Disables unprivileged software access to the SWTRIG register. Enables unprivileged software access to the SWTRIG register (see page 121). 1 1 MAINPEND R/W 0 Thread State Control Value Description The processor can enter Thread mode only when no exception is active. 0 The processor can enter Thread mode from any level under the control of an EXC_RETURN value (see “Exception Return” on page 87 for more information). 1 0 BASETHR R/W 0 132 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved USAGE reserved Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS reserved MEM reserved Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0x00 Usage Fault Priority This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 23:21 USAGE R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20:16 reserved RO 0x0 Bus Fault Priority This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 15:13 BUS R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:8 reserved RO 0x0 Memory Management Fault Priority This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority. 7:5 MEM R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 reserved RO 0x0 January 08, 2011 133 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SVC reserved Type R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description SVCall Priority This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority. 31:29 SVC R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28:0 reserved RO 0x000.0000 134 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TICK reserved PENDSV reserved Type R/W R/W R/W RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DEBUG reserved Type RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description SysTick Exception Priority This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority. 31:29 TICK R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28:24 reserved RO 0x0 PendSV Priority This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority. 23:21 PENDSV R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20:8 reserved RO 0x000 Debug Priority This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority. 7:5 DEBUG R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4:0 reserved RO 0x0.0000 January 08, 2011 135 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers. If a system handler is disabled and the corresponding fault occurs, the processor treats the fault as a hard fault. This register can be modified to change the pending or active status of system exceptions. An OS kernel can write to the active bits to perform a context switch that changes the current exception type. Caution – Software that changes the value of an active bit in this register without correct adjustment to the stacked content can cause the processor to generate a fault exception. Ensure software that writes to this register retains and subsequently restores the current active status. If the value of a bit in this register must be modified after enabling the system handlers, a read-modify-write procedure must be used to ensure that only the required bit is modified. System Handler Control and State (SYSHNDCTRL) Base 0xE000.E000 Offset 0xD24 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved USAGE BUS MEM Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SVC BUSP MEMP USAGEP TICK PNDSV reserved MON SVCA reserved USGA reserved BUSA MEMA Type R/W R/W R/W R/W R/W R/W RO R/W R/W RO RO RO R/W RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:19 reserved RO 0x000 Usage Fault Enable Value Description 0 Disables the usage fault exception. 1 Enables the usage fault exception. 18 USAGE R/W 0 Bus Fault Enable Value Description 0 Disables the bus fault exception. 1 Enables the bus fault exception. 17 BUS R/W 0 136 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Memory Management Fault Enable Value Description 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. 16 MEM R/W 0 SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception. 15 SVC R/W 0 Bus Fault Pending Value Description 0 A bus fault exception is not pending. 1 A bus fault exception is pending. This bit can be modified to change the pending status of the bus fault exception. 14 BUSP R/W 0 Memory Management Fault Pending Value Description 0 A memory management fault exception is not pending. 1 A memory management fault exception is pending. This bit can be modified to change the pending status of the memory management fault exception. 13 MEMP R/W 0 Usage Fault Pending Value Description 0 A usage fault exception is not pending. 1 A usage fault exception is pending. This bit can be modified to change the pending status of the usage fault exception. 12 USAGEP R/W 0 SysTick Exception Active Value Description 0 A SysTick exception is not active. 1 A SysTick exception is active. This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit. 11 TICK R/W 0 January 08, 2011 137 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 10 PNDSV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9 reserved RO 0 Debug Monitor Active Value Description 0 The Debug monitor is not active. 1 The Debug monitor is active. 8 MON R/W 0 SVC Call Active Value Description 0 SVC call is not active. 1 SVC call is active. This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit. 7 SVCA R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:4 reserved RO 0x0 Usage Fault Active Value Description 0 Usage fault is not active. 1 Usage fault is active. This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit. 3 USGA R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0 Bus Fault Active Value Description 0 Bus fault is not active. 1 Bus fault is active. This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit. 1 BUSA R/W 0 138 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit. 0 MEMA R/W 0 January 08, 2011 139 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault. Each of these functions is assigned to a subregister as follows: ■ Usage Fault Status (UFAULTSTAT), bits 31:16 ■ Bus Fault Status (BFAULTSTAT), bits 15:8 ■ Memory Management Fault Status (MFAULTSTAT), bits 7:0 FAULTSTAT is byte accessible. FAULTSTAT or its subregisters can be accessed as follows: ■ The complete FAULTSTAT register, with a word access to offset 0xD28 ■ The MFAULTSTAT, with a byte access to offset 0xD28 ■ The MFAULTSTAT and BFAULTSTAT, with a halfword access to offset 0xD28 ■ The BFAULTSTAT, with a byte access to offset 0xD29 ■ The UFAULTSTAT, with a halfword access to offset 0xD2A Bits are cleared by writing a 1 to them. In a fault handler, the true faulting address can be determined by: 1. Read and save the Memory Management Fault Address (MMADDR) or Bus Fault Address (FAULTADDR) value. 2. Read the MMARV bit in MFAULTSTAT, or the BFARV bit in BFAULTSTAT to determine if the MMADDR or FAULTADDR contents are valid. Software must follow this sequence because another higher priority exception might change the MMADDR or FAULTADDR value. For example, if a higher priority handler preempts the current fault handler, the other fault might change the MMADDR or FAULTADDR value. Configurable Fault Status (FAULTSTAT) Base 0xE000.E000 Offset 0xD28 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DIV0 UNALIGN reserved NOCP INVPC INVSTAT UNDEF Type RO RO RO RO RO RO R/W1C R/W1C RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BFARV reserved BSTKE BUSTKE IMPRE PRECISE IBUS MMARV reserved MSTKE MUSTKE reserved DERR IERR Type R/W1C RO RO R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C RO RO R/W1C R/W1C RO R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:26 reserved RO 0x00 140 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Divide-by-Zero Usage Fault Value Description No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 0 The processor has executed an SDIV or UDIV instruction with a divisor of 0. 1 When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register (see page 131). This bit is cleared by writing a 1 to it. 25 DIV0 R/W1C 0 Unaligned Access Usage Fault Value Description No unaligned access fault has occurred, or unaligned access trapping is not enabled. 0 1 The processor has made an unaligned memory access. Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register (see page 131). This bit is cleared by writing a 1 to it. 24 UNALIGN R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0x00 No Coprocessor Usage Fault Value Description A usage fault has not been caused by attempting to access a coprocessor. 0 1 The processor has attempted to access a coprocessor. This bit is cleared by writing a 1 to it. 19 NOCP R/W1C 0 Invalid PC Load Usage Fault Value Description A usage fault has not been caused by attempting to load an invalid PC value. 0 The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value. 1 When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it. 18 INVPC R/W1C 0 January 08, 2011 141 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. The processor has attempted to execute an instruction that makes illegal use of the EPSR register. 1 When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it. 17 INVSTAT R/W1C 0 Undefined Instruction Usage Fault Value Description 0 A usage fault has not been caused by an undefined instruction. The processor has attempted to execute an undefined instruction. 1 When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it. 16 UNDEF R/W1C 0 Bus Fault Address Register Valid Value Description The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address. 0 1 The FAULTADDR register is holding a valid fault address. This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 15 BFARV R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14:13 reserved RO 0 Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. Stacking for an exception entry has caused one or more bus faults. 1 When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 12 BSTKE R/W1C 0 142 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Unstack Bus Fault Value Description No bus fault has occurred on unstacking for a return from exception. 0 Unstacking for a return from exception has caused one or more bus faults. 1 This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 11 BUSTKE R/W1C 0 Imprecise Data Bus Error Value Description 0 An imprecise data bus error has not occurred. A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. 1 When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it. 10 IMPRE R/W1C 0 Precise Data Bus Error Value Description 0 A precise data bus error has not occurred. A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. 1 When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 9 PRECISE R/W1C 0 Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it. 8 IBUS R/W1C 0 January 08, 2011 143 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Memory Management Fault Address Register Valid Value Description The value in the Memory Management Fault Address (MMADDR) register is not a valid fault address. 0 1 The MMADDR register is holding a valid fault address. If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten. This bit is cleared by writing a 1 to it. 7 MMARV R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:5 reserved RO 0 Stack Access Violation Value Description No memory management fault has occurred on stacking for exception entry. 0 Stacking for an exception entry has caused one or more access violations. 1 When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 4 MSTKE R/W1C 0 Unstack Access Violation Value Description No memory management fault has occurred on unstacking for a return from exception. 0 Unstacking for a return from exception has caused one or more access violations. 1 This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 3 MUSTKE R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2 reserved RO 0 144 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Data Access Violation Value Description 0 A data access violation has not occurred. The processor attempted a load or store at a location that does not permit the operation. 1 When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it. 1 DERR R/W1C 0 Instruction Access Violation Value Description 0 An instruction access violation has not occurred. The processor attempted an instruction fetch from a location that does not permit execution. 1 This fault occurs on any access to an XN region, even when the MPU is disabled or not present. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it. 0 IERR R/W1C 0 January 08, 2011 145 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG FORCED reserved Type R/W1C R/W1C RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VECT reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Debug Event This bit is reserved for Debug use. This bit must be written as a 0, otherwise behavior is unpredictable. 31 DBG R/W1C 0 Forced Hard Fault Value Description 0 No forced hard fault has occurred. A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled. 1 When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it. 30 FORCED R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29:2 reserved RO 0x00 Vector Table Read Fault Value Description 0 No bus fault has occurred on a vector table read. 1 A bus fault occurred on a vector table read. This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it. 1 VECT R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 146 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted. Because a single read or write instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the requested access size. Bits in the Memory Management Fault Status (MFAULTSTAT) register indicate the cause of the fault and whether the value in the MMADDR register is valid (see page 140). Memory Management Fault Address (MMADDR) Base 0xE000.E000 Offset 0xD34 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Fault Address When the MMARV bit of MFAULTSTAT is set, this field holds the address of the location that generated the memory management fault. 31:0 ADDR R/W - January 08, 2011 147 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault. Bits in the Bus Fault Status (BFAULTSTAT) register indicate the cause of the fault and whether the value in the FAULTADDR register is valid (see page 140). Bus Fault Address (FAULTADDR) Base 0xE000.E000 Offset 0xD38 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Fault Address When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault. 31:0 ADDR R/W - 3.6 Memory Protection Unit (MPU) Register Descriptions This section lists and describes the Memory Protection Unit (MPU) registers, in numerical order by address offset. The MPU registers can only be accessed from privileged mode. 148 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 40: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.0800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved IREGION Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DREGION reserved SEPARATE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0x00 Number of I Regions This field indicates the number of supported MPU instruction regions. This field always contains 0x00. The MPU memory map is unified and is described by the DREGION field. 23:16 IREGION RO 0x00 Number of D Regions Value Description 0x08 Indicates there are eight supported MPU data regions. 15:8 DREGION RO 0x08 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:1 reserved RO 0x00 Separate or Unified MPU Value Description 0 Indicates the MPU is unified. 0 SEPARATE RO 0 January 08, 2011 149 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 41: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers. When the ENABLE and PRIVDEFEN bits are both set: ■ For privileged accesses, the default memory map is as described in “Memory Model” on page 71. Any access by privileged software that does not address an enabled memory region behaves as defined by the default memory map. ■ Any access by unprivileged software that does not address an enabled memory region causes a memory management fault. Execute Never (XN) and Strongly Ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit. When the ENABLE bit is set, at least one region of the memory map must be enabled for the system to function unless the PRIVDEFEN bit is set. If the PRIVDEFEN bit is set and no regions are enabled, then only privileged software can operate. When the ENABLE bit is clear, the system uses the default memory map, which has the same memory attributes as if the MPU is not implemented (see Table 2-5 on page 74 for more information). The default memory map applies to accesses from both privileged and unprivileged software. When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are accessible based on regions and whether PRIVDEFEN is set. Unless HFNMIENA is set, the MPU is not enabled when the processor is executing the handler for an exception with priority –1 or –2. These priorities are only possible when handling a hard fault or NMI exception or when FAULTMASK is enabled. Setting the HFNMIENA bit enables the MPU when operating with these two priorities. MPU Control (MPUCTRL) Base 0xE000.E000 Offset 0xD94 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIVDEFEN HFNMIENA ENABLE Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x0000.000 150 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 0 If the MPU is enabled, this bit enables use of the default memory map as a background region for privileged software accesses. 1 When this bit is set, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. If the MPU is disabled, the processor ignores this bit. 2 PRIVDEFEN R/W 0 MPU Enabled During Faults This bit controls the operation of the MPU during hard fault, NMI, and FAULTMASK handlers. Value Description The MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit. 0 The MPU is enabled during hard fault, NMI, and FAULTMASK handlers. 1 When the MPU is disabled and this bit is set, the resulting behavior is unpredictable. 1 HFNMIENA R/W 0 MPU Enable Value Description 0 The MPU is disabled. 1 The MPU is enabled. When the MPU is disabled and the HFNMIENA bit is set, the resulting behavior is unpredictable. 0 ENABLE R/W 0 January 08, 2011 151 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register. However, the region number can be changed by writing to the MPUBASE register with the VALID bit set (see page 153). This write updates the value of the REGION field. MPU Region Number (MPUNUMBER) Base 0xE000.E000 Offset 0xD98 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved NUMBER Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x0000.000 MPU Region to Access This field indicates the MPU region referenced by the MPUBASE and MPUATTR registers. The MPU supports eight memory regions. 2:0 NUMBER R/W 0x0 152 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode. The MPUBASE register defines the base address of the MPU region selected by the MPU Region Number (MPUNUMBER) register and can update the value of the MPUNUMBER register. To change the current region number and update the MPUNUMBER register, write the MPUBASE register with the VALID bit set. The ADDR field is bits 31:N of the MPUBASE register. Bits (N-1):5 are reserved. The region size, as specified by the SIZE field in the MPU Region Attribute and Size (MPUATTR) register, defines the value of N where: N = Log2(Region size in bytes) If the region size is configured to 4 GB in the MPUATTR register, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x0000.0000. The base address is aligned to the size of the region. For example, a 64-KB region must be aligned on a multiple of 64 KB, for example, at 0x0001.0000 or 0x0002.0000. MPU Region Base Address (MPUBASE) Base 0xE000.E000 Offset 0xD9C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR VALID reserved REGION Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Base Address Mask Bits 31:N in this field contain the region base address. The value of N depends on the region size, as shown above. The remaining bits (N-1):5 are reserved. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 ADDR R/W 0x0000.000 January 08, 2011 153 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Region Number Valid Value Description The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 0 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field. 1 This bit is always read as 0. 4 VALID WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 Region Number On a write, contains the value to be written to the MPUNUMBER register. On a read, returns the current region number in the MPUNUMBER register. 2:0 REGION R/W 0x0 154 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode. The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions. The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits. The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault. The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 3-9 on page 155 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register. Table 3-9. Example SIZE Field Values SIZE Encoding Region Size Value of Na Note 00100b (0x4) 32 B 5 Minimum permitted size 01001b (0x9) 1 KB 10 - 10011b (0x13) 1 MB 20 - 11101b (0x1D) 1 GB 30 - No valid ADDR field inMPUBASE; the Maximum possible size region occupies the complete memory map. 11111b (0x1F) 4 GB a. Refers to the N parameter in the MPUBASE register (see page 153). MPU Region Attribute and Size (MPUATTR) Base 0xE000.E000 Offset 0xDA0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved XN reserved AP reserved TEX S C B Type RO RO RO R/W RO R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRD reserved SIZE ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 January 08, 2011 155 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:29 reserved RO 0x00 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled. 28 XN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27 reserved RO 0 Access Privilege For information on using this bit field, see Table 3-5 on page 101. 26:24 AP R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:22 reserved RO 0x0 Type Extension Mask For information on using this bit field, see Table 3-3 on page 100. 21:19 TEX R/W 0x0 Shareable For information on using this bit, see Table 3-3 on page 100. 18 S R/W 0 Cacheable For information on using this bit, see Table 3-3 on page 100. 17 C R/W 0 Bufferable For information on using this bit, see Table 3-3 on page 100. 16 B R/W 0 Subregion Disable Bits Value Description 0 The corresponding subregion is enabled. 1 The corresponding subregion is disabled. Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See the section called “Subregions” on page 99 for more information. 15:8 SRD R/W 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0x0 Region Size Mask The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 3-9 on page 155 for more information. 5:1 SIZE R/W 0x0 156 January 08, 2011 Texas Instruments-Production Data Cortex-M3 Peripherals Bit/Field Name Type Reset Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled. 0 ENABLE R/W 0 January 08, 2011 157 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Stellaris® JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs. The multiplexer is controlled by the Stellaris JTAG controller, which has comprehensive programming for the ARM, Stellaris, and unimplemented JTAG instructions. The Stellaris JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST ■ ARM additional instructions: APACC, DPACC and ABORT ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Debug Interface V5 Architecture Specification for more information on the ARM JTAG controller. 158 January 08, 2011 Texas Instruments-Production Data JTAG Interface 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram Instruction Register (IR) TAP Controller BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TCK TMS TDI TDO Cortex-M3 Debug Port TRST 4.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 4-1 on page 159. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 4-2 on page 165 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 684 for JTAG timing diagrams. 4.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 4-1 on page 160. Detailed information on each pin follows. January 08, 2011 159 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 4-1. JTAG Port Pins Reset State Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TRST Input Enabled Disabled N/A N/A TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z 4.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 4.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 4.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 4-2 on page 162. By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 160 January 08, 2011 Texas Instruments-Production Data JTAG Interface 4.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 4.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 4.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 4-2 on page 162. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. January 08, 2011 161 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 4-2. Test Access Port State Machine Test Logic Reset Run Test Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit 1 DR Exit 1 IR Exit 2 DR Exit 2 IR Pause DR Pause IR Update DR Update IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 165. 4.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 162 January 08, 2011 Texas Instruments-Production Data JTAG Interface 4.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 299) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 309) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 310) have been set to 1. Recovering a "Locked" Device Note: The mass erase of the flash memory caused by the below sequence erases the entire flash memory, regardless of the settings in the Flash Memory Protection Program Enable n (FMPPEn) registers. Performing the sequence below does not affect the nonvolatile registers discussed in “Nonvolatile Register Programming” on page 259. If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. January 08, 2011 163 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 11. Perform the SWD-to-JTAG switch sequence. 12. Release the RST signal. 13. Wait 400 ms. 14. Power-cycle the device. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 164. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence in the section called “JTAG-to-SWD Switching” on page 164 must be performed. 4.2.4.2 Communication with JTAG/SWD Because the debug clock and the system clock can be running at different frequencies, care must be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state, the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software should check the ACK response to see if the previous operation has completed before initiating a new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock (TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have to be checked. 4.2.4.3 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Debug Interface V5 Architecture Specification. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send the switching preamble to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 164 January 08, 2011 Texas Instruments-Production Data JTAG Interface 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011100111100, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 4.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. In addition to enabling the alternate functions, any other changes to the GPIO pad configurations on the five JTAG pins (PB7 andPC[3:0]) should be reverted to their default settings. 4.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 4.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 4-2 on page 165. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 4-2. JTAG Instruction Register Commands IR[3:0] Instruction Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0001 INTEST January 08, 2011 165 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 4-2. JTAG Instruction Register Commands (continued) IR[3:0] Instruction Description Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 0010 SAMPLE / PRELOAD 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1110 IDCODE 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. All Others Reserved 4.4.1.1 EXTEST Instruction The EXTEST instruction is not associated with its own Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows tests to be developed that drive known values out of the controller, which can be used to verify connectivity. While the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.4.1.2 INTEST Instruction The INTEST instruction is not associated with its own Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. While the INTEXT instruction is present in the Instruction Register, the Boundary Scan Data Register can be accessed to sample and shift out the current data and load new data into the Boundary Scan Data Register. 4.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with 166 January 08, 2011 Texas Instruments-Production Data JTAG Interface each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 168 for more information. 4.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 169 for more information. 4.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 169 for more information. 4.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 169 for more information. 4.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a Power-On-Reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 168 for more information. 4.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 168 for more information. 4.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. January 08, 2011 167 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 4.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3 on page 168. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA0.0477. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 4-3. IDCODE Register Format Version Part Number Manufacturer ID 1 31 28 27 12 11 1 0 TDI TDO 4.4.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-4 on page 168. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. Figure 4-4. BYPASS Register Format TDI 0 TDO 0 4.4.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 4-5 on page 169. Each GPIO pin, starting with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. 168 January 08, 2011 Texas Instruments-Production Data JTAG Interface Figure 4-5. Boundary Scan Register Format O TDO TDI O IN E UT O O IN U E T O O IN E UT O O IN U E T I N ... ... GPIO PB6 GPIO m RST GPIO m+1 GPIO n 4.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. 4.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Debug Interface V5 Architecture Specification. January 08, 2011 169 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 5 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 5.1 Functional Description The System Control module provides the following capabilities: ■ Device identification (see “Device Identification” on page 170) ■ Local control, such as reset (see “Reset Control” on page 170), power (see “Power Control” on page 174) and clock control (see “Clock Control” on page 175) ■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 180 5.1.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 5.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 5.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 5.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion; see “External RST Pin” on page 171. 2. Power-on reset (POR); see “Power-On Reset (POR)” on page 171. 3. Internal brown-out (BOR) detector; see “Brown-Out Reset (BOR)” on page 173. 4. Software-initiated reset (with the software reset registers); see “Software Reset” on page 173. 5. A watchdog timer reset condition violation; see “Watchdog Timer Reset” on page 174. Table 5-1 provides a summary of results of the various reset operations. Table 5-1. Reset Sources Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset? Power-On Reset Yes Yes Yes RST Yes Pin Config Only Yes Brown-Out Reset Yes No Yes 170 January 08, 2011 Texas Instruments-Production Data System Control Table 5-1. Reset Sources (continued) Reset Source Core Reset? JTAG Reset? On-Chip Peripherals Reset? Software System Request Yes No Yes Reseta Software Peripheral Reset No No Yesb Watchdog Reset Yes No Yes a. By using the SYSRESREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control (APINT) register b. Programmable on a module-by-module basis using the Software Reset Control Registers. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 5.1.2.3 Power-On Reset (POR) Note: The power-on reset also resets the JTAG controller. An external reset does not. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH). The microcontroller must be operating within the specified operating parameters when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller must reach 3.0 V within 10 msec of VDD crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset signal to hold the microcontroller in reset longer than the internal POR, the RST input may be used as discussed in “External RST Pin” on page 171. The Power-On Reset sequence is as follows: 1. The microcontroller waits for internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset timing is shown in Figure 22-6 on page 686. 5.1.2.4 External RST Pin Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be sure to place any components connected to the RST signal as close to the microcontroller as possible. If the application only uses the internal POR circuit, the RST input must be connected to the power supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 5-1 on page 172. January 08, 2011 171 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 5-1. Basic RST Configuration PU RST Stellaris® R VDD RPU = 0 to 100 kΩ The external reset pin (RST) resets the microcontroller including the core and all the on-chip peripherals except the JTAG TAP controller (see “JTAG Interface” on page 158). The external reset sequence is as follows: 1. The external reset pin (RST) is asserted for the duration specified by TMIN and then de-asserted (see “Reset” on page 685). 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 172. Figure 5-2. External Circuitry to Extend Power-On Reset PU C1 RST Stellaris® R VDD RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 μF If the application requires the use of an external reset switch, Figure 5-3 on page 173 shows the proper circuitry to use. 172 January 08, 2011 Texas Instruments-Production Data System Control Figure 5-3. Reset Circuit Controlled by Switch PU C1 RS RST Stellaris® R VDD Typical RPU = 10 kΩ Typical RS = 470 Ω C1 = 10 nF The RPU and C1 components define the power-on delay. The external reset timing is shown in Figure 22-5 on page 686. 5.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivalent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 22-7 on page 686. 5.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 180). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: January 08, 2011 173 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 22-8 on page 687. 5.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The watchdog reset timing is shown in Figure 22-9 on page 687. 5.1.3 Power Control The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Figure 5-4 on page 175 shows the power architecture. Note: On the printed circuit board, use the LDO output as the source of VDD25 input. Do not use an external regulator to supply the voltage to VDD25. In addition, the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator Characteristics” on page 680. VDDA must be supplied with 3.3 V, or the microcontroller does not function properly. VDDA is the supply for all of the analog circuitry on the device, including the LDO and the clock circuitry. 174 January 08, 2011 Texas Instruments-Production Data System Control Figure 5-4. Power Architecture I/O Buffers Analog circuits Low-noise LDO Internal Logic and PLL GND GND GND GND GNDA GND GND GND GND VDD VDD VDD VDD VDDA VDDA VDD25 VDD25 VDD25 VDD25 LDO +3.3V GNDA 5.1.4 Clock Control System control determines the control of clocks in this part. 5.1.4.1 Fundamental Clock Sources There are multiple clock sources for use in the device: ■ Internal Oscillator (IOSC). The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being January 08, 2011 175 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller used, the crystal value must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit field in the RCC register (see page 192). ■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. ■ External Real-Time Oscillator. The external real-time oscillator provides a low-frequency, accurate clock reference. It is intended to provide the system with a real-time clock source. The real-time oscillator is part of the Hibernation Module (see “Hibernation Module” on page 236) and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the above sources plus two others: the output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). Table 5-2 on page 176 shows how the various clock sources can be used in a system. Table 5-2. Clock Source Options Clock Source Drive PLL? Used as SysClk? Internal Oscillator (12 MHz) No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x1 Internal Oscillator divide by 4 (3 No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x2 MHz) BYPASS = 0, OSCSRC = Yes BYPASS = 1, OSCSRC = 0x0 0x0 Main Oscillator Yes Internal 30-kHz Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC = 0x3 External Real-Time Oscillator No BYPASS = 1 Yes BYPASS = 1, OSCSRC2 = 0x7 5.1.4.2 Clock Configuration The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. These registers control the following clock functionality: ■ Source of clocks in sleep and deep-sleep modes ■ System clock derived from PLL or other clock source ■ Enabling/disabling of oscillators and PLL ■ Clock divisors ■ Crystal input selection Figure 5-5 on page 177 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. The ADC clock signal is automatically divided down to 16 MHz for proper ADC operation. The PWM clock signal is a 176 January 08, 2011 Texas Instruments-Production Data System Control synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV in RCC). Note: When the ADC module is in operation, the system clock must be at least 16 MHz. Figure 5-5. Main Clock Tree PLL Main OSC (400 MHz) Internal OSC (12 MHz) Internal OSC (30 kHz) ÷ 4 Hibernation Module (32.768 kHz) ÷ 25 PWRDN ADC Clock System Clock XTALa PWRDN b MOSCDIS a IOSCDISa OSCSRCb,d BYPASS b,d SYSDIVb,d USESYSDIV a,d PWMDW a USEPWMDIV a PWM Clock a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. ÷ 2 ÷ 50 CAN Clock Note: The figure above shows all features available on all Stellaris® Fury-class devices. Not all peripherals may be available on this device. In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. Table 5-3 shows how the SYSDIV encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1). January 08, 2011 177 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see Table 5-2 on page 176. Table 5-3. Possible System Clock Frequencies Using the SYSDIV Field Frequency Frequency (BYPASS=1) StellarisWare Parametera (BYPASS=0) SYSDIV Divisor 0x0 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1b 0x1 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x2 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3 0x3 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x4 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x5 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x6 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x7 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x8 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x9 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 0xA /11 18.18 MHz Clock source frequency/11 SYSCTL_SYSDIV_11 0xB /12 16.67 MHz Clock source frequency/12 SYSCTL_SYSDIV_12 0xC /13 15.38 MHz Clock source frequency/13 SYSCTL_SYSDIV_13 0xD /14 14.29 MHz Clock source frequency/14 SYSCTL_SYSDIV_14 0xE /15 13.33 MHz Clock source frequency/15 SYSCTL_SYSDIV_15 0xF /16 12.5 MHz (default) Clock source frequency/16 SYSCTL_SYSDIV_16 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding plus 1. Table 5-4 shows how the SYSDIV2 encoding affects the system clock frequency, depending on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list of possible clock sources, see Table 5-2 on page 176. Table 5-4. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field Frequency Frequency (BYPASS2=1) StellarisWare Parametera (BYPASS2=0) SYSDIV2 Divisor 0x00 /1 reserved Clock source frequency/2 SYSCTL_SYSDIV_1b 0x01 /2 reserved Clock source frequency/2 SYSCTL_SYSDIV_2 0x02 /3 reserved Clock source frequency/3 SYSCTL_SYSDIV_3 0x03 /4 50 MHz Clock source frequency/4 SYSCTL_SYSDIV_4 0x04 /5 40 MHz Clock source frequency/5 SYSCTL_SYSDIV_5 0x05 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x06 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x07 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x08 /9 22.22 MHz Clock source frequency/9 SYSCTL_SYSDIV_9 0x09 /10 20 MHz Clock source frequency/10 SYSCTL_SYSDIV_10 178 January 08, 2011 Texas Instruments-Production Data System Control Table 5-4. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) Frequency Frequency (BYPASS2=1) StellarisWare Parametera (BYPASS2=0) SYSDIV2 Divisor ... ... ... ... ... 0x3F /64 3.125 MHz Clock source frequency/64 SYSCTL_SYSDIV_64 a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library. b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results in the system clock having the same frequency as the clock source. 5.1.4.3 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 192) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 5.1.4.4 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software specifies the output divisor to set the system clock frequency, and enables the main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 196). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. Table 22-9 on page 683 shows the actual PLL frequency and error for a given crystal choice. The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 192) describes the available crystal choices and default programming of the PLLCFG register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. To configure the external 32-kHz real-time oscillator as the PLL input reference, program the OSCRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x7. 5.1.4.5 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 192 and page 197). 5.1.4.6 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 22-8 on page 682). During the relock time, the affected PLL is not usable as a clock reference. January 08, 2011 179 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the controller from the oscillator selected by the RCC/RCC2 register until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. 5.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. There are four levels of operation for the device defined as: ■ Run Mode. In Run mode, the controller actively executes code. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor and the memory subsystem are not clocked and therefore no longer execute code. Sleep mode is entered by the Cortex-M3 core executing a WFI(Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See “Power Management” on page 89 for more details. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See “Power Management” on page 89 for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the 180 January 08, 2011 Texas Instruments-Production Data System Control WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. ■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. It can determine that it has been restarted from Hibernate mode by inspecting the Hibernation module registers. Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals have been restored to their run mode configuration. The DAP is usually enabled by software tools accessing the JTAG or SWD interface when debugging or flash programming. If this condition occurs, a Hard Fault is triggered when software accesses a peripheral with an invalid clock. A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses a peripheral register that might cause a fault. This loop can be removed for production software as the DAP is most likely not enabled during normal execution. Because the DAP is disabled by default (power on reset), the user can also power-cycle the device. The DAP is not enabled unless it is enabled through the JTAG or SWD interface. 5.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5.3 Register Map Table 5-5 on page 182 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. January 08, 2011 181 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Note: Spaces in the System Control register space that are not used are reserved for future or internal use. Software should not modify any reserved memory address. Table 5-5. System Control Register Map See Offset Name Type Reset Description page 0x000 DID0 RO - Device Identification 0 184 0x004 DID1 RO - Device Identification 1 200 0x008 DC0 RO 0x00FF.007F Device Capabilities 0 202 0x010 DC1 RO 0x0311.33FF Device Capabilities 1 203 0x014 DC2 RO 0x070F.5337 Device Capabilities 2 205 0x018 DC3 RO 0xBF0F.B7FF Device Capabilities 3 207 0x01C DC4 RO 0x0000.00FF Device Capabilities 4 209 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 186 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 187 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 231 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 233 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 235 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 188 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 189 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 190 0x05C RESC R/W - Reset Cause 191 0x060 RCC R/W 0x078E.3AD1 Run-Mode Clock Configuration 192 0x064 PLLCFG RO - XTAL to PLL Translation 196 0x070 RCC2 R/W 0x0780.2810 Run-Mode Clock Configuration 2 197 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 210 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 216 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 225 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 212 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 219 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 227 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 214 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 222 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 229 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 199 182 January 08, 2011 Texas Instruments-Production Data System Control 5.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. January 08, 2011 183 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved VER reserved CLASS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 Second version of the DID0 register format. 30:28 VER RO 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:24 reserved RO 0x0 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 184 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 15:8 MAJOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. 7:0 MINOR RO - January 08, 2011 185 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BORIOR reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 1 BORIOR R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 186 January 08, 2011 Texas Instruments-Production Data System Control Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VADJ Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 5:0 VADJ R/W 0x0 January 08, 2011 187 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLRIS reserved BORRIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 6 PLLLRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 1 BORRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 188 January 08, 2011 Texas Instruments-Production Data System Control Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLIM reserved BORIM reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Interrupt Mask This bit specifies whether a PLL Lock interrupt is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 1 BORIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 January 08, 2011 189 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 188). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLMIS reserved BORMIS reserved Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 1 BORMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 190 January 08, 2011 Texas Instruments-Production Data System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SW WDT BOR POR EXT Type RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:5 reserved RO 0 Software Reset When set, indicates a software reset is the cause of the reset event. 4 SW R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 3 WDT R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 2 BOR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 1 POR R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. 0 EXT R/W - January 08, 2011 191 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x078E.3AD1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ACG SYSDIV USESYSDIV reserved USEPWMDIV PWMDIV reserved Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0x0 Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 27 ACG R/W 0 System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). See Table 5-3 on page 178 for bit encodings. If the SYSDIV value is less than MINSYSDIV (see page 203), and the PLL is being used, then the MINSYSDIV value is used as the divisor. If the PLL is not being used, the SYSDIV value can be less than MINSYSDIV. 26:23 SYSDIV R/W 0xF Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. If the USERCC2 bit in the RCC2 register is set, then the SYSDIV2 field in the RCC2 register is used as the system clock divider rather than the SYSDIV field in this register. 22 USESYSDIV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21 reserved RO 0 192 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Enable PWM Clock Divisor Use the PWM clock divider as the source for the PWM clock. 20 USEPWMDIV R/W 0 PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. This clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. Value Divisor 0x0 /2 0x1 /4 0x2 /8 0x3 /16 0x4 /32 0x5 /64 0x6 /64 0x7 /64 (default) 19:17 PWMDIV R/W 0x7 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 16:14 reserved RO 0 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 13 PWRDN R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 1 PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. See Table 5-3 on page 178 for programming guidelines. Note: The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. While the ADC works in a 14-18 MHz range, to maintain a 1 M sample/second rate, the ADC must be provided a 16-MHz clock source. 11 BYPASS R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 reserved RO 0 January 08, 2011 193 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz (see Table 22-9 on page 683 for more information). Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value 0x0 1.000 reserved 0x1 1.8432 reserved 0x2 2.000 reserved 0x3 2.4576 reserved 0x4 3.579545 MHz 0x5 3.6864 MHz 0x6 4 MHz 0x7 4.096 MHz 0x8 4.9152 MHz 0x9 5 MHz 0xA 5.12 MHz 0xB 6 MHz (reset value) 0xC 6.144 MHz 0xD 7.3728 MHz 0xE 8 MHz 0xF 8.192 MHz 9:6 XTAL R/W 0xB Oscillator Source Selects the input source for the OSC. The values are: Value Input Source MOSC Main oscillator 0x0 IOSC Internal oscillator (default) 0x1 IOSC/4 Internal oscillator / 4 0x2 30 kHz 30-KHz internal oscillator 0x3 For additional oscillator sources, see the RCC2 register. 5:4 OSCSRC R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 194 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). 0 MOSCDIS R/W 1 January 08, 2011 195 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 192). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved F R Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x0 PLL F Value This field specifies the value supplied to the PLL’s F input. 13:5 F RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 4:0 R RO - 196 January 08, 2011 Texas Instruments-Production Data System Control Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-6, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts. Each RCC2 field that supersedes an RCC field is located at the same LSB bit position; however, some RCC2 fields are larger than the corresponding RCC field. Table 5-6. RCC2 Fields that Override RCC fields RCC2 Field... Overrides RCC Field SYSDIV2, bits[28:23] SYSDIV, bits[26:23] PWRDN2, bit[13] PWRDN, bit[13] BYPASS2, bit[11] BYPASS, bit[11] OSCSRC2, bits[6:4] OSCSRC, bits[5:4] Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2810 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 USERCC2 reserved SYSDIV2 reserved Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Use RCC2 When set, overrides the RCC register fields. 31 USERCC2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30:29 reserved RO 0x0 System Clock Divisor Specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS2 bit is configured). SYSDIV2 is used for the divisor when both the USESYSDIV bit in the RCC register and the USERCC2 bit in this register are set. See Table 5-4 on page 178 for programming guidelines. 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:14 reserved RO 0x0 Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 January 08, 2011 197 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Bypass PLL When set, bypasses the PLL for the clock source. See Table 5-4 on page 178 for programming guidelines. 11 BYPASS2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:7 reserved RO 0x0 Oscillator Source Selects the input source for the OSC. The values are: Value Description MOSC Main oscillator 0x0 IOSC Internal oscillator 0x1 IOSC/4 Internal oscillator / 4 0x2 30 kHz 30-kHz internal oscillator 0x3 0x4 Reserved 0x5 Reserved 0x6 Reserved 32 kHz 32.768-kHz external oscillator 0x7 6:4 OSCSRC2 R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0 198 January 08, 2011 Texas Instruments-Production Data System Control Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DSDIVORIDE reserved Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DSOSCSRC reserved Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:29 reserved RO 0x0 Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 28:23 DSDIVORIDE R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:7 reserved RO 0x0 Clock Source Specifies the clock source during Deep-Sleep mode. Value Description MOSC Use main oscillator as source. 0x0 IOSC Use internal 12-MHz oscillator as source. 0x1 0x2 Reserved 30 kHz Use 30-kHz internal oscillator as source. 0x3 0x4 Reserved 0x5 Reserved 0x6 Reserved 32 kHz Use 32.768-kHz external oscillator as source. 0x7 6:4 DSOSCSRC R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x0 January 08, 2011 199 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VER FAM PARTNO Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINCOUNT reserved TEMP PKG ROHS QUAL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 0 - - - - - 1 - - Bit/Field Name Type Reset Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 Second version of the DID1 register format. 31:28 VER RO 0x1 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 0x0 27:24 FAM RO 0x0 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x55 LM3S2965 23:16 PARTNO RO 0x55 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin or 108-ball package 15:13 PINCOUNT RO 0x2 200 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:8 reserved RO 0 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Commercial temperature range (0°C to 70°C) 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) 7:5 TEMP RO - Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 SOIC package 0x1 LQFP package 0x2 BGA package 4:3 PKG RO - RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 2 ROHS RO 1 Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 1:0 QUAL RO - January 08, 2011 201 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 31:16 SRAMSZ RO 0x00FF Flash Size Indicates the size of the on-chip flash memory. Value Description 0x007F 256 KB of Flash 15:0 FLASHSZ RO 0x007F 202 January 08, 2011 Texas Instruments-Production Data System Control Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0311.33FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN1 CAN0 reserved PWM reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MINSYSDIV reserved MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:26 reserved RO 0 CAN Module 1 Present When set, indicates that CAN unit 1 is present. 25 CAN1 RO 1 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 24 CAN0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 reserved RO 0 PWM Module Present When set, indicates that the PWM module is present. 20 PWM RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC Module Present When set, indicates that the ADC module is present. 16 ADC RO 1 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 15:12 MINSYSDIV RO 0x3 January 08, 2011 203 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x3 1M samples/second 9:8 MAXADCSPD RO 0x3 MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter in the Stellaris Data Sheet for details on the MPU. 7 MPU RO 1 Hibernation Module Present When set, indicates that the Hibernation module is present. 6 HIB RO 1 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 5 TEMPSNS RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 4 PLL RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 3 WDT RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 2 SWO RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 1 SWD RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 0 JTAG RO 1 204 January 08, 2011 Texas Instruments-Production Data System Control Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x070F.5337 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 26 COMP2 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 25 COMP1 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 24 COMP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 Timer 3 Present When set, indicates that General-Purpose Timer module 3 is present. 19 TIMER3 RO 1 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 18 TIMER2 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 17 TIMER1 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 16 TIMER0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 I2C Module 1 Present When set, indicates that I2C module 1 is present. 14 I2C1 RO 1 January 08, 2011 205 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 I2C Module 0 Present When set, indicates that I2C module 0 is present. 12 I2C0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 QEI1 Present When set, indicates that QEI module 1 is present. 9 QEI1 RO 1 QEI0 Present When set, indicates that QEI module 0 is present. 8 QEI0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 SSI1 Present When set, indicates that SSI module 1 is present. 5 SSI1 RO 1 SSI0 Present When set, indicates that SSI module 0 is present. 4 SSI0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Present When set, indicates that UART module 2 is present. 2 UART2 RO 1 UART1 Present When set, indicates that UART module 1 is present. 1 UART1 RO 1 UART0 Present When set, indicates that UART module 0 is present. 0 UART0 RO 1 206 January 08, 2011 Texas Instruments-Production Data System Control Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0xBF0F.B7FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 32KHZ reserved CCP5 CCP4 CCP3 CCP2 CCP1 CCP0 reserved ADC3 ADC2 ADC1 ADC0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWMFAULT reserved C2PLUS C2MINUS reserved C1PLUS C1MINUS C0O C0PLUS C0MINUS PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description 32KHz Input Clock Available When set, indicates an even CCP pin is present and can be used as a 32-KHz input clock. 31 32KHZ RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30 reserved RO 0 CCP5 Pin Present When set, indicates that Capture/Compare/PWM pin 5 is present. 29 CCP5 RO 1 CCP4 Pin Present When set, indicates that Capture/Compare/PWM pin 4 is present. 28 CCP4 RO 1 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 27 CCP3 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 26 CCP2 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 25 CCP1 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 24 CCP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 ADC3 Pin Present When set, indicates that ADC pin 3 is present. 19 ADC3 RO 1 ADC2 Pin Present When set, indicates that ADC pin 2 is present. 18 ADC2 RO 1 January 08, 2011 207 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description ADC1 Pin Present When set, indicates that ADC pin 1 is present. 17 ADC1 RO 1 ADC0 Pin Present When set, indicates that ADC pin 0 is present. 16 ADC0 RO 1 PWM Fault Pin Present When set, indicates that the PWM Fault pin is present. 15 PWMFAULT RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 14 reserved RO 0 C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. 13 C2PLUS RO 1 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. 12 C2MINUS RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11 reserved RO 0 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 10 C1PLUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 9 C1MINUS RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 8 C0O RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 7 C0PLUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 6 C0MINUS RO 1 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 5 PWM5 RO 1 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 4 PWM4 RO 1 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 3 PWM3 RO 1 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 2 PWM2 RO 1 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 1 PWM1 RO 1 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. 0 PWM0 RO 1 208 January 08, 2011 Texas Instruments-Production Data System Control Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 GPIO Port H Present When set, indicates that GPIO Port H is present. 7 GPIOH RO 1 GPIO Port G Present When set, indicates that GPIO Port G is present. 6 GPIOG RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 5 GPIOF RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 4 GPIOE RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 3 GPIOD RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 2 GPIOC RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 1 GPIOB RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 0 GPIOA RO 1 January 08, 2011 209 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN1 CAN0 reserved PWM reserved ADC Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO RO RO R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:26 reserved RO 0 CAN1 Clock Gating Control This bit controls the clock gating for CAN unit 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 25 CAN1 R/W 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 210 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 reserved RO 0 ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 9:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 January 08, 2011 211 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN1 CAN0 reserved PWM reserved ADC Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO RO RO R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:26 reserved RO 0 CAN1 Clock Gating Control This bit controls the clock gating for CAN unit 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 25 CAN1 R/W 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 212 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:10 reserved RO 0 ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 9:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 January 08, 2011 213 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN1 CAN0 reserved PWM reserved ADC Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved HIB reserved WDT reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:26 reserved RO 0 CAN1 Clock Gating Control This bit controls the clock gating for CAN unit 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 25 CAN1 R/W 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 reserved RO 0 PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 214 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 January 08, 2011 215 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0 Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 216 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 14 I2C1 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 9 QEI1 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 8 QEI0 R/W 0 January 08, 2011 217 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 SSI1 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 218 January 08, 2011 Texas Instruments-Production Data System Control Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0 Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 January 08, 2011 219 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 14 I2C1 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 9 QEI1 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 8 QEI0 R/W 0 220 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 SSI1 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 January 08, 2011 221 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0 Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 222 January 08, 2011 Texas Instruments-Production Data System Control Bit/Field Name Type Reset Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 14 I2C1 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 9 QEI1 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 8 QEI0 R/W 0 January 08, 2011 223 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 SSI1 Clock Gating Control This bit controls the clock gating for SSI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 SSI1 R/W 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 224 January 08, 2011 Texas Instruments-Production Data System Control Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7 GPIOH R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 January 08, 2011 225 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 226 January 08, 2011 Texas Instruments-Production Data System Control Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7 GPIOH R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 January 08, 2011 227 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 228 January 08, 2011 Texas Instruments-Production Data System Control Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7 GPIOH R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 January 08, 2011 229 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 230 January 08, 2011 Texas Instruments-Production Data System Control Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN1 CAN0 reserved PWM reserved ADC Type RO RO RO RO RO RO R/W R/W RO RO RO R/W RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved HIB reserved WDT reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:26 reserved RO 0 CAN1 Reset Control Reset control for CAN unit 1. 25 CAN1 R/W 0 CAN0 Reset Control Reset control for CAN unit 0. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:21 reserved RO 0 PWM Reset Control Reset control for PWM module. 20 PWM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:17 reserved RO 0 ADC0 Reset Control Reset control for SAR ADC module 0. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:7 reserved RO 0 HIB Reset Control Reset control for the Hibernation module. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Reset Control Reset control for Watchdog unit. 3 WDT R/W 0 January 08, 2011 231 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 232 January 08, 2011 Texas Instruments-Production Data System Control Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C1 reserved I2C0 reserved QEI1 QEI0 reserved SSI1 SSI0 reserved UART2 UART1 UART0 Type RO R/W RO R/W RO RO R/W R/W RO RO R/W R/W RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comp 2 Reset Control Reset control for analog comparator 2. 26 COMP2 R/W 0 Analog Comp 1 Reset Control Reset control for analog comparator 1. 25 COMP1 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 Timer 3 Reset Control Reset control for General-Purpose Timer module 3. 19 TIMER3 R/W 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 18 TIMER2 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 17 TIMER1 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15 reserved RO 0 I2C1 Reset Control Reset control for I2C unit 1. 14 I2C1 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 reserved RO 0 January 08, 2011 233 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description I2C0 Reset Control Reset control for I2C unit 0. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 QEI1 Reset Control Reset control for QEI unit 1. 9 QEI1 R/W 0 QEI0 Reset Control Reset control for QEI unit 0. 8 QEI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 SSI1 Reset Control Reset control for SSI unit 1. 5 SSI1 R/W 0 SSI0 Reset Control Reset control for SSI unit 0. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3 reserved RO 0 UART2 Reset Control Reset control for UART unit 2. 2 UART2 R/W 0 UART1 Reset Control Reset control for UART unit 1. 1 UART1 R/W 0 UART0 Reset Control Reset control for UART unit 0. 0 UART0 R/W 0 234 January 08, 2011 Texas Instruments-Production Data System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 Port H Reset Control Reset control for GPIO Port H. 7 GPIOH R/W 0 Port G Reset Control Reset control for GPIO Port G. 6 GPIOG R/W 0 Port F Reset Control Reset control for GPIO Port F. 5 GPIOF R/W 0 Port E Reset Control Reset control for GPIO Port E. 4 GPIOE R/W 0 Port D Reset Control Reset control for GPIO Port D. 3 GPIOD R/W 0 Port C Reset Control Reset control for GPIO Port C. 2 GPIOC R/W 0 Port B Reset Control Reset control for GPIO Port B. 1 GPIOB R/W 0 Port A Reset Control Reset control for GPIO Port A. 0 GPIOA R/W 0 January 08, 2011 235 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 6 Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in Real-Time Clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: ■ System power control using discrete external regulator ■ Dedicated pin for waking from an external signal ■ Low-battery detection, signaling, and interrupt generation ■ 32-bit real-time clock (RTC) ■ Two 32-bit RTC match registers for timed wake-up and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal ■ RTC predivider trim for making fine adjustments to the clock rate ■ 64 32-bit words of non-volatile memory ■ Programmable interrupts for RTC match, external wake, and low battery events 236 January 08, 2011 Texas Instruments-Production Data Hibernation Module 6.1 Block Diagram Figure 6-1. Hibernation Module Block Diagram HIBIM HIBRIS HIBMIS HIBIC HIBRTCT Pre-Divider /128 XOSC0 XOSC1 HIBCTL.CLK32EN HIBCTL.CLKSEL HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 RTC Interrupts Power Sequence Logic MATCH0/1 WAKE Interrupts to CPU Low Battery Detect LOWBAT VDD VBAT HIB HIBCTL.LOWBATEN HIBCTL.PWRCUT HIBCTL.EXTWEN HIBCTL.RTCWEN HIBCTL.VABORT Non-Volatile Memory 64 words HIBDATA 32.768 kHz 4.194304 MHz 6.2 Functional Description The Hibernation module controls the power to the processor with an enable signal (HIB) that signals an external voltage regulator to turn off. The Hibernation module power source is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. The Hibernation module also has a separate clock source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low, and optionally prevent hibernation when this occurs. When waking from hibernation, the HIB signal is deasserted. The return of VDD causes a POR to be executed. The time from when the WAKE signal is asserted to when code begins execution is equal to the wake-up time (tWAKE_TO_HIB) plus the power-on reset time (TIRPOR). 6.2.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain Hibernation registers, or between a write followed by a read to those same registers. There is no January 08, 2011 237 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller restriction on timing for back-to-back reads from the Hibernation module. The following registers are subject to this timing restriction: ■ Hibernation RTC Counter (HIBRTCC) ■ Hibernation RTC Match 0 (HIBRTCM0) ■ Hibernation RTC Match 1 (HIBRTCM1) ■ Hibernation RTC Load (HIBRTCLD) ■ Hibernation RTC Trim (HIBRTCT) ■ Hibernation Data (HIBDATA) 6.2.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature is not used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. For an alternate clock source, a 32.768-kHz oscillator can be connected to the XOSC0 pin. See Figure 6-2 on page 239 and Figure 6-3 on page 239. Note that these diagrams only show the connection to the Hibernation pins and not to the full system. See “Hibernation Module” on page 687 for specific values. The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a 32.768-kHz clock source. If the bit is set to 0, the 4.194304-MHz input clock is divided by 128, resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. 238 January 08, 2011 Texas Instruments-Production Data Hibernation Module Figure 6-2. Clock Source Using Crystal Open drain external wake up circuit 3 V Battery GND C1 C2 X1 RL VBAT EN Input Voltage Regulator or Switch XOSC1 XOSC0 VDD HIB WAKE IN OUT Stellaris Microcontroller RPU Note: X1 = Crystal frequency is fXOSC_XTAL. C1,2 = Capacitor value derived from crystal vendor load capacitance specifications. RL = Load resistor is RXOSC_LOAD. RPU = Pull-up resistor (1 M½). See “Hibernation Module” on page 687 for specific parameter values. Figure 6-3. Clock Source Using Dedicated Oscillator Open drain external wake up circuit EN 3 V Battery GND Stellaris Microcontroller Input Voltage Regulator or Switch Clock Source (fEXT_OSC) N.C. XOSC1 XOSC0 VDD HIB WAKE VBAT IN OUT RPU Note: RPU = Pull-up resistor (1 M½). 6.2.3 Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage drops below VLOWBAT. When this happens, an interrupt can be generated. The module can also be configured so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Battery voltage is not measured while in Hibernate mode. January 08, 2011 239 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Important: System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements. Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 241). 6.2.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see “Clock Source” on page 238). The 32.768-kHz clock signal is fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate, and down from 0x7FFF in order to speed up the RTC rate. The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see “Interrupts and Status” on page 241). 6.2.5 Non-Volatile Memory The Hibernation module contains 64 32-bit words of memory which are retained during hibernation. This memory is powered from the battery or auxiliary power supply during hibernation. The processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. The non-volatile memory can be accessed through the HIBDATA registers. 6.2.6 Power Control Important: The Hibernation Module requires special system implementation considerations when using HIB to control power, as it is intended to power-down all other sections of its host device. All system signals and power supplies that connect to the chip must be driven to 0 VDC or powered down with the same regulator controlled by HIB. See “Hibernation Module” on page 687 for more details. The Hibernation module controls power to the microcontroller through the use of the HIB pin. This pin is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V 240 January 08, 2011 Texas Instruments-Production Data Hibernation Module and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the system. The Hibernation module remains powered from the VBAT supply (which could be a battery or an auxiliary power source) until a Wake event. Power to the device is restored by deasserting the HIB signal, which causes the external regulator to turn power back on to the chip. 6.2.7 Initiating Hibernate Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power supply as the logic 1 reference. When the Hibernation module wakes, the microcontroller will see a normal power-on reset. Software can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 241) and by looking for state data in the non-volatile memory (see “Non-Volatile Memory” on page 240). When the HIB signal deasserts, enabling the external regulator, the external regulator must reach the operating voltage within tHIB_TO_VDD. 6.2.8 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register. 6.3 Initialization and Configuration The Hibernation module can be set in several different configurations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32.768 kHz and is asynchronous to the rest of the system, software must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access Timing” on page 237). The registers that require a delay are listed in a note in “Register Map” on page 243 as well as in each register description. January 08, 2011 241 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 6.3.1 Initialization The Hibernation module clock source must be enabled first, even if the RTC feature is not used. If a 4.194304-MHz crystal is used, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any other operations with the Hibernation module. If a 32.678-kHz oscillator is used, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input. 2. No delay is necessary. The above is only necessary when the entire system is initialized for the first time. If the processor is powered due to a wake from hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. 6.3.2 RTC Match Functionality (No Hibernation) Use the following steps to implement the RTC match functionality of the Hibernation module: 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 6.3.3 RTC Match/Wake-Up from Hibernation Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 6.3.4 External Wake-Up from Hibernation Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 242 January 08, 2011 Texas Instruments-Production Data Hibernation Module 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 6.3.5 RTC/External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 6.4 Register Map Table 6-1 on page 243 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note that the Hibernation module clock must be enabled before the registers can be programmed (see page 210). There must be a delay of 3 system clocks after the Hibernation module clock is enabled before any Hibernation module registers are accessed. Table 6-1. Hibernation Module Register Map See Offset Name Type Reset Description page 0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 244 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 245 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 246 0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 247 0x010 HIBCTL R/W 0x8000.0000 Hibernation Control 248 0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 250 0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 251 0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 252 0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 253 0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 254 0x030- HIBDATA R/W - Hibernation Data 255 0x12C 6.5 Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. January 08, 2011 243 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description RTC Counter A read returns the 32-bit counter value. This register is read-only. To change the value, use the HIBRTCLD register. 31:0 RTCC RO 0x0000.0000 244 January 08, 2011 Texas Instruments-Production Data Hibernation Module Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 31:0 RTCM0 R/W 0xFFFF.FFFF January 08, 2011 245 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCM1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. 31:0 RTCM1 R/W 0xFFFF.FFFF 246 January 08, 2011 Texas Instruments-Production Data Hibernation Module Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCLD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCLD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 31:0 RTCLD R/W 0xFFFF.FFFF January 08, 2011 247 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x8000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Power Cut Abort Enable Value Description 0 Power cut occurs during a low-battery alert. 1 Power cut is aborted. 7 VABORT R/W 0 Clocking Enable Value Description 0 Disabled 1 Enabled This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 6 CLK32EN R/W 0 Low Battery Monitoring Enable Value Description 0 Disabled 1 Enabled When set, low battery voltage detection is enabled (VBAT < VLOWBAT). 5 LOWBATEN R/W 0 External WAKE Pin Enable Value Description 0 Disabled 1 Enabled When set, an external event on the WAKE pin will re-power the device. 4 PINWEN R/W 0 248 January 08, 2011 Texas Instruments-Production Data Hibernation Module Bit/Field Name Type Reset Description RTC Wake-up Enable Value Description 0 Disabled 1 Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. 3 RTCWEN R/W 0 Hibernation Module Clock Select Value Description Use Divide by 128 output. Use this value for a 4.194304-MHz crystal. 0 Use raw output. Use this value for a 32.768-kHz oscillator. 1 2 CLKSEL R/W 0 Hibernation Request Value Description 0 Disabled 1 Hibernation initiated After a wake-up event, this bit is cleared by hardware. 1 HIBREQ R/W 0 RTC Timer Enable Value Description 0 Disabled 1 Enabled 0 RTCEN R/W 0 January 08, 2011 249 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 External Wake-Up Interrupt Mask Value Description 0 Masked 1 Unmasked 3 EXTW R/W 0 Low Battery Voltage Interrupt Mask Value Description 0 Masked 1 Unmasked 2 LOWBAT R/W 0 RTC Alert1 Interrupt Mask Value Description 0 Masked 1 Unmasked 1 RTCALT1 R/W 0 RTC Alert0 Interrupt Mask Value Description 0 Masked 1 Unmasked 0 RTCALT0 R/W 0 250 January 08, 2011 Texas Instruments-Production Data Hibernation Module Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Raw Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status January 08, 2011 251 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Masked Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status 252 January 08, 2011 Texas Instruments-Production Data Hibernation Module Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 External Wake-Up Masked Interrupt Clear Reads return an indeterminate value. 3 EXTW R/W1C 0 Low Battery Voltage Masked Interrupt Clear Reads return an indeterminate value. 2 LOWBAT R/W1C 0 RTC Alert1 Masked Interrupt Clear Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert0 Masked Interrupt Clear Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 January 08, 2011 253 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRIM Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. The compensation is made by software by adjusting the default value of 0x7FFF up or down. 15:0 TRIM R/W 0x7FFF 254 January 08, 2011 Texas Instruments-Production Data Hibernation Module Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store any non-volatile state data and will not lose power during a power cut operation. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 RTD R/W - Hibernation Module NV Registers[63:0] January 08, 2011 255 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 7 Internal Memory The LM3S2965 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1 on page 256 illustrates the Flash functions. The dashed boxes in the figure indicate registers residing in the System Control module rather than the Flash Control module. Figure 7-1. Flash Block Diagram Flash Control FMA FMD FCIM FCMISC Flash Array Cortex-M3 Bridge SRAM Array System Bus Icode Bus Dcode Bus Flash Protection FMPREn FMPPEn Flash Timing USECRL User Registers USER_DBG USER_REG0 USER_REG1 FMC FCRIS 7.2 Functional Description This section describes the functionality of the SRAM and Flash memories. 7.2.1 SRAM Memory The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C 256 January 08, 2011 Texas Instruments-Production Data Internal Memory With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 75. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 693 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 7.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 7.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If a bit is set, the corresponding block may be executed or read by software or debuggers. If a bit is cleared, the corresponding block may only be executed, and contents of the memory block are prohibited from being read as data. The policies may be combined as shown in Table 7-1 on page 257. Table 7-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 0 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. 1 0 January 08, 2011 257 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 7-1. Flash Protection Policy Combinations (continued) FMPPEn FMPREn Protection Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 0 1 1 1 No protection. The block may be written, erased, executed or read. A Flash memory access that attempts to read a read-protected block (FMPREn bit is set) is prohibited and generates a bus fault. A Flash memory access that attempts to program or erase a program-protected block (FMPPEn bit is set) is prohibited and can optionally generate an interrupt (by setting the AMASK bit in the Flash Controller Interrupt Mask (FCIM) register) to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. These settings create a policy of open access and programmability. The register bits may be changed by clearing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The changes are committed using the Flash Memory Control (FMC) register. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 259. 7.2.2.3 Interrupts The Flash memory controller can generate interrupts when the following conditions are observed: ■ Programming Interrupt - signals when a program or erase action is complete. ■ Access Interrupt - signals when a program or erase action has been attempted on a 2-kB block of memory that is protected by its corresponding FMPPEn bit. The interrupt events that can trigger a controller-level interrupt are defined in the Flash Controller Masked Interrupt Status (FCMIS) register (see page 267) by setting the corresponding MASK bits. If interrupts are not used, the raw interrupt status is always visible via the Flash Controller Raw Interrupt Status (FCRIS) register (see page 266). Interrupts are always cleared (for both the FCMIS and FCRIS registers) by writing a 1 to the corresponding bit in the Flash Controller Masked Interrupt Status and Clear (FCMISC) register (see page 268). 7.3 Flash Memory Initialization and Configuration 7.3.1 Flash Programming The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. During a Flash memory operation (write, page erase, or mass erase) access to the Flash memory is inhibited. As a result, instruction and literal fetches are held off until the Flash memory operation is complete. If instruction execution is required during a Flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress. 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 258 January 08, 2011 Texas Instruments-Production Data Internal Memory 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 7.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. 7.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the Flash memory itself. These registers exist in a separate space from the main Flash memory array and are not affected by an ERASE or MASS ERASE operation. The bits in these registers can be changed from 1 to 0 with a write operation. Prior to being committed, the register contents are unaffected by any reset condition except power-on reset, which returns the register contents to the original value. By committing the register values using the COMT bit in the FMC register, the register contents become nonvolatile and are therefore retained following power cycling. Once the register contents are committed, the contents are permanent, and they cannot be restored to their factory default values. With the exception of the USER_DBG register, the settings in these registers can be tested before committing them to Flash memory. For the USER_DBG register, the data to be written is loaded into the FMD register before it is committed. The FMD register is read only and does not allow the USER_DBG operation to be tried before committing it to nonvolatile memory. Important: The Flash memory registers can only have bits changed from 1 to 0 by user programming and can only be committed once. After being committed, these registers cannot be restored to their factory default values. In addition, the USER_REG0, USER_REG1, USER_REG2, USER_REG3, and USER_DBG registers each use bit 31 (NW) to indicate that they have not been committed and bits in the register may be changed from 1 to 0. These five registers can only be committed once whereas the Flash memory protection registers may be committed multiple times. Table 7-2 on page 259 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 7-2. User-Programmable Flash Memory Resident Registers Register to be Committed FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0006 FMPRE3 January 08, 2011 259 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 7-2. User-Programmable Flash Memory Resident Registers (continued) Register to be Committed FMA Value Data Source FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_REG2 0x8000.0002 USER_REG2 USER_REG3 0x8000.0003 USER_REG3 USER_DBG 0x7510.0000 FMD 7.4 Register Map Table 7-3 on page 260 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC register offsets are relative to the Flash memory control base address of 0x400F.D000. The Flash memory protection register offsets are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map See Offset Name Type Reset Description page Flash Memory Control Registers (Flash Control Offset) 0x000 FMA R/W 0x0000.0000 Flash Memory Address 262 0x004 FMD R/W 0x0000.0000 Flash Memory Data 263 0x008 FMC R/W 0x0000.0000 Flash Memory Control 264 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 266 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 267 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 268 Flash Memory Protection Registers (System Control Offset) 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 271 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 271 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 272 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 272 0x140 USECRL R/W 0x31 USec Reload 270 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 273 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 274 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 275 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 276 0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 277 260 January 08, 2011 Texas Instruments-Production Data Internal Memory Table 7-3. Flash Register Map (continued) See Offset Name Type Reset Description page 0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 278 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 279 0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 280 0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 281 7.5 Flash Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. January 08, 2011 261 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved OFFSET Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:18 reserved RO 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 259 for details on values for this field). 17:0 OFFSET R/W 0x0 262 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Data Value Data value for write operation. 31:0 DATA R/W 0x0 January 08, 2011 263 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 262). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 263) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved COMT MERASE ERASE WRITE Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 31:16 WRKEY WO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:4 reserved RO 0x0 Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 3 COMT R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 2 MERASE R/W 0 264 January 08, 2011 Texas Instruments-Production Data Internal Memory Bit/Field Name Type Reset Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 1 ERASE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 μs. 0 WRITE R/W 0 January 08, 2011 265 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIS ARIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC register bits (see page 264). Value Description 1 The programming cycle has completed. 0 The programming cycle has not completed. This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 1 PRIS RO 0 Access Raw Interrupt Status Value Description A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. 1 No access has tried to improperly program or erase the Flash memory. 0 This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register. 0 ARIS RO 0 266 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMASK AMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. Value Description An interrupt is sent to the interrupt controller when the PRIS bit is set. 1 The PRIS interrupt is suppressed and not sent to the interrupt controller. 0 1 PMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the interrupt controller. Value Description An interrupt is sent to the interrupt controller when the ARIS bit is set. 1 The ARIS interrupt is suppressed and not sent to the interrupt controller. 0 0 AMASK R/W 0 January 08, 2011 267 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMISC AMISC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 Programming Masked Interrupt Status and Clear Value Description When read, a 1 indicates that an unmasked interrupt was signaled because a programming cycle completed. Writing a 1 to this bit clears PMISC and also the PRIS bit in the FCRIS register (see page 266). 1 When read, a 0 indicates that a programming cycle complete interrupt has not occurred. A write of 0 has no effect on the state of this bit. 0 1 PMISC R/W1C 0 Access Masked Interrupt Status and Clear Value Description When read, a 1 indicates that an unmasked interrupt was signaled because a program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. Writing a 1 to this bit clears AMISC and also the ARIS bit in the FCRIS register (see page 266). 1 When read, a 0 indicates that no improper accesses have occurred. A write of 0 has no effect on the state of this bit. 0 0 AMISC R/W1C 0 268 January 08, 2011 Texas Instruments-Production Data Internal Memory 7.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. January 08, 2011 269 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved USEC Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. If the maximum system frequency is being used, USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 7:0 USEC R/W 0x31 270 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.E000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable. Enables 2-KB Flash memory blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 0xFFFFFFFF 31:0 READ_ENABLE R/W 0xFFFFFFFF January 08, 2011 271 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.E000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description Bits [31:0] each enable protection on a 2-KB block of Flash memory up to the total of 64 KB. 0xFFFFFFFF 31:0 PROG_ENABLE R/W 0xFFFFFFFF 272 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NW bit (bit 31) indicates that the register has not yet been committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. Once committed, this register cannot be restored to the factory default value. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DBG1 DBG0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Bit/Field Name Type Reset Description User Debug Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 30:2 DATA R/W 0x1FFFFFFF Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 1 DBG1 R/W 1 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 January 08, 2011 273 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once committed, this register cannot be restored to the factory default value. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 30:0 DATA R/W 0x7FFFFFFF 274 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. Once committed, this register cannot be restored to the factory default value. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written When set, this bit indicates that this 32-bit register has not been committed. When clear, this bit specifies that this register has been committed and may not be committed again. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be committed once. 30:0 DATA R/W 0x7FFFFFFF January 08, 2011 275 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable. Enables 2-KB Flash memory blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 0xFFFFFFFF 31:0 READ_ENABLE R/W 0xFFFFFFFF 276 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF January 08, 2011 277 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF 278 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks. This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. The reset value shown only applies to power-on reset; any other type of reset does not affect this register. If the Flash memory size on the device is less than 64 KB, this register usually reads as zeroes, but software should not rely on these bits to be zero. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Value Description Bits [31:0] each enable protection on a 2-KB block of Flash memory in memory range from 65 to 128 KB. 0xFFFFFFFF 31:0 PROG_ENABLE R/W 0xFFFFFFFF January 08, 2011 279 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF 280 January 08, 2011 Texas Instruments-Production Data Internal Memory Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF January 08, 2011 281 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, Port H). The GPIO module supports 3-56 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ 3-56 GPIOs, depending on configuration ■ 5-V-tolerant in input configuration ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ Bit masking in both read and write operations through address lines ■ Can initiate an ADC sample sequence ■ Pins configured as digital inputs are Schmitt-triggered. ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 8.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. While debugging systems where PB7 is being used as a GPIO, care must be taken to ensure that a low value is not applied to the pin when the part is reset. Because PB7 reverts to the TRST function after reset, a Low value on the pin causes the JTAG controller to be reset, resulting in a loss of JTAG communication. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 283). The LM3S2965 microcontroller contains eight ports and thus eight of these physical GPIO blocks. 282 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Figure 8-1. GPIO Port Block Diagram Alternate Input Alternate Output Alternate Output Enable Interrupt GPIO Input GPIO Output GPIO Output Enable Pad Output Pad Output Enable Package I/O Pin GPIODATA GPIODIR Data Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Interrupt Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Pad Control GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Identification Registers GPIOAFSEL Mode Control DEMUX MUX MUX Digital I/O Pad Pad Input GPIOLOCK Commit Control GPIOCR 8.1.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 8.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 291) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 8.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 290) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. January 08, 2011 283 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-2 on page 284, where u is data unchanged by the write. Figure 8-2. GPIODATA Write Example 0 0 1 0 0 1 1 0 0 u u 1 u u 0 1 u 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 GPIODATA 0xEB 0x098 ADDR[9:2] 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 284. Figure 8-3. GPIODATA Read Example 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 7 6 5 4 3 2 1 0 Returned Value GPIODATA 0x0C4 ADDR[9:2] 8.1.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 292) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 293) ■ GPIO Interrupt Event (GPIOIEV) register (see page 294) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 295). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 296 and page 297). As the name implies, the GPIOMIS register only shows interrupt 284 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the PortB interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4, and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 109 for more information. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 298). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 8.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 299), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 8.1.4 Commit Control The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 299) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 309) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 310) have been set to 1. 8.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength, open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital input enable. For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package. January 08, 2011 285 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 8.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 286 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-2 on page 286 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 8-1. GPIO Pad Configuration Examples GPIO Register Bit Valuea Configuration AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR Digital Input (GPIO) 0 0 0 1 ? ? X X X X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Output 0 1 1 1 X X ? ? ? ? (GPIO) Open Drain 1 X 1 1 X X ? ? ? ? Input/Output (I2C) Digital Input (Timer 1 X 0 1 ? ? X X X X CCP) Digital Input (QEI) 1 X 0 1 ? ? X X X X Digital Output (PWM) 1 X 0 1 ? ? ? ? ? ? Digital Output (Timer 1 X 0 1 ? ? ? ? ? ? PWM) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (SSI) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (UART) Analog Input 0 0 0 0 0 0 X X X X (Comparator) Digital Output 1 X 0 1 ? ? ? ? ? ? (Comparator) a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 8-2. GPIO Interrupt Configuration Example Desired Pin 2 Bit Valuea Interrupt Event Trigger Register 7 6 5 4 3 2 1 0 0=edge X X X X X 0 X X 1=level GPIOIS 286 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-2. GPIO Interrupt Configuration Example (continued) Desired Pin 2 Bit Valuea Interrupt Event Trigger Register 7 6 5 4 3 2 1 0 0=single X X X X X 0 X X edge 1=both edges GPIOIBE 0=Low level, X X X X X 1 X X or negative edge 1=High level, or positive edge GPIOIEV 0=masked 0 0 0 0 0 1 0 0 1=not masked GPIOIM a. X=Ignored (don’t care bit) 8.3 Register Map Table 8-3 on page 288 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 ■ GPIO Port B: 0x4000.5000 ■ GPIO Port C: 0x4000.6000 ■ GPIO Port D: 0x4000.7000 ■ GPIO Port E: 0x4002.4000 ■ GPIO Port F: 0x4002.5000 ■ GPIO Port G: 0x4002.6000 ■ GPIO Port H: 0x4002.7000 Note that the GPIO module clock must be enabled before the registers can be programmed (see page 225). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed. Important: The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect, and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. January 08, 2011 287 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-3. GPIO Register Map See Offset Name Type Reset Description page 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 290 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 291 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 292 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 293 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 294 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 295 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 296 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 297 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 298 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 299 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 301 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 302 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 303 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 304 0x510 GPIOPUR R/W - GPIO Pull-Up Select 305 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 306 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 307 0x51C GPIODEN R/W - GPIO Digital Enable 308 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 309 0x524 GPIOCR - - GPIO Commit 310 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 312 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 313 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 314 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 315 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 316 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 317 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 318 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 319 288 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Table 8-3. GPIO Register Map (continued) See Offset Name Type Reset Description page 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 320 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 321 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 322 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 323 8.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. January 08, 2011 289 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 291). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 283 for examples of reads and writes. 7:0 DATA R/W 0x00 290 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. 7:0 DIR R/W 0x00 January 08, 2011 291 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IS Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). 7:0 IS R/W 0x00 292 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 292) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 294). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IBE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 294). 0 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 7:0 IBE R/W 0x00 January 08, 2011 293 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 292). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IEV Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description Falling edge or Low levels on corresponding pins trigger interrupts. 0 Rising edge or High levels on corresponding pins trigger interrupts. 1 7:0 IEV R/W 0x00 294 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IME Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. 7:0 IME R/W 0x00 January 08, 2011 295 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 295). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. 7:0 RIS RO 0x00 296 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the Interrupt 0-31 Set Enable (EN0) register can disable the PortB interrupts, and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on PB4, and wait for the ADC interrupt or the ADC interrupt must be disabled in the EN0 register and the PortB interrupt handler must poll the ADC registers until the conversion is completed. See page 109 for more information. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. 7:0 MIS RO 0x00 January 08, 2011 297 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IC Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. 7:0 IC W1C 0x00 298 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is currently provided for the five JTAG/SWD pins (PB7 and PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 299) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 309) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 310) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. While debugging systems where PB7 is being used as a GPIO, care must be taken to ensure that a low value is not applied to the pin when the part is reset. Because PB7 reverts to the TRST function after reset, a Low value on the pin causes the JTAG controller to be reset, resulting in a loss of JTAG communication. Caution – It is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x420 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AFSEL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 January 08, 2011 299 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). Hardware control of corresponding GPIO line (alternate hardware function). 1 Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 AFSEL R/W - 300 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV2 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV2 R/W 0xFF January 08, 2011 301 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV4 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV4 R/W 0x00 302 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV8 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV8 R/W 0x00 January 08, 2011 303 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 308). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input, the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module, in addition to configuring the pin to open drain, the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set to 1 (see examples in “Initialization and Configuration” on page 286). GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ODE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. 7:0 ODE R/W 0x00 304 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 306). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x510 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PUE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 PUE R/W - January 08, 2011 305 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 305). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PDE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 7:0 PDE R/W 0x00 306 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 303). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SRL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. 7:0 SRL R/W 0x00 January 08, 2011 307 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x51C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 DEN R/W - 308 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 310). Writing 0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description GPIO Lock A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked 31:0 LOCK R/W 0x0000.0001 January 08, 2011 309 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSELregister bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x524 Type -, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CR Type RO RO RO RO RO RO RO RO - - - - - - - - Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 310 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. 7:0 CR - - January 08, 2011 311 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] 312 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] January 08, 2011 313 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] 314 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] January 08, 2011 315 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x61 316 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 January 08, 2011 317 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 318 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 January 08, 2011 319 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 320 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 January 08, 2011 321 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 322 January 08, 2011 Texas Instruments-Production Data General-Purpose Input/Outputs (GPIOs) Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 January 08, 2011 323 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1, Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). In addition, timers can be used to trigger analog-to-digital conversions (ADC). The ADC trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The GPT Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see 94) and the PWM timer in the PWM module (see “PWM Timer” on page 593). The General-Purpose Timers provide the following features: ■ Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently: – As a single 32-bit timer – As one 32-bit Real-Time Clock (RTC) to event capture – For Pulse Width Modulation (PWM) – To trigger analog-to-digital conversions ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock when using an external 32.768-KHz clock as the input – User-enabled stalling when the controller asserts CPU Halt flag during debug – ADC event trigger ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – User-enabled stalling when the controller asserts CPU Halt flag during debug – ADC event trigger ■ 16-bit Input Capture modes – Input edge count capture 324 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 9.1 Block Diagram Note: In Figure 9-1 on page 325, the specific CCP pins available depend on the Stellaris device. See Table 9-1 on page 325 for the available CCPs. Figure 9-1. GPTM Module Block Diagram TA Comparator TB Comparator GPTMTBR GPTMAR Clock / Edge Detect RTC Divider Clock / Edge Detect TimerA Interrupt TimerB Interrupt System Clock 0x0000 (Down Counter Modes) 0x0000 (Down Counter Modes) 32 KHz or Even CCP Pin Odd CCP Pin En En TimerA Control GPTMTAPMR GPTMTAILR GPTMTAMATCHR GPTMTAPR GPTMTAMR TimerB Control GPTMTBPMR GPTMTBILR GPTMTBMATCHR GPTMTBPR GPTMTBMR Interrupt / Config GPTMCFG GPTMRIS GPTMICR GPTMMIS GPTMIMR GPTMCTL Table 9-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 Timer 1 TimerA CCP2 - TimerB - CCP3 Timer 2 TimerA CCP4 - TimerB - CCP5 Timer 3 TimerA - - TimerB - - January 08, 2011 325 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 9.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 336), the GPTM TimerA Mode (GPTMTAMR) register (see page 337), and the GPTM TimerB Mode (GPTMTBMR) register (see page 339). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 350) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 351). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 354) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 355). 9.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 350 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 351 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 358 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 359 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 9.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 337), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. 326 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 341), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 346), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 348). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register (see page 344), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 347). The ADC trigger is enabled by setting the TAOTE bit in GPTMCTL. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. 9.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 352) by the controller. The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 336). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. January 08, 2011 327 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTMIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The ADC trigger is enabled by setting the TnOTE bit in the GPTMCTL register. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is halted by the debugger. The timer resumes counting when the processor resumes execution. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 9-2. 16-Bit Timer With Prescaler Configurations Prescale #Clock (T c)a Max Time Units 00000000 1 1.3107 mS 00000001 2 2.6214 mS 00000010 3 3.9322 mS ------------ -- -- -- 11111101 254 332.9229 mS 11111110 255 334.2336 mS 11111111 256 335.5443 mS a. Tc is the clock period. 9.2.3.2 16-Bit Input Edge Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Count mode. In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). 328 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-2 on page 329 shows how input edge count mode works. In this case, the timer start value is set to GPTMTnILR =0x000A and the match value is set to GPTMTnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMTnMATCHR register. Figure 9-2. 16-Bit Input Edge Count Mode Example Input Signal Timer stops, flags asserted Timer reload Count on next cycle Ignored Ignored 0x000A 0x0006 0x0007 0x0008 0x0009 9.2.3.3 16-Bit Input Edge Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMTnILR register. January 08, 2011 329 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 9-3 on page 330 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). Figure 9-3. 16-Bit Input Edge Time Mode Example GPTMTnR=Y Input Signal Time Count GPTMTnR=X GPTMTnR=Z Z X Y 0xFFFF 9.2.3.4 16-Bit PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. In this mode, the PWM frequency and period are synchronous events and therefore guaranteed to be glitch free. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMTnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 on page 331 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMTnIRL=0xC350 and the match value is GPTMTnMATCHR=0x411A. 330 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Figure 9-4. 16-Bit PWM Mode Example Output Signal Time Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A TnPWML = 0 TnPWML = 1 TnEN set 9.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. January 08, 2011 331 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 332. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on an even CCP input. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in the GPTMRIS register and continues counting until Timer A is disabled or a hardware reset. The interrupt is cleared by writing the RTCCINT bit in the GPTMICR register. 9.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 332 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers In One-Shot mode, the timer stops counting after step 8 on page 332. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 333 through step 9 on page 333. 9.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM January 08, 2011 333 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.4 Register Map Table 9-3 on page 334 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 ■ Timer3: 0x4003.3000 Note that the Timer module clock must be enabled before the registers can be programmed (see page 216). There must be a delay of 3 system clocks after the Timer module clock is enabled before any Timer module registers are accessed. Table 9-3. Timers Register Map See Offset Name Type Reset Description page 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 336 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 337 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 339 334 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Table 9-3. Timers Register Map (continued) See Offset Name Type Reset Description page 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 341 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 344 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 346 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 347 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 348 0x028 GPTMTAILR R/W 0xFFFF.FFFF GPTM TimerA Interval Load 350 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 351 0x030 GPTMTAMATCHR R/W 0xFFFF.FFFF GPTM TimerA Match 352 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 353 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 354 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 355 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 356 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 357 0x048 GPTMTAR RO 0xFFFF.FFFF GPTM TimerA 358 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 359 9.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. January 08, 2011 335 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPTMCFG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved 0x3 Reserved 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x4-0x7 2:0 GPTMCFG R/W 0x0 336 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAAMS TACMR TAMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. 3 TAAMS R/W 0 GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode 2 TACMR R/W 0 January 08, 2011 337 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 1:0 TAMR R/W 0x0 338 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBAMS TBCMR TBMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. 3 TBAMS R/W 0 GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode 2 TBCMR R/W 0 January 08, 2011 339 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register’s contents are ignored and GPTMTAMR is used. 1:0 TBMR R/W 0x0 340 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:15 reserved RO 0x00 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 14 TBPWML R/W 0 GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output TimerB ADC trigger is disabled. 1 The output TimerB ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 398). 13 TBOTE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 January 08, 2011 341 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 11:10 TBEVENT R/W 0x0 GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description Timer B continues counting while the processor is halted by the debugger. 0 Timer B freezes counting while the processor is halted by the debugger. 1 If the processor is executing normally, the TBSTALL bit is ignored. 9 TBSTALL R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 8 TBEN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 6 TAPWML R/W 0 GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output TimerA ADC trigger is disabled. 1 The output TimerA ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see page 398). 5 TAOTE R/W 0 342 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 0 RTC counting is disabled. 1 RTC counting is enabled. 4 RTCEN R/W 0 GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 3:2 TAEVENT R/W 0x0 GPTM Timer A Stall Enable The TASTALL values are defined as follows: Value Description Timer A continues counting while the processor is halted by the debugger. 0 Timer A freezes counting while the processor is halted by the debugger. 1 If the processor is executing normally, the TASTALL bit is ignored. 1 TASTALL R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 0 TAEN R/W 0 January 08, 2011 343 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 10 CBEIM R/W 0 GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 9 CBMIM R/W 0 GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 8 TBTOIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0 344 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 3 RTCIM R/W 0 GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 2 CAEIM R/W 0 GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 1 CAMIM R/W 0 GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 0 TATOIM R/W 0 January 08, 2011 345 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 10 CBERIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 9 CBMRIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 8 TBTORIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 3 RTCRIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 1 CAMRIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 0 TATORIS RO 0 346 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 10 CBEMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 9 CBMMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 8 TBTOMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 3 RTCMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 1 CAMMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. 0 TATOMIS RO 0 January 08, 2011 347 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 10 CBECINT W1C 0 GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 9 CBMCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 8 TBTOCINT W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 348 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 3 RTCCINT W1C 0 GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 2 CAECINT W1C 0 GPTM CaptureA Match Interrupt Clear The CAMCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 1 CAMCINT W1C 0 GPTM TimerA Time-Out Interrupt Clear The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 0 TATOCINT W1C 0 January 08, 2011 349 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAILRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 31:16 TAILRH R/W 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 15:0 TAILRL R/W 0xFFFF 350 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 15:0 TBILRL R/W 0xFFFF January 08, 2011 351 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAMRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 31:16 TAMRH R/W 0xFFFF GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 15:0 TAMRL R/W 0xFFFF 352 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 15:0 TBMRL R/W 0xFFFF January 08, 2011 353 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-2 on page 328 for more details and an example. 7:0 TAPSR R/W 0x00 354 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-2 on page 328 for more details and an example. 7:0 TBPSR R/W 0x00 January 08, 2011 355 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 7:0 TAPSMR R/W 0x00 356 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 7:0 TBPSMR R/W 0x00 January 08, 2011 357 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TARH Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TARL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 31:16 TARH RO 0xFFFF GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge-Count mode, when it returns the number of edges that have occurred. 15:0 TARL RO 0xFFFF 358 January 08, 2011 Texas Instruments-Production Data General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBRL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge-Count mode, when it returns the number of edges that have occurred. 15:0 TBRL RO 0xFFFF January 08, 2011 359 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module has the following features: ■ 32-bit down counter with a programmable load register ■ Separate watchdog clock with an enable ■ Programmable interrupt generation logic with interrupt masking ■ Lock register protection from runaway software ■ Reset generation logic with an enable/disable ■ User-enabled stalling when the controller asserts the CPU Halt flag during debug The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 360 January 08, 2011 Texas Instruments-Production Data Watchdog Timer 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR WDTRIS WDTMIS WDTLOCK WDTTEST WDTLOAD WDTVALUE Comparator 32-Bit Down Counter 0x00000000 Interrupt System Clock Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 10.2 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. January 08, 2011 361 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 10.4 Register Map Table 10-1 on page 362 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 10-1. Watchdog Timer Register Map See Offset Name Type Reset Description page 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 364 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 365 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 366 0x00C WDTICR WO - Watchdog Interrupt Clear 367 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 368 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 369 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 370 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 371 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 372 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 373 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 374 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 375 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 376 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 377 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 378 362 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Table 10-1. Watchdog Timer Register Map (continued) See Offset Name Type Reset Description page 0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 379 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 380 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 381 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 382 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 383 10.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. January 08, 2011 363 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description 31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value 364 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Watchdog Value Current value of the 32-bit down counter. 31:0 WDTValue RO 0xFFFF.FFFF January 08, 2011 365 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RESEN INTEN Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 Disabled. 1 Enable the Watchdog module reset output. 1 RESEN R/W 0 Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 1 Interrupt event enabled. Once enabled, all writes are ignored. 0 INTEN R/W 0 366 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 WDTIntClr WO - Watchdog Interrupt Clear January 08, 2011 367 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTRIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 0 WDTRIS RO 0 368 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 0 WDTMIS RO 0 January 08, 2011 369 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved STALL reserved Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:9 reserved RO 0x00 Watchdog Stall Enable When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 8 STALL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 0x00 370 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 31:0 WDTLock R/W 0x0000 January 08, 2011 371 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] 372 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] January 08, 2011 373 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] 374 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] January 08, 2011 375 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] 376 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] January 08, 2011 377 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] 378 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] January 08, 2011 379 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] 380 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] January 08, 2011 381 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] 382 January 08, 2011 Texas Instruments-Production Data Watchdog Timer Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] January 08, 2011 383 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 11 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris® ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor. The ADC module contains four programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. The Stellaris ADC module provides the following features: ■ Four analog input channels ■ Single-ended and differential-input configurations ■ On-chip internal temperature sensor ■ Sample rate of one million samples/second ■ Flexible, configurable analog-to-digital conversion ■ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy ■ Converter uses an internal 3-V reference ■ Power and ground for the analog circuitry is separate from the digital power and ground 11.1 Block Diagram Figure 11-1 on page 385 provides details on the internal configuration of the ADC controls and data registers. 384 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-1. ADC Module Block Diagram Analog-to-Digital Converter ADCSSFSTAT0 ADCSSCTL0 ADCSSMUX0 Sample Sequencer 0 ADCSSFSTAT1 ADCSSCTL1 ADCSSMUX1 Sample Sequencer 1 ADCSSFSTAT2 ADCSSCTL2 ADCSSMUX2 Sample Sequencer 2 ADCSSFSTAT3 ADCSSCTL3 ADCSSMUX3 Sample Sequencer 3 ADCUSTAT ADCOSTAT ADCACTSS Control/Status ADCSSPRI ADCISC ADCRIS ADCIM Interrupt Control Analog Inputs SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt ADCEMUX ADCPSSI Trigger Events SS0 SS1 SS2 SS3 Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM ADCSSFIFO0 ADCSSFIFO1 ADCSSFIFO2 ADCSSFIFO3 FIFO Block Hardware Averager ADCSAC 11.2 Functional Description The Stellaris ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approaches found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the controller. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. 11.2.1 Sample Sequencers The sampling control and data capture is handled by the sample sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 11-1 on page 385 shows the maximum number of samples that each sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 11-1. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 1 1 SS2 4 4 SS1 4 4 SS0 8 8 For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn January 08, 2011 385 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, and should be configured before being enabled. When configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. In the ADCSSCTLn register, the IEn bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 11.2.2 Module Control Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: ■ Interrupt generation ■ Sequence prioritization ■ Trigger configuration Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock divider configuration targets 16.667 MHz operation for all Stellaris devices. 11.2.2.1 Interrupts The register configurations of the sample sequencers dictate which events generate raw interrupts, but do not have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of the various interrupt signals, and the ADC Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by the ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. 11.2.2.2 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 386 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) 11.2.2.3 Sampling Events Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select (ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member, but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. Care must be taken when using the "Always" trigger. If a sequence's priority is too high, it is possible to starve other lower priority sequences. 11.2.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 406). There is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or differential. 11.2.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. An internal 3 V reference is used by the converter resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended input mode. 11.2.5 Differential Sampling In addition to traditional single-ended sampling, the ADC module supports differential sampling of two analog input channels. To enable differential sampling, software must set the Dn bit in the ADCSSCTL0n register in a step's configuration nibble. When a sequence step is configured for differential sampling, its corresponding value in the ADCSSMUXn register must be set to one of the four differential pairs, numbered 0-3. Differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see Table 11-2 on page 387). The ADC does not support other differential pairings such as analog input 0 with analog input 3. The number of differential pairs supported is dependent on the number of analog inputs (see Table 11-2 on page 387). Table 11-2. Differential Sampling Pairs Differential Pair Analog Inputs 0 0 and 1 1 2 and 3 The voltage sampled in differential mode is the difference between the odd and even channels: ΔV (differential voltage) = VIN_EVEN (even channels) – VIN_ODD (odd channels), therefore: ■ If ΔV = 0, then the conversion result = 0x1FF ■ If ΔV > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF) January 08, 2011 387 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller ■ If ΔV < 0, then the conversion result < 0x1FF (range is 0–0x1FF) The differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. In order for a valid conversion result to appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 V or 0 V, respectively, to the ADC. Figure 11-2 on page 388 shows an example of the negative input centered at 1.5 V. In this configuration, the differential range spans from -1.5 V to 1.5 V. Figure 11-3 on page 389 shows an example where the negative input is centered at -0.75 V, meaning inputs on the positive input saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure 11-4 on page 389 shows an example of the negative input centered at 2.25 V, where inputs on the positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater than 3 V. Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V 0 V 1.5 V 3.0 V -1.5 V 0 V 1.5 V VIN_EVEN DV VIN_ODD = 1.5 V 0x3FF 0x1FF ADC Conversion Result - Input Saturation 388 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V ADC Conversion Result 0x3FF 0x1FF 0x0FF 0 V +0.75 V +2.25 V VIN_EVEN -1.5 V -0.75 V +1.5 V DV - Input Saturation Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V ADC Conversion Result 0x3FF 0x2FF 0x1FF 0.75 V 2.25 V 3.0 V VIN_EVEN -1.5 V 0.75 V 1.5 V DV - Input Saturation 11.2.6 Test Modes There is a user-available test mode that allows for loopback operation within the digital portion of the ADC module. This can be useful for debugging software without having to provide actual analog stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see page 419). January 08, 2011 389 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 11.2.7 Internal Temperature Sensor The temperature sensor serves two primary purposes: 1) to notify the system that internal temperature is too high or low for reliable operation, and 2) to provide temperature measurements for calibration of the Hibernate module RTC trim value. The temperature sensor does not have a separate enable, since it also contains the bandgap reference and must always be enabled. The reference is supplied to other analog modules; not just the ADC. The internal temperature sensor provides an analog temperature reading as well as a reference voltage. The voltage at the output terminal SENSO is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 11-5 on page 390. Figure 11-5. Internal Temperature Sensor Characteristic 11.3 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 11.3.1 Module Initialization Initialization of the ADC module is a simple process with very few steps. The main steps include enabling the clock to the ADC and reconfiguring the sample sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC0 register (see page 210). 2. If required by the application, reconfigure the sample sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority. 390 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) 11.3.2 Sample Sequencer Configuration Configuration of the sample sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. The configuration for each sample sequencer should be as follows: 1. Ensure that the sample sequencer is disabled by writing a 0 to the corresponding ASENn bit in the ADCACTSS register. Programming of the sample sequencers is allowed without having them enabled. Disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the sample sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6. Enable the sample sequencer logic by writing a 1 to the corresponding ASENn bit in the ADCACTSS register. 11.4 Register Map Table 11-3 on page 391 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s address, relative to the ADC base address of 0x4003.8000. Note that the ADC module clock must be enabled before the registers can be programmed (see page 210). There must be a delay of 3 system clocks after the ADC module clock is enabled before any ADC module registers are accessed. Table 11-3. ADC Register Map See Offset Name Type Reset Description page 0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 393 0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 394 0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 395 0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 396 0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 397 0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 398 0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 402 0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 403 0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 405 0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 406 January 08, 2011 391 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Table 11-3. ADC Register Map (continued) See Offset Name Type Reset Description page 0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 407 0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 409 0x048 ADCSSFIFO0 RO - ADC Sample Sequence Result FIFO 0 412 0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 413 0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 414 0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 415 0x068 ADCSSFIFO1 RO - ADC Sample Sequence Result FIFO 1 412 0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 413 0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 414 0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 415 0x088 ADCSSFIFO2 RO - ADC Sample Sequence Result FIFO 2 412 0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 413 0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 417 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 418 0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 412 0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 413 0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 419 11.5 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. 392 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ASEN3 ASEN2 ASEN1 ASEN0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x0000.000 ADC SS3 Enable Specifies whether Sample Sequencer 3 is enabled. If set, the sample sequence logic for Sequencer 3 is active. Otherwise, the sequencer is inactive. 3 ASEN3 R/W 0 ADC SS2 Enable Specifies whether Sample Sequencer 2 is enabled. If set, the sample sequence logic for Sequencer 2 is active. Otherwise, the sequencer is inactive. 2 ASEN2 R/W 0 ADC SS1 Enable Specifies whether Sample Sequencer 1 is enabled. If set, the sample sequence logic for Sequencer 1 is active. Otherwise, the sequencer is inactive. 1 ASEN1 R/W 0 ADC SS0 Enable Specifies whether Sample Sequencer 0 is enabled. If set, the sample sequence logic for Sequencer 0 is active. Otherwise, the sequencer is inactive. 0 ASEN0 R/W 0 January 08, 2011 393 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INR3 INR2 INR1 INR0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000 SS3 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL3 IE bit has completed conversion. This bit is cleared by setting the IN3 bit in the ADCISC register. 3 INR3 RO 0 SS2 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL2 IE bit has completed conversion. This bit is cleared by setting the IN2 bit in the ADCISC register. 2 INR2 RO 0 SS1 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL1 IE bit has completed conversion. This bit is cleared by setting the IN1 bit in the ADCISC register. 1 INR1 RO 0 SS0 Raw Interrupt Status This bit is set by hardware when a sample with its respective ADCSSCTL0 IE bit has completed conversion. This bit is cleared by setting the IN30 bit in the ADCISC register. 0 INR0 RO 0 394 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the sample sequencer raw interrupt signals are promoted to controller interrupts. Each raw interrupt signal can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MASK3 MASK2 MASK1 MASK0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000 SS3 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 3 does not affect the SS3 interrupt status. 3 MASK3 R/W 0 SS2 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 2 does not affect the SS2 interrupt status. 2 MASK2 R/W 0 SS1 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 1 does not affect the SS1 interrupt status. 1 MASK1 R/W 0 SS0 Interrupt Mask When set, this bit allows the raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) to be promoted to a controller interrupt. When clear, the status of Sample Sequencer 0 does not affect the SS0 interrupt status. 0 MASK0 R/W 0 January 08, 2011 395 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing sample sequence interrupt conditions and shows the status of controller interrupts generated by the sample sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Sample sequence nterrupts are cleared by setting the corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the sample sequence INR bits are still cleared via the ADCISC register, even if the IN bit is not set. ADC Interrupt Status and Clear (ADCISC) Base 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IN3 IN2 IN1 IN0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000 SS3 Interrupt Status and Clear This bit is set when both the INR3 bit in the ADCRIS register and the MASK3 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR3 bit. 3 IN3 R/W1C 0 SS2 Interrupt Status and Clear This bit is set when both the INR2 bit in the ADCRIS register and the MASK2 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR2 bit. 2 IN2 R/W1C 0 SS1 Interrupt Status and Clear This bit is set when both the INR1 bit in the ADCRIS register and the MASK1 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR1 bit. 1 IN1 R/W1C 0 SS0 Interrupt Status and Clear This bit is set when both the INR0 bit in the ADCRIS register and the MASK0 bit in the ADCIM register are set, providing a level-based interrupt to the controller. This bit is cleared by writing a 1. Clearing this bit also clears the INR0 bit. 0 IN0 R/W1C 0 396 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OV3 OV2 OV1 OV0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x0000.000 SS3 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 3 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 3 OV3 R/W1C 0 SS2 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 2 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 2 OV2 R/W1C 0 SS1 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 1 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS0 FIFO Overflow When set, this bit specifies that the FIFO for Sample Sequencer 0 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped. This bit is cleared by writing a 1. 0 OV0 R/W1C 0 January 08, 2011 397 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM3 EM2 EM1 EM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0 SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 341). 0x5 PWM0 The PWM module 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register, see page 611. 0x6 PWM1 The PWM module 1 trigger can be configured with the PWM1INTEN register, see page 611. 0x7 PWM2 The PWM module 2 trigger can be configured with the PWM2INTEN register, see page 611. 0x8 0x9-0xE reserved 0xF Always (continuously sample) 15:12 EM3 R/W 0x0 398 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 341). 0x5 PWM0 The PWM module 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register, see page 611. 0x6 PWM1 The PWM module 1 trigger can be configured with the PWM1INTEN register, see page 611. 0x7 PWM2 The PWM module 2 trigger can be configured with the PWM2INTEN register, see page 611. 0x8 0x9-0xE reserved 0xF Always (continuously sample) 11:8 EM2 R/W 0x0 January 08, 2011 399 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 341). 0x5 PWM0 The PWM module 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register, see page 611. 0x6 PWM1 The PWM module 1 trigger can be configured with the PWM1INTEN register, see page 611. 0x7 PWM2 The PWM module 2 trigger can be configured with the PWM2INTEN register, see page 611. 0x8 0x9-0xE reserved 0xF Always (continuously sample) 7:4 EM1 R/W 0x0 400 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 341). 0x5 PWM0 The PWM module 0 trigger can be configured with the PWM0 Interrupt and Trigger Enable (PWM0INTEN) register, see page 611. 0x6 PWM1 The PWM module 1 trigger can be configured with the PWM1INTEN register, see page 611. 0x7 PWM2 The PWM module 2 trigger can be configured with the PWM2INTEN register, see page 611. 0x8 0x9-0xE reserved 0xF Always (continuously sample) 3:0 EM0 R/W 0x0 January 08, 2011 401 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved UV3 UV2 UV1 UV0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x0000.000 SS3 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 3 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 3 UV3 R/W1C 0 SS2 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 2 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 2 UV2 R/W1C 0 SS1 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 1 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS0 FIFO Underflow When set, this bit specifies that the FIFO for Sample Sequencer 0 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 402 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for the ADC to operate properly. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS3 reserved SS2 reserved SS1 reserved SS0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x0000.0 SS3 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 13:12 SS3 R/W 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0x0 SS2 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 9:8 SS2 R/W 0x2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0x0 SS1 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 5:4 SS1 R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 January 08, 2011 403 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description SS0 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal. 1:0 SS0 R/W 0x0 404 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.8000 Offset 0x028 Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS3 SS2 SS1 SS0 Type RO RO RO RO RO RO RO RO RO RO RO RO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0 SS3 Initiate When set, this bit triggers sampling on Sample Sequencer 3 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 3 SS3 WO - SS2 Initiate When set, this bit triggers sampling on Sample Sequencer 2 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 2 SS2 WO - SS1 Initiate When set, this bit triggers sampling on Sample Sequencer 1 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 1 SS1 WO - SS0 Initiate When set, this bit triggers sampling on Sample Sequencer 0 if the sequencer is enabled in the ADCACTSS register. Only a write by software is valid; a read of this register returns no meaningful data. 0 SS0 WO - January 08, 2011 405 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG = 7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) Base 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AVG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x0000.000 Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 No hardware oversampling 0x1 2x hardware oversampling 0x2 4x hardware oversampling 0x3 8x hardware oversampling 0x4 16x hardware oversampling 0x5 32x hardware oversampling 0x6 64x hardware oversampling 0x7 Reserved 2:0 AVG R/W 0x0 406 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:30 reserved RO 0 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 1 indicates the input is ADC1. 29:28 MUX7 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:26 reserved RO 0 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 25:24 MUX6 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:22 reserved RO 0 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 21:20 MUX5 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:18 reserved RO 0 January 08, 2011 407 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 17:16 MUX4 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:14 reserved RO 0 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 13:12 MUX3 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 3rd Sample Input Select The MUX72 field is used during the third sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 9:8 MUX2 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 5:4 MUX1 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 1:0 MUX0 R/W 0x0 408 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with a sample sequencer. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) Base 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description 8th Sample Temp Sensor Select This bit is used during the eighth sample of the sample sequence and and specifies the input source of the sample. When set, the temperature sensor is read. When clear, the input pin specified by the ADCSSMUX register is read. 31 TS7 R/W 0 8th Sample Interrupt Enable This bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal (INR0 bit) is asserted at the end of the sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to a controller-level interrupt. When this bit is set, the raw interrupt is asserted. When this bit is clear, the raw interrupt is not asserted. It is legal to have multiple samples within a sequence generate interrupts. 30 IE7 R/W 0 8th Sample is End of Sequence The END7 bit indicates that this is the last sample of the sequence. It is possible to end the sequence on any sample position. Samples defined after the sample containing a set END are not requested for conversion even though the fields may be non-zero. It is required that software write the END bit somewhere within the sequence. (Sample Sequencer 3, which only has a single sample in the sequence, is hardwired to have the END0 bit set.) Setting this bit indicates that this sample is the last in the sequence. 29 END7 R/W 0 8th Sample Diff Input Select The D7 bit indicates that the analog input is to be differentially sampled. The corresponding ADCSSMUXx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". The temperature sensor does not have a differential option. When set, the analog inputs are differentially sampled. 28 D7 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 27 TS6 R/W 0 January 08, 2011 409 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 26 IE6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 25 END6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 24 D6 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 23 TS5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 21 END5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 20 D5 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 19 TS4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 17 END4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 16 D4 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 13 END3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 12 D3 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 11 TS2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 9 END2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 8 D2 R/W 0 410 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 7 TS1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 5 END1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 4 D1 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 1 END0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 January 08, 2011 411 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 Important: Use caution when reading this register. Performing a read may change bit status. This register contains the conversion results for samples collected with the sample sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0) Base 0x4003.8000 Offset 0x048 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO - 9:0 DATA RO - Conversion Result Data 412 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the sample sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO. The ADCSSFSTAT0 register provides status on FIFO0, ADCSSFSTAT1 on FIFO1, ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) Base 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FULL reserved EMPTY HPTR TPTR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:13 reserved RO 0x0 FIFO Full When set, this bit indicates that the FIFO is currently full. 12 FULL RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0x0 FIFO Empty When set, this bit indicates that the FIFO is currently empty. 8 EMPTY RO 1 FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. 7:4 HPTR RO 0x0 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. 3:0 TPTR RO 0x0 January 08, 2011 413 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 407 for detailed bit descriptions. The ADCSSMUX1 register affects Sample Sequencer 1 and the ADCSSMUX2 register affects Sample Sequencer 2. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) Base 0x4003.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x0000 13:12 MUX3 R/W 0x0 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 9:8 MUX2 R/W 0x0 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 5:4 MUX1 R/W 0x0 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 1:0 MUX0 R/W 0x0 1st Sample Input Select 414 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSCTL0 register on page 409 for detailed bit descriptions. The ADCSSCTL1 register configures Sample Sequencer 1 and the ADCSSCTL2 register configures Sample Sequencer 2. ADC Sample Sequence Control 1 (ADCSSCTL1) Base 0x4003.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 13 END3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 12 D3 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 11 TS2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 9 END2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 8 D2 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 7 TS1 R/W 0 January 08, 2011 415 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Bit/Field Name Type Reset Description 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 5 END1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 4 D1 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. 1 END0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 416 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for a sample executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 407 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0000.000 1:0 MUX0 R/W 0 1st Sample Input Select January 08, 2011 417 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for a sample executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 409 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) Base 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TS0 IE0 END0 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x0000.000 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 1 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 418 January 08, 2011 Texas Instruments-Production Data Analog-to-Digital Converter (ADC) Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned. ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LB Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x0000.000 Loopback Mode Enable When set, forces a loopback within the digital block to provide information on input and unique numbering. The ADCSSFIFOn registers do not provide sample data, but instead provide the 10-bit loopback data as shown below. Bit/Field Name Description Continuous Sample Counter Continuous sample counter that is initialized to 0 and counts each sample as it processed. This helps provide a unique value for the data received. 9:6 CNT Continuation Sample Indicator When set, indicates that this is a continuation sample. For example, if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 5 CONT Differential Sample Indicator When set, indicates that this is a differential sample. 4 DIFF Temp Sensor Sample Indicator When set, indicates that this is a temperature sensor sample. 3 TS Analog Input Indicator Indicates which analog input is to be sampled. 2:0 MUX 0 LB R/W 0 January 08, 2011 419 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller 12 Universal Asynchronous Receivers/Transmitters (UARTs) Each Stellaris® Universal Asynchronous Receiver/Transmitter (UART) has the following features: ■ Three fully programmable 16C550-type UARTs with IrDA support ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable baud-rate generator allowing speeds up to 3.125 Mbps ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Standard asynchronous communication bits for start, stop, and parity ■ Line-break generation and detection ■ Fully programmable serial interface characteristics – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration 420 January 08, 2011 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 12.1 Block Diagram Figure 12-1. UART Module Block Diagram TxFIFO 16 x 8 ... RxFIFO 16 x 8 ... Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 Interrupt Control UARTDR Control/Status Transmitter (with SIR Transmit Baud Rate Encoder) Generator Receiver (with SIR Receive Decoder) UnTx UnRx System Clock Interrupt UARTIFLS UARTIM UARTMIS UARTRIS UARTICR UARTIBRD UARTFBRD UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR 12.2 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 439). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 12.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data January 08, 2011 421 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 12-2 on page 422 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 12-2. UART Character Frame 1 0 5-8 data bits LSB MSB Parity bit if enabled 1-2 stop bits UnTX n Start 12.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 435) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 436). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 437), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 422 January 08, 2011 Texas Instruments-Production Data Universal Asynchronous Receivers/Transmitters (UARTs) 12.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 432) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 421). The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 12.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 434 for more information on IrDA low-power pulse-duration configuration. Figure 12-3 on page 424 shows the UART transmit and receive signals, with and without IrDA modulation. January 08, 2011 423 Texas Instruments-Production Data Stellaris® LM3S2965 Microcontroller Figure 12-3. IrDA Data Modulation 0 1 0 1 0 0 1 1 0 1 Data bits 0 1 0 1 0 0 1 1 0 1 Start Data bits bit Start Stop Bit period 3 Bit period 16 UnTx UnTx with IrDA UnRx with IrDA UnRx Stop bit In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. If the application does not require the use of the UnRx signal, the GPIO pin that has the UnRx signal as an alternate function must be configured as the UnRx signal and pulled High. 12.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 428). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 437). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 432) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 441). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive