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STM32F103x8 STM32F103xB - Farnell Element 14
STM32F103x8 STM32F103xB - Farnell Element 14
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Farnell Element 14 :
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See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
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This is information on a product in full production.
August 2013 DocID13587 Rev 16 1/105
STM32F103x8
STM32F103xB
Medium-density performance line ARM-based 32-bit MCU with 64
or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces
Datasheet - production data
Features
ARM 32-bit Cortex™-M3 CPU Core
– 72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
– Single-cycle multiplication and hardware
division
Memories
– 64 or 128 Kbytes of Flash memory
– 20 Kbytes of SRAM
Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR, and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
2 x 12-bit, 1 μs A/D converters (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Dual-sample and hold capability
– Temperature sensor
DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
Up to 80 fast I/O ports
– 26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Debug mode
– Serial wire debug (SWD) & JTAG
interfaces
7 timers
– Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– 16-bit, motor control PWM timer with deadtime
generation and emergency stop
– 2 watchdog timers (Independent and
Window)
– SysTick timer 24-bit downcounter
Up to 9 communication interfaces
– Up to 2 x I2C interfaces (SMBus/PMBus)
– Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– Up to 2 SPIs (18 Mbit/s)
– CAN interface (2.0B Active)
– USB 2.0 full-speed interface
CRC calculation unit, 96-bit unique ID
Packages are ECOPACK®
Table 1. Device summary
Reference Part number
STM32F103x8 STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103xB STM32F103RB STM32F103VB,
STM32F103CB, STM32F103TB
BGA100 10 × 10 mm
UFBGA100 7 x 7 mm
BGA64 5 × 5 mm
VFQFPN36 6 × 6 mm
LQFP100 14 × 14 mm
LQFP64 10 × 10 mm
LQFP48 7 × 7 mm
UFQFPN48 7 × 7 mm
www.st.com
2012-2013
Dremel Experts: US: 1 (800) 437-3635 Canada: 1 (888) 285-3476 www.dremel.com
The M akers o f Scan this code with your phone for
product information, videos, and more.
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ROTARY TOOLS
Corded.. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Cordless.. . . . . . . . . . . . . . . . . . . . . . . 13-20
At tachments.. . . . . . . . . . . . . . . . . 21-26
Accessories.. . . . . . . . . . . . . . . . . . 27-42
OSCILLATING TOOLS
Mul t i-Max™ Corded.. . . . . . 43-48
Mul t i-Max™ Cordless.. . . . 49-50
Accessories.. . . . . . . . . . . . . . . . . . 51-54
At tachments.. . . . . . . . . . . . . . . . . . . . . 54
SPECIALTY TOOLS
Saw-Max™ System. . . . . . . . 55-60
Trio™ System.. . . . . . . . . . . . . . . . 61-66
VersaTip™ and
Accessories.. . . . . . . . . . . . . . . . . . . . . . 67
Engraver and
Accessories.. . . . . . . . . . . . . . . . . . . . . . 67
V ersatile Tool Systems™
INDEX
Customer
Support
A well-prepared staff of
Dremel Experts is available to
answer questions about our tools.
With over 650 total years of
combined work experience, the
Dremel Experts are ready to serve
you. Call:
1-800-4-DREMEL
(1-800-437-3635) USA.
1-888-285-3476 CANADA.
Cal l for Your
Free Dremel DVD
1(800) 437-3635
1
The Makers of Versatile
Tool Systems™
ROTARY TOOLS
2
What Is a Rotary Tool ?
Rotary tools are hand held power tools that use high-speed
and low torque to undertake a variety of useful tasks with
control and precision. Since AJ Dremel invented the first
rotary tool over 80 years ago, no other brand has worked
harder to bring users a more complete and innovative
system of rotary tools, accessories and attachments.
Over the years Dremel rotary tools have become the gold
standard in versatility, performance, and quality by which
all other rotary tools are judged.
3
4200, 4000,
8220
3000, 8100
ROTARY TOOL OVERVIEW CORDED
VERSATILITY METER
Model 4200 4000 3000 200
SERIES
100
SERIES
Amps 1.6 1.6 1.2 1.15 1.15
Speed Range
[RPM]
5,000—
35,000
5,000—
35,000
5,000—
32,000
15,000 and
35,000 35,000
Versatility Level High High Intermediate Basic + Basic
Electronic
Feedback Control Yes Yes No No No
Number of
Speeds Variable Variable Variable 2 1
Soft Grip Yes Yes Yes No No
Separate On/Off
Speed Control Yes Yes No No No
Accessory
Change System EZ Change™
EZ Twist™
Nose Cap
EZ Twist™
Nose Cap Wrench Wrench
Weight [oz.] 25 22.5 20.0 18.0 18.0
Warranty 2 year 2 year 2 year 2 year 2 year
High Intermediate
Models: Models:
Premium Rotary Tools, able t o
perform the wide st range o f
applications.
High Performance Rotary Tools,
able to tackle a wider r ange of
applications.
4
200 SERIES,
STYLUS, 7700
100 SERIES,
7300
ROTARY TOOL OVERVIEW CORDLESS
Model 8220 8100 STYLUS™ 7700 7300
Voltage 12Vmax 8Vmax 7.2 7.2 4.8
Battery
Type
Lithium
Ion
Lithium
Ion
Lithium
Ion Ni-Cd Ni-Cd
Speed Range
[RPM]
5,000—
30,000
5,000—
30,000
5,000—
25,000
10,000 and
20,000
6,500 and
13,000
Versatility Level High Intermediate Basic + Basic + Basic
Electronic
Feedback Control No No No No No
Number of
Speeds Variable Variable Variable 2 2
Soft Grip Yes Yes Yes No No
Separate On/Off
Speed Control Yes Yes Yes No No
Accessory
Change System
EZ Twist™
Nose Cap
EZ Twist™
Nose Cap Wrench Wrench Wrench
Weight [oz.] 22.0 14.0 9.0 12.0 9.0
Warranty 2 year 2 year 2 year 2 year 2 year
Basic + Basic
Models: Models:
Enhanced Level Rotary Tools,
with improved control across
multiple applications.
Entry Level Rotary Tools,
ideal for precision applications.
5
1 2 3
NEW!
PULL INSERT SECURE
Integrated EZ Change™
For the fastest and easiest
accessory change.
Patented pull
lever system
Means you'll never need to
look for the wrench again.
Variable Speed
For maximum accessory
versatility and precise
tool control.
Electronic Feedback
Auto adjusts power and
speed as needed.
Can be used with all
Dremel accessories
and attachments
except MS400 and
PL400 attachments.*
High-Performance Motor
For maximum
performance at
all speeds.
Separate On/Off Switch
Retains speed setting for
ease of use.
Increased power
and air flow
For cooler operation.
Limited
Warranty
CORDED ROTARY TOOLS
Versatility
* Attachment models 225, 575 and 670 are compatible
with the 4200 when used with the 4200 Attachment
Adapter found in your Dremel 4200 kit.
6
EZC480 EZC481 EZC482 EZC483
• 4200 High Performance Rotary Tool, Circle
Cutter, Safety Shield, Cutting Guide, Lawn
Mower Sharpener, Lawn Mower and Garden
Tool Sharpener, Sanding/Grinding Guide,
Detailers Grip
• Storage Case, Accessory Case, Product
Reference Sheet, Adapter/Drive Coupling
40 ASSORTED ACCESSORIES
Carving/Engraving - 107, 191
Grinding/Sharpening - 932, 8193, 84922
Cutting - EZ409, EZ456, 561
Cleaning/Polishing - 403, 428
Sanding - EZ407, 408 (x6), EZ411 (x3) EZ412 (x3), EZ413 (x3), 432 (x6), 445 (x6)
Miscellaneous - 150, EZ402
4200 KIT 4200 - 6/40
The following 4200-specific collets
are available for purchase. Call
1-800-4-DREMEL for more information.
2615001034 – EZC480
2615001035 – EZC481
2615001036 – EZC482
2615001037 – EZC483
1/8" 3/32" 1/16" 1/32"
3,2 mm 2,4 mm 1,6 mm 0,8 mm
4200 COLLETS
7
Electronic Feedback
Auto adjusts power and
speed as needed.
EZ Twist™
Nose Cap Wrench for fast
accessory changes.
Variable Speed
For maximum accessory
versatility and precise
tool control.
Can be used with all
Dremel accessories
and attachments.
Does it All, Better.™
Limited
Warranty Versatility
CORDED ROTARY TOOLS
High-Performance Motor
For maximum
performance at
all speeds.
Separate On/Off Switch
Retains speed setting for
ease of use.
360º Grip Zone
With soft grip for comfort
and control.
Quick Collet Lock
For fast accessory
changes.
Integrated nose cap
wrench for fast
accessory changes.
8
• 4000 High Performance Rotary Tool, Planer, Flex
Shaft, Circle Cutter, Sanding/Grinding Guide,
Cutting Guide, Detail Nose Piece, Lawn Mower
and Garden Tool Sharpener
• Storage Case, Accessory Case,
Product Reference Sheet, Wrench, 1/8" Collet
• 4000 High Performance Rotary Tool, Detailer’s
Grip, Sanding/Grinding Guide, Cutting Guide,
Circle Cutter
• Storage Case, Accessory Case,
Product Reference Sheet, Wrench, 1/8" Collet
• 4000 High Performance Rotary Tool, Sanding/
Grinding Guide, Circle Cutter
• Storage Case, Accessory Case,
Product Reference Sheet, Wrench, 1/8" Collet
Carving/Engraving - 107, 191, 194
Grinding/Sharpening - 541, 932, 8193, 84922
Cutting - 420 (x4), 540, 561, EZ409, EZ456 (x2), EZ476 (x2)
Cleaning/Polishing - 405, 414 (x3), 421, 428, 429, 442, EZ423
Sanding - 407, 408 (x2), 411 (x2), 412 (x2), 413 (x2), 432 (x2), 445 (x2), EZ511, EZ512
Miscellaneous - 150, 401, 402, 481, EZ402
50 ASSORTED ACCESSORIES
Carving/Engraving - 107, 191
Grinding/Sharpening - 932, 8193, 84922, 85602
Cutting - 420 (x2), 540, 561, EZ456
Cleaning/Polishing - 403, 414 (x3), 421, 428, 429 (x2), 802
Sanding - 407, 408, 411 (x2), 412, 413, 432 (x3), 445 (x2)
Miscellaneous - 401, 402, 481, EZ402
34 ASSORTED ACCESSORIES
Carving/Engraving - 191
Grinding/Sharpening - 541, 932, 84922
Cutting - 420 (x2), 426 (x2), 561
Cleaning/Polishing - 403, 414, 421, 428, 429
Sanding - 407, 408 (x3), 411 (x3), 412 (x2), 413 (x2), 432 (x2), 445 (x2)
Miscellaneous - 401, 402
30 ASSORTED ACCESSORIES
4000 KIT 4000 - 6/50
4000 KIT 4000 - 4/34
4000 KIT 4000 - 2/30
9
Versatility
Does it Better.™
CORDED ROTARY TOOLS
Limited
Warranty
EZ Twist™
Nose Cap Wrench for fast
accessory changes.
Variable Speed
For maximum accessory
versatility and precise
tool control.
Sealed Ball
Bearing Motor
Runs cool for comfort
and longer tool life.
Can be used with all
Dremel accessories
and attachments
except MS400 and
PL400 attachments.
Separate On/Off Switch
Retains speed setting
for ease of use.
Double hull construction
Eliminates direct heat
transfer to hand.
10
• 3000 Series Variable Speed Rotary Tool,
Sanding/Grinding Guide
• Storage Case, Accessory Case,
Product Reference Sheet
• Wrench, 1/8" Collet
• 3000 Series Variable Speed Rotary Tool,
Cutting Guide
• Storage Case, Accessory Case, Product
Reference Sheet
• Wrench, 1/8" Collet
Carving/Engraving - 191
Grinding/Sharpening - 932, 952, 85422
Cutting - 426 (x2)
Cleaning/Polishing - 403, 414 (x2), 421, 428, 429
Sanding - 407, 408, 430, 432 (x2), 438, 445 (x2), 446
Miscellaneous - 401, 402, 415
24 ASSORTED ACCESSORIES
Carving/Engraving - 107, 191, 7144
Grinding/Sharpening - 932, 952, 953, 84922
Cutting - 426 (x2), 560, 561
Cleaning/Polishing - 403, 404, 405, 414 (x2), 421, 428, 429 (x2)
Sanding - 407, 408 (x2), 432 (x2), 445 (x2)
Miscellaneous - 150, 401, 402, 415
31 ASSORTED ACCESSORIES
3000 KIT 3000 - 1/24
3000 KIT 3000 - 1/31
11
Versatility
Limited
Warranty
Two Speed control
For application versatility and control.
Sealed Ball Bearing Motor
For cool running and longer tool life.
• Two-Speed Rotary Tool, Lawn
Mower and Garden
Tool Sharpener
• Corrugated Storage Case,
Product Reference Sheet
• Wrench, 1/8" Collet
Carving/Engraving - 194
Grinding/Sharpening - 932, 8193, 83322
Cutting - 420, 426
Cleaning/Polishing - 421, 422, 425, 429
Sanding - 407, 408, 432
Miscellaneous - 401, 402
15 ASSORTED ACCESSORIES
• Two-Speed Rotary Tool, Cutting Guide
• Corrugated Storage Case,
Product Reference Sheet
• Wrench, 1/8" Collet
CORDED ROTARY TOOLS
200 SERIES KIT 200 - 1/15
200 SERIES KIT 200 - 1/21
Carving/Engraving - 194
Grinding/Sharpening - 932, 8193, 83142, 84922
Cutting - 420, 426, 561
Cleaning/Polishing - 414 (x2), 421, 422, 425 (x2), 429 (x2)
Sanding - 407, 432, 445
Miscellaneous - 401, 402, 415
21 ASSORTED ACCESSORIES
12
Single Speed control
For fulltime 35,000 rpm operation.
Sealed Ball Bearing Motor
For cool running and longer tool life.
Limited
Warranty
Ideal for sanding, carving
and drilling.
• Single-Speed Rotary Tool
• Product Reference Sheet
• Wrench, 1/8" Collet
100 SERIES KIT 100 - N/7
Versatility
Grinding/Sharpening - 932, 84922
Cutting - 420
Sanding - 407, 432
Miscellaneous - 402, 415
7 ASSORTED ACCESSORIES
13
Limited
Warranty
CORDLESS ROTARY TOOLS
Does it All, Unplugged.™
Next Generation 12V Max
For maximum performance
and run time.
Removable
Lithium-Ion Battery
Always ready with no
memory effects.
EZ Twist™
Nose Cap Wrench for fast
accessory changes.
Variable Speed
For maximum accessory
versatility and precise
tool control.
Versatility
High-Performance Motor
For maximum
performance at all speeds.
Can be used with all
Dremel accessories
and attachments.
Separate On/Off Switch
Retains speed setting for
ease of use.
360º Grip Zone
With soft grip for comfort
and control.
NEW!
NEW!
LITHIUM-ION TECHNOLOGY
• More power in a smaller size
• Always ready – holds charge up to 2 years
• No memory effects – charge any time
* When compared to 8200 while cutting screws
14
B812-01 876
12VMAX Lithium-Ion
Battery Pack
12VMAX 1-Hour
Lithium-Ion
Battery Charger
• 8220 Cordless 12VMAX High Performance
Rotary Tool, Cutting Guide
• 1-Hour Battery Charger,
12VMAX Lithium-Ion Battery Pack (1)
• Storage Case, Accessory Case,
Product Reference Sheet
• Wrench, 1/8" Collet
Grinding/Sharpening - 541, 8193
Cutting - 426, 561
Cleaning/Polishing - 414 (X4), 421, 425 (X4), 429 (X4)
Sanding - 407, 408 (X2), 432 (X3), 445 (X3)
Miscellaneous - 401, 402,
28 ASSORTED ACCESSORIES
• 8220 Cordless 12VMAX High Performance
Rotary Tool, Shield, Cutting Guide
• 1-Hour Battery Charger,
12VMAX Lithium-Ion Battery Packs (2)
• Storage Case, Accessory Case,
Product Reference Sheet
• Wrench, 1/8" Collet
Grinding/Sharpening - 541, 8193
Cutting - 561, 426, EZ456
Cleaning/Polishing - 414 (X3), 421, 425 (x4), 429 (x3)
Sanding - 407, 408 (X2), 432 (X3), 445 (X3)
Miscellaneous - 401, 402, EZ402
28 ASSORTED ACCESSORIES
Includes
2 batteries
8220 KIT 8220 - 1/28
8220 KIT 8220 - 2/28
CORDLESS 12VMAX ROTARY TOOL ACCESSORIES
15
Limited
Warranty
Versatility
CORDLESS ROTARY TOOLS
NEW!
EZ Twist™
Nose Cap Wrench for fast accessory changes.
Variable Speed
For maximum accessory versatility and precise
tool control.
8V Max Lithium-ion
For power in a smaller size, always ready
and no memory effects.
Can be used with all Dremel accessories
and attachments except MS400 and PL400
attachments.
Separate On/Off Switch
Retains speed setting for ease of use.
Small and Lightweight
For easier handling and less fatigue.
16
B808-01 876
• 8100 Cordless 8VMAX Rotary Tool
• 1-Hour Charger, 8VMAX Lithium-Ion Battery Pack (1)
• Compact Storage Case
• Wrench, 1/8" Collet
Grinding/Sharpening - 84922, 932, 952
Cutting - 540 (x3)
Cleaning/Polishing - 403, 414 (x2), 421
Sanding - 407, 408 (x3), 432 (x3), 445 (x2)
Miscellaneous - 401, 402
21 ASSORTED ACCESSORIES
8100 KIT 8100-N/21
CORDLESS 8VMAX ROTARY TOOL ACCESSORIES
8VMAX Lithium-Ion
Battery Pack
8VMAX 1-Hour
Lithium-Ion
Battery Charger
17
Limited
Warranty
Versatility
Variable Speed
For maximum accessory versatility
and precise tool control.
Rechargeable 7.2V Lithium-ion
Battery holds a charge 2 years while
in storage.
Unique Contoured Grip
Designed for superior precision,
control, and comfort in your hand.
Finger-Tip On/Off Switch
For one-handed operation.
Compact and Ultra-Lightweight
Can be used with most Dremel
accessories and no attachments.
Docking Station
Continually charges so the tool is
always fully charged and ready to use.
CORDLESS ROTARY TOOLS
• Always Ready
• Goes Everywhere
Created to Fit Your Hand
and Your Lifestyle™
18
• Dremel Stylus Rotary Tool
• Charging Base and Accessory Organizer
• Accessory Case, Product Reference Sheet
• Wrench, 1/8" Collet
Carving/Engraving - 105, 107, 191, 194
Grinding/Sharpening - 932, 84922
Cleaning/Polishing - 403, 414 (X4), 421, 425, 429 (X3)
Sanding - 430, 431, 438 (X2), 446, 521E
Miscellaneous - 401, 402, 481
25 ASSORTED ACCESSORIES
STYLUS KIT 1100 - N/25
19
757-01 758-01
Two Speeds
For control and accuracy.
Removable battery pack
Continuous use to finish your projects.
7.2 Volts of Power
. . . goes anywhere.
Light and Compact
Easy to handle and fun to use — anywhere!
3-Hour Charger
Quick battery recharge with LED light. Light
indicates battery is correctly placed into the
charger for proper charging.
Versatility Limited
Warranty
CORDLESS ROTARY TOOLS
3-Hour Battery
Charger
7.2V Battery Pack
7700 ACCESSORIES
• 7.2V Two-Speed Cordless Rotary Tool, Lawn
Mower and Garden Tool Sharpener
• Corrugated Storage Case, Accessory Organizer,
Product Reference Sheet
• 3-Hour Charger
• Wrench, 1/8" Collet
Carving/Engraving - 191
Grinding/Sharpening - 932, 8193, 83322
Cutting - 420, 426
Cleaning/Polishing - 421, 422, 425, 429
Sanding - 407, 408, 432
Miscellaneous - 401, 402
15 ASSORTED ACCESSORIES
7700 KIT 7700-02
20
755-01 756-01
Two Speeds
For control and accuracy.
Removable battery pack
Continuous use to finish your projects.
4.8 Volts of Power
For light duty precision jobs.
Light and Compact
Easy to handle and fun to use — anywhere!
3-Hour Charger
Quick battery recharge with LED light. Light
indicates battery is correctly placed into the
charger for proper charging.
Versatility Limited
Warranty
4.8V Battery Pack
7300 ACCESSORIES
• 4.8V Two-Speed MINIMITE®
• 3-Hour Charger
• Wrench, 1/8" Collet
Grinding/Sharpening - 84922
Cleaning/Polishing - 414
Sanding - 407, 432
Miscellaneous - 401
5 ASSORTED ACCESSORIES
3-Hour Battery
Charger
7300 KIT 750-02
21
220
225
231
335
565
566
568
575
A576
A577
670
675
678-01
1453
2500-01
A550
A679-02
4200 • * • • • • • • * • • * • • • • •
4000 • • • • • • • • • • • • • • • • •
400 • • • • • • • • • • • • • • • • •
3000 • • • • • • • • • • • • • • • • •
300 • • • • • • • • • • • • • • • • •
398 • • • • • • • • • • • • • • • • •
395 • • • • • • • • • • • • • • • • •
285 • • • • • • • • • • • • • • • • •
275 • • • • • • • • • • • • • • • •
200 • • • • • • • • • • • • • • • • •
100 • • • • • • • • • • • • • • • •
8220 • • • • • • • • • • • • • • • • •
8200 • • • • • • • • • • • • • • • • •
8100 • • • • • • • • • • • • • • •
800 • • • • • • • • • • • • • • •
770 • • • • •
750
1100
7300
ROTARY TOOL ATTACHMENT COMPATIBILITY KEY
SHIELD KIT MODEL A550
Increased comfort from debris and sparks
during cutting, grinding, sanding, and
polishing applications.
• Easy to Use – Spring friction design allows for
quick adjustment and accessibility to accessory.
• Compact for greater maneuverability.
Use this chart to find out which attachments work with your tool.
Adapters may be needed.
* This attachment is compatible with the 4200 when used with
the 4200 Attachment Adapter found in your Dremel 4200 kit.
Grinding/Sharpening - 8193
Cutting - EZ456
4 ASSORTED ACCESSORIES
ROTARY TOOL ATTACHMENTS
CORDLESS CORDED
ATTACHMENT MODEL NUMBER
Cleaning/Polishing - 428
Miscellaneous - EZ402
TOOL MODEL
NUMBER
22
107 481
Functions as an articulating drill press
that rotates 90º, rotary tool holder, and
flex-shaft tool stand.
• Detents click the tool in place in 15º
increments from vertical to horizontal.
• “Crow’s Nest” provides on-board
storage for Dremel accessories.
• Durable, die-cast aluminum base.
WORK STATION™ MODEL 220 - 01
Ideal for hard to reach places and fine detail work.
• Quick connect attach system.
• 36" long cable with new 5" bend radius
provides more flexibility.
• Comfort grip hand piece.
• Integrated shaft lock button.
• Holds up to 1/8" shank.
• Works with collet system and Dremel chuck.
FLEX SHAFT ATTACHMENT MODEL 225 - 01
TOOLS NOT INCLUDED WITH ATTACHMENTS
Transfers the weight of the tool to the palm of your
hand for improved tool balance and control.
• Offers enhanced grip and comfort for
detailed applications.
• Provides optimal tool control when precision
is required.
• Attaches onto a rotary tool in place of its nose piece
for quick and easy installation.
• Includes 107 engraving cutter and
tracing stencil.
DETAILER'S GRIP MODEL A577
23
• Allows for sturdy controlled cuts with
maximum visibility.
• Easy depth adjustment. Set to the correct cutting
depth for the material you are working on.
• Includes cutting guide, 2 drywall cutting bits for
cutting drywall for electrical boxes & air vents.
• Includes 1 multipurpose cutting bit for making cuts
in ceiling tile, wood, plastic, fiberglass, drywall,
laminate and vinyl siding.
MULTIPURPOSE CUTTING KIT MODEL 565
Converts your corded Rotary Tool into a bench
mounted wood shaper.
• Features an adjustable fence and large
8" x 6" worktable.
• Slot, groove, sand and trim edges.
SHAPER/ROUTER TABLE MODEL 231
Converts your corded Rotary Tool into a plunge router.
• Clear base.
• Two depth stops.
• Includes edge guide and circle guide.
• Rout circles, parallel to edge, signs and inlay
work and decorative edges.
PLUNGE ROUTER ATTACHMENT MODEL 335 - 01
Gets a Grip on Anything, Anywhere!
• Portable vise holds work piece for projects
such as woodworking, home projects, crafts
and hobbies.
• Clamps to any work surface up to 2-1/2" thick.
• Rotates 360º and tilts 50º allowing user to
lock the workpiece in any position.
• Tool holder turns Dremel Rotary Tools into a
stationary sander, grinder or polisher.
• Removable clamping jaws creates a stand-alone
bar clamp.
MULTI-VISE™ MODEL 2500 - 01
24
569
570
• Allows for sturdy controlled cuts with
maximum visibility.
• Easy depth adjustment. Set to the correct
cutting depth for the material you are working on.
• Includes cutting guide and tile cutting bit.
• Shape ceramic wall tile around fixtures or
plumbing pipes.
Not for use on ceramic floor tile.
• Also available: Model 570 1/8" Grout Removal Bit
(Not included with 568).
For use on wall and floor grout!
• Multiple slide depth adjustment.
• 30° angle for controlled cutting.
• Guides 180° apart to keep bit centered
between tiles.
• Easy screw-on mounting.
• Excellent cutting visibility.
• Includes 1/16" Grout Removal Bit – Model 569.
Made of solid carbide, the bit will remove both wall
and floor grout.
TILE CUTTING KIT MODEL 566
GROUT REMOVAL ATTACHMENT MODEL 568
TOOLS NOT INCLUDED WITH ATTACHMENTS
Enhances the versatility of your Dremel Rotary Tool by
allowing you to get into hard-to-reach areas.
• Quick connect system easily attaches to your rotary
tool in place of the housing cap, no
wrenches required.
• Compact, durable design for those
“hard-to-reach” places.
RIGHT ANGLE ATTACHMENT MODEL 575
25
561
932
407
Works great on wood and all wood-like materials.
• Make clean, straight perpendicular
cuts up to 1/4" thick.
• Quick connect system attaches to
your rotary tool in seconds.
• Includes blade.
• Long-lasting steel blade.
• 1-1/4" diameter, 48 teeth.
• One blade per package.
• For use with Mini Saw Attachment only.
CIRCLE CUTTER AND STRAIGHT EDGE GUIDE
MODEL 678 - 01
The simple way to cut circular holes in many types
of materials. Convenient measurement guides in
both inches and centimeters, so you can cut out the
right-sized circle every time.
• Makes circles from 3/4" -12" (1.9-30 cm).
• Attaches quickly and easily without tools.
• Depth adjustment allows easy setting of the
correct cutting depth.
• Straight Edge Guide allows routing or cutting
in a straight line.
• Includes 1/8" Multipurpose Cutting Bit –
Model 561 (see p. 34).
Stabilizes a handheld tool by providing an edge guide
or serves as a work platform when the tool is mounted
in a secure position.
• Increased control during sanding and
grinding applications.
• Platform provides greater stability during edge
sanding and sharpening.
• Adjustable depth control for a precise finish.
• Attaches onto a rotary tool in place of its nose piece
for quick and easy installation.
• Includes 407 1/2" 60 grit sanding drum, 932
aluminum oxide grinding stone and instructions.
SANDING/GRINDING GUIDE™ MODEL A576
MINI SAW ATTACHMENT MODEL 670
RIP CROSSCUT BLADE MODEL 546
26
932
The Dremel chain saw sharpening attachment as
well as the Dremel lawn mower and garden tool
sharpening attachment are included together in
one kit for your convenience.
• Guide provides optimum sharpening angle.
• Sharpens all rotary lawn mower blades.
• Easily sharpen the dullest of chains.
• Garden Tool Sharpening
Attachment, Lawn
Mower Sharpening
Attachment, Chain Saw
Sharpening Attachment
• Wrench, Gauge
• 2 Spacers
• Instruction Manual
• 4 Sharpening Stones
Nos. 453, 454, 455,
(see p. 30) and 932
(see p. 31)
Easily sharpen the dullest of chains.
• Sharpening Attachment
• 3 Sharpening Stones
Nos. 453, 454 and 455
(see p. 30)
• Gauge
• 2 Spacers
• Wrench
• Instruction Manual
The fastest, easiest, safest way to sharpen your
lawn mower blade and other garden tools.
• Guide provides optimum sharpening angle.
• Sharpens most rotary lawn mower blades.
• Long-wearing ABS plastic material.
• Includes grinding stone, #932 (see p.31).
LAWN MOWER & GARDEN TOOL SHARPENER
MODEL 675
LAWN MOWER, GARDEN TOOL, AND CHAIN SAW
SHARPENING KIT MODEL A679 - 02
CHAIN SAW SHARPENING ATTACHMENT
MODEL 1453
TOOLS NOT INCLUDED WITH ATTACHMENTS
27
9931 9933 9934 9935 9936
100 114 115 (x2) 116 117 (x2) 118 121 124 125 (x2)
134 144 190 191 192 (x2) 193 194 (x2) 196 (x2) 199
480
1/4" 5/16" 5/16" 5/16" 3/4"
6,4 mm 7,9 mm 7,9 mm 7,9 mm 19,1 mm
1/4" 5/16" 5/16" 1/4" 1/4" 1/8" 1/4" 5/16" 1/4"
6,4 mm 7,9 mm 7,9 mm 6,4 mm 6,4 mm 3,2 mm 6,4 mm 7,9 mm 6,4
5/16" 5/16" 3/32 1/8" 3/16" 5/64" 1/8" 7/32" 3/8"
7,9 mm 7,9 mm 2,4 mm 3,2 mm 4,8 mm 2,0 mm 3,2 mm 5,6 mm 9,5 mm
HIGH SPEED CUTTERS High speed cutters can
be used for shaping, hollowing, grooving, slotting,
making tapered holes in soft metals, plastics and
woods. # 199 cutter can be used to make small slits.
STRUCTURED TOOTH TUNGSTEN CARBIDE CUTTERS Fast-cutting sharp teeth
for greater material removal. Use on fiberglass, wood, plastic, epoxy, rubber,
laminates, particle board and ceramic tile.
CARVING/ENGRAVING
NEW UNIVERSAL SHANK STANDARD
ROTARY TOOL ACCESSORIES
NO MORE HUNTING FOR THE RIGHT COLLET
Over the next year, all Dremel rotary accessories are transitioning
to a 1/8" shank standard. This means never having to search for the
right collet again. Colet 480 will soon work for all rotary accessories.
CARVING SOFT MATERIALS
* As this conversion will take some time, please
refer to accessory packaging to verify accessory shank size.
1/8"
28
7103 7105 7120 7122 7123 7134 7144 7150
9901 9902 9903 9904 9905 9906 9909 9910 9911
105 (x2) 106 (x2) 107 (x2) 108 109 110 111 113
7103 (x1) 7144 (x1)
CARVING/ENGRAVING
5/64" 11/64" 17/64" 3/32" 3/16" 5/64" 3/32"
2,0 mm 4,4 mm 6,7 mm 2,4 mm 4,8 mm 2,0 mm 2,4 mm
Dual Package
1/8" 3/32" 1/8" 3/32" 1/8" 1/8" 1/8" 1/8" 1/8"
3,2 mm 2,4 mm 3,2 mm 2,4 mm 3,2 mm 3,2 mm 3,2 mm 3,2 mm 3,2 mm
ENGRAVING CUTTERS Quality cutters for detail engraving,
carving, routing in wood, fiberglass, plastic and soft metals.
DIAMOND WHEEL POINTS For fine detail work, engraving, carving, touch-up and
finishing. Use on wood, jade, ceramic, glass, hardened steel, semi precious stones
and other hard materials. Bits are covered with diamond particles.
1/32" 1/16" 3/32" 1/32" 1/16" 5/64" 1/32" 1/16"
0,8 mm 1,6 mm 2,4 mm 0,8 mm 1,6 mm 2,0 mm 0,8 mm 1,6 mm
ENGRAVING
ENGRAVING
CARVING HARD MATERIALS
SOFT MATERIALS
HARD MATERIALS
TUNGSTEN CARBIDE CUTTERS Use for shaping, smoothing and material removal.
Use on hardened steel, stainless steel, cast iron, nonferrous metals, fired
ceramics, plastics, hardwoods and other hard materials. Not for use with floor tile.
29
612 615 617 618 640
650 652 654 655
ROUTER BITS For routing, inlaying, and mortising in wood and other soft
materials. Use with Dremel # 330 Router Attachment, # 335 Plunge Router
Attachment, and # 231 Shaper/Router Table. Made of high speed steel.
3/32"
2,4 mm
Piloted
Beading
1/8"
3,2 mm
Corner
Rounding
1/4"
6,4 mm
Core
Box
1/2"
12,7 mm
Chamfer
1/4"
6,4 mm
V-Groove
1/8"
3,2 mm
Straight
3/16"
4,8 mm
Straight
1/4"
6,4 mm
Straight
5/16"
7,9 mm
Keyhole
ROUTING
ROTARY TOOL ACCESSORIES
30
453 (x2) 454 (x2) 455 (x2) 500 516 541 EZ541GR
CHAIN SAW SHARPENING STONES – 453, 454, 455
Precision-ground for quick, easy sharpening
of chain saw blades.
Each package contains 2 stones.
ALUMINUM OXIDE ABRASIVE WHEEL – 500
Perfect for cleaning, de-burring, removing rust, and polishing
of most metals, including stainless steel.
ALUMINUM OXIDE ABRASIVE POINT – 516 Abrasive point is great for
finishing work and light de-burring. It can be used for paint and rust removal
without removing any of the base material.
ALUMINUM OXIDE GRINDING WHEEL – 541 Use for de-burring, rust
removal and general purpose grinding. 2 Per Pack. Use 541 with Mandrel 402.
EZ Lock™ 1-½" ALUMINUM OXIDE GRINDING WHEEL – EZ541GR
For use with EZ Lock™ mandrel EZ402.
5/32" 3/16" 7/32"
4,0 mm 4,8 mm 5,6 mm
1"
25,4 mm
1/2"
12,7 mm
7/8"
22,2 mm
1-1/2"
38,1 mm
GRINDING/SHARPENING
FERROUS MATERIALS
31
971 997 8153 8175 8193 8215
911 932 941 945 952 953 (x2)
83142 83322 83702 84922 (x2) 85422 85602 85622
ALUMINIUM OXIDE GRINDING STONES (ORANGE/BROWN) Use on
metals, castings, welded joints, rivets and rust. Ideal for sharpening,
de-burring
and general purpose grinding of most materials.
5/8" 1/8" 3/16" 3/8" 5/8" 1"
15,9 mm 3,2 mm 4,8 mm 9,5 mm 15,9 mm 25,4 mm
7/16" 3/8" 5/8" 3/16" 3/8" 1/4"
11,1 mm 9,5 mm 15,9 mm 4,8 mm 9,5 mm 6,4 mm
SILICON CARBIDE GRINDING STONES (BLUE/GREEN)
Designed to work well on stone, glass, ceramics, porcelain and
non-ferrous metals.
9/32" 1/8" 1/8" 3/16" 25/32" 13/32" 1/2"
7,1 mm 3,2 mm 3,2 mm 4,8 mm 19,8 mm 10,3 mm 12,7 mm
GRINDING/SHARPENING
ROTARY TOOL ACCESSORIES
FERROUS MATERIALS
NON-FERROUS MATERIALS
32
EZ406 EZ409 EZ426CU EZ456 EZ456B EZ476
1 2 3
EZ L ock™
EZ Lock™ STARTER KIT – EZ406 Includes 1 EZ Lock™ mandrel and 5
reinforced cut-off wheels.
EZ Lock™ 1-½" THIN REINFORCED CUT-OFF WHEEL – EZ409
For use with EZ Lock™. Reinforced cut-off wheels for cutting metal. 2X more cuts
compared with 409. 5pc.
EZ Lock™ 1-¼" REINFORCED CUT-OFF WHEEL – EZ426CU
For use with EZ Lock™. Reinforced cut-off wheels for cutting metal. 2X more cuts
compared with 420. 3pc.
EZ Lock™ 1-½" REINFORCED CUT-OFF WHEEL – EZ456
For use with EZ Lock™. Reinforced cut-off wheels for cutting metal. 2X more cuts
compared with 426. 5pc.
EZ Lock™ 1-½" REINFORCED CUT-OFF WHEEL
BULK PACK – EZ456B For use with EZ Lock™. Reinforced cut-off wheels for
cutting metal. 12pc. Bulk pack.
EZ Lock™ 1-½" REINFORCED CUT-OFF WHEEL – EZ476
For use with EZ Lock™. Reinforced cut-off wheel makes clean cuts in plastic. 5pc.
Faster Accessory Changes – Easy As 1, 2, 3
Pul l – Twist – Release
CUTTING
33
409 420 540 426 456 426B
543 EZ544 546
CUT-OFF WHEELS – 409, 420, 540 For slicing and cutting metal, wood
and plastic. Cut-off wheels make it easy to cut or slot bolts, screws, sheet metal,
thin wood and plastic. The cut-off wheel cuts only along its edge. Do not attempt
to sand or cut curved holes with them. Use with mandrel 402.
FIBERGLASS REINFORCED CUT-OFF WHEELS – 426, 456
Use with mandrel 402. 456 package includes a washer set only used with 456.
Mandrel 402 is sold separately.
CARBIDE CUTTING/SHAPING WHEEL – 543 For cutting and
shaping on soft and hard woods, fiberglass, plastics and laminates.
Do not use on metal. Mandrel included. Thickness .070" (1,8 mm).
EZ Lock™ 1-½" CARBIDE CUTTING WHEEL – EZ544 For cutting and
shaping on soft and hard woods, fiberglass, plastics and laminates. Do not use on
metal. For use with EZ Lock™ mandrel.
RIP/CROSSCUT BLADE – 546 For use with Mini Saw Attachment 670
only (page 25). Thickness .023" (0,6 mm).
1 - 1/4"
31,8 mm
1 - 1/2"
38,1 mm
15/16"
23,8 mm
.025" thick
36 per pack
15/16"
23,8 mm
.040" thick
20 per pack
1-1/4"
31,8 mm
.0625" thick
5 per pack
1-1/4"
31,8 mm
.045" thick
5 per pack
1-1/2"
38,1 mm
.045" thick
10 per pack
Cut-off wheel
dispenser
20 per pack
1-1/4"
31,8 mm
CUTTING
ROTARY TOOL ACCESSORIES
METAL (Limited use on wood and plastic)
WOOD
34
545 EZ545 560 561 562 569 570
DIAMOND WHEEL – 545 Great for cutting, sawing and carving of
hard materials such as marble, concrete, brick, porcelain, ceramics, hard
epoxy, soft and hard wood. Mandrel 402 is included. Thickness .023"
(0,6 mm). Do not run in excess of 20,000 RPM.
EZ Lock™ 1-½" DIAMOND WHEEL – EZ545 For use with
EZ Lock™. Diamond cutting wheel makes clean cuts in hard materials.
1 - 1/2"
38,1 mm
7/8"
22,2 mm
1/16" 1/8"
1,6 mm 3,2 mm
CUTTING
DRYWALL CUTTING BIT – 560* Gives you fast clean cuts
in drywall.
MULTIPURPOSE CUTTING BIT – 561* Cuts hardwood up to
3/8" and softwood up to 5/8". Also cuts plastic, fiberglass, drywall,
laminate, aluminum & vinyl siding.
TILE CUTTING BIT – 562* Cuts ceramic wall tile, cement board,
and plaster. (Not for use on floor tile.)
CARBIDE GROUT REMOVAL BITS – 569 AND 570† Ideal for
replacing wall and floor grout or removing grout to replace broken tiles.
* Use with cutting guide (page 23).
† Use with grout removal guide (page 24).
DRYWALL, MULTIPURPOSE, TILE AND GROUT
HARD MATERIALS
35
414 422 429 423E
421 425 461 462 463
POLISHING ACCESSORIES – 414, 422, 429 Ideal for polishing metals
and plastics. Using polishing compound
# 421 with wheels produces a high luster.
Use 414, 422 and 429 with Mandrel 401.
POLISHING CLOTH – 423E Made to take a smooth finish and polish it to
a high luster. Use with either EZ402, or with 402. Mandrels sold separately.
POLISHING COMPOUND – 421 Use with felt or cloth accessories to polish
metals and plastics. Compound will remove a dull oxidized film and/or light
surface imperfections. A solid compound.
EMERY IMPREGNATED POLISHING WHEEL – 425 Ideal for general
polishing of most ferrous metal, stone, glass and ceramic. Use 425 with
mandrel 402.
RUBBER POLISHING POINTS – 461, 462, 463 Blue points for finishing
and polishing all ferrous metals. Removes small burrs and scratch marks left by
grinding and sanding, and cleans and defines grooves. Also effective on many
stones and ceramics.
Felt 1/2" dia.
6 per pack
Felt 3/8" dia. Felt 1" dia. Cloth 1" dia.
1"
25,4 mm
1/4" 1/4" 1/4"
6,4 mm 6,4 mm 6,4 mm
CLEANING/POLISHING
ROTARY TOOL ACCESSORIES
36
520 538 403 404 405 428 442 443
530 531 532 535 536 537
POLISHING WHEEL – 520 Use for light stock removal and high luster
polishing of metals and hard plastics. The wheel is impregnated with a silicon
carbide abrasive and lubricant, eliminating the need for polishing compound.
ABRASIVE BRUSH – 538 Dremel’s strongest and longest lasting brush.
Extra-thick nylon bristles are coated with an abrasive grit for material removal
on the toughest jobs. Use for de-burring metal or wood and for removing rust
and paint. Do not run brush in excess of 20,000 RPM.
BRISTLE BRUSHES – 403, 404, 405 Use for light de-burring, cleaning,
polishing of silverware, jewelry and other precious metals; can use with polishing
compound.
CARBON STEEL BRUSHES – 428, 442, 443 Versatile brush for removing
rust and corrosion, polish metal surfaces. De-burr and blend surface junctures,
clean electrical components.
STAINLESS STEEL BRUSHES – 530, 531, 532 Stainless steel brushes
do not cause “after-rust” when used on corrosive-resistant materials like pewter,
aluminum and stainless steel.
BRASS BRUSHES – 535, 536, 537 Brass brushes are non-sparking
and softer than steel. They will not scratch soft metals like gold, copper, brass.
Do not run brushes in excess of 15,000 RPM.
CLEANING/POLISHING
3/4" 1/2" 1/8"
19,1 mm 12,7 mm 3,2 mm
3/4" 1/2" 1/8"
19,1 mm 12,7 mm 3,2 mm
1"
25,4 mm
1/2"
12,7 mm
3/4" 1/2" 1/8"
19,1 mm 12,7 mm 3,2 mm
3/4" 1/2" 1/8"
19,1 mm 12,7 mm 3,2 mm
37
EZ471SA EZ472SA EZ473SA
502 503 504 505 801
511E 512E (x2)
DETAIL ABRASIVE BRUSHES – EZ471SA, EZ472SA, EZ473SA Great
for detail cleaning and light sanding. Use on metal, glass, wood, aluminum and
plastics. Use with either EZ402, or 402. Mandrels sold separately. Not to be used
in excess of 15,000 RPM.
FINISHING ABRASIVE BUFFS – 511E, 512E Great for cleaning and light
sanding. Use on metal, glass, wood, aluminum and plastics. The 512 fine-grit
buff is particularly ideal for removing tarnish from brass. Use 511E and 512E
with either EZ402, or 402. Mandrels sold separately. Not to be used in excess of
15,000 RPM.
FLAPWHEELS – 502, 503, 504, 505 Flapwheels grind and polish flat or
contoured surfaces. They are used most effectively as a finishing sander after
heavier surface sanding and material removal is completed.
CARBIDE SHAPING WHEEL – 801 A powerful shaping tool that quickly
and efficiently removes material. Easily creates compound curves and works on
a variety of materials including woods, fiberglass, laminates, plastic, and leather.
Mandrel included. Not to be used for cutting.
Grit: 36 120 220
Coarse Medium Fine
Grit: 80 120 80 120 60
3/8" 3/8" 3/16" 3/16" 1-1/4"
9,5 mm 9,5 mm 4,8 mm 4,8 mm 31,8 mm
SANDING
ROTARY TOOL ACCESSORIES
180 280
Coarse Medium
320
Fine
38
430 431 (x6) 438 (x6) 446 (x6) 407 408 (x6) 432 (x6) 445 (x6)
411 412 413 EZ411SA (x5) EZ412SA (x5) EZ413SA (x5)
EZ407SA
SANDING BANDS – 407, 408, 430, 431, 432, 438, 445, 446 For
rough shaping and smoothing wood and fiberglass; removing rust from metal
surfaces; shaping rubber surfaces. Sander bands are easily replaceable on
drums, and are available in packages of 6 each.
EZ DRUM SANDING MANDREL – EZ407SA Resilient rubber sleeve forms
around 4 tabs to keep accessory secure. Contoured collar holds entire assembly
in place. Currently sold with one sanding band. More accessories to come!
SANDING DISCS – 411, 412, 413, EZ411SA, EZ412SA, EZ413SA
For rough shaping and smoothing wood and fiberglass; removing rust from
metal surfaces; shaping rubber surfaces. Use 411, 412 and 413 with mandrel
402. 36 pieces per pack. Use EZ411SA, EZ412SA and EZ413SA only with the
EZ402 mandrel. 5 pieces per pack.
1/4" diameter 1/2" diameter
3/4" diameter
Grit: 60 120 240 60 120 240
Grit: 180 220 240 60 120 240
Coarse Medium Fine Coarse Medium Fine
SANDING
39
401 402 EZ402 4486 4485
480 481 482 483
90930-04
90930-04
90931
90935
90826*
90827*
90828*
90936
90930*
90929*
90930* 90937
90940
MANDREL – 401 Use with 414, 422 and 429.
MANDREL – 402 Use with 409, 411, 412, 413, 420, 423E, 425, 426, 429, 456, EZ471SA,
EZ472SA, EZ473SA, 511E, 512E, 540, and 541.
EZ Lock™ MANDREL – EZ402 Use with EZ407SA, EZ409, EZ426CU, EZ456,
EZ411SA, EZ412SA, EZ413SA, EZ471SA, EZ472SA, EZ473SA, EZ476, 423E, 511E, 512E,
EZ541GR, EZ544 and EZ545.
DREMEL CHUCK – 4486 This chuck allows you to quickly and easily
change accessories on Dremel Rotary Tools without changing collets. Accepts
accessories with 1/32" - 1/8" shanks. Use with rotary tool models 100, 200, 275,
285, 300, 3000, 395, 398, 400, 4000, 750, 770, 780, 800 and 8200. Also use
with Dremel attachments 212, 225, 575, and 961.
QUICK CHANGE COLLET NUT SET – 4485 Includes Collet Nut and 4
Collets. For use with all Rotary Tools except models 1, 2 & 260, 270, 280 series 1 or
earlier. Collets also available separately.
1/8" 3/32" 1/16" 1/32"
3,2 mm 2,4 mm 1,6 mm 0,8 mm
MISCELLANEOUS
* Available as service part only.
ROTARY TOOL ACCESSORIES
MANDRELS AND COLLETS
CARBON MOTOR BRUSHES
100, 200, 275, 285, 4, 5,
300, 395, 595 & 3000 & 6
6000 1 & 2
398
732
Advantage 9000
400 XPR™
4000
260
270, 280, 370 & 380
232 & 332
275, 285 & 395 1 & 2
275, 285, 300, 3, 4,
395 & 595 5 & 6
6000 1 & 2
BRUSH TOOLS TYPE BRUSH TOOLS TYPE
40
EZ495 90962 415
631-01 660 661 662DR 663DR
150 628
490
EZ TWIST NOSE CAP – EZ495 Loosen
or tighten the collet and replace an accessory
quickly and easily without the need for a wrench.
WRENCH – 90962 For ease of changing bits.
3/8" x 1" DRESSING STONE – 415 Clean
grinding wheels. Shape or reshape for desired
applications. Available as service part only.
COLLET FAN – 490 Blows dust away
for greater visibility to work piece. Great
for sanding, engraving, and carving.
1/8" DRILL BIT – 150 Available as service part only.
DRILL BIT SET – 628
BRAD POINT DRILL BIT SET – 631-01 Titanium coated brad points stay
on center and begin drilling immediately. For use on wood.
1/32" DRILL – 660 4 pc. per pack. *Use with 483 collet.
3/64" DRILL – 661 4 pc. per pack. *Use with 482 collet.
GLASS DRILLING BITS – 662DR, 663DR Diamond tipped drill bits
for use on glass and ceramic wall tile. Lubricant included.
1/8" 1/32" 3/64" 1/16" 5/64" 3/32" 7/64" 1/8"
3,2 mm 0,8 mm 1,2 mm 1,6 mm 2,0 mm 2,4 mm 2,8 mm 3,2 mm
1/8" 5/32" 3/16" 1/4" 1/32" 3/64" 1/8" 1/4"
3,2 mm 4,0 mm 4,8 mm 6,4 mm 0,8 mm 1,2 mm 3,2 mm 6,4 mm
MISCELLANEOUS
DRILL BITS
OTHER
NEW!
NEW!
use 482 use 483
41
MINI ACCESSORY KITS
GENERAL PURPOSE KIT – 687-01 Everything
you need to cut, carve, sand, grind, clean, and polish,
plus a whole lot more!
Carving/Engraving - 194
Grinding/Sharpening - 952, 85422
Cutting - 409 (x36), 426
Cleaning/Polishing - 414 (x2), 421, 428, 429 (x2)
Sanding - 407, 408, 432 (x2)
Miscellaneous - 401, 402
52 ASSORTED ACCESSORIES
ROUTER BIT KIT – 692 For routing, inlaying and mortising in
wood and other soft materials. Use with #330 Router Attachment,
#335 Plunge Router Attachment, and #231 Shaper/Router Table.
CUTTING KIT – 688-01 Reslot a screw, cut
conduit, sheet metal, rusted hose clamps, plus a whole
lot more!
Cutting - 409 (x36), 420 (x24), 426 (x3), 540 (x5)
Miscellaneous - 402
69 ASSORTED ACCESSORIES
CARVING/ENGRAVING KIT – 689-01
Carve intricate details, etch glass, stoneware,
terracotta, plus a whole lot more!
Carving/Engraving - 105, 106, 107, 108, 7103, 7134
Grinding/Sharpening - 83142, 83322 , 83702, 84922
Miscellaneous - 481
11 ASSORTED ACCESSORIES
SANDING/GRINDING KIT – 686-01 Sharpen
lawn tools, remove rust, sand down a sticking door,
and engrave on glass, plus a whole lot more!
Grinding/Sharpening - 932, 8193, 84922, 85422
Cutting - 426
Sanding - 407, 408 (x4), 432 (x4), 412 (x15), 511
Miscellaneous - 402
18 ASSORTED ACCESSORIES
CLEANING/POLISHING KIT – 684-01
Polish a variety of materials to a high luster, clean those
tough-to-reach areas, plus a whole lot more!
Cleaning/Polishing - 403, 404, 405, 414 (x6), 421,
422, 425 (x2), 428, 429 (x3), 520
Miscellaneous - 401, 402
20 ASSORTED ACCESSORIES
Routing - 612, 615, 617, 618, 650, 654
6 ASSORTED ACCESSORIES
42
SUPER ACCESSORY KIT – 709-01 This versatile and
re-usable accessory kit includes everything you need to cut,
grind, sand, polish, drill, sharpen, clean and more.
Carving/Engraving - 191
Grinding/Sharpening - 952, 953, 83142, 84922
Cutting - 409 (x12), 420 (x12), 426, 540
Cleaning/Polishing - 405, 414 (x4), 421, 422, 428, 429 (x4)
Sanding - 407, 408 (x6), 432 (x6), 430, 431 (x6), 438 (x6),
411 (x12), 412 (x12), 413 (x12), 511E
Miscellaneous - 401, 402, 415, 90962
110 ASSORTED ACCESSORIES
ALL-PURPOSE ACCESSORY KIT – 710-05 This
versatile and re-usable accessory kit includes everything
you need to cut, grind, sand, polish, drill, sharpen, clean
and more.
Carving/Engraving - 191
Grinding/Sharpening - 8193, 83142
Cutting - EZ409, EZ456, EZ476, 540
Cleaning/Polishing - 414 (x5), 421, 423E, 428, 429 (x4)
Sanding - 407, 408 (x15), 432 (x15), 430, 431 (x15), 438 (x15),
411 (x24), 412 (x24), 413 (x24), 511E, 512E
Miscellaneous - 401 (x2), 402, EZ402, 90962
160 ASSORTED ACCESSORIES
EZ LOCK™ CUTTING KIT – EZ688-01 Reslot
a screw, cut conduit, sheet metal, rusted hose
clamps, plus a whole lot more!
Cutting - EZ409 (x3), EZ456 (x4), EZ476 (x3)
Miscellaneous - EZ402
11 ASSORTED ACCESSORIES
EZ LOCK™ SANDING/POLISHING KIT –
EZ684-01 Polish a variety of materials to a high
luster, clean those tough-to-reach areas, remove
rust, plus a whole lot more!
Cleaning/Polishing - 423E, 421
Sanding - EZ471SA, EZ472SA, 511E, 512E
7 ASSORTED ACCESSORIES
EZ LOCK™ SANDING/GRINDING KIT –
EZ686-01 Contains all of the sanding and
grinding products a consumer needs.
Grinding - 952, 84922, EZ541GR
Cutting - 426
Sanding - EZ407SA, 408 (x3), 432 (x3), EZ411SA (x2), EZ412SA (x2), EZ413SA (x2)
Miscellaneous - EZ402
18 ASSORTED ACCESSORIES
43
The Makers of Versatile
Tool Systems™
OSCILLATING TOOLS
44
WHAT IS AN OSCILLATING TOOL?
Multi-Max™ oscillating tools, like rotary tools,
use a variety of accessories to accomplish a
wide range of DIY tasks for repair, remodeling
and restoration. However, rather than spinning
like a rotary tool, Multi-Max™ oscillating tools
use rapid side- to-side motion to cut, scrape,
sand, remove grout, grind and more. You
can rest assured that a Dremel Multi-Max™
oscillating tool will help you get the job done
with superior versatility, durability, and control.
45
1 2 3
Repair. R emodel. R estore. Faster. ™
Limited
Warranty
CORDED OSCILLATING TOOLS
For tool-less and
secure accessory
changes.
Unlock – Inser t – Lock
ACCESSORIES
Quick Lock™
For tool-less and secure accessory
changes.
High-Performance 2.5 Amp Motor
For the most demanding applications.
Variable Speed
For optimal performance and control
in a variety of materials.
Electronic Feedback
Auto adjusts power and speed
as needed.
65% More Power
vs. the 6300
Separate On/Off Switch
Retains speed setting for ease of use.
Compact design
Provides easy access to tight areas.
Quick Fit™ Accessory
Interface System
For fast accessory changes without
removing the clamping screw.
46
MULTI-MAX™ KIT MM40-01
• Dremel Multi-Max™ MM40 tool
Cutting - MM480, MM482, MM450
Scraping - MM600
Sanding - MM14, MM70W (x10), MM70P (x5)
Misc - Storage Case
21 ASSORTED PIECES
47
Repair. R emodel. R estore.™
Limited
Warranty
Separate On/Off Switch
Retains speed setting for ease of use.
Compact design
Provides easy access to tight areas.
CORDED OSCILLATING TOOLS
ACCESSORIES
Powerful 2.3 Amp Motor
Easily tackles the toughest
applications.
Variable Speed
For optimal performance and control
in a variety of materials.
Quick Fit™
For fast accessory changes without
removing the clamping screw.
50% More Power
vs. the 6300
Efficient Motor
Runs cool and smooth under load.
48
• Dremel Multi-Max™ MM20 tool
Cutting - MM450, MM480
Scraping - MM610
Sanding - MM11, MM70W (x8), MM70P (x3)
Misc - Storage Case, Allen Wrench
17 ASSORTED PIECES
MULTI-MAX™ KIT MM20-03
CORDED OSCILLATING TOOL OVERVIEW
Model MM40 MM20
Amps 2.5 2.3
OPM 10,000–21,000 10,000–21,000
Electronic
Feedback Control Yes No
Number
of Speeds Variable Variable
Soft Grip Yes Yes
Separate
On/Off Yes Yes
QuickFit™ Accessories Yes Yes
Tool-less Accessory
Change System Yes No
Weight 2 lb. 15 oz. 2 lb. 7 oz.
Warranty 2 year 2 year
49
Repair. R emodel. R estore. Unplugg ed.™
Limited
Warranty
Variable Speed
For optimal performance and control
in a variety of materials.
High Performance Motor
Cuts through a 1-1/4" oak door jamb.
Quick Fit™
For fast accessory changes without
removing the clamping screw.
Compact design
Provides easy access to tight areas.
CORDLESS OSCILLATING TOOLS
Separate On/Off Switch
Retains speed setting for ease of use.
Cordless
For added convenience and versatility.
ACCESSORIES
50
875 876
12VMAX 1-Hour Lithium-Ion
Battery Charger
12VMAX 1-Hour Lithium-Ion
Battery Pack
• Cordless Dremel Multi-Max™ 8300 Tool
• 1-Hour Battery Charger
• 12VMAX Lithium-Ion Battery Packs (2)
Cutting - MM440, MM450
Sanding - MM11, MM70W (x3)
Misc - Storage Case, Allen Wrench
8 ASSORTED PIECES
CORDLESS 12VMAX OSCILLATING TOOL ACCESSORIES
CORDLESS MULTI-MAX™ KIT 8300-01
51
MM470 MM472 MM480 MM482
MM411 MM422 MM440 MM430 MM435
MM450 MM452 MM460 MM462
3" Wood & Drywall
Saw Blade
3.5" Wood
& Metal
Saw Blade
3/4" Wood
& Metal
1-1/4" Wood
Flush Cut Blade
1-1/4" Wood & Metal
Flush Cut Blade
3/8" Wood
Flush Cut Blade
Flush cut a baseboard to install new flooring or cut out drywall to install a
new light switch. Choose from 13 blades to accomplish a variety of tough cuts.
3/4" Wood &
Metal Flush
Cut Blade
1-1/8”
Wood Flush
Cut Blade
3/4" Wood Flush
Cut Blade
Multi-Knife Drywall
Jab Saw
3/4"
Wood Flush
Cut Blade
1-1/8" Wood
& Metal Flush
Cut Blade
OSCILLATING TOOL ACCESSORIES
CUTTING
NEW! NEW!
Dremel Multi-Max™ accessories undergo
rigorous testing so you can feel assured
that you are purchasing a product of
proven value & performance.
52
MM720/MM725
MM723
MM422B (x3) MM440B (x3) MM450B (x3) MM472B (x3) MM491
MM721 (x3) MM722 (x3)
MM900 MM920
Multi-Flex™
Spiral Blade
Multi Flex™
Bracket
MULTI-FLEX™ ACCESSORIES
Multi-Flex™
Saw Blade
Multi-Flex™
Carbide Blade
3-Pack Cutting Assortment
(MM440, MM450, MM422)
Bulk Packs - 3 per pack
Carbide
Rasp
60 Grit
Diamond Paper
Prepare surfaces for ceramic floor tile
replacement. Use the diamond paper
to remove cement, plaster, and thin-set
mortar. Use the carbide rasp to grind and
shape flat surfaces, cement, tile adhesives,
stone and rasp wood.
GRINDING
53
MM70P MM80P MM70W MM80W MM14
MM500 MM501
MM600 MM610
SCRAPING
Rigid
Scraper Blade
Flexible
Scraper Blade
Use the rigid scraper blade for removing
stuck vinyl flooring, carpeting and carpet
pad, and the flexible scraper blade for
projects such as removing old caulking
around the tub or shower.
6 per pack:
80(2), 120(2),
240(2) Grit
6 per pack:
60(2), 120(2),
240(2) Grit
18 per pack:
80(6), 120(6),
240(6) Grit
18 per pack:
60(6), 120(6),
240(6) Grit
Hook &
Loop Pad
Restore windows, make stuck doors work, and remove rust from metal.
Available in assorted grit for sanding bare or painted wood and metal.
Sanding Sheets - Paint Sanding Sheets - Wood
SANDING
Remove wall and floor grout to free
a broken tile. Available in a 1/8" size
and a 1/16" size.
GROUT REMOVAL
1/16" Grout
Removal Blade
1/8" Grout
Removal Blade
OSCILLATING TOOL ACCESSORIES
54
MM300 MM810
MM820 MM830
MM385-01 MM386 MM388 MM389
MULTI-MAX™ ATTACHMENTS
1-3/16" UNIVERSAL ADAPTER –
MM300
Adapters allow use of Dremel
accessories on most oscillating
tools brands.
Cutting Dept h Guide – MM810
Includes Depth Foot and Depth Stop.
Dust Extraction COLLAR –
MM830
NEW!
NEW!
ACCESSORY KITS
NEW! NEW!
ASSIST HANDLE – MM820
Only compatible on Multi-Max™ 6300.
5-Piece Multi-Max™
Cutting Kit
MM422, MM440,
MM450 (3)
6-Piece Multi-Max™
Cutting Kit
MM300, MM462,
MM470, MM450 (3)
14-Piece Multi-Max™
Accessory Kit
MM300, MM482, MM610,
MM450 (2), MM60W(9)
6-Piece Multi-Max™
Cutting Kit
MM300, MM480,
MM482, MM450 (3)
55
The Makers of Versatile
Tool Systems™
SAW-MAX™ TOOL SYSTEM
56
WHAT IS A SAW-MAX™ TOOL?
The new Dremel Saw-Max™ tool is reinventing cutting as
we know it. This powerful tool performs smooth, precise
cuts through a variety of materials including wood, metal,
drywall, plastic, laminate flooring and floor and wall tile.
Its compact design, adjustable foot and excellent line
of sight make accurate one-handed operation simple.
Offering two blade positions and a variety of unique
attachments and accessories - this versatile tool
system can help you make any straight, plunge,
flush, angle or bevel cut.
57
Limited
Warranty
Versatile
Cutting System
Cuts wood, plastic, metal,
tile, masonry & more.
Two cutting
wheel positions
For straight, plunge and
flush cuts.
Powerful 6 Amp Motor
For tough applications.
Worm Drive Gearing
For durability and power.
Excellent line of sight
For confident, precise cuts.
Compact size and
gripping zone
For user friendly one
handed operation.
Adjustable Depth Guide
And plunge action for
precision and control.
Dust Extraction Port
For clean work
environment.
SAW-MAX™ TOOL SYSTEM
• SAW-MAX™ SM20 Tool, 2 x 4 Guide,
Dust Port Adapter
• Storage Case
Cutting - SM500, SM510, SM540, SM600
4 ASSORTED ACCESSORIES
SAW-MAX™ KIT SM20-02
58
1 2
Interior Position
For standard straight cuts.
Exterior Position
For flush cuts with SM600.
Plunge Into Material
For clean and precise cuts.
One-handed Operation
2 CUTTING WHEEL POSITIONS
59
SM500 SM510 (x3) SM520 (x3) SM540 SM600
SAW-MAX™ ACCESSORIES
Wood & Plastic
Cutting Blade
Metal
Cutting Blade
Masonry
Cutting Blade
Tile
Cutting Blade
Wood & Plastic
Flush Cut Blade
Dremel Saw-Max™ tool only uses Dremel Saw-Max™ accessories.
CUTTING
60
SM842 TRSM810
TRSM800 SM840
SM844
1
2
3
4
SAW-MAX™ ATTACHMENTS
Dust
Port Adapter
Miter Guide
2 x 4 Guide
Straight Edge/
Circle Guide
Angle cut to create
miter joint (SM840)
Bevel Cut for
Corner Joint (SM840)
Straight Cut to
Butt Joint Trim at
Door Jamb (SM840)
Compound Miter
Cuts for Crown
Molding Joints (SM844)
IDEAL FOR TRIMWORK
NEW!
Crown Moulding
Guide
61
The Makers of Versatile
Tool Systems™
TRIO™ TOOL SYSTEM
62
WHAT IS A TRIO™ TOOL?
The Dremel Trio™ allows users to cut, sand, and rout
using one multi-purpose tool. Featuring a system of
accessories and attachments to increase versatility, Trio™
users can cut multiple materials including wood, plastic,
drywall, sheet metal, wall tile and more without switching
tools. The tool’s unique, 360-degree cutting technology
and plunge-cut ability allows users to make quick and
controlled cuts, while its unique, 90-degree pivoting
handle facilitates added comfort, control, and accuracy.
63
Cut. Sand. Rout.™ Limited
Warranty
Variable Speed
For maximum accessory versatility
and precise tool control.
90º Pivoting Handle
For superior comfort and control.
Telescoping Foot
For accurate depth control while
cutting, sanding and routing.
Lock-on Button
For comfort during extended use.
On Board Dust Extraction Port
To maintain a clean workspace.
Non-marring Base
To protect delicate work pieces.
Separate On/Off Switch
Retains speed setting for ease of use.
TRIO™ TOOL SYSTEM
64
TRSM800 TR820
• Dremel Trio™ Tool, Compact Depth
Guide, Dust Port Adapter
• Storage Case, Manual, Wrench
Straight Edge/ Compact Depth Guide/Dust Port Adapter
Circle Guide
Cutting - TR563
Sanding - TR407, TR408 (x2),
TR432 (x2), TR445 (x2)
Routing - TR654
9 ASSORTED ACCESSORIES
TRIO™ KIT 6800-02
TRIO™ ATTACHMENTS
65
TR560 TR561 TR562 TR563
TR407 TR408 (x6) TR432 (x6) TR445 (x6) TR451
Trio™ accessories are exclusive to the Dremel Trio™ tool system
and not interchangeable with Dremel rotary tools. Dremel Trio™
tool only uses Dremel Trio™ 3/16" shaft accessories.
PILOTED CUTTING BIT – TR560 Fast, clean cuts in drywall.
MULTIPURPOSE CUTTING BIT (STEEL) – TR561 Softwood, plywood
composites, drywall, acoustic tile, plastic and aluminum.
WALL TILE CUTTING BIT – TR562 Wall tile, plaster, cement board and
backer board.
HARDWOOD/SHEET METAL BIT (CARBIDE) – TR563 Wood, plywood
composites, laminate/engineered flooring and sheet metal.
1/2" SANDING BANDS – TR407, TR408, TR432, TR445 Shape wood
and sand edges and curves.
RANDOM ORBITAL SANDING KIT – TR451 Sand wood faces.
TRIO™ TOOL ACCESSORIES
TRIO™ CUTTING ACCESSORIES
TRIO™ SANDING ACCESSORIES
Grit: 60 120 240
NEW!
66
TR750
TR770
TR780
STRAIGHT ROUTER BIT KIT – TR750
STARTER ROUTER BIT KIT – TR770
SPECIALTY ROUTER BIT KIT – TR780
1/8"
3,2 mm
Straight Router Bit
1/4"
6,4 mm
Straight Router Bit
1/2"
12,7 mm
Straight Router Bit
1/8"
3,2 mm
Roman Ogee
Router Bit
1/8"
3,2 mm
Corner Rounding
Router Bit
1/2"
12,7 mm
V-Groove
Router Bit
3/8"
9,5 mm
Dovetail
Router Bit
1/4"
6,4 mm
Rabbet
Router Bit
3/16"
4,8 mm
Beading
Router Bit
1/4"
6,4 mm
Cove
Router Bit
1/4"
6,4 mm
Flush Trim
Router Bit
1/4"
6,4 mm
Chamfer
Router Bit
1/4"
6,4 mm
Roundnose
Router Bit
TRIO™ ROUTING ACCESSORIES
67
9924 9929
470 471 473 474 499
Multipurpose tool for wood burning, soldering, hot
knife cutting of styrofoam and plastics, cutting and
fusing rope.
Max. Tip Temp: 1,050º F (565º C) | Volts: 110-120V, AC
Watts: 30 | Tool Length: 7-3/8" (187,3 mm)
Tool Weight: 2.5 oz. (71 g)
• VersaTip™ Tool, Tool Stand, Handy
Tip Storage Tube
• 5 Tips (470, 471, 473, 474 & 499)
VERSATIP™ KIT 1550
Limited
Warranty
VERSATIP™ MULTIPURPOSE TOOL
Limited
Warranty
Identify and personalize your valuables. Use for
decorative engraving. Engraves metal, glass, wood,
plastic, and ceramics. Holding area allows for
extended use. Soft grip adds extra comfort
and control.
Motor: 115V, AC/115V, 60Hz, .2 amps/0,2 A
Strokes: 7,200/SPM | Tool Weight: 12 oz. (340 g)
• Engraver Tool, Letter / Number Template
• Carbide Point (9924)
ENGRAVER KIT 290-01
Carbide Point – 9924 For most applications
Diamond Point – 9929 For continuous use
ENGRAVER ACCESSORIES
Available only through Service Center.
Soldering Tip – 470, General Purpose
Tip – 471, Script Tip – 473, Fine
Cutting Tip – 474, Hot Knife Tip – 499
VERSATIP™ ACCESSORIES
ENGRAVER
DP83846A
DP83846A DsPHYTER - Single 10/100 Ethernet Transceiver
Literature Number: SNLS063E
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
©2002 National Semiconductor Corporation www.national.com
May 2002
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
General Description
The DP83846A is a full feature single Physical Layer
device with integrated PMD sublayers to support both
10BASE-T and 100BASE-TX Ethernet protocols over Category
3 (10 Mb/s) or Category 5 Unsheilded twisted pair
cables.
The DP83846A is designed for easy implementation of
10/100 Mb/s Ethernet home or office solutions. It interfaces
to Twisted Pair media via an external transformer. This
device interfaces directly to MAC devices through the IEEE
802.3u standard Media Independent Interface (MII) ensuring
interoperability between products from different vendors.
The DP83846A utilizes on chip Digital Signal Processing
(DSP) technology and digital Phase Lock Loops (PLLs) for
robust performance under all operating conditions,
enhanced noise immunity, and lower external component
count when compared to analog solutions.
System Diagram
Status
10BASE-T
or
MII 100BASE-TX
25 MHz
Typical DsPHYTER application
Ethernet MAC
Magnetics
RJ-45
Clock LEDs
DP83846A
10/100 Mb/s
DsPHYTER
Features
■ IEEE 802.3 ENDEC, 10BASE-T transceivers and filters
■ IEEE 802.3u PCS, 100BASE-TX transceivers and filters
■ IEEE 802.3 compliant Auto-Negotiation
■ Output edge rate control eliminates external filtering for
Transmit outputs
■ BaseLine Wander compensation
■ 5V/3.3V MAC interface
■ IEEE 802.3u MII (16 pins/port)
■ LED support (Link, Rx, Tx, Duplex, Speed, Collision)
■ Single register access for complete PHY status
■ 10/100 Mb/s packet loopback BIST (Built in Self Test)
■ Low-power 3.3V, 0.35um CMOS technology
■ Power consumption < 495mW (typical)
■ 5V tolerant I/Os
■ 80-pin LQFP package (12w) x (12l) x (1.4h) mm
Applications
■ Network Interface Cards
■ PCMCIA Cards
Obsolete
2 www.national.com
DP83846A
Figure 1. Block Diagram of the 10/100 DSP based core.
SERIAL
MANAGEMENT
MII
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDIO
MDC
COL
CRS
RX_ER
RX_DV
RXD[3:0]
RX_CLK
TRANSMIT CHANNELS &
100 Mb/s 10 Mb/s
NRZ TO
MANCHESTER
ENCODER
STATE MACHINES
TRANSMIT
FILTER
LINK PULSE
GENERATOR
4B/5B
ENCODER
PARALLEL TO
SCRAMBLER
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10/100 COMMON
RECEIVE CHANNELS &
100 Mb/s 10 Mb/s
MANCHESTER
TO NRZ
DECODER
STATE MACHINES
RECEIVE
FILTER
LINK PULSE
DETECTOR
4B/5B
DECODER
DESCRAMBLER
SERIAL TO
PARALLEL
NRZI TO NRZ
DECODER
MLT-3 TO
10/100 COMMON
AUTO-NEGOTIATION
STATE MACHINE
REGISTERS
AUTO
100BASE-TX
10BASE-T
MII
BASIC MODE
PCS CONTROL
PHY ADDRESS
NEGOTIATION
CLOCK
CLOCK
RECOVERY
CLOCK
RECOVERY
CODE GROUP
ALIGNMENT
SMART
SQUELCH
RX_DATA
RX_CLK
RX_CLK RX_DATA
TX_DATA TX_DATA TX_CLK
SYSTEM CLOCK
REFERENCE
OUTPUT DRIVER
TD±
INPUT BUFFER
BINARY
DECODER
ADAPTIVE
RD±
LED
DRIVERS
LEDS
HARDWARE
CONFIGURATION
PINS
GENERATION
(AN_EN, AN0, AN1)
CONTROL
MII INTERFACE/CONTROL
(PAUSE_EN)
(LED_CFG, PHYAD)
SERIAL
BLW
AND EQ
COMP
Obsolete
3 www.national.com
DP83846A
Table of Contents
1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6
1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Special Connections . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Strapping Options/Dual Purpose Pins . . . . . . . . . . 7
1.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.8 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . 9
1.9 Package Pin Assignments . . . . . . . . . . . . . . . . . . 10
2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 PHY Address and LEDs . . . . . . . . . . . . . . . . . . . 12
2.3 LED INTERFACES . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . 13
2.5 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 802.3u MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . 16
3.3 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . 20
3.4 10BASE-T TRANSCEIVER MODULE . . . . . . . . . 23
3.5 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . 26
4.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2 Extended Registers . . . . . . . . . . . . . . . . . . . . . . . 37
6.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2 PGM Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 47
6.3 MII Serial Management Timing . . . . . . . . . . . . . . 47
6.4 100 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.5 10 Mb/s Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.7 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Obsolete
4 www.national.com
DP83846A
Connection Diagram
COL
TXD_3
TXD_2
IO_VDD
IO_GND
TXD_1
TXD_0
IO_GND
TX_EN
TX_CLK
TX_ER
CORE_VDD
CORE_GND
RESERVED
RX_ER/PAUSE_EN
RX_CLK
RX_DV
IO_VDD
IO_GND
RXD_0
RESERVED
ANA_GND
RBIAS
ANA_VDD
RESERVED
ANA_GND
ANA_VDD
RESERVED
ANA_GND
RDRD+
ANA_VDD
ANA_GND
ANA_VDD
ANA_GND
TD+
TDANA_
GND
SUB_GND
RESERVED
DP83846A
DSPHYTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CRS/LED_CFG
RESET
RESERVED
IO_GND
IO_VDD
X2
X1
RESERVED
RESERVED
RESERVED
RESERVED
CORE_VDD
CORE_GND
RESERVED
RESERVED
SUB_GND
RESERVED
RESERVED
SUB_GND
RESERVED
RXD_1
RXD_2
RXD_3
MDC
MDIO
IO_VDD
IO_GND
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1
AN_0
CORE_VDD
CORE_GND
RESERVED
RESERVED
Plastic Quad Flat Pack (LQFP)
Order Number DP83846AVHG
NS Package Number VHG-80A
Obsolete
5 www.national.com
DP83846A
1.0 Pin Descriptions
The DP83846A pins are classified into the following interface
categories (each interface is described in the sections
that follow):
— MII Interface
— 10/100 Mb/s PMD Interface
— Clock Interface
— Special Connect Pins
— LED Interface
— Strapping Options/Dual Function pins
— Reset
— Power and Ground pins
Note: Strapping pin option (BOLD) Please see Section 1.6
for strap definitions.
Note: All DP83846A signal pins are I/O cells regardless of
the particular use. Below definitions define the functionality
of the I/O cells for each pin.
1.1 MII Interface
Type: I Inputs
Type: O Outputs
Type: I/O Input/Output
Type OD Open Drain
Type: PD,PU Internal Pulldown/Pullup
Type: S Strapping Pin (All strap pins except PHYAD[
0:4] have internal pull-ups or pulldowns.
If the default strap value is needed
to be changed then an external 5 kΩ resistor
should be used. Please see Table 1.6 on
page 7 for details.)
Signal Name Type LQFP Pin # Description
MDC I 37 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO
management data input/output serial interface which may be asynchronous
to transmit and receive clocks. The maximum clock rate is
25 MHz with no minimum clock rate.
MDIO I/O, OD 36 MANAGEMENT DATA I/O: Bi-directional management instruction/
data signal that may be sourced by the station management entity
or the PHY. This pin requires a 1.5 kΩ pullup resistor.
CRS/LED_CFG O, S 61 CARRIER SENSE: Asserted high to indicate the presence of carrier
due to receive or transmit activity in 10BASE-T or 100BASE-TX Half
Duplex Modes, while in full duplex mode carrier sense is asserted to
indicate the presence of carrier due only to receive activity.
COL O 60 COLLISION DETECT: Asserted high to indicate detection of a collision
condition (simultaneous transmit and receive activity) in 10
Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with Heartbeat enabled this
pin are also asserted for a duration of approximately 1μs at the end
of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal
is always logic 0. There is no heartbeat function during 10 Mb/s full
duplex operation.
TX_CLK O 51 TRANSMIT CLOCK: 25 MHz Transmit clock outputs in 100BASETX
mode or 2.5 MHz in 10BASE-T mode derived from the 25 MHz
reference clock.
TXD[3]
TXD[2]
TXD[1]
TXD[0]]
I 59, 58, 55, 54 TRANSMIT DATA: Transmit data MII input pins that accept nibble
data synchronous to the TX_CLK (2.5 MHz in 10BASE-T Mode or
25 MHz in 100BASE-TX mode.
TX_EN I 52 TRANSMIT ENABLE: Active high input indicates the presence of
valid nibble data on data inputs, TXD[3:0] for both 100 Mb/s or 10
Mb/s nibble mode.
TX_ER I 50 TRANSMIT ERROR: In 100MB/s mode, when this signal is high and
the corresponding TX_EN is active the HALT symbol is substituted
for data.
In 10 Mb/s this input is ignored.
RX_CLK O, PU 45 RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks
for 100BASE-TX mode and 2.5 MHz for 10BASE-T nibble mode.
Obsolete
6 www.national.com
DP83846A
1.2 10 Mb/s and 100 Mb/s PMD Interface
1.3 Clock Interface
1.4 Special Connections
RXD[3]
RXD[2]
RXD[1]
RXD[0]
O, PU/PD 38, 39, 40, 41 RECEIVE DATA: Nibble wide receive data (synchronous to corresponding
RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz for
10BASE-T nibble mode). Data is driven on the falling edge of
RX_CLK. RXD[2] has an internal pulldown resistor. The remaining
RXD pins have pullups.
RX_ER/PAUSE_EN S, O, PU 46 RECEIVE ERROR: Asserted high to indicate that an invalid symbol
has been detected within a received packet in 100BASE-TX mode.
RX_DV O 44 RECEIVE DATA VALID: Asserted high to indicate that valid data is
present on the corresponding RXD[3:0] for nibble mode. Data is driven
on the falling edge of the corresponding RX_CLK.
Signal Name Type LQFP Pin # Description
Signal Name Type LQFP Pin # Description
TD+, TD- O 16, 17 Differential common driver transmit output. These differential outputs
are configurable to either 10BASE-T or 100BASE-TX signaling.
The DP83846A will automatically configure the common driver outputs
for the proper signal type as a result of either forced configuration
or Auto-Negotiation.
RD-, RD+ I 10, 11 Differential receive input. These differential inputs can be configured
to accept either 100BASE-TX or 10BASE-T signaling.
The DP83846A will automatically configure the receive inputs to accept
the proper signal type as a result of either forced configuration
or Auto-Negotiation.
Signal Name Type LQFP Pin # Description
X1 I 67 REFERENCE CLOCK INPUT 25 MHz: This pin is the primary
clock reference input for the DP83846A and must be connected to
a 25 MHz 0.005% (±50 ppm) clock source. The DP83846A supports
CMOS-level oscillator sources.
X2 O 66 REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary
clock reference output.
Signal Name Type LQFP Pin # Description
RBIAS I 3 Bias Resistor Connection. A 9.31 kΩ 1% resistor should be connected
from RBIAS to ANA_GND.
RESERVED I/O 1, 5, 8, 20,
21, 22, 47,
63, 68, 69,
70, 71, 74,
75, 77, 78,
80
RESERVED: These pins must be left unconnected.
Obsolete
7 www.national.com
DP83846A
1.5 LED Interface
1.6 Strapping Options/Dual Purpose Pins
A 5 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors, since the internal pull-up or pull down resistors
will set the default value. Please note that the
PHYAD[0:4] pins have no internal pull-ups or pull-downs
and they must be strapped. Since these pins may have
alternate functions after reset is deasserted, they should
not be connected directly to Vcc or GND.
Signal Name Type LQFP Pin # Description
LED_DPLX/PHYAD0 S, O 33 FULL DUPLEX LED STATUS: Indicates Full-Duplex status.
LED_COL/PHYAD1 S, O 32 COLLISION LED STATUS: Indicates Collision activity in Half Duplex
mode.
LED_GDLNK/PHYAD2 S, O 31 GOOD LINK LED STATUS: Indicates Good Link Status for 10BASET
and 100BASE-TX.
LED_TX/PHYAD3 S, O 30 TRANSMIT LED STATUS: Indicates transmit activity. LED is on for
activity, off for no activity.
LED_RX/PHYAD4 S, O 29 RECEIVE LED STATUS: Indicates receive activity. LED is on for activity,
off for no activity.
LED_SPEED O 28 SPEED LED STATUS: Indicates link speed; high for 100 Mb/s, low
for 10 Mb/s.
Signal Name Type LQFP Pin # Description
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
S, O 33
32
31
30
29
PHY ADDRESS [4:0]: The DP83846A provides five PHY address
pins, the state of which are latched into the PHYCTRL register at
system Hardware-Reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). PHY Address 0 puts the part
into the MII Isolate Mode. The MII isolate mode must be selected
by strapping Phy Address 0; changing to Address 0 by register
write will not put the Phy in the MII isolate mode.
The status of these pins are latched into the PHY Control Register
during Hardware-Reset. (Please note these pins have no internal
pull-up or pull-down resistors and they must be strapped high or low
using 5 kΩ resistors.) Obsolete
8 www.national.com
DP83846A
AN_EN
AN_1
AN_0
S, O, PU 27
26
25
Auto-Negotiation Enable: When high enables Auto-Negotiation
with the capability set by ANO and AN1 pins. When low, puts the
part into Forced Mode with the capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating
mode of the DP83846A according to the following table. The
value on these pins is set by connecting the input pins to GND (0)
or VCC (1) through 5 kΩ resistors. These pins should NEVER be
connected directly to GND or VCC.
The value set at this input is latched into the DP83846A at Hardware-
Reset.
The float/pull-down status of these pins are latched into the Basic
Mode Control Register and the Auto_Negotiation Advertisement
Register during Hardware-Reset. After reset is deasserted, these
pins may switch to outputs so if pull-ups or pull-downs are implemented,
they should be pulled through a 5kΩ resistor.
The default is 111 since these pins have pull-ups.
RX_ER/PAUSE_EN S, O, PU 46 PAUSE ENABLE: This strapping option allows advertisement of
whether or not the DTE(MAC) has implemented both the optional
MAC control sublayer and the pause function as specified in clause
31 and annex 31B of the IEEE 802.3x specification (Full Duplex
Flow Control).
When left floating the Auto-Negotiation Advertisement Register will
be set to 0, indicating that Full Duplex Flow Control is not supported.
When tied low through a 5 kΩ, the Auto-Negotiation Advertisement
Register will be set to 1, indicating that Full Duplex Flow Control is
supported.
The float/pull-down status of this pin is latched into the Auto-Negotiation
Advertisement Register during Hardware-Reset.
CRS/LED_CFG S, O,
PU
61 LED CONFIGURATION: This strapping option defines the polarity
and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping option.
Signal Name Type LQFP Pin # Description
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Obsolete
9 www.national.com
DP83846A
1.7 Reset
1.8 Power and Ground Pins
Signal Name Type LQFP
Pin #
LLP
Pin #
Description
RESET I 62 46 RESET: Active Low input that initializes or re-initializes the
DP83846A. Asserting this pin low for at least 160 μs will
force a reset process to occur which will result in all internal
registers re-initializing to their default states as specified for
each bit in the Register Block section and all strapping options
are re-initialized.
Signal Name LQFP Pin # Description
TTL/CMOS INPUT/OUTPUT SUPPLY
IO_VDD 35, 43, 57, 65 I/O Supply
IO_GND 34, 42, 53, 56, 64 I/O Ground
INTERNAL SUPPLY PAIRS
CORE_VDD 24, 49, 72 Digital Core Supply
CORE_GND 23, 48, 73 Digital Core Ground
ANALOG SUPPLY PINS
ANA_VDD 4, 7, 12, 14 Analog Supply
ANA_GND 2, 6, 9, 13, 15, 18, Analog Ground
SUBSTRATE GROUND
SUB_GND 19, 76, 79 Bandgap Substrate connection Obsolete
10 www.national.com
DP83846A
1.9 Package Pin Assignments
LQFP Pin # Pin Name LQFP Pin # Pin Name
1 RESERVED 41 RXD_0
2 ANA_GND 42 IO_GND
3 RBIAS 43 IO_VDD
4 ANA_VDD 44 RX_DV
5 RESERVED 45 RX_CLK
6 ANA_GND 46 RX_ER/PAUSE_EN
7 ANA_VDD 47 RESERVED
8 RESERVED 48 CORE_GND
9 ANA_GND 49 CORE_VDD
10 RD- 50 TX_ER
11 RD+ 51 TX_CLK
12 ANA_VDD 52 TX_EN
13 ANA_GND 53 IO_GND
14 ANA_VDD 54 TXD_0
15 ANA_GND 55 TXD_1
16 TD+ 56 IO_GND
17 TD- 57 IO_VDD
18 ANA_GND 58 TXD_2
19 SUB_GND 59 TXD_3
20 RESERVED 60 COL
21 RESERVED 61 CRS/LED_CFG
22 RESERVED 62 RESET
23 CORE_GND 63 RESERVED
24 CORE_VDD 64 IO_GND
25 AN_0 65 IO_VDD
26 AN_1 66 X2
27 AN_EN 67 X1
28 LED_SPEED 68 RESERVED
29 LED_RX /PHYAD4 69 RESERVED
30 LED_TX /PHYAD3 70 RESERVED
31 LED_GDLNK/PHYAD2 71 RESERVED
32 LED_COL /PHYAD1 72 CORE_VDD
33 LED_FDPLX /PHYAD0 73 CORE_GND
34 IO_GND 74 RESERVED
35 IO_VDD 75 RESERVED
36 MDIO 76 SUB_GND
37 MDC 77 RESERVED
38 RXD_3 78 RESERVED
39 RXD_2 79 SUB_GND
40 RXD_1 80 RESERVED
Obsolete
11 www.national.com
DP83846A
2.0 Configuration
This section includes information on the various configuration
options available with the DP83846A. The configuration
options described below include:
— Device Configuration
— Auto-Negotiation
— PHY Address and LEDs
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
— BIST
2.1 Auto-Negotiation
The Auto-Negotiation function provides a mechanism for
exchanging configuration information between two ends of
a link segment and automatically selecting the highest performance
mode of operation supported by both devices.
Fast Link Pulse (FLP) Bursts provide the signalling used to
communicate Auto-Negotiation abilities between two
devices at each end of a link segment. For further detail
regarding Auto-Negotiation, refer to Clause 28 of the IEEE
802.3u specification. The DP83846A supports four different
Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full
Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),
so the inclusion of Auto-Negotiation ensures that the highest
performance protocol will be selected based on the
advertised ability of the Link Partner. The Auto-Negotiation
function within the DP83846A can be controlled either by
internal register access or by the use of the AN_EN, AN1
and AN0 pins.
2.1.1 Auto-Negotiation Pin Control
The state of AN_EN, AN0 and AN1 determines whether the
DP83846A is forced into a specific mode or Auto-Negotiation
will advertise a specific ability (or set of abilities) as
given in Table 1. These pins allow configuration options to
be selected without requiring internal register access.
The state of AN_EN, AN0 and AN1, upon power-up/reset,
determines the state of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or
reset can be changed at any time by writing to the Basic
Mode Control Register (BMCR) at address 00h.
2.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83846A transmits
the abilities programmed into the Auto-Negotiation
Advertisement register (ANAR) at address 04h via FLP
Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-
Duplex, and Full Duplex modes may be selected. The
BMCR provides software with a mechanism to control the
operation of the DP83846A. The AN0 and AN1 pins do not
affect the contents of the BMCR and cannot be used by
software to obtain status of the mode selected. Bits 1 & 2 of
the PHYSTS register are only valid if Auto-Negotiation is
disabled or after Auto-Negotiation is complete. The Auto-
Negotiation protocol compares the contents of the
ANLPAR and ANAR registers and uses the results to automatically
configure to the highest performance protocol
between the local and far-end port. The results of Auto-
Negotiation (Auto-Neg Complete, Duplex Status and
Speed) may be accessed in the PHYSTS register.
Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is disabled
the Speed Selection bit in the BMCR controls switching
between 10 Mb/s or 100 Mb/s operation, and the
Duplex Mode bit controls switching between full duplex
operation and half duplex operation. The Speed Selection
and Duplex Mode bits have no effect on the mode of operation
when the Auto-Negotiation Enable bit is set.
The Basic Mode Status Register (BMSR) indicates the set
of available abilities for technology types, Auto-Negotiation
ability, and Extended Register Capability. These bits are
permanently set to indicate the full functionality of the
DP83846A (only the 100BASE-T4 bit is not set since the
DP83846A does not support that function).
Table 1. Auto-Negotiation Modes
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
Obsolete
12 www.national.com
DP83846A
The BMSR also provides status on:
— Whether Auto-Negotiation is complete
— Whether the Link Partner is advertising that a remote
fault has occurred
— Whether valid link has been established
— Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR) indicates
the Auto-Negotiation abilities to be advertised by the
DP83846A. All available abilities are transmitted by default,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
management agent to change (force) the technology that is
used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR) at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indicates
additional Auto-Negotiation status. The ANER provides
status on:
— Whether a Parallel Detect Fault has occurred
— Whether the Link Partner supports the Next Page function
— Whether the DP83846A supports the Next Page function
— Whether the current page being exchanged by Auto-Negotiation
has been received
— Whether the Link Partner supports Auto-Negotiation
2.1.3 Auto-Negotiation Parallel Detection
The DP83846A supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to monitor
the receive signal and report link status to the Auto-
Negotiation function. Auto-Negotiation uses this information
to configure the correct technology in the event that the
Link Partner does not support Auto-Negotiation but is
transmitting link signals that the 100BASE-TX or 10BASET
PMAs recognize as valid link signals.
If the DP83846A completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the
Link Partner. Note that bits 4:0 of the ANLPAR will also be
set to 00001 based on a successful parallel detection to
indicate a valid 802.3 selector field. Software may determine
that negotiation completed via Parallel Detection by
reading a zero in the Link Partner Auto-Negotiation Able bit
once the Auto-Negotiation Complete bit is set. If configured
for parallel detect mode and any condition other than a single
good link occurs then the parallel detect fault bit will set.
2.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted
at any time by setting bit 9 (Restart Auto-Negotiation) of the
BMCR to one. If the mode configured by a successful Auto-
Negotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configuration
for the link. This function ensures that a valid configuration
is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a management
agent, will cause the DP83846A to halt any transmit
data and link pulse activity until the break_link_timer
expires (~1500 ms). Consequently, the Link Partner will go
into link fail and normal Auto-Negotiation resumes. The
DP83846A will resume Auto-Negotiation after the
break_link_timer has expired by issuing FLP (Fast Link
Pulse) bursts.
2.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83846A has been initialized
upon power-up as a non-auto-negotiating device
(forced technology), and it is then required that Auto-Negotiation
or re-Auto-Negotiation be initiated via software,
bit 12 (Auto-Negotiation Enable) of the Basic Mode Control
Register must first be cleared and then set for any Auto-
Negotiation function to take effect.
2.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to complete,
depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full
description of the individual timers related to Auto-Negotiation.
2.2 PHY Address and LEDs
The 5 PHY address inputs pins are shared with the LED
pins as shown below.
The DP83846A can be set to respond to any of 32 possible
PHY addresses. Each DP83846A or port sharing an MDIO
bus in a system must have a unique physical address.
Refer to Section 3.1.4, PHY Address Sensing section for
more details.
The state of each of the PHYAD inputs latched into the
PHYCTRL register bits [4:0] at system power-up/reset
depends on whether a pull-up or pull-down resistor has
been installed for each pin. For further detail relating to the
latch-in timing requirements of the PHY Address pins, as
well as the other hardware configuration pins, refer to the
Reset summary in Section 4.0.
Since the PHYAD strap options share the LED output pins,
the external components required for strapping and LED
usage must be considered in order to avoid contention.
Specifically, when the LED outputs are used to drive LEDs
directly, the active state of each output driver is dependent
on the logic level sampled by the corresponding PHYAD
input upon power-up/reset. For example, if a given PHYAD
input is resistively pulled low then the corresponding output
will be configured as an active high driver. Conversely, if a
given PHYAD input is resistively pulled high, then the corresponding
output will be configured as an active low
Table 2. PHY Address Mapping
Pin # PHYAD Function LED Function
33 PHYAD0 Duplex
32 PHYAD1 COL
31 PHYAD2 Good Link
30 PHYAD3 TX Activity
29 PHYAD4 RX Activity
28 n/a Speed
Obsolete
13 www.national.com
DP83846A
driver. Refer to Figure 2 for an example of a PHYAD connection
to external components. In this example, the
PHYAD strapping results in address 00011 (03h).
The adaptive nature of the LED outputs helps to simplify
potential implementation issues of these dual purpose pins.
2.3 LED INTERFACES
The DP83846A has 6 Light Emitting Diode (LED) outputs,
each capable to drive a maximum of 10 mA, to indicate the
status of Link, Transmit, Receive, Collision, Speed, and
Full/Half Duplex operation. The LED_CFG strap option is
used to configure the LED_FDPLX output for use as an
LED driver or more general purpose control pin. See the
table below:
The LED_FDPLX pin indicates the Half or Full Duplex configuration
of the port in both 10 Mb/s and 100 Mb/s operation.
Since this pin is also used as the PHY address strap
option, the polarity of this indicator may be adjusted so that
in the “active” (FULL DUPLEX selected) state it drives
against the pullup/pulldown strap. In this configuration it is
suitable for use as an LED. When LED_CFG is high this
mode is selected and DsPHYTER automatically adjusts the
polarity of the output. If LED_CFG is low, the output drives
high to indicate the “active” state. In this configuration the
output is suitable for use as a control pin. The
LED_SPEED pin indicates 10 or 100 Mb/s data rate of the
port. The standard CMOS driver goes high when operating
in 100 Mb/s operation. Since this pin is not utilized as a
strap option, it is not affected by polarity adjustment.
The LED_GDLNK pin indicates the link status of the port.
Since this pin is also used as the PHY address strap
option, the polarity of this indicator is adjusted to be the
inverse of the strap value.
In 100BASE-T mode, link is established as a result of input
receive amplitude compliant with TP-PMD specifications
which will result in internal generation of signal detect.
10 Mb/s Link is established as a result of the reception of at
least seven consecutive normal Link Pulses or the reception
of a valid 10BASE-T packet. This will cause the assertion
of GD_LINK. GD_LINK will deassert in accordance
with the Link Loss Timer as specified in IEEE 802.3.
The Collision LED indicates the presence of collision activity
for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit
has no meaning in Full Duplex operation and will be deasserted
when the port is operating in Full Duplex. Since this
pin is also used as the PHY address strap option, the
polarity of this indicator is adjusted to be the inverse of the
strap value. In 10 Mb/s half duplex mode, the collision LED
is based on the COL signal. When in this mode, the user
should disable the Heartbeat (SQE) to avoid asserting the
COL LED during transmission. See Section 3.4.2 for more
information about the Heartbeat signal.
The LED_RX and LED_TX pins indicate the presence of
transmit and/or receive activity. Since these pins are also
used in PHY address strap options, the polarity is adjusted
to be the inverse of the respective strap values.
2.4 Half Duplex vs. Full Duplex
The DP83846A supports both half and full duplex operation
at both 10 Mb/s and 100 Mb/s speeds. Half-duplex is the
standard, traditional mode of operation which relies on the
CSMA/CD protocol to handle collisions and network
access. In Half-Duplex mode, CRS responds to both transmit
and receive activity in order to maintain compliance
with IEEE 802.3 specification.
Since the DP83846A is designed to support simultaneous
transmit and receive activity it is capable of supporting fullduplex
switched applications with a throughput of up to
Figure 2. PHYAD Strapping and LED Loading Example
LED_FDPLX
LED_COL
LED_GDLNK
LED_TX
LED_RX
VCC
10kΩ
1kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
PHYAD4= 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1
10kΩ
Table 3. LED Mode Select
LED_CFG Mode Description
1 LED polarity adjusted
0 Duplex active-high Obsolete
14 www.national.com
DP83846A
200 Mb/s per port when operating in 100BASE-TX mode.
Because the CSMA/CD protocol does not apply to fullduplex
operation, the DP83846A disables its own internal
collision sensing and reporting functions and modifies the
behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to
operate properly.
All modes of operation (100BASE-TX and 10BASE-T) can
run either half-duplex or full-duplex. Additionally, other than
CRS and Collision reporting, all remaining MII signaling
remains the same regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation
with the use of Fast Link Pulse code words can interpret
and configure to full-duplex operation, parallel detection
can not recognize the difference between full and halfduplex
from a fixed 10 Mb/s or 100 Mb/s link partner over
twisted pair. As specified in 802.3u, if a far-end link partner
is transmitting forced full duplex 100BASE-TX for example,
the parallel detection state machine in the receiving station
would be unable to detect the full duplex capability of the
far-end link partner and would negotiate to a half duplex
100BASE-TX configuration (same scenario for 10 Mb/s).
2.5 MII Isolate Mode
The DP83846A can be put into MII Isolate mode by writing
to bit 10 of the BMCR register. In addition, the MII isolate
mode can be selected by strapping in Physical Address 0.
It should be noted that selecting Physical Address 0 via an
MDIO write to PHYCTRL will not put the device in the MII
isolate mode.
When in the MII isolate mode, the DP83846A does not
respond to packet data present at TXD[3:0], TX_EN, and
TX_ER inputs and presents a high impedance on the
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and
CRS outputs. The DP83846A will continue to respond to all
management transactions.
While in Isolate mode, the TD± outputs will not transmit
packet data but will continue to source 100BASE-TX
scrambled idles or 10BASE-T normal link pulses.
2.6 Loopback
The DP83846A includes a Loopback Test mode for facilitating
system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Register
(BMCR). Writing 1 to this bit enables MII transmit data
to be routed to the MII receive outputs. Loopback status
may be checked in bit 3 of the PHY Status Register
(PHYSTS). While in Loopback mode the data will not be
transmitted onto the media in 100 Mb/s mode. To ensure
that the desired operating mode is maintained, Auto-Negotiation
should be disabled before selecting the Loopback
mode.
During 10BASE-T operation, in order to be standard compliant,
the loopback mode loops MII transmit data to the MII
receive data, however, Link Pulses are not looped back. In
100BASE-TX Loopback mode the data is routed through
the PCS and PMA layers into the PMD sublayer before it is
looped back. In addition to serving as a board diagnostic,
this mode serves as a functional verification of the device.
2.7 BIST
The DsPHYTER incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnostics.
The BIST circuit can be utilized to test the integrity of
the transmit and receive data paths. BIST testing can be
performed with the part in the internal loopback mode or
externally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and
receive paths, with the transmit block generating a continuous
stream of a pseudo random sequence. The user can
select a 9 bit or 15 bit pseudo random sequence from the
PSR_15 bit in the PHY Control Register (PHYCTRL). The
looped back data is compared to the data generated by the
BIST Linear Feedback Shift Register (LFSR, which generates
a pseudo random sequence) to determine the BIST
pass/fail status.
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCTRL register. The status bit defaults to 0
(BIST fail) and will transition on a successful comparison. If
an error (mis-compare) occurs, the status bit is latched and
is cleared upon a subsequent write to the Start/Stop bit.
Obsolete
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DP83846A
3.0 Functional Description
3.1 802.3u MII
The DP83846A incorporates the Media Independent Interface
(MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes both the serial MII management interface as well
as the nibble wide MII data interface.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gathering
of status, error information, and the determination of the
type and capabilities of the attached PHY(s).
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
3.1.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are accessible
through the management interface pins MDC and
MDIO. The DP83846A implements all the required MII registers
as well as several optional registers. These registers
are fully described in Section 5. A description of the serial
management access protocol follows.
3.1.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management
Data Clock (MDC) and Management Data Input/Output
(MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame format
is shown below in Table 4: Typical MDIO Frame Format.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83846A with a sequence that can be used
to establish synchronization. This preamble may be generated
either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resistor
to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.
The DP83846A waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83846A serial management port has been initialized
no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid contention
during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83846A drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data. Figure 3 shows the timing relationship
between MDC and the MDIO as driven/received by the Station
(STA) and the DP83846A (PHY) for a typical register
read access.
For write transactions, the station management entity
writes data to the addressed DP83846A thus eliminating
the requirement for MDIO Turnaround. The Turnaround
time is filled by the management entity by inserting <10>.
Figure 4 shows the timing relationship for a typical MII register
write access.
3.1.3 Serial Management Preamble Suppression
The DP83846A supports a Preamble Suppression mode
as indicated by a one in bit 6 of the Basic Mode Status
Register (BMSR, address 01h.) If the station management
entity (i.e. MAC or other management controller) determines
that all PHYs in the system support Preamble Sup-
Table 4. Typical MDIO Frame Format
MII Management
Serial Protocol
Read Operation <01><10>
Write Operation <01><01><10>
Figure 3. Typical MDC/MDIO Read Operation
MDC
MDIO
0 1 1 0 0 1 1 0 0 0 0 0 0 0
(STA)
Idle Start Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA Register Data
Z
MDIO
(PHY)
Z
Z Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 Z
Idle
Z
Z Obsolete
16 www.national.com
DP83846A
pression by returning a one in this bit, then the station
management entity need not generate preamble for each
management transaction.
The DP83846A requires a single initialization sequence of
32 bits of preamble following hardware/software reset. This
requirement is generally met by the mandatory pull-up
resistor on MDIO in conjunction with a continuous MDC, or
the management access made to determine whether Preamble
Suppression is supported.
While the DP83846A requires an initial preamble sequence
of 32 bits for management initialization, it does not require
a full 32-bit sequence between each subsequent transaction.
A minimum of one idle bit between management
transactions is required as specified in IEEE 802.3u.
3.1.4 PHY Address Sensing
The DP83846A provides five PHY address pins, the information
is latched into the PHYCTRL register (address 19h,
bits [4:0]) at device power-up/Hardware reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address
0 puts the part into Isolate Mode. It should also be noted
that selecting PHY Address 0 via an MDIO write to PHYCTRL
will not put the device in Isolate Mode; Address 0 must
be strapped in.
3.1.5 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the
Media Independent Interface. This interface includes a
dedicated receive bus and a dedicated transmit bus. These
two data buses, along with various control and indicate signals,
allow for the simultaneous exchange of data between
the DP83846A and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus
RXD[3:0], a receive error signal RX_ER, a receive data
valid flag RX_DV, and a receive clock RX_CLK for synchronous
transfer of the data. The receive clock can operate
at either 2.5 MHz to support 10 Mb/s operation modes
or at 25 MHz to support 100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus
TXD[3:0], a transmit enable control signal TX_EN, and a
transmit clock TX_CLK which runs at either 2.5 MHz or 25
MHz.
Additionally, the MII includes the carrier sense signal CRS,
as well as a collision detect signal COL. The CRS signal
asserts to indicate the reception of data from the network
or as a function of transmit data in Half Duplex mode. The
COL signal asserts as an indication of a collision which can
occur during half-duplex operation when both a transmit
and receive operation occur simultaneously.
3.1.6 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is
detected when the receive and transmit channels are
active simultaneously. Collisions are reported by the COL
signal on the MII.
If the DP83846A is transmitting in 10 Mb/s mode when a
collision is detected, the collision is not reported until seven
bits have been received while in the collision state. This
prevents a collision being reported incorrectly due to noise
on the network. The COL signal remains set for the duration
of the collision.
If a collision occurs during a receive operation, it is immediately
reported by the COL signal.
When heartbeat is enabled (only applicable to 10 Mb/s
operation), approximately 1μs after the transmission of
each packet, a Signal Quality Error (SQE) signal of approximately
10 bit times is generated (internally) to indicate
successful transmission. SQE is reported as a pulse on the
COL signal of the MII.
3.1.7 Carrier Sense
Carrier Sense (CRS) may be asserted due to receive activity,
once valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is
asserted when a valid link (SD) and two non-contiguous
zeros are detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
3.2 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, as provided
by the MII, to a scrambled MLT-3 125 Mb/s serial
data stream. Because the 100BASE-TX TP-PMD is integrated,
the differential output pins, TD±, can be directly
routed to the magnetics.
The block diagram in Figure 5 provides an overview of
each functional block within the 100BASE-TX transmit section.
The Transmitter section consists of the following functional
blocks:
— Code-group Encoder and Injection block (bypass option)
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
Figure 4. Typical MDC/MDIO Write Operation
MDC
MDIO
0 1 0 1 0 1 1 0 0 0 0 0 0 0
(STA)
Idle Start Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA Register Data
Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z
Idle
1 00 0
Z Z
Obsolete
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DP83846A
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83846A implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Standard,
Clause 24.
3.2.1 Code-group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data
generated by the MAC into 5-bit (5B) code-groups for
transmission. This conversion is required to allow control
data to be combined with packet data code-groups. Refer
to Table 5: 4B5B Code-Group Encoding/Decoding for 4B to
5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001)
upon transmission. The code-group encoder continues to
replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the deassertion of Transmit Enable signal
from the MAC, the code-group encoder injects the T/R
code-group pair (01101 00111) indicating the end of frame.
After the T/R code-group pair, the code-group encoder
continuously injects IDLEs into the transmit data stream
until the next transmit packet is detected (reassertion of
Transmit Enable).
3.2.2 Scrambler
The scrambler is required to control the radiated emissions
at the media connector and on the twisted pair cable (for
100BASE-TX applications). By scrambling the data, the
total energy launched onto the cable is randomly distributed
over a wide frequency range. Without the scrambler,
energy levels at the PMD and on the cable could peak
beyond FCC limitations at frequencies related to repeating
5B sequences (i.e., continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback
shift register (LFSR) with an 11-bit polynomial. The
output of the closed loop LFSR is X-ORd with the serial
Figure 5. 100BASE-TX Transmit Block Diagram
4B5B Code-group
encoder & injector
scrambler
nrz to nrzi
encoder
5B parallel
to serial
TD±
TX_CLK TXD[3:0] /
tx_er
100BASE-TX
Loopback
mux
binary to mlt-3 /
Common Driver
FROM PGM
BP_4B5B
BP_SCR mux
DIV BY 5
Obsolete
18 www.national.com
DP83846A
NRZ data from the code-group encoder. The result is a
scrambled data stream with sufficient randomization to
decrease radiated emissions at certain frequencies by as
much as 20 dB. The DP83846A uses the PHY_ID (pins
PHYAD [4:0]) to set a unique seed value.
3.2.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and
scrambled, the data must be NRZI encoded in order to
comply with the TP-PMD standard for 100BASE-TX transmission
over Category-5 Unsheilded twisted pair cable.
3.2.4 Binary to MLT-3 Convertor / Common Driver
The Binary to MLT-3 conversion is accomplished by converting
the serial binary data stream output from the NRZI
encoder into two binary data streams with alternately
phased logic one events. These two binary streams are
then fed to the twisted pair output driver which converts the
voltage to current and alternately drives either side of the
transmit transformer primary winding, resulting in a minimal
current (20 mA max) MLT-3 signal. Refer to Figure 6.
Figure 6. Binary to MLT-3 conversion
D Q
Q
binary_in
binary_plus
binary_minus
binary_in
binary_plus
binary_minus
COMMON
DRIVER MLT-3
differential MLT-3 Obsolete
19 www.national.com
DP83846A
Table 5. 4B5B Code-Group Encoding/Decoding
Name PCS 5B Code-group MII 4B Nibble Code
DATA CODES
0 11110 0000
1 01001 0001
2 10100 0010
3 10101 0011
4 01010 0100
5 01011 0101
6 01110 0110
7 01111 0111
8 10010 1000
9 10011 1001
A 10110 1010
B 10111 1011
C 11010 1100
D 11011 1101
E 11100 1110
F 11101 1111
IDLE AND CONTROL CODES
H 00100 HALT code-group - Error code
I 11111 Inter-Packet IDLE - 0000 (Note 1)
J 11000 First Start of Packet - 0101 (Note 1)
K 10001 Second Start of Packet - 0101 (Note 1)
T 01101 First End of Packet - 0000 (Note 1)
R 00111 Second End of Packet - 0000 (Note 1)
INVALID CODES
V 00000
V 00001
V 00010
V 00011
V 00101
V 00110
V 01000
V 01100
V 10000
V 11001
Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
Obsolete
20 www.national.com
DP83846A
The 100BASE-TX MLT-3 signal sourced by the TD± common
driver output pins is slew rate controlled. This should
be considered when selecting AC coupling magnetics to
ensure TP-PMD Standard compliant transition times (3 ns
< Tr < 5 ns).
The 100BASE-TX transmit TP-PMD function within the
DP83846A is capable of sourcing only MLT-3 encoded
data. Binary output from the TD± outputs is not possible in
100 Mb/s mode.
3.3 100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is provided
to the MII. Because the 100BASE-TX TP-PMD is
integrated, the differential input pins, RD±, can be directly
routed from the AC coupling magnetics.
See Figure 8 for a block diagram of the 100BASE-TX
receive function. This provides an overview of each functional
block within the 100BASE-TX receive section.
The Receive section consists of the following functional
blocks:
— ADC
— Input and BLW Compensation
— Signal Detect
— Digital Adaptive Equalization
— MLT-3 to Binary Decoder
— Clock Recovery Module
— NRZI to NRZ Decoder
— Serial to Parallel
— DESCRAMBLER (bypass option)
— Code Group Alignment
— 4B/5B Decoder (bypass option)
— Link Integrity Monitor
— Bad SSD Detection
The bypass option for the functional blocks within the
100BASE-TX receiver provides flexibility for applications
where data conversion is not always required.
3.3.1 Input and Base Line Wander Compensation
Unlike the DP83223V Twister, the DP83846A requires no
external attenuation circuitry at its receive inputs, RD±. It
accepts TP-PMD compliant waveforms directly, requiring
only a 100Ω termination plus a simple 1:1 transformer.
The DP83846A is completely ANSI TP-PMD compliant and
includes Base Line Wander (BLW) compensation. The
BLW compensation block can successfully recover the TPPMD
defined “killer” pattern and pass it to the digital adaptive
equalization block.
BLW can generally be defined as the change in the average
DC content, over time, of an AC coupled digital transmission
over a given transmission medium. (i.e., copper
wire).
BLW results from the interaction between the low frequency
components of a transmitted bit stream and the frequency
response of the AC coupling component(s) within
the transmission system. If the low frequency content of
the digital bit stream goes below the low frequency pole of
the AC coupling transformers then the droop characteristics
of the transformers will dominate resulting in potentially
serious BLW.
The digital oscilloscope plot provided in Figure 7 illustrates
the severity of the BLW event that can theoretically be generated
during 100BASE-TX packet transmission. This
event consists of approximately 800 mV of DC offset for a
Figure 7. 100BASE-TX BLW Event
Obsolete
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DP83846A
Figure 8. Receive Block Diagram
4b/5b Decoder
DEscrambler
Digital
adaptive
Equalization
MLT-3 to
Binary decoder
rd±
RX_CLK RXD[3:0] / RX_ER
InPUT BLW
Compensation
BP_4B5B
BP_SCR
Signal Detect
nrzi to nrz
decoder
Code group
alignment
Serial to
parallel
mux
mux
LINK STATUS
Clock
Recovery
Module
CLOCK
LINK
Monitor
÷5
ADC
AGC
Obsolete
22 www.national.com
DP83846A
period of 120 μs. Left uncompensated, events such as this
can cause packet loss.
3.3.2 Signal Detect
The signal detect function of the DP83846A is incorporated
to meet the specifications mandated by the ANSI FDDI TPPMD
Standard as well as the IEEE 802.3 100BASE-TX
Standard for both voltage thresholds and timing parameters.
Note that the reception of normal 10BASE-T link pulses
and fast link pulses per IEEE 802.3u Auto-Negotiation by
the 100BASE-TX receiver do not cause the DP83846A to
assert signal detect.
3.3.3 Digital Adaptive Equalization
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a
concern. In high-speed twisted pair signalling, the frequency
content of the transmitted signal can vary greatly
during normal operation based primarily on the randomness
of the scrambled data stream. This variation in signal
attenuation caused by frequency variations must be compensated
for to ensure the integrity of the transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt
to various cable lengths and cable types depending on the
installed environment. The selection of long cable lengths
for a given implementation, requires significant compensation
which will over-compensate for shorter, less attenuating
lengths. Conversely, the selection of short or
intermediate cable lengths requiring less compensation will
cause serious under-compensation for longer length
cables. The compensation or equalization must be adaptive
to ensure proper conditioning of the received signal
independent of the cable length.
The DP83846A utilizes a extremely robust equalization
scheme referred as ‘Digital Adaptive Equalization’. Traditional
designs use a pseudo adaptive equalization scheme
that determines the approximate cable length by monitoring
signal attenuation at certain frequencies. This attenuation
value was compared to the internal receive input
reference voltage. This comparison would indicate the
amount of equalization to use. Although this scheme is
used successfully on the DP83223V twister, it is sensitive
to transformer mismatch, resistor variation and process
induced offset. The DP83223V also required an external
attenuation network to help match the incoming signal
amplitude to the internal reference.
The Digital Equalizer removes ISI (inter symbol interference)
from the receive data stream by continuously adapting
to provide a filter with the inverse frequency response
of the channel. When used in conjunction with a gain
stage, this enables the receive 'eye pattern' to be opened
sufficiently to allow very reliable data recovery.
Traditionally 'adaptive' equalizers selected 1 of N filters in
an attempt to match the cables characteristics. This
approach will typically leave holes at certain cable lengths,
where the performance of the equalizer is not optimized.
The DP83846A equalizer is truly adaptive to any length of
cable up to 150m.
3.3.4 Clock Recovery Module
The Clock Recovery Module (CRM) accepts 125 Mb/s
MLT3 data from the equalizer. The DPLL locks onto the
125 Mb/s data stream and extracts a 125 MHz recovered
clock. The extracted and synchronized clock and data are
used as required by the synchronous receive operations as
generally depicted in Figure 8.
The CRM is implemented using an advanced all digital
Phase Locked Loop (PLL) architecture that replaces sensitive
analog circuitry. Using digital PLL circuitry allows the
DP83846A to be manufactured and specified to tighter tolerances.
3.3.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is
required in order to present NRZ formatted data to the
descrambler (or to the code-group alignment block, if the
descrambler is bypassed, or directly to the PCS, if the
receiver is bypassed).
3.3.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel
converter which supplies 5-bit wide data symbols to the
PCS Rx state machine.
3.3.7 Descrambler
A serial descrambler is used to de-scramble the received
NRZ data. The descrambler has to generate an identical
data scrambling sequence (N) in order to recover the original
unscrambled data (UD) from the scrambled data (SD)
as represented in the equations:
Synchronization of the descrambler to the original scrambling
sequence (N) is achieved based on the knowledge
that the incoming scrambled data stream consists of
scrambled IDLE data. After the descrambler has recognized
12 consecutive IDLE code-groups, where an
unscrambled IDLE code-group in 5B NRZ is equal to five
consecutive ones (11111), it will synchronize to the receive
data stream and generate unscrambled data in the form of
unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data
that it generates. To ensure this, a line state monitor and a
hold timer are used to constantly monitor the synchronization
status. Upon synchronization of the descrambler the
hold timer starts a 722 μs countdown. Upon detection of
sufficient IDLE code-groups (58 bit times) within the 722 μs
period, the hold timer will reset and begin a new countdown.
This monitoring operation will continue indefinitely
given a properly operating network connection with good
signal integrity. If the line state monitor does not recognize
sufficient unscrambled IDLE code-groups within the 722 μs
period, the entire descrambler will be forced out of the current
state of synchronization and reset in order to reacquire
synchronization.
3.3.8 Code-group Alignment
The code-group alignment module operates on unaligned
5-bit data from the descrambler (or, if the descrambler is
bypassed, directly from the NRZI/NRZ decoder) and converts
it into 5B code-group data (5 bits). Code-group alignment
occurs after the J/K code-group pair is detected.
Once the J/K code-group pair (11000 10001) is detected,
subsequent data is aligned on a fixed boundary.
UD= (SD ⊕ N)
SD UD N ⊕ ( ) = Obsolete
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DP83846A
3.3.9 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair
preceded by IDLE code-groups and replaces the J/K with
MAC preamble. Specifically, the J/K 10-bit code-group pair
is replaced by the nibble pair (0101 0101). All subsequent
5B code-groups are converted to the corresponding 4B
nibbles for the duration of the entire packet. This conversion
ceases upon the detection of the T/R code-group pair
denoting the End of Stream Delimiter (ESD) or with the
reception of a minimum of two IDLE code-groups.
3.3.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and stable
link is established before enabling both the Transmit
and Receive PCS layer.
Signal detect must be valid for 395us to allow the link monitor
to enter the 'Link Up' state, and enable the transmit and
receive functions.
3.3.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83846A will assert
RX_ER and present RXD[3:0] = 1110 to the MII for the
cycles that correspond to received 5B code-groups until at
least two IDLE code groups are detected. In addition, the
False Carrier Sense Counter register (FCSCR) will be
incremented by one.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
3.4 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compliant.
It includes the receiver, transmitter, collision, heartbeat,
loopback, jabber, and link integrity functions, as
defined in the standard. An external filter is not required on
the 10BASE-T interface since this is integrated inside the
DP83846A. This section focuses on the general 10BASE-T
system level operation.
3.4.1 Operational Modes
The DP83846A has two basic 10BASE-T operational
modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83846A functions as a standard
IEEE 802.3 10BASE-T transceiver supporting the
CSMA/CD protocol.
Full Duplex Mode
In Full Duplex mode the DP83846A is capable of simultaneously
transmitting and receiving without asserting the
collision signal. The DP83846A's 10 Mb/s ENDEC is
designed to encode and decode simultaneously.
3.4.2 Collision Detection and SQE
When in Half Duplex, a 10BASE-T collision is detected
when the receive and transmit channels are active simultaneously.
Collisions are reported by the COL signal on the
MII. Collisions are also reported when a jabber condition is
detected.
The COL signal remains set for the duration of the collision.
If the ENDEC is receiving when a collision is detected it is
reported immediately (through the COL pin).
When heartbeat is enabled, approximately 1 μs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indicate
successful transmission. SQE is reported as a pulse
on the COL signal of the MII.
The SQE test is inhibited when the PHY is set in full duplex
mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit in the 10BTSCR register.
3.4.3 Carrier Sense
Carrier Sense (CRS) may be asserted due to receive activity
once valid data is detected via the squelch function.
For 10 Mb/s Half Duplex operation, CRS is asserted during
either packet transmission or reception.
For 10 Mb/s Full Duplex operation, CRS is asserted only
during receive activity.
CRS is deasserted following an end of packet.
3.4.4 Normal Link Pulse Detection/Generation
The link pulse generator produces pulses as defined in the
IEEE 802.3 10BASE-T standard. Each link pulse is nominally
100 ns in duration and transmitted every 16 ms in the
absence of transmit data.
Link pulses are used to check the integrity of the connection
with the remote end. If valid link pulses are not
received, the link detector disables the 10BASE-T twisted
pair transmitter, receiver and collision detection functions.
When the link integrity function is disabled
(FORCE_LINK_10 of the 10BTSCR register), good link is
forced and the 10BASE-T transceiver will operate regardless
of the presence of link pulses.
3.4.5 Jabber Function
The jabber function monitors the DP83846A's output and
disables the transmitter if it attempts to transmit a packet of
longer than legal size. A jabber timer monitors the transmitter
and disables the transmission if the transmitter is active
beyond the Jab time (20-150 ms).
Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's internal
transmit enable is asserted. This signal has to be deasserted
for approximately 250-750 ms (the “unjab” time)
before the Jabber function re-enables the transmit outputs.
The Jabber function is only relevant in 10BASE-T mode.
3.4.6 Automatic Link Polarity Detection and Correction
The DP83846A's 10BASE-T transceiver module incorporates
an automatic link polarity detection circuit. When
seven consecutive inverted link pulses are received,
inverted polarity is reported.
Obsolete
24 www.national.com
DP83846A
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame
(MDF) or patch panel in the wiring closet.
The inverse polarity condition is latched in the 10BTSCR
register. The DP83846A's 10BASE-T transceiver module
corrects for this error internally and will continue to decode
received data correctly. This eliminates the need to correct
the wiring error immediately.
The user is cautioned that if Auto Polarity Detection and
Correction is disabled and inverted Polarity is detected but
not corrected, the DsPHYTER may falsely report Good
Link status and allow Transmission and Reception of
inverted data. It is recommended that Auto Polarity Detection
and Correction not be disabled during normal operation.
3.4.7 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83846A, as the required signal conditioning is integrated
into the device.
Only isolation/step-up transformers and impedance matching
resistors are required for the 10BASE-T transmit and
receive interface. The internal transmit filtering ensures
that all the harmonics in the transmit signal are attenuated
by at least 30 dB.
3.4.8 Transmitter
The encoder begins operation when the Transmit Enable
input (TX_EN) goes high and converts NRZ data to preemphasized
Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is
encoded for the transmit-driver pair (TD±). TXD must be
valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN deasserts. The last transition
is always positive; it occurs at the center of the bit cell
if the last bit is a one, or at the end of the bit cell if the last
bit is a zero.
3.4.9 Receiver
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data. The differential input must be externally
terminated with a differential 100Ω termination network
to accommodate UTP cable. The impedance of RD±
(typically 1.1KΩ) is in parallel with the two 54.9Ω resistors
as is shown in Figure 9 below to approximate the 100Ω
termination.
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit
times after the last bit, carrier sense is de-asserted.
3.5 TPI Network Circuit
Figure 9 shows the recommended circuit for a 10/100 Mb/s
twisted pair interface. Below is a partial list of recommended
transformers. Is is important that the user realize
that variations with PCB and component characteristics
requires that the application be tested to ensure that the
circuit meets the requirements of the intended application.
Pulse H1012B, PE-68515L
Halo TG22-S052ND
Valor PT4171
BELFUSE S558-5999-K2
BELFUSE S558-5999-46
Figure 9. 10/100 Mb/s Twisted Pair Interface
RJ45
RDRD+
TDTD+
RDRD+
TDTD+
1:1
49.9Ω 49.9 Ω
0.1μF*
T1
1:1
Common Mode Chokes may
be required.
54.9Ω 54.9Ω
0.1μF
0.1μF*
Vdd
* Place capacitors close to
the transformer center taps
Obsolete
25 www.national.com
DP83846A
3.6 ESD Protection
Typically, ESD precautions are predominantly in effect
when handling the devices or board before being installed
in a system. In those cases, strict handling procedures can
be implemented during the manufacturing process to
greatly reduce the occurrences of catastrophic ESD
events. After the system is assembled, internal components
are usually relatively immune from ESD events.
In the case of an installed Ethernet system however, the
network interface pins are still susceptible to external ESD
events. For example, a category 5 cable being dragged
across a carpet has the potential of developing a charge
well above the typical ESD rating of a semiconductor
device.
For applications where high reliability is required, it is recommended
that additional ESD protection diodes be added
as shown below. There are numerous dual series connected
diode pairs that are available specifically for ESD
protection. The level of protection will vary dependent upon
the diode ratings. The primary parameter that affects the
level of ESD protection is peak forward surge current. Typical
specifications for diodes intended for ESD protection
range from 500mA (Motorola BAV99LT1 single pair diodes)
to 12A (STM DA108S1 Quad pair array). The user should
also select diodes with low input capacitance to minimize
the effect on system performance.
Since performance is dependent upon components used,
board impedance characteristics, and layout, the circuit
should be completely tested to ensure performance to the
required levels.
Figure 10. Typical DP83846A Network Interface with additional ESD protection
RJ-45
DP83846A 10/100
TX±
RX±
Vcc
Pin 1
Pin 2
Pin 3
Pin 6
Diodes placed on
the device side of
the isolation
transformer
3.3V Vcc
Vcc Obsolete
26 www.national.com
DP83846A
3.7 Crystal Oscillator Circuit
The DsPHYTER supports an external CMOS level oscillator
source or a crystal resonator device. If an external clock
source is used, X1 should be tied to the clock source and
X2 should be left floating. In either case, the clock source
must be a 25 MHz 0.005% (50 PPM) CMOS oscillator, or a
25 MHz (50 PPM), parallel, 20 pF load crystal resonator.
Figure 11 below shows a typical connection for a crystal
resonator circuit. The load capacitor values will vary with
the crystal vendors; check with the vendor for the recommended
loads.
The oscillator circuit was designed to drive a parallel resonance
AT cut crystal with a maximum drive level of 500μW.
If a crystal is specified for a lower drive level, a current limiting
resistor should be placed in series between X2 and
the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 22 pF, and R1 should be set at 0Ω.
4.0 Reset Operation
The DP83846A can be reset either by hardware or software.
A hardware reset may be accomplished by asserting
the RESET pin after powering up the device (this is
required) or during normal operation when a reset is
needed. A software reset is accomplished by setting the
reset bit in the Basic Mode Control Register.
While either the hardware or software reset can be implemented
at any time after device initialization, a hardware
reset, as described in Section 4.1 must be provided upon
device power-up/initialization. Omitting the hardware reset
operation during the device power-up/initialization
sequence can result in improper device operation.
4.1 Hardware Reset
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 160 μs, to the
RESET pin during normal operation. This will reset the
device such that all registers will be reset to default values
and the hardware configuration values will be re-latched
into the device (similar to the power-up/reset operation).
4.2 Software Reset
A software reset is accomplished by setting the reset bit
(bit 15) of the Basic Mode Control Register (BMCR). The
period from the point in time when the reset bit is set to the
point in time when software reset has concluded is approximately
160 μs.
The software reset will reset the device such that all registers
will be reset to default values and the hardware configuration
values will be re-latched into the device (similar to
the power-up/reset operation). Software driver code should
wait 500 μs following a software reset before allowing further
serial MII operations with the DP83846A.
Figure 11. Crystal Oscillator Circuit
X1 X2
CL1 CL2
R1
Obsolete
27 www.national.com
DP83846A
5.0 Register Block
Table 6. Register Map
Offset
Access Tag Description
Hex Decimal
00h 0 RW BMCR Basic Mode Control Register
01h 1 RO BMSR Basic Mode Status Register
02h 2 RO PHYIDR1 PHY Identifier Register #1
03h 3 RO PHYIDR2 PHY Identifier Register #2
04h 4 RW ANAR Auto-Negotiation Advertisement Register
05h 5 RW ANLPAR Auto-Negotiation Link Partner Ability Register (Base Page)
05h 5 RW ANLPARNP Auto-Negotiation Link Partner Ability Register (Next Page)
06h 6 RW ANER Auto-Negotiation Expansion Register
07h 7 RW ANNPTR Auto-Negotiation Next Page TX
08h-Fh 8-15 RESERVED RESERVED
Extended Registers
10h 16 RO PHYSTS PHY Status Register
11h-13h 17-19 RESERVED RESERVED
14h 20 RW FCSCR False Carrier Sense Counter Register
15h 21 RW RECR Receive Error Counter Register
16h 22 RW PCSR PCS Sub-Layer Configuration and Status Register
17h 23 RW RESERVED RESERVED
18h 24 RW RESERVED RESERVED
19h 25 RW PHYCTRL PHY Control Register
1Ah 26 RW 10BTSCR 10Base-T Status/Control Register
1Bh 27 RW CDCTRL CD Test Control Register
1Ch-1Fh 28 RW RESERVED RESERVED Obsolete
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DP83846A
Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Basic Mode Control Register 00h BMCR Reset Loopback Speed Select
Auto-Neg
Enable
Power
down
Isolate Restart
Auto-Neg
Duplex Collision
Test
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Basic Mode Status Register 01h BMSR 100Base-
T4
100Base-
TX FDX
100Base-
TX HDX
10Base-
T
FDXx
10Base-
T
HDX
Reserved Reserved Reserved Reserved MF Preamble
Suppress
Auto-Neg
Complete
Remote
Fault
Auto-Neg
Ability
Link
Status
Jabber
Detect
Extended
Capability
PHY Identifier Register 1 02h PHYIDR1 OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB OUI MSB
PHY Identifier Register 2 03h PHYIDR2 OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
VNDR_
MDL
MDL_
REV
MDL_
REV
MDL_
REV
MDL_
REV
Auto-Negotiation Advertisement Register 04h ANAR Next Page
Ind
Reserved Remote
Fault
Reserved Reserved PAUSE T4 TX_FD TX 10_FD 10 Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Auto-Negotiation Link Partner Ability Register
(Base Page)
05h ANLPAR Next Page
Ind
ACK Remote
Fault
Reserved Reserved Reserved T4 TX_FD TX 10_FD 10 Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Protocol
Selection
Auto-Negotiation Link Partner Ability Register
Next Page
05h ANLPARNP Next Page
Ind
ACK Message
Page
ACK2 Toggle Code Code Code Code Code Code Code Code Code Code Code
Auto-Negotiation Expansion Register 06h ANER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PDF LP_NP_
ABLE
NP_
ABLE
PAGE_
RX
LP_AN_
ABLE
Auto-Negotiation Next Page TX Register 07h ANNPTR Next Page
Ind
Reserved Message
Page
ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE
RESERVED 08-0fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXTENDED REGISTERS
PHY Status Register 10h PHYSTS Reserved Reserved Rx Err
Latch
Polarity
Status
False Carrier
Sense
Signal Detect
Descram
Lock
Page
Receive
Reserved Remote
Fault
Jabber
Detect
Auto-Neg
Complete
Loopback
Status
Duplex
Status
Speed
Status
Link
Status
RESERVED 11-13h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
False Carrier Sense Counter Register 14h FCSCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT
Receive Error Counter Register 15h RECR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
RXERCNT
PCS Sub-Layer Configuration and Status
Register
16h PCSR Reserved Reserved Reserved BYP_
4B5B
FREE_
CLK
TQ_EN SD_FOR
CE_PMA
SD_
OPTION
Unused Reserved FORCE_
100_OK
Reserved Reserved NRZI_
BYPASS
SCRAM_
BYPASS
DE
SCRAM_
BYPASS
RESERVED 17-18h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PHY Control Register 19h PHYCTRL Unused Unused Unused Unused PSR_15 BIST_
STATUS
BIST_
START
BP_
STRETC
H
PAUSE_
STS
LED_
CNFG
LED_
CNFG
PHY
ADDR
PHY
ADDR
PHY
ADDR
PHY
ADDR
PHY
ADDR
10Base-T Status/Control Register 1Ah 10BTSCR Unused Unused Unused Unused Unused Unused Unused Loopback
_10_dis
LP_DIS Force_
Link_10
Force_
Pol_Cor
Polarity Autopol
_Dis
Reserved Hrtbeat
_Dis
Jabber
_Dis
CD Test Control Register 1Bh CDCTRL CD_Enabl
e
DCD_
Comp
FIL_TTL rise-
Time[1]
rise-
Time[0]
fallTime[1] fallTime[0] cdTestEn Reserved Reserved Reserved cdPattEn_
10
cdPatEn_
100
10meg_
patt_gap
cdPatt-
Sel[1]
cdPatt-
Sel[0]
RESERVED 1C-1Fh Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Obsolete
29 www.national.com
DP83846A
5.1 Register Definition
In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW=Read Write access
— SC=Register sets on event occurrence and Self-Clears when event ends
— RW/SC =Read Write access/Self Clearing bit
— RO=Read Only access
— COR = Clear on Read
— RO/COR=Read Only, Clear on Read
— RO/P=Read Only, Permanently set to a default value
— LL=Latched Low and held until read, based upon the occurrence of the corresponding event
— LH=Latched High and held until read, based upon the occurrence of the corresponding event
Obsolete
30 www.national.com
DP83846A
Table 7. Basic Mode Control Register (BMCR), Address 0x00
Bit Bit Name Default Description
15 Reset 0, RW/SC Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset process is
complete. The configuration is re-strapped.
14 Loopback 0, RW Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII receive
data path.
Setting this bit may cause the descrambler to lose synchronization and produce a
500 μs “dead time” before any valid data will appear at the MII receive outputs.
13 Speed Selection Strap, RW Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100 Mb/s.
0 = 10 Mb/s.
12 Auto-Negotiation
Enable
Strap, RW Auto-Negotiation Enable:
Strap controls initial value at reset.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this
bit is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex
mode.
11 Power Down 0, RW Power Down:
1 = Power down.
0 = Normal operation.
Setting this bit powers down the PHY. Only the register block is enabled during a
power down condition.
10 Isolate 0, RW Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
9 Restart Auto-
Negotiation
0, RW/SC Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-
Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and
will return a value of 1 until Auto-Negotiation is initiated, whereupon it will selfclear.
Operation of the Auto-Negotiation process is not affected by the management
entity clearing this bit.
0 = Normal operation.
8 Duplex Mode Strap, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability
to be selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response to the assertion
of TX_EN within 512-bit times. The COL signal will be de-asserted within
4-bit times in response to the de-assertion of TX_EN.
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.
Obsolete
31 www.national.com
DP83846A
Table 8. Basic Mode Status Register (BMSR), address 0x01
Bit Bit Name Default Description
15 100BASE-T4 0, RO/P 100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
14 100BASE-TX
Full Duplex
1, RO/P 100BASE-TX Full Duplex Capable:
1 = Device able to perform 100BASE-TX in full duplex mode.
13 100BASE-TX
Half Duplex
1, RO/P 100BASE-TX Half Duplex Capable:
1 = Device able to perform 100BASE-TX in half duplex mode.
12 10BASE-T
Full Duplex
1, RO/P 10BASE-T Full Duplex Capable:
1 = Device able to perform 10BASE-T in full duplex mode.
11 10BASE-T
Half Duplex
1, RO/P 10BASE-T Half Duplex Capable:
1 = Device able to perform 10BASE-T in half duplex mode.
10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0.
6 MF P reamble
Suppression
1, RO/P Preamble suppression Capable:
1 = Device able to perform management transaction with preamble
suppressed, 32-bits of preamble needed only once after reset, invalid
opcode or invalid turnaround.
0 = Normal management operation.
5 Auto-Negotiation
Complete
0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.
4 Remote Fault 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset).
Fault criteria: Far End Fault Indication or notification from Link Partner
of Remote Fault.
0 = No remote fault condition detected.
3 Auto-Negotiation
Ability
1, RO/P Auto Negotiation Ability:
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
2 Link Status 0, RO/LL Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
The criteria for link validity is implementation specific. The occurrence
of a link failure condition will causes the Link Status bit to clear. Once
cleared, this bit may only be set by establishing a good link condition
and a read via the management interface.
1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occurrence
of a jabber condition causes it to set until it is cleared by a read
to this register by the management interface or by a reset.
0 Extended Capability
1, RO/P Extended Capability:
1 = Extended register capabilities.
0 = Basic register set capabilities only.
Obsolete
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DP83846A
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83846A. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number.
A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit Bit Name Default Description
15:0 OUI_MSB <0010 0000 0000
0000>, RO/P
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Table 10. PHY Identifier Register #2 (PHYIDR2), address 0x03
Bit Bit Name Default Description
15:10 OUI_LSB <01 0111>, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10 of
this register respectively.
9:4 VNDR_MDL <00 0010>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped to bits 9 to 4
(most significant bit to bit 9).
3:0 MDL_REV <0011>, RO/P Model Revision Number:
Four bits of the vendor model revision number are mapped to bits
3 to 0 (most significant bit to bit 3). This field will be incremented for
all major device changes. Obsolete
33 www.national.com
DP83846A
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation.
Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0.
13 RF 0, RW Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12:11 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0
10 PAUSE Strap, RW PAUSE: The default is set by the strap option for PAUSE_EN pin.
1 = Advertise that the DTE (MAC) has implemented both the optional
MAC control sublayer and the pause function as specified in
clause 31 and annex 31B of 802.3u.
0= No MAC based full duplex flow control.
9 T4 0, RO/P 100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device.
0 = 100BASE-T4 not supported.
8 TX_FD Strap, RW 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7 TX Strap, RW 100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
6 10_FD Strap, RW 10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the local device.
0 = 10BASE-T Full Duplex not supported.
5 10 Strap, RW 10BASE-T Support:
1 = 10BASE-T is supported by the local device.
0 = 10BASE-T not supported.
4:0 Selector <00001>, RW Protocol Selection Bits:
These bits contain the binary encoded protocol selector supported
by this port. <00001> indicates that this device supports IEEE
802.3u.
Obsolete
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DP83846A
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content
changes after the successful auto negotiation if Next-pages are supported.
Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05
Bit Bit Name Default Description
15 NP 0, RO Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Device's Auto-Negotiation state machine will automatically
control the this bit based on the incoming FLP bursts.
13 RF 0, RO Remote Fault:
1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.
12:10 RESERVED 0, RO RESERVED for Future IEEE use:
Write as 0, read as 0.
9 T4 0, RO 100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.
8 TX_FD 0, RO 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.
7 TX 0, RO 100BASE-TX Support:
1 = 100BASE-TX is supported by the Link Partner.
0 = 100BASE-TX not supported by the Link Partner.
6 10_FD 0, RO 10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the Link Partner.
0 = 10BASE-T Full Duplex not supported by the Link Partner.
5 10 0, RO 10BASE-T Support:
1 = 10BASE-T is supported by the Link Partner.
0 = 10BASE-T not supported by the Link Partner.
4:0 Selector <0 0000>, RO Protocol Selection Bits:
Link Partner’s binary encoded protocol selector.
Obsolete
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DP83846A
This register contains additional Local Device and Link Partner status information.
Table 13. Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page, address 0x05
Bit Bit Name Default Description
15 NP 0, RO Next Page Indication:
1 = Link Partner desires Next Page Transfer.
0 = Link Partner does not desire Next Page Transfer.
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Device's Auto-Negotiation state machine will automatically
control the this bit based on the incoming FLP bursts. Software
should not attempt to write to this bit.
13 MP 0, RO Message Page:
1 = Message Page.
0 = Unformatted Page.
12 ACK2 0, RO Acknowledge 2:
1 = Link Partner does have the ability to comply to next page message.
0 = Link Partner does not have the ability to comply to next page
message.
11 Toggle 0, RO Toggle:
1 = Previous value of the transmitted Link Code word equalled 0.
0 = Previous value of the transmitted Link Code word equalled 1.
10:0 CODE <000 0000 0000>,
RO
Code:
This field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a “Message Page”, as defined in annex 28C of
Clause 28. Otherwise, the code shall be interpreted as an “Unformatted
Page”, and the interpretation is application specific.
Table 14. Auto-Negotiate Expansion Register (ANER), address 0x06
Bit Bit Name Default Description
15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
4 PDF 0, RO/LH/COR Parallel Detection Fault:
1 = A fault has been detected via the Parallel Detection function.
0 = A fault has not been detected.
3 LP_NP_ABLE 0, RO Link Partner Next Page Able:
1 = Link Partner does support Next Page.
0 = Link Partner does not support Next Page.
2 NP_ABLE 1, RO/P Next Page Able:
1 = Indicates local device is able to send additional “Next Pages”.
1 PAGE_RX 0, RO/LH/COR Link Code Word Page Received:
1 = Link Code Word has been received, cleared on a read.
0 = Link Code Word has not been received.
0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:
1 = indicates that the Link Partner supports Auto-Negotiation.
0 = indicates that the Link Partner does not support Auto-Negotiation.
Obsolete
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DP83846A
This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
13 MP 1, RW Message Page:
1 = Message Page.
0 = Unformatted Page.
12 ACK2 0, RW Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate that Local
Device has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word
was 0.
0 = Value of toggle bit in previously transmitted Link Code Word
was 1.
Toggle is used by the Arbitration function within Auto-Negotiation
to ensure synchronization with the Link Partner during Next Page
exchange. This bit shall always take the opposite value of the Toggle
bit in the previously exchanged Link Code Word.
10:0 CODE <000 0000 0001>,
RW
This field represents the code field of the next page transmission.
If the MP bit is set (bit 13 of this register), then the code shall be
interpreted as a "Message Page”, as defined in annex 28C of IEEE
802.3u. Otherwise, the code shall be interpreted as an "Unformatted
Page”, and the interpretation is application specific.
The default value of the CODE represents a Null Page as defined
in Annex 28C of IEEE 802.3u.
Obsolete
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DP83846A
5.2 Extended Registers
This register provides a single location within the register set for quick access to commonly accessed information.
Table 16. PHY Status Register (PHYSTS), address 0x10
Bit Bit Name Default Description
15:14 RESERVED 0, RO RESERVED: Write ignored, read as 0.
13 Receive Error Latch 0, RO/LH Receive Error Latch:
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT
(address 0x15, Page 0).
0 = No receive error event has occurred.
12 Polarity Status 0, RO Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will
be cleared upon a read of the 10BTSCR register, but not upon a
read of the PHYSTS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11 False Carrier Sense
Latch
0, RO/LH False Carrier Sense Latch:
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event has occurred since last read of FCSCR (address
0x14).
0 = No False Carrier event has occurred.
10 Signal Detect 0, RO/LL 100Base-TX unconditional Signal Detect from PMD.
9 Descrambler Lock 0, RO/LL 100Base-TX Descrambler Lock from PMD.
8 Page Received 0, RO Link Code Word Page Received:
This is a duplicate of the Page Received bit in the ANER register,
but this bit will not be cleared upon a read of the PHYSTS register.
1 = A new Link Code Word Page has been received. Cleared on
read of the ANER (address 0x06, bit 1).
0 = Link Code Word Page has not been received.
Obsolete
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DP83846A
7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
6 Remote Fault 0, RO Remote Fault:
1 = Remote Fault condition detected (cleared on read of BMSR (address
01h) register or by reset). Fault criteria: notification from Link
Partner of Remote Fault via Auto-Negotiation.
0 = No remote fault condition detected.
5 Jabber Detect 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode
This bit is a duplicate of the Jabber Detect bit in the BMSR register,
except that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
4 Auto-Neg Complete 0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
3 Loopback Status 0, RO Loopback:
1 = Loopback enabled.
0 = Normal operation.
2 Duplex Status 0, RO Duplex:
This bit indicates duplex status and is determined from Auto-Negotiation
or Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete
and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
1 Speed Status 0, RO Speed10:
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete
and there is a valid link or if Auto-Negotiation is disabled and
there is a valid link.
0 Link Status 0, RO Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register,
except that it will no be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued)
Bit Bit Name Default Description
Obsolete
39 www.national.com
DP83846A
This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.
This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY managed
object class of Clause 30 of the IEEE 802.3u specification.
Table 17. False Carrier Sense Counter Register (FCSCR), address 0x14
Bit Bit Name Default Description
15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
7:0 FCSCNT[7:0] 0, RW / COR False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This
counter sticks when it reaches its max count (FFh).
Table 18. Receiver Error Counter Register (RECR), address 0x15
Bit Bit Name Default Description
15:8 RESERVED 0, RO RESERVED: Writes ignored, Read as 0
7:0 RXERCNT[7:0] 0, RW / COR RX_ER Counter:
This 8-bit counter increments for each receive error detected.
When a valid carrier is present and there is at least one occurrence
of an invalid data symbol. This event can increment only once per
valid carrier event. If a collision is present, the attribute will not increment.
The counter sticks when it reaches its max count.
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16
Bit Bit Name Default Description
15:13 RESERVED <00>, RO RESERVED: Writes ignored, Read as 0.
12 BYP_4B5B 0, RW Bypass 4B/5B Encoding:
1 = 4B5B encoder functions bypassed.
0 = Normal 4B5B operation.
11 FREE_CLK 0, RW Receive Clock:
1 = RX_CK is free-running.
0 = RX_CK phase adjusted based on alignment.
10 TQ_EN 0, RW 100Mbs True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
9 SD FORCE PMA 0, RW Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
8 SD_OPTION 1, RW Signal Detect Option:
1 = Enhanced signal detect algorithm.
0 = Reduced signal detect algorithm.
Obsolete
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DP83846A
7 Unused 0,RO
6 RESERVED 0 RESERVED:
Must be zero.
5 FORCE_100_OK 0, RW Force 100Mb/s Good Link:
1 = Forces 100Mb/s Good Link.
0 = Normal 100Mb/s operation.
4 RESERVED 0 RESERVED:
Must be zero.
3 RESERVED 0 RESERVED:
Must be zero.
2 NRZI_BYPASS 0, RW NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1 SCRAM_BYPASS 0, RW Scrambler Bypass Enable:
1 = Scrambler Bypass Enabled.
0 = Scrambler Bypass Disabled.
0 DESCRAM_BYPA
SS
0, RW Descrambler Bypass Enable:
1 = Descrambler Bypass Enabled.
0 = Descrambler Bypass Disabled.
Table 20. Reserved Registers, addresses 0x17, 0x18
Bit Bit Name Default Description
15:0 RESERVED none, RW RESERVED: Must not be written to during normal operation.
Table 19. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 (Continued)
Bit Bit Name Default Description
Obsolete
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DP83846A
Table 21. PHY Control Register (PHYCTRL), address 0x19
Bit Bit Name Default Description
15:12 Unused 0, RO
11 PSR_15 0, RW BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
10 BIST_STATUS 0, RO/LL BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared by write to BIST_ START bit.
9 BIST_START 0, RW BIST Start:
1 = BIST start.
0 = BIST stop.
8 BP_STRETCH 0, RW Bypass LED Stretching:
This will bypass the LED stretching for the Receive, Transmit and
Collision LEDs.
1 = Bypass LED stretching.
0 = Normal operation.
7 PAUSE_STS 0, RO Pause Compare Status:
0 = Local Device and the Link Partner are not Pause capable.
1 = Local Device and the Link Partner are both Pause capable.
6 RESERVED 1, RO/P Reserved: Must be 1.
5 LED_CNFG Strap, RW This bit is used to bypass the selective inversion on the LED output
for DPLX - this enables its use in non-LED applications.
Mode Description
1 = Led polarity adjusted - DPLX selected.
0 = DPLX active HIGH.
4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port.
Obsolete
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DP83846A
Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A
Bit Bit Name Default Description
15:9 Unused 0, RO
8 LOOPBACK_10_DIS 0, RW 10BASE-T Loopback Disable:
If bit 14 (Loopback) in the BMCR is 0:
1 = 10 Mb/s Loopback is disabled.
If bit 14 (Loopback) in the BMCR is 1:
1 = 10 Mb/s Loopback is enabled.
7 LP_DIS 0, RW Normal Link Pulse Disable:
1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.
6 FORCE_LINK_10 0, RW Force 10Mb Good Link:
1 = Forced Good 10Mb Link.
0 = Normal Link Status.
5 FORCE_POL_COR 0, RW Force 10Mb Polarity Correction:
1 = Force inverted polarity.
0 = Normal polarity.
4 POLARITY RO/LH 10Mb Polarity Status:
This bit is a duplication of bit 12 in the PHYSTS register. Both bits
will be cleared upon a read of 10BTSCR register, but not upon a
read of the PHYSIS register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
3 AUTOPOL_DIS 0, RW Auto Polarity Detection & Correction Disable:
1 = Polarity Sense & Correction disabled.
0 = Polarity Sense & Correction enabled.
2 RESERVED 1, RW RESERVED:
Must be set to one.
1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has influence in half-duplex 10Mb
mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
When the device is operating at 100Mb or configured for full
duplex operation, this bit will be ignored - the heartbeat function
is disabled.
0 JABBER_DIS 0, RW Jabber Disable:
Applicable only in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
Obsolete
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DP83846A
Table 23. CD Test Register (CDCTRL), Address 0x1B
Bit Bit Name Default Description
15 CD_ENABLE 1, RW CD Enable:
1 = CD Enabled - power-down mode, outputs high impedance.
0 = CD Disabled.
14 DCDCOMP 0, RW Duty Cycle Distortion Compensation:
1 = Increases the amount of DCD compensation.
13 FIL_TTL 0, RW Waveshaper Current Source Test:
To check ability of waveshaper current sources to switch on/off.
1 = Test mode; waveshaping is done, but the output is a square
wave. All sources are either on or off.
0 = Normal mode; sinusoidal.
12 RESERVED none, RW Reserved: This bit should be written with a 0 if write access is required
on this register.
11 RISETIME Strap, RW CD Rise Time Control:
10 RESERVED none, RW Reserved: This bit should be written with a 0 if write access is required
on this register.
9 FALLTIME Strap, RW CD Fall Time Control:
8 CDTESTEN 0, RW CD Test Mode Enable:
1 = Enable CD test mode - differs based on speed of operation
(10/100Mb).
0 = Normal operation.
7:5 RESERVED[2:0] 000, RW RESERVED:
Must be zero.
4 CDPATTEN_10 0, RW CD Pattern Enable for 10meg:
1 = Enabled.
0 = Disabled.
3 CDPATTEN_100 0, RW CD Pattern Enable for 100meg:
1 = Enabled.
0 = Disabled.
2 10MEG_PATT_GAP 0, RW Defines gap between data or NLP test sequences:
1 = 15 μs.
0 = 10 μs.
1:0 CDPATTSEL[1:0] 00, RW CD Pattern Select[1:0]:
If CDPATTEN_100 = 1:
00 = All 0’s (True quiet)
01 = All 1’s
10 = 2 1’s, 2 0’s repeating pattern
11 = 14 1’s, 6 0’s repeating pattern
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence
01 = Data, EOP1 sequence
10 = NLPs
11 = Constant Manchester 1s (10mhz sine wave) for harmonic distortion
testing.
Obsolete
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DP83846A
6.0 Electrical Specifications
Absolute Maximum Ratings Recommended Operating Conditions
Absolute maximum ratings are those values beyond which
the safety of the device cannot be guaranteed. They are
not meant to imply that the device should be operated at
these limits.
Note:0 DC Electrical Specification
Supply Voltage (VCC) -0.5 V to 4.2 V
DC Input Voltage (VIN) -0.5V to 5.5V
DC Output Voltage (VOUT) -0.5V to 5.5V
Storage Temperature (TSTG) -65oC to 150°C
Lead Temp. (TL)
(Soldering, 10 sec)
260°C
ESD Rating
(RZAP = 1.5k, CZAP = 120 pF)
1.0 kV
Supply voltage (VCC) 3.3 Volts + 0.3V
Ambient Temperature (TA) 0 to 70 °C
Max. die temperature (Tj) 107°C
Max case temp 96°C
Thermal Characteristic Max Units
Theta Junction to Case (Tjc) 15 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0W 51 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 225 LFPM Airflow @ 1.0W 42 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 500 LFPM Airflow @ 1.0W 37 °C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - 900 LFPM Airflow @ 1.0W 33 °C / W
Symbol Pin Types Parameter Conditions Min Typ Max Units
VIH I
I/O
Input High Voltage Nominal VCC 2.0 V
VIL I
I/O
Input Low Voltage 0.8 V
IIH I
I/O
Input High Current VIN = VCC 10 μA
IIL I
I/O
Input Low Current VIN = GND 10 μA
VOL O,
I/O
Output Low
Voltage
IOL = 4 mA 0.4 V
VOH O,
I/O
Output High
Voltage
IOH = -4 mA VCC - 0.5 V
VledOL LED Output Low
Voltage
* IOL = 2.5 mA 0.4 V
VledOH LED Output High
Voltage
IOH = -2.5 mA VCC - 0.5 V
IOZH I/O,
O
TRI-STATE
Leakage
VOUT = VCC 10 μA
I5IH I/O,
O
5 Volt Tolerant
MII Leakage
VIN = 5.25 V 10 μA
I5OZH I/O,
O
5 Volt Tolerant
MII Leakage
VOUT = 5.25 V 10 μA
RINdiff RD+/− Differential Input
Resistance
1.1 kΩ
VTPTD_100 TD+/− 100M Transmit
Voltage
.95 1 1.05 V
Obsolete
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DP83846A
Note: For Idd Measurements, outputs are not loaded.
VTPTDsym TD+/− 100M Transmit
Voltage Symmetry
±2 %
VTPTD_10 TD+/− 10M Transmit
Voltage
2.2 2.5 2.8 V
CIN1 I CMOS Input
Capacitance
Parameter is not
100% tested
8 pF
SDTHon RD+/− 100BASE-TX
Signal detect turnon
threshold
1000 mV diff pk-pk
SDTHoff RD+/− 100BASE-TX
Signal detect turnoff
threshold
200 mV diff pk-pk
VTH1 RD+/− 10BASE-T Receive
Threshold
300 585 mV
Idd100 Supply 100BASE-TX
(Full Duplex)
IOUT = 0 mA
See Note
150 200 mA
Idd10 Supply 10BASE-T
(Full Duplex)
IOUT = 0 mA
See Note
100 130 mA
Symbol Pin Types Parameter Conditions Min Typ Max Units
Obsolete
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DP83846A
6.1 Reset Timing
Note1: Software Reset should be initiated no sooner then 500 μs after power-up or the deassertion of hardware reset.
Note2: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide
fast RC time constants in order to latch-in the proper value prior to the pin transitioning to an output driver.
Parameter Description Notes Min Typ Max Units
T1.0.1 Post RESET Stabilization time
prior to MDC preamble for register
accesses
MDIO is pulled high for 32-bit serial
management initialization
3 μs
T1.0.2 Hardware Configuration Latch-in
Time from the Deassertion of RESET
(either soft or hard)
Hardware Configuration Pins are
described in the Pin Description
section
3 μs
T1.0.3 Hardware Configuration pins
transition to output drivers
3.5 μs
T1.0.4 RESET pulse width X1 Clock must be stable for a
minimum of 160us during RESET
pulse low time.
160 μs
VCC
HARDWARE
RSTN
MDC
32 CLOCKS
Latch-In of Hardware
Configuration Pins
Dual Function Pins
Become Enabled As Outputs
INPUT OUTPUT
T1.0.3
T1.0.2
T1.0.1
T1.0.4
X1 Clock
Obsolete
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DP83846A
6.2 PGM Clock Timing
6.3 MII Serial Management Timing
Parameter Description Notes Min Typ Max Units
T2.0.1 TX_CLK Duty Cycle 35 65 %
Parameter Description Notes Min Typ Max Units
T3.0.1 MDC to MDIO (Output) Delay Time 0 300 ns
T3.0.2 MDIO (Input) to MDC Setup Time 10 ns
T3.0.3 MDIO (Input) to MDC Hold Time 10 ns
T3.0.4 MDC Frequency 2.5 MHz
TX_CLK
X1
T2.0.1
MDC
MDC
MDIO (output)
MDIO (input) Valid Data
T3.0.1
T3.0.2 T3.0.3
T3.0.4 Obsolete
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DP83846A
6.4 100 Mb/s Timing
6.4.1 100 Mb/s MII Transmit Timing
6.4.2 100 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to
TX_CLK
10 ns
T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from
TX_CLK
5 ns
Parameter Description Notes Min Typ Max Units
T4.2.1 RX_CLK Duty Cycle 35 65 %
T4.2.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 10 30 ns
TX_CLK
TXD[3:0]
TX_EN
TX_ER
Valid Data
T4.1.1 T4.1.2
RX_CLK
RXD[3:0]
RX_DV
RX_ER Valid Data
T4.2.2
T4.2.1
Obsolete
49 www.national.com
DP83846A
6.4.3 100BASE-TX Transmit Packet Latency Timing
Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the TD± pins.
6.4.4 100BASE-TX Transmit Packet Deassertion Timing
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion
of TX_EN to the first bit of the “T” code group as output from the TD± pins.
Parameter Description Notes Min Typ Max Units
T4.3.1 TX_CLK to TD± Latency 6.0 bit times
Parameter Description Notes Min Typ Max Units
T4.4.1 TX_CLK to TD± Deassertion 6.0 bit times
TX_CLK
TX_EN
TXD
TD± IDLE (J/K) DATA
T4.3.1
TX_CLK
TXD
TX_EN
TD± DATA (T/R) IDLE
T4.4.1
DATA (T/R) IDLE
Obsolete
50 www.national.com
DP83846A
6.4.5 100BASE-TX Transmit Timing (tR/F & Jitter)
Note1: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
Note2: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
Parameter Description Notes Min Typ Max Units
T4.5.1 100 Mb/s TD± tR and tF 3 4 5 ns
100 Mb/s tR and tF Mismatch 500 ps
T4.5.2 100 Mb/s TD± Transmit Jitter 1.4 ns
TD±
T4.5.1
T4.5.1 T4.5.1
T4.5.1
+1 rise
+1 fall
-1 fall -1 rise
TD±
eye pattern
T4.5.2
T4.5.2
90%
10%
10%
90% Obsolete
51 www.national.com
DP83846A
6.4.6 100BASE-TX Receive Packet Latency Timing
Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion
of Carrier Sense.
Note: RD± voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
6.4.7 100BASE-TX Receive Packet Deassertion Timing
Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion
of Carrier Sense.
Parameter Description Notes Min Typ Max Units
T4.6.1 Carrier Sense ON Delay 17.5 bit times
T4.6.2 Receive Data Latency 21 bit times
Parameter Description Notes Min Typ Max Units
T4.7.1 Carrier Sense OFF Delay 21.5 bit times
CRS
RXD[3:0]
RD±
RX_DV
RX_ER/RXD[4]
IDLE Data
T4.6.1
T4.6.2
(J/K)
CRS
T4.7.1
RXD[3:0]
RX_DV
RX_ER/RXD[4]
RD± DATA IDLE (T/R) Obsolete
52 www.national.com
DP83846A
6.5 10 Mb/s Timing
6.5.1 10 Mb/s MII Transmit Timing
6.5.2 10 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T5.1.1 TXD[3:0], TX_EN Data Setup to TX_CLK 25 ns
T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 5 ns
Parameter Description Notes Min Typ Max Units
T5.2.1 RX_CLK Duty Cycle 35 65 %
T5.2.2 RX_CLK to RXD[3:0], RX_DV 190 210 ns
TX_CLK
TXD[3:0]
TX_EN Valid Data
T5.1.1 T5.1.2
RX_CLK
RXD[3:0]
Valid Data
T5.2.2
T5.2.1
RX_DV
Obsolete
53 www.national.com
DP83846A
6.5.3 10BASE-T Transmit Timing (Start of Packet)
6.5.4 10BASE-T Transmit Timing (End of Packet)
Parameter Description Notes Min Typ Max Units
T5.3.1 Transmit Enable Setup Time from the
Falling Edge of TX_CLK
25 ns
T5.3.2 Transmit Data Setup Time from the
Falling Edge of TX_CLK
25 ns
T5.3.3 Transmit Data Hold Time from the
Falling Edge of TX_CLK
5 ns
T5.3.4 Transmit Output Delay from the
Falling Edge of TX_CLK
6.8 bit times
Parameter Description Notes Min Typ Max Units
T5.4.1 Transmit Enable Hold Time from the
Falling Edge of TX_CLK
5 ns
T5.4.2 End of Packet High Time
(with ‘0’ ending bit)
250 ns
T5.4.3 End of Packet High Time
(with ‘1’ ending bit)
250 ns
TX_CLK
TX_EN
TXD[0]
TPTD±
T5.3.1
T5.3.2
T5.3.3
T5.3.4
TX_CLK
TX_EN
TPTD±
0 0
1 1
TPTD±
T5.4.2
T5.4.3
T5.4.1 Obsolete
54 www.national.com
DP83846A
6.5.5 10BASE-T Receive Timing (Start of Packet)
Note: 10BASE-T receive Data Latency is measured from first bit of preamble on the wire to the assertion of RX_DV.
6.5.6 10BASE-T Receive Timing (End of Packet)
Parameter Description Notes Min Typ Max Units
T5.5.1 Carrier Sense Turn On Delay
(TPRD± to CRS)
1 μs
T5.5.2 Decoder Acquisition Time 3.6 μs
T5.5.3 Receive Data Latency 17.3 bit times
T5.5.4 SFD Propagation Delay 10 bit times
Parameter Description Notes Min Typ Max Units
T5.6.1 Carrier Sense Turn Off Delay 1.1 μs
1 0 1
TPRD±
CRS
RX_CLK
RXD[0]
1st SFD bit decoded
RX_DV
T5.5.1
T5.5.2
T5.5.3
T5.5.4
1 0 1
TPRD±
RX_CLK
CRS
IDLE
T5.6.1
Obsolete
55 www.national.com
DP83846A
6.5.7 10 Mb/s Heartbeat Timing
6.5.8 10 Mb/s Jabber Timing
6.5.9 10BASE-T Normal Link Pulse Timing
Parameter Description Notes Min Typ Max Units
T5.7.1 CD Heartbeat Delay 600 1600 ns
T5.7.2 CD Heartbeat Duration 500 1500 ns
Parameter Description Notes Min Typ Max Units
T5.8.1 Jabber Activation Time 20 150 ms
T5.8.2 Jabber Deactivation Time 250 750 ms
Parameter Description Notes Min Typ Max Units
T5.9.1 Pulse Width 100 ns
T5.9.2 Pulse Period 8 16 24 ms
TXC
TXE
COL
T5.7.1
T5.7.2
TXE
TPTD±
COL
T5.8.2
T5.8.1
T5.9.2
T5.9.1
Normal Link Pulse(s)Obsolete
56 www.national.com
DP83846A
6.5.10 Auto-Negotiation Fast Link Pulse (FLP) Timing
6.5.11 100BASE-TX Signal Detect Timing
Note: The signal amplitude at RD± is TP-PMD compliant.
Parameter Description Notes Min Typ Max Units
T5.10.1 Clock, Data Pulse Width 100 ns
T5.10.2 Clock Pulse to Clock Pulse
Period
111 125 139 μs
T5.10.3 Clock Pulse to Data Pulse
Period
Data = 1 55.5 69.5 μs
T5.10.4 Number of Pulses in a Burst 17 33 #
T5.10.5 Burst Width 2 ms
T5.10.6 FLP Burst to FLP Burst Period 8 24 ms
Parameter Description Notes Min Typ Max Units
T5.11.1 SD Internal Turn-on Time 1 ms
T5.11.2 SD Internal Turn-off Time 300 μs
clock
pulse
data
pulse
clock
pulse
FLP Burst FLP Burst
Fast Link Pulse(s)
T5.10.1
T5.10.1
T5.10.2
T5.10.3
T5.10.4 T5.10.5
T5.10.6
T5.11.1
SD+ internal
T5.11.2
RD± Obsolete
57 www.national.com
DP83846A
6.6 Loopback Timing
6.6.1 100 Mb/s Internal Loopback Mode
Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 μs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550μs “dead-time”.
Note2: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
Parameter Description Notes Min Typ Max Units
T6.1.1 TX_EN to RX_DV Loopback 240 ns
TX_CLK
TX_EN
TXD[3:0]
CRS
RX_CLK
RXD[3:0]
RX_DV
T6.1.1
Obsolete
58 www.national.com
DP83846A
6.6.2 10 Mb/s Internal Loopback Mode
Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN.
Parameter Description Notes Min Typ Max Units
T6.2.1 TX_EN to RX_DV Loopback 2 μs
TX_CLK
TX_EN
TXD[3:0]
CRS
RX_CLK
RXD[3:0]
RX_DV
T6.2.1
Obsolete
59 www.national.com
DP83846A
6.7 Isolation Timing
Parameter Description Notes Min Typ Max Units
T7.0.1 From software clear of bit 10 in
the BMCR register to the transition
from Isolate to Normal Mode
100 μs
T7.0.2 From Deassertion of S/W or H/W
Reset to transition from Isolate to
Normal mode
500 μs
Clear bit 10 of BMCR
(return to normal operation
from Isolate mode)
H/W or S/W Reset
(with PHYAD = 00000)
MODE
ISOLATE NORMAL
T7.0.2
T7.0.1
Obsolete
DP83846A DsPHYTER — Single 10/100 Ethernet Transceiver
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Tel: 1-800-272-9959
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Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
www.national.com
7.0 Physical Dimensions
Plastic Quad Flat Pack (LQFP)
Order Number DP83846AVHG
NS Package Number VHG-80A Obsolete
IMPORTANT NOTICE
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Mar 9, 2013
1
Product data sheet
Characteristics
XPSAF5130
module XPSAF - Emergency stop - 24 V AC
DC
Main
Range of product Preventa Safety automation
Product or component
type
Preventa safety module
Safety module name XPSAF
Safety module application
For emergency stop and switch monitoring
Function of module Monitoring of a movable guard
Emergency stop monitoring 1-channel wiring
Emergency stop monitoring 2-channel wiring
Safety level Can reach SILCL 3 conforming to EN/IEC 62061
Can reach PL e/category 4 conforming to EN/ISO
13849-1
Safety reliability data PFHd = 4.62E-9 1/h conforming to EN/IEC 62061
MTTFd = 243 years conforming to EN/ISO 13849-1
DC > 99 % conforming to EN/ISO 13849-1
Type of start Configurable
Connections - terminals Captive screw clamp terminals (2 x 0.5...2 x 1.5
mm²)flexible cable with cable end, with double bezel
Captive screw clamp terminals (2 x 0.25...2 x 1
mm²)flexible cable with cable end, with double bezel
Captive screw clamp terminals (2 x 0.14...2 x 0.75
mm²)solid cable with cable end, with double bezel
Captive screw clamp terminals (2 x 0.14...2 x 0.75
mm²)flexible cable with cable end, with double bezel
Captive screw clamp terminals (1 x 0.25...1 x 2.5
mm²)flexible cable with cable end, with double bezel
Captive screw clamp terminals (1 x 0.25...1 x 1.5
mm²)flexible cable with cable end, with double bezel
Captive screw clamp terminals (1 x 0.14...1 x 2.5
mm²)solid cable with cable end, with double bezel
Captive screw clamp terminals (1 x 0.14...1 x 2.5
mm²)flexible cable with cable end, with double bezel
Output type Relay instantaneous opening 3 NO, volt-free
Number of additional
circuits
0
[Us] rated supply voltage
24 V DC (- 15...10 %)
24 V AC (- 15...10 %)
Complementary
Synchronisation time between inputs Unlimited
Supply frequency 50/60 Hz
Power consumption in VA <= 5 VA AC
Input protection type Internal, electronic
Control circuit voltage 24 V
Line resistance 90 Ohm
Breaking capacity C300: 1800 VA, AC-15 (inrush) for relay output
C300: 180 VA, AC-15 (holding) for relay output
Breaking capacity 1.5 A at 24 V (DC-13) time constant: 50 ms for relay output
Output thermal current 6 A per relay for relay output
[Ith] conventional free air thermal current 18 A
Associated fuse rating 6 A fuse type fast blow for relay output conforming to EN/IEC 60947-5-1, DIN
VDE 0660 part 200
4 A fuse type gG or gL for relay output conforming to EN/IEC 60947-5-1, DIN
VDE 0660 part 200
Minimum output current 10 mA for relay output
Minimum output voltage 17 V for relay output
2
Response time on input open <= 40 ms
[Ui] rated insulation voltage 300 V (degree of pollution: 2) conforming to IEC 60647-5-1, DIN VDE 0110 part 1
[Uimp] rated impulse withstand voltage 4 kV overvoltage category III conforming to IEC 60647-5-1, DIN VDE 0110 part 1
Local signalling 3 LEDs
Current consumption 30 mA at 24 V AC (on power supply)
Mounting support 35 mm symmetrical DIN rail
Product weight 0.25 kg
Environment
Standards EN 1088/ISO 14119
EN 60204-1
EN/IEC 60947-5-1
EN/ISO 13850
Product certifications CSA
TÜV
UL
IP degree of protection IP40 (enclosure) conforming to EN/IEC 60529
IP20 (terminals) conforming to EN/IEC 60529
Ambient air temperature for operation -25...60 °C
Ambient air temperature for storage -40...85 °C
3
Product data sheet
Dimensions Drawings
XPSAF5130
Dimensions
4
Product data sheet
Connections and Schema
XPSAF5130
Wiring Diagrams
Refer to the Instruction Sheet
To download the instruction sheet, follow below procedure:
1 Click on Download & Documents.
2 Click on Instruction sheet.
General Description
The MAX1365/MAX1367 low-power, 4.5- and 3.5-digit,
panel meters feature an integrated sigma-delta analogto-
digital converter (ADC), LED display drivers, voltage
digital-to-analog converter (DAC), and a 4–20mA
(or 0 to 16mA) current driver.
The MAX1365/MAX1367’s analog input voltage range is
programmable to either ±2V or ±200mV. The MAX1367
drives a 3.5-digit (±1999 count) display and the
MAX1365 drives a 4.5-digit (±19,999 count) display.
The ADC output directly drives the LED display as well
as the voltage DAC, which in turn drives the 4–20mA
(or 0 to 16mA) current-loop output.
In normal operation, the 0 to 16mA/4–20mA currentloop
output follows the ±2V or ±200mV analog input to
drive remote panel-meter displays, data loggers, and
other industrial controllers. For added flexibility, the
MAX1365/MAX1367 allow direct access to the DAC
output and the V/I converter input.
The sigma-delta ADC does not require external precision
integrating capacitors, autozero capacitors, crystal
oscillators, charge pumps, or other circuitry commonly
required in dual-slope ADC panel-meter circuits. Onchip
analog input and reference buffers allow direct
interface with high-impedance signal sources. Excellent
common-mode rejection and digital filtering provide
greater than 100dB rejection of simultaneous 50Hz and
60Hz line noise. Other features include data hold, peak
detection, and overrange/underrange detection.
The MAX1365/MAX1367 require a 2.7V to 5.25V supply,
a 4.75V to 5.25V V/I supply, and a 7V to 30V loop supply.
They are available in a space-saving (7mm x
7mm), 48-pin TQFP package and operate over the
extended (-40°C to +85°C) temperature range.
Applications
Automated Test Equipment
Data-Acquisition Systems
Digital Multimeters
Digital Panel Meters
Digital Voltmeters
Industrial Process Control
Features
♦ Stand-Alone, Digital Panel Meter
20-Bit Sigma-Delta ADC
4.5-Digit Resolution (±19,999 Count, MAX1365)
3.5-Digit Resolution (±1999 Count, MAX1367)
No Integrating/Autozeroing Capacitors
100MΩ Input Impedance
±200mV or ±2.000V Input Range
♦ LED Display
Common-Cathode 7-Segment LED Driver
Programmable LED Current (0 to 20mA)
2.5Hz Update Rate
♦ Output DAC and Current Driver
±15-Bit DAC with 14-Bit Linear V/I Converter
Selectable 0 to 16mA or 4–20mA Current Output
Unipolar/Bipolar Modes
±50μA Zero Scale, ±40ppmFS/°C (typ)
±0.5% Gain Error, ±25ppmFS/°C (typ)
Separate 7V to 30V Supply for Current-Loop
Output
♦ 2.7V to 5.25V ADC/DAC Supply
♦ 4.75V to 5.25V V/I Converter Supply
♦ Internal 2.048V Reference or External Reference
♦ 48-Pin, 7mm x 7mm TQFP Package
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
________________________________________________________________ Maxim Integrated Products 1
Selector Guide
19-3889; Rev 1; 1/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX1365ECM -40°C to +85°C 48 TQFP
MAX1367ECM -40°C to +85°C 48 TQFP
Ordering Information
PART
RESOLUTION
(DIGITS)
PKG
CODE
MAX1365ECM 4.5 C48-6
MAX1367ECM 3.5 C48-6
Pin Configuration appears at end of datasheet.
Typical Operating Circuits appear at end of datasheet.
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external
reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1μF, REF- = GND, CNEGV = 0.1μF. Internal clock mode, unless otherwise
noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD ....................................................................-0.3V to +6.0V
AIN+, AIN-, REF+, REF-.........................VNEGV to (AVDD + 0.3V)
REG_FORCE, CMP, DAC_VDD, DACVOUT,
CONV_IN, 4-20OUT.............................-0.3V to (AVDD + 0.3V)
EN_BPM, EN_I, REFSELE, DACDATA_SEL, INTREF, RANGE,
DPSET1, DPSET2, HOLD, PEAK, DPON,
CS_DAC...............................................-0.3V to (DVDD + 0.3V)
NEGV .......................................................-2.6V to (AVDD + 0.3V)
LED_EN....................................................-0.3V to (DVDD + 0.3V)
SET...........................................................-0.3V to (AVDD + 0.3V)
REG_AMP, REG_VDD ...........................................-0.3V to +6.0V
LEDV......................................................................-0.3V to +6.0V
LEDG.....................................................................-0.3V to +0.3V
GND_DAC .............................................................-0.3V to +0.3V
GND_V/I.................................................................-0.3V to +0.3V
SEG_ to LEDG.........................................-0.3V to (VLEDV + 0.3V)
DIG_ to LEDG..........................................-0.3V to (VLEDV + 0.3V)
REF_DAC .................................................-0.3V to (AVDD + 0.3V)
DIG_ Sink Current .............................................................300mA
DIG_ Source Current...........................................................50mA
SEG_ Sink Current . ............................................................50mA
SEG_ Source Current..........................................................50mA
Maximum Current Input into Any Other Pin . ......................50mA
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 22.7mW/°C above +70°C).....1818.2mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC ACCURACY
MAX1365 -19,999 +19,999
Noise-Free Resolution
MAX1367 -1999 +1999
Counts
2.000V range ±1
Integral Nonlinearity (Note 1) INL
200mV range ±1
Counts
Range Change Ratio
(VAIN+ - VAIN- = 0.100V) on 200mV range;
(VAIN+ - VAIN- = 0.100V) on 2.0V range
10:1 Ratio
Rollover Error VAIN+ - VAIN- = full scale ±1 Counts
Output Noise 10 μVP-P
Offset Error (Zero Input Reading) VAIN+ - VAIN- = 0 (Note 2) -0 +0 Counts
Gain Error (Note 3) -0.5 +0.5 %FSR
Offset Drift (Zero Reading Drift) VAIN+ - VAIN- = 0 (Note 4) 0.1 μV/°C
Gain Drift ±1 ppm/°C
INPUT CONVERSION RATE
Update Rate 5 Hz
ANALOG INPUTS (AIN+, AIN-) (bypass to GND with 0.1μF or greater capacitors)
RANGE = GND -2.0 +2.0
AIN Input Voltage Range (Note 5)
RANGE = DVDD -0.2 +0.2
V
AIN Absolute Input Voltage
Range to GND
-2.2 +2.2 V
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
50Hz and 60Hz ±2% 100 dB
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
CMR
For 50Hz and 60Hz ±2%, RSOURCE <
10kΩ
150 dB
Common-Mode Rejection CMR At DC 100 dB
Input Leakage Current 10 nA
Input Capacitance 10 pF
Average Dynamic Input Current -20 +20 nA
INTERNAL REFERENCE (REF- = GND, INTREF = DVDD)
REF Input Voltage VREF 2.007 2.048 2.089 V
REF Output Short-Circuit Current 1 mA
REF Output Temperature
Coefficient
TCVREF 40 ppm/°C
Load Regulation ISOURCE = 0 to 300μA, ISINK = 0 to 30μA 6 μV/μA
Line Regulation 50 μV/V
0.1Hz to 10Hz 25
Noise Voltage
10Hz to 10kHz 400
μVP-P
EXTERNAL REFERENCE (INTREF = GND)
REF Input Voltage Differential (VREF+ - VREF-) 2.048 V
Absolute REF+, REF- Input
Voltage to GND (VREF+ Must Be
Greater Than VREF-)
-2.2 +2.2 V
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
50Hz and 60Hz ±2% 100 dB
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
CMR
For 50Hz and 60Hz ±2%, RSOURCE <
10kΩ
150 dB
Common-Mode Rejection CMR At DC 100 dB
Input Leakage Current 10 nA
Input Capacitance 10 pF
Average Dynamic Input Current (Note 6) -20 +20 nA
CHARGE PUMP
Output Voltage NEGV CNEGV = 0.1μF to GND -2.60 -2.42 -2.30 V
DIGITAL INPUTS (INTREF, RANGE, PEAK, HOLD, DPSET1, DPSET2)
Input Current IIN VIN = 0 or DVDD -10 +10 μA
Input Low Voltage VINL
0.3 x
DVDD
V
Input High Voltage VINH
0.7 x
DVDD
V
Input Hysteresis VHYS DVDD = 3V 200 mV
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external
reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1μF, REF- = GND, CNEGV = 0.1μF. Internal clock mode, unless otherwise
noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external
reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1μF, REF- = GND, CNEGV = 0.1μF. Internal clock mode, unless otherwise
noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC POWER SUPPLY (Note 7)
AVDD Voltage AVDD 2.70 5.25 V
DVDD Voltage DVDD 2.70 5.25 V
Power-Supply Rejection AVDD PSRA (Note 8) 80 dB
Power-Supply Rejection DVDD PSRD (Note 8) 100 dB
640
AVDD Current (Note 9) IAVDD
Standby mode 305
μA
DVDD = +5.25V 320
DVDD Current (Note 9) IDVDD DVDD = +3.3V 180
Standby mode 20
μA
DAC POWER SUPPLY
DAC Supply Voltage VDAC_VDD 2.70 5.25 V
DAC Supply Current 0.10 0.21 mA
LINEAR REGULATOR AND V/I CONVERTER POWER REQUIREMENTS
REG_AMP Supply Voltage VREG_AMP 4.75 5.25 V
REG_AMP Supply Current 0.19 0.30 mA
REG_VDD Supply Voltage VREG_VDD 5.20 V
REG_VDD Supply Current Includes 20mA programmed current 25.2 27.4 mA
LED DRIVERS
LED Supply Voltage VLEDV 2.70 5.25 V
LED Shutdown Supply Current ISHDN 10 μA
LED Supply Current ILEDV 176 180 mA
MAX1365 512
Display Scan Rate fOSC
MAX1367 640
Hz
Segment Current Slew Rate ISEG/Δt 25 mA/μs
DIG_ Voltage Low VDIG 0.178 0.300 V
Segment-Drive Source-Current
Matching
ΔISEG 3 ±12 %
Segment-Drive Source Current ISEG VLEDV - VSEG = 0.6V, RSET = 25kΩ 15.0 21.5 25.5 mA
LED Drivers Bias Current From AVDD 120 μA
Interdigit Blanking Time 4 μs
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = DAC_VDD = +2.7V to +5.25V, GND = 0, VLEDV = +2.7V to +5.25V, LEDG = 0, VREF+ - VREF- = 2.048V (external
reference), 4-20OUT = 7V, VREG_AMP = +5.0V, CREF+ = 0.1μF, REF- = GND, CNEGV = 0.1μF. Internal clock mode, unless otherwise
noted. All specifications are at TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC OUTPUT ACCURACY
Zero-Scale Error 4–20mA or 0 to 16mA mode, TA = +25°C ±50 μA
Zero-Scale Error Tempco ±40 p p mFS /° C
Gain Error 4–20mA or 0 to 16mA mode, TA = +25°C ±0.5 %FS
Gain-Error Tempco ±25 p p mFS /° C
Span Linearity ±2 ±4 μA
Power-Supply Rejection PSR VEXT = 7V to 30V 4 μA/V
Signal Path Noise 10pF to GND on 4-20OUT 2.0 μARMS
4–20mA Current Limit Limited to 12.5 x VREF / 1.28kΩ 20 mA
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and
offset error.
Note 2: Offset calibrated.
Note 3: Offset nulled.
Note 4: Drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: VAIN+ or VAIN- = -2.2V to +2.2V. VREF+ or VREF- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only. VREF+ must always be greater than VREF-.
Note 7: Power-supply currents are measured with all digital inputs at either GND or DVDD.
Note 8: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion error
with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 1).
Note 9: LED drivers are disabled.
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
6 _______________________________________________________________________________________
0
300
200
100
400
500
600
700
800
900
1000
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1365/67 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (μA)
DAC_VDD
AVDD
DVDD
0
200
100
400
300
600
500
700
-40 -15 10 35 60 85
SUPPLY CURRENT vs. TEMPERATURE
MAX1365/67 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (μA)
AVDD
DVDD
DAC_VDD
MAX1365
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1365/67 toc03
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
3.25 3.75 4.25 4.75
-0.11
-0.06
-0.01
0.04
0.09
0.14
0.19
-0.16
2.75 5.25
MAX1365
OFFSET ERROR vs. TEMPERATURE
MAX1365/67 toc04
TEMPERATURE (°C)
OFFSET ERROR (LSB)
10 20 30 40 50 60
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
-0.2
0 70
MAX1365
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1365/67 toc05
SUPPLY VOLTAGE (V)
GAIN ERROR (% FULL SCALE)
3.25 3.75 4.25 4.75
-0.08
-0.04
-0.06
-0.02
0
0.02
0.04
0.06
0.08
-0.10
2.75 5.25
MAX1365
GAIN ERROR vs. TEMPERATURE
MAX1365/67 toc06
TEMPERATURE (°C)
GAIN ERROR (% FULL SCALE)
10 20 30 40 50 60
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
-0.10
0 70
MAX1365
INL (±200mV INPUT RANGE) vs. OUTPUT CODE
MAX1365/67 toc07
OUTPUT CODE
INL (COUNTS)
-10,000 0 10,000
-0.5
0
0.5
1.0
-1.0
-20,000 20,000
MAX1365
INL (±2V INPUT RANGE) vs. OUTPUT CODE
MAX1365/67 toc08
OUTPUT CODE
INL (COUNTS)
-10,000 0 10,000
-0.5
0
0.5
1.0
-1.0
-20,000 20,000
NOISE DISTRIBUTION
MAX1365/67 toc09
NOISE (LSB)
PERCENTAGE OF UNITS (%)
-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
5
10
15
20
25
0
-0.2
Typical Operating Characteristics
(AVDD = DVDD = +5V, VDAC_VDD = +5.0V, GND = 0, LEDG = 0, VLEDV = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference),
VEXT = 7V, CREF+ = CREF- = 0.1μF, CNEGV = 0.1μF. Internal clock mode, unless otherwise noted. TA = +25°C, unless otherwise
noted.)
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
_______________________________________________________________________________________ 7
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1365/67 toc10
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
10 20 30 40 50 60
2.046
2.045
2.047
2.049
2.048
2.051
2.050
2.053
2.052
2.054
2.044
0 70
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1365/67 toc11
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
3.25 3.75 4.25 4.75
2.045
2.046
2.047
2.048
2.049
2.050
2.044
2.75 5.25
DATA OUTPUT RATE
vs. TEMPERATURE
MAX1365/67 toc12
TEMPERATURE (°C)
DATA OUTPUT RATE (Hz)
-15 10 35 60
4.92
4.98
4.96
4.94
5.00
5.02
5.04
5.06
5.08
5.10
4.90
-40 85
DATA OUTPUT RATE
vs. SUPPLY VOLTAGE
MAX1365/67 toc13
SUPPLY VOLTAGE (V)
DATA OUTPUT RATE (Hz)
3.21 3.72 4.23 4.74
4.995
4.990
4.985
5.000
5.005
5.010
5.015
5.020
4.980
2.70 5.25
OFFSET ERROR
vs. COMMON-MODE VOLTAGE
MAX1365/67 toc14
COMMON-MODE VOLTAGE (V)
OFFSET ERROR (LSB)
-1.5 -1.0 -0.5 0 0.5 1.0 1.5
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-0.20
-2.0 2.0
VNEG STARTUP SCOPE SHOT
MAX1365/67 toc15
20ms/div
2V/div
1V/div
VDD
VNEG
CHARGE-PUMP OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1365/67 toc16
SUPPLY VOLTAGE (V)
VNEG VOLTAGE (V)
3.25 3.75 4.25 4.75
-2.48
-2.46
-2.44
-2.42
-2.40
-2.50
2.75 5.25
SEGMENT CURRENT
vs. SUPPLY VOLTAGE
MAX1365/67 toc17
SUPPLY VOLTAGE (V)
SEGMENT CURRENT (μA)
3.21 3.72 4.23 4.74
5
10
15
20
25
30
0
2.70 5.25
RISET = 25kΩ
-0.2
0
-0.1
0.2
0.1
0.3
0.4
-40 -15 10 35 60 85
DAC ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
MAX1365/67 toc18
TEMPERATURE (°C)
OFFSET ERROR (LSB)
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, VDAC_VDD = +5.0V, GND = 0, LEDG = 0, VLEDV = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference),
VEXT = 7V, CREF+ = CREF- = 0.1μF, CNEGV = 0.1μF. Internal clock mode, unless otherwise noted. TA = +25°C, unless otherwise
noted.)
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, VDAC_VDD = +5.0V, GND = 0, LEDG = 0, VLEDV = +2.7V to +5.25V, VREF+ - VREF- = 2.048V (external reference),
VEXT = 7V, CREF+ = CREF- = 0.1μF, CNEGV = 0.1μF. Internal clock mode, unless otherwise noted. TA = +25°C, unless otherwise
noted.)
-0.30
-0.20
-0.25
-0.10
-0.15
-0.05
0
-40 -15 10 35 60 85
DAC GAIN ERROR
vs. TEMPERATURE
MAX1365/67 toc19
TEMPERATURE (°C)
GAIN ERROR (LSB)
4–20OUT
= 21.7mA
CONV_IN
= 1V
10mA/div
500mV/div
STEP RESPONSE
MAX1365/67 toc20
100μs/div
-50
-20
-30
-40
0
-10
40
30
20
10
50
-40 -20 0 20 40 60 80
4–20OUT ZERO-SCALE ERROR
vs. TEMPERATURE
MAX1365/67 toc21
TEMPERATURE (°C)
CURRENT OUTPUT (μA)
EXTERNAL REFERENCE = 2.048V
-50
-20
-30
-40
0
-10
40
30
20
10
50
-40 -20 0 20 40 60 80
4–20OUT GAIN ERROR
vs. TEMPERATURE
MAX1365/67 toc22
TEMPERATURE (°C)
GAIN ERROR (%)
EXTERNAL REFERENCE = 2.048V
4–20mA MODE
0 TO 16mA MODE
-0.5
0
0.5
1.0
1.5
2.0
2.5
-20,000 -10,000 0 10,000 20,000
4–20OUT vs. DAC CODE
(4–20OUT SPAN LINEARITY)
MAX1365/67 toc24
DAC CODE (COUNTS)
SPAN LINEARITY (μA)
OFFSET ENABLED
(EN_I = HIGH)
-150
-100
-50
0
50
100
150
4 6 8 10 12 14 16 18 20
POWER-SUPPLY REJECTION
vs. CURRENT OUTPUT (4-20OUT)
MAX1365/67 toc23
4-20OUT OUTPUT CURRENT (mA)
POWER-SUPPLY REJECTION (nA/V)
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
_______________________________________________________________________________________ 9
PIN NAME FUNCTION
1 AIN+
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND with a
0.1μF or greater capacitor.
2 AINNegative
Analog Input. Negative side of fully differential analog input. Bypass AIN- to GND with a
0.1μF or greater capacitor.
3 GND Ground. Connect to star ground.
4 AVDD
Analog Positive Supply Voltage. Connect AVDD to a +2.7V to +5.25V power supply. Bypass AVDD
to GND with a 0.1μF capacitor.
5 DVDD
Digital Positive Supply Voltage. Connect DVDD to a +2.7V to +5.25V power supply. Bypass DVDD
to GND with a 0.1μF capacitor.
6 SET
Segment Current Set. Connect to ground through a resistor to set the segment current. See Table
7 for segment-current selection.
7 REG_VDD V/I Converter Regulated Supply Output (5.2V typ)
8 REG_FORCE REG_VDD Control. Drives the gate of external depletion-mode FET.
9 REG_AMP Regulator/Reference Buffer Supply. Connect to a 4.75V to 5.25V power supply.
10 CMP Regulator Compensation Node. Connect a 0.1μF capacitor from CMP to REG_FORCE.
11 DAC_VDD DAC Analog Supply. Connect DAC_VDD to a +2.7V to +5.25V power supply.
12 DACVOUT DAC Voltage Output. DAC output impedance is typically 6.2kΩ.
13 CONV_IN V/I Converter Input
14 4-20OUT 4–20mA (0 to 16mA) Current-Loop Output. Referenced to GND.
15 GND_DAC DAC Analog Ground. Connect to star ground.
16 GND_V/I V/I Converter Analog Ground. Connect to star ground.
17 REF_DAC
V-to-I Converter/DAC Reference Input. Connect a voltage source for external reference operation
or leave floating for internal reference. Bypass REF_DAC with a 0.1μF capacitor to GND for either
internal or external reference operation.
18 EN_BPM Acti ve- H i g h V /I- C onver ter Bi p ol ar - M od e E nab l e. S et hi g h for b i p ol ar m od e. S et l ow for uni p ol ar m od e.
19 EN_I Acti ve- H i g h V /I- C onver ter 4m A O ffset E nab l e. S et l ow for 0 to 16m A outp ut. S et hi g h for 4–20m A.
20 REFSELE
DAC External Reference Selection. Set low for internal reference. Set high for external reference.
Leave REF_DAC unconnected when REFSELE is low.
21 DACDATA_SEL DAC Data-Source Select. Connect to logic high for the MAX1365/MAX1367.
22 CS_DAC DAC Chip Select. Connect to logic high for the MAX1365/MAX1367.
23 INTREF
ADC Reference Selection. Set INTREF high to select the internal ADC reference. Set INTREF low
to select external ADC reference.
24 RANGE
ADC Range Select. Set RANGE low for ±2V analog input voltage range. Set RANGE high for
±200mV analog input voltage range.
25 PEAK
Peak Logic Input. Connect PEAK to DVDD to display the highest ADC value on the LED. Connect
PEAK to GND to disable the PEAK function (see Table 1).
Pin Description
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
10 ______________________________________________________________________________________
PIN NAME FUNCTION
26 HOLD
Hold Logic Input. Connect HOLD to DVDD to hold the current ADC value on the LED. Connect
HOLD to GND to update the LED at a rate of 2.5Hz and disable the hold function. Placing the
device into hold mode initiates an offset mismatch calibration. Assert HOLD high for a minimum of
2s to ensure the completion of offset mismatch calibration (see Table 1).
27 DPSET2
Display Decimal-Point Logic-Input 2. Controls the decimal point of the LED. See the Decimal-Point
Control section.
28 DPSET1
Display Decimal-Point Logic-Input 1. Controls the decimal point of the LED. See the Decimal-Point
Control section.
29 LEDG LED Segment-Drivers Ground
30 DIG0 Digit 0 Driver Out (Connected to GLED for the MAX1367)
31 DIG1 Digit 1 Driver Out
32 DIG2 Digit 2 Driver Out
33 DIG3 Digit 3 Driver Out
34 DIG4 Digit 4 Driver Out
35 SEGA Segment A Driver
36 SEGB Segment B Driver
37 LEDV
LED-Display Segment-Driver Supply. Connect to a +2.7V to +5.25V supply. Bypass with a 0.1μF
capacitor to LEDG.
38 SEGC Segment C Driver
39 SEGD Segment D Driver
40 SEGE Segment E Driver
41 SEGF Segment F Driver
42 SEGG Segment G Driver
43 SEGDP Segment DP Driver
44 LED_EN
Active-High LED Enable. The MAX1365/MAX1367 display driver turns off when LED_EN is low.
The MAX1365/MAX1367 LED-display driver turns on when LED_EN is high.
45 NEGV -2.5V Charge-Pump Voltage Output. Connect a 0.1μF capacitor to GND.
46 DPON
Decimal-Point Enable Input. Controls the decimal point of the LED. See the Decimal-Point Control
section. Connect DPON to DVDD to enable the decimal point.
47 REFADC
Negative Reference Voltage Input. For internal reference operation, connect REF- to GND.
For external reference operation, bypass REF- to GND with a 0.1μF capacitor and
set VREF- from -2.2V to +2.2V (VREF+ > VREF-).
48 REF+
ADC Positive Reference Voltage Input. For internal reference operation, connect a 4.7μF capacitor
from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1μF capacitor
and set VREF+ from -2.2V to +2.2V (VREF+ > VREF-).
Pin Description (continued)
Detailed Description
The MAX1365/MAX1367 low-power, highly integrated
ADCs with LED drivers convert a ±2V differential input
voltage (one count is equal to 100μV for the MAX1365
and 1mV for the MAX1367) with a sigma-delta ADC and
output the result to an LED display. An additional
±200mV input range (one count is equal to 10μV for the
MAX1365 and 100μV for the MAX1367) is available to
measure small signals with finer resolution.
In addition to displaying the results on an LED display,
these devices feature a DAC and V-to-I converter for
4–20mA (or 0 to 16mA) current output that proportionally
follows the ADC input. The MAX1365/MAX1367 use
an external depletion-mode NMOS transistor to regulate
7V to 30V for the V/I converter. Use the 4–20mA (or 0 to
16mA) output to drive a remote display, data logger,
PLC input, or other 4–20mA devices in a current loop.
The MAX1365/MAX1367 include a 2.048V reference,
internal charge pump, and a high-accuracy on-chip
oscillator. The devices feature on-chip buffers for the differential
input signal and external-reference inputs,
allowing direct interface with high-impedance signal
sources. In addition, they use continuous internal offsetcalibration
and offer > 100dB of 50Hz and 60Hz linenoise
rejection. Other features include data hold and
peak detection and overrange/underrange detection.
Analog Input Protection
The MAX1365/MAX1367 provide internal protection
diodes that limit the analog input range on AIN+, AIN-,
REF+, and REF- from NEGV to (AVDD + 0.3V). If the
analog input exceeds this range, limit the input current
to 10mA.
Internal Analog Input/Reference Buffers
The MAX1365/MAX1367 analog input/reference buffers
allow the use of high-impedance signal sources. The
input buffers’ common-mode input range allows the analog
inputs and the reference to range from -2.2V to +2.2V.
Modulator
The MAX1365/MAX1367 perform analog-to-digital conversions
using a single-bit, 3rd-order, sigma-delta modulator.
The sigma-delta modulator converts the input
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 11
LED
DRIVER
LEDG
SEGA
SEGG
DIG0(1)
DIG4(4)
LED_EN
MAX1365
MAX1367
ADC
INPUT
BUFFER
-2.5V
AIN+
AINREF+
REFNEGV
+2.5V
2.048V
BANDGAP
REFERENCE
LOGIC
GND
CHARGE
PUMP -2.5V
OUTPUT
DAC
DAC REF
BUFFER
AVDD DVDD INTREF RANGE
5V REGULATOR
V/I
CONVERTER
CURRENT
SUMMER
AND
AMPLIFIER
OFFSET
GENERATOR EN_BPM
EN_I
DACVOUT
4-20OUT
REG_FORCE
CS_DAC DACDATA_SEL SET
REFSELE REF_DAC REG_AMP
CONV_IN
CMP REG_VDD
DAC_VDD
PEAK DPON DPSET1 DPSET 2 HOLD LEDV
Functional Diagram
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
12 ______________________________________________________________________________________
signal into a digital pulse train whose average duty
cycle represents the digitized signal information. The
modulator quantizes the input signal at a much higher
sample rate than the bandwidth of the input. The
MAX1365/MAX1367 modulator provides 3rd-order frequency
shaping of the quantization noise resulting from
the single-bit quantizer. The modulator is fully differential
for maximum signal-to-noise ratio and minimum susceptibility
to power-supply noise. A single-bit data
stream is then presented to the digital filter to remove
the frequency-shaped quantization noise.
Digital Filtering
The MAX1365/MAX1367 contain an on-chip digital lowpass
filter that processes the data stream from the
modulator using a SINC4 response:
The SINC4 filter has a settling time of four output data
periods (4 x 200ms). The MAX1365/MAX1367 have
25% overrange capability built into the modulator and
digital filter. The digital filter is optimized for the fCLK
equal to 4.9152MHz. The frequency response of the
SINC4 filter is calculated as follows:
where N is the oversampling ratio, and fm = N x output
data rate = 5Hz.
Filter Characteristics
Figure 1 shows the filter frequency response. The
SINC4 characteristic -3dB cutoff frequency is 0.228
times the first notch frequency (5Hz). The oversampling
ratio (OSR) for the MAX1367 is 128 and the OSR for the
MAX1365 is 1024. The output data rate for the digital filter
corresponds to the positioning of the first notch of
the filter’s frequency response. The notches of the
SINC4 filter are repeated at multiples of the first notch
frequency. The SINC4 filter provides an attenuation of
better than 100dB at these notches. For example, 50Hz
is equal to 10 times the first notch frequency and 60Hz
is equal to 12 times the first notch frequency. For large
step changes at the input, allow a settling time of
800ms before valid data is read.
Internal Clock
The MAX1365/MAX1367 contain an internal oscillator.
Using the internal oscillator saves board space by
removing the need for an external clock source. The
oscillator is optimized to give 50Hz and 60Hz powersupply
and common-mode rejection.
Charge Pump
The MAX1365/MAX1367 contain an internal charge pump
to provide the negative supply voltage for the internal
analog input/reference buffers. The bipolar input range of
the analog input/reference buffers allows this device to
accept negative inputs with high source impedances.
Connect a 0.1μF capacitor from NEGV to GND.
LED Driver (Table 1)
The MAX1365 has a 4.5-digit common-cathode display
driver, and the MAX1367 has a 3.5-digit common-cathode
display driver. In addition, the LED drivers of the
MAX1365/MAX1367 feature peak-detection and datahold
circuitry.
Figures 2 and 3 show the connection schemes for a
standard seven-segment LED display. The LED update
rate is 2.5Hz. Figure 4 shows a typical common-cathode
configuration for two digits. In common-cathode
configuration, the cathodes of all LEDs in a digit are
connected together. Each segment driver of the
MAX1365/MAX1367 connects to its corresponding
LED’s anodes. For example, segment driver SEGA connects
to all LED segments designated as A. Similar
configurations are used for other segment drivers.
H z
Z
N
H f
N
N
f
f
f
f
N
Z
m
m
( )
( )
( )
sin
sin
( )
=
−
=
−
− −
11
1
1
4
4
1
π
π
sin(x)
x
4
FREQUENCY (Hz)
GAIN (dB)
10 20 30 40 50
-160
-120
-80
-40
0
-200
0 60
Figure 1. Frequency Response of the SINC4 Filter (Notch at 60Hz)
The MAX1365/MAX1367 use a multiplexing scheme to
drive one digit at a time. The scan rate is fast enough to
make the digits appear to be lit. Figure 5 shows the
data-timing diagram for the MAX1365/MAX1367 where
T is the display scan period (typically around 1/512Hz
or 1.9531ms). TON in Figure 5 denotes the amount of
time each digit is on and is calculated as follows:
Decimal-Point Control
The MAX1365/MAX1367 allow for full decimal-point
control and feature leading-zero suppression.
Use the DPON, DPSET1, and DPSET2 bits in the control
register to set the value of the decimal point (Tables
2 and 3). The MAX1365/MAX1367 overrange and
underrange display is shown in Table 4.
Leading-Zero Suppression
The MAX1365/MAX1367 include a leading-zero suppression
circuitry to turn off unnecessary zeros. For
example, when DPSET1 and DPSET2 = [0,0], 0.0 is displayed
instead of 000.0 (MAX1365). This feature saves
a substantial amount of power by not lighting unnecessary
LEDs.
Interdigit Blanking
The MAX1365/MAX1367 also include an interdigitblanking
circuitry. Without this feature, it is possible to
see a faint digit next to a digit that is completely on.
The interdigit-blanking circuitry prevents ghosting over
into the next digit for a short period of time. The typical
interdigit blanking time is 4μs.
T
T ms
ON = = = s
5
1 95312
5
390 60
.
. μ
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 13
A
B
C
A A A A
D
DIGIT 4 DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0
D D D D
E
G
F
E E E
F G B F G B F G B F G B
C C C C
DP DP DP DP DP
Figure 2. Segment Connection for the MAX1365 (4.5 Digits)
A
B
A A A
D
DIGIT 4 DIGIT 3 DIGIT 2 DIGIT 1
D D D
E
G
F
E E
F G B F G B F G B
C C C
DP DP DP DP
C
Figure 3. Segment Connection for the MAX1367 (3.5 Digits)
HOLD PEAK DISPLAY VALUES FORM
1 X Hold value
0 1 Peak value
0 0 Latest ADC result
Table 1. LED Priority Table
X = Don’t care.
DPON DPSET1 DPSET2
DISPLAY
OUTPUT
ZERO INPUT
READING
1 0 0 1888. 0.
1 0 1 188.8 0.0
1 1 0 18.88 0.00
1 1 1 1.888 0.000
Table 3. Decimal-Point Control Table—
MAX1367
CONDITION MAX1367 MAX1365
Overrange 1--- 1----
Underrange -1--- -1----
Table 4. LED During Overrange and
Underrange Conditions
DPON DPSET1 DPSET2
DISPLAY
OUTPUT
ZERO INPUT
READING
0 0 0 18888 0
0 0 1 18888 0
0 1 0 18888 0
0 1 1 18888 0
1 0 0 1888.8 0.0
1 0 1 188.88 0.00
1 1 0 18.888 0.000
1 1 1 1.8888 0.0000
Table 2. Decimal-Point Control Table—
MAX1365
Current Output
The MAX1365/MAX1367 feature a 4–20mA (0 to 16mA)
current output for driving remote panel meters, data loggers,
and process controllers in industrial applications.
The DAC output is proportional to the input of the ADC
and LED display. In the simplest configuration, connect
DAC_VOUT directly to CONV_IN to have the current output
(4–20mA or 0 to 16mA) follow the analog inputs.
Custom signal conditioning can be inserted between
DAC_VOUT and CONV_IN, or CONV_IN can be driven
independently by a voltage source if desired. See
Figures 11–14 for the transfer functions of the DAC and
V/I converter.
Note: The MAX1365/MAX1367 expect a 6kΩ (typ)
source impedance from the external voltage source
driving CONV_IN.
Current Offset
Set EN_I high for a current span of 4–20mA. Set EN_I low
for a current span of 0 to 16mA. See Table 5 for current
output.
Unipolar Mode
Set EN_BPM low to engage unipolar operation. In
unipolar mode, the current output at 4-20OUT (4–20mA
or 0 to 16mA) maps the analog input voltage (0 to 2V or
0 to 200mV). Negative voltages at the analog input
result in a 4mA or 0mA output, depending on the EN_I
setting. See Table 5 for current output. See Figures 12
and 13.
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
14 ______________________________________________________________________________________
A
A
A
DIGIT 1 DIGIT 2
SEGDP
SEGG
SEGF
SEGE
SEGD
SEGC
SEGB
SEGA
D D
E E
F G B F G B
C C
DP DP
B C D E F G DP A B C D E F G DP
Figure 4. 2-Digit Common-Cathode Configuration
4 3 2 1 0 4 3 2 1 0 4
T
TON
DIGIT 4 (MSD)
DIGIT 3
INTERDIGIT BLANKING TIME
DIGIT 2
DIGIT 1
DIGIT 0 (LSD)
DATA
MSD LSD
Figure 5. LED Voltage Waveform
Bipolar Mode
Set EN_BPM high to engage bipolar operation. In bipolar
mode, the current output at 4–20OUT (4–20mA or
0 to 16mA) maps the analog input voltage (±2V or
±200mV). In bipolar mode, a 0V analog input maps to
midscale (12mA). See Table 5 for current output (see
Figures 12 and 13).
5.2V Linear Regulator with Compensation
The MAX1365/MAX1367 feature a 5.2V linear regulator.
The 5.2V regulator consists of an op amp and connections
to an external depletion-mode FET. The 5.2V regulator
regulates the loop voltage that powers the
voltage-to-current converter and the rest of the transmitter
circuitry. The regulator output voltage is available
at REG_VDD and is given by the equation:
VREG_VDD = 2.54 x VREF+
The FET breakdown and saturation voltages determine
the usable range of loop voltages (VEXT). The external
FET parameters such as VGS (off), IDSS, and transconductance
must be chosen so that the op amp output on
the REG_FORCE pin can control the FET operating
point while swinging in the range from VREG_AMP to
REG_VDD. See the Selecting Depletion-Mode FET section
in the Applications Information section.
Connect a 0.1μF capacitor between CMP and
REG_FORCE to ensure stable operation of the regulator.
Applications Information
Power-On Reset
At power-on, the digital filter and modulator circuits
reset. The MAX1365 allows 6s for the reference to stabilize
before performing enhanced offset calibration.
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 15
CURRENT OUTPUT (mA)
ANALOG INPUT UNIPOLAR MODE
(EN_I = LOW)
UNIPOLAR MODE
(EN_I = HIGH)
BIPOLAR MODE
(EN_I = LOW)
BIPOLAR MODE
(EN_I = HIGH)
Negative Full Scale 0 4 0 4
0V 0 4 8 12
Positive Full Scale 16 20 16 20
Table 5. Current Output Table
MAX1365
MAX1367
AVDD DVDD
10μF
10μF
0.1μF
0.1μF
0.1μF
0.1μF
ANALOG SUPPLY
FERRITE
BEAD
RREF
R
R
ACTIVE
GAUGE
DUMMY
GAUGE
REF+
REFNEGV
AIN+
AIN-
4-20OUT
4–20mA/0 TO 16mA
CURRENT-LOOP
OUTPUT
GND
0.1μF
0.1μF
Figure 6. Strain-Gauge Application with the MAX1365/MAX1367
MAX1365/MAX1367
During these 6s, the MAX1365 displays 1.2V to 1.5V
when a stable reference is detected. If a valid reference
is not found, the MAX1365 times out after 6s and
begins enhanced offset calibration. Enhanced offset
calibration typically lasts 2s. The MAX1365 begins converting
after enhanced offset calibration.
Reference
ADC Reference
The MAX1365/MAX1367 reference sets the full-scale
range of the ADC transfer function. With a nominal
2.048V reference, the ADC full-scale range is ±2V with
RANGE = GND. With RANGE = DVDD, the full-scale
range is ±200mV. A decreased reference voltage
decreases full-scale range (see the Transfer Functions
section).
The ADC of the MAX1365/MAX1367 can accept either
an external reference or an internal reference (INTREF).
The INTREF logic selects the reference mode. For internal-
reference operation, set INTREF to DVDD, connect
REF- to GND, and bypass REF+ to GND with a 4.7μF
capacitor. The internal reference provides a nominal
2.048V source between REF+ and GND. The internalreference
temperature coefficient is typically
40ppm/°C.
For external-reference operation, set INTREF to GND.
REF+ and REF- are fully differential. For a valid external-
reference input, VREF+ must be greater than VREF-.
Bypass REF+ and REF- with a 0.1μF or greater capacitor
to GND in external-reference mode.
Figure 6 shows the MAX1365/MAX1367 operating with
an external differential reference. In this figure, REF- is
connected to the top of the strain gauge and REF+ is
connected to the midpoint of the resistor-divider of
the supply.
DAC Reference
The DAC of the MAX1365/MAX1367 accept either an
external reference or an internal reference. The REFSELE
enables or disables the internal reference. For externalreference
operation, disable the DAC reference buffer by
setting REFSELE to DVDD and connect a voltage source
to REF_DAC.
For internal-reference operation, enable the DAC reference
buffer by setting REFSELE to GND. In this mode,
leave REFDAC floating.
In either internal or external reference operation,
bypass REF_DAC with a 0.1μF capacitor to GND.
Choose a reference with output impedance (load regulation
equivalent) of 100mΩ or less, such as the
MAX6126. For best performance, use an external
reference source for the ADC and DAC.
DAC Operation
For the MAX1365/MAX1367, a voltage proportional to
the ADC input is available at DACVOUT. Connect
DACVOUT to CONV_IN for normal operation. See
Figure 11 for the DAC transfer function.
Offset Calibration
The MAX1365/MAX1367 offer on-chip offset calibration.
The device offset calibrates during every conversion
cycle.
Enhanced Offset Calibration
Enhanced offset calibration is a more accurate calibration
method that is needed in the case of the ±200mV
range and 4.5-digit resolution. In addition to enhanced
offset calibration at power-up, the MAX1365/MAX1367
perform enhanced calibration on demand by connecting
HOLD to AVDD for > 2s.
Peak
The MAX1365/MAX1367 feature peak-detection circuitry.
When activated, the devices display only the highest
voltage measured to the LED. First, the current ADC
result is displayed. The new ADC conversion result is
compared to the current result. If the new value is larger
than the previous peak value, the new value is displayed.
If the new value is less than the previous peak
value, the display remains unchanged. Connect PEAK
to GND to clear the peak value and disable the peak
function. See Table 1 for LED Display priority.
Hold
The MAX1365/MAX1367 feature data-hold circuitry.
When activated, the device holds the current reading
on the LED.
Strain-Gauge Measurement
Connect the differential inputs of the MAX1365/
MAX1367 to the bridge network of the strain gauge. In
Figure 6, the analog supply voltage powers the bridge
network and the MAX1365/MAX1367, along with the
reference voltage. The MAX1365/MAX1367 handle an
analog input voltage range of ±200mV and ±2V full
scale. The analog/reference inputs of the parts allow
the analog input range to have an absolute value of
anywhere between -2.2V and +2.2V.
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
16 ______________________________________________________________________________________
Transfer Functions
ADC Transfer Functions
Figures 7–10 show the transfer functions of the
MAX1365/MAX1367. The output data is stored in the
ADC data register in two’s complement.
The transfer function for the MAX1365 with AIN+ - AIN-
≥ 0 and RANGE = GND is:
The transfer function for the MAX1365 with AIN+ - AIN-
< 0 and RANGE = GND is:
The transfer function for the MAX1367 with AIN+ - AIN-
≥ 0 and RANGE = GND is:
(3) COUNT 1.024 2000
V V
V V
AIN AIN x
REF REF
=
+ − −
+ − −
(2) COUNT 1.024 20,000 1
V V
V V
AIN AIN x
REF REF
=
+ − − +
+ − −
(1) COUNT 1.024 20,000
V V
V V
AIN AIN x
REF REF
=
+ − −
+ − −
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 17
-2V 0
ANALOG INPUT VOLTAGE
+2V
LED
1 - - - -
19,999
2
1
0
- 0
- 1
- 2
-19,999
- 1 - - - -
-100μV 100μV
Figure 7. MAX1365 Transfer Function—±2V Range
-200mV 0
ANALOG INPUT VOLTAGE
+200mV
LED
1 - - - -
19,999
2
1
0
- 0
- 1
- 2
-19,999
- 1 - - - -
-10μV 10μV
Figure 8. MAX1365 Transfer Function—±200mV Range
-2V 0
ANALOG INPUT VOLTAGE
+2V
LED
1 - - -
1999
2
1
0
- 0
- 1
- 2
-1999
- 1 - - -
-1mV 1mV
Figure 10. MAX1367 Transfer Function—±2V Range
-200mV 0
ANALOG INPUT VOLTAGE
+200mV
LED
1 - - -
1999
2
1
0
- 0
- 1
- 2
-1999
- 1 - - -
-100μV 100μV
Figure 9. MAX1367 Transfer Function—±200mV Range
MAX1365/MAX1367
The transfer function for the MAX1367 with AIN+ - AIN-
< 0 and RANGE = GND is:
The transfer function for the MAX1365 with AIN+ - AIN-
≥ 0 and RANGE = DVDD is:
The transfer function for the MAX1365 with AIN+ - AIN-
< 0 and RANGE = DVDD is:
(6) COUNT 1.024 20,000 10 1
V V
V V
AIN AIN x x
REF REF
=
+ − − +
+ − −
(5) COUNT 1.024 20,000 10
V V
V V
AIN AIN x x
REF REF
=
+ − −
+ − −
(4) COUNT 1.024 2000 1
V V
V V
AIN AIN x
REF REF
=
+ − − +
+ − −
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
18 ______________________________________________________________________________________
- FS + FS
ADC OUTPUT CODE
0
DAC OUTPUT VOLTAGE (V)
0
1. 25
UNIPOLAR :
BIPLOLAR :
FS = FULL SCALE
Figure 11. DAC Output Voltage vs. ADC Output Code
UNIPOLAR :
BIPLOLAR :
ADC OUTPUT CODE
4-20OUT (mA)
20
FS = FULL SCALE
0
16
4
- FS 0 + FS
CURRENT
OFFSET
ENABLED
(EN_I = 1)
12
Figure 12. Output Current (4-20OUT) vs. ADC Output Code
(Current Offset Enabled)
OFFSET ENABLED :
OFFSET DISABLED :
V/I CONVERTER INPUT ( V )
0
4-20OUT (mA)
20
0
16
4
1. 25
Figure 14. 4-20OUT Output Current vs. V/I Converter Input
Voltage
UNIPOLAR :
BIPLOLAR :
ADC OUTPUT CODE
4-20OUT (mA)
16
FS = FULL SCALE
0
- FS 0 + FS
CURRENT
OFFSET
DISABLED
(EN_I = 0)
8
Figure 13. Output Current (4-20OUT) vs. ADC Output Code
(Current Offset Disabled)
The transfer function for the MAX1367 with AIN+ - AIN-
≥ 0 and RANGE = DVDD is:
The transfer function for the MAX1367 with AIN+ - AIN-
< 0 and RANGE = DVDD is:
DAC Transfer Functions
Figure 11 shows the DAC transfer function for the
MAX1365/MAX1367 in unipolar and bipolar modes.
The transfer function for the DAC in the MAX1365/
MAX1367 unipolar mode is:
where N = two’s complement ADC output code.
In unipolar mode, VDACVOUT is equal to 0V for all two’s
complement ADC codes less than zero (see Figure 12).
The transfer function for the DAC in the MAX1365/
MAX1367 in bipolar mode is:
where N = two’s complement ADC output.
Voltage-to-Current Transfer Function
Figures 12 and 13 show the MAX1365/MAX1367 transfer
function of the output current (4-20OUT) versus the
ADC input code.
The transfer function for the MAX1365/MAX1367 with
the current offset enabled (EN_I is high) is:
The transfer function for the MAX1365/MAX1367 with
the current offset disabled (EN_I is low) is:
Supplies, Layout, and Bypassing
Power up AVDD and DVDD before applying an analog
input and external-reference voltage to the device. If
this is not possible, limit the current into these inputs to
50mA. When the analog and digital supplies come from
the same source, isolate the digital supply from the
analog supply with a low-value resistor (10Ω) or ferrite
bead. For best performance, ground the MAX1365/
MAX1367 to the analog ground plane of the circuit
board. Avoid running digital lines under the device as
this can couple noise onto the IC. Run the analog
ground plane under the MAX1365/MAX1367 to minimize
coupling of digital noise. Make the power-supply
lines to the MAX1365/MAX1367 as wide as possible to
provide low-impedance paths and reduce the effects of
glitches on the power-supply line. Shield fast-switching
signals, such as clocks, with digital ground to avoid
radiating noise to other sections of the board. Avoid
running clock signals near the analog inputs. Avoid
crossover of digital and analog signals. Running traces
that are on opposite sides of the board at right angles to
each other reduces feedthrough effects. Good decoupling
is important when using high-resolution ADCs.
Decouple the supplies with 0.1μF ceramic capacitors to
GND. Place these components as close to the device
as possible to achieve the best decoupling.
Selecting Segment Current
A resistor from ISET to ground sets the current for each
LED segment. See Table 6 for more detail. Use the following
formula to set the segment current:
RISET values below 25kΩ increase the ISEG. However,
the internal current-limit circuit limits the ISEG to less than
30mA. At higher ISEG values, proper operation of the
device is not guaranteed. In addition, the power dissipated
may exceed the package power-dissipation limit.
Choosing Supply Voltage to Minimize
Power Dissipation
The MAX1365/MAX1367 drive a peak current of 25.5mA
into LEDs with a 2.2V forward voltage drop when operated
from a supply voltage of at least 3.0V. Therefore, the
minimum voltage drop across the internal LED drivers is
0.8V (3.0V - 2.2V = 0.8V). The MAX1365/MAX1367 sink
when the outputs are operating and the LED segment
drivers are at full current (8 x 25.5mA = 204mA). For a
3.3V supply, the MAX1365/MAX1367 dissipate 224.4mW
((3.3V - 2.2V) x 204 = 224.4mW). If a higher supply voltage
is used, the driver absorbs a higher voltage, and the
driver’s power dissipation increases accordingly.
I
V
R
SEG x
ISET
=
1 20
450
.
IOUT
mA
≅ x VCONV IN
16
1.25
_
IOUT
mA
≅ x VCONV IN + mA
16
1 25
4
.
_
V
N
DACVOUT = x VREF
+19 999
65 536
,
,
V
N
DACVOUT = x VREF
32,768−1
(8) COUNT 1.024 2000 10 1
V V
V V
AIN AIN x x
REF REF
=
+ − − +
+ − −
(7) COUNT 1.024 2000 10
V V
V V
AIN AIN x x
REF REF
=
+ − −
+ − −
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 19
Note: The input at VCONV_IN expects a source impedance
of typically 6kΩ when driving VCONV_IN externally.
MAX1365/MAX1367
However, if the LEDs used have a higher forward voltage
drop than 2.2V, the supply voltage must be raised
accordingly to ensure that the driver always has at least
0.8V headroom. For a LEDV supply voltage of 2.7V, the
maximum LED forward voltage is 1.9V to ensure 0.8V driver
headroom. The voltage drop across the drivers with
a nominal +5V supply (5.0V - 2.2V = 2.8V) is almost
three times the drop across the drivers with a nominal
3.3V supply (3.3V - 2.2V = 1.1V). Therefore, the driver’s
power dissipation increases three times. The power dissipation
in the part causes the junction temperature to
rise accordingly. In the high ambient temperature case,
the total junction temperature may be very high
(> +125°C). At higher junction temperatures, the ADC
performance degrades. To ensure the dissipation limit
for the MAX1365/MAX1367 is not exceeded and the
ADC performance is not degraded; a diode can be
inserted between the power supply and LEDV.
Selecting Depletion-Mode FET
An external depletion-mode FET (DMOS) works in conjunction
with the regulator circuit to supply the V/I converter
with loop power. REG_FORCE regulates the gate
of the DMOS so that the drain voltage is 5.2V (typ) and
allows the 4–20mA (0 to 16mA) loop to be directly powered
from a 7V to 30V supply. DMOS IDS consists of the
current output at 4-20OUT, a 4mA offset current, and
1mA (typ) consumed by the V/I converter.
For offset-enabled mode (EN_I = 1):
IDS = I4-20OUT + 4mA + 1mA
where IDS is the current in the DMOS.
For offset-disabled mode (EN_I = 0):
IDS = I4-20OUT + 1mA
where IDS is the current in the DMOS.
Table 7 provides the FET characteristics for selecting
an external DMOS transistor. The DN25D FET transistor
from Supertex meets all the requirements of Table 7.
Other suitable transistors include ND2020L and
ND2410L from Siliconix.
Connect a 0.1μF capacitor between CMP and
REG_FORCE to ensure stable regulator compensation.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best-straight-line fit or a line drawn between the end
points of the transfer function, once offset and gain
errors have been nullified. INL for the MAX1365/
MAX1367 is measured using the end-point method.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of ±1 LSB. A DNL error specification of
less than ±1 LSB guarantees no missing codes and a
monotonic transfer function.
Rollover Error
Rollover error is defined as the absolute-value difference
between a near positive full-scale reading and
near negative full-scale reading. Rollover error is tested
by applying a full-scale positive voltage, swapping
AIN+ and AIN-, and adding the results.
Zero-Input Reading
Ideally, with AIN+ connected to AIN-, the MAX1365/
MAX1367 LED displays zero. Zero-input reading is the
measured deviation from the ideal zero and the actual
measured point.
Gain Error
Gain error is the amount of deviation between the measured
full-scale transition point and the ideal full-scale
transition point.
Common-Mode Rejection (CMR)
CMR is the ability of a device to reject a signal that is
common to both input terminals. The common-mode
signal can be either an AC or a DC signal or a combination
of the two. CMR is often expressed in decibels.
Normal-Mode 50Hz and 60Hz Rejection
(Simultaneously)
Normal-mode rejection is a measure of how much output
changes when 50Hz and 60Hz signals are injected into
only one of the differential inputs. The MAX1365/
MAX1367 sigma-delta converter uses its internal digital
filter to provide normal-mode rejection to both 50Hz and
60Hz power-line frequencies simultaneously.
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
20 ______________________________________________________________________________________
Power-Supply Rejection (PSR)—ADC
PSR is a measure of the data converter’s level of immunity
to power-supply fluctuations. PSR assumes that the
converter’s linearity is unaffected by changes in the
power-supply voltage. Power-supply rejection ratio
(PSRR) is the ratio of the input signal change to the
change in the converter output. PSRR is typically measured
in dB.
Power-Supply Rejection—V/I Converter
PSR is a measure of the data converter’s level of immunity
to power-supply fluctuations. PSR assumes that the
converter’s linearity is unaffected by changes in the
power-supply voltage.
Note: The V/I converter current output (4–20mA)
power-supply rejection is with respect to the 7V to 30V
loop supply.
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 21
RSET (kΩ) ISEG (mA)
25 21.6
50 10.8
100 5.4
500 1.1
> 2500 LED driver disabled
Table 6. Segment-Current Selection
FET TYPE N-CHANNEL DEPLETION MODE
IDS 30mA
BVDS (VEXT* - REG_VDD) min
VPINCHOFF REG_VDD max
Power dissipation 30mA x (VEXT - REG_VDD) min
Table 7. FET Characteristics
*VEXT is the 7V to 30V loop voltage.
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
22 ______________________________________________________________________________________
MAX1365
MAX6126
0.1μF 10μF
10μF
0.1μF
0.1μF
10μF
10μF
LISO
RL
2.7V TO
5.25V
4.75V TO
5.25V
DEPLETIONMODE
FET
VEXT
7V TO 30V
4-20mA
PLC INPUT
ADC
AIN+
IN
DAC_VDD
SUPPLY VOLTAGE
0.1μF
AINLEDV
4-20mA/0 TO 16mA
CURRENT-LOOP OUTPUT
LED_EN
DVDD
AVDD
DAC_VDD
GND_DAC REF_DAC
SET NEGV GND REF- REF+ LEDG GND_V/I
DACVOUT
OUTF
OUTS
CONV_IN
EN_BPM
EN_I
TO DVDD
DACDATA_SEL
CS_DAC
REFSELE
INTREF
RANGE
PEAK
HOLD
DPON
DPSET2
DPSET1
DIG0–DIG4
DIGIT
CONNECTIONS
SEGA–SEGDP
SEGMENT
CONNECTIONS
VIN
CMP
GNDS GND
REG_FORCE
REG_VDD
REG_AMP
4-20OUT
25kΩ
0.1μF
0.1μF
MAX1365 Typical Operating Circuit
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
______________________________________________________________________________________ 23
MAX1367
MAX6126
0.1μF 10μF
10μF
0.1μF
0.1μF
10μF
10μF
LISO
RL
2.7V TO
5.25V
4.75V TO
5.25V
DEPLETIONMODE
FET
VEXT
7V TO 30V
4-20mA
PLC INPUT
ADC
AIN+
IN
DAC_VDD
SUPPLY VOLTAGE
0.1μF
AINLEDV
4-20mA/0 TO 16mA
CURRENT-LOOP OUTPUT
LED_EN
DVDD
AVDD
DAC_VDD
DIGO GND_DAC REF_DAC
SET NEGV GND REF- REF+ LEDG GND_V/I
DACVOUT
OUTF
OUTS
CONV_IN
EN_BPM
EN_I
TO DVDD
DACDATA_SEL
CS_DAC
REFSELE
INTREF
RANGE
PEAK
HOLD
DPON
DPSET2
DPSET1
DIG1–DIG4
DIGIT
CONNECTIONS
SEGA–SEGDP
SEGMENT
CONNECTIONS
VIN
CMP
GNDS GND
REG_FORCE
REG_VDD
REG_AMP
4-20OUT
25kΩ
0.1μF
0.1μF
MAX1367 Typical Operating Circuit
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
24 ______________________________________________________________________________________
TOP VIEW
MAX1365
MAX1367
TQFP
13
14
15
16
17
18
19
20
21
22
23
24
CONV_IN
4-200UT
GDN_DAC
GND_V/I
REF_DAC
EN_BPM
EN_I
REFSELE
DACDATA_SEL
CS_DAC
INTREF
RANGE
48
47
46
45
44
43
42
41
40
39
38
37
1 2 3 4 5 6 7 8 9 10 11 12
REF+
REFDPON
NEGV
LED_EN
SEGDP
SEGG
SEGF
SEGE
SEGD
SEGC
LEDV
DACVOUT
DAC_VDD
CMP
REG_AMP
REG_FORCE
REG_VDD
SET
DVDD
AVDD
GND
AINAIN+
36 35 34 33 32 31 30 29 28 27 26 25
PEAK
HOLD
DPSET2
DPSET1
LEDG
DIG0
DIG1
DIG2
DIG3
DIG4
SEGA
SEGB
Pin Configuration
Chip Information
TRANSISTOR COUNT: 83,463
PROCESS: CMOS
MAX1365/MAX1367
Stand-Alone, 4.5-/3.5-Digit Panel Meters
with 4–20mA Output
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
E
1
21-0054 2
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
E
2
21-0054 2
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
1
623345fc
LT6233/LT6233-10
LT6234/LT6235
Typical Application
Features Description
60MHz, Rail-to-Rail Output,
1.9nV/√Hz, 1.2mA Op Amp Family
Low Noise Low Power Instrumentation Amplifier
Applications
n Low Noise Voltage: 1.9nV/√Hz
n Low Supply Current: 1.2mA/Amp Max
n Low Offset Voltage: 350μV Max
n Gain-Bandwidth Product:
LT6233: 60MHz; AV ≥ 1
LT6233-10: 375MHz; AV ≥ 10
n Wide Supply Range: 3V to 12.6V
n Output Swings Rail-to-Rail
n Common Mode Rejection Ratio: 115dB Typ
n Output Current: 30mA
n Operating Temperature Range: –40°C to 85°C
n LT6233 Shutdown to 10μA Maximum
n LT6233/LT6233-10 in a Low Profile (1mm)
ThinSOT™ Package
n Dual LT6234 in 8-Pin SO and Tiny DFN Packages
n LT6235 in a 16-Pin SSOP Package
n Ultrasound Amplifiers
n Low Noise, Low Power Signal Processing
n Active Filters
n Driving A/D Converters
n Rail-to-Rail Buffer Amplifiers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Noise Voltage and Unbalanced
Noise Current vs Frequency
The LT®6233/LT6234/LT6235 are single/dual/quad low
noise, rail-to-rail output unity-gain stable op amps that
feature 1.9nV/√Hz noise voltage and draw only 1.2mA of
supply current per amplifier. These amplifiers combine
very low noise and supply current with a 60MHz gainbandwidth
product, a 17V/μs slew rate and are optimized
for low supply voltage signal conditioning systems. The
LT6233-10 is a single amplifier optimized for higher gain
applications resulting in higher gain bandwidth and slew
rate. The LT6233 and LT6233-10 include an enable pin
that can be used to reduce the supply current to less
than 10μA.
The amplifier family has an output that swings within 50mV
of either supply rail to maximize the signal dynamic range
in low supply applications and is specified on 3.3V, 5V and
±5V supplies. The en • √ISUPPLY product of 2.1 per amplifier
is among the most noise efficient of any op amp.
The LT6233/LT6233-10 are available in the 6-lead SOT‑23
package and the LT6234 dual is available in the 8-pin SO
package with standard pinouts. For compact layouts,
the dual is also available in a tiny dual fine pitch leadless
package (DFN). The LT6235 is available in the 16-pin
SSOP package.
R6
499
VS
+
AV = 20
BW = 2.8MHz
VS = ±1.5V to ±5V
VOUT
VS
–
IN+
IN–
VS
–
VS
+
R7
499
R4
499
R2
475
R1
49.9
R3
475 R5
499
EN
IS = 3mA
EN = 8μVRMS INPUT REFERRED,
MEASUREMENT BW = 4MHz
623345 TA01a
–
+
LT6233
1/2 LT6234
1/2 LT6234
FREQUENCY (Hz)
NOISE VOLTAGE (nV/ Hz)
6
5
4
3
2
1
0
10 1k 10k 100k
623345 TA01b
100
VS = ±2.5V
TA = 25°C
VCM = 0V
NOISE VOLTAGE
NOISE CURRENT
UNBALANCED NOISE CURRENT (pA/ Hz)
6
5
4
3
2
1
0
LT6233/LT6233-10
LT6234/LT6235
2
623345fc
Absolute Maximum Ratings
Total Supply Voltage (V+ to V–)............................... 12.6V
Input Current (Note 2).......................................... ±40mA
Output Short-Circuit Duration (Note 3)............. Indefinite
Operating Temperature Range (Note 4)....–40°C to 85°C
Specified Temperature Range (Note 5).....–40°C to 85°C
Junction Temperature............................................ 150°C
(Note 1)
6 V+
5 ENABLE
4 –IN
OUT 1
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
V– 2
+IN 3
TJMAX = 150°C, θJA = 250°C/W
TOP VIEW
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
OUT A 1
–IN A
+IN A
V–
V+
OUT B
–IN B
+IN B
+
–
+
–
TJMAX = 125°C, θJA = 160°C/W
UNDERSIDE METAL CONNECTED TO V– (PCB CONNECTION OPTIONAL)
TOP VIEW
V+
OUT B
–IN B
+IN B
OUT A
–IN A
+IN A
V–
S8 PACKAGE
8-LEAD PLASTIC SO
1
2
3
4
8
7
6
5
+
–
+
–
TJMAX = 150°C, θJA = 190°C/W
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
NC
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
NC
+
–
+
–
+
–
+
–
A D
B C
TJMAX = 150°C, θJA = 135°C/W
Pin Configuration
Junction Temperature (DD Package)..................... 125°C
Storage Temperature Range................... –65°C to 150°C
Storage Temperature Range
(DD Package)......................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)....................300°C
3
623345fc
LT6233/LT6233-10
LT6234/LT6235
Electrical Characteristics TA = 25°C, VS = 5V, 0V; VS = 3.3V, 0V; VCM = VOUT = half supply,
ENABLE = 0V, unless otherwise noted.
Order Information
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE
LT6233CS6#PBF LT6233CS6#TRPBF LTAFL 6-Lead Plastic TS0T-23 0°C to 70°C
LT6233IS6#PBF LT6233IS6#TRPBF LTAFL 6-Lead Plastic TS0T-23 –40°C to 85°C
LT6233CS6-10#PBF LT6233CS6-10#TRPBF LTAFM 6-Lead Plastic TS0T-23 0°C to 70°C
LT6233IS6-10#PBF LT6233IS6-10#TRPBF LTAFM 6-Lead Plastic TS0T-23 –40°C to 85°C
LT6234CS8#PBF LT6234CS8#TRPBF 6234 8-Lead Plastic SO 0°C to 70°C
LT6234IS8#PBF LT6234IS8#TRPBF 6234I 8-Lead Plastic SO –40°C to 85°C
LT6234CDD#PBF LT6234CDD#TRPBF LAET 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C
LT6234IDD#PBF LT6234IDD#TRPBF LAET 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C
LT6235CGN#PBF LT6235CGN#TRPBF 6235 16-Lead Narrow Plastic SSOP 0°C to 70°C
LT6235IGN#PBF LT6235IGN#TRPBF 6235I 16-Lead Narrow Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage LT6233S6, LT6233S6-10
LT6234S8, LT6235GN
LT6234DD
100
50
75
500
350
450
μV
μV
μV
Input Offset Voltage Match
(Channel-to-Channel) (Note 6)
80 600 μV
IB Input Bias Current 1.5 3 μA
IB Match (Channel-to-Channel) (Note 6) 0.04 0.3 μA
IOS Input Offset Current 0.04 0.3 μA
Input Noise Voltage 0.1Hz to 10Hz 220 nVP-P
en Input Noise Voltage Density f = 10kHz, VS = 5V 1.9 3 nV/√Hz
in Input Noise Current Density, Balanced Source
Input Noise Current Density, Unbalanced Source
f = 10kHz, VS = 5V, RS = 10k
f = 10kHz, VS = 5V, RS = 10k
0.43
0.78
pA/√Hz
pA/√Hz
Input Resistance Common Mode
Differential Mode
22
25
MΩ
kΩ
CIN Input Capacitance Common Mode
Differential Mode
2.5
4.2
pF
pF
AVOL Large-Signal Gain VS = 5V, VO = 0.5V to 4.5V, RL = 10k to VS/2
VS = 5V, VO = 0.5V to 4.5V, RL = 1k to VS/2
73
18
140
35
V/mV
V/mV
VS = 3.3V, VO = 0.65V to 2.65V, RL = 10k to VS/2
VS = 3.3V, VO = 0.65V to 2.65V, RL = 1k to VS/2
53
11
100
20
V/mV
V/mV
VCM Input Voltage Range Guaranteed by CMRR, VS = 5V, 0V
Guaranteed by CMRR, VS = 3.3V, 0V
1.5
1.15
4
2.65
V
V
CMRR Common Mode Rejection Ratio VS = 5V, VCM = 1.5V to 4V
VS = 3.3V, VCM = 1.15V to 2.65V
90
85
115
110
dB
dB
CMRR Match (Channel-to-Channel) (Note 6) VS = 5V, VCM = 1.5V to 4V 84 115 dB
LT6233/LT6233-10
LT6234/LT6235
4
623345fc
Electrical Characteristics TA = 25°C, VS = 5V, 0V; VS = 3.3V, 0V; VCM = VOUT = half supply,
ENABLE = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
PSRR Power Supply Rejection Ratio VS = 3V to 10V 90 115 dB
PSRR Match (Channel-to-Channel) (Note 6) VS = 3V to 10V 84 115 dB
Minimum Supply Voltage (Note 7) 3 V
VOL Output Voltage Swing Low (Note 8) No Load
ISINK = 5mA
VS = 5V, ISINK = 15mA
VS = 3.3V, ISINK = 10mA
4
75
165
125
40
180
320
240
mV
mV
mV
mV
VOH Output Voltage Swing High (Note 8) No Load
ISOURCE = 5mA
VS = 5V, ISOURCE = 15mA
VS = 3.3V, ISOURCE = 10mA
5
85
220
165
50
195
410
310
mV
mV
mV
mV
ISC Short-Circuit Current VS = 5V
VS = 3.3V
±40
±35
±55
±50
mA
mA
IS Supply Current per Amplifier
Disabled Supply Current per Amplifier
ENABLE = V+ – 0.35V
1.05
0.2
1.2
10
mA
μA
IENABLE ENABLE Pin Current ENABLE = 0.3V –25 –75 μA
VL ENABLE Pin Input Voltage Low 0.3 V
VH ENABLE Pin Input Voltage High V+ – 0.35 V
Output Leakage Current ENABLE = V+ – 0.35V, VO = 1.5V to 3.5V 0.2 10 μA
tON Turn-On Time ENABLE = 5V to 0V, RL = 1k, VS = 5V 500 ns
tOFF Turn-Off Time ENABLE = 0V to 5V, RL = 1k, VS = 5V 76 μs
GBW Gain-Bandwidth Product Frequency = 1MHz, VS = 5V
LT6233-10
55
320
MHz
MHz
SR Slew Rate VS = 5V, A V = –1, RL = 1k, VO = 1.5V to 3.5V 10 15 V/μs
LT6233-10, VS = 5V, AV = –10, RL = 1k,
VO = 1.5V to 3.5V
80 V/μs
FPBW Full-Power Bandwidth VS = 5V, VOUT = 3VP-P (Note 9) 1.06 1.6 MHz
LT6233-10, HD2 = HD3 ≤ 1% 2.2 MHz
tS Settling Time (LT6233, LT6234, LT6235) 0.1%, VS = 5V, VSTEP = 2V, AV = –1, RL = 1k 175 ns
5
623345fc
LT6233/LT6233-10
LT6234/LT6235
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
VOS Input Offset Voltage LT6233CS6, LT6233CS6-10
LT6234CS8, LT6235CGN
LT6234CDD
l
l
l
600
450
550
μV
μV
μV
Input Offset Voltage Match
(Channel-to-Channel) (Note 6)
l 800 μV
VOS TC Input Offset Voltage Drift (Note 10) VCM = Half Supply l 0.5 3.0 μV/°C
IB Input Bias Current l 3.5 μA
IB Match (Channel-to-Channel) (Note 6) l 0.4 μA
IOS Input Offset Current l 0.4 μA
AVOL Large-Signal Gain VS = 5V, VO = 0.5V to 4.5V, RL = 10k to VS/2
VS = 5V, VO = 0.5V to 4.5V, RL = 1k to VS/2
l
l
47
12
V/mV
V/mV
VS = 3.3V, VO = 0.65V to 2.65V, RL = 10k to VS/2
VS = 3.3V, VO = 0.65V to 2.65V, RL = 1k to VS/2
l
l
40
7.5
V/mV
V/mV
VCM Input Voltage Range Guaranteed by CMRR
VS = 5V, 0V
Vs = 3.3V, 0V
l
l
1.5
1.15
4
2.65
V
V
CMRR Common Mode Rejection Ratio VS = 5V, VCM = 1.5V to 4V
VS = 3.3V, VCM = 1.15V to 2.65V
l
l
90
85
dB
dB
CMRR Match (Channel-to-Channel) (Note 6) VS = 5V, VCM = 1.5V to 4V l 84 dB
PSRR Power Supply Rejection Ratio VS = 3V to 10V l 90 dB
PSRR Match (Channel-to-Channel) (Note 6) VS = 3V to 10V l 84 dB
Minimum Supply Voltage (Note 7) l 3 V
VOL Output Voltage Swing Low (Note 8) No Load
ISINK = 5mA
VS = 5V, ISINK = 15mA
VS = 3.3V, ISINK = 10mA
l
l
l
l
50
195
360
265
mV
mV
mV
mV
VOH Output Voltage Swing High (Note 8) No Load
ISOURCE = 5mA
VS = 5V, ISOURCE = 15mA
VS = 3.3V, ISOURCE = 10mA
l
l
l
l
60
205
435
330
mV
mV
mV
mV
ISC Short-Circuit Current VS = 5V
VS = 3.3V
l
l
±35
±30
mA
mA
IS Supply Current per Amplifier
Disabled Supply Current per Amplifier
ENABLE = V+ – 0.25V
l
l
1
1.45 mA
μA
IENABLE ENABLE Pin Current ENABLE = 0.3V l –85 μA
VL ENABLE Pin Input Voltage Low l 0.3 V
VH ENABLE Pin Input Voltage High l V+ – 0.25 V
Output Leakage Current ENABLE = V+ – 0.25V, VO = 1.5V to 3.5V l 1 μA
tON Turn-On Time ENABLE = 5V to 0V, RL = 1k, VS = 5V l 500 ns
tOFF Turn-Off Time ENABLE = 0V to 5V, RL = 1k, VS = 5V l 120 μs
SR Slew Rate VS = 5V, AV = –1, RL = 1k, VO = 1.5V to 3.5V l 9 V/μs
LT6233-10, AV = –10, RL = 1k, VO = 1.5V to 3.5V l 75 V/μs
FPBW Full-Power Bandwidth (Note 9) VS = 5V, VOUT = 3VP-P; LT6233C, LT6234C,
LT6235C
l 955 kHz
Electrical Characteristics The l denotes the specifications which apply over the 0°C < TA < 70°C
temperature range. VS = 5V, 0V; VS = 3.3V, 0V; VCM = VOUT = half supply, ENABLE = 0V, unless otherwise noted.
LT6233/LT6233-10
LT6234/LT6235
6
623345fc
Electrical Characteristics The l denotes the specifications which apply over the –40°C < TA < 85°C
temperature range. VS = 5V, 0V; VS = 3.3V, 0V; VCM = VOUT = half supply, ENABLE = 0V, unless otherwise noted. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage LT6233IS6, LT6233IS6-10
LT6234IS8, LT6235IGN
LT6234IDD
l
l
l
700
550
650
μV
μV
μV
Input Offset Voltage Match
(Channel-to-Channel) (Note 6)
l 1000 μV
VOS TC Input Offset Voltage Drift (Note 10) VCM = Half Supply l 0.5 3 μV/°C
IB Input Bias Current l 4 μA
IB Match (Channel-to-Channel) (Note 6) l 0.4 μA
IOS Input Offset Current l 0.5 μA
AVOL Large-Signal Gain VS = 5V, VO = 0.5V to 4.5V, RL = 10k to VS/2
VS = 5V, VO = 0.5V to 4.5V, RL = 1k to VS/2
l
l
45
11
V/mV
V/mV
VS = 3.3V, VO = 0.65V to 2.65V, RL = 10k to VS/2
VS = 3.3V, VO = 0.65V to 2.65V, RL = 1k to VS/2
l
l
38
7
V/mV
V/mV
VCM Input Voltage Range Guaranteed by CMRR
VS = 5V, 0V
VS = 3.3V, 0V
l
l
1.5
1.15
4
2.65
V
V
CMRR Common Mode Rejection Ratio VS = 5V, VCM = 1.5V to 4V
VS = 3.3V, VCM = 1.15V to 2.65V
l
l
90
85
dB
dB
CMRR Match (Channel-to-Channel) (Note 6) VS = 5V, VCM = 1.5V to 4V l 84 dB
PSRR Power Supply Rejection Ratio VS = 3V to 10V l 90 dB
PSRR Match (Channel-to-Channel) (Note 6) VS = 3V to 10V l 84 dB
Minimum Supply Voltage (Note 7) l 3 V
VOL Output Voltage Swing Low (Note 8) No Load
ISINK = 5mA
VS = 5V, ISINK = 15mA
VS = 3.3V, ISINK = 10mA
l
l
l
l
50
195
370
275
mV
mV
mV
mV
VOH Output Voltage Swing High (Note 6) No Load
ISOURCE = 5mA
VS = 5V, ISOURCE = 15mA
VS = 3.3V, ISOURCE = 10mA
l
l
l
l
60
210
445
335
mV
mV
mV
mV
ISC Short-Circuit Current VS = 5V
VS = 3.3V
l
l
±30
±20
mA
mA
IS Supply Current per Amplifier
Disabled Supply Current per Amplifier
ENABLE = V+ – 0.2V
l
l
1
1.5 mA
μA
IENABLE ENABLE Pin Current ENABLE = 0.3V l –100 μA
VL ENABLE Pin Input Voltage Low l 0.3 V
VH ENABLE Pin Input Voltage High l V+ – 0.2 V
Output Leakage Current ENABLE = V+ – 0.2V, VO = 1.5V to 3.5V l 1 μA
tON Turn-On Time ENABLE = 5V to 0V, RL = 1k, VS = 5V l 500 ns
tOFF Turn-Off Time ENABLE = 0V to 5V, RL = 1k, VS = 5V l 135 μs
SR Slew Rate VS = 5V, AV = –1, RL = 1k, VO = 1.5V to 3.5V l 8 V/μs
LT6233-10, AV = –10, RL = 1k, VO = 1.5V to 3.5V l 70 V/μs
FPBW Full-Power Bandwidth (Note 9) VS = 5V, VOUT = 3VP-P; LT6233I, LT6234I,
LT6235I
l 848 kHz
7
623345fc
LT6233/LT6233-10
LT6234/LT6235
Electrical Characteristics TA = 25°C, VS = ±5V, VCM = VOUT = 0V, ENABLE = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage LT6233S6, LT6233S6-10
LT6234S8, LT6235GN
LT6234DD
100
50
75
500
350
450
μV
μV
μV
Input Offset Voltage Match
(Channel-to-Channel) (Note 6)
100 600 μV
IB Input Bias Current 1.5 3 μA
IB Match (Channel-to-Channel) (Note 6) 0.04 0.3 μA
IOS Input Offset Current 0.04 0.3 μA
Input Noise Voltage 0.1Hz to 10Hz 220 nVP-P
en Input Noise Voltage Density f = 10kHz 1.9 3.0 nV/√Hz
in Input Noise Current Density, Balanced Source
Input Noise Current Density, Unbalanced Source
f = 10kHz, RS = 10k
f = 10kHz, RS = 10k
0.43
0.78
pA/√Hz
pA/√Hz
Input Resistance Common Mode
Differential Mode
22
25
MΩ
kΩ
CIN Input Capacitance Common Mode
Differential Mode
2.1
3.7
pF
pF
AVOL Large-Signal Gain VO = ±4.5V, RL = 10k
VO = ±4.5V, RL = 1k
97
28
180
55
V/mV
V/mV
VCM Input Voltage Range Guaranteed by CMRR –3 4 V
CMRR Common Mode Rejection Ratio VCM = –3V to 4V 90 110 dB
CMRR Match (Channel-to-Channel) (Note 6) VCM = –3V to 4V 84 120 dB
PSRR Power Supply Rejection Ratio VS = ±1.5V to ±5V 90 115 dB
PSRR Match (Channel-to-Channel) (Note 6) VS = ±1.5V to ±5V 84 115 dB
VOL Output Voltage Swing Low (Note 8) No Load
ISINK = 5mA
ISINK = 15mA
4
75
165
40
180
320
mV
mV
mV
VOH Output Voltage Swing High (Note 8) No Load
ISOURCE = 5mA
ISOURCE = 15mA
5
85
220
50
195
410
mV
mV
mV
ISC Short-Circuit Current ±40 ±55 mA
IS Supply Current per Amplifier
Disabled Supply Current per Amplifier
ENABLE = 4.65V
1.15
0.2
1.4
10
mA
μA
IENABLE ENABLE Pin Current ENABLE = 0.3V –35 –85 μA
VL ENABLE Pin Input Voltage Low 0.3 V
VH ENABLE Pin Input Voltage High 4.65 V
Output Leakage Current ENABLE = 4.65V, VO = ±1V 0.2 10 μA
tON Turn-On Time ENABLE = 5V to 0V, RL = 1k 900 ns
tOFF Turn-Off Time ENABLE = 0V to 5V, RL = 1k 100 μs
GBW Gain-Bandwidth Product Frequency = 1MHz
LT6233-10
42
260
60
375
MHz
MHz
SR Slew Rate AV = –1, RL = 1k, VO = –2V to 2V 12 17 V/μs
LT6233-10, AV = –10, RL = 1k, VO = –2V to 2V 115 V/μs
FPBW Full-Power Bandwidth VOUT = 3VP-P (Note 9) 1.27 1.8 MHz
LT6233-10, HD2 = HD3 ≤ 1% 2.2 MHz
tS Settling Time (LT6233, LT6234, LT6235) 0.1%, VSTEP = 2V, AV = –1, RL = 1k 170 ns
LT6233/LT6233-10
LT6234/LT6235
8
623345fc
Electrical Characteristics The l denotes the specifications which apply over the 0°C < TA < 70°C
temperature range. VS = ±5V, VCM = VOUT = 0V, ENABLE = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage LT6233CS6, LT6233CS6-10
LT6234CS8, LT6235CGN
LT6234CDD
l
l
l
600
450
550
μV
μV
μV
Input Offset Voltage Match
(Channel-to-Channel) (Note 6)
l 800 μV
VOS TC Input Offset Voltage Drift (Note 10) l 0.5 3 μV/°C
IB Input Bias Current l 3.5 μA
IB Match (Channel-to-Channel) (Note 6) l 0.4 μA
IOS Input Offset Current l 0.4 μA
AVOL Large-Signal Gain VO = ±4.5V, RL = 10k
VO = ±4.5V, RL = 1k
l
l
75
22
V/mV
V/mV
VCM Input Voltage Range Guaranteed by CMRR l –3 4 V
CMRR Common Mode Rejection Ratio VCM = –3V to 4V l 90 dB
CMRR Match (Channel-to-Channel) (Note 6) VCM = –3V to 4V l 84 dB
PSRR Power Supply Rejection Ratio VS = ±1.5V to ±5V l 90 dB
PSRR Match (Channel-to-Channel) (Note 6) VS = ±1.5V to ±5V l 84 dB
VOL Output Voltage Swing Low (Note 8) No Load
ISINK = 5mA
ISINK = 15mA
l
l
l
50
195
360
mV
mV
mV
VOH Output Voltage Swing High (Note 8) No Load
ISOURCE = 5mA
ISOURCE = 15mA
l
l
l
60
205
435
mV
mV
mV
ISC Short-Circuit Current l ±35 mA
IS Supply Current per Amplifier
Disabled Supply Current per Amplifier
ENABLE = 4.75V
l
l
1
1.7 mA
μA
IENABLE ENABLE Pin Current ENABLE = 0.3V l –95 μA
VL ENABLE Pin Input Voltage Low l 0.3 V
VH ENABLE Pin Input Voltage High l 4.75 V
Output Leakage Current ENABLE = 4.75V, VO = ±1V l 1 μA
tON Turn-On Time ENABLE = 5V to 0V, RL = 1k l 900 ns
tOFF Turn-Off Time ENABLE = 0V to 5V, RL = 1k l 150 μs
SR Slew Rate AV = –1, RL = 1k, VO = –2V to 2V l 11 V/μs
LT6233-10, AV = –10, RL = 1k, VO = –2V to 2V l 105 V/μs
FPBW Full-Power Bandwidth (Note 9) VOUT = 3VP-P ; LT6233C, LT6234C, LT6235C l 1.16 MHz
9
623345fc
LT6233/LT6233-10
LT6234/LT6235
Electrical Characteristics The l denotes the specifications which apply over the –40°C < TA < 85°C
temperature range. VS = ±5V, VCM = VOUT = 0V, ENABLE = 0V, unless otherwise noted. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage LT6233IS6, LT6233IS6-10
LT6234IS8, LT6235IGN
LT6234IDD
l
l
l
700
550
650
μV
μV
μV
Input Offset Voltage Match
(Channel-to-Channel) (Note 6)
l 1000 μV
VOS TC Input Offset Voltage Drift (Note 10) l 0.5 3 μV/°C
IB Input Bias Current l 4 μA
IB Match (Channel-to-Channel) (Note 6) l 0.4 μA
IOS Input Offset Current l 0.5 μA
AVOL Large-Signal Gain VO = ±4.5V, RL = 10k
VO = ±4.5V, RL = 1k
l
l
68
20
V/mV
V/mV
VCM Input Voltage Range Guaranteed by CMRR l –3 4 V
CMRR Common Mode Rejection Ratio VCM = –3V to 4V l 90 dB
CMRR Match (Channel-to-Channel) (Note 6) VCM = –3V to 4V l 84 dB
PSRR Power Supply Rejection Ratio VS = ±1.5V to ±5V l 90 dB
PSRR Match (Channel-to-Channel) (Note 6) VS = ±1.5V to ±5V l 84 dB
VOL Output Voltage Swing Low (Note 8) No Load
ISINK = 5mA
ISINK = 15mA
l
l
l
50
195
370
mV
mV
mV
VOH Output Voltage Swing High (Note 8) No Load
ISOURCE = 5mA
ISOURCE = 15mA
l
l
l
70
210
445
mV
mV
mV
ISC Short-Circuit Current l ±30 mA
IS Supply Current per Amplifier
Disabled Supply Current per Amplifier
ENABLE = 4.8V
l
l
1
1.75 mA
μA
IENABLE ENABLE Pin Current ENABLE = 0.3V l –110 μA
VL ENABLE Pin Input Voltage Low l 0.3 V
VH ENABLE Pin Input Voltage High l 4.8 V
Output Leakage Current ENABLE = 4.8V, VO = ±1V l 1 μA
tON Turn-On Time ENABLE = 5V to 0V, RL = 1k l 900 ns
tOFF Turn-Off Time ENABLE = 0V to 5V, RL = 1k l 160 μs
SR Slew Rate AV = –1, RL = 1k, VO = –2V to 2V l 10 V/μs
LT6233-10, AV = –10, RL = 1k, VO = –2V to 2V l 95 V/μs
FPBW Full-Power Bandwidth (Note 9) VOUT = 3VP-P; LT6233I, LT6234I, LT6235I l 1.06 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Inputs are protected by back-to-back diodes. If the differential
input voltage exceeds 0.7V, the input current must be limited to less than
40mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LT6233C/LT6233I the LT6234C/LT6234I, and LT6235C/LT6235I
are guaranteed functional over the temperature range of –40°C to 85°C.
Note 5: The LT6233C/LT6234C/LT6235C are guaranteed to meet specified
performance from 0°C to 70°C. The LT6233C/LT6234C/LT6235C are
designed, characterized and expected to meet specified performance from
–40°C to 85°C, but are not tested or QA sampled at these temperatures.
The LT6233I/LT6234I/LT6235I are guaranteed to meet specified
performance from –40°C to 85°C.
Note 6: Matching parameters are the difference between the two amplifiers
A and D and between B and C of the LT6235; between the two amplifiers
of the LT6234. CMRR and PSRR match are defined as follows: CMRR and
PSRR are measured in μV/V on the matched amplifiers. The difference is
calculated between the matching sides in μV/V. The result is converted to
dB.
LT6233/LT6233-10
LT6234/LT6235
10
623345fc
Note 7: Minimum supply voltage is guaranteed by power supply rejection
ratio test.
Note 8: Output voltage swings are measured between the output and
power supply rails.
Electrical Characteristics
Note 9: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/2πVP
Note 10: This parameter is not 100% tested.
Typical Performance Characteristics
Input Bias Current
vs Common Mode Voltage Input Bias Current vs Temperature
Output Saturation Voltage
vs Load Current (Output Low)
VOS Distribution
Supply Current vs Supply Voltage
(Per Amplifier)
Offset Voltage vs Input Common
Mode Voltage
(LT6233/LT6234/LT6235)
INPUT OFFSET VOLTAGE (μV)
–200
0
NUMBER OF UNITS
10
20
30
40
–100 0 100 200
623345 GO1
50
60
–150 –50 50 150
VS = 5V, 0V
VCM = V+/2
S8
TOTAL SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
6
623345 GO2
2 4 8
2.0
1.5
1.0
0.5
0
10 12 14
TA = 125°C
TA = 25°C
TA = –55°C
INPUT COMMON MODE VOLTAGE (V)
0
OFFSET VOLTAGE (μV)
1.5
623345 GO3
0.5 1 2
500
400
300
200
100
0
–100
–200
–300
–400
–500
2.5 3 3.5 4 4.5 5
TA = –55°C
TA = 25°C
TA = 125°C
VS = 5V, 0V
COMMON MODE VOLTAGE (V)
–1
INPUT BIAS CURRENT (μA)
2
623345 GO4
0 1 3
6
5
4
3
2
1
0
–2
–1
4 5 6
TA = 125°C
TA = –55°C
TA = 25°C
VS = 5V, 0V
TEMPERATURE (°C)
–50
INPUT BIAS CURRENT (μA)
25
623345 GO5
–25 0 50
6
5
4
3
2
1
0
–1
75 100 125
VCM = 4V
VCM = 1.5V
VS = 5V, 0V
LOAD CURRENT (mA)
0.01 0.1
0.0001
OUTPUT SATURATION VOLTAGE (V)
0.01
10
1 10 100
623345 GO6
0.001
0.1
1
VS = 5V, 0V
TA = –55°C
TA = 125°C
TA = 25°C
11
623345fc
LT6233/LT6233-10
LT6234/LT6235
Typical Performance Characteristics
Open-Loop Gain Open-Loop Gain Open-Loop Gain
Offset Voltage vs Output Current Warm-Up Drift vs Time
Total Noise vs Total Source
Resistance
Output Saturation Voltage
vs Load Current (Output High) Minimum Supply Voltage
Output Short-Circuit Current
vs Power Supply Voltage
(LT6233/LT6234/LT6235)
LOAD CURRENT (mA)
OUTPUT SATURATION VOLTAGE (V)
623345 G07
0.01 0.1
0.01
10
1 10 100
0.001
0.1
1
VS = 5V, 0V
TA = –55°C
TA = 125°C
TA = 25°C
TOTAL SUPPLY VOLTAGE (V)
0
OFFSET VOLTAGE (mV)
1.5
623345 G08
0.5 1 2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
2.5 3 3.5 4 4.5 5
TA = –55°C
TA = 125°C
TA = 25°C
VCM = VS/2
POWER SUPPLY VOLTAGE (±V)
1.5
OUTPUT SHORT-CIRCUIT CURRENT (mA)
3.0
623345 GO9
2.0 2.5 3.5
80
60
40
20
0
–20
–40
–80
–60
4.0 4.5 5.0
TA = 125°C
TA = –55°C
TA = –55°C
TA = 25°C
SINKING
SOURCING
TA = 25°C
TA = 125°C
OUTPUT VOLTAGE (V)
0
INPUT VOLTAGE (mV)
1.5
623345 G10
0.5 1.0 2.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
2.5 3.0
RL = 100
RL = 1k
VS = 3V, 0V
TA = 25°C
OUTPUT VOLTAGE (V)
0
INPUT VOLTAGE (mV)
1.5
623345 G11
0.5 1 2
0
2.5 3 3.5 4 4.5 5
RL = 100
RL = 1k
VS = 5V, 0V
TA = 25°C
2.5
2.0
1.5
1.0
0.5
–0.5
–1.0
–1.5
–2.0
–2.5
OUTPUT VOLTAGE (V)
–5
INPUT VOLTAGE (mV)
–2
623345 G12
–4 –3 –1
0
0 1 2 3 4 5
RL = 100
RL = 1k
VS = ±5V
TA = 25°C
2.5
2.0
1.5
1.0
0.5
–0.5
–1.0
–1.5
–2.0
–2.5
OUTPUT CURRENT (mA)
–90
OFFSET VOLTAGE (mV)
623345 G13
–60 –30
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0 30 60 90
TA = –55°C
TA = 125°C
VS = ±5V
TA = 25°C
TIME AFTER POWER-UP (s)
0
CHANGE IN OFFSET VOLTAGE (μV)
20
623345 G14
10 30
40
35
30
25
20
15
10
0
40 50
TA = 25°C
VS = ±5V
VS = ±2.5V
VS = ±1.5V
TOTAL SOURCE RESISTANCE ( )
1
TOTAL NOISE (nV/ Hz)
10
10 1k 10k 100k
623345 G15
0.1
100
100
VS = ±2.5V
VCM = 0V
f = 100kHz
UNBALANCED
SOURCE
RESISTORS
TOTAL NOISE
RESISTOR NOISE
AMPLIFIER NOISE VOLTAGE
LT6233/LT6233-10
LT6234/LT6235
12
623345fc
Typical Performance Characteristics
Open-Loop Gain vs Frequency
Gain Bandwidth and Phase Margin
vs Supply Voltage Slew Rate vs Temperature
Output Impedance vs Frequency
Common Mode Rejection Ratio
vs Frequency Channel Separation vs Frequency
Noise Voltage and Unbalanced
Noise Current vs Frequency
0.1Hz to 10Hz Output Voltage
Noise
Gain Bandwidth and Phase Margin
vs Temperature
(LT6233/LT6234/LT6235)
FREQUENCY (Hz)
NOISE VOLTAGE (nV/ Hz)
6
5
4
3
2
1
0
10 1k 10k 100k
623345 G16
100
VS = ±2.5V
TA = 25°C
VCM = 0V
NOISE VOLTAGE
NOISE CURRENT
UNBALANCED NOISE CURRENT (pA/ Hz)
6
5
4
3
2
1
0
5s/DIV
623345 G17
100nV
100nV/DIV
–100nV
VS = ±2.5V
TEMPERATURE (°C)
–55
GAIN BANDWIDTH (MHz)
5
623345 G18
–25 35
90
80
70
60
40
50
PHASE MARGIN (DEG)
70
60
50
40
65 95 125
VS = ±5V
VS = 3V, 0V
VS = ±5V
VS = 3V, 0V
PHASE MARGIN
GAIN BANDWIDTH
CL = 5pF
RL = 1k
VCM = VS/2
FREQUENCY (Hz)
GAIN (dB)
80
70
50
30
0
–10
60
40
10
20
–20
PHASE (DEG)
120
100
60
20
–60
80
40
–20
–40
0
–80
100k 10M 100M 1G
623345 G19
1M
CL = 5pF
RL = 1k
VCM = VS/2
PHASE
GAIN
VS = ±5V
VS = 3V, 0V
V VS = ±5V S = 3V, 0V
TOTAL SUPPLY VOLTAGE (V)
0
GAIN BANDWIDTH (MHz)
6
623345 G20
2 4 8
70
60
50
30
40
PHASE MARGIN (DEG)
80
70
60
50
40
10 12 14
PHASE MARGIN
GAIN BANDWIDTH
TA = 25°C
CL = 5pF
RL = 1k
TEMPERATURE (°C)
–55
SLEW RATE (V/μs)
5
623345 G21
–35 –15 45
20
22
24
26
18
16
14
10
12
25 65 85 105 125
VS = ±5V FALLING
VS = ±2.5V RISING
AV = –1
RF = RG = 1k
VS = ±2.5V FALLING
VS = ±5V RISING
FREQUENCY (Hz)
1
OUTPUT IMPEDANCE ( )
10
100k 10M 100M
623345 G22
0.1
1M
1k
100
VS = 5V, 0V
AV = 10
AV = 1
AV = 2
FREQUENCY (Hz)
20
COMMON MODE REJECTION RATIO (dB)
40
60
80
120
100
10k 100k 10M 100M 1G
623345 G23
0
1M
VS = 5V, 0V
VCM = VS/2
FREQUENCY (Hz)
100k
CHANNEL SEPARATION (dB)
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
1M 10M 100M
623345 G24
AV = 1
TA = 25°C
VS = ±5V
13
623345fc
LT6233/LT6233-10
LT6234/LT6235
Typical Performance Characteristics
Settling Time vs Output Step
(Noninverting)
Settling Time vs Output Step
(Inverting)
Maximum Undistorted Output
Signal vs Frequency
Distortion vs Frequency Distortion vs Frequency Distortion vs Frequency
Power Supply Rejection Ratio
vs Frequency
Series Output Resistance and
Overshoot vs Capacitive Load
Series Output Resistance and
Overshoot vs Capacitive Load
(LT6233/LT6234/LT6235)
FREQUENCY (Hz)
20
POWER SUPPLY REJECTION RATIO (dB)
40
60
80
120
100
1k 10k 100k 10M 100M
623345 G25
0
1M
VS = 5V, 0V
TA = 25°C
VCM = VS/2
NEGATIVE SUPPLY
POSITIVE SUPPLY
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
50
45
40
35
30
25
20
15
10
5
0
100 1000
623345 G26
VS = 5V, 0V
AV = 1
RS = 10
RS = 20
RS = 50
RL = 50
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
50
45
40
35
30
25
20
15
10
5
0
100 1000
623345 G27
VS = 5V, 0V
AV = 2
RS = 10
RS = 20
RS = 50
RL = 50
OUTPUT STEP (V)
–4
SETTLING TIME (ns)
0
623345 G28
–3 –2 –1 1
300
400
350
250
200
150
50
100
2 3 4
1mV
10mV
1mV
10mV
VS = ±5V
TA = 25°C
AV = 1
+
–
500
VOUT
VIN
OUTPUT STEP (V)
–4
SETTLING TIME (ns)
0
623345 G29
–3 –2 –1 1
300
400
350
250
200
150
50
100
2 3 4
1mV
10mV
1mV
10mV
VS = ±5V
TA = 25°C
AV = –1
+
–
500
500
VOUT
VIN
FREQUENCY (Hz)
10k
OUTPUT VOLTAGE SWING (VP-P)
10
9
8
7
6
5
4
3
2
100k 1M 10M
623345 G30
VS = ±5V
TA = 25°C
HD2, HD3 < –40dBc
AV = –1
AV = 2
FREQUENCY (Hz)
10k
DISTORTION (dBc)
–40
–50
–60
–70
–80
–90
–100
100k 1M 10M
623345 G31
VS = ±2.5V
AV = 1
VOUT = 2VP-P
RL = 100 , 3RD
RL = 1k, 3RD
RL = 1k, 2ND
RL = 100 , 2ND
FREQUENCY (Hz)
10k
DISTORTION (dBc) –
40
–50
–60
–70
–80
–90
–100
100k 1M 10M
623345 G32
VS = ±5V
AV = 1
VOUT = 2VP-P
RL = 100 , 3RD
RL = 1k, 3RD
RL = 1k, 2ND
RL = 100 , 2ND
FREQUENCY (Hz)
10k
DISTORTION (dBc)
–30
–40
–50
–60
–70
–80
–90
–100
100k 1M 10M
623345 G33
VS = ±2.5V
AV = 2
VOUT = 2VP-P
RL = 100 , 3RD
RL = 1k, 3RD
RL = 1k, 2ND
RL = 100 , 2ND
LT6233/LT6233-10
LT6234/LT6235
14
623345fc
Typical Performance Characteristics
Distortion vs Frequency Large-Signal Response Small-Signal Response
(LT6233/LT6234/LT6235)
Large-Signal Response Output Overdrive Recovery
(LT6233) ENABLE Characteristics
Supply Current
vs ENABLE Pin Voltage
ENABLE Pin Current
vs ENABLE Pin Voltage ENABLE Pin Response Time
FREQUENCY (Hz)
10k
DISTORTION (dBc)
–30
–40
–50
–60
–70
–80
–90
–100
100k 1M 10M
623345 G34
VS = ±5V
AV = 2
VOUT = 2VP-P
RL = 100 , 3RD
RL = 1k, 3RD
RL = 1k, 2ND
RL = 100 , 2ND
2V
0V
–2V
200ns/DIV 623345 G35 VS = ±2.5V
AV = –1
RL = 1k
1V/DIV
0V
200ns/DIV 623345 G36 VS = ±2.5V
AV = 1
RL = 1k
50mV/DIV
0V
5V
–5V
200ns/DIV 623345 G37 VS = ±5V
AV = 1
RL = 1k
2V/DIV
0V
0V
200ns/DIV 623345 G38 VS = ±2.5V
AV = 3
VIN
1V/DIV
VOUT
2V/DIV
PIN VOLTAGE (V)
SUPPLY CURRENT (mA)
–1.0
623345 G39
–2.0 0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.0 2.0
TA = 125°C
VS = ±2.5V
TA = 25°C
TA = –55°C
PIN VOLTAGE (V)
ENABLE PIN CURRENT (μA)
623345 G40
35
30
25
20
15
10
5
0
TA = 125°C
VS = ±2.5V
AV = 1
TA = 25°C
TA = –55°C
–2.0 –1.0 0 1.0 2.0
0V
5V
0.5V
0V
200μs/DIV 623345 G41 VS = ±2.5V
VIN = 0.5V
AV = 1
RL = 1k
VOUT ENABLE
15
623345fc
LT6233/LT6233-10
LT6234/LT6235
Typical Performance Characteristics
Open-Loop Gain and Phase
vs Frequency
Gain Bandwidth and Phase Margin
vs Supply Voltage Gain Bandwidth vs Resistor Load
Common Mode Rejection Ratio
vs Frequency
Maximum Undistorted Output
vs Frequency
2nd and 3rd Harmonic Distortion
vs Frequency
Gain Bandwidth and Phase Margin
vs Temperature Slew Rate vs Temperature
Series Output Resistor and
Overshoot vs Capacitive Load
(LT6233-10)
TEMPERATURE (°C)
–50
GAIN BANDWIDTH (MHz)
25
623345 G42
–25 0 50
450
400
350
300
200
250
PHASE MARGIN (DEG)
70
60
50
40
75 100 125
VS = ±5V
VS = 3V, 0V
VS = ±5V
VS = 3V, 0V
PHASE MARGIN
GAIN BANDWIDTH
AV = 10
TEMPERATURE (°C)
–55
SLEW RATE (V/μs)
5
623345 G43
–35 –15 45
140
160
180
200
120
100
60
0
20
80
40
25 65 85 105 125
VS = ±5V FALLING
VS = ±2.5V RISING
AV = –10
RF = 1k
RG = 100
VS = ±2.5V FALLING
VS = ±5V RISING
CAPACITIVE LOAD (pF)
10
OVERSHOOT (%)
70
60
50
40
30
20
10
0
100 1000 10000
623345 G44
VS = 5V, 0V
AV = 10 RS = 10
RS = 20
RS = 50
FREQUENCY (Hz)
GAIN (dB)
80
70
60
50
40
30
20
10
0
–10
–20
PHASE (DEG)
120
100
80
60
40
20
0
–20
–40
–60
–80
100k 10M 100M 1G
623345 G45
1M
AV = 10
CL = 5pF
RL = 1k
VCM = VS/2
VS = 3V, 0V
VS = ±5V
PHASE
GAIN
VS = ±5V
VS = 3V, 0V
TOTAL SUPPLY VOLTAGE (V)
0
GAIN BANDWIDTH (MHz)
6
623345 G46
2 4 8
450
375
300
225
PHASE MARGIN (DEG)
100
50
0
10 12
PHASE MARGIN
GAIN BANDWIDTH
TA = 25°C
AV = 10
CL = 5pF
RL = 1k
TOTAL RESISTOR LOAD ( )
(INCLUDES FEEDBACK R)
0
GAIN BANDWIDTH (MHz)
600
623345 G47
200 400 800
400
350
300
200
150
100
50
0
250
1000
AVSV = 1±05V
TA = 25°C
RF = 1k
RG = 100
FREQUENCY (Hz)
20
COMMON MODE REJECTION RATIO (dB)
40
60
80
120
100
10k 100k 10M 100M 1G
623345 G48
0
1M
VS = 5V, 0V
VCM = VS/2
FREQUENCY (Hz)
10k
OUTPUT VOLTAGE SWING (VP-P)
10
9
8
7
6
5
4
3
2
1
0
100k 1M 10M
623345 G49
VS = ±5V
TA = 25°C
AV = 10
HD2, HD3 40dBc
FREQUENCY (Hz)
10k
DISTORTION (dBc)
–30
–40
–50
–60
–70
–80
–90
–100
100k 1M 10M
623345 G50
VS = ±2.5V
AV = 10
VOUT = 2VP-P
RL = 100 , 3RD
RL = 100 , 2ND
RL = 1k, 3RD
RL = 1k, 2ND
LT6233/LT6233-10
LT6234/LT6235
16
623345fc
Typical Performance Characteristics
2nd and 3rd Harmonic Distortion
vs Frequency Large-Signal Response Output-Overload Recovery
(LT6233-10)
Small-Signal Response
Input Referred High Frequency
Noise Spectrum
FREQUENCY (Hz)
10k
DISTORTION (dBc)
–30
–40
–50
–60
–70
–80
–90
–100
100k 1M 10M
623345 G51
VS = ±5V
AV = 10
VOUT = 2VP-P
RL = 100 , 3RD
RL = 100 , 2ND
RL = 1k, 3RD
RL = 1k, 2ND
0V
100ns/DIV 623345 G52 VS = ±5V
AV = 10
RF = 900
RG = 100
VOUT
2V/DIV
0V
100ns/DIV 623345 G53 VS = 5V, 0V
AV = 10
RF = 900
RG = 100
VOUT
2V/DIV
0V
VIN
0.5V/DIV
2.5V
100ns/DIV 623345 G54 VS = 5V, 0V
AV = 10
RF = 900
RG = 100
VOUT
100mV/DIV
10
0
2MHz/DIV 623345 G55
100kHz 20MHz
1nV/ Hz/DIV
17
623345fc
LT6233/LT6233-10
LT6234/LT6235
Applications Information
Figure 1. Simplified Schematic
Figure 2. VS = ±2.5V, AV = 1 with Large Overdrive
ENABLE
DESD6
DESD5
–V
+V
+VIN
–VIN
+V
623345 F01
BIAS
DIFFERENTIAL
DRIVE GENERATOR
VOUT
+V
CM
I1
–V
DESD3
–V
–V
DESD4
+V
DESD1
–V
DESD2
+V
D1
C1
D2
Q5
Q6
Q4
Q2
Q3
Q1
2.5V
–2.5V
0V
500μs/DIV 623345 F02
1V/DIV
Amplifier Characteristics
Figure 1 is a simplified schematic of the LT6233/LT6234/
LT6235, which has a pair of low noise input transistors
Q1 and Q2. A simple current mirror Q3/Q4 converts the
differential signal to a single-ended output, and these
transistors are degenerated to reduce their contribution
to the overall noise.
Capacitor C1 reduces the unity-cross frequency and improves
the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor CM sets the overall
amplifier gain bandwidth. The differential drive generator
supplies current to transistors Q5 and Q6 that swing the
output from rail-to-rail.
Input Protection
There are back-to-back diodes, D1 and D2 across the + and
– inputs of these amplifiers to limit the differential input
voltage to ±0.7V. The inputs of the LT6233/LT6234/LT6235
do not have internal resistors in series with the input transistors.
This technique is often used to protect the input
devices from overvoltage that causes excessive current
to flow. The addition of these resistors would significantly
degrade the low noise voltage of these amplifiers. For
instance, a 100Ω resistor in series with each input would
generate 1.8nV/√Hz of noise, and the total amplifier noise
voltage would rise from 1.9nV/√Hz to 2.6nV/√Hz. Once
the input differential voltage exceeds ±0.7V, steady-state
current conducted through the protection diodes should
be limited to ±40mA. This implies 25Ω of protection resistance
is necessary per volt of overdrive beyond ±0.7V.
These input diodes are rugged enough to handle transient
currents due to amplifier slew rate overdrive and clipping
without protection resistors.
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. With the input signal low, current source I1 saturates
and the differential drive generator drives Q6 into
saturation so the output voltage swings all the way to V–.
The input can swing positive until transistor Q2 saturates
into current mirror Q3/Q4. When saturation occurs, the
output tries to phase invert, but diode D2 conducts current
from the signal source to the output through the feedback
connection. The output is clamped a diode drop below the
input. In this photo, the input signal generator is limiting
at about 20mA.
LT6233/LT6233-10
LT6234/LT6235
18
623345fc
Applications Information
With the amplifier connected in a gain of AV ≥ 2, the output
can invert with very heavy overdrive. To avoid this inversion,
limit the input overdrive to 0.5V beyond the power
supply rails.
ESD
The LT6233/LT6234/LT6235 have reverse-biased ESD
protection diodes on all inputs and outputs as shown in
Figure 1. If these pins are forced beyond either supply,
unlimited current will flow through these diodes. If the
current is transient and limited to one hundred milliamps
or less, no damage to the device will occur.
Noise
The noise voltage of the LT6233/LT6234/LT6235 is
equivalent to that of a 225Ω resistor, and for the lowest
possible noise it is desirable to keep the source and feedback
resistance at or below this value, i.e., RS + RG||RFB
≤ 225Ω. With RS + RG||RFB = 225Ω the total noise of the
amplifier is:
eN = √(1.9nV)2 + (1.9nV)2 = 2.69nV/√Hz
Below this resistance value, the amplifier dominates the
noise, but in the region between 225Ω and about 30k,
the noise is dominated by the resistor thermal noise. As
the total resistance is further increased beyond 30k, the
amplifier noise current multiplied by the total resistance
eventually dominates the noise.
The product of eN • √ISUPPLY is an interesting way to
gauge low noise amplifiers. Most low noise amplifiers
with low eN have high ISUPPLY current. In applications that
require low noise voltage with the lowest possible supply
current, this product can prove to be enlightening. The
LT6233/LT6234/LT6235 have an eN • √ISUPPLY product of
only 2.1 per amplifier, yet it is common to see amplifiers
with similar noise specifications to have eN • √ISUPPLY as
high as 13.5.
For a complete discussion of amplifier noise, see the
LT1028 data sheet.
Enable Pin
The LT6233 and LT6233-10 include an ENABLE pin that
shuts down the amplifier to 10μA maximum supply current.
The ENABLE pin must be driven low to operate the
amplifier with normal supply current. The ENABLE pin
must be driven high to within 0.35V of V+ to shut down
the supply current. This can be accomplished with simple
gate logic; however care must be taken if the logic and the
LT6233 operate from different supplies. If this is the case,
then open-drain logic can be used with a pull-up resistor
to ensure that the amplifier remains off. See Typical
Performance Characteristics.
The output leakage current when disabled is very low;
however, current can flow into the input protection diodes
D1 and D2 if the output voltage exceeds the input voltage
by a diode drop.
19
623345fc
LT6233/LT6233-10
LT6234/LT6235
Typical Applications
Single Supply, Low Noise, Low Power, Bandpass Filter with Gain = 10
Frequency Response Plot of
Bandpass Filter
Low Power, Low Noise, Single Supply, Instrumentation Amplifier with Gain = 100
R2
732
R4
10k
C3
0.1μF
EN
f0 = 1 = 1MHz
C = C1,C2 R = R1 = R2
f0 = (732 )MHz, MAXIMUM f0 = 1MHz
f–3dB = f0
AV = 20dB at f0
EN = 6μVRMS INPUT REFERRED
IS = 1.5mA FOR V+ = 5V
623345 F03
0.1μF
C2
47pF
C1
1000pF R3
10k
R1
732
VOUT
V+
VIN
2πRC
R
2.5
+
–
LT6233
FREQUENCY (Hz)
100k
GAIN (dB)
23
3
–7
1M 10M
623345 F04
+
–
R14
2k
EN
U3
LT6233
VOUT = 100 (VIN2 – VIN1)
GAIN = (R2 + 1) (R10)
INPUT RESISTANCE = R5 = R6
f–3dB = 310Hz TO 2.5MHz
EN = 10μVRMS INPUT REFERRED
IS = 4.7mA FOR VS = 5V, 0V 623345 F05
C8
68pF
C3
1μF
R13
2k
R10
511
R15
88.7
R16
88.7
R4
511
R3
30.9
R1
30.9
R2
511
VOUT
VIN1
VIN2
V+
R1 R15
C9
68pF
R12
511
+
–
EN
U2
LT6233-10
V+
C1
1μF
C2
2200pF
+
–
EN
U1
LT6233-10
V+
R5
511
R6
511
C4
10μF
R1 = R3
R2 = R4
R10 = R12
R15 = R16
LT6233/LT6233-10
LT6234/LT6235
20
623345fc
Package Description
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
2.62 REF 1.4 MIN
1.22 REF
21
623345fc
LT6233/LT6233-10
LT6234/LT6235
Package Description
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
4 1
5 8
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ± 0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
2.10 ±0.05 (2 SIDES)
0.50
BSC
0.70 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
LT6233/LT6233-10
LT6234/LT6235
22
623345fc
Package Description
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)
× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1 2 3 4
.150 – .157
(3.810 – 3.988)
NOTE 3
8 7 6 5
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
1 2 3 4 5 6 7 8
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10)
× 45°
.007 – .0098 0° – 8° TYP
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0165 ±.0015 .0250 BSC
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
23
623345fc
LT6233/LT6233-10
LT6234/LT6235
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Revision History
REV DATE DESCRIPTION PAGE NUMBER
C 1/11 Revised y-axis lable on curve G40 in Typical Performance Characteristics
Updated ENABLE Pin section in Applications Information
14
18
(Revision history begins at Rev C)
LT6233/LT6233-10
LT6234/LT6235
24
623345fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2003
LT 0111 REV C • PRINTED IN USA
Related Parts
Typical Applications
Low Power Avalanche Photodiode Transimpedance Amplifier
IS = 1.2mA
Photodiode Amplifier Time Domain Response
PART NUMBER DESCRIPTION COMMENTS
LT1028 Single, Ultralow Noise 50MHz Op Amp 0.85nV/√Hz
LT1677 Single, Low Noise Rail-to-Rail Amplifier 3V Operation, 2.5mA, 4.5nV/√Hz, 60μV Max VOS
LT1806/LT1807 Single/Dual, Low Noise 325MHz Rail-to-Rail Amplifier 2.5V Operation, 550μV Max VOS, 3.5nV/√Hz
LT6200/LT6201 Single/Dual, Low Noise 165MHz 0.95nV√Hz, Rail-to-Rail Input and Output
LT6202/LT6203/LT6204 Single/Dual/Quad, Low Noise, Rail-to-Rail Amplifier 1.9nV/√Hz, 3mA Max, 100MHz Gain Bandwidth
The LT6233 is applied as a transimpedance amplifier with
an I-to-V conversion gain of 10kΩ set by R1. The LT6233
is ideally suited to this application because of its low input
offset voltage and current, and its low noise. This is
because the 10k resistor has an inherent thermal noise of
13nV/√Hz or 1.3pA/√Hz at room temperature, while the
LT6233 contributes only 2nV and 0.8pA/√Hz. So, with
respect to both voltage and current noises, the LT6233 is
actually quieter than the gain resistor.
The circuit uses an avalanche photodiode with the cathode
biased to approximately 200V. When light is incident on
the photodiode, it induces a current IPD which flows into
the amplifier circuit. The amplifier output falls negative
to maintain balance at its inputs. The transfer function
is therefore VOUT = –IPD • 10k. C1 ensures stability and
good settling characteristics. Output offset was measured
at better than 500μV, so low in part because R2 serves to
cancel the DC effects of bias current. Output noise was
measured at below 1mVP-P on a 20MHz measurement
bandwidth, with C2 shunting R2’s thermal noise. As shown
in the scope photo, the rise time is 45ns, indicating a signal
bandwidth of 7.8MHz.
+
–
R1
10k
R2
10k
C2
0.1μF
5V
–5V
ENABLE
LT6233
200V BIAS
ADVANCED PHOTONIX
012-70-62-541
WWW.ADVANCEDPHOTONIX.COM
OUTPUT OFFSET = 500μV TYPICAL
BANDWIDTH = 7.8MHz
OUTPUT NOISE = 1mVP-P (20MHz MEASUREMENT BW)
623345 TA02a
C1
2.7pF
100ns/DIV 623345 TA02b
50mV/DIV
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8300
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
FUNCTIONAL BLOCK DIAGRAM
VDD
VOUT
GND
CLR
LD
CS
CLK
SDI AD8300
12
12
12-BIT
REF DAC
DAC
REGISTER
EN
SERIAL
REGISTER
+3 Volt, Serial Input
Complete 12-Bit DAC
FEATURES
Complete 12-Bit DAC
No External Components
Single +3 Volt Operation
0.5 mV/Bit with 2.0475 V Full Scale
6 ms Output Voltage Settling Time
Low Power: 3.6 mW
Compact SO-8 1.5 mm Height Package
APPLICATIONS
Portable Communications
Digitally Controlled Calibration
Servo Controls
PC Peripherals
GENERAL DESCRIPTION
The AD8300 is a complete 12-bit, voltage-output digital-toanalog
converter designed to operate from a single +3 volt supply.
Built using a CBCMOS process, this monolithic DAC
offers the user low cost, and ease-of-use in single-supply +3 volt
systems. Operation is guaranteed over the supply voltage range
of +2.7 V to +5.5 V making this device ideal for battery operated
applications.
The 2.0475 V full-scale voltage output is laser trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half-millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 5 mA.
A double buffered serial data interface offers high speed, threewire,
DSP and microcontroller compatible inputs using data in
(SDI), clock (CLK) and load strobe (LD) pins. A chip select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, a CLR
input sets the output to zero scale at power on or upon user
demand.
The AD8300 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8300s are available in plastic
DIP, and low profile 1.5 mm height SO-8 surface mount packages.
3.0
2.8
2.0
0.01 0.1 1.0 10
2.6
2.4
2.2
OUTPUT LOAD CURRENT – mA
MINIMUM SUPPLY VOLTAGE – Volts
PROPER OPERATION
WHEN VDD SUPPLY
VOLTAGE ABOVE
CURVE
DVFS 1 LSB
DATA = FFFH
TA = +258C
Figure 1. Minimum Supply Voltage vs. Load
1.00
0.75
–1.00
0 1024 2048 4096
0.50
3072
0.25
0.00
–0.25
–0.50
–0.75
DIGITAL INPUT CODE – Decimal
INL LINEARITY ERROR – LSB
VDD = +2.7V
TA = –408C, +258C, +1258C
= –408C
= +258C
= +1258C
Figure 2. Linearity Error vs. Digital Code and Temperature
–2– REV. A
AD8300–SPECIFICATIONS
+3 V OPERATION
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N [Note 1] 12 Bits
Relative Accuracy INL –2 ±1/2 +2 LSB
Differential Nonlinearity2 DNL Monotonic –1 ±1/2 +1 LSB
Zero-Scale Error VZSE Data = 000H +1/2 +3 mV
Full-Scale Voltage3 VFS Data = FFFH 2.039 2.0475 2.056 Volts
Full-Scale Tempco TCVFS [Notes 3, 4] 16 ppm/°C
ANALOG OUTPUT
Output Current (Source) IOUT Data = 800H, DVOUT = 5 LSB 5 mA
Output Current (Sink) IOUT Data = 800H, DVOUT = 5 LSB 2 mA
Load Regulation LREG RL = 200 W to ¥, Data = 800H 1.5 5 LSB
Output Resistance to GND ROUT Data = 000H 30 W
Capacitive Load CL No Oscillation4 500 pF
LOGIC INPUTS
Logic Input Low Voltage VIL 0.6 V
Logic Input High Voltage VIH 2.1 V
Input Leakage Current IIL 10 mA
Input Capacitance CIL 10 pF
INTERFACE TIMING
SPECIFICATIONS4, 5
Clock Width High tCH 40 ns
Clock Width Low tCL 40 ns
Load Pulsewidth tLDW 50 ns
Data Setup tDS 15 ns
Data Hold tDH 15 ns
Clear Pulsewidth tCLRW 40 ns
Load Setup tLD1 15 ns
Load Hold tLD2 40 ns
Select tCSS 40 ns
Deselect tCSH 40 ns
AC CHARACTERISTICS4
Voltage Output Settling Time tS To ±0.2% of Full Scale 7 ms
To ±1 LSB of Final Value6 14 ms
Output Slew Rate SR Data = 000H to FFFH to 000H 2.0 V/ms
DAC Glitch 15 nV/s
Digital Feedthrough 15 nV/s
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE DNL < ±1 LSB 2.7 5.5 V
Positive Supply Current IDD VDD = 3 V, VIL = 0 V, Data = 000H 1.2 1.7 mA
VDD = 3.6 V, VIH = 2.3 V, Data = FFFH 1.9 3.0 mA
Power Dissipation PDISS VDD = 3 V, VIL = 0 V, Data = 000H 3.6 5.1 mW
Power Supply Sensitivity PSS DVDD = ±5% 0.001 0.005 %/%
NOTES
1LSB = 0.5 mV for 0 V to +2.0475 V output range.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ VDD = +5 V 6 10%, –408C £ TA £ +858C, unless otherwise noted)
REV. A –3–
AD8300
+5 V OPERATION
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N [Note 1] 12 Bits
Relative Accuracy INL –2 ±1/2 +2 LSB
Differential Nonlinearity2 DNL Monotonic –1 ±1/2 +1 LSB
Zero-Scale Error VZSE Data = 000H +1/2 +3 mV
Full-Scale Voltage3 VFS Data = FFFH 2.039 2.0475 2.056 Volts
Full-Scale Tempco TCVFS [Notes 3, 4] 16 ppm/°C
ANALOG OUTPUT
Output Current (Source) IOUT Data = 800H, DVOUT = 5 LSB 5 mA
Output Current (Sink) IOUT Data = 800H, DVOUT = 5 LSB 2 mA
Load Regulation LREG RL = 200 W to ¥, Data = 800H 1.5 5 LSB
Output Resistance to GND ROUT Data = 000H 30 W
Capacitive Load CL No Oscillation4 500 pF
LOGIC INPUTS
Logic Input Low Voltage VIL 0.8 V
Logic Input High Voltage VIH 2.4 V
Input Leakage Current IIL 10 mA
Input Capacitance CIL 10 pF
INTERFACE TIMING
SPECIFICATIONS4, 5
Clock Width High tCH 30 ns
Clock Width Low tCL 30 ns
Load Pulsewidth tLDW 30 ns
Data Setup tDS 15 ns
Data Hold tDH 15 ns
Clear Pulsewidth tCLWR 30 ns
Load Setup tLD1 15 ns
Load Hold tLD2 30 ns
Select tCSS 30 ns
Deselect tCSH 30 ns
AC CHARACTERISTICS4
Voltage Output Settling Time tS To ±0.2% of Full Scale 6 ms
To ±1 LSB of Final Value6 13 ms
Output Slew Rate SR Data = 000H to FFFH to 000H 2.2 V/ms
DAC Glitch 15 nV/s
Digital Feedthrough 15 nV/s
SUPPLY CHARACTERISTICS
Power Supply Range VDD RANGE DNL < ±1 LSB 2.7 5.5 V
Positive Supply Current IDD VDD = 5 V, VIL = 0 V, Data = 000H 1.2 1.7 mA
VDD = 5.5 V, VIH = 2.3 V, Data = FFFH 2.8 4.0 mA
Power Dissipation PDISS VDD = 5 V, VIL = 0 V, Data = 000H 6 5.1 mW
Power Supply Sensitivity PSS DVDD = ±10% 0.001 0.006 %/%
NOTES
11 LSB = 0.5 mV for 0 V to +2.0475 V output range.
2The first two codes (000H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ VDD = +5 V 6 10%, –408C £ TA £ +858C, unless otherwise noted)
REV. A
AD8300
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (TJ Max – TA)/qJA
Thermal Resistance qJA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
SO-8 Plastic DIP
1
2
3
4
TOP VIEW
(Not to Scale)
8
7
6
5
AD8300
VDD
CS
CLK
SDI
VOUT
GND
LD
CLR
1
4
8
5
ORDERING GUIDE
Package Package
Model INL Temp Description Options
AD8300AN ±2 XIND 8-Lead P-DIP N-8
AD8300AR ±2 XIND 8-Lead SOIC SO-8
NOTES
XIND = –40°C to +85°C.
The AD8300 contains 630 transistors. The die size measures 72 mil ´ 65 mil.
PIN DESCRIPTIONS
Pin # Name Function
1 VDD Positive power supply input. Specified range
of operation +2.7 V to +5.5 V.
2 CS Chip Select, active low input. Disables shift
register loading when high. Does not affect
LD operation.
3 CLK Clock input, positive edge clocks data into
shift register.
4 SDI Serial Data Input, input data loads directly
into the shift register, MSB first.
5 LD Load DAC register strobes, active low.
Transfers shift register data to DAC register.
See Truth Table I for operation. Asynchronous
active low input.
6 CLR Resets DAC register to zero condition.
Asynchronous active low input.
7 GND Analog and Digital Ground.
8 VOUT DAC voltage output, 2.0475 V full scale
with 0.5 mV per bit. An internal temperature
stabilized reference maintains a fixed
full-scale voltage independent of time, temperature
and power supply variations.
SDI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tCSS
tLD1
tCSH
tLD2
CLK
CS
LD
SDI
CLK
CLR
LD
61LSB
ERROR BAND
FS
ZS
tDS tDH
tCL
tCH
tLDW
tS
tCLRW
tS
VOUT
Figure 3. Timing Diagram
REV. A
AD8300
–5–
2.5
2.0
0
0 1 4 5 6
0.5
1.0
1.5
2 3
VDD SUPPLY VOLTAGE – Volts
LOGIC THRESHOLD VOLTAGE
TA = –40 TO +858C
Figure 5. Logic Input Threshold
Voltage vs. VDD
50
45
0
10 100 10k 100k 1M
40
35
30
25
20
15
10
5
1k
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
VDD = +3V 610%
VDD = +5V 610%
TA = +258C
DATA = FFFH
Figure 8. Power Supply Rejection
vs. Frequency
CODE 800H TO 7FFH
Figure 11. Midscale Transition
Performance
80
40
–80
0 1 2
–40
0
60
20
–60
–20
OUTPUT VOLTAGE – Volts
OUTPUT CURRENT – mA
VDD = +3V
VDD = +5V
VDD = +3V
POSITIVE VDD = +5V
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
DATA = 800H
RL TIED TO +1.024V
Figure 4. IOUT vs. VOUT
TIME = 100ms/DIV
BROADBAND NOISE – 200mV/DIV
Figure 7. Broadband Noise
3.5
3.0
0
0 1 3 4 5
1.5
2.5
2.0
2
LOGIC VOLTAGE – Volts
SUPPLY CURRENT – mA
VDD = +5V
VDD = +3V
TA = +258C
DATA = FFFH
1.0
0.5
Figure 10. Supply Current vs. Logic
Input Voltage
HORIZONTAL = 1ms/DIV
Figure 6. Detail Settling Time
HORIZONTAL = 20ms/DIV
Figure 9. Large Signal Settling Time
0.5ms/DIV
Figure 12. Digital Feedthrough vs.
Time
Typical Performance Characteristics–
REV. A
AD8300
–6–
1.5
1.0
–1.5
–55 –35 –15 5 25 45 65 85 105 125
0.5
0
–0.5
–1.0
VOUT DRIFT – mV
TEMPERATURE – 8C
VDD = +2.7V
VDD = +5V
NO LOAD
ss = 300 UNITS
NORMALIZED TO +258C
Figure 14. Zero-Scale Voltage Drift
vs. Temperature
10
1
0.01
1 10 100 1k 10k 100k
0.1
FREQUENCY – Hz
NOISE DENSITY – mV/Hz
VDD = +3V
DATA = FFFH
Figure 17. Output Voltage Noise
Density vs. Frequency
2.4
2.0
0
0 100 200 300 500 600
0.8
1.2
1.6
0.4
400
HOURS OF OPERATION AT +1508C
NOMINAL VOLTAGE CHANGE – mV
FULL SCALE (DATA = FFFH)
ZERO SCALE (DATA = 000H)
VDD = +2.7V
ss = 135 UNITS
Figure 19. Long Term Drift
Accelerated by Burn-In
60
50
0
10
30
40
20
–1 0 1 2 3 4 5 6
TOTAL UNADJUSTED ERROR – mV
FREQUENCY
TUE = SINL+ZS+FS
ss = 300 UNITS
VDD = +3V
TA = +258C
Figure 13. Total Unadjusted
Error Histogram
1.5
1.0
–1.5
–55 –35 –15 5 25 45 65 85 105 125
0.5
0
–0.5
–1.0
VOUT DRIFT – mV
TEMPERATURE – 8C
VDD = +2.7V
VDD = +5.5V
NO LOAD
ss = 300 UNITS
NORMALIZED TO +258C
Figure 16. Full-Scale Voltage Drift
vs. Temperature
3.0
1.0
–60 –20 20 60 100 140
2.2
2.6
1.8
TEMPERATURE – 8C
IDD SUPPLY CURRENT – mA
DATA = FFFH
VIH = +2.4V
VIL = 0V
VDD = +5.5V
VDD = +5.0V
1.4
VDD = +4.5V
VDD = +2.7, 3.0, 3.3V
Figure 15. Supply Current vs.
Temperature
70
60
0
–50 –40 –20 –10 40
50
–30
40
30
20
10
0 10 20 30
TEMPERATURE COEFFICIENT – ppm/8C
FREQUENCY
VDD = +3V
DATA FFFH
TA = –40 TO +858C
Figure 18. Full-Scale Output
Tempco Histogram
REV. A
AD8300
–7–
Table I. Control Logic Truth Table
CS CLK CLR LD Serial Shift Register Function DAC Register Function
H X H H No Effect Latched
L L H H No Effect Latched
L H H H No Effect Latched
L H H Shift-Register-Data Advanced One Bit Latched
L H H No Effect Latched
H X H ¯ No Effect Updated with Current Shift Register Contents
H X H L No Effect Transparent
H X L X No Effect Loaded with All Zeros
H X H No Effect Latched All Zeros
NOTES
1. = Positive Logic Transition; ¯ = Negative Logic Transition; X = Don’t Care.
2. Do not clock in serial data while LD is LOW.
3. Data loads MSB first.
OPERATION
The AD8300 is a complete ready to use 12-bit digital-to-analog
converter. Only one +3 V power supply is necessary for operation.
It contains a 12-bit laser-trimmed digital-to-analog
converter, a curvature-corrected bandgap reference, rail-to-rail
output op amp, serial-input register, and DAC register. The
serial data interface consists of a serial-data-input (SDI) clock
(CLK), and load strobe pins (LD) with an active low CS strobe.
In addition an asynchronous CLR pin will set all DAC register
bits to zero causing the VOUT to become zero volts. This function
is useful for power on reset or system failure recovery to a
known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit device with an output that swings
from GND potential to 0.4 volt generated from the internal bandgap
voltage, see Figure 20. It uses a laser-trimmed segmented
R-2R ladder which is switched by N-channel MOSFETs. The
output voltage of the DAC has a constant resistance independent
of digital input code. The DAC output is internally connected
to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power consumption
precision amplifier. This low power amplifier contains
a differential PNP pair input stage that provides low offset voltage
and low noise, as well as the ability to amplify the zero-scale
DAC output voltages. The rail-to-rail amplifier is configured
with a gain of approximately five in order to set the 2.0475 volt
full-scale output (0.5 mV/LSB). See Figure 20 for an equivalent
circuit schematic of the analog section.
12-BIT DAC
R1 R2
VOUT
2.047V
FS
1.2V
0.4V
0.4V
FS
BANDGAP
REF
Figure 20. Equivalent AD8300 Schematic of Analog Portion
The op amp has a 2 ms typical settling time to 0.4% of full scale.
There are slight differences in settling time for negative slewing
signals versus positive. Also negative transition settling time to
within the last 6 LSB of zero volts has an extended settling time.
See the oscilloscope photos in the typical performances section
of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 21 shows an equivalent output schematic
of the rail-to-rail amplifier with its N-channel pull-down FETs
that will pull an output load directly to GND. The output
sourcing current is provided by a P-channel pull-up device that
can source current to GND terminated loads.
P-CH
N-CH
VDD
VOUT
AGND
Figure 21. Equivalent Analog Output Circuit
The rail-to-rail output stage achieves the minimum operating
supply voltage capability shown in Figure 2. The N-channel
output pull-down MOSFET shown in Figure 21 has a 35 W on
resistance which sets the sink current capability near ground. In
addition to resistive load driving capability, the amplifier has
also been carefully designed and characterized for up to 500 pF
capacitive load driving capability.
REFERENCE SECTION
The internal curvature-corrected bandgap voltage reference is
laser trimmed for both initial accuracy and low temperature
coefficient. Figure 18 provides a histogram of total output performance
of full-scale vs. temperature which is dominated by
the reference performance.
POWER SUPPLY
The very low power consumption of the AD8300 is a direct
result of a circuit design optimizing use of a CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors, good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8300 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CLK, CS, LD, and CLR pins. Since these
inputs are standard CMOS logic structures, they contribute
static power dissipation dependent on the actual driving logic
REV. A
AD8300
–8–
PRINTED IN U.S.A. C1968a–0–5/99
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
8 5
1 4
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
88
08
0.0196 (0.50)
0.0099 (0.25) 3 458
8-Lead Plastic DIP (N-8)
SEATING
PLANE
0.015
(0.381)
0.210 TYP
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
1 4
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
158
08
VOH and VOL voltage levels. Consequently, for optimum dissipation
use of CMOS logic versus TTL provides minimal dissipation
in the static state. A VINL = 0 V on the logic input pins
provides the lowest standby dissipation of 1.2 mA with a +3.3 V
power supply.
As with any analog system, it is recommended that the AD8300
power supply be bypassed on the same PC card that contains
the chip. Figure 8 shows the power supply rejection versus frequency
performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8300 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+2.7 V to +5.5 V. If reduced linearity and source current capability
near full scale can be tolerated, operation of the AD8300
is possible down to +2.1 volts. The minimum operating supply
voltage versus load current plot in Figure 2 provides information
for operation below VDD = +2.7 V.
TIMING AND CONTROL
The AD8300 has a separate serial-input register from the 12-bit
DAC register that allows preloading of a new data value MSB
first into the serial register without disturbing the present DAC
output voltage value. Data can only be loaded when the CS pin
is active low. After the new value is fully loaded in the serialinput
register, it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any new
data is loaded into the serial-input register. At any time the
contents of the DAC resister can be reset to zero by strobing the
CLR pin which causes the DAC output voltage to go to zero
volts. All of the timing requirements are detailed in Figure 3
along with Table I. Control Logic Truth Table.
All digital inputs are protected with a Zener type ESD protection
structure (Figure 22) that allows logic input voltages to exceed
the VDD supply voltage. This feature can be useful if the user is
loading one or more of the digital inputs with a 5 V CMOS logic
input voltage level while operating the AD8300 on a +3.3 V
power supply. If this mode of interface is used, make sure that
the VOL of the +5 V CMOS meets the VIL input requirement of
the AD8300 operating at 3 V. See Figure 5 for the effect on
digital logic input threshold versus operating VDD supply voltage.
VDD
LOGIC
IN
GND
Figure 22. Equivalent Digital Input ESD Protection
Unipolar Output Operation
This is the basic mode of operation for the AD8300. The
AD8300 has been designed to drive loads as low as 400 W in
parallel with 500 pF. The code table for this operation is shown
in Table II.
APPLICATIONS INFORMATION
See DAC8512 data sheet for additional application circuit ideas.
Table II. Unipolar Code Table
Hexadecimal Decimal
Number in Number in Analog Output
DAC Register DAC Register Voltage (V)
FFF 4095 +2.0475
801 2049 +1.0245
800 2048 +1.0240
7FF 2047 +1.0235
000 0 +0.0000
DATA
RDS 80
Microprocessor-Controlled Digital 80 Watt Soldering Station
The digital soldering station ERSA RDS 80, offers the established and proven ERSA Res istr onic heating technology with a generous 80 watts of power.
With this unique temperature control technology, the ceramic PTC heating element (Positive Temperature Coefficient) replaces the function of the thermocouple. This guarantees very fast preheating due to high initial power and fast heat recovery for a stable soldering process.
The very high heating power and the largest range of soldering tips allow for great flexibility in handling all applications.
The heating system with interior heated soldering tips has the highest thermal efficiency. The newly constructed ergonomic handle, the new design of the housing, and the big digital multi-function display leave nothing to be desired!
Precise temperatures can be selected between 150°C and 450°C (302°F - 842°F), and with a touch of a button, 3 fixed temperatures or 2 fixed temperatures and one stand-by temperature can be programmed and selected.
I
n addition, the station offers a power bar graph display, a calibration capability, and an automatic power-off function. Finally, the potential equalization jack (with integraded 220 kΩ resistor) allows the system to be grounded to the desired resistance of the working environment.
Power, Precision, Comfort and Safety-
the ERSA RDS 80 offers the best Bang for your Buck!
The digital power soldering station with microprocessor
control and fantastic price/performance ratio !
Fig.: Microprocessor-controlled digital power soldering station
Fig.: Microprocessor-controlled digital power soldering station
ERSA product range
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desoldering stations
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I
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DATA
RDS 80
49263-0507 • subject to changes • © by ERSA
Microprocessor-Controlled Digital 80 Watt Soldering Station
832 BD
832 YD
832 CD
832 ED
832 VD
832 GD
832 LD
832 MD
842 BD
842 YD
842 CD
842 ED
Technical data:
Electronic station RDS 803
Supply voltage: 230 V / 50 Hz
Secondary voltage: 24 V ~
Power: 80 VA
C
ontrol technology: Res istr onic
temperature regulation
Temperature range: 150°C - 459°C
302°F - 842°F
Temperature accuracy: 0°C after
calibration
Display resolution: 1°C / 1°F
C
able: 2 m PVC
Fuse: 0.63 A delayed action
Station dimensions: 110 x 105 x 147 mm
(W x H x D)
Permissible ambient
temperature: 0 - 40°C / 32 - 104°F
Weight: approx. 2 kg
Soldering iron RT 80 with soldering tip 842 CD
Voltage: 24 V ~
Power: 80 W at 350°C
(662°F)
Preheating power: 290 W
Preheating time: approx. 40 s
(to 280°C / 536°F)
C
able: 1.5 m PVC,
Weight: approx. 130 g
Holder RH 80
Weight: approx. 400 g
Fig.: Soldering iron RT 80 with optional soldering tips
Excerpt of
832/842 soldering tip series
actual size
Europe (Headquarters):
ERSA GmbH
Leonhard-Karl-Str. 24
97877 Wertheim / Germany
Phone: +49 (0) 9342 / 800-0
Fax: +49 (0) 9342 / 800-127
e-mail: info@ersa.de
www.ersa.com
General Description
The DS3231 is a low-cost, extremely accurate I2C realtime
clock (RTC) with an integrated temperaturecompensated
crystal oscillator (TCXO) and crystal. The
device incorporates a battery input, and maintains accurate
timekeeping when main power to the device is interrupted.
The integration of the crystal resonator enhances
the long-term accuracy of the device as well as reduces
the piece-part count in a manufacturing line. The DS3231
is available in commercial and industrial temperature
ranges, and is offered in a 16-pin, 300-mil SO package.
The RTC maintains seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. Two programmable time-ofday
alarms and a programmable square-wave output
are provided. Address and data are transferred serially
through an I2C bidirectional bus.
A precision temperature-compensated voltage reference
and comparator circuit monitors the status of VCC
to detect power failures, to provide a reset output, and
to automatically switch to the backup supply when necessary.
Additionally, the RST pin is monitored as a
pushbutton input for generating a reset externally.
Applications
Servers Utility Power Meters
Telematics GPS
Features
♦ Accuracy ±2ppm from 0°C to +40°C
♦ Accuracy ±3.5ppm from -40°C to +85°C
♦ Battery Backup Input for Continuous
Timekeeping
♦ Operating Temperature Ranges
Commercial: 0°C to +70°C
Industrial: -40°C to +85°C
♦ Low-Power Consumption
♦ Real-Time Clock Counts Seconds, Minutes,
Hours, Day, Date, Month, and Year with Leap Year
Compensation Valid Up to 2100
♦ Two Time-of-Day Alarms
♦ Programmable Square-Wave Output
♦ Fast (400kHz) I2C Interface
♦ 3.3V Operation
♦ Digital Temp Sensor Output: ±3°C Accuracy
♦ Register for Aging Trim
♦ RST Output/Pushbutton Reset Debounce Input
♦ Underwriters Laboratories (UL) Recognized
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
______________________________________________ Maxim Integrated Products 1
Rev 5; 4/08
Ordering Information
PART TEMP RANGE PIN-PACKAGE
TOP
MARK
DS3231S 0°C to +70°C 16 SO DS3231
DS3231SN -40°C to +85°C 16 SO DS3231N
DS3231S# 0°C to +70°C 16 SO DS3231S
DS3231SN# -40°C to +85°C 16 SO DS3231SN
Pin Configuration appears at end of data sheet.
DS3231
VCC
SCL
RPU
RPU = tR/CB
RPU
INT/SQW
32kHz
VBAT
PUSHBUTTON
RESET
SDA
RST
N.C.
N.C.
N.C.
N.C.
VCC
VCC
GND
VCC
CPU
N.C.
N.C.
N.C.
N.C.
Typical Operating Circuit
# Denotes a RoHS-compliant device that may include lead that
is exempt under RoHS requirements. The lead finish is JESD97
category e3, and is compatible with both lead-based and leadfree
soldering processes. A "#" anywhere on the top mark
denotes a RoHS-compliant device.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
2 _____________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST,
INT/SQW Relative to Ground.............................-0.3V to +6.0V
Operating Temperature Range
(noncondensing) .............................................-40°C to +85°C
Junction Temperature......................................................+125°C
Storage Temperature Range ...............................-40°C to +85°C
Lead Temperature
(Soldering, 10s).....................................................+260°C/10s
Soldering Temperature....................................See the Handling,
PC Board Layout, and Assembly section.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC 2.3 3.3 5.5 V
Supply Voltage
VBAT 2.3 3.0 5.5 V
Logic 1 Input SDA, SCL VIH
0.7 x
VCC
VCC +
0.3
V
Logic 0 Input SDA, SCL VIL -0.3
+0.3 x
VCC
V
Pullup Voltage
(SDA, SCL, 32kHz, INT/SQW)
VPU VCC = 0V 5.5V V
ELECTRICAL CHARACTERISTICS
(VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC = 3.63V 200
Active Supply Current ICCA (Notes 3, 4)
VCC = 5.5V 300
μA
VCC = 3.63V 110
Standby Supply Current ICCS
I2C bus inactive, 32kHz
output on, SQW output off
(Note 4) VCC = 5.5V 170
μA
VCC = 3.63V 575
Temperature Conversion Current ICCSCONV
I2C bus inactive, 32kHz
output on, SQW output off VCC = 5.5V 650
μA
Power-Fail Voltage VPF 2.45 2.575 2.70 V
Logic 0 Output, 32kHz,
INT/SQW, SDA
VOL IOL = 3mA 0.4 V
Logic 0 Output, RST VOL IOL = 1mA 0.4 V
Output Leakage Current 32kHz,
INT/SQW, SDA
ILO Output high impedance -1 0 +1 μA
Input Leakage SCL ILI -1 +1 μA
RST Pin I/O Leakage IOL RST high impedance (Note 5) -200 +10 μA
VBAT Leakage Current
(VCC Active)
IBATLKG 25 100 nA
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
_____________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.3V to 5.5V, VCC = Active Supply (see Table 1), TA = TMIN to TMAX, unless otherwise noted.) (Typical values are at VCC =
3.3V, VBAT = 3.0V, and TA = +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency fOUT VCC = 3.3V or VBAT = 3.3V 32.768 kHz
Frequency Stability vs. 0°C to +40°C ±2
Temperature (Commercial) f/fOUT
VCC = 3.3V or
VBAT = 3.3V,
aging offset = 00h >40°C to +70°C ±3.5
ppm
-40°C to <0°C ±3.5
0°C to +40°C ±2
Frequency Stability vs.
Temperature (Industrial)
f/fOUT
VCC = 3.3V or
VBAT = 3.3V,
aging offset = 00h >40°C to +85°C ±3.5
ppm
Frequency Stability vs. Voltage f/V 1 ppm/V
-40°C 0.7
+25°C 0.1
+70°C 0.4
Trim Register Frequency
Sensitivity per LSB
f/LSB Specified at:
+85°C 0.8
ppm
Temperature Accuracy Temp VCC = 3.3V or VBAT = 3.3V -3 +3 °C
First year ±1.0
Crystal Aging f/fO
After reflow,
not production tested 0–10 years ±5.0
ppm
ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBAT = 2.3V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VBAT = 3.63V 70
Active Battery Current IBATA
EOSC = 0, BBSQW = 0,
SCL = 400kHz (Note 4) VBAT = 5.5V 150
μA
VBAT = 3.63V 0.84 3.0
Timekeeping Battery Current IBATT
EOSC = 0, BBSQW = 0,
EN32kHz = 1,
SCL = SDA = 0V or
SCL = SDA = VBAT (Note 4) VBAT = 5.5V 1.0 3.5
μA
VBAT = 3.63V 575
Temperature Conversion Current IBATTC
EOSC = 0, BBSQW = 0,
SCL = SDA = 0V or
SCL = SDA = VBAT VBAT = 5.5V 650
μA
Data-Retention Current IBATTDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
4 _____________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX) or VBAT = VBAT(MIN) to VBAT(MAX), VBAT > VCC, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Fast mode 100 400
SCL Clock Frequency fSCL
Standard mode 0 100
kHz
Bus Free Time Between STOP Fast mode 1.3
and START Conditions
tBUF
Standard mode 4.7
μs
Hold Time (Repeated) START Fast mode 0.6
Condition (Note 6)
tHD:STA
Standard mode 4.0
μs
Fast mode 1.3
Low Period of SCL Clock tLOW
Standard mode 4.7
μs
Fast mode 0.6
High Period of SCL Clock tHIGH
Standard mode 4.0
μs
Fast mode 0 0.9
Data Hold Time (Notes 7, 8) tHD:DAT
Standard mode 0 0.9
μs
Fast mode 100
Data Setup Time (Note 9) tSU:DAT
Standard mode 250
ns
Fast mode 0.6
START Setup Time tSU:STA
Standard mode 4.7
μs
Rise Time of Both SDA and SCL Fast mode 300
Signals (Note 10)
tR
Standard mode
20 +
0.1CB 1000
ns
Fall Time of Both SDA and SCL Fast mode 300
Signals (Note 10)
tF
Standard mode
20 +
0.1CB 300
ns
Fast mode 0.6
Setup Time for STOP Condition tSU:STO
Standard mode 4.7
μs
Capacitive Load for Each Bus
Line (Note 10)
CB 400 pF
Capacitance for SDA, SCL CI/O 10 pF
Pulse Width of Spikes That Must
Be Suppressed by the Input Filter
tSP 30 ns
Pushbutton Debounce PBDB 250 ms
Reset Active Time tRST 250 ms
Oscillator Stop Flag (OSF) Delay tOSF (Note 11) 100 ms
Temperature Conversion Time tCONV 125 200 ms
POWER-SWITCH CHARACTERISTICS
(TA = TMIN to TMAX)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Fall Time; VPF(MAX) to
VPF(MIN)
tVCCF 300 μs
VCC Rise Time; VPF(MIN) to
VPF(MAX)
tVCCR 0 μs
Recovery at Power-Up tREC (Note 12) 250 300 ms
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
_____________________________________________________________________ 5
Pushbutton Reset Timing
PBDB tRST
RST
Power-Switch Timing
VCC
tVCCF tVCCR
tREC
VPF(MAX)
VPF VPF
VPF(MIN)
RST
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
6 _____________________________________________________________________
Data Transfer on I2C Serial Bus
SDA
SCL
tHD:STA
tLOW
tHIGH
tR tF
tBUF
tHD:DAT
tSU:DAT REPEATED
START
tSU:STA
tHD:STA
tSU:STO
tSP
STOP START
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: ICCA—SCL clocking at max frequency = 400kHz.
Note 4: Current is the averaged input current, which includes the temperature conversion current.
Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC.
Note 6: After this period, the first clock pulse is generated.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 8: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This
is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the
low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 10: CB—total capacitance of one bus line in pF.
Note 11: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of
0.0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V.
Note 12: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, tREC is bypassed and RST immediately
goes high. The state of RST does not affect the I2C interface, RTC, or TCXO.
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
_____________________________________________________________________ 7
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DS3231 toc01
VCC (V)
ICCS (μA)
2.5 3.0 3.5 4.0 4.5 5.0
25
50
75
100
125
150
0
2.0 5.5
RST ACTIVE
BSY = 0, SCL = SDA = VCC
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DS3231 toc02
VBAT (V)
IBAT (μA)
3.3 4.3 5.3
0.7
0.8
0.9
1.0
1.1
1.2
0.6
2.3
VCC = 0V, BSY = 0,
SDA = SCL = VBAT OR VCC
EN32kHz = 1
EN32kHz = 0
SUPPLY CURRENT
vs. TEMPERATURE
DS3231 toc03
TEMPERATURE (°C)
IBAT (μA)
-15 10 35 60
0.7
0.8
0.9
1.0
0.6
-40 85
VCC = 0, EN32kHz = 1, BSY = 0,
SDA = SCL = VBAT OR GND
FREQUENCY DEVIATION
vs. TEMPERATURE vs. AGING VALUE
DS3231 toc04
TEMPERATURE (°C)
FREQUENCY DEVIATION (ppm)
-15 10 35 60
-30
-20
-10
0
10
20
30
40
50
60
-40
-40 85
127
32
0
-33
8
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
8 _____________________________________________________________________
Block Diagram
N
N
N
RST
VCC
32kHz
INT/SQW
CLOCK AND CALENDAR
REGISTERS
USER BUFFER
(7 BYTES)
I2C INTERFACE AND
ADDRESS REGISTER
DECODE
POWER CONTROL
VCC
VBAT
GND
SCL
SDA
TEMPERATURE
SENSOR
CONTROL LOGIC/
DIVIDER
PUSHBUTTON RESET;
SQUARE-WAVE BUFFER;
INT/SQW CONTROL
CONTROL AND STATUS
REGISTERS
OSCILLATOR AND
CAPACITOR ARRAY
X1
X2
DS3231
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
_____________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 32kHz
32kHz Output. This open-drain pin requires an external pullup resistor. When enabled, the output operates
on either power supply. It may be left open if not used.
2 VCC
DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1μF to 1.0μF capacitor.
If not used, connect to ground.
3 INT/SQW
Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor
connected to a supply at 5.5V or less. It may be left open if not used. This multifunction pin is determined
by the state of the INTCN bit in the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a
square wave and its frequency is determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a
match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the
alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an
interrupt output with alarms disabled.
4 RST
Active-Low Reset. This pin is an open-drain input/output. It indicates the status of VCC relative to the
VPF specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the RST
pin is pulled high by the internal pullup resistor. The active-low, open-drain output is combined with a
debounced pushbutton input function. This pin can be activated by a pushbutton reset request. It has an
internal 50k nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the
oscillator is disabled, tREC is bypassed and RST immediately goes high.
5–12 N.C. No Connection. Must be connected to ground.
13 GND Ground
14 VBAT
Backup Power-Supply Input. This pin should be decoupled using a 0.1μF to 1.0μF low-leakage capacitor.
If the I2C interface is inactive whenever the device is powered by the VBAT input, the decoupling capacitor
is not required. If VBAT is not used, connect to ground. UL recognized to ensure against reverse charging
when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul.
15 SDA
Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin
requires an external pullup resistor.
16 SCL
Serial Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data
movement on the serial interface.
Detailed Description
The DS3231 is a serial RTC driven by a temperaturecompensated
32kHz crystal oscillator. The TCXO provides
a stable and accurate reference clock, and
maintains the RTC to within ±2 minutes per year accuracy
from -40°C to +85°C. The TCXO frequency output
is available at the 32kHz pin. The RTC is a low-power
clock/calendar with two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW provides either an interrupt signal due to
alarm conditions or a square-wave output. The clock/calendar
provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. The
clock operates in either the 24-hour or 12-hour format
with an AM/PM indicator. The internal registers are
accessible though an I2C bus interface.
A temperature-compensated voltage reference and
comparator circuit monitors the level of VCC to detect
power failures and to automatically switch to the backup
supply when necessary. The RST pin provides an
external pushbutton function and acts as an indicator
of a power-fail event.
DS3231
Operation
The block diagram shows the main elements of the
DS3231. The eight blocks can be grouped into four
functional groups: TCXO, power control, pushbutton
function, and RTC. Their operations are described separately
in the following sections.
32kHz TCXO
The temperature sensor, oscillator, and control logic
form the TCXO. The controller reads the output of the
on-chip temperature sensor and uses a lookup table to
determine the capacitance required, adds the aging
correction in AGE register, and then sets the capacitance
selection registers. New values, including
changes to the AGE register, are loaded only when a
change in the temperature value occurs, or when a
user-initiated temperature conversion is completed.
The temperature is read on initial application of VCC
and once every 64 seconds afterwards.
Power Control
This function is provided by a temperature-compensated
voltage reference and a comparator circuit that
monitors the VCC level. When VCC is greater than VPF,
the part is powered by VCC. When VCC is less than VPF
but greater than VBAT, the DS3231 is powered by VCC.
If VCC is less than VPF and is less than VBAT, the
device is powered by VBAT. See Table 1.
To preserve the battery, the first time VBAT is applied to
the device, the oscillator will not start up until VCC
exceeds VPF, or until a valid I2C address is written to
the part. Typical oscillator startup time is less than one
second. Approximately 2 seconds after VCC is applied,
or a valid I2C address is written, the device makes a
temperature measurement and applies the calculated
correction to the oscillator. Once the oscillator is running,
it continues to run as long as a valid power
source is available (VCC or VBAT), and the device continues
to measure the temperature and correct the
oscillator frequency every 64 seconds.
On the first application of power (VCC) or when a valid
I2C address is written to the part (VBAT), the time and
date registers are reset to 01/01/00 01 00:00:00
(MM/DD/YY DOW HH:MM:SS).
Pushbutton Reset Function
The DS3231 provides for a pushbutton switch to be connected
to the RST output pin. When the DS3231 is not in
a reset cycle, it continuously monitors the RST signal for
a low going edge. If an edge transition is detected, the
DS3231 debounces the switch by pulling the RST low.
After the internal timer has expired (PBDB), the DS3231
continues to monitor the RST line. If the line is still low,
the DS3231 continuously monitors the line looking for a
rising edge. Upon detecting release, the DS3231 forces
the RST pin low and holds it low for tRST.
RST is also used to indicate a power-fail condition.
When VCC is lower than VPF, an internal power-fail signal
is generated, which forces the RST pin low. When
VCC returns to a level above VPF, the RST pin is held
low for approximately 250ms (tREC) to allow the power
supply to stabilize. If the oscillator is not running (see
the Power Control section) when VCC is applied, tREC is
bypassed and RST immediately goes high. The state of
RST does not affect the operation of the TCXO, I2C
interface, or RTC functions.
Real-Time Clock
With the clock source from the TCXO, the RTC provides
seconds, minutes, hours, day, date, month, and year
information. The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in either
the 24-hour or 12-hour format with an AM/PM indicator.
The clock provides two programmable time-of-day
alarms and a programmable square-wave output. The
INT/SQW pin either generates an interrupt due to alarm
condition or outputs a square-wave signal and the
selection is controlled by the bit INTCN.
Address Map
Figure 1 shows the address map for the DS3231 timekeeping
registers. During a multibyte access, when the
address pointer reaches the end of the register space
(12h), it wraps around to location 00h. On an I2C
START or address pointer incrementing to location 00h,
the current time is transferred to a second set of registers.
The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
I2C Interface
The I2C interface is accessible whenever either VCC or
VBAT is at a valid level. If a microcontroller connected to
the DS3231 resets because of a loss of VCC or other
event, it is possible that the microcontroller and DS3231
I2C communications could become unsynchronized,
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
10 ____________________________________________________________________
SUPPLY CONDITION ACTIVE SUPPLY
VCC < VPF, VCC < VBAT VBAT
VCC < VPF, VCC > VBAT VCC
VCC > VPF, VCC < VBAT VCC
VCC > VPF, VCC > VBAT VCC
Table 1. Power Control
e.g., the microcontroller resets while reading data from
the DS3231. When the microcontroller resets, the
DS3231 I2C interface may be placed into a known state
by toggling SCL until SDA is observed to be at a high
level. At that point the microcontroller should pull SDA
low while SCL is high, generating a START condition.
Clock and Calendar
The time and calendar information is obtained by reading
the appropriate register bytes. Figure 1 illustrates the
RTC registers. The time and calendar data are set or initialized
by writing the appropriate register bytes. The contents
of the time and calendar registers are in the
binary-coded decimal (BCD) format. The DS3231 can be
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode select bit.
When high, the 12-hour mode is selected. In the 12-hour
mode, bit 5 is the AM/PM bit with logic-high being PM. In
the 24-hour mode, bit 5 is the second 10-hour bit (20–23
hours). The century bit (bit 7 of the month register) is toggled
when the years register overflows from 99 to 00.
The day-of-week register increments at midnight.
Values that correspond to the day of week are userdefined
but must be sequential (i.e., if 1 equals
Sunday, then 2 equals Monday, and so on). Illogical
time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary
(user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any START and when the register
pointer rolls over to zero. The time information is read
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
____________________________________________________________________ 11
Figure 1. Timekeeing Registers
Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.
ADDRESS
BIT 7
MSB
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
BIT 0
LSB
FUNCTION RANGE
00h 0 10 Seconds Seconds Seconds 00–59
01h 0 10 Minutes Minutes Minutes 00–59
AM/PM
02h 0 12/24
10 Hour
10 Hour Hour Hours
1–12 + AM/PM
00–23
03h 0 0 0 0 0 Day Day 1–7
04h 0 0 10 Date Date Date 01–31
05h Century 0 0 10 Month Month
Month/
Century
01–12 +
Century
06h 10 Year Year Year 00–99
07h A1M1 10 Seconds Seconds Alarm 1 Seconds 00–59
08h A1M2 10 Minutes Minutes Alarm 1 Minutes 00–59
AM/PM
09h A1M3 12/24
10 Hour
10 Hour Hour Alarm 1 Hours
1–12 + AM/PM
00–23
Day Alarm 1 Day 1–7
0Ah A1M4 DY/DT 10 Date
Date Alarm 1 Date 1–31
0Bh A2M2 10 Minutes Minutes Alarm 2 Minutes 00–59
AM/PM
0Ch A2M3 12/24
10 Hour
10 Hour Hour Alarm 2 Hours
1–12 + AM/PM
00–23
Day Alarm 2 Day 1–7
0Dh A2M4 DY/DT 10 Date
Date Alarm 2 Date 1–31
0Eh EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE Control —
0Fh OSF 0 0 0 EN32kHz BSY A2F A1F Control/Status —
10h SIGN DATA DATA DATA DATA DATA DATA DATA Aging Offset —
11h SIGN DATA DATA DATA DATA DATA DATA DATA MSB of Temp —
12h DATA DATA 0 0 0 0 0 0 LSB of Temp —
DS3231
from these secondary registers, while the clock continues
to run. This eliminates the need to reread the registers
in case the main registers update during a read.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowledge
from the DS3231. Once the countdown chain is
reset, to avoid rollover issues the remaining time and
date registers must be written within 1 second. The 1Hz
square-wave output, if enabled, transitions high 500ms
after the seconds data transfer, provided the oscillator
is already running.
Alarms
The DS3231 contains two time-of-day/date alarms.
Alarm 1 can be set by writing to registers 07h to 0Ah.
Alarm 2 can be set by writing to registers 0Bh to 0Dh.
The alarms can be programmed (by the alarm enable
and INTCN bits of the control register) to activate the
INT/SQW output on an alarm match condition. Bit 7 of
each of the time-of-day/date alarm registers are mask
bits (Table 2). When all the mask bits for each alarm
are logic 0, an alarm only occurs when the values in the
timekeeping registers match the corresponding values
stored in the time-of-day/date alarm registers. The
alarms can also be programmed to repeat every second,
minute, hour, day, or date. Table 2 shows the possible
settings. Configurations not listed in the table will
result in illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to logic 0, the alarm will
be the result of a match with date of the month. If
DY/DT is written to logic 1, the alarm will be the result of
a match with day of the week.
When the RTC register values match alarm register settings,
the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt
Enable ‘A1IE’ or ‘A2IE’ is also set to logic 1 and the
INTCN bit is set to logic 1, the alarm condition will activate
the INT/SQW signal. The match is tested on the
once-per-second update of the time and date registers.
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
12 ____________________________________________________________________
Table 2. Alarm Mask Bits
ALARM 1 REGISTER MASK BITS (BIT 7)
DY/DT
A1M4 A1M3 A1M2 A1M1
ALARM RATE
X 1 1 1 1 Alarm once per second
X 1 1 1 0 Alarm when seconds match
X 1 1 0 0 Alarm when minutes and seconds match
X 1 0 0 0 Alarm when hours, minutes, and seconds match
0 0 0 0 0 Alarm when date, hours, minutes, and seconds match
1 0 0 0 0 Alarm when day, hours, minutes, and seconds match
ALARM 2 REGISTER MASK BITS (BIT 7)
DY/DT
A2M4 A2M3 A2M2
ALARM RATE
X 1 1 1 Alarm once per minute (00 seconds of every minute)
X 1 1 0 Alarm when minutes match
X 1 0 0 Alarm when hours and minutes match
0 0 0 0 Alarm when date, hours, and minutes match
1 0 0 0 Alarm when day, hours, and minutes match
Special-Purpose Registers
The DS3231 has two additional registers (control and
status) that control the real-time clock, alarms, and
square-wave output.
Control Register (0Eh)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscillator
is stopped when the DS3231 switches to VBAT. This
bit is clear (logic 0) when power is first applied. When
the DS3231 is powered by VCC, the oscillator is always
on regardless of the status of the EOSC bit.
Bit 6: Battery-Backed Square-Wave Enable
(BBSQW). When set to logic 1 and the DS3231 is being
powered by the VBAT pin, this bit enables the squarewave
or interrupt output when VCC is absent. When
BBSQW is logic 0, the INT/SQW pin goes high impedance
when VCC falls below the power-fail trip point. This
bit is disabled (logic 0) when power is first applied.
Bit 5: Convert Temperature (CONV). Setting this bit to
1 forces the temperature sensor to convert the temperature
into digital code and execute the TCXO algorithm
to update the capacitance array to the oscillator. This
can only happen when a conversion is not already in
progress. The user should check the status bit BSY
before forcing the controller to start a new TCXO execution.
A user-initiated temperature conversion does
not affect the internal 64-second update cycle.
A user-initiated temperature conversion does not affect
the BSY bit for approximately 2ms. The CONV bit
remains at a 1 from the time it is written until the conversion
is finished, at which time both CONV and BSY go
to 0. The CONV bit should be used when monitoring
the status of a user-initiated conversion.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits
control the frequency of the square-wave output when
the square wave has been enabled. The following table
shows the square-wave frequencies that can be selected
with the RS bits. These bits are both set to logic 1
(8.192kHz) when power is first applied.
Bit 2: Interrupt Control (INTCN). This bit controls the
INT/SQW signal. When the INTCN bit is set to logic 0, a
square wave is output on the INT/SQW pin. When the
INTCN bit is set to logic 1, then a match between the
timekeeping registers and either of the alarm registers
activates the INT/SQW output (if the alarm is also
enabled). The corresponding alarm flag is always set
regardless of the state of the INTCN bit. The INTCN bit
is set to logic 1 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert INT/SQW (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the INT/SQW signal.
The A1IE bit is disabled (logic 0) when power is
first applied.
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
____________________________________________________________________ 13
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE
RS2 RS1
SQUARE-WAVE OUTPUT
FREQUENCY
0 0 1Hz
0 1 1.024kHz
1 0 4.096kHz
1 1 8.192kHz
SQUARE-WAVE OUTPUT FREQUENCY
Control Register (0Eh)
DS3231
Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator either is stopped or was
stopped for some period and may be used to judge the
validity of the timekeeping data. This bit is set to logic 1
any time that the oscillator stops. The following are
examples of conditions that can cause the OSF bit to
be set:
1) The first time power is applied.
2) The voltages present on both VCC and VBAT are
insufficient to support oscillation.
3) The EOSC bit is turned off in battery-backed mode.
4) External influences on the crystal (i.e., noise, leakage,
etc.).
This bit remains at logic 1 until written to logic 0.
Bit 3: Enable 32kHz Output (EN32kHz). This bit controls
the status of the 32kHz pin. When set to logic 1,
the 32kHz pin is enabled and outputs a 32.768kHz
square-wave signal. When set to logic 0, the 32kHz pin
goes to a high-impedance state. The initial power-up
state of this bit is logic 1, and a 32.768kHz square-wave
signal appears at the 32kHz pin after a power source is
applied to the DS3231 (if the oscillator is running).
Bit 2: Busy (BSY). This bit indicates the device is busy
executing TCXO functions. It goes to logic 1 when the
conversion signal to the temperature sensor is asserted
and then is cleared when the device is in the 1-minute
idle state.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 registers.
If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 registers.
If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the INT/SQW pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Aging Offset
The crystal aging offset register provides an 8-bit code
to add to the codes in the capacitance array registers.
The code is encoded in two’s complement. One LSB
represents one small capacitor to be switched in or out
of the capacitance array at the crystal pins. The offset
register is added to the capacitance array register
under the following conditions: during a normal temperature
conversion, if the temperature changes from the
previous conversion, or during a manual user conversion
(setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immediately,
a manual conversion should be started after each
aging register change.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
The change in ppm per LSB is different at different temperatures.
The frequency vs. temperature curve is shifted
by the values used in this register. At +25°C, one LSB
typically provides about 0.1ppm change in frequency.
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
14 ____________________________________________________________________
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Sign Data Data Data Data Data Data Data
Aging Offset (10h)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OSF 0 0 0 EN32kHz BSY A2F A1F
Status Register (0Fh)
Temperature Registers (11h–12h)
Temperature is represented as a 10-bit code with a resolution
of +0.25°C and is accessible at location 11h
and 12h. The temperature is encoded in two’s complement
format. The upper 8 bits are at location 11h and
the lower 2 bits are in the upper nibble at location 12h.
Upon power reset, the registers are set to a default
temperature of 0°C and the controller starts a temperature
conversion. New temperature readings are stored
in this register.
I2C Serial Data Bus
The DS3231 supports a bidirectional I2C bus and data
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiving
data is defined as a receiver. The device that controls
the message is called a master. The devices that
are controlled by the master are slaves. The bus must
be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions. The DS3231
operates as a slave on the I2C bus. Connections to the
bus are made through the SCL input and open-drain
SDA I/O lines. Within the bus specifications, a standard
mode (100kHz maximum clock rate) and a fast mode
(400kHz maximum clock rate) are defined. The DS3231
works in both modes.
The following bus protocol has been defined (Figure 2):
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
START data transfer: A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
STOP data transfer: A change in the state of the
data line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associated
with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
____________________________________________________________________ 15
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Sign Data Data Data Data Data Data Data
Temperature Register (Upper Byte) (11h)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Data Data 0 0 0 0 0 0
Temperature Register (Lower Byte) (12h)
DS3231
Figures 3 and 4 detail how data transfer is accomplished
on the I2C bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data is transferred with the most
significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted
by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock pulses
and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated
START condition. Since a repeated START condition
is also the beginning of the next serial transfer, the
bus will not be released. Data is transferred with the
most significant bit (MSB) first.
The DS3231 can operate in the following two modes:
Slave receiver mode (DS3231 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are recognized
as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit. The
slave address byte is the first byte received after the
master generates the START condition. The slave
address byte contains the 7-bit DS3231 address,
which is 1101000, followed by the direction bit (R/W),
which is 0 for a write. After receiving and decoding
the slave address byte, the DS3231 outputs an
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
16 ____________________________________________________________________
STOP
CONDITION
OR REPEATED
START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERED
ACK
START
CONDITION
ACK
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SLAVE ADDRESS
MSB
SCL
SDA
R/W
DIRECTION
BIT
1 2 6 7 8 9 1 2 3–7 8 9
Figure 2. I2C Data Transfer Overview
S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S = START
A = ACKNOWLEDGE
P = STOP
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D0h
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
Figure 3. Slave Receiver Mode (Write Mode)
S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = D1h
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY
A NOT ACKNOWLEDGE (A) SIGNAL
Figure 4. Slave Transmitter Mode (Read Mode)
acknowledge on SDA. After the DS3231 acknowledges
the slave address + write bit, the master
transmits a word address to the DS3231. This sets
the register pointer on the DS3231, with the DS3231
acknowledging the transfer. The master may then
transmit zero or more bytes of data, with the DS3231
acknowledging each byte received. The register
pointer increments after each data byte is transferred.
The master generates a STOP condition to
terminate the data write.
Slave transmitter mode (DS3231 read mode): The
first byte is received and handled as in the slave
receiver mode. However, in this mode, the direction
bit indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the DS3231
while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is
performed by hardware after reception of the slave
address and direction bit. The slave address byte is
the first byte received after the master generates a
START condition. The slave address byte contains
the 7-bit DS3231 address, which is 1101000, followed
by the direction bit (R/W), which is 1 for a
read. After receiving and decoding the slave
address byte, the DS3231 outputs an acknowledge
on SDA. The DS3231 then begins to transmit data
starting with the register address pointed to by the
register pointer. If the register pointer is not written to
before the initiation of a read mode, the first address
that is read is the last one stored in the register pointer.
The DS3231 must receive a not acknowledge to
end a read.
Handling, PC Board Layout,
and Assembly
The DS3231 package contains a quartz tuning-fork
crystal. Pick-and-place equipment can be used, but
precautions should be taken to ensure that excessive
shocks are avoided. Ultrasonic cleaning should be
avoided to prevent damage to the crystal.
Avoid running signal traces under the package, unless
a ground plane is placed between the package and the
signal line. All N.C. (no connect) pins must be connected
to ground.
Moisture-sensitive packages are shipped from the factory
dry packed. Handling instructions listed on the
package label must be followed to prevent damage
during reflow. Refer to the IPC/JEDEC J-STD-020 standard
for moisture-sensitive device (MSD) classifications
and reflow profiles. Exposure to reflow is limited to 2
times maximum.
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
____________________________________________________________________ 17
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
18 ____________________________________________________________________
Chip Information
TRANSISTOR COUNT: 33,000
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Thermal Information
Theta-JA: +73°C/W
Theta-JC: +23°C/W
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
32kHz SCL
SDA
VBAT
GND
N.C.
N.C.
N.C.
N.C.
TOP VIEW
SO
VCC
INT/SQW
N.C.
RST
N.C.
N.C.
N.C.
DS3231S
Pin Configuration
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 SO — 56-G4009-001
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
DS3231
Extremely Accurate I2C-Integrated
RTC/TCXO/Crystal
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0 1/05 Initial release. —
Changed Digital Temp Sensor Output from ±2°C to ±3°C. 1, 3
Updated Typical Operating Circuit. 1
Changed TA = -40°C to +85°C to TA = TMIN to TMAX. 2, 3, 4
1 2/05
Updated Block Diagram. 8
Added “UL Recognized” to Features; added lead-free packages and removed S
from top mark info in Ordering Information table; added ground connections to
the N.C. pin in the Typical Operating Circuit.
1
Added “noncondensing” to operating temperature range; changed VPF MIN from
2.35V to 2.45V.
2
Added aging offset specification. 3
Relabeled TOC4. 7
Added arrow showing input on X1 in the Block Diagram. 8
Updated pin descriptions for VCC and VBAT. 9
Added the I2C Interface section. 10
Figure 1: Added sign bit to aging and temperature registers; added MSB and LSB. 11
Corrected title for rate select bits frequency table. 13
Added note that frequency stability over temperature spec is with aging offset
register = 00h; changed bit 7 from Data to Sign (Crystal Aging Offset Register).
14
Changed bit 7 from Data to Sign (Temperature Register); correct pin definitions
in I2C Serial Data Bus section.
15
2 6/05
Modified the Handing, PC Board Layout, and Assembly section to refer to
J-STD-020 for reflow profiles for lead-free and leaded packages.
17
3 11/05 Changed lead-free packages to RoHS-compliant packages. 1
Changed RST and UL bullets in Features. 1
Changed EC condition “VCC > VBAT” to “VCC = Active Supply (see Table 1).” 2, 3
Modified Note 12 to correct tREC operation. 6
Added various conditions text to TOCs 1, 2, and 3. 7
Added text to pin descriptions for 32kHz, VCC, and RST. 9
Table 1: Changed column heading “Powered By” to “Active Supply”; changed
“applied” to “exceeds VPF” in the Power Control section. 10
Indicated BBSQW applies to both SQW and interrupts; simplified temp convert
description (bit 5); added “output” to INT\SQW (bit 2). 13
4 10/06
Changed the Crystal Aging section to the Aging Offset section; changed “this
bit indicates” to “this bit controls” for the enable 32kHz output bit. 14
Added Warning note to EC table notes; updated Note 12. 6
Updated the Typical Operating Characteristics graphs. 7
In the Power Control section, added information about the POR state of the time
and date registers; in the Real-Time Clock section, added to the description of
the RST function.
10
5 4/08
In Figure 1, corrected the months date range for 04h from 00–31 to 01–31. 11
© 2007 Microchip Technology Inc. Preliminary DS39631B
PIC18F2420/2520/4420/4520
Data Sheet
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt Technology
DS39631B-page ii Preliminary © 2007 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 1
PIC18F2420/2520/4420/4520
Power Managed Modes:
• Run: CPU on, peripherals on
• Idle: CPU off, peripherals on
• Sleep: CPU off, peripherals off
• Idle mode currents down to 5.8 μA typical
• Sleep mode current down to 0.1 μA typical
• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
• Two-Speed Oscillator Start-up
Peripheral Highlights:
• High-current sink/source 25 mA/25 mA
• Three programmable external interrupts
• Four input change interrupts
• Up to 2 Capture/Compare/PWM (CCP) modules,
one with Auto-Shutdown (28-pin devices)
• Enhanced Capture/Compare/PWM (ECCP)
module (40/44-pin devices only):
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
• Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI™ (all 4 modes) and I2C™
Master and Slave Modes
• Enhanced Addressable USART module:
- Supports RS-485, RS-232 and LIN 1.2
- RS-232 operation using internal oscillator
block (no external crystal required)
- Auto-Wake-up on Start bit
- Auto-Baud Detect
• 10-bit, up to 13-channel Analog-to-Digital
Converter module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
• Dual analog comparators with input multiplexing)
Flexible Oscillator Structure:
• Four Crystal modes, up to 40 MHz
• 4X Phase Lock Loop (available for crystal and
internal oscillators)
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal oscillator block:
- 8 user selectable frequencies, from 31 kHz to 8 MHz
- Provides a complete range of clock speeds
from 31 kHz to 32 MHz when used with PLL
- User tunable to compensate for frequency drift
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if peripheral clock stops
Special Microcontroller Features:
• C compiler optimized architecture:
- Optional extended instruction set designed to
optimize re-entrant code
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Flash/Data EEPROM Retention: 100 years typical
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-supply 5V In-Circuit Serial
Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
• Programmable 16-level High/Low-Voltage
Detection (HLVD) module:
- Supports interrupt on High/Low-Voltage
Detection
• Programmable Brown-out Reset (BOR
- With software enable option
28/40/44-Pin Enhanced Flash Microcontrollers with
10-Bit A/D and nanoWatt Technology
PIC18F2420/2520/4420/4520
DS39631B-page 2 Preliminary © 2007 Microchip Technology Inc.
-
Device
Program Memory Data Memory
I/O
10-bit
A/D (ch)
CCP/
ECCP
(PWM)
MSSP
EUSART
Comp.
Timers
Flash 8/16-bit
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
SPI
Master
I2C
PIC18F2420 16K 8192 768 256 25 10 2/0 Y Y 1 2 1/3
PIC18F2520 32K 16384 1536 256 25 10 2/0 Y Y 1 2 1/3
PIC18F4420 16K 8192 768 256 36 13 1/1 Y Y 1 2 1/3
PIC18F4520 32K 16384 1536 256 36 13 1/1 Y Y 1 2 1/3
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 3
PIC18F2420/2520/4420/4520
Pin Diagrams
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F4520 PIC18F2520
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
40-pin PDIP
28-pin PDIP, SOIC
PIC18F4420 PIC18F2420
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
1011
2
3
6
1
18
19
20
21
22
12 13 14
15
8
7
16
17
2827 2625 2423
9
PIC18F2420
RC0/T1OSO/T13CKI
5
4
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4KBI0/AN11
RB3/AN9/CCP2(1)
RB2/INT2/AN8
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI/RA7
OSC2/CLKO/RA6
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
PIC18F2520
28-pin QFN
PIC18F2420/2520/4420/4520
DS39631B-page 4 Preliminary © 2007 Microchip Technology Inc.
Pin Diagrams (Cont.’d)
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
10
11
2
345
6
1
18
19
20
21
22
12
13
14
15
38
8 7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4420
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
RB3/AN9/CCP2(1)
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
44-pin QFN
PIC18F4520
10
11
2
345
6
1
18
19
20
21
22
12
13
14
15
38
8 7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18F4420
37
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
MCLR/VPP/RE3
NC
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)
NC
NC
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
VSS
VDD
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
44-pin TQFP
PIC18F4520
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 5
PIC18F2420/2520/4420/4520
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 23
3.0 Power Managed Modes ............................................................................................................................................................. 33
4.0 Reset .......................................................................................................................................................................................... 41
5.0 Memory Organization................................................................................................................................................................. 53
6.0 Flash Program Memory.............................................................................................................................................................. 73
7.0 Data EEPROM Memory ............................................................................................................................................................. 83
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 89
9.0 Interrupts .................................................................................................................................................................................... 91
10.0 I/O Ports ................................................................................................................................................................................... 105
11.0 Timer0 Module ......................................................................................................................................................................... 123
12.0 Timer1 Module ......................................................................................................................................................................... 127
13.0 Timer2 Module ......................................................................................................................................................................... 133
14.0 Timer3 Module ......................................................................................................................................................................... 135
15.0 Capture/Compare/Pwm (CCP) Modules .................................................................................................................................. 139
16.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 147
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 161
18.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 201
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 223
20.0 Comparator Module.................................................................................................................................................................. 233
21.0 Comparator Voltage Reference Module................................................................................................................................... 239
22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 243
23.0 Special Features of the CPU.................................................................................................................................................... 249
24.0 Instruction Set Summary .......................................................................................................................................................... 267
25.0 Development Support............................................................................................................................................................... 317
26.0 Electrical Characteristics .......................................................................................................................................................... 323
27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 361
28.0 Packaging Information.............................................................................................................................................................. 363
Appendix A: Revision History............................................................................................................................................................. 371
Appendix B: Device Differences ........................................................................................................................................................ 371
Appendix C: Conversion Considerations ........................................................................................................................................... 372
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 372
Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 373
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 373
Index .................................................................................................................................................................................................. 375
On-Line Support................................................................................................................................................................................. 385
Systems Information and Upgrade Hot Line ...................................................................................................................................... 385
Reader Response .............................................................................................................................................................................. 386
PIC18F2420/2520/4420/4520 Product Identification System ............................................................................................................ 387
PIC18F2420/2520/4420/4520
DS39631B-page 6 Preliminary © 2007 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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© 2007 Microchip Technology Inc. Preliminary DS39631B-page 7
PIC18F2420/2520/4420/4520
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18 microcontrollers
– namely, high computational performance
at an economical price – with the addition of highendurance,
Enhanced Flash program memory. On top
of these features, the PIC18F2420/2520/4420/4520
family introduces design enhancements that make
these microcontrollers a logical choice for many highperformance,
power sensitive applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F2420/2520/4420/4520
family incorporate a range of features that can significantly
reduce power consumption during operation.
Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled but the peripherals still
active. In these states, power consumption can be
reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The power
managed modes are invoked by user code during
operation, allowing the user to incorporate powersaving
ideas into their application’s software
design.
• Low Consumption in Key Modules: The
power requirements for both Timer1 and the
Watchdog Timer are minimized. See
Section 26.0 “Electrical Characteristics”
for values.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F2420/2520/4420/4520
family offer ten different oscillator options, allowing
users a wide range of choices in developing application
hardware. These include:
• Four Crystal modes, using crystals or ceramic
resonators
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output) or one pin (oscillator input, with the
second pin reassigned as general I/O)
• Two External RC Oscillator modes with the same
pin options as the External Clock modes
• An internal oscillator block which provides an
8 MHz clock and an INTRC source (approximately
31 kHz), as well as a range of 6 user
selectable clock frequencies, between 125 kHz to
4 MHz, for a total of 8 clock frequencies. This
option frees the two oscillator pins for use as
additional general purpose I/O.
• A Phase Lock Loop (PLL) frequency multiplier,
available to both the high-speed crystal and internal
oscillator modes, which allows clock speeds of
up to 40 MHz. Used with the internal oscillator, the
PLL gives users a complete selection of clock
speeds, from 31 kHz to 32 MHz – all without using
an external crystal or clock circuit.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a
clock failure occurs, the controller is switched to
the internal oscillator block, allowing for continued
low-speed operation or a safe application
shutdown.
• Two-Speed Start-up: This option allows the
internal oscillator to serve as the clock source
from Power-on Reset, or wake-up from Sleep
mode, until the primary clock source is available.
• PIC18F2420 • PIC18LF2420
• PIC18F2520 • PIC18LF2520
• PIC18F4420 • PIC18LF4420
• PIC18F4520 • PIC18LF4520
PIC18F2420/2520/4420/4520
DS39631B-page 8 Preliminary © 2007 Microchip Technology Inc.
1.2 Other Special Features
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Self-programmability: These devices can write
to their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top
of program memory, it becomes possible to create
an application that can update itself in the field.
• Extended Instruction Set: The PIC18F2420/
2520/4420/4520 family introduces an optional
extension to the PIC18 instruction set, which adds
8 new instructions and an Indexed Addressing
mode. This extension, enabled as a device configuration
option, has been specifically designed
to optimize re-entrant application code originally
developed in high-level languages, such as C.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers.
Other features include Auto-Shutdown, for disabling
PWM outputs on interrupt or other select
conditions and Auto-Restart, to reactivate outputs
once the condition has cleared.
• Enhanced Addressable USART: This serial
communication module is capable of standard
RS-232 operation and provides support for the LIN
bus protocol. Other enhancements include
automatic baud rate detection and a 16-bit Baud
Rate Generator for improved resolution. When the
microcontroller is using the internal oscillator
block, the USART provides stable operation for
applications that talk to the outside world without
using an external crystal (or its accompanying
power requirement).
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This
enhanced version incorporates a 16-bit prescaler,
allowing an extended time-out range that is stable
across operating voltage and temperature. See
Section 26.0 “Electrical Characteristics” for
time-out periods.
1.3 Details on Individual Family
Members
Devices in the PIC18F2420/2520/4420/4520 family are
available in 28-pin and 40/44-pin packages. Block
diagrams for the two groups are shown in Figure 1-1
and Figure 1-2.
The devices are differentiated from each other in five
ways:
1. Flash program memory (16 Kbytes for
PIC18F2420/4420 devices and 32 Kbytes for
PIC18F2520/4520).
2. A/D channels (10 for 28-pin devices, 13 for
40/44-pin devices).
3. I/O ports (3 bidirectional ports on 28-pin devices,
5 bidirectional ports on 40/44-pin devices).
4. CCP and Enhanced CCP implementation
(28-pin devices have 2 standard CCP modules,
40/44-pin devices have one standard CCP
module and one ECCP module).
5. Parallel Slave Port (present only on 40/44-pin
devices).
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F2420/2520/4420/4520 family are available as
both standard and low-voltage devices. Standard
devices with Enhanced Flash memory, designated with
an “F” in the part number (such as PIC18F2420),
accommodate an operating VDD range of 4.2V to 5.5V.
Low-voltage parts, designated by “LF” (such as
PIC18LF2420), function over an extended VDD range
of 2.0V to 5.5V.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 9
PIC18F2420/2520/4420/4520
TABLE 1-1: DEVICE FEATURES
Features PIC18F2420 PIC18F2520 PIC18F4420 PIC18F4520
Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 16384 32768 16384 32768
Program Memory
(Instructions)
8192 16384 8192 16384
Data Memory (Bytes) 768 1536 768 1536
Data EEPROM Memory (Bytes) 256 256 256 256
Interrupt Sources 19 19 20 20
I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PWM Modules 2 2 1 1
Enhanced
Capture/Compare/PWM Modules
0 0 1 1
Serial Communications MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Parallel Communications (PSP) No No Yes Yes
10-bit Analog-to-Digital Module 10 Input Channels 10 Input Channels 13 Input Channels 13 Input Channels
Resets (and Delays) POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction,
Stack Full, Stack
Underflow (PWRT, OST),
MCLR (optional), WDT
Programmable
High/Low-Voltage Detect
Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
75 Instructions;
83 with Extended
Instruction Set enabled
Packages 28-pin PDIP
28-pin SOIC
28-pin QFN
28-pin PDIP
28-pin SOIC
28-pin QFN
40-pin PDIP
44-pin QFN
44-pin TQFP
40-pin PDIP
44-pin QFN
44-pin TQFP
PIC18F2420/2520/4420/4520
DS39631B-page 10 Preliminary © 2007 Microchip Technology Inc.
FIGURE 1-1: PIC18F2420/2520 (28-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
Data Latch
Data Memory
( 3.9 Kbytes )
Address Latch
Data Address<12>
12
BSR FSR0 Access
FSR1
FSR2
inc/dec
logic
Address
4 12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
8
BITOP
8 8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
RB2/INT2/AN8
RB3/AN9/CCP2(1)
PCLATU
PCU
OSC2/CLKO(3)/RA6
Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
Comparator MSSP EUSART 10-bit
ADC
Timer0 Timer1 Timer2 Timer3
CCP2
HLVD
CCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSO
OSC1/CLKI(3)/RA7
T1OSI
PORTE
MCLR/VPP/RE3(2)
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 11
PIC18F2420/2520/4420/4520
FIGURE 1-2: PIC18F4420/4520 (40/44-PIN) BLOCK DIAGRAM
Instruction
Decode and
Control
Data Latch
Data Memory
( 3.9 Kbytes )
Address Latch
Data Address<12>
12
BSR FSR0 Access
FSR1
FSR2
inc/dec
logic
Address
4 12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
8
BITOP
8 8
ALU<8>
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
20
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
PORTD
RD0/PSP0
PCLATU
PCU
PORTE
MCLR/VPP/RE3(2)
RE2/CS/AN7
RE0/RD/AN5
RE1/WR/AN6
Note 1: CCP2 is multiplexed with RC1 when configuration bit CCP2MX is set, or RB3 when CCP2MX is not set.
2: RE3 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
:RD4/PSP4
Comparator MSSP EUSART 10-bit
ADC
Timer0 Timer1 Timer2 Timer3
CCP2
HLVD
ECCP1
BOR Data
EEPROM
W
Instruction Bus <16>
STKPTR Bank
8
State machine
control signals
Decode
8
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
OSC1(3)
OSC2(3)
VDD,
Brown-out
Reset
Internal
Oscillator
Fail-Safe
Clock Monitor
Precision
Reference
Band Gap
VSS
MCLR(2)
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
T1OSI
T1OSO
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
PORTA
PORTB
PORTC
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
RB0/INT0/FLT0/AN12
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-/CVREF
RA1/AN1
RA0/AN0
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2(1)
OSC2/CLKO(3)/RA6
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
OSC1/CLKI(3)/RA7
PIC18F2420/2520/4420/4520
DS39631B-page 12 Preliminary © 2007 Microchip Technology Inc.
TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
PDIP, Description
SOIC
QFN
MCLR/VPP/RE3
MCLR
VPP
RE3
1 26
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
9 6
I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
External clock source input. Always associated with pin
function OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 7
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 13
PIC18F2420/2520/4420/4520
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2 27
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3 28
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4 1
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5 2
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6 3
I/O
I
O
ST
ST
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7 4
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI™ slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PDIP, Description
SOIC
QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PIC18F2420/2520/4420/4520
DS39631B-page 14 Preliminary © 2007 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
21 18
I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O.
External interrupt 0.
PWM Fault input for CCP1.
Analog input 12.
RB1/INT1/AN10
RB1
INT1
AN10
22 19
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 10.
RB2/INT2/AN8
RB2
INT2
AN8
23 20
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 2.
Analog input 8.
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
24 21
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
RB4/KBI0/AN11
RB4
KBI0
AN11
25 22
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
RB5/KBI1/PGM
RB5
KBI1
PGM
26 23
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
27 24
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
28 25
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PDIP, Description
SOIC
QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 15
PIC18F2420/2520/4420/4520
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
11 8
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
12 9
I/O
I
I/O
ST
Analog
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
RC2/CCP1
RC2
CCP1
13 10
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 11
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI™ mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 12
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
16 13
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
17 14
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
18 15
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
RE3 — — — — See MCLR/VPP/RE3 pin.
VSS 8, 19 5, 16 P — Ground reference for logic and I/O pins.
VDD 20 17 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18F2420/2520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PDIP, Description
SOIC
QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PIC18F2420/2520/4420/4520
DS39631B-page 16 Preliminary © 2007 Microchip Technology Inc.
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
MCLR/VPP/RE3
MCLR
VPP
RE3
1 18 18
I
P
I
ST
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
13 32 30
I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode;
analog otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 33 31
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which
has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 17
PIC18F2420/2520/4420/4520
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
2 19 19
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3 20 20
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
4 21 21
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Comparator reference voltage output.
RA3/AN3/VREF+
RA3
AN3
VREF+
5 22 22
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI/C1OUT
RA4
T0CKI
C1OUT
6 23 23
I/O
I
O
ST
ST
—
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
RA5/AN4/SS/HLVDIN/
C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
7 24 24
I/O
I
I
I
O
TTL
Analog
TTL
Analog
—
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PIC18F2420/2520/4420/4520
DS39631B-page 18 Preliminary © 2007 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0/FLT0/AN12
RB0
INT0
FLT0
AN12
33 9 8
I/O
I
I
I
TTL
ST
ST
Analog
Digital I/O.
External interrupt 0.
PWM Fault input for Enhanced CCP1.
Analog input 12.
RB1/INT1/AN10
RB1
INT1
AN10
34 10 9
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 1.
Analog input 10.
RB2/INT2/AN8
RB2
INT2
AN8
35 11 10
I/O
I
I
TTL
ST
Analog
Digital I/O.
External interrupt 2.
Analog input 8.
RB3/AN9/CCP2
RB3
AN9
CCP2(1)
36 12 11
I/O
I
I/O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
RB4/KBI0/AN11
RB4
KBI0
AN11
37 14 14
I/O
I
I
TTL
TTL
Analog
Digital I/O.
Interrupt-on-change pin.
Analog input 11.
RB5/KBI1/PGM
RB5
KBI1
PGM
38 15 15
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
39 16 16
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
40 17 17
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming
data pin.
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 19
PIC18F2420/2520/4420/4520
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15 34 32
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2(2)
16 35 35
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM 2 output.
RC2/CCP1/P1A
RC2
CCP1
P1A
17 36 36
I/O
I/O
O
ST
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 37 37
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI™ mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 42 42
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
RC5/SDO
RC5
SDO
24 43 43
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
25 44 44
I/O
O
I/O
ST
—
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
26 1 1
I/O
I
I/O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PIC18F2420/2520/4420/4520
DS39631B-page 20 Preliminary © 2007 Microchip Technology Inc.
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when PSP module
is enabled.
RD0/PSP0
RD0
PSP0
19 38 38
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD1/PSP1
RD1
PSP1
20 39 39
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD2/PSP2
RD2
PSP2
21 40 40
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD3/PSP3
RD3
PSP3
22 41 41
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD4/PSP4
RD4
PSP4
27 2 2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
RD5/PSP5/P1B
RD5
PSP5
P1B
28 3 3
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD6/PSP6/P1C
RD6
PSP6
P1C
29 4 4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
RD7/PSP7/P1D
RD7
PSP7
P1D
30 5 5
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 21
PIC18F2420/2520/4420/4520
PORTE is a bidirectional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8 25 25
I/O
I
I
ST
TTL
Analog
Digital I/O.
Read control for Parallel Slave Port
(see also WR and CS pins).
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
9 26 26
I/O
I
I
ST
TTL
Analog
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 27 27
I/O
I
I
ST
TTL
Analog
Digital I/O.
Chip Select control for Parallel Slave Port
(see related RD and WR).
Analog input 7.
RE3 — — — — — See MCLR/VPP/RE3 pin.
VSS 12, 31 6, 30,
31
6, 29 P — Ground reference for logic and I/O pins.
VDD 11, 32 7, 8,
28, 29
7, 28 P — Positive supply for logic and I/O pins.
NC — 13 12, 13,
33, 34
— — No connect.
TABLE 1-3: PIC18F4420/4520 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number Pin
Type
Buffer
Type
Description
PDIP QFN TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
Note 1: Default assignment for CCP2 when configuration bit CCP2MX is set.
2: Alternate assignment for CCP2 when configuration bit CCP2MX is cleared.
PIC18F2420/2520/4420/4520
DS39631B-page 22 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 23
PIC18F2420/2520/4420/4520
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
PIC18F2420/2520/4420/4520 devices can be operated
in ten different oscillator modes. The user can program
the configuration bits, FOSC3:FOSC0, in Configuration
Register 1H to select one of these ten modes:
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO External Resistor/Capacitor with I/O
on RA6
7. INTIO1 Internal Oscillator with FOSC/4 output
on RA6 and I/O on RA7
8. INTIO2 Internal Oscillator with I/O on RA6
and RA7
9. EC External Clock with FOSC/4 output
10. ECIO External Clock with I/O on RA6
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
TABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Use of a series cut crystal may give a frequency
out of the crystal manufacturer’s
specifications.
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 3.58 MHz
4.19 MHz
4 MHz
4 MHz
15 pF
15 pF
30 pF
50 pF
15 pF
15 pF
30 pF
50 pF
Capacitor values are for design guidance only.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Note: When using resonators with frequencies
above 3.5 MHz, the use of HS mode,
rather than XT mode, is recommended.
HS mode may be used at any VDD for
which the controller is rated. If HS is
selected, it is possible that the gain of the
oscillator will overdrive the resonator.
Therefore, a series resistor should be
placed between the OSC2 pin and the
resonator. As a good starting point, the
recommended value of RS is 330Ω.
Note 1: See Table 2-1 and Table 2-2 for initial values of
C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18FXXXX
RS(2)
Internal
PIC18F2420/2520/4420/4520
DS39631B-page 24 Preliminary © 2007 Microchip Technology Inc.
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
2.3 External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-3: EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional general
purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-4 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK
INPUT OPERATION
(ECIO CONFIGURATION)
Osc Type
Crystal
Freq
Typical Capacitor Values
Tested:
C1 C2
LP 32 kHz 30 pF 30 pF
XT 1 MHz
4 MHz
15 pF
15 pF
15 pF
15 pF
HS 4 MHz
10 MHz
20 MHz
25 MHz
25 MHz
15 pF
15 pF
15 pF
0 pF
15 pF
15 pF
15 pF
15 pF
5 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Crystals Used:
32 kHz 4 MHz
25 MHz 10 MHz
1 MHz 20 MHz
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Rs may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
OSC1
Open OSC2
Clock from
Ext. System PIC18FXXXX
(HS Mode)
OSC1/CLKI
FOSC/4 OSC2/CLKO
Clock from
Ext. System PIC18FXXXX
OSC1/CLKI
RA6 I/O (OSC2)
Clock from
Ext. System PIC18FXXXX
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 25
PIC18F2420/2520/4420/4520
2.4 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:
• supply voltage
• values of the external resistor (REXT) and
capacitor (CEXT)
• operating temperature
Given the same device, operating voltage and temperature
and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
• normal manufacturing variation
• difference in lead frame capacitance between
package types (especially for low CEXT values)
• variations within the tolerance of limits of REXT
and CEXT
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-5 shows how the R/C combination is
connected.
FIGURE 2-5: RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 2-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 2-6: RCIO OSCILLATOR MODE
2.5 PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
2.5.1 HSPLL OSCILLATOR MODE
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz. The PLLEN bit is not
available in this oscillator mode.
The PLL is only available to the crystal oscillator when
the FOSC3:FOSC0 configuration bits are programmed
for HSPLL mode (= 0110).
FIGURE 2-7: PLL BLOCK DIAGRAM
(HS MODE)
2.5.2 PLL AND INTOSC
The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock output
of up to 32 MHz. The operation of INTOSC with the
PLL is described in Section 2.6.4 “PLL in INTOSC
Modes”.
OSC2/CLKO
CEXT
REXT
PIC18FXXXX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
CEXT
REXT
PIC18FXXXX
OSC1 Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
RA6 I/O (OSC2)
MUX
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
÷4
(from Configuration Register 1H)
HS Mode
PIC18F2420/2520/4420/4520
DS39631B-page 26 Preliminary © 2007 Microchip Technology Inc.
2.6 Internal Oscillator Block
The PIC18F2420/2520/4420/4520 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the microcontroller’s
clock source. This may eliminate the need for
external oscillator circuits on the OSC1 and/or OSC2
pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the device clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 30).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source eliminates
the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
2.6.2 INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s application.
This is done by writing to the OSCTUNE register
(Register 2-1).
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTRC clock will reach the new frequency within
8 clock cycles (approximately 8 * 32 μs = 256 μs). The
INTOSC clock will stabilize within 1 ms. Code execution
continues during this shift. There is no indication
that the shift has occurred.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.
2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the internal
oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output frequency
is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.
2.6.5 INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made and in some cases, how large a change is
needed. Three compensation techniques are discussed
in Section 2.6.5.1 “Compensating with the USART”,
Section 2.6.5.2 “Compensating with the Timers” and
Section 2.6.5.3 “Compensating with the CCP Module
in Capture Mode”, but other techniques may be used.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 27
PIC18F2420/2520/4420/4520
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
2.6.5.1 Compensating with the USART
An adjustment may be required when the USART
begins to generate framing errors or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the device clock frequency is too high; to
adjust for this, decrement the value in OSCTUNE to
reduce the clock frequency. On the other hand, errors
in data may suggest that the clock speed is too low; to
compensate, increment OSCTUNE to increase the
clock frequency.
2.6.5.2 Compensating with the Timers
This technique compares device clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast. To adjust for this, decrement
the OSCTUNE register.
2.6.5.3 Compensating with the CCP Module
in Capture Mode
A CCP module can use free running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power frequency).
The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the calculated
time, the internal oscillator block is running too
fast; to compensate, decrement the OSCTUNE register.
If the measured time is much less than the calculated
time, the internal oscillator block is running too slow; to
compensate, increment the OSCTUNE register.
R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)
0 = 31 kHz device clock derived directly from INTRC internal oscillator
bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)
1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)
0 = PLL disabled
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable
and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.
bit 5 Unimplemented: Read as ‘0’
bit 4-0 TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 28 Preliminary © 2007 Microchip Technology Inc.
2.7 Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F2420/2520/
4420/4520 family includes a feature that allows the
device clock source to be switched from the main oscillator
to an alternate low-frequency clock source.
PIC18F2420/2520/4420/4520 devices offer two alternate
clock sources. When an alternate clock source is enabled,
the various power managed operating modes are available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
configuration bits. The details of these modes are
covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F2420/2520/4420/4520 devices offer the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power managed modes, is often the time base for
functions such as a real-time clock.
Most often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI
pins. Like the LP mode oscillator circuit, loading
capacitors are also connected from each pin to ground.
The Timer1 oscillator is discussed in greater detail in
Section 12.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F2420/2520/4420/4520
devices are shown in Figure 2-8. See Section 23.0
“Special Features of the CPU” for Configuration
register details.
FIGURE 2-8: PIC18F2420/2520/4420/4520 CLOCK DIAGRAM
PIC18F2420/2520/4420/4520
4 x PLL
FOSC3:FOSC0
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for other Modules
OSC1
OSC2
Sleep HSPLL, INTOSC/PLL
LP, XT, HS, RC, EC
T1OSC
CPU
Peripherals
IDLEN Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000
31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, PWRT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
OSCCON<6:4>
Clock
Control
OSCCON<1:0>
Source
8 MHz
31 kHz (INTRC)
OSCTUNE<6>
0
1
OSCTUNE<7>
and Two-Speed Start-up
Primary Oscillator
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 29
PIC18F2420/2520/4420/4520
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 configuration
bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The Internal Oscillator Frequency Select bits
(IRCF2:IRCF0) select the frequency output of the
internal oscillator block to drive the device clock. The
choices are the INTRC source, the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31.25 kHz to 4 MHz). If the
internal oscillator block is supplying the device clock,
changing the states of these bits will have an immediate
change on the internal oscillator’s output. On
device Resets, the default output frequency of the
internal oscillator block is set at 1 MHz.
When a nominal output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which internal
oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has stabilized
and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock or the internal oscillator block has just started and
is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power Managed Modes”.
2.7.2 OSCILLATOR TRANSITIONS
PIC18F2420/2520/4420/4520 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register
(T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source will be ignored.
2: It is recommended that the Timer1
oscillator be operating and stable before
selecting the secondary clock source or a
very long delay may occur while the
Timer1 oscillator starts.
PIC18F2420/2520/4420/4520
DS39631B-page 30 Preliminary © 2007 Microchip Technology Inc.
REGISTER 2-2: OSCCON REGISTER
R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
bit 7 IDLEN: Idle Enable bit
1 = Device enters Idle mode on SLEEP instruction
0 = Device enters Sleep mode on SLEEP instruction
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (INTOSC drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz(3)
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Oscillator start-up time-out timer has expired; primary oscillator is running
0 = Oscillator start-up time-out timer is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x = Internal oscillator block
01 = Secondary (Timer1) oscillator
00 = Primary oscillator
Note 1: Reset state depends on state of the IESO configuration bit.
2: Source selected by the INTSRC bit (OSCTUNE<7>), see text.
3: Default output frequency of INTOSC on Reset.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 31
PIC18F2420/2520/4420/4520
2.8 Effects of Power Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated primary
oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and providing
the device clock. The Timer1 oscillator may also
run in all power managed modes if required to clock
Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support
various special features, regardless of the power
managed mode (see Section 23.2 “Watchdog Timer
(WDT)”, Section 23.3 “Two-Speed Start-up” and
Section 23.4 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and Two-
Speed Start-up). The INTOSC output at 8 MHz may be
used directly to clock the device or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a realtime
clock. Other features may be operating that do not
require a device clock source (i.e., SSP slave, PSP,
INTn pins and others). Peripherals that may add
significant current consumption are listed in
Section 26.2 “DC Characteristics”.
2.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applications.
The delays ensure that the device is kept in
Reset until the device power supply is stable under normal
circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 4.5 “Device Reset Timers”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 26-10). It is enabled by clearing (= 0) the
PWRTEN configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval TCSD (parameter 38,
Table 26-10), following POR, while the controller
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO Floating, external resistor should pull high Configured as PORTA, bit 6
INTIO2 Configured as PORTA, bit 7 Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.
PIC18F2420/2520/4420/4520
DS39631B-page 32 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS39631B-page 33
PIC18F2420/2520/4420/4520
3.0 POWER MANAGED MODES
PIC18F2420/2520/4420/4520 devices offer a total of
seven operating modes for more efficient power management.
These modes provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery-powered
devices).
There are three categories of power managed modes:
• Run modes
• Idle modes
• Sleep mode
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or internal oscillator
block); the Sleep mode does not use a clock source.
The power managed modes include several powersaving
features offered on previous PIC® devices. One
is the clock switching feature, offered in other PIC18
devices, allowing the controller to use the Timer1 oscillator
in place of the primary oscillator. Also included is
the Sleep mode, offered by all PIC devices, where all
device clocks are stopped.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires two
decisions: if the CPU is to be clocked or not and the
selection of a clock source. The IDLEN bit
(OSCCON<7>) controls CPU clocking, while the
SCS1:SCS0 bits (OSCCON<1:0>) select the clock
source. The individual modes, bit settings, clock sources
and affected modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power managed modes. They are:
• the primary clock, as defined by the
FOSC3:FOSC0 configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block (for RC modes)
3.1.2 ENTERING POWER MANAGED
MODES
Switching from one power managed mode to another
begins by loading the OSCCON register. The
SCS1:SCS0 bits select the clock source and determine
which Run or Idle mode is to be used. Changing these
bits causes an immediate switch to the new clock
source, assuming that it is running. The switch may
also be subject to clock transition delays. These are
discussed in Section 3.1.3 “Clock Transitions and
Status Indicators” and subsequent sections.
Entry to the Power Managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power managed mode does
not always require setting all of these bits. Many
transitions may be done by changing the oscillator select
bits, or changing the IDLEN bit, prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 3-1: POWER MANAGED MODES
Mode
OSCCON Bits Module Clocking
IDLEN(1) Available Clock and Oscillator Source
<7>
SCS1:SCS0
<1:0>
CPU Peripherals
Sleep 0 N/A Off Off None – All clocks are disabled
PRI_RUN N/A 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC and
Internal Oscillator Block(2).
This is the normal full power execution mode.
SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN N/A 1x Clocked Clocked Internal Oscillator Block(2)
PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 1 1x Off Clocked Internal Oscillator Block(2)
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
PIC18F2420/2520/4420/4520
DS39631B-page 34 © 2007 Microchip Technology Inc.
3.1.3 CLOCK TRANSITIONS AND STATUS
INDICATORS
The length of the transition between clock sources is
the sum of two cycles of the old clock source and three
to four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Three bits indicate the current clock source and its
status. They are:
• OSTS (OSCCON<3>)
• IOFS (OSCCON<2>)
• T1RUN (T1CON<6>)
In general, only one of these bits will be set while in a
given power managed mode. When the OSTS bit is
set, the primary clock is providing the device clock.
When the IOFS bit is set, the INTOSC output is
providing a stable 8 MHz clock source to a divider that
actually drives the device clock. When the T1RUN bit is
set, the Timer1 oscillator is providing the clock. If none
of these bits are set, then either the INTRC clock
source is clocking the device, or the INTOSC source is
not yet stable.
If the internal oscillator block is configured as the primary
clock source by the FOSC3:FOSC0 configuration
bits, then both the OSTS and IOFS bits may be set
when in PRI_RUN or PRI_IDLE modes. This indicates
that the primary clock (INTOSC output) is generating a
stable 8 MHz output. Entering another RC Power
Managed mode at the same frequency would clear the
OSTS bit.
3.1.4 MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEP instruction is determined by the setting of the
IDLEN bit at the time the instruction is executed. If
another SLEEP instruction is executed, the device will
enter the power managed mode specified by IDLEN at
that time. If IDLEN has changed, the device will enter
the new power managed mode specified by the new
setting.
3.2 Run Modes
In the Run modes, clocks to both the core and
peripherals are active. The difference between these
modes is the clock source.
3.2.1 PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution
mode of the microcontroller. This is also the default
mode upon a device Reset, unless Two-Speed Start-up
is enabled (see Section 23.3 “Two-Speed Start-up”
for details). In this mode, the OSTS bit is set. The IOFS
bit may be set if the internal oscillator block is the primary
clock source (see Section 2.7.1 “Oscillator
Control Register”).
3.2.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by setting the SCS1:SCS0
bits to ‘01’. The device clock source is switched to the
Timer1 oscillator (see Figure 3-1), the primary oscillator
is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
On transitions from SEC_RUN mode to PRI_RUN, the
peripherals and CPU continue to be clocked from the
Timer1 oscillator while the primary clock is started.
When the primary clock becomes ready, a clock switch
back to the primary clock occurs (see Figure 3-2).
When the clock switch is complete, the T1RUN bit is
cleared, the OSTS bit is set and the primary clock is
providing the clock. The IDLEN and SCS bits are not
affected by the wake-up; the Timer1 oscillator
continues to run.
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode. It acts as the trigger to place the
controller into either the Sleep mode or
one of the Idle modes, depending on the
setting of the IDLEN bit.
Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SCS1:SCS0 bits are set to ‘01’, entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, device clocks will be delayed until
the oscillator has started; in such situations,
initial oscillator operation is far from
stable and unpredictable operation may
result.
© 2007 Microchip Technology Inc. DS39631B-page 35
PIC18F2420/2520/4420/4520
FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distinguishable
differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software compatibility
with future devices. When the clock source is
switched to the INTOSC multiplexer (see Figure 3-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC PC + 2
1 2 3 n-1 n
Clock Transition(1)
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
Q1 Q3 Q4
OSC1
Peripheral
Program PC
T1OSI
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
SCS1:SCS0 bits changed
TPLL(1)
1 2 n-1 n
Clock
OSTS bit set
Transition(2)
TOST(1)
Note: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
PIC18F2420/2520/4420/4520
DS39631B-page 36 © 2007 Microchip Technology Inc.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
TIOBST.
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-3: TRANSITION TIMING TO RC_RUN MODE
FIGURE 3-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC PC + 2
1 2 3 n-1 n
Clock Transition(1)
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
Note 1: Clock transition typically occurs within 2-4 TOSC.
Q1 Q3 Q4
OSC1
Peripheral
Program PC
INTOSC
PLL Clock
Q1
PC + 4
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 2
Clock
Counter
Q2 Q2 Q3
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
2: Clock transition typically occurs within 2-4 TOSC.
SCS1:SCS0 bits changed
TPLL(1)
1 2 n-1 n
Clock
OSTS bit set
Transition(2)
Multiplexer
TOST(1)
© 2007 Microchip Technology Inc. DS39631B-page 37
PIC18F2420/2520/4420/4520
3.3 Sleep Mode
The Power Managed Sleep mode in the PIC18F2420/
2520/4420/4520 devices is identical to the legacy
Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 3-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS1:SCS0 bits
becomes ready (see Figure 3-6), or it will be clocked
from the internal oscillator block if either the Two-
Speed Start-up or the Fail-Safe Clock Monitor are
enabled (see Section 23.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The
IDLEN and SCS bits are not affected by the wake-up.
3.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS1:SCS0 bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 26-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE
FIGURE 3-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4
OSC1
Peripheral
Sleep
Program
Q1 Q1
Counter
Clock
CPU
Clock
PC PC + 2
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 6 PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit set
PC + 2
PIC18F2420/2520/4420/4520
DS39631B-page 38 © 2007 Microchip Technology Inc.
3.4.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruction.
If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 configuration bits. The OSTS bit
remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wakeup,
the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-8).
3.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by setting
the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS1:SCS0 bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of TCSD following the wake event, the CPU begins executing
code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such situations,
initial oscillator operation is far
from stable and unpredictable operation
may result.
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD
© 2007 Microchip Technology Inc. DS39631B-page 39
PIC18F2420/2520/4420/4520
3.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals
continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. Although its value is
ignored, it is recommended that SCS0 also be cleared;
this is to maintain software compatibility with future
devices. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC bit is set, the INTOSC output is enabled. The
IOFS bit becomes set, after the INTOSC output
becomes stable, after an interval of TIOBST
(parameter 39, Table 26-10). Clocks to the peripherals
continue while the INTOSC source stabilizes. If the
IRCF bits were previously at a non-zero value, or
INTSRC was set before the SLEEP instruction was executed
and the INTOSC source was already stable, the
IOFS bit will remain set. If the IRCF bits and INTSRC
are all clear, the INTOSC output will not be enabled, the
IOFS bit will remain clear and there will be no indication
of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
of TCSD following the wake event, the CPU begins executing
code being clocked by the INTOSC multiplexer.
The IDLEN and SCS bits are not affected by the wakeup.
The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
3.5 Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is
triggered by an interrupt, a Reset or a WDT time-out.
This section discusses the triggers that cause exits
from power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Section 3.2 “Run Modes”, Section 3.3
“Sleep Mode” and Section 3.4 “Idle Modes”).
3.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.
On all exits from Idle or Sleep modes by interrupt, code
execution branches to the interrupt vector if the GIE/
GIEH bit (INTCON<7>) is set. Otherwise, code execution
continues or resumes without branching (see
Section 9.0 “Interrupts”).
A fixed delay of interval TCSD following the wake event
is required when leaving Sleep and Idle modes. This
delay is required for the CPU to prepare for execution.
Instruction execution resumes on the first clock cycle
following this delay.
3.5.2 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending
on which power managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in an exit from the
power managed mode (see Section 3.2 “Run Modes”
and Section 3.3 “Sleep Mode”). If the device is executing
code (all Run modes), the time-out will result in
a WDT Reset (see Section 23.2 “Watchdog Timer
(WDT)”).
The WDT timer and postscaler are cleared by
executing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
device clock source.
3.5.3 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock becomes
ready. At that time, the OSTS bit is set and the device
begins executing code. If the internal oscillator block is
the new clock source, the IOFS bit is set instead.
The exit delay time from Reset to the start of code
execution depends on both the clock sources before
and after the wake-up and the type of oscillator if the
new clock source is the primary clock. Exit delays are
summarized in Table 3-2.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 23.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 23.4 “Fail-Safe Clock
Monitor”) is enabled, the device may begin execution
as soon as the Reset source has cleared. Execution is
clocked by the INTOSC multiplexer driven by the internal
oscillator block. Execution is clocked by the internal
oscillator block until either the primary clock becomes
ready or a power managed mode is entered before the
primary clock becomes ready; the primary clock is then
shut down.
PIC18F2420/2520/4420/4520
DS39631B-page 40 © 2007 Microchip Technology Inc.
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped and
• the primary clock source is not any of the LP, XT,
HS or HSPLL modes.
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
TCSD HSPLL (1) OSTS
EC, RC
INTOSC(2) IOFS
T1OSC or INTRC(1)
LP, XT, HS TOST(3)
HSPLL TOST + trc OSTS
(3)
EC, RC TCSD(1)
INTOSC(1) TIOBST(4) IOFS
INTOSC(2)
LP, XT, HS TOST(4)
HSPLL TOST + trc OSTS
(3)
EC, RC TCSD(1)
INTOSC(1) None IOFS
None
(Sleep mode)
LP, XT, HS TOST(3)
HSPLL TOST + trc OSTS
(3)
EC, RC TCSD(1)
INTOSC(1) TIOBST(4) IOFS
Note 1: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, INTOSC defaults to 1 MHz.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
4: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 41
PIC18F2420/2520/4420/4520
4.0 RESET
The PIC18F2420/2520/4420/4520 devices differentiate
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC(1)
POR Pulse
OST
10-bit Ripple Counter
PWRT
11-bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
Brown-out
Reset
BOREN
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
32 μs 65.5 ms
MCLRE
S
R Q
Chip_Reset
PIC18F2420/2520/4420/4520
DS39631B-page 42 Preliminary © 2007 Microchip Technology Inc.
REGISTER 4-1: RCON REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6 SBOREN: BOR Software Enable bit(1)
If BOREN1:BOREN0 = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN1:BOREN0 = 00, 10 or 11:
Bit is disabled and read as ‘0’.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset (must be set in software after
a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Set by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit(2)
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise, it is ‘0’.
2: The actual Reset value of POR is determined by the type of device Reset. See the
notes following this register and Section 4.6 “Reset State of Registers” for
additional information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been
detected so that subsequent Power-on Resets may be detected.
2: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming
that POR was set to ‘1’ by software immediately after POR).
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 43
PIC18F2420/2520/4420/4520
4.2 Master Clear (MCLR)
The MCLR pin provides a method for triggering an
external Reset of the device. A Reset is generated by
holding the pin low. These devices have a noise filter in
the MCLR Reset path which detects and ignores small
pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
In PIC18F2420/2520/4420/4520 devices, the MCLR
input can be disabled with the MCLRE configuration bit.
When MCLR is disabled, the pin becomes a digital
input. See Section 10.5 “PORTE, TRISE and LATE
Registers” for more information.
4.3 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip
whenever VDD rises above a certain threshold. This
allows the device to start in the initialized state when
VDD is adequate for operation.
To take advantage of the POR circuitry, tie the MCLR
pin through a resistor (1 kΩ to 10 kΩ) to VDD. This will
eliminate external RC components usually needed to
create a Power-on Reset delay. A minimum rise rate for
VDD is specified (parameter D004). For a slow rise
time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
POR events are captured by the POR bit (RCON<1>).
The state of the bit is set to ‘0’ whenever a POR occurs;
it does not change for any other Reset event. POR is
not reset to ‘1’ by any hardware event. To capture
multiple events, the user manually resets the bit to ‘1’
in software following any POR.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
D R
VDD
MCLR
PIC18FXXXX
VDD
PIC18F2420/2520/4420/4520
DS39631B-page 44 Preliminary © 2007 Microchip Technology Inc.
4.4 Brown-out Reset (BOR)
PIC18F2420/2520/4420/4520 devices implement a
BOR circuit that provides the user with a number of
configuration and power-saving options. The BOR is
controlled by the BORV1:BORV0 and
BOREN1:BOREN0 configuration bits. There are a total
of four BOR configurations which are summarized in
Table 4-1.
The BOR threshold is set by the BORV1:BORV0 bits. If
BOR is enabled (any values of BOREN1:BOREN0,
except ‘00’), any drop of VDD below VBOR (parameter
D005) for greater than TBOR (parameter 35) will reset
the device. A Reset may or may not occur if VDD falls
below VBOR for less than TBOR. The chip will remain in
Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once VDD rises above VBOR, the Power-up
Timer will execute the additional time delay.
BOR and the Power-on Timer (PWRT) are
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
4.4.1 SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be
enabled or disabled by the user in software. This is
done with the control bit, SBOREN (RCON<6>).
Setting SBOREN enables the BOR to function as
previously described. Clearing SBOREN disables the
BOR entirely. The SBOREN bit operates only in this
mode; otherwise it is read as ‘0’.
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change BOR configuration. It also allows the user to
tailor device power consumption in software by eliminating
the incremental current that the BOR consumes.
While the BOR current is typically very small, it may
have some impact in low-power applications.
4.4.2 DETECTING BOR
When BOR is enabled, the BOR bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any POR event. If BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a BOR event
has occurred.
4.4.3 DISABLING BOR IN SLEEP MODE
When BOREN1:BOREN0 = 10, the BOR remains
under hardware control and operates as previously
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
TABLE 4-1: BOR CONFIGURATIONS
Note: Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV1:BORV0 configuration bits. It
cannot be changed in software.
BOR Configuration Status of
SBOREN
(RCON<6>)
BOR Operation
BOREN1 BOREN0
0 0 Unavailable BOR disabled; must be enabled by reprogramming the configuration bits.
0 1 Available BOR enabled in software; operation controlled by SBOREN.
1 0 Unavailable BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
1 1 Unavailable BOR enabled in hardware; must be disabled by reprogramming the
configuration bits.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 45
PIC18F2420/2520/4420/4520
4.5 Device Reset Timers
PIC18F2420/2520/4420/4520 devices incorporate three
separate on-chip timers that help regulate the Power-on
Reset process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1 POWER-UP TIMER (PWRT)
The Power-up Timer (PWRT) of PIC18F2420/2520/
4420/4520 devices is an 11-bit counter which uses
the INTRC source as the clock input. This yields an
approximate time interval of 2048 x 32 μs = 65.6ms.
While the PWRT is counting, the device is held in
Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip to chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing the PWRTEN
configuration bit.
4.5.2 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power managed modes.
4.5.3 PLL LOCK TIME-OUT
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly different
from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
4.5.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows:
1. After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
2. Then, the OST is activated.
The total time-out will vary based on oscillator configuration
and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also
apply to devices operating in XT or LP modes. For
devices in RC mode and with the PWRT disabled, on
the other hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
PWRTEN = 0 PWRTEN = 1 Power Managed Mode
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) — —
RC, RCIO 66 ms(1) — —
INTIO1, INTIO2 66 ms(1) — —
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the PLL to lock.
PIC18F2420/2520/4420/4520
DS39631B-page 46 Preliminary © 2007 Microchip Technology Inc.
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 47
PIC18F2420/2520/4420/4520
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.
PIC18F2420/2520/4420/4520
DS39631B-page 48 Preliminary © 2007 Microchip Technology Inc.
4.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation.
Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations, as indicated in Table 4-3. These bits
are used in software to determine the nature of the
Reset.
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
TABLE 4-3: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION
FOR RCON REGISTER
Condition
Program
Counter
RCON Register STKPTR Register
SBOREN RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 1 1 1 1 0 0 0 0
RESET Instruction 0000h u(2) 0 u u u u u u
Brown-out Reset 0000h u(2) 1 1 1 u 0 u u
MCLR during Power Managed
Run Modes
0000h u(2) u 1 u u u u u
MCLR during Power Managed
Idle Modes and Sleep Mode
0000h u(2) u 1 0 u u u u
WDT Time-out during Full Power
or Power Managed Run Mode
0000h u(2) u 0 u u u u u
MCLR during Full Power
Execution
0000h u(2) u u u u u u u
Stack Full Reset (STVREN = 1) 0000h u(2) u u u u u 1 u
Stack Underflow Reset
(STVREN = 1)
0000h u(2) u u u u u u 1
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h u(2) u u u u u u 1
WDT Time-out during Power
Managed Idle or Sleep Modes
PC + 2 u(2) u 0 0 u u u u
Interrupt Exit from Power
Managed Modes
PC + 2(1) u(2) u u 0 u u u u
Legend: u = unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
2: Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 configuration bits = 01 and SBOREN = 1). Otherwise, the Reset state is ‘0’.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 49
PIC18F2420/2520/4420/4520
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 2420 2520 4420 4520 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 2420 2520 4420 4520 00-0 0000 uu-0 0000 uu-u uuuu(3)
PCLATU 2420 2520 4420 4520 ---0 0000 ---0 0000 ---u uuuu
PCLATH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
PCL 2420 2520 4420 4520 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu
TBLPTRH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
TABLAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
PRODH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 2420 2520 4420 4520 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 2420 2520 4420 4520 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 2420 2520 4420 4520 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 2420 2520 4420 4520 N/A N/A N/A
POSTINC0 2420 2520 4420 4520 N/A N/A N/A
POSTDEC0 2420 2520 4420 4520 N/A N/A N/A
PREINC0 2420 2520 4420 4520 N/A N/A N/A
PLUSW0 2420 2520 4420 4520 N/A N/A N/A
FSR0H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu
FSR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 2420 2520 4420 4520 N/A N/A N/A
POSTINC1 2420 2520 4420 4520 N/A N/A N/A
POSTDEC1 2420 2520 4420 4520 N/A N/A N/A
PREINC1 2420 2520 4420 4520 N/A N/A N/A
PLUSW1 2420 2520 4420 4520 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
PIC18F2420/2520/4420/4520
DS39631B-page 50 Preliminary © 2007 Microchip Technology Inc.
FSR1H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu
FSR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu
INDF2 2420 2520 4420 4520 N/A N/A N/A
POSTINC2 2420 2520 4420 4520 N/A N/A N/A
POSTDEC2 2420 2520 4420 4520 N/A N/A N/A
PREINC2 2420 2520 4420 4520 N/A N/A N/A
PLUSW2 2420 2520 4420 4520 N/A N/A N/A
FSR2H 2420 2520 4420 4520 ---- 0000 ---- 0000 ---- uuuu
FSR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 2420 2520 4420 4520 ---x xxxx ---u uuuu ---u uuuu
TMR0H 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
TMR0L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu
OSCCON 2420 2520 4420 4520 0100 q000 0100 q000 uuuu uuqu
HLVDCON 2420 2520 4420 4520 0-00 0101 0-00 0101 u-uu uuuu
WDTCON 2420 2520 4420 4520 ---- ---0 ---- ---0 ---- ---u
RCON(4) 2420 2520 4420 4520 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 2420 2520 4420 4520 0000 0000 u0uu uuuu uuuu uuuu
TMR2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
PR2 2420 2520 4420 4520 1111 1111 1111 1111 1111 1111
T2CON 2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu
SSPBUF 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
SSPCON1 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
SSPCON2 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 51
PIC18F2420/2520/4420/4520
ADRESH 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu
ADCON1 2420 2520 4420 4520 --00 0qqq --00 0qqq --uu uuuu
ADCON2 2420 2520 4420 4520 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON
2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu
CCPR2H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 2420 2520 4420 4520 --00 0000 --00 0000 --uu uuuu
BAUDCON 2420 2520 4420 4520 01-0 0-00 01-0 0-00 --uu uuuu
PWM1CON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
ECCP1AS
2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
2420 2520 4420 4520 0000 00-- 0000 00-- uuuu uu--
CVRCON 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
CMCON 2420 2520 4420 4520 0000 0111 0000 0111 uuuu uuuu
TMR3H 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 2420 2520 4420 4520 0000 0000 uuuu uuuu uuuu uuuu
SPBRGH 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
SPBRG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
RCREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
TXREG 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
TXSTA 2420 2520 4420 4520 0000 0010 0000 0010 uuuu uuuu
RCSTA 2420 2520 4420 4520 0000 000x 0000 000x uuuu uuuu
EEADR 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
EEDATA 2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
EECON2 2420 2520 4420 4520 0000 0000 0000 0000 0000 0000
EECON1 2420 2520 4420 4520 xx-0 x000 uu-0 u000 uu-0 u000
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
PIC18F2420/2520/4420/4520
DS39631B-page 52 Preliminary © 2007 Microchip Technology Inc.
IPR2 2420 2520 4420 4520 11-1 1111 11-1 1111 uu-u uuuu
PIR2 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu(1)
PIE2 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu
IPR1
2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu
2420 2520 4420 4520 -111 1111 -111 1111 -uuu uuuu
PIR1
2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu(1)
2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu(1)
PIE1
2420 2520 4420 4520 0000 0000 0000 0000 uuuu uuuu
2420 2520 4420 4520 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 2420 2520 4420 4520 00-0 0000 00-0 0000 uu-u uuuu
TRISE 2420 2520 4420 4520 0000 -111 0000 -111 uuuu -uuu
TRISD 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu
TRISC 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu
TRISB 2420 2520 4420 4520 1111 1111 1111 1111 uuuu uuuu
TRISA(5) 2420 2520 4420 4520 1111 1111(5) 1111 1111(5) uuuu uuuu(5)
LATE 2420 2520 4420 4520 ---- -xxx ---- -uuu ---- -uuu
LATD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 2420 2520 4420 4520 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)
PORTE 2420 2520 4420 4520 ---- xxxx ---- uuuu ---- uuuu
PORTD 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 2420 2520 4420 4520 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5) 2420 2520 4420 4520 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 53
PIC18F2420/2520/4420/4520
5.0 MEMORY ORGANIZATION
There are three types of memory in PIC18 Enhanced
microcontroller devices:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses; this allows for concurrent
access of the two memory spaces. The data
EEPROM, for practical purposes, can be regarded as
a peripheral device, since it is addressed and accessed
through a set of control registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 6.0
“Flash Program Memory”. Data EEPROM is
discussed separately in Section 7.0 “Data EEPROM
Memory”.
5.1 Program Memory Organization
PIC18 microcontrollers implement a 21-bit program
counter, which is capable of addressing a 2-Mbyte
program memory space. Accessing a location between
the upper boundary of the physically implemented
memory and the 2-Mbyte address will return all ‘0’s (a
NOP instruction).
The PIC18F2420 and PIC18F4420 each have
16 Kbytes of Flash memory and can store up to 8,192
single-word instructions. The PIC18F2520 and
PIC18F4520 each have 32 Kbytes of Flash memory
and can store up to 16,384 single-word instructions.
PIC18 devices have two interrupt vectors. The Reset
vector address is at 0000h and the interrupt vector
addresses are at 0008h and 0018h.
The program memory map for PIC18F2420/2520/
4420/4520 devices is shown in Figure 5-1.
FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR
PIC18F2420/2520/4420/4520 DEVICES
PC<20:0>
Stack Level 1
•
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
••
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
On-Chip
Program Memory
High Priority Interrupt Vector 0008h
User Memory Space
1FFFFFh
4000h
3FFFh
Read ‘0’
200000h
PIC18FX4X0
PIC18FX5X0
8000h
7FFFh
On-Chip
Program Memory
Read ‘0’
PIC18F2420/2520/4420/4520
DS39631B-page 54 Preliminary © 2007 Microchip Technology Inc.
5.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The
low byte, known as the PCL register, is both readable
and writable. The high byte, or PCH register, contains
the PC<15:8> bits; it is not directly readable or writable.
Updates to the PCH register are performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits; it is also not
directly readable or writable. Updates to the PCU
register are performed through the PCLATU register.
The contents of PCLATH and PCLATU are transferred
to the program counter by any operation that writes
PCL. Similarly, the upper two bytes of the program
counter are transferred to PCLATH and PCLATU by an
operation that reads PCL. This is useful for computed
offsets to the PC (see Section 5.1.4.1 “Computed
GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to
a value of ‘0’. The PC increments by 2 to address
sequential instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
5.1.2 RETURN ADDRESS STACK
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction
is executed or an interrupt is Acknowledged. The
PC value is pulled off the stack on a RETURN, RETLW
or a RETFIE instruction. PCLATU and PCLATH are not
affected by any of the RETURN or CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, STKPTR. The stack space is not
part of either program or data space. The stack pointer
is readable and writable and the address on the top of
the stack is readable and writable through the top-ofstack
Special File Registers. Data can also be pushed
to, or popped from the stack, using these registers.
A CALL type instruction causes a push onto the stack;
the stack pointer is first incremented and the location
pointed to by the stack pointer is written with the
contents of the PC (already pointing to the instruction
following the CALL). A RETURN type instruction causes
a pop from the stack; the contents of the location
pointed to by the STKPTR are transferred to the PC
and then the stack pointer is decremented.
The stack pointer is initialized to ‘00000’ after all
Resets. There is no RAM associated with the location
corresponding to a stack pointer value of ‘00000’; this
is only a Reset value. Status bits indicate if the stack is
full or has overflowed or has underflowed.
5.1.2.1 Top-of-Stack Access
Only the top of the return address stack (TOS) is
readable and writable. A set of three registers,
TOSU:TOSH:TOSL, hold the contents of the stack location
pointed to by the STKPTR register (Figure 5-2). This
allows users to implement a software stack if necessary.
After a CALL, RCALL or interrupt, the software can read
the pushed value by reading the TOSU:TOSH:TOSL
registers. These values can be placed on a user defined
software stack. At return time, the software can return
these values to TOSU:TOSH:TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
FIGURE 5-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack <20:0>
Top-of-Stack
000D58h
TOSU TOSH TOSL
00h 1Ah 34h
STKPTR<4:0>
Top-of-Stack Registers Stack Pointer
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 55
PIC18F2420/2520/4420/4520
5.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 5-1) contains the stack
pointer value, the STKFUL (stack full) status bit and the
STKUNF (stack underflow) status bits. The value of the
stack pointer can be 0 through 31. The stack pointer
increments before values are pushed onto the stack
and decrements after values are popped off the stack.
On Reset, the stack pointer value will be zero. The user
may read and write the stack pointer value. This feature
can be used by a Real-Time Operating System (RTOS)
for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVREN (Stack Overflow
Reset Enable) configuration bit. (Refer to
Section 23.1 “Configuration Bits” for a description of
the device configuration bits.) If STVREN is set
(default), the 31st push will push the (PC + 2) value
onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the stack
pointer will be set to zero.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at zero. The STKUNF bit will remain
set until cleared by software or until a POR occurs.
5.1.2.3 PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the
ability to push values onto the stack and pull values off
the stack without disturbing normal program execution
is a desirable feature. The PIC18 instruction set
includes two instructions, PUSH and POP, that permit
the TOS to be manipulated under software control.
TOSU, TOSH and TOSL can be modified to place data
or a return address on the stack.
The PUSH instruction places the current PC value onto
the stack. This increments the stack pointer and loads
the current PC value onto the stack.
The POP instruction discards the current TOS by decrementing
the stack pointer. The previous value pushed
onto the stack then becomes the TOS value.
REGISTER 5-1: STKPTR REGISTER
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
bit 7 STKFUL: Stack Full Flag bit(1)
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6 STKUNF: Stack Underflow Flag bit(1)
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 56 Preliminary © 2007 Microchip Technology Inc.
5.1.2.4 Stack Full and Underflow Resets
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.3 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG
and BSR registers, to provide a “fast return” option for
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All interrupt
sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no interrupts
are used, the fast register stack can be used to
restore the Status, WREG and BSR registers at the end
of a subroutine call. To use the fast register stack for a
subroutine call, a CALL label, FAST instruction must
be executed to save the Status, WREG and BSR
registers to the fast register stack. A RETURN, FAST
instruction is then executed to restore these registers
from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
5.1.4 LOOK-UP TABLES IN PROGRAM
MEMORY
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.4.1 Computed GOTO
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW nn instructions. The
W register is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW nn
instructions that returns the value ‘nn’ to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-2: COMPUTED GOTO USING
AN OFFSET VALUE
5.1.4.2 Table Reads and Table Writes
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per program
word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to or from program memory one
byte at a time.
Table read and table write operations are discussed
further in Section 6.1 “Table Reads and Table
Writes”.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
••
SUB1 ••
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
MOVF OFFSET, W
CALL TABLE
ORG nn00h
TABLE ADDWF PCL
RETLW nnh
RETLW nnh
RETLW nnh
.
.
.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 57
PIC18F2420/2520/4420/4520
5.2 PIC18 Instruction Cycle
5.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an internal
or external source, is internally divided by four to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the program counter is
incremented on every Q1; the instruction is fetched
from the program memory and latched into the instruction
register during Q4. The instruction is decoded and
executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 5-3.
5.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the pipelining,
each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 5-3).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-3: CLOCK/INSTRUCTION CYCLE
EXAMPLE 5-3: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
PIC18F2420/2520/4420/4520
DS39631B-page 58 Preliminary © 2007 Microchip Technology Inc.
5.2.3 INSTRUCTIONS IN PROGRAM
MEMORY
The program memory is addressed in bytes. Instructions
are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSb = 0). To maintain alignment
with instruction boundaries, the PC increments in steps
of 2 and the LSb will always read ‘0’ (see Section 5.1.1
“Program Counter”).
Figure 5-4 shows an example of how instruction words
are stored in the program memory.
The CALL and GOTO instructions have the absolute program
memory address embedded into the instruction.
Since instructions are always stored on word boundaries,
the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 5-4 shows how the
instruction GOTO 0006h is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner. The
offset value stored in a branch instruction represents the
number of single-word instructions that the PC will be
offset by. Section 24.0 “Instruction Set Summary”
provides further details of the instruction set.
FIGURE 5-4: INSTRUCTIONS IN PROGRAM MEMORY
5.2.4 TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word
instructions: CALL, MOVFF, GOTO and LSFR. In all
cases, the second word of the instructions always has
‘1111’ as its four Most Significant bits; the other 12 bits
are literal data, usually a data memory address.
The use of ‘1111’ in the 4 MSbs of an instruction specifies
a special form of NOP. If the instruction is executed
in proper sequence – immediately after the first word –
the data in the second word is accessed and used by
the instruction sequence. If the first word is skipped for
some reason and the second word is executed by itself,
a NOP is executed instead. This is necessary for cases
when the two-word instruction is preceded by a conditional
instruction that changes the PC. Example 5-4
shows how this works.
EXAMPLE 5-4: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1 LSB = 0 ↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 0006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
Note: See Section 5.6 “PIC18 Instruction
Execution and the Extended Instruction
Set” for information on two-word
instructions in the extended instruction set.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 59
PIC18F2420/2520/4420/4520
5.3 Data Memory Organization
The data memory in PIC18 devices is implemented as
static RAM. Each register in the data memory has a
12-bit address, allowing up to 4096 bytes of data
memory. The memory space is divided into as many as
16 banks that contain 256 bytes each; PIC18F2420/
2520/4420/4520 devices implement all 16 banks.
Figure 5-5 shows the data memory organization for the
PIC18F2420/2520/4420/4520 devices.
The data memory contains Special Function Registers
(SFRs) and General Purpose Registers (GPRs). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratchpad operations in the user’s
application. Any read of an unimplemented location will
read as ‘0’s.
The instruction set and architecture allow operations
across all banks. The entire data memory may be
accessed by Direct, Indirect or Indexed Addressing
modes. Addressing modes are discussed later in this
subsection.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle, PIC18
devices implement an Access Bank. This is a 256-byte
memory space that provides fast access to SFRs and
the lower portion of GPR Bank 0 without using the
BSR. Section 5.3.2 “Access Bank” provides a
detailed description of the Access RAM.
5.3.1 BANK SELECT REGISTER (BSR)
Large areas of data memory require an efficient
addressing scheme to make rapid access to any
address possible. Ideally, this means that an entire
address does not need to be provided for each read or
write operation. For PIC18 devices, this is accomplished
with a RAM banking scheme. This divides the
memory space into 16 contiguous banks of 256 bytes.
Depending on the instruction, each location can be
addressed directly by its full 12-bit address, or an 8-bit
low-order address and a 4-bit bank pointer.
Most instructions in the PIC18 instruction set make use
of the bank pointer, known as the Bank Select Register
(BSR). This SFR holds the 4 Most Significant bits of a
location’s address; the instruction itself includes the
8 Least Significant bits. Only the four lower bits of the
BSR are implemented (BSR3:BSR0). The upper four
bits are unused; they will always read ‘0’ and cannot be
written to. The BSR can be loaded directly by using the
MOVLB instruction.
The value of the BSR indicates the bank in data
memory; the 8 bits in the instruction show the location
in the bank and can be thought of as an offset from the
bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is
shown in Figure 5-7.
Since up to 16 registers may share the same low-order
address, the user must always be careful to ensure that
the proper bank is selected before performing a data
read or write. For example, writing what should be
program data to an 8-bit address of F9h while the BSR
is 0Fh will end up resetting the program counter.
While any bank can be selected, only those banks that
are actually implemented can be read or written to.
Writes to unimplemented banks are ignored, while
reads from unimplemented banks will return ‘0’s. Even
so, the Status register will still be affected as if the
operation was successful. The data memory map in
Figure 5-5 indicates which banks are implemented.
In the core PIC18 instruction set, only the MOVFF
instruction fully specifies the 12-bit address of the
source and target registers. This instruction ignores the
BSR completely when it executes. All other instructions
include only the low-order address as an operand and
must use either the BSR or the Access Bank to locate
their target registers.
Note: The operation of some aspects of data
memory are changed when the PIC18
extended instruction set is enabled. See
Section 5.5 “Data Memory and the
Extended Instruction Set” for more
information.
PIC18F2420/2520/4420/4520
DS39631B-page 60 Preliminary © 2007 Microchip Technology Inc.
FIGURE 5-5: DATA MEMORY MAP FOR PIC18F2420/4420 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 128 bytes are
general purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
F7Fh
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 61
PIC18F2420/2520/4420/4520
FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2520/4520 DEVICES
Bank 0
Bank 1
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 0001
= 1111
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When ‘a’ = 0:
The BSR is ignored and the
Access Bank is used.
The first 128 bytes are
general purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When ‘a’ = 1:
The BSR specifies the Bank
used by the instruction.
F7Fh
F00h
EFFh
1FFh
100h
0FFh
Access RAM 000h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Access RAM High
Access RAM Low
Bank 2
= 0110
= 0010
(SFRs)
2FFh
200h
3FFh
300h
4FFh
400h
5FFh
500h
6FFh
600h
7FFh
700h
8FFh
800h
9FFh
900h
AFFh
A00h
BFFh
B00h
CFFh
C00h
DFFh
D00h
E00h
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
Bank 10
Bank 11
Bank 12
Bank 13
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
FFh
00h
= 0011
= 0100
= 0101
= 0111
= 1000
= 1001
= 1010
= 1011
= 1100
= 1101
= 1110
Unused
Read 00h
Unused
GPR
GPR
GPR
PIC18F2420/2520/4420/4520
DS39631B-page 62 Preliminary © 2007 Microchip Technology Inc.
FIGURE 5-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
5.3.2 ACCESS BANK
While the use of the BSR with an embedded 8-bit
address allows users to address the entire range of
data memory, it also means that the user must always
ensure that the correct bank is selected. Otherwise,
data may be read from or written to the wrong location.
This can be disastrous if a GPR is the intended target
of an operation, but an SFR is written to instead.
Verifying and/or changing the BSR for each read or
write to data memory can become very inefficient.
To streamline access for the most commonly used data
memory locations, the data memory is configured with
an Access Bank, which allows users to access a
mapped block of memory without specifying a BSR.
The Access Bank consists of the first 128 bytes of
memory (00h-7Fh) in Bank 0 and the last 128 bytes of
memory (80h-FFh) in Block 15. The lower half is known
as the “Access RAM” and is composed of GPRs. This
upper half is also where the device’s SFRs are
mapped. These two areas are mapped contiguously in
the Access Bank and can be addressed in a linear
fashion by an 8-bit address (Figure 5-5).
The Access Bank is used by core PIC18 instructions
that include the Access RAM bit (the ‘a’ parameter in
the instruction). When ‘a’ is equal to ‘1’, the instruction
uses the BSR and the 8-bit address included in the
opcode for the data memory address. When ‘a’ is ‘0’,
however, the instruction is forced to use the Access
Bank address map; the current value of the BSR is
ignored entirely.
Using this “forced” addressing allows the instruction to
operate on a data address in a single cycle, without
updating the BSR first. For 8-bit addresses of 80h and
above, this means that users can evaluate and operate
on SFRs more efficiently. The Access RAM below 80h
is a good place for data values that the user might need
to access rapidly, such as immediate computational
results or common program variables. Access RAM
also allows for faster and more code efficient context
saving and switching of variables.
The mapping of the Access Bank is slightly different
when the extended instruction set is enabled (XINST
configuration bit = 1). This is discussed in more detail
in Section 5.5.3 “Mapping the Access Bank in
Indexed Literal Offset Mode”.
5.3.3 GENERAL PURPOSE REGISTER
FILE
PIC18 devices may have banked memory in the GPR
area. This is data RAM, which is available for use by all
instructions. GPRs start at the bottom of Bank 0
(address 000h) and grow upwards towards the bottom of
the SFR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data Memory
Bank Select(2)
7 0
From Opcode(2)
0 0 0 0
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
Bank 3
through
Bank 13
0 0 1 1 1 1 1 1 1 1 1 1
7 0
BSR(1)
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 63
PIC18F2420/2520/4420/4520
5.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those associated
with the “core” device functionality (ALU, Resets
and interrupts) and those related to the peripheral functions.
The reset and interrupt registers are described in
their respective chapters, while the ALU’s Status register
is described later in this section. Registers related to
the operation of a peripheral feature are described in
the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F2420/2520/4420/4520 DEVICES
Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(1) FBFh CCPR1H F9Fh IPR1
FFEh TOSH FDEh POSTINC2(1) FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2(1) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2(1) FBCh CCPR2H F9Ch —(2)
FFBh PCLATU FDBh PLUSW2(1) FBBh CCPR2L F9Bh OSCTUNE
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —(2)
FF9h PCL FD9h FSR2L FB9h —(2) F99h —(2)
FF8h TBLPTRU FD8h STATUS FB8h BAUDCON F98h —(2)
FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON(3) F97h —(2)
FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS(3) F96h TRISE(3)
FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD(3)
FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h HLVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —(2)
FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —(2)
FEFh INDF0(1) FCFh TMR1H FAFh SPBRG F8Fh —(2)
FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG F8Eh —(2)
FEDh POSTDEC0(1) FCDh T1CON FADh TXREG F8Dh LATE(3)
FECh PREINC0(1) FCCh TMR2 FACh TXSTA F8Ch LATD(3)
FEBh PLUSW0(1) FCBh PR2 FABh RCSTA F8Bh LATC
FEAh FSR0H FCAh T2CON FAAh —(2) F8Ah LATB
FE9h FSR0L FC9h SSPBUF FA9h EEADR F89h LATA
FE8h WREG FC8h SSPADD FA8h EEDATA F88h —(2)
FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2(1) F87h —(2)
FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h —(2)
FE5h POSTDEC1(1) FC5h SSPCON2 FA5h —(2) F85h —(2)
FE4h PREINC1(1) FC4h ADRESH FA4h —(2) F84h PORTE(3)
FE3h PLUSW1(1) FC3h ADRESL FA3h —(2) F83h PORTD(3)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 28-pin devices.
PIC18F2420/2520/4420/4520
DS39631B-page 64 Preliminary © 2007 Microchip Technology Inc.
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 49, 54
TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 49, 54
TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 49, 54
STKPTR STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 00-0 0000 49, 55
PCLATU — — — Holding Register for PC<20:16> ---0 0000 49, 54
PCLATH Holding Register for PC<15:8> 0000 0000 49, 54
PCL PC, Low Byte (PC<7:0>) 0000 0000 49, 54
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 49, 76
TBLPTRH Program Memory Table Pointer, High Byte (TBLPTR<15:8>) 0000 0000 49, 76
TBLPTRL Program Memory Table Pointer, Low Byte (TBLPTR<7:0>) 0000 0000 49, 76
TABLAT Program Memory Table Latch 0000 0000 49, 76
PRODH Product Register, High Byte xxxx xxxx 49, 89
PRODL Product Register, Low Byte xxxx xxxx 49, 89
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 49, 93
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 49, 94
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 49, 95
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 69
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 69
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 69
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 69
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 49, 69
FSR0H — — — — Indirect Data Memory Address Pointer 0, High Byte ---- 0000 49, 69
FSR0L Indirect Data Memory Address Pointer 0, Low Byte xxxx xxxx 49, 69
WREG Working Register xxxx xxxx 49
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 69
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 69
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 69
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 69
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 49, 69
FSR1H — — — — Indirect Data Memory Address Pointer 1, High Byte ---- 0000 50, 69
FSR1L Indirect Data Memory Address Pointer 1, Low Byte xxxx xxxx 50, 69
BSR — — — — Bank Select Register ---- 0000 50, 59
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 69
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 69
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 69
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 69
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 50, 69
FSR2H — — — — Indirect Data Memory Address Pointer 2, High Byte ---- 0000 50, 69
FSR2L Indirect Data Memory Address Pointer 2, Low Byte xxxx xxxx 50, 69
STATUS — — — N OV Z DC C ---x xxxx 50, 67
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 65
PIC18F2420/2520/4420/4520
TMR0H Timer0 Register, High Byte 0000 0000 50, 125
TMR0L Timer0 Register, Low Byte xxxx xxxx 50, 125
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 50, 123
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 30, 50
HLVDCON VDIRMAG — IRVST HLVDEN HLVDL3 HLVDL2 HLVDL1 HLVDL0 0-00 0101 50, 245
WDTCON — — — — — — — SWDTEN --- ---0 50, 259
RCON IPEN SBOREN(1) — RI TO PD POR BOR 0q-1 11q0 42, 48,
102
TMR1H Timer1 Register, High Byte xxxx xxxx 50, 131
TMR1L Timer1 Register, Low Bytes xxxx xxxx 50, 131
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 50, 127
TMR2 Timer2 Register 0000 0000 50, 134
PR2 Timer2 Period Register 1111 1111 50, 134
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 133
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 50, 169,
170
SSPADD SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 50, 170
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 50, 162,
171
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 50, 163,
172
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 50, 173
ADRESH A/D Result Register, High Byte xxxx xxxx 51, 232
ADRESL A/D Result Register, Low Byte xxxx xxxx 51, 232
ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 51, 223
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0qqq 51, 224
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 51, 225
CCPR1H Capture/Compare/PWM Register 1, High Byte xxxx xxxx 51, 140
CCPR1L Capture/Compare/PWM Register 1, Low Byte xxxx xxxx 51, 140
CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 51, 139,
147
CCPR2H Capture/Compare/PWM Register 2, High Byte xxxx xxxx 51, 140
CCPR2L Capture/Compare/PWM Register 2, Low Byte xxxx xxxx 51, 140
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 51, 139
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 51, 204
PWM1CON PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 0000 0000 51, 156
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 0000 0000 51, 157
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 51, 239
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 51, 233
TMR3H Timer3 Register, High Byte xxxx xxxx 51, 137
TMR3L Timer3 Register, Low Byte xxxx xxxx 51, 137
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 51, 135
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
PIC18F2420/2520/4420/4520
DS39631B-page 66 Preliminary © 2007 Microchip Technology Inc.
SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 51, 206
SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 51, 206
RCREG EUSART Receive Register 0000 0000 51, 213
TXREG EUSART Transmit Register 0000 0000 51, 211
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 51, 202
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 51, 203
EEADR EEPROM Address Register 0000 0000 51, 74, 83
EEDATA EEPROM Data Register 0000 0000 51, 74, 83
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 51, 74, 83
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 51, 75, 84
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 11-1 1111 52, 101
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 00-0 0000 52, 97
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 00-0 0000 52, 99
IPR1 PSPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 52, 100
PIR1 PSPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 52, 96
PIE1 PSPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 52, 98
OSCTUNE INTSRC PLLEN(3) — TUN4 TUN3 TUN2 TUN1 TUN0 0q-0 0000 27, 52
TRISE(2) IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 52, 118
TRISD(2) PORTD Data Direction Control Register 1111 1111 52, 114
TRISC PORTC Data Direction Control Register 1111 1111 52, 111
TRISB PORTB Data Direction Control Register 1111 1111 52, 108
TRISA TRISA7(5) TRISA6(5) Data Direction Control Register for PORTA 1111 1111 52, 105
LATE(2) — — — — — PORTE Data Latch Register
(Read and Write to Data Latch)
---- -xxx 52, 117
LATD(2) PORTD Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 114
LATC PORTC Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 111
LATB PORTB Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 108
LATA LATA7(5) LATA6(5) PORTA Data Latch Register (Read and Write to Data Latch) xxxx xxxx 52, 105
PORTE — — — — RE3(4) RE2(2) RE1(2) RE0(2) ---- xxxx 52, 117
PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 52, 114
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 52, 111
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 52, 108
PORTA RA7(5) RA6(5) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 52, 105
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2420/2520/4420/4520) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
2: These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: The RE3 bit is only available when Master Clear Reset is disabled (MCLRE configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
5: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 67
PIC18F2420/2520/4420/4520
5.3.5 STATUS REGISTER
The Status register, shown in Register 5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any instruction.
If the Status register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results of the
instruction are not written; instead, the Status register
is updated according to the instruction performed.
Therefore, the result of an instruction with the Status
register as its destination may be different than
intended. As an example, CLRF STATUS will set the Z
bit and leave the remaining status bits unchanged
(‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the Status
register, because these instructions do not affect the Z,
C, DC, OV or N bits in the Status register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 24-2 and
Table 24-3.
REGISTER 5-2: STATUS REGISTER
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC C
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7 of the result) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 68 Preliminary © 2007 Microchip Technology Inc.
5.4 Data Addressing Modes
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST configuration bit = 1). Its operation is
discussed in greater detail in Section 5.5.1 “Indexed
Addressing with Literal Offset”.
5.4.1 INHERENT AND LITERAL
ADDRESSING
Many PIC18 control instructions do not need any argument
at all; they either perform an operation that globally
affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byteoriented
instructions use some version of direct
addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its original
contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
5.4.3 INDIRECT ADDRESSING
Indirect addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Registers, they can also be directly manipulated
under program control. This makes FSRs very
useful in implementing data structures, such as tables
and arrays in data memory.
The registers for indirect addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
Note: The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.5 “Data Memory
and the Extended Instruction Set” for
more information.
LFSR FSR0, 100h ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
BRA NEXT ; NO, clear next
CONTINUE ; YES, continue
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 69
PIC18F2420/2520/4420/4520
5.4.3.1 FSR Registers and the INDF
Operand
At the core of indirect addressing are three sets of registers:
FSR0, FSR1 and FSR2. Each represents a pair
of 8-bit registers, FSRnH and FSRnL. The four upper
bits of the FSRnH register are not used so each FSR
pair holds a 12-bit value. This represents a value that
can address the entire range of the data memory in a
linear fashion. The FSR register pairs, then, serve as
pointers to data memory locations.
Indirect addressing is accomplished with a set of
Indirect File Operands, INDF0 through INDF2. These
can be thought of as “virtual” registers: they are
mapped in the SFR space but are not physically implemented.
Reading or writing to a particular INDF register
actually accesses its corresponding FSR register pair.
A read from INDF1, for example, reads the data at the
address indicated by FSR1H:FSR1L. Instructions that
use the INDF registers as operands actually use the
contents of their corresponding FSR as a pointer to the
instruction’s target. The INDF operand is just a
convenient way of using the pointer.
Because indirect addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
5.4.3.2 FSR Registers and POSTINC,
POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair
also has four additional indirect operands. Like INDF,
these are “virtual” registers that cannot be indirectly
read or written to. Accessing these registers actually
accesses the associated FSR register pair, but also
performs a specific action on it stored value. They are:
• POSTDEC: accesses the FSR value, then
automatically decrements it by 1 afterwards
• POSTINC: accesses the FSR value, then
automatically increments it by 1 afterwards
• PREINC: increments the FSR value by 1, then
uses it in the operation
• PLUSW: adds the signed value of the W register
(range of -127 to 128) to that of the FSR and uses
the new value in the operation.
In this context, accessing an INDF register uses the
value in the FSR registers without changing them. Similarly,
accessing a PLUSW register gives the FSR value
offset by that in the W register; neither value is actually
changed in the operation. Accessing the other virtual
registers changes the value of the FSR registers.
Operations on the FSRs with POSTDEC, POSTINC
and PREINC affect the entire register pair; that is, rollovers
of the FSRnL register from FFh to 00h carry over
to the FSRnH register. On the other hand, results of
these operations do not change the value of any flags
in the Status register (e.g., Z, N, OV, etc.).
FIGURE 5-8: INDIRECT ADDRESSING
FSR1H:FSR1L
7 0
Data Memory
000h
100h
200h
300h
F00h
E00h
FFFh
Bank 0
Bank 1
Bank 2
Bank 14
Bank 15
Bank 3
through
Bank 13
ADDWF, INDF1, 1
7 0
Using an instruction with one of the
indirect addressing registers as the
operand....
...uses the 12-bit address stored in
the FSR pair associated with that
register....
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
ECCh. This means the contents of
location ECCh will be added to that
of the W register and stored back in
ECCh.
x x x x 1 1 1 0 1 1 0 0 1 1 0 0
PIC18F2420/2520/4420/4520
DS39631B-page 70 Preliminary © 2007 Microchip Technology Inc.
The PLUSW register can be used to implement a form
of indexed addressing in the data memory space. By
manipulating the value in the W register, users can
reach addresses that are fixed offsets from pointer
addresses. In some applications, this can be used to
implement some powerful program control structure,
such as software stacks, inside of data memory.
5.4.3.3 Operations by FSRs on FSRs
Indirect addressing operations that target other FSRs
or virtual registers represent special cases. For example,
using an FSR to point to one of the virtual registers
will not result in successful operations. As a specific
case, assume that FSR0H:FSR0L contains FE7h, the
address of INDF1. Attempts to read the value of the
INDF1 using INDF0 as an operand will return 00h.
Attempts to write to INDF1 using INDF0 as the operand
will result in a NOP.
On the other hand, using the virtual registers to write to
an FSR pair may not occur as planned. In these cases,
the value will be written to the FSR pair but without any
incrementing or decrementing. Thus, writing to INDF2
or POSTDEC2 will write the same value to the
FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the
SFR space, they can be manipulated through all direct
operations. Users should proceed cautiously when
working on these registers, particularly if their code
uses indirect addressing.
Similarly, operations by indirect addressing are generally
permitted on all other SFRs. Users should exercise
the appropriate caution that they do not inadvertently
change settings that might affect the operation of the
device.
5.5 Data Memory and the Extended
Instruction Set
Enabling the PIC18 extended instruction set (XINST
configuration bit = 1) significantly changes certain
aspects of data memory and its addressing. Specifically,
the use of the Access Bank for many of the core
PIC18 instructions is different; this is due to the introduction
of a new addressing mode for the data memory
space.
What does not change is just as important. The size of
the data memory space is unchanged, as well as its
linear addressing. The SFR map remains the same.
Core PIC18 instructions can still operate in both Direct
and Indirect Addressing mode; inherent and literal
instructions do not change at all. Indirect addressing
with FSR0 and FSR1 also remain unchanged.
5.5.1 INDEXED ADDRESSING WITH
LITERAL OFFSET
Enabling the PIC18 extended instruction set changes
the behavior of indirect addressing using the FSR2
register pair within Access RAM. Under the proper
conditions, instructions that use the Access Bank – that
is, most bit-oriented and byte-oriented instructions –
can invoke a form of indexed addressing using an
offset specified in the instruction. This special addressing
mode is known as Indexed Addressing with Literal
Offset, or Indexed Literal Offset mode.
When using the extended instruction set, this
addressing mode requires the following:
• The use of the Access Bank is forced (‘a’ = 0) and
• The file address argument is less than or equal to
5Fh.
Under these conditions, the file address of the instruction
is not interpreted as the lower byte of an address
(used with the BSR in direct addressing), or as an 8-bit
address in the Access Bank. Instead, the value is
interpreted as an offset value to an address pointer,
specified by FSR2. The offset and the contents of
FSR2 are added to obtain the target address of the
operation.
5.5.2 INSTRUCTIONS AFFECTED BY
INDEXED LITERAL OFFSET MODE
Any of the core PIC18 instructions that can use direct
addressing are potentially affected by the Indexed
Literal Offset Addressing mode. This includes all
byte-oriented and bit-oriented instructions, or almost
one-half of the standard PIC18 instruction set.
Instructions that only use Inherent or Literal Addressing
modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions
are not affected if they do not use the Access Bank
(Access RAM bit is ‘1’), or include a file address of 60h
or above. Instructions meeting these criteria will
continue to execute as before. A comparison of the different
possible addressing modes when the extended
instruction set is enabled in shown in Figure 5-9.
Those who desire to use byte-oriented or bit-oriented
instructions in the Indexed Literal Offset mode should
note the changes to assembler syntax for this mode.
This is described in more detail in Section 24.2.1
“Extended Instruction Syntax”.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 71
PIC18F2420/2520/4420/4520
FIGURE 5-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is interpreted
as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations 060h to 07Fh
(Bank 0) and F80h to FFFh
(Bank 15) of data memory.
Locations below 60h are not
available in this addressing
mode.
When ‘a’ = 0 and f ≤ 5Fh:
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
Note that in this mode, the
correct syntax is now:
ADDWF [k], d
where ‘k’ is the same as ‘f’.
When ‘a’ = 1 (all values of f):
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is interpreted
as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
000h
060h
100h
F00h
F80h
FFFh
Valid range
00h
60h
80h
FFh
Data Memory
Access RAM
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
000h
080h
100h
F00h
F80h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
FSR2H FSR2L
001001da ffffffff
001001da ffffffff
000h
080h
100h
F00h
F80h
FFFh
Data Memory
Bank 0
Bank 1
through
Bank 14
Bank 15
SFRs
for ‘f’
BSR
00000000
080h
PIC18F2420/2520/4420/4520
DS39631B-page 72 Preliminary © 2007 Microchip Technology Inc.
5.5.3 MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET MODE
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 5.3.2 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 5-10.
Remapping of the Access Bank applies only to operations
using the Indexed Literal Offset mode. Operations
that use the BSR (Access RAM bit is ‘1’) will continue
to use direct addressing as before.
5.6 PIC18 Instruction Execution and
the Extended Instruction Set
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 24.2 “Extended Instruction Set”.
FIGURE 5-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Data Memory
000h
100h
200h
F80h
F00h
FFFh
Bank 1
Bank 15
Bank 2
through
Bank 14
SFRs
05Fh
ADDWF f, d, a
FSR2H:FSR2L = 120h
Locations in the region
from the FSR2 pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to the bottom of the
Access RAM (000h-05Fh).
Locations in Bank 0 from
060h to 07Fh are mapped,
as usual, to the middle half
of the Access Bank.
Special File Registers at
F80h through FFFh are
mapped to 80h through
FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
Access Bank
00h
80h
FFh
7Fh
Bank 0
SFRs
Bank 1 “Window”
Bank 0
Bank 0
Window
Example Situation:
07Fh
120h
17Fh
5Fh
Bank 1
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 73
PIC18F2420/2520/4420/4520
6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 64 bytes at a time. Program memory is
erased in blocks of 64 bytes at a time. A bulk erase
operation may not be issued from user code.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and places it into the data RAM space.
Figure 6-1 shows the operation of a table read with
program memory and data RAM.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 6.5 “Writing
to Flash Program Memory”. Figure 6-2 shows the
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block can
start and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
FIGURE 6-1: TABLE READ OPERATION
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer register points to a byte in program memory.
Program Memory
(TBLPTR)
PIC18F2420/2520/4420/4520
DS39631B-page 74 Preliminary © 2007 Microchip Technology Inc.
FIGURE 6-2: TABLE WRITE OPERATION
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 6-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory write and erase sequences. Reading
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
The CFGS control bit determines if the access will be
to the configuration/calibration registers or to program
memory/data EEPROM memory. When set,
subsequent operations will operate on configuration
registers regardless of EEPGD (see Section 23.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 6.5 “Writing to Flash Program Memory”.
Holding Registers
Program Memory
Note: During normal operation, the WRERR is
read as ‘1’. This can indicate that a write
operation was prematurely terminated by
a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 75
PIC18F2420/2520/4420/4520
REGISTER 6-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0 = The write operation completed
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 76 Preliminary © 2007 Microchip Technology Inc.
6.2.2 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between program
memory and data RAM.
6.2.3 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) register addresses a byte
within the program memory. The TBLPTR is comprised
of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the device ID, the user ID and the configuration bits.
The Table Pointer register, TBLPTR, is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
6.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the TBLPTR
determine which byte is read from program memory
into TABLAT.
When a TBLWT is executed, the six LSbs of the Table
Pointer register (TBLPTR<5:0>) determine which of the
64 program memory holding registers is written to.
When the timed write to program memory begins (via
the WR bit), the 16 MSbs of the TBLPTR
(TBLPTR<21:6>) determine which program memory
block of 64 bytes is written to. For more detail, see
Section 6.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer register (TBLPTR<21:6>)
point to the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21 16 15 8 7 0
TABLE ERASE/WRITE TABLE WRITE
TABLE READ – TBLPTR<21:0>
TBLPTRU TBLPTRH TBLPTRL
TBLPTR<21:6> TBLPTR<5:0>
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 77
PIC18F2420/2520/4420/4520
6.3 Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
(Even Byte Address)
Program Memory
(Odd Byte Address)
TBLRD
TABLAT
TBLPTR = xxxxx1
FETCH
Instruction Register
(IR) Read Register
TBLPTR = xxxxx0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment
MOVF TABLAT, W ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment
MOVFW TABLAT, W ; get data
MOVF WORD_ODD
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DS39631B-page 78 Preliminary © 2007 Microchip Technology Inc.
6.4 Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the Flash array is not
supported.
When initiating an erase sequence from the microcontroller
itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash program
memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
6.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of row
being erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
Required MOVLW 55h
Sequence MOVWF EECON2 ; write 55h
MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 79
PIC18F2420/2520/4420/4520
6.5 Writing to Flash Program Memory
The minimum programming block is 32 words or
64 bytes. Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction may need to be executed 64
times for each programming operation. All of the table
write operations will essentially be short writes because
only the holding registers are written. At the end of
updating the 64 holding registers, the EECON1 register
must be written to in order to start the programming
operation with a long write.
The long write is necessary for programming the internal
Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the row erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the 64 bytes into the holding registers with
auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program memory;
• set WREN to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write 0AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Note: The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 64 holding registers
before executing a write operation.
TABLAT
TBLPTR = xxxxx0 TBLPTR = xxxxx1 TBLPTR = xxxx3F
Write Register
TBLPTR = xxxxx2
Program Memory
Holding Register Holding Register Holding Register Holding Register
8 8 8 8
Note: Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 bytes in
the holding register.
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DS39631B-page 80 Preliminary © 2007 Microchip Technology Inc.
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64 ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data
DECFSZ COUNTER ; done?
BRA READ_BLOCK ; repeat
MODIFY_WORD
MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start erase (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
TBLRD*- ; dummy read decrement
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
WRITE_BUFFER_BACK
MOVLW D’64 ; number of bytes in holding register
MOVWF COUNTER
WRITE_BYTE_TO_HREGS
MOVFF POSTINC0, WREG ; get low byte of buffer data
MOVWF TABLAT ; present data to table latch
TBLWT+* ; write data, perform a short write
; to internal TBLWT holding register.
DECFSZ COUNTER ; loop until buffers are full
BRA WRITE_WORD_TO_HREGS
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 81
PIC18F2420/2520/4420/4520
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed
if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
6.5.4 PROTECTION AGAINST
SPURIOUS WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of the
CPU” for more detail.
6.6 Flash Program Operation During
Code Protection
See Section 23.5 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
PROGRAM_MEMORY
BSF EECON1, EEPGD ; point to Flash program memory
BCF EECON1, CFGS ; access Flash program memory
BSF EECON1, WREN ; enable write to memory
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
Required MOVWF EECON2 ; write 55h
Sequence MOVLW 0AAh
MOVWF EECON2 ; write 0AAh
BSF EECON1, WR ; start program (CPU stall)
BSF INTCON, GIE ; re-enable interrupts
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49
TABLAT Program Memory Table Latch 49
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
EECON2 EEPROM Control Register 2 (not a physical register) 51
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PIC18F2420/2520/4420/4520
DS39631B-page 82 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 83
PIC18F2420/2520/4420/4520
7.0 DATA EEPROM MEMORY
The data EEPROM is a nonvolatile memory array, separate
from the data RAM and program memory, that is
used for long-term storage of program data. It is not
directly mapped in either the register file or program
memory space but is indirectly addressed through the
Special Function Registers (SFRs). The EEPROM is
readable and writable during normal operation over the
entire VDD range.
Five SFRs are used to read and write to the data
EEPROM as well as the program memory. They are:
• EECON1
• EECON2
• EEDATA
• EEADR
The data EEPROM allows byte read and write. When
interfacing to the data memory block, EEDATA holds
the 8-bit data for read/write and the EEADR register
holds the address of the EEPROM location being
accessed.
The EEPROM data memory is rated for high erase/write
cycle endurance. A byte write automatically erases the
location and writes the new data (erase-before-write).
The write time is controlled by an on-chip timer; it will
vary with voltage and temperature as well as from chip
to chip. Please refer to parameter D122 (Table 26-1 in
Section 26.0 “Electrical Characteristics”) for exact
limits.
7.1 EEADR Register
The EEADR register is used to address the data
EEPROM for read and write operations. The 8-bit
range of the register can address a memory range of
256 bytes (00h to FFh).
7.2 EECON1 and EECON2 Registers
Access to the data EEPROM is controlled by two
registers: EECON1 and EECON2. These are the same
registers which control access to the program memory
and are used in a similar manner for the data
EEPROM.
The EECON1 register (Register 7-1) is the control register
for data and program memory access. Control bit
EEPGD determines if the access will be to program or
data EEPROM memory. When clear, operations will
access the data EEPROM memory. When set, program
memory is accessed.
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
can be set but not cleared in software. It is only cleared
in hardware at the completion of the write operation.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
The EECON2 register is not a physical register. It is
used exclusively in the memory write and erase
sequences. Reading EECON2 will read all ‘0’s.
Note: During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely terminated
by a Reset, or a write operation was
attempted improperly.
Note: The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
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DS39631B-page 84 Preliminary © 2007 Microchip Technology Inc.
REGISTER 7-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration registers
0 = Access Flash program or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3 WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in
normal operation, or an improper write attempt)
0 = The write operation completed
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared.
This allows tracing of the error condition.
bit 2 WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
0 = Write cycle to the EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit W = Writable bit
S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 85
PIC18F2420/2520/4420/4520
7.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control
bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available on the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).
The basic process is shown in Example 7-1.
7.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data written
to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution
(i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag
bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
software.
7.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
EXAMPLE 7-1: DATA EEPROM READ
EXAMPLE 7-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BCF EECON1, CFGS ; Access EEPROM
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
; User code execution
BCF EECON1, WREN ; Disable writes on write complete (EEIF set)
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DS39631B-page 86 Preliminary © 2007 Microchip Technology Inc.
7.6 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
7.7 Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
7.8 Using the Data EEPROM
The data EEPROM is a high endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specification D124. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 87
PIC18F2420/2520/4420/4520
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
EEADR EEPROM Address Register 51
EEDATA EEPROM Data Register 51
EECON2 EEPROM Control Register 2 (not a physical register) 51
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 51
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
PIC18F2420/2520/4420/4520
DS39631B-page 88 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 89
PIC18F2420/2520/4420/4520
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
All PIC18 devices include an 8 x 8 hardware multiplier
as part of the ALU. The multiplier performs an unsigned
operation and yields a 16-bit result that is stored in the
product register pair, PRODH:PRODL. The multiplier’s
operation does not affect any flags in the Status
register.
Making multiplication a hardware operation allows it to
be completed in a single instruction cycle. This has the
advantages of higher computational throughput and
reduced code size for multiplication algorithms and
allows the PIC18 devices to be used in many applications
previously reserved for digital signal processors.
A comparison of various hardware and software
multiply operations, along with the savings in memory
and execution time, is shown in Table 8-1.
8.2 Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed
Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs
Hardware multiply 6 6 600 ns 2.4 μs 6 μs
16 x 16 unsigned
Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs
Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs
16 x 16 signed
Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs
Hardware multiply 35 40 4.0 μs 16.0 μs 40 μs
PIC18F2420/2520/4420/4520
DS39631B-page 90 Preliminary © 2007 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiplication. Equation 8-1 shows the
algorithm that is used. The 32-bit result is stored in four
registers (RES3:RES0).
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers
(RES3:RES0). To account for the sign bits of the arguments,
the MSb for each argument pair is tested and
the appropriate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 91
PIC18F2420/2520/4420/4520
9.0 INTERRUPTS
The PIC18F2420/2520/4420/4520 devices have multiple
interrupt sources and an interrupt priority feature
that allows most interrupt sources to be assigned a
high priority level or a low priority level. The high priority
interrupt vector is at 0008h and the low priority interrupt
vector is at 0018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files supplied
with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all interrupts
that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will vector
immediately to address 0008h or 0018h, depending
on the priority bit setting. Individual interrupts can be
disabled through their corresponding enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In Compatibility
mode, the interrupt priority bits for each source
have no effect. INTCON<6> is the PEIE bit, which
enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
0008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address (0008h
or 0018h). Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bits must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
PIC18F2420/2520/4420/4520
DS39631B-page 92 Preliminary © 2007 Microchip Technology Inc.
FIGURE 9-1: PIC18 INTERRUPT LOGIC
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
SSPIF
SSPIE
SSPIP
SSPIF
SSPIE
SSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIEH/GIE
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 93
PIC18F2420/2520/4420/4520
9.1 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1: INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note: A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 94 Preliminary © 2007 Microchip Technology Inc.
REGISTER 9-2: INTCON2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 95
PIC18F2420/2520/4420/4520
REGISTER 9-3: INTCON3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
PIC18F2420/2520/4420/4520
DS39631B-page 96 Preliminary © 2007 Microchip Technology Inc.
9.2 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request Flag registers (PIR1 and PIR2).
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the appropriate
interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 97
PIC18F2420/2520/4420/4520
REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF
bit 7 bit 0
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = Device clock operating
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit
1 = A high/low-voltage condition occurred (direction determined by
VDIRMAG bit, HLVDCON<7>)
0 = A high/low-voltage condition has not occurred
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not overflow
bit 0 CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 98 Preliminary © 2007 Microchip Technology Inc.
9.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Enable registers (PIE1 and PIE2). When IPEN = 0, the
PEIE bit must be set to enable any of these peripheral
interrupts.
REGISTER 9-6: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5 RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
bit 4 TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 99
PIC18F2420/2520/4420/4520
REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE
bit 7 bit 0
bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 100 Preliminary © 2007 Microchip Technology Inc.
9.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Priority registers (IPR1 and IPR2). Using the priority bits
requires that the Interrupt Priority Enable (IPEN) bit be
set.
REGISTER 9-8: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1 = High priority
0 = Low priority
Note 1: This bit is unimplemented on 28-pin devices and will read as ‘0’.
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: EUSART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 101
PIC18F2420/2520/4420/4520
REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP
bit 7 bit 0
bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 CMIP: Comparator Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 102 Preliminary © 2007 Microchip Technology Inc.
9.5 RCON Register
The RCON register contains flag bits which are used to
determine the cause of the last Reset or wake-up from
Idle or Sleep modes. RCON also contains the IPEN bit
which enables interrupt priorities.
The operation of the SBOREN bit and the Reset flag
bits is discussed in more detail in Section 4.1 “RCON
Register”.
REGISTER 9-10: RCON REGISTER
R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(1) R/W-0
IPEN SBOREN — RI TO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16XXX Compatibility mode)
bit 6 SBOREN: Software BOR Enable bit(1)
For details of bit operation, see Register 4-1.
Note 1: Actual Reset values are determined by device configuration and the nature of the
device Reset. See Register 4-1 for additional information.
bit 5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-1.
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-1.
bit 2 PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-1.
bit 1 POR: Power-on Reset Status bit
For details of bit operation, see Register 4-1.
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 103
PIC18F2420/2520/4420/4520
9.6 INTn Pin Interrupts
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge-triggered. If the corresponding
INTEDGx bit in the INTCON2 register is set (= 1), the
interrupt is triggered by a rising edge; if the bit is clear,
the trigger is on the falling edge. When a valid edge
appears on the RBx/INTx pin, the corresponding flag
bit, INTxF, is set. This interrupt can be disabled by
clearing the corresponding enable bit, INTxE. Flag bit,
INTxF, must be cleared in software in the Interrupt
Service Routine before re-enabling the interrupt.
All external interrupts (INT0, INT1 and INT2) can wakeup
the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
9.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh → 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh → 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority
bit, TMR0IP (INTCON2<2>). See Section 11.0
“Timer0 Module” for further details on the Timer0
module.
9.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
9.9 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 5.3 “Data
Memory Organization”), the user may need to save
the WREG, Status and BSR registers on entry to the
Interrupt Service Routine. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, Status
and BSR registers during an Interrupt Service Routine.
EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
PIC18F2420/2520/4420/4520
DS39631B-page 104 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 105
PIC18F2420/2520/4420/4520
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for read-modifywrite
operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 PORTA, TRISA and LATA Registers
PORTA is a 8-bit wide, bidirectional port. The corresponding
data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Data Latch (LATA) register is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in the configuration register (see
Section 23.1 “Configuration Bits” for details). When
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog VREF+ and VREF- inputs and the comparator
voltage reference output. The operation of pins
RA3:RA0 and RA5 as A/D converter inputs is selected
by clearing or setting the control bits in the ADCON1
register (A/D Control Register 1).
Pins RA0 through RA5 may also be used as comparator
inputs or outputs by setting the appropriate bits in the
CMCON register. To use RA3:RA0 as digital inputs, it is
also necessary to turn off the comparators.
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1: INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
D Q
CK
D Q
CK
EN
Q D
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to VDD and VSS.
Note: On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 07h ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVWF 07h ; Configure comparators
MOVWF CMCON ; for digital input
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
PIC18F2420/2520/4420/4520
DS39631B-page 106 Preliminary © 2007 Microchip Technology Inc.
TABLE 10-1: PORTA I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0 RA0 0 O DIG LATA<0> data output; not affected by analog input.
1 I TTL PORTA<0> data input; disabled when analog input enabled.
AN0 1 I ANA A/D input channel 0 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
RA1/AN1 RA1 0 O DIG LATA<1> data output; not affected by analog input.
1 I TTL PORTA<1> data input; disabled when analog input enabled.
AN1 1 I ANA A/D input channel 1 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF
RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1 I TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2 1 I ANA A/D input channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
VREF- 1 I ANA A/D and comparator voltage reference low input.
CVREF x O ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/VREF+ RA3 0 O DIG LATA<3> data output; not affected by analog input.
1 I TTL PORTA<3> data input; disabled when analog input enabled.
AN3 1 I ANA A/D input channel 3 and Comparator C1+ input. Default input
configuration on POR.
VREF+ 1 I ANA A/D and comparator voltage reference high input.
RA4/T0CKI/C1OUT RA4 0 O DIG LATA<4> data output.
1 I ST PORTA<4> data input; default configuration on POR.
T0CKI 1 I ST Timer0 clock input.
C1OUT 0 O DIG Comparator 1 output; takes priority over port data.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5 0 O DIG LATA<5> data output; not affected by analog input.
1 I TTL PORTA<5> data input; disabled when analog input enabled.
AN4 1 I ANA A/D input channel 4. Default configuration on POR.
SS 1 I TTL Slave select input for SSP (MSSP module).
HLVDIN 1 I ANA High/Low-Voltage Detect external trip point input.
C2OUT 0 O DIG Comparator 2 output; takes priority over port data.
OSC2/CLKO/RA6 RA6 0 O DIG LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1 I TTL PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
OSC2 x O ANA Main oscillator feedback output connection (XT, HS and LP modes).
CLKO x O DIG System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
OSC1/CLKI/RA7 RA7 0 O DIG LATA<7> data output. Disabled in external oscillator modes.
1 I TTL PORTA<7> data input. Disabled in external oscillator modes.
OSC1 x I ANA Main oscillator input connection.
CLKI x I ANA Main clock input connection.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 107
PIC18F2420/2520/4420/4520
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52
LATA LATA7(1) LATA6(1) PORTA Data Latch Register (Read and Write to Data Latch) 52
TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register 52
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.
PIC18F2420/2520/4420/4520
DS39631B-page 108 Preliminary © 2007 Microchip Technology Inc.
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corresponding
data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 10-2: INITIALIZING PORTB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed
by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB7:RB4) have an interrupton-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-
change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction).
b) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit,
CCP2MX, as the alternate peripheral pin for the CCP2
module (CCP2MX = 0).
Note: On a Power-on Reset, RB4:RB0 are
configured as analog inputs by default and
read as ‘0’; RB7:RB5 are configured as
digital inputs.
By programming the configuration bit,
PBADEN, RB4:RB0 will alternatively be
configured as digital inputs on POR.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0Fh ; Set RB<4:0> as
MOVWF ADCON1 ; digital I/O pins
; (required if config bit
; PBADEN is set)
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 109
PIC18F2420/2520/4420/4520
TABLE 10-3: PORTB I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/INT0/FLT0/
AN12
RB0 0 O DIG LATB<0> data output; not affected by analog input.
1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
INT0 1 I ST External interrupt 0 input.
FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
AN12 1 I ANA A/D input channel 12.(1)
RB1/INT1/AN10 RB1 0 O DIG LATB<1> data output; not affected by analog input.
1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
INT1 1 I ST External Interrupt 1 input.
AN10 1 I ANA A/D input channel 10.(1)
RB2/INT2/AN8 RB2 0 O DIG LATB<2> data output; not affected by analog input.
1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
INT2 1 I ST External interrupt 2 input.
AN8 1 I ANA A/D input channel 8.(1)
RB3/AN9/CCP2 RB3 0 O DIG LATB<3> data output; not affected by analog input.
1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
AN9 1 I ANA A/D input channel 9.(1)
CCP2(2) 0 O DIG CCP2 compare and PWM output.
1 I ST CCP2 capture input
RB4/KBI0/AN11 RB4 0 O DIG LATB<4> data output; not affected by analog input.
1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.(1)
KBI0 1 I TTL Interrupt on pin change.
AN11 1 I ANA A/D input channel 11.(1)
RB5/KBI1/PGM RB5 0 O DIG LATB<5> data output.
1 I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.
KBI1 1 I TTL Interrupt on pin change.
PGM x I ST Single-Supply Programming mode entry (ICSP™). Enabled by LVP
configuration bit; all other pin functions disabled.
RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output.
1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.
KBI2 1 I TTL Interrupt on pin change.
PGC x I ST Serial execution (ICSP) clock input for ICSP and ICD operation.(3)
RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output.
1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.
KBI3 1 I TTL Interrupt on pin change.
PGD x O DIG Serial execution data output for ICSP and ICD operation.(3)
x I ST Serial execution data input for ICSP and ICD operation.(3)
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Configuration on POR is determined by the PBADEN configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
2: Alternate assignment for CCP2 when the CCP2MX configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP or ICD are enabled.
PIC18F2420/2520/4420/4520
DS39631B-page 110 Preliminary © 2007 Microchip Technology Inc.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52
LATB PORTB Data Latch Register (Read and Write to Data Latch) 52
TRISB PORTB Data Direction Control Register 52
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 49
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 49
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 111
PIC18F2420/2520/4420/4520
10.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corresponding
data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). The pins have Schmitt Trigger input buffers.
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for additional information.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 10-3: INITIALIZING PORTC
Note: On a Power-on Reset, these pins are
configured as digital inputs.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
PIC18F2420/2520/4420/4520
DS39631B-page 112 Preliminary © 2007 Microchip Technology Inc.
TABLE 10-5: PORTC I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RC0/T1OSO/
T13CKI
RC0 0 O DIG LATC<0> data output.
1 I ST PORTC<0> data input.
T1OSO x O ANA Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T13CKI 1 I ST Timer1/Timer3 counter input.
RC1/T1OSI/CCP2 RC1 0 O DIG LATC<1> data output.
1 I ST PORTC<1> data input.
T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
CCP2(1) 0 O DIG CCP2 compare and PWM output; takes priority over port data.
1 I ST CCP2 capture input.
RC2/CCP1/P1A RC2 0 O DIG LATC<2> data output.
1 I ST PORTC<2> data input.
CCP1 0 O DIG ECCP1 compare or PWM output; takes priority over port data.
1 I ST ECCP1 capture input.
P1A(2) 0 O DIG ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK/SCL RC3 0 O DIG LATC<3> data output.
1 I ST PORTC<3> data input.
SCK 0 O DIG SPI™ clock output (MSSP module); takes priority over port data.
1 I ST SPI clock input (MSSP module).
SCL 0 O DIG I2 C™ clock output (MSSP module); takes priority over port data.
1 I I2C/SMB I2C clock input (MSSP module); input type depends on module setting.
RC4/SDI/SDA RC4 0 O DIG LATC<4> data output.
1 I ST PORTC<4> data input.
SDI 1 I ST SPI data input (MSSP module).
SDA 1 O DIG I2 C data output (MSSP module); takes priority over port data.
1 I I2C/SMB I2C data input (MSSP module); input type depends on module setting.
RC5/SDO RC5 0 O DIG LATC<5> data output.
1 I ST PORTC<5> data input.
SDO 0 O DIG SPI data output (MSSP module); takes priority over port data.
RC6/TX/CK RC6 0 O DIG LATC<6> data output.
1 I ST PORTC<6> data input.
TX 1 O DIG Asynchronous serial transmit data output (USART module);
takes priority over port data. User must configure as output.
CK 1 O DIG Synchronous serial clock output (USART module); takes priority
over port data.
1 I ST Synchronous serial clock input (USART module).
RC7/RX/DT RC7 0 O DIG LATC<7> data output.
1 I ST PORTC<7> data input.
RX 1 I ST Asynchronous serial receive data input (USART module).
DT 1 O DIG Synchronous serial data output (USART module); takes priority over
port data.
1 I ST Synchronous serial data input (USART module). User must
configure as an input.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignment for CCP2 when the CCP2MX configuration bit is set. Alternate assignment is RB3.
2: Enhanced PWM output is available only on PIC18F4520 devices.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 113
PIC18F2420/2520/4420/4520
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52
LATC PORTC Data Latch Register (Read and Write to Data Latch) 52
TRISC PORTC Data Direction Control Register 52
PIC18F2420/2520/4420/4520
DS39631B-page 114 Preliminary © 2007 Microchip Technology Inc.
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corresponding
data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt Trigger
input buffers. Each pin is individually configurable
as an input or output.
Three of the PORTD pins are multiplexed with outputs
P1B, P1C and P1D of the enhanced CCP module. The
operation of these additional PWM output pins is
covered in greater detail in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
PORTD can also be configured as an 8-bit wide microprocessor
port (Parallel Slave Port) by setting control
bit, PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.6 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4: INITIALIZING PORTD
Note: PORTD is only available on 40/44-pin
devices.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Note: When the enhanced PWM mode is used
with either dual or quad outputs, the PSP
functions of PORTD are automatically
disabled.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0CFh ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 115
PIC18F2420/2520/4420/4520
TABLE 10-7: PORTD I/O SUMMARY
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RD0/PSP0 RD0 0 O DIG LATD<0> data output.
1 I ST PORTD<0> data input.
PSP0 x O DIG PSP read data output (LATD<0>); takes priority over port data.
x I TTL PSP write data input.
RD1/PSP1 RD1 0 O DIG LATD<1> data output.
1 I ST PORTD<1> data input.
PSP1 x O DIG PSP read data output (LATD<1>); takes priority over port data.
x I TTL PSP write data input.
RD2/PSP2 RD2 0 O DIG LATD<2> data output.
1 I ST PORTD<2> data input.
PSP2 x O DIG PSP read data output (LATD<2>); takes priority over port data.
x I TTL PSP write data input.
RD3/PSP3 RD3 0 O DIG LATD<3> data output.
1 I ST PORTD<3> data input.
PSP3 x O DIG PSP read data output (LATD<3>); takes priority over port data.
x I TTL PSP write data input.
RD4/PSP4 RD4 0 O DIG LATD<4> data output.
1 I ST PORTD<4> data input.
PSP4 x O DIG PSP read data output (LATD<4>); takes priority over port data.
x I TTL PSP write data input.
RD5/PSP5/P1B RD5 0 O DIG LATD<5> data output.
1 I ST PORTD<5> data input.
PSP5 x O DIG PSP read data output (LATD<5>); takes priority over port data.
x I TTL PSP write data input.
P1B 0 O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD6/PSP6/P1C RD6 0 O DIG LATD<6> data output.
1 I ST PORTD<6> data input.
PSP6 x O DIG PSP read data output (LATD<6>); takes priority over port data.
x I TTL PSP write data input.
P1C 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RD7/PSP7/P1D RD7 0 O DIG LATD<7> data output.
1 I ST PORTD<7> data input.
PSP7 x O DIG PSP read data output (LATD<7>); takes priority over port data.
x I TTL PSP write data input.
P1D 0 O DIG ECCP1 Enhanced PWM output, channel D; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; x = Don’t care
(TRIS bit does not affect port direction or is overridden for this option).
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DS39631B-page 116 Preliminary © 2007 Microchip Technology Inc.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52
LATD PORTD Data Latch Register (Read and Write to Data Latch) 52
TRISD PORTD Data Direction Control Register 52
TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 117
PIC18F2420/2520/4420/4520
10.5 PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F2420/2520/4420/
4520 device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as an analog input, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input
only pin. Its operation is controlled by the MCLRE configuration
bit. When selected as a port pin (MCLRE = 0),
it functions as a digital input only pin; as such, it does not
have TRIS or LAT bits associated with its operation.
Otherwise, it functions as the device’s Master Clear
input. In either configuration, RE3 also functions as the
programming voltage input during programming.
EXAMPLE 10-5: INITIALIZING PORTE
10.5.1 PORTE IN 28-PIN DEVICES
For 28-pin devices, PORTE is only available when
Master Clear functionality is disabled (MCLRE = 0). In
these cases, PORTE is a single bit, input only port comprised
of RE3 only. The pin operates as previously
described.
Note: On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
Note: On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 0Ah ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 03h ; Value used to
; initialize data
; direction
MOVWF TRISE ; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
PIC18F2420/2520/4420/4520
DS39631B-page 118 Preliminary © 2007 Microchip Technology Inc.
REGISTER 10-1: TRISE REGISTER (40/44-PIN DEVICES ONLY)
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0
bit 7 bit 0
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General purpose I/O mode
bit 3 Unimplemented: Read as ‘0’
bit 2 TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1 TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0 TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 119
PIC18F2420/2520/4420/4520
TABLE 10-9: PORTE I/O SUMMARY
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/RD/AN5 RE0 0 O DIG LATE<0> data output; not affected by analog input.
1 I ST PORTE<0> data input; disabled when analog input enabled.
RD 1 I TTL PSP read enable input (PSP enabled).
AN5 1 I ANA A/D input channel 5; default input configuration on POR.
RE1/WR/AN6 RE1 0 O DIG LATE<1> data output; not affected by analog input.
1 I ST PORTE<1> data input; disabled when analog input enabled.
WR 1 I TTL PSP write enable input (PSP enabled).
AN6 1 I ANA A/D input channel 6; default input configuration on POR.
RE2/CS/AN7 RE2 0 O DIG LATE<2> data output; not affected by analog input.
1 I ST PORTE<2> data input; disabled when analog input enabled.
CS 1 I TTL PSP write enable input (PSP enabled).
AN7 1 I ANA A/D input channel 7; default input configuration on POR.
MCLR/VPP/RE3(1) MCLR — I ST External Master Clear input; enabled when MCLRE configuration bit is
set.
VPP — I ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
RE3 —(2) I ST PORTE<3> data input; enabled when MCLRE configuration bit is clear.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: RE3 is available on both 28-pin and 40/44-pin devices. All other PORTE pins are only implemented on 40/44-pin
devices.
2: RE3 does not have a corresponding TRIS bit to control data direction.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTE — — — — RE3(1,2) RE2 RE1 RE0 52
LATE(2) — — — — — LATE Data Output Register 52
TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
PIC18F2420/2520/4420/4520
DS39631B-page 120 Preliminary © 2007 Microchip Technology Inc.
10.6 Parallel Slave Port
In addition to its function as a general I/O port, PORTD
can also operate as an 8-bit wide Parallel Slave Port
(PSP) or microprocessor port. PSP operation is controlled
by the 4 upper bits of the TRISE register
(Register 10-1). Setting control bit, PSPMODE
(TRISE<4>), enables PSP operation as long as the
enhanced CCP module is not operating in dual output
or quad output PWM mode. In Slave mode, the port is
asynchronously readable and writable by the external
world.
The PSP can directly interface to an 8-bit microprocessor
data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
the control bit, PSPMODE, enables the PORTE I/O
pins to become control inputs for the microprocessor
port. When set, port pin RE0 is the RD input, RE1 is the
WR input and RE2 is the CS (Chip Select) input. For
this functionality, the corresponding data direction bits
of the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits,
PFCG3:PFCG0 (ADCON1<3:0>), must also be set to a
value in the range of ‘1010’ through ‘1111’.
A write to the PSP occurs when both the CS and WR
lines are first detected low and ends when either are
detected high. The PSPIF and IBF flag bits are both set
when the write ends.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The data in PORTD is read
out and the OBF bit is clear. If the user writes new data
to PORTD to set OBF, the data is immediately read out;
however, the OBF bit is not set.
When either the CS or RD lines are detected high, the
PORTD pins return to the input state and the PSPIF bit
is set. User applications should wait for PSPIF to be set
before servicing the PSP; when this happens, the IBF
and OBF bits can be polled and the appropriate action
taken.
The timing for the control signals in Write and Read
modes is shown in Figure 10-3 and Figure 10-4,
respectively.
FIGURE 10-2: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Note: The Parallel Slave Port is only available on
40/44-pin devices.
Data Bus
WR LATD
RDx pin
D Q
CK
EN
Q D
RD PORTD EN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
TTL
TTL
TTL
TTL
or
WR PORTD
RD LATD
Data Latch
Note: I/O pins have diode protection to VDD and VSS.
PORTE Pins
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 121
PIC18F2420/2520/4420/4520
FIGURE 10-3: PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52
LATD PORTD Data Latch Register (Read and Write to Data Latch) 52
TRISD PORTD Data Direction Control Register 52
PORTE — — — — RE3 RE2 RE1 RE0 52
LATE — — — — — LATE Data Output bits 52
TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 52
INTCON GIE/GIEH PEIE/GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
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DS39631B-page 122 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 123
PIC18F2420/2520/4420/4520
11.0 TIMER0 MODULE
The Timer0 module incorporates the following features:
• Software selectable operation as a timer or
counter in both 8-bit or 16-bit modes
• Readable and writable registers
• Dedicated 8-bit, software programmable
prescaler
• Selectable clock source (internal or external)
• Edge select for external clock
• Interrupt-on-overflow
The T0CON register (Register 11-1) controls all
aspects of the module’s operation, including the
prescale selection. It is both readable and writable.
A simplified block diagram of the Timer0 module in 8-bit
mode is shown in Figure 11-1. Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39631B-page 124 Preliminary © 2007 Microchip Technology Inc.
11.1 Timer0 Operation
Timer0 can operate as either a timer or a counter; the
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 11.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the Timer0 Source Edge
Select bit, T0SE (T0CON<4>); clearing this bit selects
the rising edge. Restrictions on the external clock input
are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
11.2 Timer0 Reads and Writes in
16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode; it is actually a buffered version of the real high
byte of Timer0 which is not directly readable nor writable
(refer to Figure 11-2). TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
PSA Internal Data Bus
T0PS2:T0PS0
Set
TMR0IF
on Overflow
3 8
8
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
1
0
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks
TMR0L
(2 TCY Delay)
Internal Data Bus
8
PSA
T0PS2:T0PS0
Set
TMR0IF
on Overflow
3
TMR0
TMR0H
High Byte
8
8
8
Read TMR0L
Write TMR0L
8
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 125
PIC18F2420/2520/4420/4520
11.3 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>) which determine the prescaler
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
11.3.1 SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register
overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clearing
the TMR0IE bit (INTCON<5>). Before re-enabling
the interrupt, the TMR0IF bit must be cleared in
software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
TMR0L Timer0 Register, Low Byte 50
TMR0H Timer0 Register, High Byte 50
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 50
TRISA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52
Legend: Shaded cells are not used by Timer0.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
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DS39631B-page 126 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 127
PIC18F2420/2520/4420/4520
12.0 TIMER1 MODULE
The Timer1 timer/counter module incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR1H
and TMR1L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Reset on CCP Special Event Trigger
• Device clock status flag (T1RUN)
A simplified block diagram of the Timer1 module is
shown in Figure 12-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 12-2.
The module incorporates its own low-power oscillator
to provide an additional clocking option. The Timer1
oscillator can also be used as a low-power clock source
for the microcontroller in power managed operation.
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications with only a minimal
addition of external components and code overhead.
Timer1 is controlled through the T1CON Control
register (Register 12-1). It also contains the Timer1
Oscillator Enable bit (T1OSCEN). Timer1 can be
enabled or disabled by setting or clearing control bit,
TMR1ON (T1CON<0>).
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of TImer1 in one 16-bit operation
0 = Enables register read/write of Timer1 in two 8-bit operations
bit 6 T1RUN: Timer1 System Clock Status bit
1 = Device clock is derived from Timer1 oscillator
0 = Device clock is derived from another source
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = Timer1 oscillator is enabled
0 = Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39631B-page 128 Preliminary © 2007 Microchip Technology Inc.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR3CS is cleared
(= 0), Timer1 increments on every internal instruction
cycle (Fosc/4). When the bit is set, Timer1 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
FIGURE 12-1: TIMER1 BLOCK DIAGRAM
FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
On/Off
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR1ON
TMR1L
Set
TMR1IF
on Overflow
TMR1
Clear TMR1 High Byte
(CCP Special Event Trigger)
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer1
Timer1 Clock Input
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR1L
Internal Data Bus
8
Set
TMR1IF
on Overflow
TMR1
TMR1H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR1ON
Clear TMR1
(CCP Special Event Trigger)
Timer1 Oscillator
On/Off
Timer1
Timer1 Clock Input
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 129
PIC18F2420/2520/4420/4520
12.2 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, has
become invalid due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
12.3 Timer1 Oscillator
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier output).
It is enabled by setting the Timer1 Oscillator Enable
bit, T1OSCEN (T1CON<3>). The oscillator is a lowpower
circuit rated for 32 kHz crystals. It will continue to
run during all power managed modes. The circuit for a
typical LP oscillator is shown in Figure 12-3. Table 12-1
shows the capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 12-3: EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
TABLE 12-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
12.3.1 USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power managed modes. By setting the clock select
bits, SCS1:SCS0 (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 3.0
“Power Managed Modes”.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(T1CON<6>), is set. This can be used to determine the
controller’s current clocking mode. It can also indicate
the clock source being currently used by the Fail-Safe
Clock Monitor. If the Clock Monitor is enabled and the
Timer1 oscillator fails while providing the clock, polling
the T1RUN bit will indicate whether the clock is being
provided by the Timer1 oscillator or another source.
12.3.2 LOW-POWER TIMER1 OPTION
The Timer1 oscillator can operate at two distinct levels
of power consumption based on device configuration.
When the LPT1OSC configuration bit is set, the Timer1
oscillator operates in a low-power mode. When
LPT1OSC is not set, Timer1 operates at a higher power
level. Power consumption for a particular mode is relatively
constant, regardless of the device’s operating
mode. The default Timer1 configuration is the higher
power mode.
As the low-power Timer1 mode tends to be more sensitive
to interference, high noise environments may
cause some oscillator instability. The low-power option
is, therefore, best suited for low noise applications
where power conservation is an important design
consideration.
Note: See the Notes with Table 12-1 for additional
information about capacitor selection.
C1
C2
XTAL
PIC18FXXXX
T1OSI
T1OSO
32.768 kHz
27 pF
27 pF
Osc Type Freq C1 C2
LP 32 kHz 27 pF(1) 27 pF(1)
Note 1: Microchip suggests these values as a
starting point in validating the oscillator
circuit.
2: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
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DS39631B-page 130 Preliminary © 2007 Microchip Technology Inc.
12.3.3 TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscillator
(such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 12-4: OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
12.4 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
12.5 Resetting Timer1 Using the CCP
Special Event Trigger
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Compare mode
(CCP1M3:CCP1M0 or CCP2M3:CCP2M0 = 1011), this
signal will reset Timer1. The trigger from CCP2 will also
start an A/D conversion if the A/D module is enabled
(see Section 15.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
12.6 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.3 “Timer1 Oscillator”
above) gives users the option to include RTC functionality
to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1 register
pair to overflow triggers the interrupt and calls the
routine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to preload
it; the simplest method is to set the MSb of TMR1H
with a BSF instruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note: The Special Event Triggers from the
CCP2 module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 131
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EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
RTCinit
MOVLW 80h ; Preload TMR1 register pair
MOVWF TMR1H ; for 1 second overflow
CLRF TMR1L
MOVLW b’00001111’ ; Configure for external clock,
MOVWF T1CON ; Asynchronous operation, external oscillator
CLRF secs ; Initialize timekeeping registers
CLRF mins ;
MOVLW .12
MOVWF hours
BSF PIE1, TMR1IE ; Enable Timer1 interrupt
RETURN
RTCisr
BSF TMR1H, 7 ; Preload for 1 sec overflow
BCF PIR1, TMR1IF ; Clear interrupt flag
INCF secs, F ; Increment seconds
MOVLW .59 ; 60 seconds elapsed?
CPFSGT secs
RETURN ; No, done
CLRF secs ; Clear seconds
INCF mins, F ; Increment minutes
MOVLW .59 ; 60 minutes elapsed?
CPFSGT mins
RETURN ; No, done
CLRF mins ; clear minutes
INCF hours, F ; Increment hours
MOVLW .23 ; 24 hours elapsed?
CPFSGT hours
RETURN ; No, done
CLRF hours ; Reset hours
RETURN ; Done
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TMR1L Timer1 Register, Low Byte 50
TMR1H Timer1 Register, High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
Legend: Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
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NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 133
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13.0 TIMER2 MODULE
The Timer2 module timer incorporates the following
features:
• 8-bit timer and period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4 and
1:16)
• Software programmable postscaler (1:1 through
1:16)
• Interrupt on TMR2-to-PR2 match
• Optional use as the shift clock for the MSSP
module
The module is controlled through the T2CON register
(Register 13-1), which enables or disables the timer
and configures the prescaler and postscaler. Timer2
can be shut off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
A simplified block diagram of the module is shown in
Figure 13-1.
13.1 Timer2 Operation
In normal operation, TMR2 is incremented from 00h on
each clock (FOSC/4). A 4-bit counter/prescaler on the
clock input gives direct input, divide-by-4 and divide-by-
16 prescale options; these are selected by the prescaler
control bits, T2CKPS1:T2CKPS0 (T2CON<1:0>). The
value of TMR2 is compared to that of the period register,
PR2, on each clock cycle. When the two values match,
the comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 13.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, while the PR2 register initializes at FFh.
Both the prescaler and postscaler counters are cleared
on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39631B-page 134 Preliminary © 2007 Microchip Technology Inc.
13.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) provides
the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>). The interrupt is
enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
13.3 Timer2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Additional
information is provided in Section 17.0 “Master
Synchronous Serial Port (MSSP) Module”.
FIGURE 13-1: TIMER2 BLOCK DIAGRAM
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TMR2 Timer2 Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2 Timer2 Period Register 50
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
Comparator
TMR2 Output
TMR2
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
4
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
Set TMR2IF
Internal Data Bus
8
Reset
TMR2/PR2
8 8
(to PWM or MSSP)
Match
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 135
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14.0 TIMER3 MODULE
The Timer3 module timer/counter incorporates these
features:
• Software selectable operation as a 16-bit timer or
counter
• Readable and writable 8-bit registers (TMR3H
and TMR3L)
• Selectable clock source (internal or external) with
device clock or Timer1 oscillator internal options
• Interrupt-on-overflow
• Module Reset on CCP Special Event Trigger
A simplified block diagram of the Timer3 module is
shown in Figure 14-1. A block diagram of the module’s
operation in Read/Write mode is shown in Figure 14-2.
The Timer3 module is controlled through the T3CON
register (Register 14-1). It also selects the clock source
options for the CCP modules (see Section 15.1.1
“CCP Modules and Timer Resources” for more
information).
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable bit
1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operations
bit 6,3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the capture/compare clock source for the CCP modules
01 = Timer3 is the capture/compare clock source for CCP2;
Timer1 is the capture/compare clock source for CCP1
00 = Timer1 is the capture/compare clock source for the CCP modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the device clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first
falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39631B-page 136 Preliminary © 2007 Microchip Technology Inc.
14.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
FIGURE 14-1: TIMER3 BLOCK DIAGRAM
FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T1OSO/T13CKI
T1OSI
1
0
TMR3ON
TMR3L
Set
TMR3IF
on Overflow
TMR3
High Byte
Timer1 Oscillator
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
On/Off
Timer3
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
Timer1 Clock Input
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Sleep Input
T1OSCEN(1)
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
1
0
2
T13CKI/T1OSO
T1OSI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
1
0
TMR3L
Internal Data Bus
8
Set
TMR3IF
on Overflow
TMR3
TMR3H
High Byte
8
8
8
Read TMR1L
Write TMR1L
8
TMR3ON
CCP1/CCP2 Special Event Trigger
Timer1 Oscillator
On/Off
Timer3
Timer1 Clock Input
CCP1/CCP2 Select from T3CON<6,3>
Clear TMR3
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 137
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14.2 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Figure 14-2). When the RD16 control bit
(T3CON<7>) is set, the address for TMR3H is mapped
to a buffer register for the high byte of Timer3. A read
from TMR3L will load the contents of the high byte of
Timer3 into the Timer3 High Byte Buffer register. This
provides the user with the ability to accurately read all
16 bits of Timer1 without having to determine whether
a read of the high byte, followed by a read of the low
byte, has become invalid due to a rollover between
reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
14.3 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 12.0
“Timer1 Module”.
14.4 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF (PIR2<1>).
This interrupt can be enabled or disabled by setting or
clearing the Timer3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
14.5 Resetting Timer3 Using the CCP
Special Event Trigger
If either of the CCP modules is configured to use
Timer3 and to generate a Special Event Trigger
in Compare mode (CCP1M3:CCP1M0 or
CCP2M3:CCP2M0 = 1011), this signal will reset
Timer3. It will also start an A/D conversion if the A/D
module is enabled (see Section 15.3.4 “Special
Event Trigger” for more information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR2H:CCPR2L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The Special Event Triggers from the
CCP2 module will not set the TMR3IF
interrupt flag bit (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TMR3L Timer3 Register, Low Byte 51
TMR3H Timer3 Register, High Byte 51
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
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NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 139
PIC18F2420/2520/4420/4520
15.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F2420/2520/4420/4520 devices all have two
CCP (Capture/Compare/PWM) modules. Each module
contains a 16-bit register which can operate as a 16-bit
Capture register, a 16-bit Compare register or a PWM
Master/Slave Duty Cycle register.
In 28-pin devices, the two standard CCP modules (CCP1
and CCP2) operate as described in this chapter. In 40/
44-pin devices, CCP1 is implemented as an enhanced
CCP module with standard Capture and Compare
modes and enhanced PWM modes. The ECCP implementation
is discussed in Section 16.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
The Capture and Compare operations described in this
chapter apply to all standard and enhanced CCP
modules.
REGISTER 15-1: CCPXCON REGISTER (CCP2 MODULE, CCP1 MODULE IN 28-PIN DEVICES)
Note: Throughout this section and Section 16.0
“Enhanced Capture/Compare/PWM (ECCP)
Module”, references to the register and bit
names for CCP modules are referred to generically
by the use of ‘x’ or ‘y’ in place of the
specific module number. Thus, “CCPxCON”
might refer to the control register for CCP1,
CCP2 or ECCP1. “CCPxCON” is used
throughout these sections to refer to the module
control register, regardless of whether the
CCP module is a standard or enhanced
implementation.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbs
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set,
CCP pin reflects I/O state)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCPxIF bit is set)
11xx = PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 140 Preliminary © 2007 Microchip Technology Inc.
15.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
15.1.1 CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2 or 3, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 is available for modules in PWM mode.
TABLE 15-1: CCP MODE – TIMER
RESOURCE
The assignment of a particular timer to a module is
determined by the Timer-to-CCP enable bits in the
T3CON register (Register 14-1). Both modules may be
active at any given time and may share the same timer
resource if they are configured to operate in the same
mode (Capture/Compare or PWM) at the same time. The
interactions between the two modules are summarized in
Figure 15-1 and Figure 15-2. In Timer1 in Asynchronous
Counter mode, the capture operation will not work.
15.1.2 CCP2 PIN ASSIGNMENT
The pin assignment for CCP2 (Capture input, Compare
and PWM output) can change, based on device configuration.
The CCP2MX configuration bit determines
which pin CCP2 is multiplexed to. By default, it is
assigned to RC1 (CCP2MX = 1). If the configuration bit
is cleared, CCP2 is multiplexed with RB3.
Changing the pin assignment of CCP2 does not automatically
change any requirements for configuring the
port pin. Users must always verify that the appropriate
TRIS register is configured correctly for CCP2
operation, regardless of where it is located.
TABLE 15-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES
CCP/ECCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
CCP1 Mode CCP2 Mode Interaction
Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different
for each CCP.
Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Automatic A/D conversions on trigger event
can also be done. Operation of CCP1 could be affected if it is using the same timer as a
time base.
Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3
(depending upon which time base is used). Operation of CCP2 could be affected if it is
using the same timer as a time base.
Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.
Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if
both modules are using the same time base.
Capture PWM(1) None
Compare PWM(1) None
PWM(1) Capture None
PWM(1) Compare None
PWM(1) PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).
Note 1: Includes standard and enhanced PWM operation.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 141
PIC18F2420/2520/4420/4520
15.2 Capture Mode
In Capture mode, the CCPRxH:CCPRxL register pair
captures the 16-bit value of the TMR1 or TMR3
registers when an event occurs on the corresponding
CCPx pin. An event is defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture
is made, the interrupt request flag bit, CCPxIF, is set; it
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value is overwritten by the new captured value.
15.2.1 CCP PIN CONFIGURATION
In Capture mode, the appropriate CCPx pin should be
configured as an input by setting the corresponding
TRIS direction bit.
15.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode or
Synchronized Counter mode. In Asynchronous Counter
mode, the capture operation will not work. The timer to be
used with each CCP module is selected in the T3CON
register (see Section 15.1.1 “CCP Modules and Timer
Resources”).
15.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false interrupts.
The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
15.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCPxM3:CCPxM0). Whenever
the CCP module is turned off or Capture mode is
disabled, the prescaler counter is cleared. This means
that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 15-1: CHANGING BETWEEN
CAPTURE PRESCALERS
(CCP2 SHOWN)
FIGURE 15-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If RB3/CCP2 or RC1/CCP2 is configured
as an output, a write to the port can cause
a capture condition.
CLRF CCP2CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP2CON ; Load CCP2CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set CCP1IF
TMR3
Enable
Q1:Q4
CCP1CON<3:0>
CCP1 pin
Prescaler
÷ 1, 4, 16
and
Edge Detect
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set CCP2IF
TMR3
Enable
CCP2CON<3:0>
CCP2 pin
Prescaler
÷ 1, 4, 16
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
TMR3H TMR3L
and
Edge Detect
4
4
4
PIC18F2420/2520/4420/4520
DS39631B-page 142 Preliminary © 2007 Microchip Technology Inc.
15.3 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
15.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
15.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
15.3.4 SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCPxM3:CCPxM0 = 1011).
For either CCP module, the Special Event Trigger resets
the timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D converter
must already be enabled.
FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP2CON register will force
the RB3 or RC1 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTB or
PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
S Q
R
Output
Logic
Special Event Trigger
Set CCP1IF
CCP1 pin
TRIS
CCP1CON<3:0>
Output Enable
TMR3H TMR3L
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
Set CCP2IF
1
0
Compare
4
(Timer1/Timer3 Reset)
S Q
R
Output
Logic
Special Event Trigger
CCP2 pin
TRIS
CCP2CON<3:0>
4 Output Enable
(Timer1/Timer3 Reset, A/D Trigger)
Match
Compare
Match
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 143
PIC18F2420/2520/4420/4520
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN — RI TO PD POR BOR 48
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TRISB PORTB Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
TMR1L Timer1 Register, Low Byte 50
TMR1H Timer1 Register, High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
TMR3H Timer3 Register, High Byte 51
TMR3L Timer3 Register, Low Byte 51
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Capture/Compare/PWM Register 1, Low Byte 51
CCPR1H Capture/Compare/PWM Register 1, High Byte 51
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
CCPR2L Capture/Compare/PWM Register 2, Low Byte 51
CCPR2H Capture/Compare/PWM Register 2, High Byte 51
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
PIC18F2420/2520/4420/4520
DS39631B-page 144 Preliminary © 2007 Microchip Technology Inc.
15.4 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP2 pin is multiplexed with a PORTB or PORTC
data latch, the appropriate TRIS bit must be cleared to
make the CCP2 pin an output.
Figure 15-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.4.4
“Setup for PWM Operation”.
FIGURE 15-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 15-4) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the
period (1/period).
FIGURE 15-4: PWM OUTPUT
15.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
EQUATION 15-1:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set (exception: if PWM duty
cycle = 0%, the CCPx pin will not be set)
• The PWM duty cycle is latched from CCPRxL into
CCPRxH
15.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPRxL register and to the CCPxCON<5:4> bits. Up
to 10-bit resolution is available. The CCPRxL contains
the eight MSbs and the CCPxCON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPRxL:CCPxCON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 15-2:
CCPRxL and CCPxCON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPRxH until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPRxH is a read-only register.
Note: Clearing the CCP2CON register will force
the RB3 or RC1 output latch (depending on
device configuration) to the default low
level. This is not the PORTB or PORTC I/O
data latch.
CCPRxL
CCPRxH (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R Q
S
Duty Cycle Registers CCPxCON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
Note 1: The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create the
10-bit time base.
CCPx Output
Corresponding
TRIS bit
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscalers (see Section 13.0
“Timer2 Module”) are not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) •
TOSC • (TMR2 Prescale Value)
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 145
PIC18F2420/2520/4420/4520
The CCPRxH register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPRxH and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCPx pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 15-3:
TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
15.4.3 PWM AUTO-SHUTDOWN
(CCP1 ONLY)
The PWM auto-shutdown features of the enhanced CCP
module are also available to CCP1 in 28-pin devices.
The operation of this feature is discussed in detail in
Section 16.4.7 “Enhanced PWM Auto-Shutdown”.
Auto-shutdown features are not available for CCP2.
15.4.4 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPRxL register and CCPxCON<5:4> bits.
3. Make the CCPx pin an output by clearing the
appropriate TRIS bit.
4. Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
5. Configure the CCPx module for PWM operation.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
FOSC
FPWM
⎝---------------⎠
log⎛ ⎞
log(2)
PWM Resolution (max) = -----------------------------bits
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
PIC18F2420/2520/4420/4520
DS39631B-page 146 Preliminary © 2007 Microchip Technology Inc.
TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN — RI TO PD POR BOR 48
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TRISB PORTB Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
TMR2 Timer2 Register 50
PR2 Timer2 Period Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
CCPR1L Capture/Compare/PWM Register 1, Low Byte 51
CCPR1H Capture/Compare/PWM Register 1, High Byte 51
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
CCPR2L Capture/Compare/PWM Register 2, Low Byte 51
CCPR2H Capture/Compare/PWM Register 2, High Byte 51
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 51
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 51
PWM1CON PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 147
PIC18F2420/2520/4420/4520
16.0 ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
In PIC18F4420/4520 devices, CCP1 is implemented
as a standard CCP module with enhanced PWM
capabilities. These include the provision for 2 or 4
output channels, user selectable polarity, dead-band
control and automatic shutdown and restart. The
enhanced features are discussed in detail in
Section 16.4 “Enhanced PWM Mode”. Capture,
Compare and single-output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
The control register for the enhanced CCP module is
shown in Register 16-1. It differs from the CCPxCON
registers in PIC18F2420/2520 devices in that the two
Most Significant bits are implemented to control PWM
functionality.
REGISTER 16-1: CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES)
Note: The ECCP module is implemented only in
40/44-pin devices.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0
bit 7-6 P1M1:P1M0: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
as port pins
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
bit 5-4 DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPR1L.
bit 3-0 CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 148 Preliminary © 2007 Microchip Technology Inc.
In addition to the expanded range of modes available
through the CCP1CON register and ECCP1AS
register, the ECCP module has an additional register
associated with Enhanced PWM operation and
auto-shutdown features. It is:
• PWM1CON (Dead-band delay)
16.1 ECCP Outputs and Configuration
The enhanced CCP module may have up to four PWM
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTC and PORTD. The
outputs that are active depend on the CCP operating
mode selected. The pin assignments are summarized
in Table 16-1.
To configure the I/O pins as PWM outputs, the proper
PWM mode must be selected by setting the
P1M1:P1M0 and CCP1M3:CCP1M0 bits. The
appropriate TRISC and TRISD direction bits for the port
pins must also be set as outputs.
16.1.1 ECCP MODULES AND TIMER
RESOURCES
Like the standard CCP modules, the ECCP module can
utilize Timers 1, 2 or 3, depending on the mode
selected. Timer1 and Timer3 are available for modules
in Capture or Compare modes, while Timer2 is available
for modules in PWM mode. Interactions between
the standard and enhanced CCP modules are identical
to those described for standard CCP modules.
Additional details on timer resources are provided in
Section 15.1.1 “CCP Modules and Timer
Resources”.
16.2 Capture and Compare Modes
Except for the operation of the Special Event Trigger
discussed below, the Capture and Compare modes of
the ECCP module are identical in operation to that of
CCP2. These are discussed in detail in Section 15.2
“Capture Mode” and Section 15.3 “Compare
Mode”. No changes are required when moving
between 28-pin and 40/44-pin devices.
16.2.1 SPECIAL EVENT TRIGGER
The Special Event Trigger output of ECCP1 resets the
TMR1 or TMR3 register pair, depending on which timer
resource is currently selected. This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1 or Timer3.
16.3 Standard PWM Mode
When configured in Single Output mode, the ECCP
module functions identically to the standard CCP
module in PWM mode, as described in Section 15.4
“PWM Mode”. This is also sometimes referred to as
“Compatible CCP” mode, as in Table 16-1.
TABLE 16-1: PIN ASSIGNMENTS FOR VARIOUS ECCP1 MODES
Note: When setting up single output PWM operations,
users are free to use either of the processes
described in Section 15.4.4 “Setup
for PWM Operation” or Section 16.4.9
“Setup for PWM Operation”. The latter is
more generic and will work for either single
or multi-output PWM.
ECCP Mode
CCP1CON
Configuration
RC2 RD5 RD6 RD7
All 40/44-pin devices:
Compatible CCP 00xx 11xx CCP1 RD5/PSP5 RD6/PSP6 RD7/PSP7
Dual PWM 10xx 11xx P1A P1B RD6/PSP6 RD7/PSP7
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 149
PIC18F2420/2520/4420/4520
16.4 Enhanced PWM Mode
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applications.
The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the P1M1:P1M0 and
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to prevent
glitches on any of the outputs. The exception is the
PWM Delay register, PWM1CON, which is loaded at
either the duty cycle boundary or the period boundary
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets, instead of
starting immediately. This means that enhanced PWM
waveforms do not exactly match the standard PWM
waveforms, but are instead offset by one full instruction
cycle (4 TOSC).
As before, the user must manually configure the
appropriate TRIS bits for output.
16.4.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 16-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
CCP1 pin will not be set)
• The PWM duty cycle is copied from CCPR1L into
CCPR1H
FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
Note: The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R Q
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
set CCP1 pin and
latch D.C.
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
time base.
TRISx
CCP1/P1A
TRISx
P1B
TRISx
TRISx
P1D
Output
Controller
P1M1<1:0>
2
CCP1M<3:0>
4
PWM1CON
CCP1/P1A
P1B
P1C
P1D
P1C
PIC18F2420/2520/4420/4520
DS39631B-page 150 Preliminary © 2007 Microchip Technology Inc.
16.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The PWM duty cycle is
calculated by the following equation.
EQUATION 16-2:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not copied into
CCPR1H until a match between PR2 and TMR2 occurs
(i.e., the period is complete). In PWM mode, CCPR1H
is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the CCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
EQUATION 16-3:
16.4.3 PWM OUTPUT CONFIGURATIONS
The P1M1:P1M0 bits in the CCP1CON register allow
one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
( )
PWM Resolution (max) =
FOSC
FPWM
log
log(2)
bits
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value FFh FFh FFh 3Fh 1Fh 17h
Maximum Resolution (bits) 10 10 10 8 7 6.58
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 151
PIC18F2420/2520/4420/4520
FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
FIGURE 16-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
0
Period
00
10
01
11
SIGNAL
PR2 + 1
CCP1CON
<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
0
Period
00
10
01
11
SIGNAL
PR2 + 1
CCP1CON
<7:6>
P1A Modulated
P1A Modulated
P1B Modulated
P1A Active
P1B Inactive
P1C Inactive
P1D Modulated
P1A Inactive
P1B Modulated
P1C Active
P1D Inactive
Duty
Cycle
(Single Output)
(Half-Bridge)
(Full-Bridge,
Forward)
(Full-Bridge,
Reverse)
Delay(1) Delay(1)
Relationships:
• Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
• Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
• Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (see Section 16.4.6 “Programmable
Dead-Band Delay”).
PIC18F2420/2520/4420/4520
DS39631B-page 152 Preliminary © 2007 Microchip Technology Inc.
16.4.4 HALF-BRIDGE MODE
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output signal
is output on the P1A pin, while the complementary PWM
output signal is output on the P1B pin (Figure 16-4). This
mode can be used for half-bridge applications, as shown
in Figure 16-5, or for full-bridge applications where four
power switches are being modulated with two PWM
signals.
In Half-Bridge Output mode, the programmable deadband
delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC6:PDC0, sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTD<5> data latches, the
TRISC<2> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4: HALF-BRIDGE PWM
OUTPUT
FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
Period
Duty Cycle
td
td
(1)
P1A(2)
P1B(2)
td = Dead-Band Delay
Period
(1) (1)
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
PIC18F4X2X
P1A
P1B
FET
Driver
FET
Driver
V+
VLoad
+
V-
+
VFET
Driver
FET
Driver
V+
VLoad
FET
Driver
FET
Driver
PIC18F4X2X
P1A
P1B
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 153
PIC18F2420/2520/4420/4520
16.4.5 FULL-BRIDGE MODE
In Full-Bridge Output mode, four pins are used as
outputs; however, only two outputs are active at a time.
In the Forward mode, pin P1A is continuously active
and pin P1D is modulated. In the Reverse mode, pin
P1C is continuously active and pin P1B is modulated.
These are illustrated in Figure 16-6.
P1A, P1B, P1C and P1D outputs are multiplexed with
the PORTC<2> and PORTD<7:5> data latches. The
TRISC<2> and TRISD<7:5> bits must be cleared to
make the P1A, P1B, P1C and P1D pins outputs.
FIGURE 16-6: FULL-BRIDGE PWM OUTPUT
Period
Duty Cycle
P1A(2)
P1B(2)
P1C(2)
P1D(2)
Forward Mode
(1)
Period
Duty Cycle
P1A(2)
P1C(2)
P1D(2)
P1B(2)
Reverse Mode
(1)
(1) (1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
Note 2: Output signal is shown as active-high.
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DS39631B-page 154 Preliminary © 2007 Microchip Technology Inc.
FIGURE 16-7: EXAMPLE OF FULL-BRIDGE APPLICATION
16.4.5.1 Direction Change in Full-Bridge Mode
In the Full-Bridge Output mode, the P1M1 bit in the
CCP1CON register allows user to control the forward/
reverse direction. When the application firmware
changes this direction control bit, the module will
assume the new direction on the next PWM cycle.
Just before the end of the current PWM period, the
modulated outputs (P1B and P1D) are placed in their
inactive state, while the unmodulated outputs (P1A and
P1C) are switched to drive in the opposite direction.
This occurs in a time interval of 4 TOSC * (Timer2
Prescale Value) before the next PWM period begins.
The Timer2 prescaler will be either 1, 4 or 16, depending
on the value of the T2CKPS1:T2CKPS0 bits
(T2CON<1:0>). During the interval from the switch of
the unmodulated outputs to the beginning of the next
period, the modulated outputs (P1B and P1D) remain
inactive. This relationship is shown in Figure 16-8.
Note that in the Full-Bridge Output mode, the CCP1
module does not provide any dead-band delay. In general,
since only one output is modulated at all times,
dead-band delay is not required. However, there is a
situation where a dead-band delay might be required.
This situation occurs when both of the following
conditions are true:
1. The direction of the PWM output changes when
the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including
the power device and driver circuit, is greater
than the turn-on time.
Figure 16-9 shows an example where the PWM
direction changes from forward to reverse at a near
100% duty cycle. At time t1, the outputs P1A and P1D
become inactive, while output P1C becomes active. In
this example, since the turn-off time of the power
devices is longer than the turn-on time, a shoot-through
current may flow through power devices, QC and QD
(see Figure 16-7), for the duration of ‘t’. The same
phenomenon will occur to power devices, QA and QB,
for PWM direction change from reverse to forward.
If changing PWM direction at high duty cycle is required
for an application, one of the following requirements
must be met:
1. Reduce PWM for a PWM period before
changing directions.
2. Use switch drivers that can drive the switches off
faster than they can drive them on.
Other options to prevent shoot-through current may
exist.
P1A
P1C
FET
Driver
FET
Driver
V+
VLoad
FET
Driver
FET
Driver
P1B
P1D
QA
QB QD
PIC18F4X2X QC
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 155
PIC18F2420/2520/4420/4520
FIGURE 16-8: PWM DIRECTION CHANGE
FIGURE 16-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
DC
Period(1)
SIGNAL
Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle.
2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals
of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals
are inactive at this time.
Period
(Note 2)
P1A (Active-High)
P1B (Active-High)
P1C (Active-High)
P1D (Active-High)
DC
Forward Period Reverse Period
P1A(1)
tON
(2)
tOFF
(3)
t = tOFF – tON
(2,3)
P1B(1)
P1C(1)
P1D(1)
External Switch D(1)
Potential
Shoot-Through
Current(1)
Note 1: All signals are shown as active-high.
2: tON is the turn-on delay of power switch QC and its driver.
3: tOFF is the turn-off delay of power switch QD and its driver.
External Switch C(1)
t1
DC
DC
PIC18F2420/2520/4420/4520
DS39631B-page 156 Preliminary © 2007 Microchip Technology Inc.
16.4.6 PROGRAMMABLE DEAD-BAND
DELAY
In half-bridge applications where all power switches are
modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shootthrough
current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from flowing
during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
current from destroying the bridge power switches. The
delay occurs at the signal transition from the nonactive
state to the active state. See Figure 16-4 for illustration.
Bits PDC6:PDC0 of the PWM1CON register
(Register 16-2) set the delay period in terms of microcontroller
instruction cycles (TCY or 4 TOSC). These bits
are not available on 28-pin devices as the standard
CCP module does not support half-bridge operation.
16.4.7 ENHANCED PWM AUTO-SHUTDOWN
When the CCP1 is programmed for any of the enhanced
PWM modes, the active output pins may be configured
for auto-shutdown. Auto-shutdown immediately places
the enhanced PWM output pins into a defined shutdown
state when a shutdown event occurs.
A shutdown event can be caused by either of the
comparator modules, a low level on the Fault input pin
(FLT0) or any combination of these three sources. The
comparators may be used to monitor a voltage input
proportional to a current being monitored in the bridge
circuit. If the voltage exceeds a threshold, the
comparator switches state and triggers a shutdown.
Alternatively, a low digital signal on FLT0 can also trigger
a shutdown. The auto-shutdown feature can be disabled
by not selecting any auto-shutdown sources. The autoshutdown
sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS
register).
When a shutdown occurs, the output pins are asynchronously
placed in their shutdown states, specified
by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits
(ECCPAS2:ECCPAS0). Each pin pair (P1A/P1C and
P1B/P1D) may be set to drive high, drive low or be tristated
(not driving). The ECCPASE bit (ECCP1AS<7>)
is also set to hold the enhanced PWM outputs in their
shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
REGISTER 16-2: PWM1CON: PWM CONFIGURATION REGISTER
Note: Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1)
bit 7 bit 0
bit 7 PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
goes away; the PWM restarts automatically
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0 PDC6:PDC0: PWM Delay Count bits(1)
Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled and actual time for
a PWM signal to transition to active.
Note 1: Reserved on 28-pin devices; maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 157
PIC18F2420/2520/4420/4520
REGISTER 16-3: ECCP1AS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1)
bit 7 bit 0
bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit
1 = A shutdown event has occurred; ECCP outputs are in shutdown state
0 = ECCP outputs are operating
bit 6-4 ECCPAS2:ECCPAS0: ECCP Auto-Shutdown Source Select bits
111 = FLT0 or Comparator 1 or Comparator 2
110 = FLT0 or Comparator 2
101 = FLT0 or Comparator 1
100 = FLT0
011 = Either Comparator 1 or 2
010 = Comparator 2 output
001 = Comparator 1 output
000 = Auto-shutdown is disabled
bit 3-2 PSSAC1:PSSAC0: Pins A and C Shutdown State Control bits
1x = Pins A and C are tri-state (40/44-pin devices);
PWM output is tri-state (28-pin devices)
01 = Drive Pins A and C to ‘1’
00 = Drive Pins A and C to ‘0’
bit 1-0 PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits(1)
1x = Pins B and D tri-state
01 = Drive Pins B and D to ‘1’
00 = Drive Pins B and D to ‘0’
Note 1: Reserved on 28-pin devices; maintain these bits clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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DS39631B-page 158 Preliminary © 2007 Microchip Technology Inc.
16.4.7.1 Auto-Shutdown and Automatic
Restart
The auto-shutdown feature can be configured to allow
automatic restarts of the module following a shutdown
event. This is enabled by setting the PRSEN bit of the
PWM1CON register (PWM1CON<7>).
In Shutdown mode with PRSEN = 1 (Figure 16-10), the
ECCPASE bit will remain set for as long as the cause
of the shutdown continues. When the shutdown condition
clears, the ECCP1ASE bit is cleared. If PRSEN = 0
(Figure 16-11), once a shutdown condition occurs, the
ECCPASE bit will remain set until it is cleared by firmware.
Once ECCPASE is cleared, the enhanced PWM
will resume at the beginning of the next PWM period.
Independent of the PRSEN bit setting, if the autoshutdown
source is one of the comparators, the
shutdown condition is a level. The ECCPASE bit
cannot be cleared as long as the cause of the shutdown
persists.
The Auto-Shutdown mode can be forced by writing a ‘1’
to the ECCPASE bit.
16.4.8 START-UP CONSIDERATIONS
When the ECCP module is used in the PWM mode, the
application hardware must use the proper external pullup
and/or pull-down resistors on the PWM output pins.
When the microcontroller is released from Reset, all of
the I/O pins are in the high-impedance state. The external
circuits must keep the power switch devices in the
off state until the microcontroller drives the I/O pins with
the proper signal levels, or activates the PWM
output(s).
The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (P1A/P1C and P1B/P1D). The PWM output
polarities must be selected before the PWM pins are
configured as outputs. Changing the polarity configuration
while the PWM pins are configured as outputs is
not recommended, since it may result in damage to the
application circuits.
The P1A, P1B, P1C and P1D output latches may not be
in the proper states when the PWM module is initialized.
Enabling the PWM pins for output at the same time as
the ECCP module may cause damage to the application
circuit. The ECCP module must be enabled in the
proper output mode and complete a full PWM cycle
before configuring the PWM pins as outputs. The completion
of a full PWM cycle is indicated by the TMR2IF
bit being set as the second PWM period begins.
FIGURE 16-10: PWM AUTO-SHUTDOWN (PRSEN = 1, AUTO-RESTART ENABLED)
FIGURE 16-11: PWM AUTO-SHUTDOWN (PRSEN = 0, AUTO-RESTART DISABLED)
Note: Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
Normal PWM
Start of
PWM Period
PWM Period
Shutdown
PWM
ECCPASE bit
Activity
Event
Shutdown
Event Occurs
Shutdown
Event Clears
PWM
Resumes
Normal PWM
Start of
PWM Period
ECCPASE
Cleared by
Firmware
PWM Period
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 159
PIC18F2420/2520/4420/4520
16.4.9 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the ECCP module for PWM operation:
1. Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRIS bits.
2. Set the PWM period by loading the PR2 register.
3. If auto-shutdown is required:
• Disable auto-shutdown (ECCP1AS = 0)
• Configure source (FLT0, Comparator 1 or
Comparator 2)
• Wait for non-shutdown condition
4. Configure the ECCP module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
configurations and direction with the
P1M1:P1M0 bits.
• Select the polarities of the PWM output
signals with the CCP1M3:CCP1M0 bits.
5. Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
6. For Half-Bridge Output mode, set the deadband
delay by loading PWM1CON<6:0> with
the appropriate value.
7. If auto-shutdown operation is required, load the
ECCP1AS register:
• Select the auto-shutdown sources using the
ECCPAS2:ECCPAS0 bits.
• Select the shutdown states of the PWM
output pins using the PSSAC1:PSSAC0 and
PSSBD1:PSSBD0 bits.
• Set the ECCPASE bit (ECCP1AS<7>).
• Configure the comparators using the CMCON
register.
• Configure the comparator inputs as analog
inputs.
8. If auto-restart operation is required, set the
PRSEN bit (PWM1CON<7>).
9. Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit (PIR1<1>).
• Set the TMR2 prescale value by loading the
T2CKPS bits (T2CON<1:0>).
• Enable Timer2 by setting the TMR2ON bit
(T2CON<2>).
10. Enable PWM outputs after a new PWM cycle
has started:
• Wait until TMRn overflows (TMRnIF bit is set).
• Enable the CCP1/P1A, P1B, P1C and/or P1D
pin outputs by clearing the respective TRIS
bits.
• Clear the ECCPASE bit (ECCP1AS<7>).
16.4.10 OPERATION IN POWER MANAGED
MODES
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the ECCP pin is driving a value, it will continue
to drive that value. When the device wakes up, it
will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC
and the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP module without change. In all other
power managed modes, the selected power managed
mode clock will clock Timer2. Other power managed
mode clocks will most likely be different than the
primary clock frequency.
16.4.10.1 Operation with Fail-Safe
Clock Monitor
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the RC_RUN Power Managed
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP will then be clocked from the internal oscillator
clock source, which may have a different clock
frequency than the primary clock.
See the previous section for additional details.
16.4.11 EFFECTS OF A RESET
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F2420/2520/4420/4520
DS39631B-page 160 Preliminary © 2007 Microchip Technology Inc.
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
RCON IPEN SBOREN — RI TO PD POR BOR 48
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
PIR2 OSCFIF CMIF — EEIF BCLIF HLVDIF TMR3IF CCP2IF 52
PIE2 OSCFIE CMIE — EEIE BCLIE HLVDIE TMR3IE CCP2IE 52
IPR2 OSCFIP CMIP — EEIP BCLIP HLVDIP TMR3IP CCP2IP 52
TRISB PORTB Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
TRISD PORTD Data Direction Control Register 52
TMR1L Timer1 Register, Low Byte 50
TMR1H Timer1 Register, High Byte 50
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50
TMR2 Timer2 Register 50
T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50
PR2 Timer2 Period Register 50
TMR3L Timer3 Register, Low Byte 51
TMR3H Timer3 Register, High Byte 51
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51
CCPR1L Capture/Compare/PWM Register 1, Low Byte 51
CCPR1H Capture/Compare/PWM Register 1, High Byte 51
CCP1CON P1M1(1) P1M0(1) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 51
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(1) PSSBD0(1) 51
PWM1CON PRSEN PDC6(1) PDC5(1) PDC4(1) PDC3(1) PDC2(1) PDC1(1) PDC0(1) 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: These bits are unimplemented on 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 161
PIC18F2420/2520/4420/4520
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
17.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
17.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly depending on whether the MSSP
module is operated in SPI or I2C mode.
Additional details are provided under the individual
sections.
17.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR reg
SSPM3:SSPM0
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
Prescaler TOSC
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
RC5/SDO
SSPBUF reg
RC4/SDI/SDA
RA5/AN4/SS/
RC3/SCK/
SCL
HLVDIN/C2OUT
PIC18F2420/2520/4420/4520
DS39631B-page 162 Preliminary © 2007 Microchip Technology Inc.
17.3.1 REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 register
is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not doublebuffered.
A write to SSPBUF will write to both SSPBUF
and SSPSR.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
bit 6 CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Note: Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5 D/A: Data/Address bit
Used in I2C mode only.
bit 4 P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
cleared.
bit 3 S: Start bit
Used in I2C mode only.
bit 2 R/W: Read/Write Information bit
Used in I2C mode only.
bit 1 UA: Update Address bit
Used in I2C mode only.
bit 0 BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 163
PIC18F2420/2520/4420/4520
REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit (Transmit mode only)
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6 SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be
cleared in software).
0 = No overflow
Note: In Master mode, the overflow bit is not set since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, these pins must be properly configured as input or output.
bit 4 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
Note: Bit combinations not specifically listed here are either reserved or implemented in
I2C mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 164 Preliminary © 2007 Microchip Technology Inc.
17.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or
written. If the interrupt method is not going to be used,
then software polling can be done to ensure that a write
collision does not occur. Example 17-1 shows the
loading of the SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 165
PIC18F2420/2520/4420/4520
17.3.3 ENABLING SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function,
some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISA<5> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
17.3.4 TYPICAL CONNECTION
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed
clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
FIGURE 17-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROCESSOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM3:SSPM0 = 010xb
Serial Clock
PIC18F2420/2520/4420/4520
DS39631B-page 166 Preliminary © 2007 Microchip Technology Inc.
17.3.5 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled
(programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is selected by appropriately
programming the CKP bit (SSPCON1<4>). This then,
would give waveforms for SPI communication as
shown in Figure 17-3, Figure 17-5 and Figure 17-6,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 17-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2↓
bit 0
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 167
PIC18F2420/2520/4420/4520
17.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
17.3.7 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The data latch
must be high. When the SS pin is low, transmission and
reception are enabled and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors
may be desirable depending on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 17-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7
bit 0
Next Q4 Cycle
after Q2↓
PIC18F2420/2520/4420/4520
DS39631B-page 168 Preliminary © 2007 Microchip Technology Inc.
FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2↓
bit 0
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2↓
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 169
PIC18F2420/2520/4420/4520
17.3.8 OPERATION IN POWER MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In most Idle modes, a clock is provided to the peripherals.
That clock should be from the primary clock
source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the controller
from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
17.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Control Register 52
TRISC PORTC Data Direction Control Register 52
SSPBUF SSP Receive Buffer/Transmit Register 50
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50
SSPSTAT SMP CKE D/A P S R/W UA BF 50
Legend: Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in 28-pin devices; always maintain these bits clear.
2: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
PIC18F2420/2520/4420/4520
DS39631B-page 170 Preliminary © 2007 Microchip Technology Inc.
17.4 I2C Mode
The MSSP module in I2C mode fully implements all
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 17-7: MSSP BLOCK DIAGRAM
(I2C MODE)
17.4.1 REGISTERS
The MSSP module has six registers for I2C operation.
These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
(SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
• MSSP Address Register (SSPADD)
SSPCON1, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON1 and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read-only.
The upper two bits of the SSPSTAT are read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address when
the SSP is configured in I2C Slave mode. When the
SSP is configured in Master mode, the lower seven bits
of SSPADD act as the Baud Rate Generator reload
value.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not doublebuffered.
A write to SSPBUF will write to both SSPBUF
and SSPSR.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/SDI/
Shift
Clock
MSb
SDA
LSb
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 171
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REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
bit 7 SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
bit 6 CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 3 S: Start bit
1 = Indicates that a Start bit has been detected last
0 = Start bit was not detected last
Note: This bit is cleared on Reset and when SSPEN is cleared.
bit 2 R/W: Read/Write Information bit (I2C mode only)
In Slave mode:
1 = Read
0 = Write
Note: This bit holds the R/W bit information following the last address match. This bit is
only valid from the address match to the next Start bit, Stop bit or not ACK bit.
In Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
Note: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in Active mode.
bit 1 UA: Update Address bit (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
In Transmit mode:
1 = SSPBUF is full
0 = SSPBUF is empty
In Receive mode:
1 = SSPBUF is full (does not include the ACK and Stop bits)
0 = SSPBUF is empty (does not include the ACK and Stop bits)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6 SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5 SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Note: When enabled, the SDA and SCL pins must be properly configured as input or
output.
bit 4 CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011 = I2C Firmware Controlled Master mode (Slave Idle)
1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 173
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REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1)
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
Note: Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4 ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)(1)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence Idle
bit 3 RCEN: Receive Enable bit (Master mode only)(1)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2 PEN: Stop Condition Enable bit (Master mode only)(1)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1 RSEN: Repeated Start Condition Enable bit (Master mode only)(1)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
these bits may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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17.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I2C modes to be selected:
• I2C Master mode, clock = (FOSC/4) x (SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
17.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured
as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware automatically
will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
17.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 175
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17.4.3.2 Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit,
CKP (SSPCON<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
17.4.3.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit, CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is complete.
In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT register)
and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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DS39631B-page 176 Preliminary © 2007 Microchip Technology Inc.
FIGURE 17-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP (CKP does not reset to ‘0’ when SEN = 0)
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 177
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FIGURE 17-9: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9
SSPBUF is written in software
Cleared in software
From SSPIF ISR
Data in
sampled
S
ACK
R/W = 0 Transmitting Data
ACK
Receiving Address
A7 D7
9 1
D6 D5 D4 D3 D2 D1 D0
2 3 4 5 6 7 8 9
SSPBUF is written in software
Cleared in software
From SSPIF ISR
Transmitting Data
D7
1
CKP
P
ACK
CKP is set in software CKP is set in software
SCL held low
while CPU
responds to SSPIF
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DS39631B-page 178 Preliminary © 2007 Microchip Technology Inc.
FIGURE 17-10: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>)
Cleared in software
Receive Second Byte of Address
Cleared by hardware
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 179
PIC18F2420/2520/4420/4520
FIGURE 17-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 A8
R/W=1
ACK ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address.
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Completion of
clears BF flag
CKP (SSPCON1<4>)
CKP is set in software
CKP is automatically cleared in hardware, holding SCL low
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
third address sequence
BF flag is clear
at the end of the
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17.4.4 CLOCK STRETCHING
Both 7-bit and 10-bit Slave modes implement
automatic clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
17.4.4.1 Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 17-13).
17.4.4.2 Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence as described in 7-bit mode.
17.4.4.3 Clock Stretching for 7-bit Slave
Transmit Mode
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock if the BF bit is clear. This occurs regardless
of the state of the SEN bit.
The user’s ISR must set the CKP bit before transmission
is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
17.4.4.4 Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled
during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled by the BF flag
as in 7-bit Slave Transmit mode (see Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence in order to prevent an overflow
condition.
Note: If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by reading
the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software
regardless of the state of the BF bit.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 181
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17.4.4.5 Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sampled
low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
FIGURE 17-12: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX DX – 1
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
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FIGURE 17-13: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0
R/W = 0 Receiving Data ACK Receiving Data ACK
ACK
Receiving Address
Cleared in software
SSPBUF is read
Bus master
terminates
transfer
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
D2
6
(PIR1<3>)
CKP
CKP
written
to ‘1’ in
If BF is cleared
prior to the falling
edge of the 9th clock,
CKP will not be reset
to ‘0’ and no clock
stretching will occur
software
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because buffer full bit is
clear prior to falling edge
of 9th clock
Clock is not held low
because ACK = 1
BF is set after falling
edge of the 9th clock,
CKP is reset to ‘0’ and
clock stretching occurs
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 183
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FIGURE 17-14: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 7 8 9 P
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
D2
6
(PIR1<3>)
Cleared in software
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with low
byte of address after falling edge
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated with high
byte of address after falling edge
SSPBUF is written with
contents of SSPSR
Dummy read of SSPBUF
to clear BF flag
ACK
CKP
1 2 3 4 5 7 8 9
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus master
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON1<6>)
CKP written to ‘1’
Note: An update of the SSPADD register before
the falling edge of the ninth clock will have
no effect on UA and UA will remain set.
Note: An update of the SSPADD
register before the falling
edge of the ninth clock will
have no effect on UA and
UA will remain set.
in software
Clock is held low until
update of SSPADD has
taken place
of ninth clock of ninth clock
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
Dummy read of SSPBUF
to clear BF flag
Clock is held low until
CKP is set to ‘1’
Clock is not held low
because ACK = 1
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17.4.5 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually
determines which device will be the slave addressed by
the master. The exception is the general call address
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the General
Call Enable bit, GCEN, is enabled (SSPCON2<7>
is set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the
interrupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
FIGURE 17-15: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
SDA
SCL
S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
R/W = 0
General Call Address ACK
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interrupt
‘0’
‘1’
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 185
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17.4.6 MASTER MODE
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop conditions.
The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle, with both the S and P bits clear.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
Once Master mode is enabled, the user has six
options.
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 17-16: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note: The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condition
is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Read Write
SSPSR
Start bit, Stop bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
Start bit Detect
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17.4.6.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmitted,
an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted contains
the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning
and end of transmission.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate” for more detail.
A typical transmit sequence would go as follows:
1. The user generates a Start condition by setting
the Start Enable bit, SEN (SSPCON2<0>).
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
11. The user generates a Stop condition by setting
the Stop Enable bit, PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 187
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17.4.7 BAUD RATE
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmission
of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17: BAUD RATE GENERATOR BLOCK DIAGRAM
TABLE 17-3: I2C CLOCK RATE W/BRG
SSPM3:SSPM0
CLKO BRG Down Counter FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
FCY FCY*2 BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz 20 MHz 18h 400 kHz(1)
10 MHz 20 MHz 1Fh 312.5 kHz
10 MHz 20 MHz 63h 100 kHz
4 MHz 8 MHz 09h 400 kHz(1)
4 MHz 8 MHz 0Ch 308 kHz
4 MHz 8 MHz 27h 100 kHz
1 MHz 2 MHz 02h 333 kHz(1)
1 MHz 2 MHz 09h 100 kHz
1 MHz 2 MHz 00h 1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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17.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 17-18).
FIGURE 17-18: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
SCL
SCL deasserted but slave holds
DX DX – 1
BRG
SCL is sampled high, reload takes
place and BRG starts its count
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 189
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17.4.8 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (TBRG), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware; the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
17.4.8.1 WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 17-19: FIRST START BIT TIMING
Note: If at the beginning of the Start condition,
the SDA and SCL pins are already sampled
low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
TBRG
1st bit 2nd bit
TBRG
SDA = 1,
SCL = At completion of Start bit, 1
TBRG Write to SSPBUF occurs here
hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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17.4.9 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sampled
low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Generator
times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. Following
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the Baud Rate Generator has timed out.
Immediately following the SSPIF bit getting set, the user
may write the SSPBUF with the 7-bit address in 7-bit
mode or the default first address in 10-bit mode. After the
first eight bits are transmitted and an ACK is received,
the user may then transmit an additional eight bits of
address (10-bit mode) or eight bits of data (7-bit mode).
17.4.9.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-20: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
SDA
SCL
Sr = Repeated Start
Write to SSPCON2
on falling edge of ninth clock, Write to SSPBUF occurs here
end of Xmit
At completion of Start bit,
hardware clears RSEN bit
1st bit
S bit set by hardware
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change).
SCL = 1
occurs here.
TBRG TBRG TBRG
and sets SSPIF
RSEN bit set by hardware
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 191
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17.4.10 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next transmission.
Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification
parameter 106). SCL is held low for one Baud Rate
Generator rollover count (TBRG). Data should be valid
before SCL is released high (see data setup time specification
parameter 107). When the SCL pin is released
high, it is held that way for TBRG. The data on the SDA
pin must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received properly.
The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
deassert the SDA pin, allowing the slave to respond
with an Acknowledge. On the falling edge of the ninth
clock, the master will sample the SDA pin to see if the
address was recognized by a slave. The status of the
ACK bit is loaded into the ACKSTAT status bit
(SSPCON2<6>). Following the falling edge of the ninth
clock transmission of the address, the SSPIF is set, the
BF flag is cleared and the Baud Rate Generator is
turned off until another write to the SSPBUF takes
place, holding SCL low and allowing SDA to float.
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
17.4.10.3 ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowledge
(ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate Generator
is suspended from counting, holding SCL low. The
MSSP is now in Idle state awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
17.4.11.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
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FIGURE 17-21: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = ‘0’ D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
Cleared in software service routine
SSPBUF is written in software
from SSP interrupt
After Start condition, SEN cleared by hardware
S
SSPBUF written with 7-bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
Start condition begins
From slave, clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
Cleared in software
SSPBUF written
PEN
R/W
Cleared in software
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 193
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FIGURE 17-22: I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
5 6 7 8 9
D7 D6 D5 D4 D3 D2 D1 D0
S
SDA A7 A6 A5 A4 A3 A2 A1
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4
Bus master
terminates
transfer
ACK
Receiving Data from Slave Receiving Data from Slave
ACK D7 D6 D5 D4 D3 D2 D1 D0
Transmit Address to Slave R/W = 0
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1),
Write to SSPBUF occurs here,
ACK from Slave
Master configured as a receiver
by programming SSPCON2<3> (RCEN = 1)
PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Cleared in software Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SSPIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknowledge
sequence
of receive
Set ACKEN, start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACKDT = 1
RCEN cleared
automatically
RCEN = 1, start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
begin Start condition
Cleared in software
SDA = ACKDT = 0
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
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17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate
an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sampled
low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sampled
high while SCL is high, the P bit (SSPSTAT<4>) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 17-24).
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the contents
of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23: ACKNOWLEDGE SEQUENCE WAVEFORM
FIGURE 17-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Note: TBRG = one Baud Rate Generator period.
SDA
SCL
SSPIF set at
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
Cleared in
TBRG TBRG
the end of receive
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software SSPIF set at the end
of Acknowledge sequence
Cleared in
software
ACK
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2,
set PEN
Falling edge of
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
9th clock
SCL brought high after TBRG
Note: TBRG = one Baud Rate Generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
TBRG
to setup Stop condition
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 195
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17.4.14 SLEEP OPERATION
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or complete
byte transfer occurs, wake the processor from
Sleep (if the MSSP interrupt is enabled).
17.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
• A Repeated Start Condition
• An Acknowledge Condition
17.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration.
When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted
and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision
Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination
of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source
Sample SDA. While SCL is high,
data doesn’t match what is driven
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
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DS39631B-page 196 Preliminary © 2007 Microchip Technology Inc.
17.4.17.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
b) SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
• the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 17-26: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus collision
because the two masters must be
allowed to arbitrate the first address following
the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 197
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FIGURE 17-27: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN
bus collision occurs. Set BCLIF.
SCL = 0 before SDA = 0,
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
bus collision occurs. Set BCLIF.
SCL = 0 before BRG time-out,
‘0’ ‘0’
‘0’ ‘0’
SDA
SCL
SEN
Set S
Less than TBRG
TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
set SSPIF in software
SDA = 0, SCL = 1,
SCL pulled low after BRG
time-out
Set SSPIF
‘0’
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SEN, enable START
sequence if SDA = 1, SCL = 1
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DS39631B-page 198 Preliminary © 2007 Microchip Technology Inc.
17.4.17.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to 0. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 17-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 17-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 17-30: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
‘0’
‘0’
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleared
in software
SCL goes low before SDA,
set BCLIF. Release SDA and SCL.
TBRG TBRG
‘0’
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 199
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17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
FIGURE 17-31: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 17-32: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
set BCLIF
‘0’
‘0’
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high,
set BCLIF
‘0’
‘0’
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DS39631B-page 200 Preliminary © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 201
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18.0 ENHANCED UNIVERSAL
SYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is one of the
two serial I/O modules. (Generically, the USART is also
known as a Serial Communications Interface or SCI.)
The EUSART can be configured as a full-duplex
asynchronous system that can communicate with
peripheral devices, such as CRT terminals and
personal computers. It can also be configured as a halfduplex
synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The Enhanced USART module implements additional
features, including automatic baud rate detection and
calibration, automatic wake-up on Sync Break reception
and 12-bit Break character transmit. These make it
ideally suited for use in Local Interconnect Network bus
(LIN bus) systems.
The EUSART can be configured in the following
modes:
• Asynchronous (full duplex) with:
- Auto-wake-up on character reception
- Auto-baud calibration
- 12-bit Break character transmission
• Synchronous – Master (half duplex) with
selectable clock polarity
• Synchronous – Slave (half duplex) with selectable
clock polarity
The pins of the Enhanced USART are multiplexed
with PORTC. In order to configure RC6/TX/CK and
RC7/RX/DT as a USART:
• bit SPEN (RCSTA<7>) must be set (= 1)
• bit TRISC<7> must be set (= 1)
• bit TRISC<6> must be set (= 1)
The operation of the Enhanced USART module is
controlled through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These are detailed on the following pages in
Register 18-1, Register 18-2 and Register 18-3,
respectively.
Note: The EUSART control will automatically
reconfigure the pin from input to output as
needed.
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DS39631B-page 202 Preliminary © 2007 Microchip Technology Inc.
REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 203
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REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8>
is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 9-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC18F2420/2520/4420/4520
DS39631B-page 204 Preliminary © 2007 Microchip Technology Inc.
REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit
1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode
(must be cleared in software)
0 = No BRG rollover has occurred
bit 6 RCIDL: Receive Operation Idle Status bit
1 = Receive operation is Idle
0 = Receive operation is active
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
Unused in this mode.
Synchronous mode:
1 = Idle state for clock (CK) is a high level
0 = Idle state for clock (CK) is a low level
bit 3 BRG16: 16-bit Baud Rate Register Enable bit
1 = 16-bit Baud Rate Generator – SPBRGH and SPBRG
0 = 8-bit Baud Rate Generator – SPBRG only (Compatible mode), SPBRGH value ignored
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin – interrupt generated on falling edge; bit
cleared in hardware on following rising edge
0 = RX pin not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field
(55h); cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 205
PIC18F2420/2520/4420/4520
18.1 Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 18-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 18-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 18-2. It may be advantageous
to use the high baud rate (BRGH = 1) or the
16-bit BRG to reduce the baud rate error, or achieve a
slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
18.1.1 OPERATION IN POWER MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
18.1.2 SAMPLING
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
TABLE 18-1: BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n + 1)]
0 0 1 8-bit/Asynchronous
FOSC/[16 (n + 1)]
0 1 0 16-bit/Asynchronous
0 1 1 16-bit/Asynchronous
1 0 x 8-bit/Synchronous FOSC/[4 (n + 1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
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DS39631B-page 206 Preliminary © 2007 Microchip Technology Inc.
EXAMPLE 18-1: CALCULATING BAUD RATE ERROR
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1))
Solving for SPBRGH:SPBRG:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on page
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register, High Byte 51
SPBRG EUSART Baud Rate Generator Register, Low Byte 51
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 207
PIC18F2420/2520/4420/4520
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — — — — — — —
1.2 — — — 1.221 1.73 255 1.202 0.16 129 1201 -0.16 103
2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2403 -0.16 51
9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12
19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —
57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —
115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.16 207 300 -0.16 103 300 -0.16 51
1.2 1.202 0.16 51 1201 -0.16 25 1201 -0.16 12
2.4 2.404 0.16 25 2403 -0.16 12 — — —
9.6 8.929 -6.99 6 — — — — — —
19.2 20.833 8.51 2 — — — — — —
57.6 62.500 8.51 0 — — — — — —
115.2 62.500 -45.75 0 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — — — — — — —
1.2 — — — — — — — — — — — —
2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207
9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 — — — — — — 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
PIC18F2420/2520/4420/4520
DS39631B-page 208 Preliminary © 2007 Microchip Technology Inc.
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 300 -0.04 1665
1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1201 -0.16 415
2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2403 -0.16 207
9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51
19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25
57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8
115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.04 832 300 -0.16 415 300 -0.16 207
1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51
2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25
9.6 9.615 0.16 25 9615 -0.16 12 — — —
19.2 19.231 0.16 12 — — — — — —
57.6 62.500 8.51 3 — — — — — —
115.2 125.000 8.51 1 — — — — — —
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 300 -0.01 6665
1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1200 -0.04 1665
2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 832
9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207
19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103
57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34
115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16
BAUD
RATE
(K)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 0.01 3332 300 -0.04 1665 300 -0.04 832
1.2 1.200 0.04 832 1201 -0.16 415 1201 -0.16 207
2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103
9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25
19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12
57.6 58.824 2.12 16 55555 3.55 8 — — —
115.2 111.111 -3.55 8 — — — — — —
TABLE 18-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 209
PIC18F2420/2520/4420/4520
18.1.3 AUTO-BAUD RATE DETECT
The enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 18-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value 55h (ASCII
“U”, which is also the LIN bus Sync character) in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming signal.
After a Start bit, the SPBRG begins counting up, using
the preselected clock source on the first rising edge of
RX. After eight bits on the RX pin or the fifth rising edge,
an accumulated value totalling the proper BRG period is
left in the SPBRGH:SPBRG register pair. Once the 5th
edge is seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG rollovers
and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 18-2).
While calibrating the baud rate period, the BRG registers
are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 18-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
TABLE 18-4: BRG COUNTER
CLOCK RATES
18.1.3.1 ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisition,
the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG cannot be written to. Users should also ensure
that ABDEN does not become set during a transmit
sequence. Failing to do this may result in unpredictable
EUSART operation.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system timing
and communication baud rates must
be taken into consideration when using the
Auto-Baud Rate Detection feature.
BRG16 BRGH BRG Counter Clock
0 0 FOSC/512
0 1 FOSC/128
1 0 FOSC/128
1 1 FOSC/32
Note: During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of BRG16 setting.
PIC18F2420/2520/4420/4520
DS39631B-page 210 Preliminary © 2007 Microchip Technology Inc.
FIGURE 18-1: AUTOMATIC BAUD RATE CALCULATION
FIGURE 18-2: BRG OVERFLOW SEQUENCE
BRG Value
RX pin
ABDEN bit
RCIF bit
Bit 0 Bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Set by User Auto-Cleared
XXXXh 0000h
Edge #1
Bit 2 Bit 3
Edge #2
Bit 4 Bit 5
Edge #3
Bit 6 Bit 7
Edge #4
Stop Bit
Edge #5
001Ch
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
SPBRG XXXXh 1Ch
SPBRGH XXXXh 00h
Start Bit 0
XXXXh 0000h 0000h
FFFFh
BRG Clock
ABDEN bit
RX pin
ABDOVF bit
BRG Value
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 211
PIC18F2420/2520/4420/4520
18.2 EUSART Asynchronous Mode
The Asynchronous mode of operation is selected by
clearing the SYNC bit (TXSTA<4>). In this mode, the
EUSART uses standard Non-Return-to-Zero (NRZ) format
(one Start bit, eight or nine data bits and one Stop
bit). The most common data format is 8 bits. An on-chip
dedicated 8-bit/16-bit Baud Rate Generator can be used
to derive standard baud rate frequencies from the
oscillator.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent but use the same data format and baud
rate. The Baud Rate Generator produces a clock, either
x16 or x64 of the bit shift rate depending on the BRGH
and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity
is not supported by the hardware but can be
implemented in software and stored as the 9th data bit.
When operating in Asynchronous mode, the EUSART
module consists of the following important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
• Auto-Wake-up on Sync Break Character
• 12-bit Break Character Transmit
• Auto-Baud Rate Detection
18.2.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 18-3. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The Shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
Once the TXREG register transfers the data to the TSR
register (occurs in one TCY), the TXREG register is empty
and the TXIF flag bit (PIR1<4>) is set. This interrupt can
be enabled or disabled by setting or clearing the interrupt
enable bit, TXIE (PIE1<4>). TXIF will be set regardless of
the state of TXIE; it cannot be cleared in software. TXIF
is also not cleared immediately upon loading TXREG, but
becomes valid in the second instruction cycle following
the load instruction. Polling TXIF immediately following a
load of TXREG will return invalid results.
While TXIF indicates the status of the TXREG register,
another bit, TRMT (TXSTA<1>), shows the status of
the TSR register. TRMT is a read-only bit which is set
when the TSR register is empty. No interrupt logic is
tied to this bit so the user has to poll this bit in order to
determine if the TSR register is empty.
To set up an Asynchronous Transmission:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-3: EUSART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
TX pin
Pin Buffer
and Control
8
• • •
BRG16 SPBRGH
PIC18F2420/2520/4420/4520
DS39631B-page 212 Preliminary © 2007 Microchip Technology Inc.
FIGURE 18-4: ASYNCHRONOUS TRANSMISSION
FIGURE 18-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 18-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
TXREG EUSART Transmit Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register, High Byte 51
SPBRG EUSART Baud Rate Generator Register, Low Byte 51
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 213
PIC18F2420/2520/4420/4520
18.2.2 EUSART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 18-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at FOSC. This mode would typically be used
in RS-232 systems.
To set up an Asynchronous Reception:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit, RCIF, will be set when reception is
complete and an interrupt will be generated if
enable bit, RCIE, was set.
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
18.2.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 18-6: EUSART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
Baud Rate Generator
RX
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
MSb RSR Register LSb
RX9D RCREG Register
FIFO
Interrupt RCIF
RCIE
Data Bus
8
÷ 64
÷ 16
or
Stop (8) 7 1 0 Start
RX9
• • •
BRG16 SPBRGH SPBRG
or
÷ 4
PIC18F2420/2520/4420/4520
DS39631B-page 214 Preliminary © 2007 Microchip Technology Inc.
FIGURE 18-7: ASYNCHRONOUS RECEPTION
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
18.2.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be performed.
The auto-wake-up feature allows the controller
to wake-up due to activity on the RX/DT line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCON<1>). Once set, the typical receive
sequence on RX/DT is disabled and the EUSART
remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event consists
of a high-to-low transition on the RX/DT line. (This
coincides with the start of a Sync Break or a Wake-up
Signal character for the LIN protocol.)
Following a wake-up event, the module generates an
RCIF interrupt. The interrupt is generated synchronously
to the Q clocks in normal operating modes
(Figure 18-8) and asynchronously, if the device is in
Sleep mode (Figure 18-9). The interrupt condition is
cleared by reading the RCREG register.
The WUE bit is automatically cleared once a low-tohigh
transition is observed on the RX line following the
wake-up event. At this point, the EUSART module is in
Idle mode and returns to normal operation. This signals
to the user that the Sync Break event is over.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51
RCREG EUSART Receive Register 51
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51
BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 51
SPBRGH EUSART Baud Rate Generator Register, High Byte 51
SPBRG EUSART Baud Rate Generator Register, Low Byte 51
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
Start
bit bit 0 bit 1 bit 7/8 Stop bit 0 bit 7/8
bit
Start
bit
Start
bit 7/8 Stop bit
bit
RX (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word
causing the OERR (overrun) bit to be set.
© 2007 Microchip Technology Inc. Preliminary DS39631B-page 215
PIC18F2420/2520/4420/4520
18.2.4.1 Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RX/DT, information with any state
changes before the Stop bit may signal a false end-ofcharacter
and cause data or framing errors. To work
properly, therefore, the initial character in the transmission
must be all ‘0’s. This can be 00h (8 bytes) for
standard RS-232 devices or 000h (12 bits) for LIN bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with longer
start-up intervals (i.e., XT or HS mode). The Sync
Break (or Wake-up Signal) character must be of
sufficient length and be followed by a sufficient interval
to allow enough time for the selected oscillator to start
and provide proper initialization of the EUSART.
18.2.4.2 Special Considerations Using
the WUE Bit
The timing of WUE and RCIF events may cause some
confusion when it comes to determining the validity of
received data. As noted, setting the WUE bit places the
EUSART in an Idle mode. The wake-up event causes a
receive interrupt by setting the RCIF bit. The WUE bit is
cleared after this when a rising edge is seen on RX/DT.
The interrupt condition is then cleared by reading the
RCREG register. Ordinarily, the data in RCREG will be
dummy data and should be discarded.
The fact that the WUE bit has been cleared (or is still
set) and the RCIF flag is set should not be used as an
indicator of the integrity of the data in RCREG. Users
should consider implementing a parallel method in
firmware to verify received data integrity.
To assure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process. If
a receive operation is not occurring, the WUE bit may
then be set just prior to entering the Sleep mode.
FIGURE 18-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
FIGURE 18-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(1)
RX/DT Line
RCIF
Note 1: The EUSART remains in Idle while the WUE bit is set.
Bit set by user
Cleared due to user read of RCREG
Auto-Cleared
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit(2)
RX/DT Line
RCIF
Bit set by user
Cleared due to user read of RCREG
Sleep Command Executed
Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This
sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
Note 1
Auto-Cleared
PIC18F2420/2520/4420/4520
DS39631B-page 216 Preliminary © 2007 Microchip Technology Inc.
18.2.5 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The frame Break character is sent whenever
the SENDB and TXEN bits (TXSTA<3> and
TXSTA<5>) are set while the Transmit Shift register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specificati