Farnell PDF TEXAS INSTRUMENTS - Highly Integrated Digital Controller for Isolated Power (Rev. B) - Farnell Element 14

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Farnell Element 14 :

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Everything You Need To Know About Arduino

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The Cube® 3D Printer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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UCD3138 Highly Integrated Digital Controller for Isolated Power Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLUSAP2B March 2012–Revised July 2012 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Contents 1 Introduction ........................................................................................................................ 6 1.1 Features ...................................................................................................................... 6 1.2 Applications .................................................................................................................. 7 2 Overview ............................................................................................................................ 7 2.1 Description ................................................................................................................... 7 2.2 Ordering Information ........................................................................................................ 8 2.3 Product Selection Matrix ................................................................................................... 8 2.4 Functional Block Diagram .................................................................................................. 9 2.5 UCD3138 64 QFN – Pin Assignments ................................................................................. 10 2.6 Pin Functions .............................................................................................................. 11 2.7 UCD3138 40 QFN – Pin Assignments ................................................................................. 13 2.8 Pin Functions .............................................................................................................. 14 3 Electrical Specifications ..................................................................................................... 15 3.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 15 3.2 THERMAL INFORMATION .............................................................................................. 15 3.3 RECOMMENDED OPERATING CONDITIONS ....................................................................... 15 3.4 ELECTRICAL CHARACTERISTICS .................................................................................... 16 3.5 PMBus/SMBus/I2C Timing ............................................................................................... 19 3.6 Power On Reset (POR) / Brown Out Reset (BOR) ................................................................... 20 3.7 Typical Clock Gating Power Savings ................................................................................... 21 3.8 Typical Temperature Characteristics ................................................................................... 22 4 Functional Overview .......................................................................................................... 23 4.1 ARM Processor ............................................................................................................ 23 4.2 Memory ..................................................................................................................... 23 4.2.1 CPU Memory Map and Interrupts ............................................................................ 23 4.2.1.1 Memory Map (After Reset Operation) ........................................................... 23 4.2.1.2 Memory Map (Normal Operation) ................................................................ 24 4.2.1.3 Memory Map (System and Peripherals Blocks) ................................................ 24 4.2.2 Boot ROM ....................................................................................................... 24 4.2.3 Customer Boot Program ....................................................................................... 25 4.2.4 Flash Management ............................................................................................. 25 4.3 System Module ............................................................................................................ 25 4.3.1 Address Decoder (DEC) ....................................................................................... 25 4.3.2 Memory Management Controller (MMC) .................................................................... 25 4.3.3 System Management (SYS) ................................................................................... 25 4.3.4 Central Interrupt Module (CIM) ............................................................................... 26 4.4 Peripherals ................................................................................................................. 27 4.4.1 Digital Power Peripherals ...................................................................................... 27 4.4.1.1 Front End ............................................................................................ 27 4.4.1.2 DPWM Module ..................................................................................... 28 4.4.1.3 DPWM Events ...................................................................................... 29 4.4.1.4 High Resolution DPWM ........................................................................... 31 4.4.1.5 Over Sampling ...................................................................................... 31 4.4.1.6 DPWM Interrupt Generation ...................................................................... 31 4.4.1.7 DPWM Interrupt Scaling/Range .................................................................. 31 4.5 DPWM Modes of Operation .............................................................................................. 32 4.5.1 Normal Mode .................................................................................................... 32 4.6 Phase Shifting ............................................................................................................. 34 4.7 DPWM Multiple Output Mode ............................................................................................ 35 4.8 DPWM Resonant Mode .................................................................................................. 36 4.9 Triangular Mode ........................................................................................................... 38 2 Contents Copyright © 2012, Texas Instruments Incorporated UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.10 Leading Edge Mode ....................................................................................................... 39 4.11 Sync FET Ramp and IDE Calculation .................................................................................. 41 4.12 Automatic Mode Switching ............................................................................................... 41 4.12.1 Phase Shifted Full Bridge Example .......................................................................... 41 4.12.2 LLC Example .................................................................................................... 42 4.12.3 Mechanism for Automatic Mode Switching .................................................................. 44 4.13 DPWMC, Edge Generation, IntraMux .................................................................................. 45 4.14 Filter ......................................................................................................................... 46 4.14.1 Loop Multiplexer ................................................................................................ 48 4.14.2 Fault Multiplexer ................................................................................................ 49 4.15 Communication Ports ..................................................................................................... 51 4.15.1 SCI (UART) Serial Communication Interface ............................................................... 51 4.15.2 PMBUS .......................................................................................................... 51 4.15.3 General Purpose ADC12 ...................................................................................... 52 4.15.4 Timers ............................................................................................................ 53 4.15.4.1 24-bit PWM Timer .................................................................................. 53 4.15.4.2 16-Bit PWM Timers ................................................................................ 54 4.15.4.3 Watchdog Timer .................................................................................... 54 4.16 Miscellaneous Analog ..................................................................................................... 54 4.17 Package ID Information ................................................................................................... 54 4.18 Brownout ................................................................................................................... 54 4.19 Global I/O ................................................................................................................... 55 4.20 Temperature Sensor Control ............................................................................................. 56 4.21 I/O Mux Control ............................................................................................................ 56 4.21.1 JTAG Use for I/O and JTAG Security ........................................................................ 57 4.22 Current Sharing Control .................................................................................................. 57 4.23 Temperature Reference .................................................................................................. 58 5 IC Grounding and Layout Recommendations ........................................................................ 59 6 Tools and Documentation ................................................................................................... 60 7 References ....................................................................................................................... 62 Revision History ......................................................................................................................... 63 Copyright © 2012, Texas Instruments Incorporated Contents 3 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com List of Figures 3-1 I2C/SMBus/PMBus Timing Diagram ........................................................................................... 20 3-2 Bus Timing in Extended Mode.................................................................................................. 20 3-3 Power On Reset (POR) / Brown Out Reset (BOR) .......................................................................... 20 3-4 EADC LSB Size with 4X Gain (mV) vs. Temperature ....................................................................... 22 3-5 ADC12 Measurement Temperature Sensor Voltage vs. Temperature.................................................... 22 3-6 ADC12 2.5-V Reference vs. Temperature .................................................................................... 22 3-7 ADC12 Temperature Sensor Measurement Error vs. Temperature....................................................... 22 3-8 UCD3138 Oscillator Frequency (2MHz Reference, Divided Down from 250MHz) vs. Temperature.................. 22 4-1 Input Stage of EADC Module ................................................................................................... 28 4-2 Front End Module ................................................................................................................ 28 4-3 Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification ................................................................................................ 42 4-4 Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification ................................................................................................ 43 4-5 Fault Mux Block Diagram ....................................................................................................... 51 4-6 PMBus Address Detection Method ............................................................................................ 52 4-7 ADC12 Control Block Diagram ................................................................................................. 53 4-8 Internal Temp Sensor............................................................................................................ 56 4-9 Simplified Current Sharing Circuitry ........................................................................................... 57 4 List of Figures Copyright © 2012, Texas Instruments Incorporated UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 List of Tables 2-1 Pin Functions ..................................................................................................................... 11 2-2 Pin Functions ..................................................................................................................... 14 3-1 I2C/SMBus/PMBus Timing Characteristics.................................................................................... 19 4-1 Interrupt Priority Table ........................................................................................................... 26 4-2 DPWM Interrupt Divide Ratio ................................................................................................... 31 Copyright © 2012, Texas Instruments Incorporated List of Tables 5 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Highly Integrated Digital Controller for Isolated Power Check for Samples: UCD3138 1 Introduction 1.1 Features 1 • Digital Control of up to 3 Independent – Synchronous Rectifier Soft On/Off Feedback Loops – Low IC Standby Power – Dedicated PID based hardware • Soft Start / Stop with and without Pre-bias – 2-pole/2-zero configurable • Fast Input Voltage Feed Forward Hardware – Non-Linear Control • Primary Side Voltage Sensing • Up to 16MHz Error Analog to Digital Converter • Copper Trace Current Sensing (EADC) • Flux and Phase Current Balancing for Non- – Configurable Resolution as Small as Peak Current Mode Control Applications 1mV/LSB • Current Share Bus Support – Automatic Resolution Selection – Analog Average – Up to 8x Oversampling – Master/Slave – Hardware Based Averaging (up to 8x) • Feature Rich Fault Protection Options – 14 bit Effective DAC – 7 High Speed Analog Comparators – Adaptive Sample Trigger Positioning – Cycle-by-Cycle Current Limiting • Up to 8 High Resolution Digital Pulse Width – Programmable Fault Counting Modulated (DPWM) Outputs – External Fault Inputs – 250ps Pulse Width Resolution – 10 Digital Comparators – 4ns Frequency Resolution – Programmable blanking time – 4ns Phase Resolution • Synchronization of DPWM waveforms between – Adjustable Phase Shift Between Outputs multiple UCD3138 devices – Adjustable Dead-band Between Pairs • 14 channel, 12 bit, 267 ksps General Purpose – Cycle-by-Cycle Duty Cycle Matching ADC with integrated – Up to 2MHz Switching Frequency – Programmable averaging filters • Configurable PWM Edge Movement – Dual sample and hold – Trailing Modulation • Internal Temperature Sensor – Leading Modulation • Fully Programmable High-Performance – Triangular Modulation 31.25MHz, 32-bit ARM7TDMI-S Processor • Configurable Feedback Control – 32 kByte (kB) Program Flash – Voltage Mode – 2 kB Data Flash with ECC – Average Current Mode – 4 kB Data RAM – Peak Current Mode Control – 4 kB Boot ROM Enables Firmware Boot-Load – Constant Current in the Field via I2C or UART – Constant Power • Communication Peripherals • Configurable Modulation Methods – I2C/PMBus – Frequency Modulation – 2 UARTs on UCD3138RGC (64-pin QFN) – Phase Shift Modulation – 1 UART on UCD3138RHA (40-pin QFN) – Pulse Width Modulation • JTAG Debug Port • Fast, Automatic and Smooth Mode Switching • Timer capture with selectable input pins – Frequency Modulation and PWM • Up to 5 Additional General Purpose Timers – Phase Shift Modulation and PWM • Built In Watchdog: BOD and POR • High Efficiency and Light Load Management • 64-pin QFN and 40-pin QFN packages – Burst Mode • Operating Temperature: –40°C to 125°C – Ideal Diode Emulation • Fusion_Digital_Power_Designer GUI Support 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2012, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 1.2 Applications • Power Supplies and Telecom Rectifiers • Power Factor Correction • Isolated dc-dc Modules 2 Overview 2.1 Description The UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single chip solution. The flexible nature of the UCD3138 makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of ac/dc and isolated dc/dc applications and reduce the solution component count in the IT and network infrastructure space. The UCD3138 is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customer’s development effort through offering best in class development tools, including application firmware, Code Composer Studio™ software development environment, and TI’s power development GUI which enables customers to configure and monitor key system parameters. At the core of the UCD3138 controller are the digital control loop peripherals, also known as Digital Power Peripherals (DPP). Each DPP implements a high speed digital control loop consisting of a dedicated Error Analog to Digital Converter (EADC), a PID based 2 pole–2 zero digital compensator and DPWM outputs with 250 ps pulse width resolution. The device also contains a 12-bit, 267ksps general purpose ADC with up to 14 channels, timers, interrupt control, JTAG debug and PMBus and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals and manages communications. The ARM microcontroller executes its program out of programmable flash memory as well as on-chip RAM and ROM. In addition to the FDPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, LLC and phase shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high resolution current sharing, hardware configurable soft start with pre bias, as well as several other features. Topology support has been optimized for voltage mode and peak current mode controlled phase shifted full bridge, single and dual phase PFC, bridgeless PFC, hard switched full bridge and half bridge, and LLC half bridge and full bridge. Copyright © 2012, Texas Instruments Incorporated Overview 7 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 2.2 Ordering Information PART NUMBER PIN COUNT PACKAGE SUPPLY TOP SIDE MARKING OPERATING TEMPERATURE RANGE, TA UCD3138RGCT 64 QFN 250 (Small Reel) UCD3138 –40°C to 125°C UCD3138RGCR 64 QFN 2000 (Large Reel) UCD3138 –40°C to 125°C UCD3138RHAT 40 QFN 250 (Small Reel) UCD3138 –40°C to 125°C UCD3138RHAR 40 QFN 2500 (large Reel) UCD3138 –40°C to 125°C 2.3 Product Selection Matrix FEATURE UCD3138 64 PIN UCD3138 40 PIN ARM7TDMI-S Core Processor 31.25 MHz 31.25 MHz High Resolution DPWM Outputs (250ps Resolution) 8 8 Number of High Speed Independent Feedback Loops (# Regulated Output 3 3 Voltages) 12-bit, 267ksps, General Purpose ADC Channels 14 7 Digital Comparators at ADC Outputs 4 4 Flash Memory (Program) 32 KB 32 KB Flash Memory (Data) 2 KB 2 KB Flash Security √ √ RAM 4 KB 4 KB DPWM Switching Frequency up to 2 MHz up to 2 MHz Programmable Fault Inputs 4 1 + 2(1) High Speed Analog Comparators with Cycle-by-Cycle Current Limiting 7(2) 6(2) UART (SCI) 2 1(1) PMBus √ √ Timers 4 (16 bit) and 1 (24 bit) 4 (16 bit) and 1 (24 bit) Timer PWM Outputs 2 1 Timer Capture Inputs 1 1(1) Watchdog √ √ On Chip Oscillator √ √ Power-On Reset and Brown-Out Reset √ √ JTAG √ √ Package Offering 64 Pin QFN (9mm x 9mm) 40 Pin QFN (6mm x 6mm) Sync IN and Sync OUT Functions √ √ Total GPIO (includes all pins with multiplexed functions such as, DPWM, Fault 30 18 Inputs, SCI, etc.) External Interrupts 1 0 (1) This number represents an alternate pin out that is programmable via firmware. See the UCD3138 Digital Power Peripherals Programmer’s Manual for details. (2) To facilitate simple OVP and UVP connections both comparators B and C are connected to the AD03 pin. 8 Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Front End 2 Analog Comparators Power and 1.8 V Voltage Regulator AD07 AD06 AD04 V33DIO /RESET SCI_RX0 SCI_TX0 PMBUS_CLK PMBUS_DATA AGND V33D BP18 FAULT3 FAULT2 TCAP TMS TDI TDO TCK EXT_INT FAULT1 FAULT0 PWM1 PWM0 SCI_RX1 SCI_TX1 PMBUS_CTRL PMBUS_ALERT SYNC DGND DPWM3B DPWM3A DPWM2B DPWM2A DPWM1B DPWM1A DPWM0B DPWM0A EAP0 EAN0 EAP1 EAN1 V33 A AD00 AD01 AD0 2 AD1 3 PID Based Filter 0 DPWM0 DPWM1 DPWM2 DPWM3 PID Based Filter 1 PID Based Filter 2 ADC_EXT_ TRIG ADC12 ADC12 Control Sequencing, Averaging, Digital Compare, Dual Sample and hold AD[13:0 ] A B C D E F G Current Share Analog, Average, Master/Slave AD03 AD0 2 AD1 3 AGND PMBus Timers 4 – 16 bit (PWM) 1 – 24 bit UART0 UART1 GPIO Control JTAG Loop MUX ARM7TDMI-S 32 bit, 31.25 MHz Memory PFLASH 32 kB DFLASH 2 kB RAM 4 kB ROM 4 kB Power On Reset Brown Out Detection Oscillator Internal Temperature Sensor Advanced Power Control Mode Switching, Burst Mode, IDE, Synchronous Rectification soft on & off Front End 1 Constant Power Constant Current Input Voltage Feed Forward Front End Averaging Digital Comparators Fault MUX & Control Cycle by Cycle Current Limit Digital Comparators DAC0 EADC X AFE Value Dither ! CPCC Filter x Ramp SAR/Prebias Abs() 2 Avg() AFE 23-AFE Peak Current Mode Control Comparator A0 EAP2 EAN2 Front End 0 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 2.4 Functional Block Diagram Copyright © 2012, Texas Instruments Incorporated Overview 9 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 (64 QFN) AGND 1 AD13 2 AD12 3 AD10 4 AD07 5 AD06 6 AD04 7 AD03 8 V33DIO 9 10 /RESET 11 ADC_EXT_TRIG/TCAP/SYNC/PWM0 12 SCI_RX0 13 SCI_TX0 14 DGND PMBUS_CLK/SCI_TX0 15 PMBUS_DATA/SCI_RX0 16 48 AGND 47 V33D 46 BP18 45 V33DIO 44 DGND 43 FAULT3 42 FAULT2 41 TCAP 40 TMS 39 TDI/SCI_RX0/PMBUS_CTRL/FAULT1 38 TDO/SCI_TX0/PMBUS_ALERT/FAULT0 37 TCK/TCAP/SYNC/PWM0 36 FAULT1 35 FAULT0 34 INT_EXT 33 DGND 32 PWM1 31 PWM0 30 SCI_RX1/PMBUS_CTRL 29 SCI_TX1/PMBUS_ALERT 28 PMBUS_CTRL 27 PMBUS_ALERT 26 SYNC/TCAP/ADC_EXT_TRIG/PWM0 25 DGND 24 DPWM3B 23 DPWM3A 22 DPWM2B 21 DPWM2A 20 DPWM1B 19 DPWM1A 18 DPWM0B 17 DPWM0A 64 AGND 63 EAP0 62 EAN0 61 EAP1 60 EAN1 59 EAP2 58 EAN2 57 AGND 56 V33A 55 AD00 54 AD01 53 AD02 52 AD05 51 AD08 50 AD09 49 AD11 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 2.5 UCD3138 64 QFN – Pin Assignments 10 Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 2.6 Pin Functions Additional pin functionality is specified in the following table. Table 2-1. Pin Functions ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO? 1 AGND Analog ground 2 AD13 12-bit ADC, Ch 13, comparator E, I-share DAC output 3 AD12 12-bit ADC, Ch 12 4 AD10 12-bit ADC, Ch 10 5 AD07 12-bit ADC, Ch 7, Connected to comparator F and reference DAC output to comparator G 6 AD06 12-bit ADC, Ch 6, Connected to comparator F DAC output 7 AD04 12-bit ADC, Ch 4, Connected to comparator D DAC output 8 AD03 12-bit ADC, Ch 3, Connected to comparator B and C 9 V33DIO Digital I/O 3.3V core supply 10 DGND Digital ground 11 RESET Device Reset Input, active low 12 ADC_EXT_TRIG ADC conversion external trigger input TCAP SYNC PWM0 Yes 13 SCI_RX0 SCI RX 0 Yes 14 SCI_TX0 SCI TX 0 Yes 15 PMBUS_CLK PMBUS Clock (Open Drain) SCI TX 0 Yes 16 PMBUS_DATA PMBus data (Open Drain) SCI RX 0 Yes 17 DPWM0A DPWM 0A output Yes 18 DPWM0B DPWM 0B output Yes 19 DPWM1A DPWM 1A output Yes 20 DPWM1B DPWM 1B output Yes 21 DPWM2A DPWM 2A output Yes 22 DPWM2B DPWM 2B output Yes 23 DPWM3A DPWM 3A output Yes 24 DPWM3B DPWM 3B output Yes 25 DGND Digital ground 26 SYNC DPWM Synchronize pin TCAP ADC_EXT_ PWM0 Yes TRIG 27 PMBUS_ALERT PMBus Alert (Open Drain) Yes 28 PMBUS_CTRL PMBus Control (Open Drain) Yes 29 SCI_TX1 SCI TX 1 PMBUS_AL Yes ERT 30 SCI_RX1 SCI RX 1 PMBUS_CT Yes RL 31 PWM0 General purpose PWM 0 Yes 32 PWM1 General purpose PWM 1 Yes 33 DGND Digital ground 34 INT_EXT External Interrupt Yes 35 FAULT0 External fault input 0 Yes 36 FAULT1 External fault input 1 Yes 37 TCK JTAG TCK TCAP SYNC PWM0 Yes 38 TDO JTAG TDO SCI_TX0 PMBUS_AL FAULT0 Yes ERT 39 TDI JTAG TDI SCI_RX0 PMBUS_CT FAULT1 Yes RL 40 TMS JTAG TMS Yes 41 TCAP Timer capture input Yes 42 FAULT2 External fault input 2 Yes 43 FAULT3 External fault input 3 Yes Copyright © 2012, Texas Instruments Incorporated Overview 11 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Table 2-1. Pin Functions (continued) ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO? 44 DGND Digital ground 45 V33DIO Digital I/O 3.3V core supply 46 BP18 1.8V Bypass 47 V33D Digital 3.3V core supply 48 AGND Substrate analog ground 49 AGND Analog ground 50 EAP0 Channel #0, differential analog voltage, positive input 51 EAN0 Channel #0, differential analog voltage, negative input 52 EAP1 Channel #1, differential analog voltage, positive input 53 EAN1 Channel #1, differential analog voltage, negative input 54 EAP2 Channel #2, differential analog voltage, positive input 55 EAN2 Channel #2, differential analog voltage, negative input 56 AGND Analog ground 57 V33A Analog 3.3V supply 58 AD00 12-bit ADC, Ch 0, Connected to current source 59 AD01 12-bit ADC, Ch 1, Connected to current source 60 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share 61 AD05 12-bit ADC, Ch 5 62 AD08 12-bit ADC, Ch 8 63 AD09 12-bit ADC, Ch 9 64 AD11 12-bit ADC, Ch 11 12 Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 (40 QFN) AGND 1 2 3 4 5 AD13 6 AD06 7 AD04 8 AD03 9 DGND 10 /RESET 11 ADC_EXT_TRIG/TCAP/SYNC/PWM0 12 13 14 15 PMBUS_CLK/SCI_TX0 16 PMBUS_DATA/SCI_RX0 AGND BP18 DGND V33D 40 39 TMS 38 TDI/SCI_RX0/PMBUS_CTRL/FAULT1 37 TDO/SCI_TX0/PMBUS_ALERT/FAULT0 36 TCK/TCAP/SYNC/PWM0 35 34 33 FAULT2 32 31 AGND 30 29 28 27 26 DPWM3B 25 DPWM3A 24 PMBUS_CTRL 23 PMBUS_ALERT 22 DPWM2B 21 DPWM2A 20 DPWM1B 19 DPWM1A 18 DPWM0B 17 DPWM0A EAP0 EAN0 EAP1 EAN1 EAP2 AGND V33A AD00 AD01 AD02 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 2.7 UCD3138 40 QFN – Pin Assignments Copyright © 2012, Texas Instruments Incorporated Overview 13 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 2.8 Pin Functions Additional pin functionality is specified in the following table. Table 2-2. Pin Functions ALTERNATE ASSIGNMENT PIN NAME PRIMARY ASSIGNMENT CONFIGURABLE NO. 1 NO. 2 NO. 3 AS A GPIO? 1 AGND Analog ground 2 AD13 12-bit ADC, Ch 13, Connected to comparator E, I-share 3 AD06 12-bit ADC, Ch 6, Connected to comparator F 4 AD04 12-bit ADC, Ch 4, Connected to comparator D 5 AD03 12-bit ADC, Ch 3, Connected to comparator B & C 6 DGND Digital ground 7 RESET Device Reset Input, active low 8 ADC_EXT_TRIG ADC conversion external trigger input TCAP SYNC PWM0 Yes 9 PMBUS_CLK PMBUS Clock (Open Drain) SCI_TX0 Yes 10 PMBUS_DATA PMBus data (Open Drain) SCI_RX0 Yes 11 DPWM0A DPWM 0A output Yes 12 DPWM0B DPWM 0B output Yes 13 DPWM1A DPWM 1A output Yes 14 DPWM1B DPWM 1B output Yes 15 DPWM2A DPWM 2A output Yes 16 DPWM2B DPWM 2B output Yes 17 DWPM3A DPWM 3A output Yes 18 DPWM3B DPWM 3B output Yes 19 PMBUS_ALERT PMBus Alert (Open Drain) Yes 20 PMBUS_CTRL PMBus Control (Open Drain) Yes 21 TCK JTAG TCK TCAP SYNC PWM0 Yes 22 TDO JTAG TDO SCI_TX0 PMBUS_A FAULT0 Yes LERT 23 TDI JTAG TDI SCI_RX0 PMBUS_C FAULT1 Yes TRL 24 TMS JTAG TMS Yes 25 FAULT2 External fault input 2 Yes 26 DGND Digital ground 27 V33D Digital 3.3V core supply 28 BP18 1.8V Bypass 29 AGND Substrate analog ground 30 AGND Analog ground 31 EAP0 Channel #0, differential analog voltage, positive input 32 EAN0 Channel #0, differential analog voltage, negative input 33 EAP1 Channel #1, differential analog voltage, positive input 34 EAN1 Channel #1, differential analog voltage, negative input 35 EAP2 Channel #2, differential analog voltage, positive input 36 AGND Analog ground 37 V33A Analog 3.3V supply 38 AD00 12-bit ADC, Ch 0, Connected to current source 39 AD01 12-bit ADC, Ch 1, Connected to current source 40 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share 14 Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 3 Electrical Specifications 3.1 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT MIN MAX V33D V33D to DGND –0.3 3.8 V V33DIO V33DIO to DGND –0.3 3.8 V V33A V33A to AGND –0.3 3.8 V |DGND – AGND| Ground difference 0.3 V All Pins, excluding AGND(2) Voltage applied to any pin –0.3 3.8 V TOPT Junction Temperature –40 125 °C TSTG Storage temperature –55 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Referenced to DGND 3.2 THERMAL INFORMATION UCD3138 UCD3138 THERMAL METRIC(1) 64 PIN QFN 40 PIN UNITS QFN θJA Junction-to-ambient thermal resistance (2) 25.1 31.8 θJCtop Junction-to-case (top) thermal resistance (3) 10.5 18.5 θJB Junction-to-board thermal resistance (4) 4.6 6.8 °C/W ψJT Junction-to-top characterization parameter(5) 0.2 0.2 ψJB Junction-to-board characterization parameter (6) 4.6 6.7 θJCbot Junction-to-case (bottom) thermal resistance (7) 1.2 1.8 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 3.3 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT V33D Digital power 3.0 3.3 3.6 V V33DIO Digital I/O power 3.0 3.3 3.6 V33A Analog power 3.0 3.3 3.6 V TJ Junction temperature -40 - 125 °C Copyright © 2012, Texas Instruments Incorporated Electrical Specifications 15 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 3.4 ELECTRICAL CHARACTERISTICS V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT Measured on V33A. The device is I33A powered up but all ADC12 and EADC 6.3 mA sampling is disabled I33DIO All GPIO and communication pins are 0.35 mA open I33D ROM program execution 60 mA I33D Flash programming in ROM mode 70 mA The device is in ROM mode with all I33 DPWMs enabled and switching at 2 100 mA MHz. The DPWMs are all unloaded. ERROR ADC INPUTS EAP, EAN EAP – AGND –0.15 1.998 V EAP – EAN –0.256 1.848 V Typical error range AFE = 0 –256 248 mV AFE = 3 0.8 1 1.20 mV AFE = 2 1.7 2 2.30 mV EAP – EAN Error voltage digital resolution AFE = 1 3.55 4 4.45 mV AFE = 0 6.90 8 9.10 mV REA Input impedance (See Figure 4-1) AGND reference 0.5 MΩ IOFFSET Input offset current (See Figure 4-1) –5 5 μA Input voltage = 0 V at AFE = 0 –2 2 LSB Input voltage = 0 V at AFE = 1 –2.5 2.5 LSB EADC Offset Input voltage = 0 V at AFE = 2 –3 -3 LSB Input voltage = 0 V at AFE = 3 –4 4 LSB Sample Rate 16 MHz Analog Front End Amplifier Bandwidth 100 MHz Gain See Figure 4-2 1 V/V A0 Minimum output voltage 100 mV EADC DAC DAC range 0 1.6 V VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV VREF DAC reference resolution With 4 bit dithering enabled 97.6 μV INL –3.0 3.0 LSB DNL Does not include MSB transition –2.1 1.6 LSB DNL at MSB transition -1.4 LSB DAC reference voltage 1.58 1.61 V τ Settling Time From 10% to 90% 250 ns ADC12 IBIAS Bias current for PMBus address pins 9.5 10.5 μA Measurement range for voltage monitoring 0 2.5 V Internal ADC reference voltage –40°C to 125°C 2.475 2.500 2.525 V –40°C to 25°C –0.4 Change in Internal ADC reference from 25°C to 85°C –1.8 mV 25°C reference voltage(1) 25°C to 125°C –4.2 (1) As designed and characterized. Not 100% tested in production. 16 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 ELECTRICAL CHARACTERISTICS (continued) V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT ADC12 INL integral nonlinearity(1) +/-2.5 LSB ADC12 DNL differential nonlinearity(1) ADC_SAMPLINGSEL = 6 for all ADC12 –0.7/+2.5 LSB ADC Zero Scale Error data, 25 °C to 125 °C –7 7 mV ADC Full Scale Error –35 35 mV Input bias 2.5 V applied to pin 400 nA Input leakage resistance(1) ADC_SAMPLINGSEL= 6 or 0 1 MΩ Input Capacitance(1) 10 pF ADC single sample conversion time(1) ADC_SAMPLINGSEL= 6 or 0 3.9 μs DIGITAL INPUTS/OUTPUTS(2) (3) V DGND OL Low-level output voltage(4) IOH = 4 mA, V33DIO = 3 V + 0.25 V V V33DIO OH High-level output voltage (4) IOH = –4 mA, V33DIO = 3 V – 0.6 V VIH High-level input voltage V33DIO = 3 V 2.1 V VIL Low-level input voltage V33DIO = 3 V 1.1 V IOH Output sinking current 4 mA IOL Output sourcing current –4 mA SYSTEM PERFORMANCE TWD Watchdog time out range Total time is: TWD x 14.6 17 20.5 ms (WDCTRL.PERIOD+1) Time to disable DPWM output based on High level on FAULT pin 70 ns active FAULT pin signal Processor master clock (MCLK) 31.25 MHz tDelay Digital compensator delay(5) (1 clock = 32ns) 6 clocks VDD Slew minimum VDD slew rate(6) VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms t(reset) Pulse width needed at reset(6) 10 μs Retention period of flash content (data TJ = 25°C 100 years retention and program) Program time to erase one page or block in 20 ms data flash or program flash Program time to write one word in data 20 μs flash or program flash f(PCLK) Internal oscillator frequency 240 250 260 MHz Sync-in/sync-out pulse width Sync pin 256 ns Flash Read 1 MCLKs Flash Write 20 μs I Current share current source (See SHARE Figure 4-9) 238 259 μA RSHARE Current share resistor (See Figure 4-9) 9.75 10.3 kΩ POWER ON RESET AND BROWN OUT (V33D pin, See Figure 3-3) VGH Voltage good High 2.7 V VGL Voltage good Low 2.5 V Vres Voltage at which IReset signal is valid 0.8 V (2) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset. (3) On the 40 pin package V33DIO is connected to V33D internally. (4) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH. (5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response. (6) As designed and characterized. Not 100% tested in production. Copyright © 2012, Texas Instruments Incorporated Electrical Specifications 17 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT T Time delay after Power is good or POR RESET* relinquished 1 ms Brownout Internal signal warning of brownout 2.9 V conditions TEMPERATURE SENSOR(7) VTEMP Voltage range of sensor 1.46 2.44 V Voltage resolution Volts/°C 5.9 mV/ºC Temperature resolution Degree C per bit 0.1034 ºC/LSB Accuracy(7) (8) -40°C to 125°C –10 ±5 10 ºC Temperature range -40°C to 125°C –40 125 ºC ITEMP Current draw of sensor when active 30 μA TON Turn on time / settling time of sensor 100 μs VAMB Ambient temperature Trimmed 25°C reading 1.85 V ANALOG COMPARATOR DAC Reference DAC Range 0 2.5 V Reference Voltage 2.478 2.5 2.513 V Bits 7 bits INL(7) –0.42 0.21 LSB DNL(7) 0.06 0.12 LSB Offset –5.5 19.5 mV Time to disable DPWM output based on 0 V to 2.5 V step input on the analog 150 ns comparator.(9) Reference DAC buffered output load(10) 0.5 1 mA Buffer offset (-0.5 mA) 4.6 8.3 mV Buffer offset (1.0 mA) –0.05 17 mV (7) Characterized by design and not production tested. (8) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy. (9) As designed and characterized. Not 100% tested in production. (10) Available from reference DACs for comparators D, E, F and G. 18 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 3.5 PMBus/SMBus/I2C Timing The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Table 3-1, Figure 3-1, and Figure 3-2. The numbers in Table 3-1 are for 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz), and fast mode plus (1 MHz). Table 3-1. I2C/SMBus/PMBus Timing Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted) fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 1000 kHz fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 1000 kHz t(BUF) Bus free time between start and stop 1.3 ms t(HD:STA) Hold time after (repeated) start 0.6 ms t(SU:STA) Repeated start setup time 0.6 ms t(SU:STO) Stop setup time 0.6 ms t(HD:DAT) Data hold time Receive mode 0 ns t(SU:DAT) Data setup time 100 ns t(TIMEOUT) Error signal/detect(1) 35 ms t(LOW) Clock low period 1.3 ms t(HIGH) Clock high period(2) 0.6 ms t Cumulative clock low slave extend (LOW:SEXT) time(3) 25 ms t 20 + 0.1 f Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) Cb(4) 300 ns t 20 + 0.1 r Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) Cb(4) 300 ns Cb Total capacitance of one bus line 400 pF (1) The device times out when any clock low exceeds t(TIMEOUT). (2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0). (3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (4) Cb (pF) Figure 3-1. I2C/SMBus/PMBus Timing Diagram Copyright © 2012, Texas Instruments Incorporated Electrical Specifications 19 Submit Documentation Feedback Product Folder Link(s): UCD3138 TPOR undefined V33D IReset 3.3 V TPOR VGH VGL Vres t t Brown Out UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Figure 3-2. Bus Timing in Extended Mode 3.6 Power On Reset (POR) / Brown Out Reset (BOR) Figure 3-3. Power On Reset (POR) / Brown Out Reset (BOR) VGH – This is the V33D threshold where the internal power is declared good. The UCD3138 comes out of reset when above this threshold. VGL – This is the V33D threshold where the internal power is declared bad. The device goes into reset when below this threshold. Vres – This is the V33D threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state. IReset – This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC high. TPOR – The time delay from when VGH is exceeded to when the device comes out of reset. Brown – This is the V33D voltage threshold at which the device sets the brown out status bit. In Out addition an interrupt can be triggered if enabled. 20 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 DPWM FE_CTRL PCM ADC12 PMBUS TIMER CPCC FILTER SCI SCI GIO 0 1 2 3 4 5 6 UCD3138 Function Power Savings (mA) G001 4.9 2.57 1.2 0.8 0.4 0.4 0.2 0.2 0.1 0.1 0 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 3.7 Typical Clock Gating Power Savings Power disable control register provides control bits that can enable or disable arrival of clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more. All these controls are enabled as default. If a specific peripheral is not used in a specific application the clock gate can be disabled in order to block the propagation of clock signal to that peripheral and therefore reduce the overall current consumption of the device. Copyright © 2012, Texas Instruments Incorporated Electrical Specifications 21 Submit Documentation Feedback Product Folder Link(s): UCD3138 2.475 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 −40 −20 0 20 40 60 80 100 120 Temperature (°C) ADC12 Reference G003b ADC12 2.5-V Reference 1.92 1.96 2 2.04 2.08 −40 −20 0 20 40 60 80 100 120 Temperature (°C) 2-MHZ Reference G004b UCD3138 Oscillator Frequency −4 −2 0 2 4 6 8 −40 −20 0 20 40 60 80 100 120 Temperature (°C) ADC12 Error (LSB) G002b ADC12 Temperature Sensor Measurement Error 1.4 1.6 1.8 2.0 2.2 2.4 2.6 −60 −40 −20 0 20 40 60 80 100 120 140 160 Temperature (°C) Sensor Voltage (V) G006b ADC12 Measurement Temperature Sensor Voltage 1.6 1.7 1.8 1.9 2 2.1 −40 −20 0 20 40 60 80 100 120 Temperature (°C) EADC LSB Size (mV) G005a UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 3.8 Typical Temperature Characteristics Figure 3-4. EADC LSB Size with 4X Gain (mV) vs. Temperature Figure 3-5. ADC12 Measurement Temperature Figure 3-7. ADC12 Temperature Sensor Sensor Voltage vs. Temperature Measurement Error vs. Temperature Figure 3-6. ADC12 2.5-V Reference vs. Figure 3-8. UCD3138 Oscillator Frequency (2MHz Temperature Reference, Divided Down from 250MHz) vs. Temperature 22 Electrical Specifications Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4 Functional Overview 4.1 ARM Processor The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The Thumb instruction allows for higher code density equivalent to a 16-bit microprocessor, with the performance of the 32-bit microprocessor. The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter. A JTAG port is also available for firmware debugging. 4.2 Memory The UCD3138 (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the memory modules. All of the memory module addresses are sequentially aligned along the same address range. This applies to program flash, data flash, ROM and all other peripherals. Within the UCD3138 architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the ROM code branches to the main FLASH-program execution. UCD3138 also supports customization of the boot program by allowing an alternative boot routine to be executed from program FLASH. This feature enables assignment of a unique address to each device; therefore, enabling firmware reprogramming even when several devices are connected on the same communication bus. Two separate FLASH memory areas are present inside the device. The 32 kB Program FLASH is organized as an 8 k x 32 bit memory block and is intended to be for the firmware program. The block is configured with page erase capability for erasing blocks as small as 1kB per page, or with a mass erase for erasing the entire program FLASH array. The FLASH endurance is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data FLASH array is organized as a 512 x 32 bit memory (32 byte page size). The Data FLASH is intended for firmware data value storage and data logging. Thus, the Data FLASH is specified as a high endurance memory of 20 k cycles with embedded error correction code (ECC). For run time data storage and scratchpad memory, a 4 kB RAM is available. The RAM is organized as a 1 k x 32 bit array. 4.2.1 CPU Memory Map and Interrupts When the device comes out of power-on-reset, the data memories are mapped to the processor as follows: 4.2.1.1 Memory Map (After Reset Operation) Address Size Module 0x0000_0000 – 0x0000_FFFF In 16 repeated blocks of 4K each 16 X 4K Boot ROM 0x0001_0000 – 0x0001_7FFF 32K Program Flash 0x0001_8800 – 0x0001_8FFF 2K Data Flash 0x0001_9000 – 0x0001_9FFF 4K Data RAM Copyright © 2012, Texas Instruments Incorporated Functional Overview 23 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 4.2.1.2 Memory Map (Normal Operation) Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as follows: Address Size Module 0x0000_0000 – 0x0000_7FFF 32K Program Flash 0x0001_0000 – 0x0001_AFFF 4K Boot ROM 0x0001_8800 – 0x0001_8FFF 2K Data Flash 0x0001_9000 – 0x0001_9FFF 4K Data RAM 4.2.1.3 Memory Map (System and Peripherals Blocks) Address Size Module 0x0002_0000 - 0x0002_00FF 256 Loop Mux 0x0003_0000 - 0x0003_00FF 256 Fault Mux 0x0004_0000 - 0x0004_00FF 256 ADC 0x0005_0000 - 0x0005_00FF 256 DPWM 3 0x0006_0000 - 0x0006_00FF 256 Filter 2 0x0007_0000 - 0x0007_00FF 256 DPWM 2 0x0008_0000 - 0x0008_00FF 256 Front End/Ramp I/F 2 0x0009_0000 - 0x0009_00FF 256 Filter 1 0x000A_0000 - 0x000A_00FF 256 DPWM 1 0x000B_0000 – 0x000B_00FF 256 Front End/Ramp I/F 1 0x000C_0000 - 0x000C_00FF 256 Filter 0 0x000D_0000 - 0x000D_00FF 256 DPWM 0 0x000E_0000 - 0x000E_00FF 256 Front End/Ramp I/F 0 0xFFF7_EC00 - 0xFFF7_ECFF 256 UART 0 0xFFF7_ED00 - 0xFFF7_EDFF 256 UART 1 0xFFF7_F000 - 0xFFF7_F0FF 256 Miscellaneous Analog Control 0xFFF7_F600 - 0xFFF7_F6FF 256 PMBus Interface 0xFFF7_FA00 - 0xFFF7_FAFF 256 GIO 0xFFF7_FD00 - 0xFFF7_FDFF 256 Timer 0xFFFF_FD00 - 0xFFFF_FDFF 256 MMC 0xFFFF_FE00 - 0xFFFF_FEFF 256 DEC 0xFFFF_FF20 - 0xFFFF_FF37 23 CIM 0xFFFF_FF40 - 0xFFFF_FF50 16 PSA 0xFFFF_FFD0 - 0xFFFF_FFEC 28 SYS The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s guide for each peripheral. 4.2.2 Boot ROM The UCD3138 incorporates a 4k boot ROM. This boot ROM includes support for: • Program download through the PMBus • Device initialization • Examining and modifying registers and memory • Verifying and executing program FLASH automatically • Jumping to a customer defined boot program 24 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it also jumps to location 0 in the program flash. This permits full automated program memory checking, when there is no need for a custom boot program. If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface These functions can be used to read and write to all memory locations in the UCD3138. Typically they are used to download a program to Program Flash, and to command its execution 4.2.3 Customer Boot Program As described above, it is possible to generate a user boot program using 2 kB or more of the Program Flash. This can support things which the Boot ROM does not support, including: • Program download via UART – useful especially for applications where the UCD3138 is isolated from the host (e.g., PFC) • Encrypted download – useful for code security in field updates. 4.2.4 Flash Management The UCD3138 offers a variety of features providing for easy prototyping and easy flash programming. At the same time, high levels of security are possible for production code, even with field updates. Standard firmware will be provided for storing multiple copies of system parameters in data flash. This is minimizes the risk of losing information if programming is interrupted. 4.3 System Module The System Module contains the interface logic and configuration registers to control and configure all the memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder, memory management controller, system management unit, central interrupt unit, and clock control unit. 4.3.1 Address Decoder (DEC) The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map addresses are selectable through configurable register settings. These memory selects can be configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection. 4.3.2 Memory Management Controller (MMC) The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space decoding. 4.3.3 System Management (SYS) The SYS unit contains the software access protection by configuring user privilege levels to memory or peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also available. Copyright © 2012, Texas Instruments Incorporated Functional Overview 25 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 4.3.4 Central Interrupt Module (CIM) The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first action in the interrupt service routine. The request channels are maskable, allowing individual channels to be selectively disabled or enabled. Table 4-1. Interrupt Priority Table NAME MODULE COMPONENT OR DESCRIPTION PRIORITY REGISTER BRN_OUT_INT Brownout Brownout interrupt 0 (Lowest) EXT_INT External Interrupts Interrupt on external input pin 1 WDRST_INT Watchdog Control Interrupt from watchdog exceeded (reset) 2 WDWAKE_INT Watchdog Control Wakeup interrupt when watchdog equals half of set 3 watch time SCI_ERR_INT UART or SCI Control UART or SCI error Interrupt. Frame, parity or overrun 4 SCI_RX_0_INT UART or SCI Control UART0 RX buffer has a byte 5 SCI_TX_0_INT UART or SCI Control UART0 TX buffer empty 6 SCI_RX_1_INT UART or SCI Control UART1 RX buffer has a byte 7 SCI_TX_1_INT UART or SCI Control UART1 TX buffer empty 8 PMBUS_INT PMBus related interrupt 9 DIG_COMP_INT 12-bit ADC Control Digital comparator interrupt 10 “Prebias complete”, “Ramp Delay Complete”, “Ramp FE0_INT Front End 0 Complete”, “Load Step Detected”, 11 “Over-Voltage Detected”, “EADC saturated” “Prebias complete”, “Ramp Delay Complete”, “Ramp FE1_INT Front End 1 Complete”, “Load Step Detected”, 12 “Over-Voltage Detected”, “EADC saturated” “Prebias complete”, “Ramp Delay Complete”, “Ramp FE2_INT Front End 2 Complete”, “Load Step Detected”, 13 “Over-Voltage Detected”, “EADC saturated” PWM3_INT 16-bit Timer PWM 3 16-bit Timer PWM3 counter overflow or compare interrupt 14 PWM2_INT 16-bit Timer PWM 2 16-bit Timer PWM2 counter Overflow or compare 15 interrupt PWM1_INT 16-bit Timer PWM 1 16-bit Timer PWM1 counter overflow or compare interrupt 16 PWM0_INT 16-bit timer PWM 0 16-bit Timer PWM1 counter overflow or compare interrupt 17 OVF24_INT 24-bit Timer Control 24-bit Timer counter overflow interrupt 18 CAPTURE_1_INT 24-bit Timer Control 24-bit Timer capture 1 interrupt 19 COMP_1_INT 24-bit Timer Control 24-bit Timer compare 1 interrupt 20 CAPTURE_0_INT 24-bit Timer Control 24-bit Timer capture 0 interrupt 21 COMP_0_INT 24-bit Timer Control 24-bit Timer compare 0 interrupt 22 CPCC_INT Constant Power Constant Current Mode switched in CPCC module Flag needs to be read 23 for details ADC_CONV_INT 12-bit ADC Control ADC end of conversion interrupt 24 Analog comparator interrupts, Over-Voltage detection, FAULT_INT Fault Mux Interrupt Under-Voltage detection, 25 LLM load step detection 26 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Error ADC (Front End) Filter Digital PWM EAP EAN DPWMA DPWMB UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Table 4-1. Interrupt Priority Table (continued) NAME MODULE COMPONENT OR DESCRIPTION PRIORITY REGISTER DPWM3 DPWM3 Same as DPWM1 26 DPWM2 DPWM2 Same as DPWM1 27 1) Every (1-256) switching cycles DPWM1 DPWM1 2) Fault Detection 28 3) Mode switching DPWM0 DPWM0 Same as DPWM1 29 EXT_FAULT_INT External Faults Fault pin interrupt 30 SYS_SSI_INT System Software System software interrupt 31 (highest) 4.4 Peripherals 4.4.1 Digital Power Peripherals At the core of the UCD3138 controller are 3 Digital Power Peripherals (DPP). Each DPP can be configured to drive from one to eight DPWM outputs. Each DPP consists of: • Differential input error ADC (EADC) with sophisticated controls • Hardware accelerated digital 2-pole/2-zero PID based compensator • Digital PWM module with support for a variety of topologies These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of supporting functions like input voltage feed forward, current mode control, and constant current/constant power, etc.. The simplest configuration is shown in the following figure: 4.4.1.1 Front End Figure 4-1 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, etc. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automatically adds the DAC value to the error. It is possible to operate the controller in a peak current mode control configuration. In this mode topologies like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in the Electrical Characteristics table. Copyright © 2012, Texas Instruments Incorporated Functional Overview 27 Submit Documentation Feedback Product Folder Link(s): UCD3138 EAP0 EAN0 DAC0 EADC 4 bit dithering gives 14 bits of effective resolution 97.65625 μV/LSB effective resolution X 6 bit ADC 8 mV/LSB Signed 9 bit result (error) 1 mV /LSB AFE_GAIN 10 bit DAC 1.5625 mV/LSB Value Dither S CPCC Filter x Ramp SAR/Prebias Absolute Value Calculation Averaging 10 bit result 1.5625 mV/LSB 2 3-AFE_GAIN Peak Current Mode Comparator Peak Current Detected A0 2 AFE_GAIN IOFFSET REA EAP EAN AGND AGND IOFFSET REA Front End Differential Amplifier UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Figure 4-1. Input Stage of EADC Module Figure 4-2. Front End Module 4.4.1.2 DPWM Module The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138 system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations. 28 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the necessary duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON time is 250 psec. Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of the DPWM outputs for multiple power stages can be tightly controlled. The DPWM logic is probably the most complex of the Digital Peripherals. It takes the output of the compensator and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section. Each DPWM module supports the following features: • Dedicated 14 bit time-base with period and frequency control • Shadow period register for end of period updates. • Quad-event control registers (A and B, rising and falling) (Events 1-4) – Used for on/off DPWM duty ratio updates. • Phase control relative to other DPWM modules • Sample trigger placement for output voltage sensing at any point during the DPWM cycle. • Support for 2 independent edge placement DPWM outputs (same frequency or period setting) • Dead-time between DPWM A and B outputs • High Resolution capabilities – 250 ps • Pulse cycle adjustment of up to ±8.192 μs ( 32768 × 250 ps) • Active high/ active low output polarity selection • Provides events to trigger both CPU interrupts and start of ADC12 conversions. 4.4.1.3 DPWM Events Each DPWM can control the following timing events: 1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship to the DPWM period. The programmed value set in the register should be one fourth of the value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the circuitry runs at one fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate. 2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation). 3. Period–low resolution switching period count. (count of PCLK cycles) 4. Event 1–count offset for rising DPWM A event. (PCLK cycles) 5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts. 6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts. 7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts. 8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments. Copyright © 2012, Texas Instruments Incorporated Functional Overview 29 Submit Documentation Feedback Product Folder Link(s): UCD3138 Start of Period Period Counter Start of Period Period Sample Trigger 1 DPWM Output A Cycle Adjust A (High Resolution) Event 2 (High Resolution) Event 1 Event 3 (High Resolution) Cycle Adjust B (High Resolution) Event 4 (High Resolution) DPWM Output B Blanking A Begin Blanking A End Blanking B Begin Blanking B End Phase Trigger Sample Trigger 2 To Other Modules To Other Modules Multi Mode Open Loop Events which change with DPWM mode: DPWM A Rising Edge = Event 1 DPWM A Falling Edge = Event 2 + Cycle Adjust A DPWM B Rising Edge = Event 3 DPWM B Falling Edge = Event 4 + Cycle Adjust B Phase Trigger = Phase Trigger Register value Events always set by their registers, regardless of mode: Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4. The drawing above is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed. 30 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWM modes are described below. 4.4.1.4 High Resolution DPWM Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138 DPWM can generate waveforms with resolutions as small as 250 ps. This is 16 times the resolution of the clock driving the DPWM module. This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each. The high resolution section of DPWM can be enabled or disabled, also the resolution can be defined in several steps between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN , HIRES_SCALE and ALL_PHASE_CLK_ENA inside the DPWM Control Register 1. See the Power Peripherals programmer’s manual for details. 4.4.1.5 Over Sampling The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling, and the “11” triggers over sampling at 8X. 4.4.1.6 DPWM Interrupt Generation The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence synchronization. Table 4-2 outlines the divide ratios that can be programmed. 4.4.1.7 DPWM Interrupt Scaling/Range Table 4-2. DPWM Interrupt Divide Ratio Interrupt Divide Interrupt Divide Interrupt Divide Switching Period Number of 32 MHz Setting Count Count (hex) Frames (assume 1MHz Processor Cycles loop) 1 0 00 1 32 2 1 01 2 64 3 3 03 4 128 4 7 07 8 256 5 15 0F 16 512 6 31 1F 32 1024 7 47 2F 48 1536 8 63 3F 64 2048 9 79 4F 80 2560 10 95 5F 96 3072 11 127 7F 128 4096 12 159 9F 160 5120 13 191 BF 192 6144 14 223 DF 224 7168 15 255 FF 256 8192 Copyright © 2012, Texas Instruments Incorporated Functional Overview 31 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 4.5 DPWM Modes of Operation The DPWM is a complex logic system which is highly configurable to support several different power supply topologies. The discussion below will focus primarily on waveforms, timing and register settings, rather than on logic design. The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts over again. The DPWM logic causes transitions in many digital signals when the period counter hits the target value for that signal. 4.5.1 Normal Mode In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies, among others. Here is a drawing of the Normal Mode waveforms: 32 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Start of Period Period Counter Start of Period Period DPWM Output A Cycle Adjust A (High Resolution) Filter Duty (High Resolution) Event 1 Event 3 – Event 2 (High Res) Event 4 (High Res) DPWM Output B Blanking B Begin Blanking B End Phase Trigger Sample Trigger 2 To Other Modules Normal Mode Closed Loop Events which change with DPWM mode: DPWM A Rising Edge = Event 1 DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2) DPWM B Falling Edge = Event 4 Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End Filter controlled edge Sample Trigger 1 Blanking A Begin Blanking A End To Other Modules Adaptive Sample Trigger A Adaptive Sample Trigger B UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for external delays, such as MOSFET and gate driver turn on times. Copyright © 2012, Texas Instruments Incorporated Functional Overview 33 Submit Documentation Feedback Product Folder Link(s): UCD3138 Phase Shift Phase Trigger = Phase Trigger Register value or Filter Duty DPWM0 Start of Period Period Counter DPWM0 Start of Period DPWM1 Start of Period Period Counter DPWM1 Start of Period UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges are dynamic, so blanking is more difficult. Cycle Adjust B has no effect in Normal Mode. 4.6 Phase Shifting In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase shift signal has two possible sources. It can come from the Phase Shift Register. This provides a fixed value, which is useful for an interleaved PFC, for example. The phase shift value can also come from the filter output. In this case, the changes in the filter output causes changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridge topologies. The following figure shows the mechanism of phase shift: 34 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Adaptive Sample Trigger B Start of Period Period Counter Start of Period Period Adaptive Sample Trigger A DPWM Output A Cycle Adjust A (High Resolution) Filter Duty (High Resolution) Event 1 To Other Modules Multi Mode Closed Loop Events which change with DPWM mode: DPWM A Rising Edge = Event 1 DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register DPWM B Rising Edge = Event 3 DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End Filter controlled edge Event 3 (High Resolution) Cycle Adjust B (High Resolution) Filter Duty (High Resolution) DPWM Output B Blanking B Begin Blanking B End Phase Trigger Sample Trigger 2 To Other Modules Sample Trigger 1 Blanking A Begin Blanking A End UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.7 DPWM Multiple Output Mode Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and with different cycle adjusts for each phase. Here is a diagram for Multi-Mode: Copyright © 2012, Texas Instruments Incorporated Functional Overview 35 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Event 2 and Event 4 are not relevant in Multi mode. DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse width operation is possible. DPWMA cannot cross over the period boundary. Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking this rising edge. And, of course, Cycle Adjust B is usable on DPWM B. 4.8 DPWM Resonant Mode This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the switching frequency changes, the dead times between the pulses remain the same. The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as described in the LLC Example section. Here is a diagram of this mode: 36 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Start of Period Period Counter Start of Period Filter Period Adaptive Sample Trigger A Sample Trigger 1 DPWM Output A Filter Duty – Average Dead Time Event 1 Event 3 - Event 2 Period Register – Event 4 DPWM Output B Blanking A Begin Blanking A End Blanking B Begin Blanking B End Phase Trigger Sample Trigger 2 To Other Modules To Other Modules Resonant Symmetrical Closed Loop Events which change with DPWM mode: Dead Time 1 = Event 3 – Event 2 Dead Time 2 = Event 1 + Period Register – Event 4) Average Dead Time = (Dead Time 1 + Dead Time 2)/2 DPWM A Rising Edge = Event 1 DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead Time Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead Time + (Event 3 – Event 2) DPWM B Falling Edge = Filter Period – (Period Register – Event 4) Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End Filter controlled edge Adaptive Sample Trigger B UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the only edge for which the blanking signals can be used easily. Copyright © 2012, Texas Instruments Incorporated Functional Overview 37 Submit Documentation Feedback Product Folder Link(s): UCD3138 Start of Period Period Counter Start of Period Period Sample Trigger 1 DPWM Output A Filter Duty/2 (High Resolution) Period/2 DPWM Output B Blanking A Begin Blanking A End Blanking B Begin Blanking B End Phase Trigger Sample Trigger 2 To Other Modules To Other Modules Triangular Mode Closed Loop Events which change with DPWM mode: DPWM A Rising Edge = None DPWM A Falling Edge = None Adaptive Sample Trigger = None DPWM B Rising Edge = Period/2 - Filter Duty/2 + Cycle Adjust A DPWM B Falling Edge = Period/2 + Filter Duty/2 + Cycle Adjust B Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End Filter controlled edge Cycle Adjust A (High Resolution) Cycle Adjust B (High Resolution) UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 4.9 Triangular Mode Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode, only DPWM-B is available. Here is a diagram for Triangular Mode: All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center of the on-time does not move in this mode. 38 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.10 Leading Edge Mode Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the Leading Edge Mode: Copyright © 2012, Texas Instruments Incorporated Functional Overview 39 Submit Documentation Feedback Product Folder Link(s): UCD3138 Start of Period Period Counter Start of Period Period Adaptive Sample Trigger B Sample Trigger 1 DPWM Output A Cycle Adjust A (High Resolution) Filter Duty (High Resolution) Event 1 Event 2 - Event 3 (High Resolution) Event 4 (High Resolution) DPWM Output B Blanking A Begin Blanking A End Blanking B Begin Blanking B End Phase Trigger Sample Trigger 2 To Other Modules To Other Modules Leading Edge Closed Loop Events which change with DPWM mode: DPWM A Falling Edge = Event 1 DPWM A Rising Edge = Event 1 - Filter Duty + Cycle Adjust A Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or Adaptive Sample Trigger B = Event 1 - Filter Duty/2 + Adaptive Sample Register DPWM B Rising Edge = Event 4 DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A -(Event 2 – Event 3) Phase Trigger = Phase Trigger Register value or Filter Duty Events always set by their registers, regardless of mode: Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End Adaptive Sample Trigger A UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are mainly useful for the edges at the beginning and end of the period. 40 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 DPWM3B (QT1) DPWM2A (QT2) DPWM2B (QB2) VTrans DPWM0B (QSYN2,4) DPWM1B (QSYN1,3) IPRI DPWM3A (QB1) UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.11 Sync FET Ramp and IDE Calculation The UCD3138 has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This comes in two forms: • Sync FET ramp • Ideal Diode Emulation (IDE) calculation When starting up a power supply, sometimes there is already a voltage on the output – this is called prebias. It is very difficult to calculate the ideal Sync FET on-time for this case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the power supply to sink current. To avoid this, Sync FETs are not turned on until after the power supply has ramped up to the nominal voltage. The Sync FETs are turned on gradually in order to avoid an output voltage glitch. The Sync FET Ramp logic can be used to turn them on at a rate below the bandwidth of the filter. In discontinuous mode, the ideal on-time for the Sync FETs is a function of Vin, Vout, and the primary side duty cycle (D). The IDE logic in the UCD3138 takes Vin and Vout data from the firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the Sync FETs. 4.12 Automatic Mode Switching Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware intervention. This is useful to increase efficiency and power range. The following paragraphs describe phase-shifted full bridge and LLC examples: 4.12.1 Phase Shifted Full Bridge Example In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather than phase shift, at light load. This is shown below: Copyright © 2012, Texas Instruments Incorporated Functional Overview 41 Submit Documentation Feedback Product Folder Link(s): UCD3138 Q1B Q1T QSR1 QSR2 fs< fr fr fs= fr_max fs> fr PWM Mode LLC Mode Tr= 1/fr Tr= 1/fr ISEC(t ) SynFET Primary QT1 QB1 Lr ISOLATED GATE Transformer SYNCHRONOUS GATE DRIVE PRIM CURRENT VOUT +12V T1 T1 ORING CTL VA VBUS QT2 QB2 D1 D2 T2 L1 Q5 C1 RL C2 R2 Q6 Q7 I_SHARE Vout Iout I_pri temp Vin VA UCD 3138 ARM7 FAULT 0 AD01 AD02/CMP0 AD03/CMP1/CMP2 AD04/CMP3 AD05/CMP4 AD00 AD06/CMP5 FAULT 1 FAULT 2 GPIO2 GPIO3 GPIO1 AD07/CMP6 AD08 AD09 DPWM0B DPWM1B DPWM2A DPWM2B ORING_CRTL P_GOOD DPWM3A DPWM3B Vout ON/OFF FAILURE ACFAIL_OUT ACFAIL_IN I_pri Iout EADC0 EADC1 CLA0 CLA1 EADC2 DPWM0 DPWM1 DPWM2 DPWM3 Duty for mode switching Vref Load Current PCM CBC < DPWM3A DPWM3B DPWM2A DPWM2B DPWM0B DPWM1B CPCC PMBus UART1 UART0 Primary OSC WD RST Memory FAULT Current Sensing I_pri UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Figure 4-3. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification 4.12.2 LLC Example In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC: 42 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Q1T CRES CRES LM LK Q1B VBUS VBUS Transformer COUT1 QSR1 QSR2 LRES DPWM0A DPWM0B DPWM1A DPWM1B Driver Driver Driver Driver RS RS1 RS2 CS RF2 CF RF1 RLRES ESR1 COUT2 ESR2 EAP0 EAN0 NP NS NS AD04 ADC13 EAP1 AD03 Oring Circuitry VOUT ILR(t) ILM(t) ISEC(t) VCR(t) VOUT(t) Rectifier and filter UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Figure 4-4. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification Copyright © 2012, Texas Instruments Incorporated Functional Overview 43 Submit Documentation Feedback Product Folder Link(s): UCD3138 Filter Duty Low – Lower Threshold High – Lower Threshold Control Register 1 Auto Config High Auto Config Mid High – Upper Threshold Low – Upper Threshold 0 Full Range Automatic Mode Switching With Hysteresis UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 4.12.3 Mechanism for Automatic Mode Switching The UCD3138 allows the customer to enable up to two distinct levels of automatic mode switching. These different modes are used to enhance light load operation, short circuit operation and soft start. Many of the configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers. If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takes place. They are used as shown below. As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is close to a mode switching point. 44 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 A ON SELECT A OFF SELECT B ON SELECT B OFF SELECT EGEN A EGEN B EDGE GEN PWM A PWM B B SELECT A SELECT INTRAMUX A/B/C (N) A/B/C (N+1) C (N+2) C (N+3) A(N) B(N) A(N+1) B(N+1) UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.13 DPWMC, Edge Generation, IntraMux The UCD3138 has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux. DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the Blanking A end time. The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it. The options are: 0 = DPWM(n) A Rising edge 1 = DPWM(n) A Falling edge 2 = DPWM(n) B Rising edge 3 = DPWM(n) B Falling edge 4 = DPWM(n+1) A Rising edge 5 = DPWM(n+1) A Falling edge 6 = DPWM(n+1) B Rising edge 7 = DPWM(n+1) B Falling edge Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1. The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit. The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high resolution must be disabled, and DPWM edge resolution goes down to 4 ns. Here is a drawing of the Edge Gen/Intra Mux: Here is a list of the IntraMux modes for DPWMA: 0 = DPWMA(n) pass through (default) 1 = Edge-gen output, DPWMA(n) 2 = DPWNC(n) 3 = DPWMB(n) (Crossover) 4 = DPWMA(n+1) Copyright © 2012, Texas Instruments Incorporated Functional Overview 45 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 5 = DPWMB(n+1) 6 = DPWMC(n+1) 7 = DPWMC(n+2) 8 = DPWMC(n+3) and for DPWMB: 0 = DPWMB(n) pass through (default) 1 = Edge-gen output, DPWMB(n) 2 = DPWNC(n) 3 = DPWMA(n) (Crossover) 4 = DPWMA(n+1) 5 = DPWMB(n+1) 6 = DPWMC(n+1) 7 = DPWMC(n+2) 8 = DPWMC(n+3) The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply: DPWM(n) DPWM3 DPWM(n+1) DPWM0 DPWM(n+2) DPWM1 DPWM(n+3) DPWM2 4.14 Filter The UCD3138 filter is a PID filter with many enhancements for power supply control. Some of its features include: • Traditional PID Architecture • Programmable non-linear limits for automated modification of filter coefficients based on received EADC error • Multiple coefficient sets fully configurable by firmware • Full 24-bit precision throughout filter calculations • Programmable clamps on integrator branch and filter output • Ability to load values into internal filter registers while system is running • Ability to stall calculations on any of the individual filter branches • Ability to turn off calculations on any of the individual filter branches • Duty cycle, resonant period, or phase shift generation based on filter output. • Flux balancing • Voltage feed forward 46 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 P I 26 D 24 All are S0.23 24 + 24 Saturate Yn S2.23 S0.23 24 Shifter S0.23 24 Yn Scale Clamp S0.23 24 Filter Yn Clamp High Filter Yn Clamp Low Filter Yn X 24 24 24 Ki_yn reg Kp Coef Xn-1 Reg Xn 16 24 <> 9 9 16 24 24 24 24 24 24 Clamp Kd yn_reg Kd alpha 9 16 9 24 24 24 24 P I D Limit Comparator PID Filter Branch Stages Ki High EADC_DATA 9 9 9 9 24 32 Ki Coef Kd coef Limit 5 9 9 Limit 6 ….. Limit 0 Coefficient select Ki Low Optional Selected by KI_ADDER_ MODE Clamp X X X + - + + Round X X +1 n n – UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Here is the first section of the Filter : The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole. The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve transient response. Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits).: This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping. Copyright © 2012, Texas Instruments Incorporated Functional Overview 47 Submit Documentation Feedback Product Folder Link(s): UCD3138 18 24 14 38 18 KCompx DPWMx Period Loop_VFF Filter YN (Duty %) Filter Duty S0.23 14.0 14.0 14.0 14.0 S14.23 Resonant Duty 14.0 Round to 18 bits, Clamp to Positive Clamp Filter Output Clamp High Filter Output Clamp Low X 14.4 14.4 OUTPUT_MULT_SEL 14 Bits [17:4] Filter Period 24 14 38 18 KCompx DPWMx Period Filter YN S0.23 14.0 14.0 14.0 S14.23 Round to 18 bits, Clamp to Positive Truncate X low 4 bits 14.0 PERIOD_MULT_SEL 14.4 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com There is a final section for the filter, which permits its output to be matched to the DPWM: This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode, the filter can be used to generate both period and duty cycle. 4.14.1 Loop Multiplexer The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and DPWM can be combined with each other in many configurations. It also controls the following connections: • DPWM to Front End • Front End DAC control from Filters or Constant Current/Constant Power Module • Filter Special Coefficients and Feed Forward • DPWM synchronization • Filter to DPWM The following control modules are configured in the Loop Mux: • Constant Power/Constant Current • Cycle Adjustment (Current and flux balancing) • Global Period • Light Load (Burst Mode) • Analog Peak Current Mode 48 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 FAULT - CBC FAULT - AB FAULT -A DCOMP– 4X EXT GPIO– 4X ACOMP– 7X FAULT -B FAULT MODULE FAULT MODULE FAULT MODULE CYCLE BY CYCLE AB FLAG AB FLAG A FLAG B FLAG FAULT MUX ALL_FAULT_EN DPWM_EN DPWM CBC_FAULT_EN CBC_PWM_AB_EN FAULT MODULE ANALOG PCM Bit20 in DPWMCTRL0 Bit30 in DPWMFLTCTRL Bit 31 in DPWMFLTCTRL Bit0 in DPWMCTRL0 DISABLE PWM A AND B DISABLE PWM A AND B DISABLE PWM A ONLY DISABLE PWM B ONLY UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.14.2 Fault Multiplexer In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138 provides an extensive array of multiplexers that are united under the name Fault Mux module. The Fault Mux Module supports the following types of mapping between all the sources of fault and all different fault response mechanism inside each DPWM module. • Many fault sources mapped to a single fault response mechanism. For instance an analog comparator in charge of over voltage protection, a digital comparator in charge of over current protection and an external digital fault pin can be all mapped to a fault-A signal connected to a single FAULT MODULE and shut down DPWM1-A. • A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through DPWM-3 by way of several fault modules. • Many fault sources can be mapped to many fault modules inside many DPWM modules. Copyright © 2012, Texas Instruments Incorporated Functional Overview 49 Submit Documentation Feedback Product Folder Link(s): UCD3138 CYCLE BY CYCLE FAULT - CBC CLIM FAULT MODULE FAULT IN FAULT FLAG MAX COUNT FAULT EN DPWM EN UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com The Fault Mux Module provides a multitude of fault protection functions within the UCD3138 high-speed loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided in the Fault Mux Module. Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault module, A fault module and B fault module. The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to the way the modules are attached to the DPWMs. All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle faults count exceeds max_count. Once the fault flag is set DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags. Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules) will be cleared simultaneously. All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannot be enabled/ disabled separately. Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module. The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signals arriving from Analog Peak current mode (PCM) module. The Fault Mux Module supports the following basic functions: • 4 digital comparators with programmable thresholds and fault generation • Configuration for 7 high speed analog comparators with programmable thresholds and fault generation • External GPIO detection control with programmable fault generation • Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection Fault, DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag • Clock Failure Detection for High and Low Frequency Oscillator blocks • Discontinuous Conduction Mode Detection 50 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 Digital Comparator 0 Control Digital Comparator 1 Control Digital Comparator 2 Control Digital Comparator 3 Control Front End Control 0 Front End Control 1 Front End Control 2 Analog Comparator 0 Analog Comparator 0 Control Analog Comparator 1 Analog Comparator 1 Control Analog Comparator 2 Analog Comparator 2 Control Analog Comparator 3 Analog Comparator 3 Control Analog Comparator 4 Analog Comparator 4 Control Analog Comparator 5 Analog Comparator 5 Control Analog Comparator 6 Analog Comparator 6 Control External GPIO Detection fault[2:0] DPWM 0 DPWM 1 DPWM 2 DPWM 3 DPWM 0 Fault Control DPWM 1 Fault Control DPWM 2 Fault Control DPWM 3 Fault Control Analog Comparator Automated Ramp DCM Detection HFO/LFO Fail Detect UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Figure 4-5. Fault Mux Block Diagram 4.15 Communication Ports 4.15.1 SCI (UART) Serial Communication Interface A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous startstop serial data communication (see the pin out sections for details) Each interface has a 24 bit for supporting programmable baud rates and has programmable data word and stop bit options. Half or full duplex operation is configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used. 4.15.2 PMBUS The PMBus Interface supports independent master and slave modes controlled directly by firmware through a processor bus interface. Individual control and status registers enable firmware to send or receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I2C Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol Specification. The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface connects directly to the I2C/SMBus/PMBus Clock, Data, Alert, and Control signals. Example: PMBus Address Decode via ADC12 Reading The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding. At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is captured by the internal 12-bit ADC. Where bin(VAD0x) is the address bin for one of 12 address as shown in Figure 4-6. Copyright © 2012, Texas Instruments Incorporated Functional Overview 51 Submit Documentation Feedback Product Folder Link(s): UCD3138 Vdd IBIAS To ADC Mux On/Off Control AD00, AD01 pin Resistor to set PMBus Address UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com Figure 4-6. PMBus Address Detection Method 4.15.3 General Purpose ADC12 The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options: • Typical conversion speed of 267 ksps • Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence • Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples • Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge, ADC_EXT_TRIG pin or Analog Comparator results • Interrupt capability to embedded processor at completion of ADC conversion • Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or averaged ADC data • Two 10 μA current sources for excitation of PMBus addressing resistors • Dual sample and hold for accurate power measurement • Internal temperature sensor for temperature protection and monitoring The control module ( ADC12 Contol Block Diagram) contains the control and conversion logic for autosequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the result register associated with the sequence number. Input channels can be sampled in any desired order or programmed to repeat conversions on the same channel multiple times during a conversion sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16. Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical Characteristics plots for the temperature variation associated with this function. 52 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 ADC Channels S/H 12-bit SAR ADC ADC12 Block ADC12 Control ADC Channel ADC Averaging Digital Comparators DPWM Modules ADC12 Registers Analog Comparators ADC External Trigger (from pin) UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Figure 4-7. ADC12 Control Block Diagram 4.15.4 Timers External to the Digital Power Peripherals there are 3 different types of timers in UCD3138. They are the 24-bit timer, 16-bit timer and the Watchdog timer 4.15.4.1 24-bit PWM Timer There is one 24 bit counter PWM timer which runs off the Interface Clock and can further be divided down by an 8-bit pre-scalar to generate a slower PWM time period. The timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, the timer has a shadow register (Data Buffer register) which can be used to store CPU updates of the compare events while still using the timer. The selected shadow register update mode happens after the compare event matches. The two capture pins TCMP0 and TCMP1 are inputs for recording a capture event. A capture event can be set either to rising, falling, or both edges of the capture pin. Upon this event, the counter value is stored in the corresponding capture data register. The counter reset can be configured to happen on a counter roll over, a compare equal event, or by software controlled register. Five Interrupts from the PWM timer can be set, which are the counter rollover event (overflow), either capture event 0 or 1, or the two comparison match events. Each interrupt can be disabled or enabled. Upon an event comparison on only the second event, the TCMP pin can be configured to set, clear, toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as general purpose I/O for reading the value of the input at the pin. The first compare event can only be used as an interrupt. Copyright © 2012, Texas Instruments Incorporated Functional Overview 53 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 4.15.4.2 16-Bit PWM Timers There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register) which can be used to store CPU updates of compare events while still using the timer. The selected shadow register update mode happens after the compare event matches. The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by the two comparison match events. Each comparison match and the overflow interrupts can be disabled or enabled. Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the value of the input at the pin. 4.15.4.3 Watchdog Timer A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided for status monitoring of the watchdog. 4.16 Miscellaneous Analog The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a wide variety of functions. These functions include device supervisory features such as Brown-Out and power saving configuration, general purpose input/output configuration and interfacing, internal temperature sensor control and current sharing control. The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually used at the time of trimming at manufacturing; therefore this document will not cover these trim controls. The MAC registers and peripherals are all available in the UCD3138 (64 pin version). Other UCD3138 devices may have reduced resources. See the device pin out description for details. 4.17 Package ID Information Package ID register includes information regarding the package type of the device and can be read by firmware for reporting through PMBus or for other package sensitive decisions. BIT NUMBER 1:0 Bit Name PKG_ID Access R/W Default 0 – UCD3138RGC, 1 – UCD3138RHA 4.18 Brownout Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition that may be considered unsafe for proper operation of the device. The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower than brownout threshold, it still does not necessarily trigger a device reset. The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an interrupt service routine. Please see the Power On Reset (POR) / Brown Out Reset (BOR) section. 54 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.19 Global I/O Up to 30 pins in UCD3138 can be configured to serve as a general purpose input or output pin (GPIO). This includes all digital input or output pins except for the RESET pin. The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins, EADC analog input pins and the RESET pin. There are two ways to configure and use the digital pins as GPIO pins: 1. Through the centralized Global I/O control registers. 2. Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO functionality. The Global I/O registers offer full control of: 1. Configuring each pin as a GPIO. 2. Setting each pin as input or output. 3. Reading the pin’s logic state, if it is configured as an input pin. 4. Setting the logic state of the pin, if it is configured as an output pin. 5. Connecting pin/pins to high rail through internal pull up resistors. The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control Register, Global I/O Value Register and Global I/O Read Register. The following is showing the format of Global I/O EN Register (GLBIOEN) as an example: BIT NUMBER 29:0 Bit Name GLOBAL_IO_EN Access R/W Default 00_0000_0000_0000_0000_0000_0000_0000 Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins 0 = Control of IO is done by the functional block assigned to the IO (Default) 1 = Control of IO is done by Global IO registers. PIN NUMBER BIT PIN_NAME UCD3138-64 PIN UCD3138-40 PIN 29 FAULT[3] 43 NA 28 ADC_EXT_TRIG 12, 26 8 27 TCK 37 21 26 TDO 38 20 25 TMS 40 24 24 TDI 39 23 23 SCI_TX[1] 29 NA 22 SCI_TX[0] 14 22 21 SCI_RX[1] 30 NA 20 SCI_RX[0] 13 23 19 TMR_CAP 12, 26, 41 8, 21 18 TMR_PWM[1] 32 NA 17 TMR_PWM[0] 12, 26, 31, 37 21 16 PMBUS-CLK 15 9 15 PMBUS-DATA 16 10 14 CONTROL 30 20 13 ALERT 29 19 12 EXT_INT 26, 34 NA Copyright © 2012, Texas Instruments Incorporated Functional Overview 55 Submit Documentation Feedback Product Folder Link(s): UCD3138 Temperature Sensor Ch14 ADC 12 Temp Cal UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com PIN NUMBER BIT PIN_NAME UCD3138-64 PIN UCD3138-40 PIN 11 FAULT[2] 42 25 10 FAULT[1] 36 23 9 FAULT[0] 35, 39 22 8 SYNC 12, 26,37 8, 21 7 DPWM3B 24 18 6 DPWM3A 23 17 5 DPWM2B 22 16 4 DPWM2A 21 15 3 DPWM1B 20 14 2 DPWM1A 19 13 1 DPWM0B 18 12 0 DPWM0A 17 11 4.20 Temperature Sensor Control Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities. The internal temperature sensor is disabled as default. Figure 4-8. Internal Temp Sensor Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value. The temperature sensor is measured using ADC12 (via Ch14). The temperature is then calculated using a mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement). The temperature sensor can be enabled or disabled. 4.21 I/O Mux Control In different packages of UCD3138 several I/O functions are multiplexed and routed toward a single physical pin. I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be assigned to a physical device pin for your application. 56 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 EXT CAP AD02 400 Ω Digital RSHARE 250 Ω 3.3 V ISHARE ADC12 and CMP ESD ESD 3.2 kΩ 250 Ω ESD AD13 3.3V SW2 SW1 SW3 3.3 V ADC12 and CMP UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 4.21.1 JTAG Use for I/O and JTAG Security The UCD3138 provides a JTAG interface for debugging and for uploading data and programs. The pins are multiplexed with other pins, and will not be available in certain topologies. For power supplies, other debugging techniques (PMBus, UART, code instrumentation) are often superior to JTAG. Code downloading is much faster via PMBus, or with a user boot program via UART. PMBus support is available from TI. JTAG for debugging has limited support from TI’s Code Composer Studio. JTAG parameter download may be supported by third parties. 4.22 Current Sharing Control UCD3138 provides three separate modes of current sharing operation. • Analog bus current sharing • PWM bus current sharing • Master/Slave current sharing • AD02 has a special ESD protection mechanism that prevents the pin from pulling down the currentshare bus if power is missing from the UCD3138 The simplified current sharing circuitry is shown in the drawing below: Figure 4-9. Simplified Current Sharing Circuitry CURRENT SHARING MODE FOR TEST ONLY, CS_MODE EN_SW1 EN_SW2 DPWM ALWAYS KEEP 00 Off or Slave Mode (3-state) 00 00 (default) 0 0 0 PWM Bus 00 01 1 0 ACTIVE Off or Slave Mode (3-state) 00 10 0 0 0 Analog Bus or Master 00 11 0 1 0 Copyright © 2012, Texas Instruments Incorporated Functional Overview 57 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be controlled through the current sharing control register (CSCTRL). 4.23 Temperature Reference The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal temperature sensor (channel 14) during the factory trim and calibration. This information can be used by different periodic temperature compensation routines implemented in the firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost. 58 Functional Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 2 .2 μF 1 .0 μF BPCAP DGND V33D UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 5 IC Grounding and Layout Recommendations • Two grounds are recommended: AGND (analog) and DGND (digital). – AGND plane should be on a different layer than DGND, and right under the UCD3138 device. – UCD3138 power pad should be tied to AGND plane by at least 4 vias – AGND plane should be just large enough to connect to all required components. – Power ground (PGND) can be independent or combined with DGND – The power pad of the driver IC should be tied to DGND • Both 3.3VD and 3.3VA should have a local 4.7μF capacitor placed as close as possible to the device pins • BPCAP decoupling (2.2 μF typically) MUST be connected to DGND • All analog signal filter capacitors should be tied to AGND – If the gate driver device, such as UCD27524 or UCD27511/7 driver is used, the filter capacitor for the current sensing pin can be tied to DGND for easy layout • All digital signals, such as GPIO, PMBus and PWM are referenced to DGND. • The RESET pin capacitor (0.1μF) should be connected to either DGND or AGND locally. A 10kΩ pullup resistor to 3.3V is recommended. • All filter and decoupling capacitors should be placed close to UCD3138 as possible – Resistor placement is less critical and can be moved a little further away • The DGND and AGND net-short resistor MUST be placed right between one UCD3138’s DGND pin and one AGND pin. Ground connections to the net short element should be made by a large via (or multiple paralleled vias) for each terminal of the net-short element. • If a gate driver device such as UCC27524 or UCC27511/7 is on the control card and there is a PGND connection, a net-short resistor should be tied to the DGND plane and PGND plane by multiple vias. In addition the net-short element should be close to the driver IC. Copyright © 2012, Texas Instruments Incorporated IC Grounding and Layout Recommendations 59 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 6 Tools and Documentation The application firmware for UCD3138 is developed on Texas Instruments Code Composer Studio (CCS) integrated development environment (v3.3 recommended). Monitoring and Configuration of key device parameters and real time debug capabilities are offered through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER Graphical User Interface (GUI), http://www.ti.com/tool/fusion_digital_power_designer. The FUSION_DIGITAL_POWER_DESIGNER software application uses PMBus protocol to communicate with the device over serial bus by way of a interface adaptor known as USB-TO-GPIO, available as an EVM from Texas Instruments (http://www.ti.com/tool/usb-to-gpio). The software application can also be used to program the devices, with a version of the tool known as FUSION_MFR_GUI optimized for manufacturing environments (http://www.ti.com/tool/fusion_mfr_gui). The FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and reporting capabilities. In terms of reference documentation, the following 3 programmer’s manuals are available offering detailed information regarding the application and usage of UCD3138 digital controller: 1. UCD3138 Digital Power Peripheral Programmer's Manual Key topics covered in this manual include: – Digital Pulse Width Modulator (DPWM) – Modes of Operation (Normal/Multi/Phase-shift/Resonant etc) – Automatic Mode Switching – DPWMC, Edge Generation & Intra-Mux – Front End – Analog Front End – Error ADC or EADC – Front End DAC – Ramp Module – Successive Approximation Register Module – Filter – Filter Math – Loop Mux – Analog Peak Current Mode – Constant Current/Constant Power (CCCP) – Automatic Cycle Adjustment – Fault Mux – Analog Comparators – Digital Comparators – Fault Pin functions – DPWM Fault Action – Ideal Diode Emulation (IDE), DCM Detection – Oscillator Failure Detection – Register Map for all of the above peripherals in UCD3138 2. UCD3138 Monitoring and Communications Programmer’s Manual Key topics covered in this manual include: – ADC12 – Control, Conversion, Sequencing & Averaging – Digital Comparators – Temperature Sensor – PMBUS Addressing – Dual Sample & Hold – Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating) – PMBUS Interface – General Purpose Input Output (GPIO) 60 Tools and Documentation Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 – Timer Modules – PMBus – Register Map for all of the above peripherals in UCD3138 3. UCD3138 ARM and Digital System Programmer’s Manual Key topics covered in this manual include: – Boot ROM & Boot Flash – BootROM Function – Memory Read/Write Functions – Checksum Functions – Flash Functions – Avoiding Program Flash Lock-Up – ARM7 Architecture – Modes of Operation – Hardware/Software Interrupts – Instruction Set – Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode) – Memory & System Module – Address Decoder, DEC (Memory Mapping) – Memory Controller (MMC) – Central Interrupt Module – Register Map for all of the above peripherals in UCD3138 In addition to the tools and documentation described above, for the most up to date information regarding evaluation modules, reference application firmware and application notes/design tips, please visit http://www.ti.com/product/ucd3138. Copyright © 2012, Texas Instruments Incorporated Tools and Documentation 61 Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 SLUSAP2B –MARCH 2012–REVISED JULY 2012 www.ti.com 7 References 1. UCD3138 Digital Power Peripherals Programmer’s Manual (Literature Number:SLUU995) 2. UCD3138 Monitoring & Communications Programmer’s Manual (Literature Number:SLUU996) 3. UCD3138 ARM and Digital System Programmer’s Manual (Literature Number:SLUU994) 4. Code Composer Studio Development Tools v3.3 – Getting Started Guide, (Literature Number: SPRU509H) 5. ARM7TDMI-S Technical Reference Manual 6. System Management Bus (SMBus) Specification 7. PMBusTM Power System Management Prototcol Specification (1) (1) PMBus is a trademark of SMIF, Inc. 62 References Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): UCD3138 UCD3138 www.ti.com SLUSAP2B –MARCH 2012–REVISED JULY 2012 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (March 2012) to Revision A Page • Added Production Data statement to footnote and removed "Product Preview" banner ........................... 6 Changes from Revision A (March 2012) to Revision B Page • Added Feature bullets ............................................................................................................. 6 • Changed "Dual Edge Modulation" to "Triangular Modulation" in Features section ................................. 6 • Changed "265 ksps" to "267 ksps" in Features section ................................................................... 6 • Clarified number of UARTs in Feature section ............................................................................... 6 • Changed "FDPP" to "DDP" throughout. ....................................................................................... 7 • Changed Total GPIO pin count for the UCD3138 40-pin device from "17" to "18" in the Product Selection Matrix table. .......................................................................................................................... 8 • Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 16 • Changed EAP – EAN Error voltage digital resolution MIN values for AFE=3, AFE=2, AFE=1, AFE=0 from 0.95, 1.90, 3.72, and 7.3 respectively; to, 0.8, 1.7, 3.55, and 6.90 respectively. ....................................... 16 • Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 17 • Changed conditions for VOL and VOH specs in the Electrical Characteristics table ................................. 17 • Added TWD spec to Electrical Characteristics table ...................................................................... 17 • Changed "VREG" to "BP18" in conditions statement for Electrical Characteristics table. ....................... 18 • Changed "PWM" to "DPWM" in DPWM Module. ............................................................................ 29 • Changed "PWMA" and "PWMB" to "DPWMA" and "DPWMB" in . ...................................................... 34 • Changed waveforms graphic for "Phase Shifted Full Bridge Example" for clarification .......................... 41 • Added text to section LLC Example .......................................................................................... 42 • Changed typical conversion speed from "268 ksps" to "267 ksps" in the General Purpose ADC12 section. .............................................................................................................................. 52 • Added package ID information for the UCD3138RGC and UCD3138RHA devices. ................................. 54 • Added bullet "AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus if power is missing from the UCD3138" to Current Sharing Control. ..................... 57 • Added sub-bullet "The power pad of the driver IC should be tied to DGND" and changed capacitor value from "0.1 μF" to "4.7 μF" in IC Grounding and Layout Recommendations ........................................... 59 • Added "Tools and Documentation" section ................................................................................. 60 • Changed " Mechanical Data" section to "References" section ......................................................... 62 Copyright © 2012, Texas Instruments Incorporated References 63 Submit Documentation Feedback Product Folder Link(s): UCD3138 PACKAGE OPTION ADDENDUM www.ti.com 26-Jul-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) UCD3138RGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UCD3138RGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UCD3138RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UCD3138RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant UCD3138RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD3138RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD3138RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 UCD3138RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD3138RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD3138RGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD3138RHAR VQFN RHA 40 2500 367.0 367.0 38.0 UCD3138RHAT VQFN RHA 40 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jul-2012 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 1 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 Power Electronics R&D Center Wireless Connectivity Panasonic Industrial Devices Europe GmbH APPROVED CHECKED DESIGNED Specification for Production Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 21337 Lüneburg Applicant / Manufacturer Hardware Germany Not applikable Applicant / Manufacturer Software Software Version Not applikable Contents Approval for Mass Production Customer Bluetooth QDL ID Qualified Design Listing (QDL) ID: B019784 As Controller Sub-System Listing for PAN13xx Series. By purchase of any products described in this document the customer accepts the document's validity and declares their agreement and understanding of its contents and recommendations. Panasonic reserves the right to make changes as required without notification. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 2 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de TABLE OF CONTENTS 1 Scope of this Document..................................................................................................5 1.1 New PAN1315A, PAN1325A.................................................................................5 2 Key Features...................................................................................................................6 2.1 Software Block Diagram........................................................................................6 3 Applications for the Module.............................................................................................7 4 Description for the Module..............................................................................................7 5 Detailed Description........................................................................................................8 5.1 Terminal Layout.....................................................................................................8 5.1.1 5.1.1. Terminal Layout PAN131x without antenna...................................8 5.1.2 5.1.2. Terminal Layout PAN132x with antenna........................................9 5.2 Pin Description.....................................................................................................10 5.3 Device Power Supply...........................................................................................11 5.4 Clock Inputs.........................................................................................................12 6 Bluetooth Features........................................................................................................12 7 Block Diagram...............................................................................................................13 8 Test Conditions.............................................................................................................14 9 General Device Requirements and Operation..............................................................14 9.1 Absolute Maximum Ratings.................................................................................14 9.2 Recommended Operating Conditions..................................................................15 9.3 Current Consumption...........................................................................................15 9.4 General Electrical Characteristics........................................................................16 9.5 nSHUTD Requirements.......................................................................................16 9.6 External Digital Slow Clock Requirements (–20°C to +70°C)..............................16 10 Host Controller Interface...............................................................................................17 11 Audio/Voice Codec Interface.........................................................................................18 11.1 PCM Hardware Interface.....................................................................................18 11.2 Data Format.........................................................................................................18 11.3 Frame Idle Period................................................................................................19 11.4 Clock-Edge Operation.........................................................................................20 11.5 Two-Channel PCM Bus Example........................................................................20 11.6 Audio Encoding....................................................................................................20 11.7 Improved Algorithm For Lost Packets..................................................................21 11.8 Bluetooth/PCM Clock Mismatch Handling...........................................................21 11.9 Bluetooth Inter-IC Sound (I2S)............................................................................21 11.10Current Consumption for Different Bluetooth Scenarios......................................22 12 Bluetooth RF Performance............................................................................................22 13 Soldering Temperature-Time Profile (for reflow soldering)...........................................25 13.1 For lead solder.....................................................................................................25 13.2 For leadfree solder...............................................................................................26 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 3 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 14 Module Dimension........................................................................................................27 14.1 Module Dimensions PAN131X without Antenna..................................................27 14.2 Module Dimensions PAN132X with Antenna.......................................................28 15 Footprint of the Module.................................................................................................29 15.1 Footprint PAN131x without antenna....................................................................29 15.2 Footprint PAN132x with antenna.........................................................................30 16 Labeling Drawing..........................................................................................................31 17 Mechanical Requirements.............................................................................................31 18 Recommended Foot Pattern.........................................................................................32 18.1 recommended foot pattern PAN131x without antenna........................................32 18.2 recommended foot pattern PAN132x with antenna.............................................33 19 Layout Recommendations with Antenna (PAN132x)....................................................34 20 Bluetooth LE (LOW ENERGY) PAN1316/26................................................................34 20.1 Network Topology................................................................................................34 20.2 module features...................................................................................................35 20.3 Current consumption for different LE scenarios..................................................36 21 ANT PAN1317/27..........................................................................................................36 21.1 Network topology.................................................................................................36 21.2 module features..................................................................................................37 21.3 ANT Current consumption...................................................................................37 22 Triple mode (BR/EDR + Bluetooth low energy + ANT) PAN1323................................38 22.1 Triple Mode Current consumption.......................................................................38 23 Development of Applications.........................................................................................39 23.1 Tools to be needed..............................................................................................39 24 List of Profiles...............................................................................................................40 25 Reliability Tests.............................................................................................................40 26 Cautions........................................................................................................................41 26.1 Design Notes.......................................................................................................41 26.2 Installation Notes.................................................................................................41 26.3 Usage Conditions Notes......................................................................................42 26.4 Storage Notes......................................................................................................42 26.5 Safety Cautions...................................................................................................43 26.6 Other cautions.....................................................................................................43 27 Packaging.....................................................................................................................44 27.1 Packaging of PAN131x without antenna.............................................................44 27.2 Packaging for PAN132x with antenna.................................................................47 28 Ordering Information.....................................................................................................48 29 RoHS Declaration.........................................................................................................49 30 Data Sheet Status.........................................................................................................49 31 History for this Document..............................................................................................50 32 Related Documents.......................................................................................................50 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 4 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 33 General Information......................................................................................................52 34 Regulatory Information..................................................................................................52 34.1 FCC for US..........................................................................................................52 34.1.1 FCC Notice.............................................................................................52 34.1.2 Caution...................................................................................................53 34.1.3 Labeling Requirements..........................................................................53 34.1.4 Antenna Warning....................................................................................53 34.1.5 Approved Antenna List...........................................................................53 34.1.6 RF Exposure PAN13xx..........................................................................54 34.2 Industry Canada Certification..............................................................................54 34.3 European R&TTE Declaration of Conformity.......................................................54 34.4 NCC for Taiwan...................................................................................................56 34.4.1 Labeling Requirements..........................................................................56 34.4.2 NCC Statement......................................................................................56 34.5 Bluetooth SIG Statement.....................................................................................56 35 Life Support Policy........................................................................................................56 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 5 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 1 SCOPE OF THIS DOCUMENT This product specification describes Panasonic’s HCI, Class 1.5 , TI based, Bluetooth®1 modules, series number 13xx. For detailed family overview that includes part numbers see Chapter 28, Ordering Information. Non-antenna versions will be refered to as PAN131x, versions with antenna will be refered to as PAN132x in this document. Fore information and features on Bluetooth Low Energy 4.0 refer to Chapter 19, for information on ANT refer to Chapter 21. 1.1 NEW PAN1315A, PAN1325A The PAN1315A/1325A Series is based on Texas Instruments’ NEW CC2560A controller. A ROM update from Texas Instruments to the CC2560 IC has allowed Panasonic to improve PAN1315/1325 Series. The NEW PAN1315A/1325A Series Modules has increased power and system efficiency resulting from reduced initialization script size, start-up time and decreased system memory requirements. Compatibility: PAN1315, PAN1315A, PAN1316 and PAN1317 are 100% footprint compatible PAN1325, PAN1325A, PAN1326 and PAN1327 are 100% footprint compatible As an updated initialization script resident on the application microcontroller is required for modules based on the CC2560A, compatibility between the PAN1315/PAN1325 and PAN1315A/PAN1325A is dependant on the Bluetooth stack. Stacks are available that will operate with all PAN1315/1325 variations. BT-Stack solutions provided by software development partners are available for most processors, including linux based host systems.. For detailed family overview that includes part numbers see Chapter 28 Ordering Information. Contact your stack provider or local Panasonic sales company for currently available Bluetooth Profiles. 1 Bluetooth is a registered trademark of the Bluetooth Special Interest Group. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 6 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 2 KEY FEATURES • Bluetooth specification v2.1 + EDR (Enhanced Data Rate) • Surface mount type 6.5(9.5 w. Ant.) x 9.0 x 1.8 mm³ • Up to 10.5dBm Tx power (typical) with transmit power control • High sensitivity (-93 dBm typ.) • Texas Instrument’s CC256X BlueLink 7.0 inside • Fast Connection Setup • Extended SCO Link • Supports convenient direct connection to battery (2.2-4.8 V), or connect to DC/DC (1.7-1.98 V) for improved power efficiency • Internal crystal oscillator (26MHz) • Fully shielded for immunity • Full Bluetooth data rate up to 2,178kbps asymmetric • Support for Bluetooth power saving modes (Sniff, Hold) • Support for very low-power modes (deep sleep and power down) • Optional support for ultra-low-power mode. Standby with Battery-Backup • PCM Interface Master / Slave supporting 13 or 16 bit linear, 8 bit μ-law or A-law Codecs and CVSD transcoders on up to 3 SCO channels • Full 8- to 128-bit encryption • UART, I²C and PCM Interface • IO operating voltage = 1.8 V nominal • 3 Channel ADC and 1 Channel DAC • Bluetooth profiles such as SPP, A2DP and others are available. Refer to Panasonic’s RF module website for a listing of the most current releases. • Manufactured in conformance with RoHS 2.1 SOFTWARE BLOCK DIAGRAM PAN13xxHost ProcessorApplicationBD/EDRBLEANTHCIL2CAPHCIRF BlockPAN13xxHost Block CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 7 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 3 APPLICATIONS FOR THE MODULE All Embedded Wireless Applications • Smart Phones • Cable Replacement • Industrial Control • Automotive • Medical • Access Points • Scanners • Consumer Electronics • Wireless Sensors • Monitoring and Control • Low Power • Access Points 4 DESCRIPTION FOR THE MODULE The PAN1315 and PAN1315A are short-range, Class 1 or 2, HCI modules for implementing Bluetooth functionality into various electronic devices. A block diagram can be found in Chapter 7. Communication between the module and the host controller is carried out via UART. New designs can be completed quickly by mating the PAN13xx series modules with Texas Instruments’ MSP430BT5190 that contains Mindtree’s EtherMind Bluetooth Protocol Stack and serial port profile, additional computing power can be achieved by choosing TI’s Stellaris ARM7 controller that includes StoneStreet One's A2DP profile. Other BT profiles are available on custom development basis. Additional controllers are also supported by the PAN13xx series by using a TI/Panasonic software development partner to port the Bluetooth stack and profiles. Mindtree's Software Development Kit (SDK) is available on TI's website -- www.ti.com/connectivity.com Contact your local sales office for further details on additional options and services, by visiting www.panasonic.com/rfmodules or write an e-mail to wireless@eu.panasonic.com. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 8 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 5 DETAILED DESCRIPTION 5.1 TERMINAL LAYOUT 5.1.1 5.1.1. Terminal Layout PAN131x without antenna No Pin Name Pull at Reset Def. Dir. 2 I/O Type 3 Description of Options (Common) 1 GND Connect to Ground 2 TX_DBG PU O 2 mA Logger output 3 HCI_CTS PU I 8 mA HCI UART clear-to-send. 4 HCI_RTS PU O 8 mA HCI UART request-to-send. 5 HCI_RX PU I 8 mA HCI UART data receive 6 HCI_TX PU O 8 mA HCI UART data transmit 7 AUD_FSYNC PD IO 4 mA PCM frame synch. (NC if not used) Fail safe4 8 SLOW_CLK_IN I 32.768-kHz clock in Fail safe 9 NC IO Not connected 10 MLDO_OUT O Main LDO output (1.8 V nom.) 11 CL1.5_LDO_IN I PA LDO input 12 GND Connect to Ground 13 RF IO Bluetooth RF IO 14 GND Connect to Ground 15 MLDO_IN I Main LDO input 16 nSHUTD PD I Shutdown input (active low). 17 AUD_OUT PD O 4 mA PCM data output. (NC if not used) Fail safe 18 AUD_IN PD I 4 mA PCM data input. (NC if not used) Fail safe 19 AUD_CLK PD IO HY, 4 mA PCM clock. (NC if not used) Fail safe 20 GND Connect to Ground 21 NC EEPROM I²C SDA (Internal) 22 VDD_IO PI I/O power supply 1.8 V Nom 23 NC EEPROM I²C SCL (Internal) 24 NC IO Not connected 2 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down 3 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ. output current 4 No signals are allowed on the IO pins if no VDD_IO (Pin 22) power supplied, except pin 7, 8, 17-19. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 9 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 5.1.2 5.1.2. Terminal Layout PAN132x with antenna No Pin Name Pull at Reset Def. Dir. 5 I/O Type 6 Description of Options (Common) A GND Connect to Ground B GND Connect to Ground C GND Connect to Ground D GND Connect to Ground No 1-24 see above in Chapter 5.1.1. Except PIN 13 is not connected. For RF conducted measurements, either use the PAN1323ETU or de-solder the antenna and solder an antenna connector to the hot pin. 5 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down 6 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ. output current CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 10 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 5.2 PIN DESCRIPTION Pin Name No ESD 7 (V) Pull at Reset Def. Dir. 8 I/O Type 9 Description of Options Bluetooth IO SIGNALS HCI_RX 5 750 PU I 8 mA HCI UART data receive HCI_TX 6 750 PU O 8 mA HCI UART data transmit HCI_RTS 4 750 PU O 8 mA HCI UART request-to-send. HCI_CTS 3 750 PU I 8 mA HCI UART clear-to-send. AUD_FYSNC 7 500 PD IO 4 mA PCM frame synch (NC if not used) Fail safe AUD_CLK 19 500 PD IO HY, 4 mS PCM clock (NC if not used) Fail safe AUD_IN 18 500 PD I 4 mA PCM data input (NC if not used) Fail safe AUD_OUT 17 500 PD O 4 mA PCM data output (NC if not used) Fail safe Logger output TX_DBG 2 1000 PU O 2 mA OPTION: nTX_DBG – logger out (low = 1) CLOCK SIGNALS SLOW_CLK_IN 8 1000 I 32.768-kHz clock in Fail safe Bluetooth ANALOG SIGNALS RF 13 1000 IO Bluetooth RF IO (not connected with antenna) nSHUTD 16 1000 PD I Shutdown input (active low). Bluetooth POWER AND GND SIGNALS VDD_IO 22 1000 PI I/O power supply 1.8 V Nom MLDO_IN 15 1000 I Main LDO inputConnect directly to battery or to a pre-regulated 1.8-V supply MLDO_OUT 10 1000 O Main LDO output (1.8 V nom.) Can not be used as 1.8V supply due to internal connection to the RF part. CL1.5_LDO_IN 11 1000 I PA LDO input Connect directly to battery or to a pre-regulated 1.8-V supply GND 1 P Connect to Ground GND 12 P Connect to Ground GND 14 P Connect to Ground GND 20 P Connect to Ground EEPROM IO SIGNALS (EEPROM is optional in PAN13x product line) NC 23 1000 PU/PD I HY, 4mA EEPROM I²C SCL (Internal) NC 21 1000 PU/PD IO HY, 4mA EEPROM I²C IRQ (Internal) Remark: HCI_CTS is an input signal to the CC256X device: - When HCI_CTS is low, then CC256X is allowed to send data to Host device. - When HCI_CTS is high, then CC256X is not allowed to send data to Host device. 7 ESD: Human Body Model (HBM). JEDEC 22-A114 8 I = input; O = output; IO = bidirectional; P = power; PU = pulled up; PD = pulled down 9 I/O Type: Digital I/O cells. HY = input hysteresis, current = typ output current CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 11 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 5.3 DEVICE POWER SUPPLY The PAN13XX Bluetooth radio solution is intended to work in devices with a limited power budget such as cellular phones, headsets, hand-held PC’s and other battery-operated devices. One of the main differentiators of the PAN13XX is its power management – its ability to draw as little current as possible. The PAN13XX device requires two kinds of power sources: • Main power supply for the Bluetooth - VDD_IN = VBAT • Power source for the 1.8 V I/O ring - VDD_IO The PAN13XX includes several on-chip voltage regulators for increased noise immunity. The PAN13XX can be connected either directly to the battery or to an external 1.8-V DC to DC converter. There are three ways to supply power: • Full-VBAT system: Maximum RF output power, but not optimum system power: • Full-DC2DC system: Lower RF output power, but optimum system power: CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 12 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de • Mixed DC2DC-VBAT system: Maximum RF output power and optimum system power, but requires routing of VBAT: 5.4 CLOCK INPUTS The slow clock is always supplied from an external source. It is connected to the SLOW_CLK_IN pin number 8 and can be a digital signal with peak to peak of 0-1.8 V. The slow clock's frequency accuracy must be 32.768 kHz ±250 ppm for Bluetooth usage (according to the Bluetooth specification). The Slow Clock 32.768 kHz is mandatory to start the internal controller, otherwise the module does not start up. 6 BLUETOOTH FEATURES • Support of Bluetooth2.1+EDR (Lisbon Release) up to HCI level. • Very fast AFH algorithm for both ACL and eSCO. • Supports typically 4 dBm Class 2 TX power w/o external PA, improving Bluetooth link robustness. Adjusting the host settings, the TX power can be increased to 10 dBm. However it is important, that the national regulations and Bluetooth specification are met. • Digital Radio Processor (DRP) single-ended 50 ohm. • Internal temperature detection and compensation ensures minimal variation in the RF performance over temperature. • Flexible PCM and I2S digital audio/voice interfaces: Full flexibility of data-format (Linear, a-Law, μ-Law), data-width, data order, sampling and slot positioning, master/slave modes, high clock rates up to 15 MHz for slave mode (or 4.096 MHz for Master Mode). Lost packet concealment for improved audio. • Proprietary low-power scan method for page and inquiry scans, achieves page and inquiry scans at 1/3rd normal power. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 13 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 7 BLOCK DIAGRAM Note: The Slow Clock 32.768 kHz is mandatory, otherwise the module does not start up, refer to Chapter 5.4 for additional information. Note: The IO are 1.8V driven and might need external level shifter and LDO. The MLDO_OUT PIN can not be used as reference due to RF internal connection. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 14 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 8 TEST CONDITIONS Measurements shall be made under room temperature and humidity unless otherwise specified. 9 GENERAL DEVICE REQUIREMENTS AND OPERATION Temperature 25 ± 10°C Humidity 40 to 85%RH SW-Patch V2.30 Supply Voltage 3.3V All specifications are over temperature and process, unless indicated otherwise. 9.1 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). Note All parameters are measured as follows unless stated otherwise: VDD_IN 10 = 3.3 V, VDD_IO = 1.8 V. No See 11 Value Unit Ratings Over Operating Free-Air Temperature Range 1 VDD_IN Supply voltage range –0.5 to 5.5 V 12 2 VDDIO_1.8V –0.5 to 2.145 V 3 Input voltage to RF (Pin 13) –0.5 to 2.1 V 4 Operating ambient temperature range –20 to 70 °C 5 Storage temperature range –40 to 125 °C 6 Bluetooth RF inputs (Pin 13) 10 dBm 7 ESD: Human Body Model (HBM). JEDEC 22-A114 500 V 10 VDD_IN is supplied to MLDO_IN (Pin 15) and CL1.5_LDO_IN (Pin 11), other options are described in Chapter 5.3. 11 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 12 Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Reference schematics. When DC2DC supply is used, maximum voltage into MLDO_OUT and LDO_IN = 2.145 V. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 15 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 9.2 RECOMMENDED OPERATING CONDITIONS No Rating Condition Symbol Min Max Unit 1 Power supply voltage 13 VDD_IN 1.7 4.8 V 2 IO power supply voltage VDD_IO 1.62 1.92 V 3 High-level input voltage Default VIH 0.65 x VDD_IO VDD_IO V 4 Low-level input voltage Default VIL 0 0.35 x VDD_IO V 5 IO Input rise/fall times, 10% to 90% 14 Tr/Tf 1 10 ns 0 to 0.1 MHz 60 0.1 to 0.5 MHz 50 0.5 to 2.5 MHz 30 2.5 to 3.0 MHz 15 6 Maximum ripple on VDD_IN (Sine wave) for 1.8 V (DC2DC) mode > 3.0 MHz 5 mVp-p 7 Voltage dips on VDD_IN (VBAT) (duration = 577 μs to2.31 ms, period = 4.6 ms) 400 mV 8 Maximum ambient operating temperature 15 70 °C 9 Minimum ambient operating temperature 16 -20 C 9.3 CURRENT CONSUMPTION No Characteristics Min 25°C Typ 25°C Max 25°C Min -20°C Typ -20°C Max -20°C Min +70°C Typ +70°C Max +70°C Unit 1 Current consumption in shutdown mode 17 1 3 7 μA 2 Current consumption in deep sleep mode 18 40 105 700 μA 3 Total IO current consumption for active mode 1 1 1 mA 4 Current consumption during transmit DH5 full throughput 40 mA 13 Excluding 1.98 < VDD_IN < 2.2 V range – not allowed. 14 Asynchronous mode. 15 The device can be reliably operated for 7 years at Tambient of 70°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours). 16 The device can be reliably operated for 7 years at Tambient of 70°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours). 17 Vbat + Vio 18 Vbat + Vio + Vsd (shutdown) CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 16 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 9.4 GENERAL ELECTRICAL CHARACTERISTICS No Rating Condition Min Max Value at 2/4/8 mA 0.8 x VDD_IO VDD_IO V 1 High-level output voltage, VOH at 0.1 mA VDD_IO – 0.2 VDD_IO V at 2/4/8 mA 0 0.2 x VDD_IO V 2 Low-level output voltage, VOL at 0.1 mA 0 0.2 V Resistance 1 MΩ 3 IO input impedance Capacitance 5 pF 4 Output rise/fall times,10% to 90% (Digital pins) CL = 20 pF 10 Ns PU typ = 6.5 3.5 9.7 TX_DBG, us PCM b PD typ = 27 9.5 55 μA PU typ = 100 100 300 5 IO pull currents All others PD typ = 100 100 360 μA 9.5 NSHUTD REQUIREMENTS No Parameter Symbol Min Max Unit 1 Operation mode level 19 V IH 1.42 1.98 V 2 Shutdown mode level VIL 0 0.4 V 3 Minimum time for nSHUT_DOWN low to reset the device 5 ms 4 Rise/fall times Tr/Tf 20 μs 9.6 EXTERNAL DIGITAL SLOW CLOCK REQUIREMENTS (–20°C TO +70°C) No Characteristics Condition Symbol Min Typ Max Unit 1 Input slow clock frequency 32768 Hz 2 Input slow clock accuracy (Initial + temp + aging) Bluetooth ±250 Ppm 3 Input transition time Tr/Tf – 10% to 90% Tr/Tf 100 Ns 4 Frequency input duty cycle 15% 50% 85% 5 Phase noise at 1 kHz -125 dBc/Hz 6 Jitter Integrated over 300 to 15000 Hz 1 Hz VIH 0.65 x VDD_IO VDD_IO 7 Slow clock input voltage limits Square wave, DC coupled VIL 0 0.35 x VDD_IO V peak 8 Input impedance 1 MΩ 9 Input capacitance 5 pF 19 Internal pull down retains shut down mode when no external signal is applied to this pin. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 17 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 10 HOST CONTROLLER INTERFACE The CC256X incorporates one UART module dedicated to the host controller interface (HCI) transport layer. The HCI interface transports commands, events, ACL, and synchronous data between the Bluetooth device and its host using HCI data packets. The UART module supports H4 (4-wires) protocol with maximum baud rate of 4 Mbps for all fast clock frequencies. After power up the baud rate is set for 115.2 kbps, irrespective of fast clock frequency. The baud rate can thereafter be changed with a vendor specific command. The CC256X responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change takes place. HCI hardware includes the following features: • Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions • Transmitter underflow detection • CTS/RTS hardware flow control The interface includes four signals: TXD, RXD, CTS, and RTS. Flow control between the host and the CC256X is byte-wise by hardware. Flow control is obtained by the following: When the UART RX buffer of the CC256X passes the “flow control” threshold, it will set the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the CC256X will stop its transmission on the interface. In case HCI_CTS is set high in the middle of transmitting a byte, the CC256X will finish transmitting the byte and stop the transmission. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 18 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 11 AUDIO/VOICE CODEC INTERFACE The codec interface is a fully-dedicated programmable serial port that provides the logic to interface to several kinds of PCM or I2S codec’s. PAN13XX supports all voice coding schemes required by Bluetooth specification – Log PCM (A-Law or μ-Law) and Linear (CVSD). In addition, module also supports transparent scheme: • Two voice channels • Master / slave modes • μ-Law, A-Law, Linear, Transparent coding schemes • Long and short frames • Different data sizes, order, and positions. • High rate PCM interface for EDR • Enlarged interface options to support a wider variety of codecs • PCM bus sharing 11.1 PCM HARDWARE INTERFACE The PCM interface is one implementation of the codec interface. It contains the following four lines: • Clock—configurable direction (input or output) • Frame Sync—configurable direction (input or output) • Data In—Input • Data Out—Output/3-state The Bluetooth device can be either the master of the interface where it generates the clock and the frame-sync signals, or slave where it receives these two signals. The PCM interface is fully configured by a vendor specific command. For slave mode, clock input frequencies of up to 16 MHz are supported. At clock rates above 12 MHz, the maximum data burst size is 32 bits. For master mode, the CC256X can generate any clock frequency between 64 kHz and 6 MHz. Please contact your sales representative if using the I2S bus over PCM. We strongly recommend adding a low pass filter (series resistor and capacitor to GND) to the bus for better noise suppression. It is not recommended to directly contact the host μController/DSP with the PCM interface. 11.2 DATA FORMAT The data format is fully configurable: • The data length can be from 8 to 320 bits, in 1-bit increments, when working with two channels, or up to 640 bits when using 1 channel. The Data length can be set independently for each channel. • The data position within a frame is also configurable in with 1 clock (bit) resolution and can be set independently (relative to the edge of the Frame Sync signal) for each channel. • The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start with the MSB while Data_Out starts with LSB. Each channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for sample sizes up to 24 bits. • It is not necessary for the data in and data out size to be the same length. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 19 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de • The Data_Out line is configured to ‘high-Z’ output between data words. Data_Out can also be set for permanent high-Z, irrespective of data out. This allows the CC256X to be a bus slave in a multi-slave PCM environment. At powerup, Data Out is configured as high-Z. 11.3 FRAME IDLE PERIOD The codec interface has the capability for frame idle periods, where the PCM clock can “take a break” and become ‘0’ at the end of the PCM frame, after all data has been transferred. The CC256X supports frame idle periods both as master and slave of the PCM bus. When CC256X is the master of the interface, the frame idle period is configurable. There are two configurable parameters: • Clk_Idle_Start – Indicates the number of PCM clock cycles from the beginning of the frame until the beginning of the idle period. After Clk_Idle_Start clock cycles, the clock will become ‘0’. • Clk_Idle_End – Indicates the time from the beginning of the frame till the end of the idle period. This time is given in multiples of PCM clock periods. The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period. For example, for PCM clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90. Between each two frame syncs there are 70 clock cycles (instead of 100). The clock idle period starts 60 clock cycles after the beginning of the frame, and lasts 90 – 60 = 30 clock cycles. This means that the idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end prior to the beginning of the idle period. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 20 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 11.4 CLOCK-EDGE OPERATION The codec interface of the CC256X can work on the rising or the falling edge of the clock. It also has the ability to sample the frame sync and the data at inversed polarity. This is the operation of a falling-edge-clock type of codec. The codec is the master of the PCM bus. The frame sync signal is updated (by the codec) on the falling clock edge and therefore shall be sampled (by the CC256X) on the next rising clock. The data from the codec is sampled (by the CC256X) on the clock falling edge. 11.5 TWO-CHANNEL PCM BUS EXAMPLE In below figure, a 2-channel PCM bus is shown where the two channels have different word sizes and arbitrary positions in the bus frame. (FT stands for Frame Timer) 11.6 AUDIO ENCODING The CC256X codec interface can use one of four audio-coding patterns: • A-Law (8-bit) • μ-Law (8-bit) • Linear (8- or 16-bit) CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 21 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 11.7 IMPROVED ALGORITHM FOR LOST PACKETS The CC256X features an improved algorithm for improving voice quality when received voice data packets are lost. There are two options: • Repeat the last sample – possible only for sample sizes up to 24 bits. For sample sizes >24 bits, the last byte is repeated. • Repeat a configurable sample of 8 to 24 bits (depends on the real sample size), in order to simulate silence (or anything else) in the PCM bus. The configured sample will be written in a specific register for each channel. The choice between those two options is configurable separately for each channel. 11.8 BLUETOOTH/PCM CLOCK MISMATCH HANDLING In Bluetooth RX, the CC256X receives RF voice packets and writes these to the codec I/F. If the CC256X receives data faster than the codec I/F output allows, an overflow will occur. In this case, the Bluetooth has two possible behaviour modes: ‘allow overflow’ and ‘don’t allow overflow’. • If overflow is allowed, the Bluetooth will continue receiving data and will overwrite any data not yet sent to the codec. • If overflow is not allowed, RF voice packets received when buffer is full will be discarded. 11.9 BLUETOOTH INTER-IC SOUND (I2S) The CC256X can be configured as an Inter-IC Sound (I2S) serial interface to an I2S codec device. In this mode, the CC256X audio codec interface is configured as a bi-directional, full-duplex interface, with two time slots per frame: Time slot 0 is used for the left channel audio data and time slot 1 for the right channel audio data. Each time slot is configurable up to 40 serial clock cycles in length and the frame is configurable up to 80 serial clock cycles in length. Do not connect the the microcontroller/DSP directly to the module's PCM interface, a simple RC low pass filter is recommended to improve noise suppression. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 22 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 11.10 CURRENT CONSUMPTION FOR DIFFERENT BLUETOOTH SCENARIOS The following table gives average current consumption for different Bluetooth scenarios. Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 4 dBm output power. 12 BLUETOOTH RF PERFORMANCE No Characteristics Typ BT Spec Max BT Spec Min Class1 Class1 1 Average Power Hopping DH5 [dBm] 21, 22 7.2 20 4 2 Average Power: Ch0 [dBm] 21, 22 7.5 20 4 3 Peak Power: Ch0 [dBm] 21, 22 7.7 23 4 Average Power: Ch39 [dBm] 21, 22 7.0 20 4 5 Peak Power: Ch39 [dBm] 21, 22 7.2 23 6 Average Power: Ch78 [dBm] 21, 22 6.7 20 4 7 Peak Power: Ch78 [dBm] 21, 22 7.0 23 8 Max. Frequency Tolerance: Ch0 [kHz] -2.6 75 -75 9 Max. Frequency Tolerance: Ch39 [kHz] -2.2 75 -75 10 Max. Frequency Tolerance: Ch78 [kHz] -2.1 75 -75 11 Max. Drift: Ch0_DH1 [kHz] 3.6 25 -25 12 Max. Drift: Ch0_DH3 [kHz] 3.7 40 -40 13 Max. Drift: Ch0_DH5 [kHz] 4.0 40 -40 14 Max. Drift Rate: Ch0_DH1 [kHz] -2.6 20 -20 15 Max. Drift Rate: Ch0_DH3 [kHz] -3.2 20 -20 16 Max. Drift Rate: Ch0_DH5 [kHz] -3.3 20 -20 17 Max. Drift: Ch39_DH1 [kHz] 4.0 25 -25 18 Max. Drift: Ch39_DH3 [kHz] 4.3 40 -40 19 Max. Drift: Ch39_DH5 [kHz] 4.3 40 -40 20 Max. Drift Rate: Ch39_DH1 [kHz] -3.1 20 -20 21 Max. Drift Rate: Ch39_DH3 [kHz] -3.6 20 -20 22 Max. Drift Rate: Ch39_DH5 [kHz] -3.7 20 -20 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 23 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de No Characteristics Typ BT Spec Max BT Spec Min Class1 Class1 23 Max. Drift: Ch78_DH1 [kHz] 4.1 25 -25 24 Max. Drift: Ch78_DH3 [kHz] 4.5 40 -40 25 Max. Drift: Ch78_DH5 [kHz] 4.4 40 -40 26 Max. Drift Rate: Ch78_DH1 [kHz] -3.4 20 -20 27 Max. Drift Rate: Ch78_DH3 [kHz] -3.9 20 -20 28 Max. Drift Rate: Ch78_DH5 [kHz] -4.1 20 -20 29 Delta F1 Avg: Ch0 [kHz] 159.5 175 140 30 Delta F2 Max.: Ch0 [%] 100.0 99.9 31 Delta F2 Avg/Delta F1 Avg: Ch0 0.9 0.8 32 Delta F1 Avg: Ch39 [kHz] 159.8 175 140 33 Delta F2 Max.: Ch39 [%] 100.0 99.9 34 Delta F2 Avg/Delta F1 Avg: Ch39 0.9 0.8 35 Delta F1 Avg: Ch78 [kHz] 159.1 175 140 36 Delta F2 Max.: Ch78 [%] 100.0 99.9 37 Delta F2 Avg/Delta F1 Avg: Ch78 0.9 0.8 45 Sensitivity -93.0 -81 46 f(H)-f(L): Ch0 [kHz] 918.4 1000 47 f(H)-f(L): Ch39 [kHz] 918.3 1000 48 f(H)-f(L): Ch78 [kHz] 918.2 1000 49 ACPower -3: Ch3 [dBm] -51.5 -40 50 ACPower -2: Ch3 [dBm] -50.4 -40 51 ACPower -1: Ch3 [dBm] -18.5 52 ACPower Center: Ch3 [dBm] 8.1 20 4 53 ACPower +1: Ch3 [dBm] -19.2 54 ACPower +2: Ch3 [dBm] -50.7 -40 55 ACPower +3: Ch3 [dBm] -53.3 -40 56 ACPower -3: Ch39 [dBm] -51.6 -40 57 ACPower -2: Ch39 [dBm] -50.7 -40 58 ACPower -1: Ch39 [dBm] -19.0 59 ACPower Center: Ch39 [dBm] 7.7 20 4 60 ACPower +1: Ch39 [dBm] -19.7 61 ACPower +2: Ch39 [dBm] -50.9 -40 62 ACPower +3: Ch39 [dBm] -53.2 -40 63 ACPower -3: Ch75 [dBm] -51.7 -40 64 ACPower -2: Ch75 [dBm] -50.7 -40 65 ACPower -1: Ch75 [dBm] -19.2 66 ACPower Center: Ch75 [dBm] 7.5 20 4 67 ACPower +1: Ch75 [dBm] -20.0 68 ACPower +2: Ch75 [dBm] -51.0 -40 69 ACPower +3: Ch75 [dBm] -53.4 -40 70 omega i 2-DH5: Ch0 [kHz] -4.7 75 -75 71 omega o + omega i 2-DH5: Ch0 [kHz] -6.0 75 -75 72 omega o 2-DH5: Ch0 [kHz] -1.5 10 -10 73 DEVM RMS 2-DH5: Ch0 [%] 0.0 0.2 74 DEVM Peak 2-DH5: Ch0 [%] 0.1 0.35 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 24 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de No Characteristics Typ BT Spec Max BT Spec Min Class1 Class1 75 DEVM 99% 2-DH5: Ch0 [%] 100.0 99 76 omega i 3-DH5: Ch0 [kHz] -3.7 75 -75 77 omega o + omega i 3-DH5: Ch0 [kHz] -5.8 75 -75 78 omega o 3-DH5: Ch0 [kHz] -2.6 10 -10 79 DEVM RMS 3-DH5: Ch0 [%] 0.0 0.13 80 DEVM Peak 3-DH5: Ch0 [%] 0.1 0.25 81 DEVM 99% 3-DH5: Ch0 [%] 100.0 99 82 omega i 2-DH5: Ch39 [kHz] -4.8 75 -75 83 omega o + omega i 2-DH5: Ch39 [kHz] -6.1 75 -75 84 omega o 2-DH5: Ch39 [kHz] -1.4 10 -10 85 DEVM RMS 2-DH5: Ch39 [%] 0.0 0.2 86 DEVM Peak 2-DH5: Ch39 [%] 0.1 0.35 87 DEVM 99% 2-DH5: Ch39 [%] 100.0 99 88 omega i 3-DH5: Ch39 [kHz] -3.8 75 -75 89 omega o + omega i 3-DH5: Ch39 [kHz] -5.9 75 -75 90 omega o 3-DH5: Ch39 [kHz] -2.6 10 -10 91 DEVM RMS 3-DH5: Ch39 [%] 0.0 0.13 92 DEVM Peak 3-DH5: Ch39 [%] 0.1 0.25 93 DEVM 99% 3-DH5: Ch39 [%] 100.0 99 94 omega i 2-DH5: Ch78 [kHz] -4.9 75 -75 95 omega o + omega i 2-DH5: Ch78 [kHz] -6.2 75 -75 96 omega o 2-DH5: Ch78 [kHz] -1.4 10 -10 97 DEVM RMS 2-DH5: Ch78 [%] 0.0 0.2 98 DEVM Peak 2-DH5: Ch78 [%] 0.1 0.35 99 DEVM 99% 2-DH5: Ch78 [%] 100.0 99 100 omega i 3-DH5: Ch78 [kHz] -3.8 75 -75 101 omega o + omega i 3-DH5: Ch78 [kHz] -6.0 75 -75 102 omega o 3-DH5: Ch78 [kHz] -2.7 10 -10 103 DEVM RMS 3-DH5: Ch78 [%] 0.0 0.13 104 DEVM Peak 3-DH5: Ch78 [%] 0.1 0.25 105 DEVM 99% 3-DH5: Ch78 [%] 100.0 99 No Characteristics Condition Min Typ Max BT Spec Unit 1 Operation frequency range 2402 2480 MHz 2 Channel spacing 1 MHz 3 Input impedance 50 Ω GFSK, BER = 0.1% -93.0 -70 Pi/4-DQPSK, BER = 0.01% -92.5 -70 4 Sensitivity, Dirty Tx on 8DPSK, BER = 0.01% -85.5 -70 dBm CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 25 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de No Characteristics Condition Typ Max Unit 30 kHz to 1 GHz 20, 21, 22 -30 1 Tx and Rx out-of-band emissions Output signal = 7dBm 1 to 12.75 GHz 20, 21, 22 -30 dBm 2 2nd harmonic at 7dBm output power 20, 21, 22 -30 dBm 3 3rd harmonic at 7dBm output power 20, 21, 22 -30 dBm The values are measured conducted. Better suppression of the spurious emissions with an antenna can be expected as, antenna frequently have band pass filter characteristics. 13 SOLDERING TEMPERATURE-TIME PROFILE (FOR REFLOW SOLDERING) 13.1 FOR LEAD SOLDER Recommended temp. profile for reflow soldering Temp.[°C] Time [s] 235°C max. 220 ±5°C 200°C150 ±10°C 90 ±30s 10 ±1s 30 +20/-10s 20 Includes effects of frequency hopping 21 Average according FCC, IC and ETSI requirements. Above +7dBm output power (refer also to 22) the customer has to verify the final product against national regulations. 22 +7dBm related to power register value 18, according to TI service pack 2.30 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 26 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 13.2 FOR LEADFREE SOLDER Our used temp. profile for reflow soldering Temp.[°C] Time [s] 230°C -250°C max. 220°C150°C – 190°C 90 ±30s 30 +20/-10s Reflow permissible cycle: 2 Opposite side reflow is prohibited due to module weight. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 27 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 14 MODULE DIMENSION 14.1 MODULE DIMENSIONS PAN131X WITHOUT ANTENNA No. Item Dimension Tolerance Remark 1 Width 6.50 ± 0.20 2 Lenght 9.00 ± 0.20 3 Height 1.80 ± 0.20 With case PAN131X Module Drawing CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 28 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 14.2 MODULE DIMENSIONS PAN132X WITH ANTENNA No. Item Dimension Tolerance Remark 1 Width 9.50 ± 0.20 2 Lenght 9.00 ± 0.20 3 Height 1.80 ± 0.20 With case PAN132X Module Drawing CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 29 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 15 FOOTPRINT OF THE MODULE 15.1 FOOTPRINT PAN131X WITHOUT ANTENNA All dimensions are in millimeters. The outer dimensions have a tolerance of ± 0.2mm. The layout is symetric to center. The inner pins (2,4,6,9,11,14,16,18,21,23) are shifted to the center by 1mm. 0.901.706,500.901.809,00171513141211987653212324211819202210416Pad = 24 x 0.60mm x 0.60mmTop View1.802.702.953.95 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 30 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 15.2 FOOTPRINT PAN132X WITH ANTENNA All dimensions are in millimeters. The outer dimensions have a tolerance of ± 0.2mm. The layout is symetric to center. The inner pins (2,4,6,9,11,14,16,18,21,23) are shifted to the center by 1mm. 2.700.901.709.50171513141211987653212324211819202210416Pad = 28 x 0.60mm x 0.60mm1.80ACBD1.800.551.001.80 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 31 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 16 LABELING DRAWING The above pictures show the laser marking on the top case, this is only an example from PAN1315. 17 MECHANICAL REQUIREMENTS No. Item Limit Condition 1 Solderability More than 75% of the soldering area shall be coated by solder Reflow soldering with recommendable temperature profile 2 Resistance to soldering heat It shall be satisfied electrical requirements and not be mechanical damage See Chapter 13.2 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 32 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 18 RECOMMENDED FOOT PATTERN 18.1 RECOMMENDED FOOT PATTERN PAN131X WITHOUT ANTENNA Dimensions in mm. 171513141211987653212324211819202210416Pad = 24 x 0.60mm x 0.60mmTop View9,00 6,008,50 The land pattern dimensions above are meant to serve only as a guide. This information is provided without any legal liability. For the solder paste screen, use as a first guideline the same foot print as shown in the figure above. Solder paste screen cutouts (with slightly different dimensions) might be optimum depending on your soldering process. For example, the solder paste screen thickness chosen might have an effect. The solder screen thickness depends on your production standard 120μm to 150μm is recommended. IMPORTANT: Although the bottom side of PAN131X is fully coated, no copper such as through hole vias, planes or tracks on the board component layer should be located below the PAN131X to avoid creating a short. In cases where a track or through hole via has to be located under the module, it must be kept away from PAN131X bottom pads. The PAN131X multilayer pcb contains an inner RF shielding plane, therefore no pcb shielding plane below the module is needed. When using an onboard ceramic antenna, place the antenna on the edge of your carrier board (if allowable). If you have any questions on these points, contact your local Panasonic representative. Schematics and layouts may be sent to wireless@eu.panasonic.com for final review. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 33 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 18.2 RECOMMENDED FOOT PATTERN PAN132X WITH ANTENNA Dimensions in mm. The land pattern dimensions above are meant to serve only as a guide. For the solder paste screen, use as a first guideline the same foot print as shown in the Figure above. Solder paste screen cutouts (with slightly different dimensions) might be optimum depending on your soldering process. For example, the solder paste screen thickness chosen might have an effect. The solder screen thickness depends on your production standard 120μm to 150μm is recommended. IMPORTANT: In cases where a track or through hole via has to be located under the module, it must be kept away from PAN132X bottom pads. The PAN132X multilayer pcb contains an inner RF shielding plane, therefore no pcb shielding plane below the module is needed. If you have any questions on these points, contact your local Panasonic representative. Schematics and layouts may be sent to wireless@eu.panasonic.com for final review. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 34 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 19 LAYOUT RECOMMENDATIONS WITH ANTENNA (PAN132X) 20 BLUETOOTH LE (LOW ENERGY) PAN1316/26 20.1 NETWORK TOPOLOGY Bluetooth Low Energy is designed to reduce power consumption. It can be put into a sleep mode and is only activated for event activities such as sending files to a gateway, PC or mobile phone. Furthermore the maximum power consumption is set to less than 15 mA and the average power consumption is about 1 uA. The benefit of low energy consumption are short messages and establishing very fast connections (few ms). Using these techniques, energy consumption is reduced to a tenth of a Classic Bluetooth unit. Thus, a small coin cell – such as a CR2032 – is capable of powering a device for up to 10 years of operation. T o be backwards compatible with Classic Bluetooth and to be able to offer an affordable solution for very inexpensive devices, Panasonic Low Energy Bluetooth modules are offered in two versions: CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 35 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de Dual-mode: Bluetooth Low Energy technology combined with Classic Bluetooth functionality on a single module. Dual mode devices act as gateways between these two technologies. Single Mode: Bluetooth Low Energy technology to optimize power consumption, which is particularly useful for products powered by small batteries. These modules have embedded controllers allowing the module to operate autonomously in low cost applications that lack intelligence. This data sheet describes dual-mode Bluetooth Low Energy technology combined with Classic Bluetooth functionality on a single module. Additional information on Panasonic’s single mode products can be found by visiting www.panasonic.com/rfmodules or write an e-mail to wireless@eu.panasonic.com. 20.2 MODULE FEATURES Fully compliant with Bluetooth 4.0: • Optimized for proximity and sports use • Supports up to 10 simultaneous connections • Multiple sniff instances are tightly coupled to minimize power consumption • Independent buffering allows a large number of multiple connections without affecting BR/EDR performance • Includes built-in coexistence and prioritization handling for BR/EDR and LE CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 36 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 20.3 CURRENT CONSUMPTION FOR DIFFERENT LE SCENARIOS Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10 dBm output power Mode Description Average Current Unit Advertising, non-connectable Advertising in all 3 channels 1.28msec advertising interval 15Bytes advertise Data 104 μA Advertising, discoverable Advertising in all 3 channels 1.28msec advertising interval 15Bytes advertise Data 121 μA Scanning Listening to a single frequency per window 1.28msec scan interval 11.25msec scan window 302 μA Connected (master role) 500msec connection interval 0msec Slave connection latency Empty Tx/Rx LL packets 169 μA 21 ANT PAN1317/27 ANT+ (sometimes ANT + or ANT Plus) is an interoperability function that can be added to the base ANT protocol (a proprietary wireless sensor network technology).[ 21.1 NETWORK TOPOLOGY ANT™ is a wireless sensor network protocol operating in the 2.4 GHz spectrum. Designed for ultra-low power, ease of use, efficiency and scalability, ANT supports peer-to-peer, star, tree and fixed mesh topologies. It provides reliable data communications, flexible and adaptive network operation and cross-talk immunity. The ANT protocol stack is compact, requiring minimal microcontroller resources to reduce system costs, lighten the computational burden and improve efficiency. Low-level security is implemented to allow user-defined network security. PAN1317/1327 provides the first wireless, single-chip solution with dual-mode ANT and Bluetooth connectivity with inclusion of TI’s CC2567 device. This solution wirelessly connects 13 million ANT-based devices to the more than 3 billion Bluetooth endpoint devices used by people every day, creating new market opportunities for companies building ANT products and Bluetooth products alike. CC2567 requires 80% less board area than a design with two single-mode solutions (one ANT+, one Bluetooth) and increases the wireless transmission range up to two times the distance of a single-mode ANT+ solution. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 37 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 21.2 MODULE FEATURES Fully compliant with ANT protocol: • ANT solution optimized for fitness, health and consumers use cases • Supports up to eight simultaneous connections, various network topologies and high-resolution proximity pairing • Includes built-in coexistence and prioritization handling for BR/EDR and ANT Features Benefits Dual-mode ANT+ and Bluetooth (Bluetooth v2.1 + EDR) on a single chip - Requires 80% less board area than any dual module or device design - Reduces costs associated with incorporating two wireless technologies Fully validated optimized single antenna solution - Enables simultaneous operation of ANT+ and Bluetooth without the need for two devices or modules - Includes built-in coexistence Best-in-class Bluetooth and ANT RF performance: - +10 dBm Tx power with transmit power control - -93 dBm sensitivity - Delivers twice the distance between the aggregator and ANT sensor device than competitive single-mode ANT solutions - Enables a robust and high-throughput connection with extended range Support for: - ANT+ ultra low power (master and slave devices) - Bluetooth power saving modes (park, sniff, hold) - Bluetooth ultra low power modes (deep sleep, power down) - Improves battery life and power efficiency of the finished product Turnkey solution: - Fully integrated module - Complete development kit with software and documentation - TI MSP430 hardware and software platform integration (optional) - Ease of integration into system allows quick time to market - Reduces costs and time associated with certification 21.3 ANT CURRENT CONSUMPTION Mode Description Average Current Unit Rx message mode 250msec interval 380 μA Rx message mode 500msec interval 205 μA Rx message mode 1000msec interval 118 μA CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 38 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 22 TRIPLE MODE (BR/EDR + BLUETOOTH LOW ENERGY + ANT) PAN1323 The PAN1323 has been engineered to give designers the flexibility to implement Bluetooth Classic (BR/EDR), Bluetooth Low Energy and ANT into an application using a single module, reducing cost and footprint area. Refer to the paragraphs above for complete descriptions on each of the three protocols. The module is fully hardware compatible with the PAN1315, 15A, 16, 17, 25, 25A, 26 and 27. A highly efficent single RF block serves all three protocols. Protocols access the RF block using time division multiplexing. The application layer determines the priority and timing of the RF block.Customers interested in this unique module are encouraged to contact StoneStreetOne for a Bluetooth SIG certified stack. 22.1 TRIPLE MODE CURRENT CONSUMPTION The current consumption of the PAN1326 is a function of the protocol that the module is running at any point in time. Refer to the paragraphs above for details on current consumption for each of the three protocols or software vendor. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 39 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 23 DEVELOPMENT OF APPLICATIONS Mindtree Ltd. has developed a Bluetooth SPP freeware for TIs MSP430 and Panasonics PAN1315(A) and PAN1325(A). For other software refer to Chapter 24 or visit the following link www.panasonic.com/rfmodules. 23.1 TOOLS TO BE NEEDED PAN1323ETU Tool Source TI - MSP-EXP430F5438 - Experimenter Board MSP-EXP430F5438 TI - MSP-FET430UIF430 - Debugging Interface MSP-FET430UIF430 TI PAN1323EMK PAN1323EMK - Bluetooth Evaluation Module Kit for MSP430 Panasonic PAN1323ETU CC2567-PAN1327ANT-BTKIT For information on Bluetooth + ANT kit for PAN1327 CC2567 + PAN1327 wiki In addition you need the software development environment, e.g. IAR Embedded Workbench, refer to: http://wiki.msp430.com/index.php/MSP430_Bluetooth_Platform Evaluation kits and modules are available through Panasonic’s network of authorized distributors. For any additional information, please visit www.panasonic.com/rfmodules. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 40 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 24 LIST OF PROFILES Profile Software Developer Controller Availability Bluetooth SPP and others MindTree TI, MSP430 Now SPP Seeran STM32, MSP430 Now HDP, SPP Stollmann TI, MSP430 Now A2DP, AVRCP, SPP StoneStreetOne TI, Stellaris Now SPP and others ARS Multiple Now Bluetooth LE All ARS, MindTree, StoneStreetOne, Stollmann TI, MSP430 and others Upon request ANT Protocoll ANT Dynastream MSP430 and others Now Triple Mode Stack SPP StoneStreetOne MSP430 and others Now For all other profiles contact your local sales representative. 25 RELIABILITY TESTS The measurement should be done after being exposed to room temperature and humidity for 1 hour. No. Item Limit Condition 1 Vibration test Electrical parameter should be in specification a) Freq.:10~50Hz,Amplitude:1.5mm a) 20min. / cycle,1hrs. each of XYZ axis b) Freq.:30~100Hz, 6G b) 20min. / cycle,1hrs. each of XYZ axis 2 Shock test the same as above Dropped onto hard wood from height of 50cm for 3 times 3 Heat cycle test the same as above -40°C for 30min. and +85°C for 30min.; each temperature 300 cycles 4 Moisture test the same as above +60°C, 90% RH, 300h 5 Low temp. test the same as above -40°C, 300h 6 High temp. test the same as above +85°C, 300h CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 41 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 26 CAUTIONS Failure to follow the guidelines set forth in this document may result in degrading of the product’s functions and damage to the product. 26.1 DESIGN NOTES (1) Follow the conditions written in this specification, especially the control signals of this module. (2) The supply voltage has to be free of AC ripple voltage (for example from a battery or a low noise regulator output). For noisy supply voltages, provide a decoupling circuit (for example a ferrite in series connection and a bypass capacitor to ground of at least 47uF directly at the module). (3) This product should not be mechanically stressed when installed. (4) Keep this product away from heat. Heat is the major cause of decreasing the life of these products. (5) Avoid assembly and use of the target equipment in conditions where the products' temperature may exceed the maximum tolerance. (6) The supply voltage should not be exceedingly high or reversed. It should not carry noise and/or spikes. (7) Keep this product away from other high frequency circuits. 26.2 INSTALLATION NOTES (1) Reflow soldering is possible twice based on the conditions in Chapter 15. Set up the temperature at the soldering portion of this product according to this reflow profile. (2) Carefully position the products so that their heat will not burn into printed circuit boards or affect the other components that are susceptible to heat. (3) Carefully locate these products so that their temperatures will not increase due to the effects of heat generated by neighboring components. (4) If a vinyl-covered wire comes into contact with the products, then the cover will melt and generate toxic gas, damaging the insulation. Never allow contact between the cover and these products to occur. (5) This product should not be mechanically stressed or vibrated when reflowed. (6) To repair a board by hand soldering, keep the conditions of this chapter. (7) Do not wash this product. (8) Refer to the recommended pattern when designing a board. (9) Pressing on parts of the metal cover or fastening objects to the metal will cause damage to the unit. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 42 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 26. 3 USAGE CONDITIONS NOTES (1) T ake measures to protect the unit against static electricity. If pulses or other transient loads (a large load applied in a short time) are applied to the products, check and evaluate their operation befor assembly on the final products. (2) Do not use dropped products. (3) Do not touch, damage or soil the pins. (4) Follow the recommended condition ratings about the power supply applied to this product. (5) Electrode peeling strength: Do not add pressure of more than 4.9N when soldered on PCB. (6) Pressing on parts of the metal cover or fastening objects to the metal cover will cause damage. (7) These products are intended for general purpose and standard use in general electronic equipment, such as home appliances, office equipment, information and communication equipment. 26. 4 STORAGE NOTES (1) T he module should not be stressed mechanically during storage. (2) Do not store these products in the following conditions or the performance characteristics of the product, such as RF performance will be adversely affected: • St orage in salty air or in an environment with a high concentration of corrosive gas, such as Cl2, H2S, NH3, SO2, or NOX • Storage in direct sunlight • Storage in an environment where the temperature may be outside the range of 5°C to 35°C range, or where the humidity may be outside the 45 to 85% range. • Storage of the products for more than one year after the date of delivery Storage period: check the adhesive strength of the embossed tape and soldering after 6 months of storage. ( 3) Keep this product away from water, poisonous gas and corrosive gas. (4) This product should not be stressed or shocked when transported. (5) Follow the specification when stacking packed crates (max. 10). CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 43 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 26. 5 SAFETY CAUTIONS These specifications are intended to preserve the quality assurance of products and individual components. Before use, check and evaluate the operation when mounted on your products. Abide by these specifications, without deviation when using the products. These products may short-circuit. If electrical shocks, smoke, fire, and/or accidents involving human life are anticipated when a short circuit occurs, then provide the following failsafe functions, as a minimum. (1) Ensure the safety of the whole system by installing a protection circuit and a protection device. (2) Ensure the safety of the whole system by installing a redundant circuit or another system to prevent a single fault causing an unsafe status. 26. 6 OTHER CAUTIONS (1) T his specification sheet is copyrighted. (2) Do not use the products for other purposes than those listed. (3) Be sure to provide an appropriate fail-safe function on your product to prevent an additional damage that may be caused by the abnormal function or the failure of the product. (4) This product has been manufactured without any ozone chemical controlled under the Montreal Protocol. (5) These products are not intended for other uses, other than under the special conditions shown below. Before using these products under such special conditions, check their performance and reliability under the said special conditions carefully to determine whether or not they can be used in such a manner. • In liquid, such as water, salt water, oil, alkali, or organic solvent, or in places where liquid may splash. • In direct sunlight, outdoors, or in a dusty environment • In an environment where condensation occurs. • In an environment with a high concentration of harmful gas (e.g. salty air, HCl, Cl2, SO2, H2S, NH3, and NOX) ( 6) If an abnormal voltage is applied due to a problem occurring in other components or circuits, replace these products with new products because they may not be able to provide normal performance even if their electronic characteristics and appearances appear satisfactory. (7) When you have any question or uncertainty, contact Panasonic. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 44 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 27 PACKAGING 27 .1 PACKAGING OF PAN131X WITHOUT ANTENNA Tape Dimension Packing in Tape trailer (empty)1 x circumference /hub(min 160mm)component packed areastandard 1500pcsleader (empty)minimum 10 pitchTop cover tape more than 1 x circumference plus 100mm to avoid fixing of tape end on sealed modules.Direction of unreeling (for customer)PAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-BarcodePAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-Barcode Empty spaces in component packed area shall be less than two per reel and those spaces shall not be consecutive. Top cover tape shall not be found on reel holes and shall not stick out from reel. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 45 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de Component direction PAN1315 01/01ENW89809M5AYYWWDLLFCC ID: T7V1315Machine readable 2D-Barcode Reel dimension A BD NW2MAXMINMIN±1.0MAX13 +0.525.0 +2.024.4 +3.0 -0.2 -0.0 -0.5*Latch (2PC)All dimensions in millimeters unless otherwise stated Assembly Method24mm330.01.520.2100.030.4*LatchTAPE SIZECW1W3 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 46 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de Label for Package PAN1315Customer CodeENW89818C2JF105 mm (1T) Lotcode [YYWWDLL] Example from above: YY year printed 08 WW normal calendar week printed 01 D day printed 5 (Friday) L line identifier, if more as one printed 1 L lot identifier per day printed 1 (1P) Customer Order Code, if any, otherwise company name will be printed (2P) Panasonic Order Code fix as ENW89818C2JF (9D) Datecode as [YYWW] (Q) Quantity [XXXX], variable max. 1500 (HW/SW) Hardware /Software Release Total Package CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 47 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 27.2 PACKAGING FOR PAN132X WITH ANTENNA Tape Dimension Measured from centreline of sprocket holeMeasured holeCumulative tolerance of 10 sprocketMeasured from centreline of sprocketto centreline of pocket.holes is ± 0.20 .hole to centreline of pocket.(I)(II)(III)(IV)Other material available.ALL DIMENSIONS IN MILLIMETRES UNLESS OTHERWISE STATED.WFP1+/-0.10+/-0.10+/-0.307.5012.0016.00K12.00+/-0.102.80+/-0.10+/-0.109.40BoKo9.90Ao+/-0.10 Tooling code: Flatbed -9 Estimated Max Length: 72m per 22B3 YYXXSECTION Y-Y SCALE 3.5 : 1SECTION X-X SCALE 3.5 : 1 Packing in Tape All other packaging information is similar to Chapter 27.1 Pin1 Marking CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 48 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 28 O RDERING INFORMATION Version Function Controller Part number Antenna on board Notes MOQ (1) PAN1315(2) CC2560 ENW89818C2JF NO PAN1315A Bluetooth v2.1 + EDR CC2560A ENW89829C2JF NO CC2560A offers reductions in init script size over CC2560 and is recommended for all new designs 1500 PAN1325(2) CC2560 ENW89818A2JF YES PAN1325A Bluetooth v2.1 + EDR CC2560A ENW89829A2JF YES CC2560A offers reductions in init script size over CC2560 and is recommended for all new designs. 1500 PAN1316 Bluetooth v2.1 + EDR BLE 4.0 CC2564 ENW89823C2JF NO 1500 PAN1326 Bluetooth v2.1 + EDR BLE 4.0 CC2564 ENW89823C2JF YES 1500 PAN1317 Bluetooth v2.1 + EDR ANT CC2567 ENW89827C2JF NO 1500 PAN1327 Bluetooth v2.1 + EDR ANT CC2567 ENW89827A2JF YES 1500 PAN1323 Bluetooth v2.1 + EDR BLE 4.0 ANT CC2569 ENW89842A2JF YES Check with your software developer for details on triple mode functionality. 1500 PAN1323ETU Bluetooth v2.1 + EDR BLE 4.0 ANT CC25xx ENW89825A2JF YES Evaluation kit for the whole series. PAN1315-PAN1327. 1 Notes: (1 ) Abbreviation for Minimum Order Quantity (MOQ). The standard MOQ for mass production are 1500 pieces, fewer only on customer demand. Samples for evaluation can be delivered at any quantity. (2) Not recommended for new designs, please refer to Chapter 1.1 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 49 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 29 ROHS DECLARATION Declaration of environmental compatibility for supplied products: Hereby we declare to our best present knowledge based on declaration of our suppliers that this product do not contain by now the following substances which are banned by Directive 2002/95/EC (RoHS) or if contain a maximum concentration of 0,1% by weight in homogeneous materials for • Le ad and lead compounds • M ercury and mercury compounds • Chromium (VI) • PBB (polybrominated biphenyl) category • PBDE (polybrominated biphenyl ether) category And a maximum concentration of 0,01% by weight in homogeneous materials for • Cadmium and cadmium compounds 3 0 DATA SHEET STATUS This data sheet contains the final specification (RELEASE). Panasonic reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Supplementary data will be published at a later date. Consult the most recently issued data sheet before initiating or completing a design. Use this URL to search for the most recent version of this data sheet: PAN13xx Latest Data Sheet! CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 50 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 3 1 HISTORY FOR THIS DOCUMENT Revision Date Modification / Remarks 0.90 18.12.2009 1st preliminary version 0.95 01.03.2010 Updated Chapter 14.2 and 28. 0.96 Not released Change ESD Information on foot note 7 in chapter Pin Description 0.97 25.03.2010 Various updates. Deleted links to TI Datasheet. 0.98 21.04.2010 Updated Links Some minor changes in Chapter 8 and 9.1 and change the base for the values in Chapter 9. 0.99 22.10.2010 Adopted changes according to CC2560 Datasheet. Included Interface Description, performance values. Not released. 1.00 04.11.2010 1st internal Release. 1.01 03.12.2010 Included reference to PAN1325 Application Note. AN-1325-2420-111.pdf 1.02 10.01.2011 Changed wording in Chapter 34.2 ” Industry Canada Certification ”. 1.03 23.05.2011 Included DOC for PAN1315 series. Included PAN13xx ANT and BLE Addendum Rev1.x.pdf reference. Included Note for IO voltage and MLD_OUT pin. 1.04 02.07.2011 Corrected wording in Chapter 34.3 Europ ean R&TTE Declaration of Conformity . 1.05 28.10.2011 Including CC2560A silicon PAN1315A HW40 at Chapter 1.1, Chapter and Chapter 0. Deleted ES label in Chapter 1.06 15.11.2011 Added overview for the core specification and their addendums. Updated front page. Updated Related Documents. 3.00 11.01.2012 Merging PAN13xx documents into this specification and correct some format 3.10 16.01.2012 Minor mistakes fixed 3.20 29.05.2012 DoC replaced with revised version 3.30 11.06.2012 Added triple mode stack Module PAN1323, add PAN1323 to ordering and software information overview, Software Block Diagram added, Bluetooth Inter IC-Sound chapter information added Layout Recommandations with Antenna added, Application Note LGA added 3.31 27.06.2012 Added design information to use low pass filter (chapter 11.1 / 11.9) for better noise surpression when using PCM interface 3.40 18.07.2012 Re-organize chapter Re gulatory Information and added 2 chapters 1. NCC St atement (only valid for PAN1325) 2. Blu etooth SIG Statement 3. Chapter 11.9, Second Paragraph was updated 4. Link in Chapter 34.1.1. was fixed 32 RELATED DOCUMENTS For an update, search in the suitable homepage. [1 ] PAN1323ETU Design-Guide: http://www.panasonic.com/industrial/includes/pdf/PAN1323ETUDesignGuide.pdf [2 ] CC2560 Product Bulletin: http://focus.ti.com/pdfs/wtbu/cc2560_slyt377.pdf [3] Bluetooth SW for MSP430 is supported by IAR IDE service pack 5.10.6 and later. Use full IAR version edition (not the kick-start version). You can find info on IAR at http://www.iar.com/website1/1.0.1.0/3/1/ and www.MSP430.com . Note, that there is an option for a 30-day free version of IAR evaluation edition. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 51 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de [4] PAN13xx CAD data: http://www.pedeu.panasonic.de/pdf/174ext.zip [5] Application Note Land Grid Array: http://www.pedeu.panasonic.de/pdf/184ext.pdf CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 52 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 33 GENERAL INFORMATION © Panasonic Industrial Devices Europe GmbH. All rights reserved. This document may contain errors. Panasonic reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its literature at any time. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to Panasonic’s terms and conditions of sale supplied at the time of order acknowledgment. If we deliver ES samples to the customer, these samples have the status Engineering Samples. This means, the design of this product is not yet concluded. Engineering Samples may be partially or fully functional, and there may be differences to be published Data Sheet. Engineering Samples are not qualified and are not to be used for reliability testing or series production. Disclaimer: Customer acknowledges that samples may deviate from the Data Sheet and may bear defects due to their status of development and the lack of qualification mentioned above. Panasonic rejects any liability or product warranty for Engineering Samples. In particular, Panasonic disclaims liability for damages caused by • th e use of the Engineering Sample other than for Evaluation Purposes, particularly the installation or integration in an other product to be sold by Customer, • de viation or lapse in function of Engineering Sample, • im proper use of Engineering Samples. Panasonic disclaimes any liability for consequential and incidental damages. Panasonic assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using Panasonic components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. In case of any questions, contact your local sales representative. 34 REGULATORY INFORMATION 34 .1 FCC FOR US 3 4.1.1 FCC Notice The devices PAN13xx, for details refer to Chapter 28 in this document, including the antennas, which are listed in Chapter 34.5 of this data sheet, complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 53 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 3 4.1.2 Caution The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Panasonic Industrial Devices Europe GmbH may void the user's authority to operate the equipment. This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • I ncrease the separation between the equipment and receiver. • Con nect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consu lt the dealer or an experienced radio/TV technician for help 34.1.3 Labeling Requirements The Original Equipment Manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Panasonic FCC identifier for this product as well as the FCC Notice above. The FCC identifier are FCC ID: T7V1315. This FCC identifier is valid for all PAN13xx modules, for details, see the Chapter 28. Ordering Information. In any case the end product must be labelled exterior with "Contains FCC ID: T7V1315" 3 4.1.4 Antenna Warning For the related part number of PAN13xx refer to Chapter 28. Ordering Information. This devices are tested with a standard SMA connector and with the antennas listed below. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. The FCC identifier for this device with the antenna listed in item 1 are the same (FCC ID: T7V1315). 3 4.1.5 Approved Antenna List Note: We are able to qualify your antenna and will add to this list as that process is completed. Item Part Number Manufacturer Frequency Band Type Gain (dBi) 1 2450AT43B100 Johanson Technologies 2.4GHz Chip-Antenna +1.3 2 LDA212G3110K Murata 2.4GHz Chip-Antenna +0.9 3 4788930245 Würth Elektronik 2.4GHz Chip-Antenna +0.5 CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 54 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 3 4.1.6 RF Exposure PAN13xx To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure that the approved antenna in the previous table must be installed. The preceding statement must be included as a CAUTION statement in manuals for products operating with the approved antennas in the previous table to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. The radiated output power of PAN13xx with mounted ceramic antenna (FCC ID: T7V1315) is far below the FCC radio frequency exposure limits. Nevertheless, the PAN13xx shall be used in such a manner that the potential for human contact during normal operation is minimized. End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. 34.2 INDUSTRY CANADA CERTIFICATION PAN1315 is licensed to meet the regulatory requirements of Industry Canada (IC), license: IC: 216Q-1315 Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. This device has been designed to operate with the antennas listed in Table 20 above, having a maximum gain of 1.3 dBi. Antennas not included in this list or having a gain greater than 1.3 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. due to the model size the IC identifier is displayed in the installation instruction. 34.3 EUROPEAN R&TTE DECLARATION OF CONFORMITY Hereby, Panasonic Industrial Devices Europe GmbH, declares that the Bluetooth module PAN1315 and their versions is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labelled as follows: PAN13xx and their versions in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 55 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 56 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de 34.4 N CC FOR TAIWAN 34.4.1 Labeling Requirements Due to the limited size on the module, the NCC ID is not visible on the module. When the module is installed inside another device, then the outside of the device into which the module is installed must also display a label referring to the enclosed module. This exterior label can use wording such as the following: “Contains Transmitter Module NCC ID:” or “Contains NCC ID:” CCAJ11LPxxxxTx Any similar wording that expresses the same meaning may be used. Panasonic is able to provide the above content from the label as a vector graphic, please ask at wireless@eu.panasonic.com. 34.4.2 NCC Statement Due to the national rule from Taiwan we have to print the below statement in Chinese language. 􀀒􀀏􀀒􀭋􀉤􀉚􀫢􀀒􀀏􀀔􀭋􀉤􀌬􀫢􀀒􀀏􀀓􀺾􀛨􀏌􁂩􁗇􀎥􀣸􀊘􀐭􀌌􀬟􀢛􁎖􀽥􁋚􀁤􀚢􀺾􀮢􀌙􀁤􀊮􀌡􀁥􀨠􀻮􀗐􀔴􀍜􀙫􀑩􀊔􀩻􁊸􀐆􁜊􀒻􁎖􀬟􀁥􀌋􀉽􀌌􀬟􀗐􁜊􀒻􀡡􀮣􀠇􀊘􀤤􀗌􀊿􀌌􀦐􀁦􀀒􀀏􀀕􀐭􀌌􀬟􀢛􁎖􀽥􁋚􀊘􀔴􀍜􀊔􀩻􁅂􁚤􀠭􀦘􀏄􀎌􀊿􀊍􁓔􀎥􀘬􀮷􀚦􀁩􀺾􀳯􀬤􀏞􀊍􁓔􀬤􀵥􀣛􀁤􁏐􀍭􀑃􀧾􀍜􀁤􀔨􀒷􀴛􀐇􀳌􀊍􁓔􀣛􀋙􀩻􁘱􁚃􀔴􀍜􀁦􀛃􀶰􀎥􀘬􀮷􀚦􀁤􀜸􀔱􀽥􀚦􀘬􀮝􀖛􀐪􀸸􀊘􀳌􁇞􀽥􀮷􀚦􀁦􀐭􀌌􀬟􀢛􁎖􀽥􁋚􀶲􀒜􀕡􀎥􀘬􀮷􀚦􀗐􀊈􀸸􀁥􀟅􁊪􀊿􁔼􁐕􀍜􀽥􀘪􁍧􀢛􀗌􀽥􁋚􀮣􀯪􀊘􀊍􁓔􀁦􀣬􁊽􀀯􀀤􀀤􀐭􀌌􀬟􀽥􀘪􁍧􀢛􀗌􀽥􁋚􁁍􀬣􁍬􀘬􀀁􀮝􀖛􀀛 34.5 BLUETOOTH SIG STATEMENT 35 L IFE SUPPORT POLICY This Panasonic product is not designed for use in life support appliances, devices, or systems where malfunction can reasonably be expected to result in a significant personal injury to the user, or as a critical component in any life support device or system whose failure to perform can be reasonably expected to cause the failure of the CLASSIFICATION PRODUCT SPECIFICATION No. DS-13xx-2400-102 REV. 3.40 SUBJECT CLASS 1 or 2 BLUETOOTH MODULE PAGE 57 of 57 CUSTOMER’S CODE PAN13XX Core Specification PANASONIC’S CODE See Chapter 28. Ordering Information DATE 18.07.2012 PANASONIC INDUSTRIAL DEVICES EUROPE GMBH www.pedeu.pansonic.de life support device or system, or to affect its safety or effectiveness. Panasonic customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Panasonic for any damages resulting. LM3S8933 Microcontroller DATA SHEET DS-LM3S8933-2550 Copyright © 2007-2008 Luminary Micro, Inc. PRELIMINARY Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 ® Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 March 17, 2008 Preliminary Table of Contents About This Document .................................................................................................................... 20 Audience .............................................................................................................................................. 20 About This Manual ................................................................................................................................ 20 Related Documents ............................................................................................................................... 20 Documentation Conventions .................................................................................................................. 20 1 Architectural Overview ...................................................................................................... 22 1.1 Product Features ...................................................................................................................... 22 1.2 Target Applications .................................................................................................................... 27 1.3 High-Level Block Diagram ......................................................................................................... 28 1.4 Functional Overview .................................................................................................................. 28 1.4.1 ARM Cortex™-M3 ..................................................................................................................... 29 1.4.2 Motor Control Peripherals .......................................................................................................... 29 1.4.3 Analog Peripherals .................................................................................................................... 30 1.4.4 Serial Communications Peripherals ............................................................................................ 30 1.4.5 System Peripherals ................................................................................................................... 32 1.4.6 Memory Peripherals .................................................................................................................. 33 1.4.7 Additional Features ................................................................................................................... 33 1.4.8 Hardware Details ...................................................................................................................... 34 2 ARM Cortex-M3 Processor Core ...................................................................................... 35 2.1 Block Diagram .......................................................................................................................... 36 2.2 Functional Description ............................................................................................................... 36 2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 36 2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 37 2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 37 2.2.4 ROM Table ............................................................................................................................... 37 2.2.5 Memory Protection Unit (MPU) ................................................................................................... 37 2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 37 3 Memory Map ....................................................................................................................... 41 4 Interrupts ............................................................................................................................ 43 5 JTAG Interface .................................................................................................................... 46 5.1 Block Diagram .......................................................................................................................... 47 5.2 Functional Description ............................................................................................................... 47 5.2.1 JTAG Interface Pins .................................................................................................................. 48 5.2.2 JTAG TAP Controller ................................................................................................................. 49 5.2.3 Shift Registers .......................................................................................................................... 50 5.2.4 Operational Considerations ........................................................................................................ 50 5.3 Initialization and Configuration ................................................................................................... 53 5.4 Register Descriptions ................................................................................................................ 53 5.4.1 Instruction Register (IR) ............................................................................................................. 53 5.4.2 Data Registers .......................................................................................................................... 55 6 System Control ................................................................................................................... 57 6.1 Functional Description ............................................................................................................... 57 6.1.1 Device Identification .................................................................................................................. 57 6.1.2 Reset Control ............................................................................................................................ 57 March 17, 2008 3 Preliminary LM3S8933 Microcontroller 6.1.3 Power Control ........................................................................................................................... 60 6.1.4 Clock Control ............................................................................................................................ 60 6.1.5 System Control ......................................................................................................................... 62 6.2 Initialization and Configuration ................................................................................................... 63 6.3 Register Map ............................................................................................................................ 64 6.4 Register Descriptions ................................................................................................................ 65 7 Hibernation Module .......................................................................................................... 119 7.1 Block Diagram ........................................................................................................................ 120 7.2 Functional Description ............................................................................................................. 120 7.2.1 Register Access Timing ........................................................................................................... 120 7.2.2 Clock Source .......................................................................................................................... 121 7.2.3 Battery Management ............................................................................................................... 121 7.2.4 Real-Time Clock ...................................................................................................................... 121 7.2.5 Non-Volatile Memory ............................................................................................................... 122 7.2.6 Power Control ......................................................................................................................... 122 7.2.7 Interrupts and Status ............................................................................................................... 122 7.3 Initialization and Configuration ................................................................................................. 123 7.3.1 Initialization ............................................................................................................................. 123 7.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 123 7.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 123 7.3.4 External Wake-Up from Hibernation .......................................................................................... 124 7.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 124 7.4 Register Map .......................................................................................................................... 124 7.5 Register Descriptions .............................................................................................................. 125 8 Internal Memory ............................................................................................................... 138 8.1 Block Diagram ........................................................................................................................ 138 8.2 Functional Description ............................................................................................................. 138 8.2.1 SRAM Memory ........................................................................................................................ 138 8.2.2 Flash Memory ......................................................................................................................... 139 8.3 Flash Memory Initialization and Configuration ........................................................................... 140 8.3.1 Flash Programming ................................................................................................................. 140 8.3.2 Nonvolatile Register Programming ........................................................................................... 141 8.4 Register Map .......................................................................................................................... 141 8.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 142 8.6 Flash Register Descriptions (System Control Offset) .................................................................. 149 9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 162 9.1 Functional Description ............................................................................................................. 162 9.1.1 Data Control ........................................................................................................................... 163 9.1.2 Interrupt Control ...................................................................................................................... 164 9.1.3 Mode Control .......................................................................................................................... 165 9.1.4 Commit Control ....................................................................................................................... 165 9.1.5 Pad Control ............................................................................................................................. 165 9.1.6 Identification ........................................................................................................................... 165 9.2 Initialization and Configuration ................................................................................................. 165 9.3 Register Map .......................................................................................................................... 167 9.4 Register Descriptions .............................................................................................................. 169 4 March 17, 2008 Preliminary Table of Contents 10 General-Purpose Timers ................................................................................................. 204 10.1 Block Diagram ........................................................................................................................ 204 10.2 Functional Description ............................................................................................................. 205 10.2.1 GPTM Reset Conditions .......................................................................................................... 206 10.2.2 32-Bit Timer Operating Modes .................................................................................................. 206 10.2.3 16-Bit Timer Operating Modes .................................................................................................. 207 10.3 Initialization and Configuration ................................................................................................. 211 10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 211 10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 212 10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 212 10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 213 10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 213 10.3.6 16-Bit PWM Mode ................................................................................................................... 214 10.4 Register Map .......................................................................................................................... 214 10.5 Register Descriptions .............................................................................................................. 215 11 Watchdog Timer ............................................................................................................... 240 11.1 Block Diagram ........................................................................................................................ 240 11.2 Functional Description ............................................................................................................. 240 11.3 Initialization and Configuration ................................................................................................. 241 11.4 Register Map .......................................................................................................................... 241 11.5 Register Descriptions .............................................................................................................. 242 12 Analog-to-Digital Converter (ADC) ................................................................................. 263 12.1 Block Diagram ........................................................................................................................ 264 12.2 Functional Description ............................................................................................................. 264 12.2.1 Sample Sequencers ................................................................................................................ 264 12.2.2 Module Control ........................................................................................................................ 265 12.2.3 Hardware Sample Averaging Circuit ......................................................................................... 266 12.2.4 Analog-to-Digital Converter ...................................................................................................... 266 12.2.5 Differential Sampling ............................................................................................................... 266 12.2.6 Test Modes ............................................................................................................................. 268 12.2.7 Internal Temperature Sensor .................................................................................................... 268 12.3 Initialization and Configuration ................................................................................................. 269 12.3.1 Module Initialization ................................................................................................................. 269 12.3.2 Sample Sequencer Configuration ............................................................................................. 269 12.4 Register Map .......................................................................................................................... 269 12.5 Register Descriptions .............................................................................................................. 270 13 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296 13.1 Block Diagram ........................................................................................................................ 297 13.2 Functional Description ............................................................................................................. 297 13.2.1 Transmit/Receive Logic ........................................................................................................... 297 13.2.2 Baud-Rate Generation ............................................................................................................. 298 13.2.3 Data Transmission .................................................................................................................. 299 13.2.4 Serial IR (SIR) ......................................................................................................................... 299 13.2.5 FIFO Operation ....................................................................................................................... 300 13.2.6 Interrupts ................................................................................................................................ 300 13.2.7 Loopback Operation ................................................................................................................ 301 13.2.8 IrDA SIR block ........................................................................................................................ 301 13.3 Initialization and Configuration ................................................................................................. 301 March 17, 2008 5 Preliminary LM3S8933 Microcontroller 13.4 Register Map .......................................................................................................................... 302 13.5 Register Descriptions .............................................................................................................. 303 14 Synchronous Serial Interface (SSI) ................................................................................ 337 14.1 Block Diagram ........................................................................................................................ 337 14.2 Functional Description ............................................................................................................. 337 14.2.1 Bit Rate Generation ................................................................................................................. 338 14.2.2 FIFO Operation ....................................................................................................................... 338 14.2.3 Interrupts ................................................................................................................................ 338 14.2.4 Frame Formats ....................................................................................................................... 339 14.3 Initialization and Configuration ................................................................................................. 346 14.4 Register Map .......................................................................................................................... 347 14.5 Register Descriptions .............................................................................................................. 348 15 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374 15.1 Block Diagram ........................................................................................................................ 374 15.2 Functional Description ............................................................................................................. 374 15.2.1 I2C Bus Functional Overview .................................................................................................... 375 15.2.2 Available Speed Modes ........................................................................................................... 377 15.2.3 Interrupts ................................................................................................................................ 378 15.2.4 Loopback Operation ................................................................................................................ 378 15.2.5 Command Sequence Flow Charts ............................................................................................ 379 15.3 Initialization and Configuration ................................................................................................. 385 15.4 I2C Register Map ..................................................................................................................... 386 15.5 Register Descriptions (I2C Master) ........................................................................................... 387 15.6 Register Descriptions (I2C Slave) ............................................................................................. 400 16 Controller Area Network (CAN) Module ......................................................................... 409 16.1 Controller Area Network Overview ............................................................................................ 409 16.2 Controller Area Network Features ............................................................................................ 409 16.3 Controller Area Network Block Diagram .................................................................................... 410 16.4 Controller Area Network Functional Description ......................................................................... 410 16.4.1 Initialization ............................................................................................................................. 411 16.4.2 Operation ............................................................................................................................... 411 16.4.3 Transmitting Message Objects ................................................................................................. 412 16.4.4 Configuring a Transmit Message Object .................................................................................... 412 16.4.5 Updating a Transmit Message Object ....................................................................................... 413 16.4.6 Accepting Received Message Objects ...................................................................................... 413 16.4.7 Receiving a Data Frame .......................................................................................................... 413 16.4.8 Receiving a Remote Frame ...................................................................................................... 413 16.4.9 Receive/Transmit Priority ......................................................................................................... 414 16.4.10 Configuring a Receive Message Object .................................................................................... 414 16.4.11 Handling of Received Message Objects .................................................................................... 415 16.4.12 Handling of Interrupts .............................................................................................................. 415 16.4.13 Bit Timing Configuration Error Considerations ........................................................................... 416 16.4.14 Bit Time and Bit Rate ............................................................................................................... 416 16.4.15 Calculating the Bit Timing Parameters ...................................................................................... 418 16.5 Controller Area Network Register Map ...................................................................................... 420 16.6 Register Descriptions .............................................................................................................. 421 6 March 17, 2008 Preliminary Table of Contents 17 Ethernet Controller .......................................................................................................... 449 17.1 Block Diagram ........................................................................................................................ 450 17.2 Functional Description ............................................................................................................. 450 17.2.1 Internal MII Operation .............................................................................................................. 450 17.2.2 PHY Configuration/Operation ................................................................................................... 451 17.2.3 MAC Configuration/Operation .................................................................................................. 452 17.2.4 Interrupts ................................................................................................................................ 455 17.3 Initialization and Configuration ................................................................................................. 455 17.4 Ethernet Register Map ............................................................................................................. 456 17.5 Ethernet MAC Register Descriptions ......................................................................................... 457 17.6 MII Management Register Descriptions ..................................................................................... 475 18 Analog Comparators ....................................................................................................... 494 18.1 Block Diagram ........................................................................................................................ 495 18.2 Functional Description ............................................................................................................. 495 18.2.1 Internal Reference Programming .............................................................................................. 497 18.3 Initialization and Configuration ................................................................................................. 498 18.4 Register Map .......................................................................................................................... 498 18.5 Register Descriptions .............................................................................................................. 499 19 Pin Diagram ...................................................................................................................... 507 20 Signal Tables .................................................................................................................... 509 20.1 100-Pin LQFP Package Pin Tables ........................................................................................... 509 20.2 108-Pin BGA Package Pin Tables ............................................................................................ 520 21 Operating Characteristics ............................................................................................... 534 22 Electrical Characteristics ................................................................................................ 535 22.1 DC Characteristics .................................................................................................................. 535 22.1.1 Maximum Ratings ................................................................................................................... 535 22.1.2 Recommended DC Operating Conditions .................................................................................. 535 22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 536 22.1.4 Power Specifications ............................................................................................................... 536 22.1.5 Flash Memory Characteristics .................................................................................................. 538 22.2 AC Characteristics ................................................................................................................... 538 22.2.1 Load Conditions ...................................................................................................................... 538 22.2.2 Clocks .................................................................................................................................... 538 22.2.3 Analog-to-Digital Converter ...................................................................................................... 539 22.2.4 Analog Comparator ................................................................................................................. 540 22.2.5 I2C ......................................................................................................................................... 540 22.2.6 Ethernet Controller .................................................................................................................. 541 22.2.7 Hibernation Module ................................................................................................................. 544 22.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 544 22.2.9 JTAG and Boundary Scan ........................................................................................................ 546 22.2.10 General-Purpose I/O ............................................................................................................... 547 22.2.11 Reset ..................................................................................................................................... 548 23 Package Information ........................................................................................................ 550 A Serial Flash Loader .......................................................................................................... 554 A.1 Serial Flash Loader ................................................................................................................. 554 A.2 Interfaces ............................................................................................................................... 554 March 17, 2008 7 Preliminary LM3S8933 Microcontroller A.2.1 UART ..................................................................................................................................... 554 A.2.2 SSI ......................................................................................................................................... 554 A.3 Packet Handling ...................................................................................................................... 555 A.3.1 Packet Format ........................................................................................................................ 555 A.3.2 Sending Packets ..................................................................................................................... 555 A.3.3 Receiving Packets ................................................................................................................... 555 A.4 Commands ............................................................................................................................. 556 A.4.1 COMMAND_PING (0X20) ........................................................................................................ 556 A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 556 A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 556 A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 557 A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 557 A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 557 B Register Quick Reference ............................................................................................... 559 C Ordering and Contact Information ................................................................................. 578 C.1 Ordering Information ................................................................................................................ 578 C.2 Kits ......................................................................................................................................... 578 C.3 Company Information .............................................................................................................. 579 C.4 Support Information ................................................................................................................. 579 8 March 17, 2008 Preliminary Table of Contents List of Figures Figure 1-1. Stellaris® 8000 Series High-Level Block Diagram ............................................................... 28 Figure 2-1. CPU Block Diagram ......................................................................................................... 36 Figure 2-2. TPIU Block Diagram ........................................................................................................ 37 Figure 5-1. JTAG Module Block Diagram ............................................................................................ 47 Figure 5-2. Test Access Port State Machine ....................................................................................... 50 Figure 5-3. IDCODE Register Format ................................................................................................. 55 Figure 5-4. BYPASS Register Format ................................................................................................ 56 Figure 5-5. Boundary Scan Register Format ....................................................................................... 56 Figure 6-1. External Circuitry to Extend Reset .................................................................................... 58 Figure 6-2. Main Clock Tree .............................................................................................................. 61 Figure 7-1. Hibernation Module Block Diagram ................................................................................. 120 Figure 8-1. Flash Block Diagram ...................................................................................................... 138 Figure 9-1. GPIO Port Block Diagram ............................................................................................... 163 Figure 9-2. GPIODATA Write Example ............................................................................................. 164 Figure 9-3. GPIODATA Read Example ............................................................................................. 164 Figure 10-1. GPTM Module Block Diagram ........................................................................................ 205 Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 209 Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 210 Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 211 Figure 11-1. WDT Module Block Diagram .......................................................................................... 240 Figure 12-1. ADC Module Block Diagram ........................................................................................... 264 Figure 12-2. Differential Sampling Range, Vin(-) = 1.5 V ...................................................................... 267 Figure 12-3. Differential Sampling Range, Vin(-) = 0.75 V .................................................................... 267 Figure 12-4. Differential Sampling Range, Vin(-) = 2.25 V .................................................................... 268 Figure 12-5. Internal Temperature Sensor Characteristic ..................................................................... 268 Figure 13-1. UART Module Block Diagram ......................................................................................... 297 Figure 13-2. UART Character Frame ................................................................................................. 298 Figure 13-3. IrDA Data Modulation ..................................................................................................... 300 Figure 14-1. SSI Module Block Diagram ............................................................................................. 337 Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 340 Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340 Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341 Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341 Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342 Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343 Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343 Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344 Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 345 Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346 Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346 Figure 15-1. I2C Block Diagram ......................................................................................................... 374 Figure 15-2. I2C Bus Configuration .................................................................................................... 375 Figure 15-3. START and STOP Conditions ......................................................................................... 375 Figure 15-4. Complete Data Transfer with a 7-Bit Address ................................................................... 376 Figure 15-5. R/S Bit in First Byte ........................................................................................................ 376 March 17, 2008 9 Preliminary LM3S8933 Microcontroller Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 376 Figure 15-7. Master Single SEND ...................................................................................................... 379 Figure 15-8. Master Single RECEIVE ................................................................................................. 380 Figure 15-9. Master Burst SEND ....................................................................................................... 381 Figure 15-10. Master Burst RECEIVE .................................................................................................. 382 Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 383 Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 384 Figure 15-13. Slave Command Sequence ............................................................................................ 385 Figure 16-1. CAN Module Block Diagram ........................................................................................... 410 Figure 16-2. CAN Bit Time ................................................................................................................ 417 Figure 17-1. Ethernet Controller Block Diagram .................................................................................. 450 Figure 17-2. Ethernet Controller ......................................................................................................... 450 Figure 17-3. Ethernet Frame ............................................................................................................. 452 Figure 18-1. Analog Comparator Module Block Diagram ..................................................................... 495 Figure 18-2. Structure of Comparator Unit .......................................................................................... 496 Figure 18-3. Comparator Internal Reference Structure ........................................................................ 497 Figure 19-1. 100-Pin LQFP Package Pin Diagram .............................................................................. 507 Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ............................................................... 508 Figure 22-1. Load Conditions ............................................................................................................ 538 Figure 22-2. I2C Timing ..................................................................................................................... 541 Figure 22-3. External XTLP Oscillator Characteristics ......................................................................... 543 Figure 22-4. Hibernation Module Timing ............................................................................................. 544 Figure 22-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545 Figure 22-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545 Figure 22-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546 Figure 22-8. JTAG Test Clock Input Timing ......................................................................................... 547 Figure 22-9. JTAG Test Access Port (TAP) Timing .............................................................................. 547 Figure 22-10. JTAG TRST Timing ........................................................................................................ 547 Figure 22-11. External Reset Timing (RST) .......................................................................................... 548 Figure 22-12. Power-On Reset Timing ................................................................................................. 549 Figure 22-13. Brown-Out Reset Timing ................................................................................................ 549 Figure 22-14. Software Reset Timing ................................................................................................... 549 Figure 22-15. Watchdog Reset Timing ................................................................................................. 549 Figure 23-1. 100-Pin LQFP Package .................................................................................................. 550 Figure 23-2. 100-Ball BGA Package .................................................................................................. 552 10 March 17, 2008 Preliminary Table of Contents List of Tables Table 1. Documentation Conventions ............................................................................................ 20 Table 3-1. Memory Map ................................................................................................................... 41 Table 4-1. Exception Types .............................................................................................................. 43 Table 4-2. Interrupts ........................................................................................................................ 44 Table 5-1. JTAG Port Pins Reset State ............................................................................................. 48 Table 5-2. JTAG Instruction Register Commands ............................................................................... 53 Table 6-1. System Control Register Map ........................................................................................... 64 Table 7-1. Hibernation Module Register Map ................................................................................... 124 Table 8-1. Flash Protection Policy Combinations ............................................................................. 140 Table 8-2. Flash Resident Registers ............................................................................................... 141 Table 8-3. Flash Register Map ........................................................................................................ 141 Table 9-1. GPIO Pad Configuration Examples ................................................................................. 166 Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 166 Table 9-3. GPIO Register Map ....................................................................................................... 168 Table 10-1. Available CCP Pins ........................................................................................................ 205 Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 208 Table 10-3. Timers Register Map ...................................................................................................... 214 Table 11-1. Watchdog Timer Register Map ........................................................................................ 241 Table 12-1. Samples and FIFO Depth of Sequencers ........................................................................ 264 Table 12-2. Differential Sampling Pairs ............................................................................................. 266 Table 12-3. ADC Register Map ......................................................................................................... 269 Table 13-1. UART Register Map ....................................................................................................... 302 Table 14-1. SSI Register Map .......................................................................................................... 347 Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 377 Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386 Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391 Table 16-1. Transmit Message Object Bit Settings ............................................................................. 412 Table 16-2. Receive Message Object Bit Settings .............................................................................. 414 Table 16-3. CAN Protocol Ranges .................................................................................................... 417 Table 16-4. CAN Register Map ......................................................................................................... 420 Table 17-1. TX & RX FIFO Organization ........................................................................................... 453 Table 17-2. Ethernet Register Map ................................................................................................... 456 Table 18-1. Comparator 0 Operating Modes ..................................................................................... 496 Table 18-2. Comparator 1 Operating Modes ..................................................................................... 496 Table 18-3. Comparator 2 Operating Modes ...................................................................................... 497 Table 18-4. Internal Reference Voltage and ACREFCTL Field Values ................................................. 497 Table 18-5. Analog Comparators Register Map ................................................................................. 499 Table 20-1. Signals by Pin Number ................................................................................................... 509 Table 20-2. Signals by Signal Name ................................................................................................. 513 Table 20-3. Signals by Function, Except for GPIO ............................................................................. 517 Table 20-4. GPIO Pins and Alternate Functions ................................................................................. 519 Table 20-5. Signals by Pin Number ................................................................................................... 520 Table 20-6. Signals by Signal Name ................................................................................................. 525 Table 20-7. Signals by Function, Except for GPIO ............................................................................. 529 Table 20-8. GPIO Pins and Alternate Functions ................................................................................. 532 Table 21-1. Temperature Characteristics ........................................................................................... 534 March 17, 2008 11 Preliminary LM3S8933 Microcontroller Table 21-2. Thermal Characteristics ................................................................................................. 534 Table 22-1. Maximum Ratings .......................................................................................................... 535 Table 22-2. Recommended DC Operating Conditions ........................................................................ 535 Table 22-3. LDO Regulator Characteristics ....................................................................................... 536 Table 22-4. Detailed Power Specifications ........................................................................................ 537 Table 22-5. Flash Memory Characteristics ........................................................................................ 538 Table 22-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 538 Table 22-7. Clock Characteristics ..................................................................................................... 538 Table 22-8. Crystal Characteristics ................................................................................................... 539 Table 22-9. ADC Characteristics ....................................................................................................... 539 Table 22-10. Analog Comparator Characteristics ................................................................................. 540 Table 22-11. Analog Comparator Voltage Reference Characteristics .................................................... 540 Table 22-12. I2C Characteristics ......................................................................................................... 540 Table 22-13. 100BASE-TX Transmitter Characteristics ........................................................................ 541 Table 22-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 541 Table 22-15. 100BASE-TX Receiver Characteristics ............................................................................ 541 Table 22-16. 10BASE-T Transmitter Characteristics ............................................................................ 541 Table 22-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 542 Table 22-18. 10BASE-T Receiver Characteristics ................................................................................ 542 Table 22-19. Isolation Transformers ................................................................................................... 542 Table 22-20. Ethernet Reference Crystal ............................................................................................ 543 Table 22-21. External XTLP Oscillator Characteristics ......................................................................... 543 Table 22-22. Hibernation Module Characteristics ................................................................................. 544 Table 22-23. SSI Characteristics ........................................................................................................ 544 Table 22-24. JTAG Characteristics ..................................................................................................... 546 Table 22-25. GPIO Characteristics ..................................................................................................... 548 Table 22-26. Reset Characteristics ..................................................................................................... 548 Table C-1. Part Ordering Information ............................................................................................... 578 12 March 17, 2008 Preliminary Table of Contents List of Registers System Control .............................................................................................................................. 57 Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 66 Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 68 Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 69 Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 70 Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 71 Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 72 Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 73 Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 74 Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 78 Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 79 Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 81 Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 82 Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 84 Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 85 Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 87 Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 89 Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 91 Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 93 Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 95 Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 97 Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 99 Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 102 Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 105 Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 108 Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 110 Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 112 Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 114 Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 115 Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 117 Hibernation Module ..................................................................................................................... 119 Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 126 Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 127 Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 128 Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 129 Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 130 Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 132 Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 133 Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 134 Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 135 Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 136 Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 137 Internal Memory ........................................................................................................................... 138 Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 143 Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 144 March 17, 2008 13 Preliminary LM3S8933 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 145 Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 147 Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 148 Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 149 Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 150 Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 151 Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 152 Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 153 Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 154 Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 155 Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 156 Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 157 Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 158 Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 159 Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 160 Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 161 General-Purpose Input/Outputs (GPIOs) ................................................................................... 162 Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170 Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171 Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172 Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173 Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174 Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175 Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176 Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177 Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178 Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179 Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181 Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182 Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183 Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184 Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185 Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186 Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187 Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188 Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189 Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190 Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192 Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193 Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194 Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195 Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196 Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197 Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198 Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199 Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200 Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201 Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202 14 March 17, 2008 Preliminary Table of Contents Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203 General-Purpose Timers ............................................................................................................. 204 Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 216 Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 217 Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 219 Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 221 Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 224 Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 226 Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 227 Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 228 Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 230 Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 231 Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 232 Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 233 Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 234 Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 235 Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 236 Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 237 Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 238 Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 239 Watchdog Timer ........................................................................................................................... 240 Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 243 Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 244 Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 245 Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 246 Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 247 Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 248 Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 249 Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 250 Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 251 Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 252 Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 253 Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 254 Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 255 Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 256 Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 257 Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 258 Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 259 Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 260 Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 261 Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 262 Analog-to-Digital Converter (ADC) ............................................................................................. 263 Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 271 Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 272 Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 273 Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 274 Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 275 Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 276 March 17, 2008 15 Preliminary LM3S8933 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 279 Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 280 Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 281 Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 282 Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 283 Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 285 Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 288 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 288 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 288 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 288 Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 289 Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 289 Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 289 Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 289 Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 290 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 290 Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 291 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 291 Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 293 Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 294 Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 295 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296 Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 304 Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 306 Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 308 Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 310 Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 311 Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 312 Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 313 Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 315 Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 317 Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 319 Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 321 Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 322 Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 323 Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 325 Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 326 Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 327 Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 328 Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 329 Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 330 Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 331 Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 332 Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 333 Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 334 Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 335 Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 336 16 March 17, 2008 Preliminary Table of Contents Synchronous Serial Interface (SSI) ............................................................................................ 337 Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 349 Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 351 Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 353 Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 354 Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 356 Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 357 Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 359 Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 360 Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 361 Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 362 Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 363 Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 364 Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 365 Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 366 Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 367 Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 368 Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 369 Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 370 Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 371 Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 372 Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 373 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374 Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 388 Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 389 Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 393 Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 394 Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 395 Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 396 Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 397 Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 398 Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 399 Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 401 Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 402 Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 404 Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 405 Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 406 Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 407 Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 408 Controller Area Network (CAN) Module ..................................................................................... 409 Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 422 Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 424 Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 427 Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 428 Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 430 Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 431 Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 433 March 17, 2008 17 Preliminary LM3S8933 Microcontroller Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 434 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 434 Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 435 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 435 Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 438 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 438 Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 439 Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 439 Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 440 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 440 Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 441 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 441 Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 442 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 442 Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 444 Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 444 Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 444 Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 444 Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 444 Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 444 Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 444 Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 444 Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 445 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 445 Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 446 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 446 Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 447 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 447 Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 448 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 448 Ethernet Controller ...................................................................................................................... 449 Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 458 Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 460 Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 461 Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 462 Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 463 Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 464 Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 466 Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 467 Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 468 Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 469 Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 470 Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 471 Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 472 Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 473 Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 474 Register 16: Ethernet MAC Timer Support (MACTS), offset 0x03C ...................................................... 475 Register 17: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 476 18 March 17, 2008 Preliminary Table of Contents Register 18: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 478 Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 480 Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 481 Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 ............................................................................................................................. 482 Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 ..................................................................................................... 484 Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 ............................................................................................................................. 485 Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 486 Register 25: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 .............................................................................................................................. 488 Register 26: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 490 Register 27: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 491 Register 28: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 492 Register 29: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 493 Analog Comparators ................................................................................................................... 494 Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 500 Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 501 Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 502 Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 503 Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 504 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 504 Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 504 Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 505 Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 505 Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 505 March 17, 2008 19 Preliminary LM3S8933 Microcontroller About This Document This data sheet provides reference information for the LM3S8933 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ■ ARM® Cortex™-M3 Technical Reference Manual ■ ARM® CoreSight Technical Reference Manual ■ ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 1 on page 20. Table 1. Documentation Conventions Notation Meaning General Register Notation APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. REGISTER bit A single bit in a register. bit field Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 41. offset 0xnnn Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. Register N 20 March 17, 2008 Preliminary About This Document Notation Meaning Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. yy:xx This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Register Bit/Field Types RC Software can read this field. The bit or field is cleared by hardware after reading the bit/field. RO Software can read this field. Always write the chip reset value. R/W Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. R/W1C Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit value in the register. R/W1S Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. W1C WO Only a write by software is valid; a read of the register returns no meaningful data. Register Bit/Field This value in the register bit diagram shows the bit/field value after any reset, unless noted. Reset Value 0 Bit cleared to 0 on chip reset. 1 Bit set to 1 on chip reset. - Nondeterministic. Pin/Signal Notation [ ] Pin alternate function; a pin defaults to the signal without the brackets. pin Refers to the physical connection on the package. signal Refers to the electrical signal encoding of a pin. Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). assert a signal deassert a signal Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. SIGNAL Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. SIGNAL Numbers An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. X Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x March 17, 2008 21 Preliminary LM3S8933 Microcontroller 1 Architectural Overview The Luminary Micro Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris® family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris® LM3S8000 series combines Bosch Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer. The LM3S8933 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S8933 microcontroller features a Battery-backed Hibernation module to efficiently power down the LM3S8933 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S8933 microcontroller perfectly for battery applications. In addition, the LM3S8933 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S8933 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise needs. Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page 578 for ordering information for Stellaris® family devices. 1.1 Product Features The LM3S8933 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication 22 March 17, 2008 Preliminary Architectural Overview – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 32 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ Internal Memory – 256 KB single-cycle flash • User-managed flash block protection on a 2-KB block basis • User-managed flash data programming • User-defined and managed flash-protection block – 64 KB single-cycle SRAM ■ General-Purpose Timers – Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. Each GPTM can be configured to operate independently: • As a single 32-bit timer • As one 32-bit Real-Time Clock (RTC) to event capture • For Pulse Width Modulation (PWM) • To trigger analog-to-digital conversions – 32-bit Timer modes • Programmable one-shot timer • Programmable periodic timer • Real-Time Clock when using an external 32.768-KHz clock as the input • User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug • ADC event trigger – 16-bit Timer modes • General-purpose timer function with an 8-bit prescaler • Programmable one-shot timer March 17, 2008 23 Preliminary LM3S8933 Microcontroller • Programmable periodic timer • User-enabled stalling when the controller asserts CPU Halt flag during debug • ADC event trigger – 16-bit Input Capture modes • Input edge count capture • Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ Controller Area Network (CAN) – Supports CAN protocol version 2.0 part A/B – Bit rates up to 1Mb/s – 32 message objects, each with its own identifier mask – Maskable interrupt – Disable automatic retransmission mode for TTCAN – Programmable loop-back mode for self-test operation ■ 10/100 Ethernet Controller – Conforms to the IEEE 802.3-2002 Specification – Hardware assistance for IEEE 1588-2002 Precision Time Protocol (PTP) – Full- and half-duplex for both 100 Mbps and 10 Mbps operation – Integrated 10/100 Mbps Transceiver (PHY) – Automatic MDI/MDI-X cross-over correction – Programmable MAC address 24 March 17, 2008 Preliminary Architectural Overview – Power-saving and power-down modes ■ Synchronous Serial Interface (SSI) – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ UART – Two fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator allowing speeds up to 3.125 Mbps – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – False-start-bit detection – Line-break generation and detection ■ ADC – Single- and differential-input configurations – Four 10-bit channels (inputs) when used as single-ended inputs – Sample rate of one million samples/second – Flexible, configurable analog-to-digital conversion – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs – Each sequence triggered by software or internal event (timers, analog comparators, or GPIO) – On-chip temperature sensor ■ Analog Comparators – Three independent integrated analog comparators March 17, 2008 25 Preliminary LM3S8933 Microcontroller – Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence – Compare external pin input to external pin input or to internal programmable voltage reference ■ I2C – Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode – Interrupt generation – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ GPIOs – 6-36 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable interrupt generation as either edge-triggered or level-sensitive – Bit masking in both read and write operations through address lines – Can initiate an ADC sample sequence – Programmable control for GPIO pad configuration: • Weak pull-up or pull-down resistors • 2-mA, 4-mA, and 8-mA pad drive • Slew rate control for the 8-mA drive • Open drain enables • Digital input enables ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – User-enabled LDO unregulated voltage detection and automatic reset – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources 26 March 17, 2008 Preliminary Architectural Overview – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Additional Features – Six reset sources – Programmable clock source control – Clock gating to individual peripherals for power savings – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces – Full JTAG boundary scan ■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package ■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation March 17, 2008 27 Preliminary LM3S8933 Microcontroller 1.3 High-Level Block Diagram Figure 1-1 on page 28 represents the full set of features in the Stellaris® 8000 series of devices; not all features may be available on the LM3S8933 microcontroller. Figure 1-1. Stellaris® 8000 Series High-Level Block Diagram 1.4 Functional Overview The following sections provide an overview of the features of the LM3S8933 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 578. 28 March 17, 2008 Preliminary Architectural Overview 1.4.1 ARM Cortex™-M3 1.4.1.1 Processor Core (see page 35) All members of the Stellaris® product family, including the LM3S8933 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. “ARM Cortex-M3 Processor Core” on page 35 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.1.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 Nested Vectored Interrupt Controller (NVIC) The LM3S8933 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 32 interrupts. “Interrupts” on page 43 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S8933 controller features Pulse Width Modulation (PWM) outputs. 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. March 17, 2008 29 Preliminary LM3S8933 Microcontroller On the LM3S8933, PWM motion control functionality can be achieved through: ■ The motion control features of the general-purpose timers using the CCP pins CCP Pins (see page 210) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 Analog Peripherals To handle analog signals, the LM3S8933 microcontroller offers an Analog-to-Digital Converter (ADC). For support of analog signals, the LM3S8933 microcontroller offers three analog comparators. 1.4.3.1 ADC (see page 263) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The LM3S8933 ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 1.4.3.2 Analog Comparators (see page 494) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S8933 microcontroller provides three independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 1.4.4 Serial Communications Peripherals The LM3S8933 controller supports both asynchronous and synchronous serial communications with: ■ Two fully programmable 16C550-type UARTs ■ One SSI module ■ One I2C module 30 March 17, 2008 Preliminary Architectural Overview ■ One CAN unit ■ Ethernet controller 1.4.4.1 UART (see page 296) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S8933 controller includes two fully programmable 16C550-type UARTs that support data transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 337) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The LM3S8933 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 374) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S8933 controller includes one I2C module that provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris® I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). March 17, 2008 31 Preliminary LM3S8933 Microcontroller Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.4.4 Controller Area Network (see page 409) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, now it is used in many embedded control applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The LM3S8933 includes one CAN units. 1.4.4.5 Ethernet Controller (see page 449) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. 1.4.5 System Peripherals 1.4.5.1 Programmable GPIOs (see page 162) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris® GPIO module is comprised of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 6-36 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 509 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 Four Programmable Timers (see page 204) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can 32 March 17, 2008 Preliminary Architectural Overview extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.3 Watchdog Timer (see page 240) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 Memory Peripherals The LM3S8933 controller offers both single-cycle SRAM and single-cycle Flash memory. 1.4.6.1 SRAM (see page 138) The LM3S8933 static random access memory (SRAM) controller supports 64 KB SRAM. The internal SRAM of the Stellaris® devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 139) The LM3S8933 Flash controller supports 256 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 Additional Features 1.4.7.1 Memory Map (see page 41) A memory map lists the location of instructions and data in memory. The memory map for the LM3S8933 controller can be found in “Memory Map” on page 41. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (see page 46) The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing March 17, 2008 33 Preliminary LM3S8933 Microcontroller information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (see page 57) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.7.4 Hibernation Module (see page 119) The Hibernation module provides logic to switch power off to the main processor and peripherals, and to wake on external or time-based events. The Hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 507 ■ “Signal Tables” on page 509 ■ “Operating Characteristics” on page 534 ■ “Electrical Characteristics” on page 535 ■ “Package Information” on page 550 34 March 17, 2008 Preliminary Architectural Overview 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution with a: – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer ■ Optimized for single-cycle flash usage ■ Three sleep modes with clock gating for low power ■ Single-cycle multiply instruction and hardware divide ■ Atomic operations ■ ARM Thumb2 mixed 16-/32-bit instruction set ■ 1.25 DMIPS/MHz The Stellaris® family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. March 17, 2008 35 Preliminary LM3S8933 Microcontroller For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual. 2.1 Block Diagram Figure 2-1. CPU Block Diagram Private Peripheral Bus (internal) Data Watchpoint and Trace Interrupts Debug Sleep Instrumentation Trace Macrocell Trace Port Interface Unit CM3 Core Instructions Data Flash Patch and Breakpoint Memory Protection Unit Adv. High- Perf. Bus Access Port Nested Vectored Interrupt Controller Serial Wire JTAG Debug Port Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus ROM Table Private Peripheral Bus (external) Serial Wire Output Trace Port (SWO) ARM Cortex-M3 2.2 Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. This section describes the Stellaris® implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 36. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow. 2.2.1 Serial Wire and JTAG Debug Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris® devices. 36 March 17, 2008 Preliminary ARM Cortex-M3 Processor Core The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. 2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris® devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace Port Analyzer. The Stellaris® devices have implemented TPIU as shown in Figure 2-2 on page 37. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram ATB Interface Asynchronous FIFO APB Interface Trace Out (serializer) Debug ATB Slave Port APB Slave Port Serial Wire Trace Port (SWO) 2.2.4 ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S8933 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling March 17, 2008 37 Preliminary LM3S8933 Microcontroller ■ Controls power management ■ Implements system control registers The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault. All NVIC registers are accessible using byte, halfword, and word unless otherwise stated. 2.2.6.1 Interrupts The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S8933 microcontroller supports 32 interrupts with eight priority levels. 2.2.6.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. Functional Description The timer consists of three registers: ■ A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ The reload value for the counter, used to provide the counter's wrap value. ■ The current value of the counter. A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris® devices. When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks. Writing a value of zero to the Reload Value register disables the counter on the next wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. 38 March 17, 2008 Preliminary ARM Cortex-M3 Processor Core Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:17 reserved RO 0 Count Flag Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 16 COUNTFLAG R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:3 reserved RO 0 Clock Source Value Description 0 External reference clock. (Not implemented for Stellaris microcontrollers.) 1 Core clock If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 2 CLKSOURCE R/W 0 Tick Int Value Description Counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0. 0 1 Counting down to 0 pends the SysTick handler. 1 TICKINT R/W 0 Enable Value Description 0 Counter disabled. Counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 1 0 ENABLE R/W 0 SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value March 17, 2008 39 Preliminary LM3S8933 Microcontroller of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0 Reload Value to load into the SysTick Current Value Register when the counter reaches 0. 23:0 RELOAD W1C - SysTick Current Value Register Use the SysTick Current Value Register to find the current value in the register. Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:24 reserved RO 0 Current Value Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 23:0 CURRENT W1C - SysTick Calibration Value Register The SysTick Calibration Value register is not implemented. 40 March 17, 2008 Preliminary ARM Cortex-M3 Processor Core 3 Memory Map The memory map for the LM3S8933 controller is provided in Table 3-1 on page 41. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. Important: In Table 3-1 on page 41, addresses not listed are reserved. Table 3-1. Memory Mapa For details on registers, see page ... Start End Description Memory 0x0000.0000 0x0003.FFFF On-chip flash b 142 0x0004.0000 0x00FF.FFFF Reserved - 0x0100.0000 0x1FFF.FFFF Reserved - 0x2000.0000 0x2000.FFFF Bit-banded on-chip SRAMc 142 0x2001.0000 0x200F.FFFF Reserved - 0x2010.0000 0x21FF.FFFF Reserved - 0x2200.0000 0x221F.FFFF Bit-band alias of 0x2000.0000 through 0x200F.FFFF 138 0x2220.0000 0x3FFF.FFFF Reserved - FiRM Peripherals 0x4000.0000 0x4000.0FFF Watchdog timer 242 0x4000.1000 0x4000.3FFF Reserved - 0x4000.4000 0x4000.4FFF GPIO Port A 169 0x4000.5000 0x4000.5FFF GPIO Port B 169 0x4000.6000 0x4000.6FFF GPIO Port C 169 0x4000.7000 0x4000.7FFF GPIO Port D 169 0x4000.8000 0x4000.8FFF SSI0 348 0x4000.A000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 303 0x4000.D000 0x4000.DFFF UART1 303 0x4000.F000 0x4000.FFFF Reserved - 0x4001.0000 0x4001.FFFF Reserved - Peripherals 0x4002.0000 0x4002.07FF I2C Master 0 387 0x4002.0800 0x4002.0FFF I2C Slave 0 400 0x4002.2000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 169 0x4002.5000 0x4002.5FFF GPIO Port F 169 0x4002.6000 0x4002.6FFF GPIO Port G 169 0x4002.9000 0x4002.BFFF Reserved - 0x4002.E000 0x4002.FFFF Reserved - March 17, 2008 41 Preliminary LM3S8933 Microcontroller For details on registers, see page ... Start End Description 0x4003.0000 0x4003.0FFF Timer0 215 0x4003.1000 0x4003.1FFF Timer1 215 0x4003.2000 0x4003.2FFF Timer2 215 0x4003.3000 0x4003.3FFF Timer3 215 0x4003.4000 0x4003.7FFF Reserved - 0x4003.8000 0x4003.8FFF ADC 270 0x4003.9000 0x4003.BFFF Reserved - 0x4003.C000 0x4003.CFFF Analog Comparators 494 0x4003.D000 0x4003.FFFF Reserved - 0x4004.0000 0x4004.0FFF CAN0 Controller 421 0x4004.3000 0x4004.7FFF Reserved - 0x4004.8000 0x4004.8FFF Ethernet Controller 457 0x4004.9000 0x4004.BFFF Reserved - 0x4004.C000 0x4004.FFFF Reserved - 0x4005.1000 0x4005.3FFF Reserved - 0x4005.4000 0x4005.7FFF Reserved - 0x4006.0000 0x400F.BFFF Reserved - 0x400F.C000 0x400F.CFFF Hibernation Module 125 0x400F.D000 0x400F.DFFF Flash control 142 0x400F.E000 0x400F.EFFF System control 65 0x4010.0000 0x41FF.FFFF Reserved - 0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF - 0x4400.0000 0x5FFF.FFFF Reserved - 0x6000.0000 0xDFFF.FFFF Reserved - Private Peripheral Bus ARM® Cortex™-M3 Technical Reference Manual 0xE000.0000 0xE000.0FFF Instrumentation Trace Macrocell (ITM) 0xE000.1000 0xE000.1FFF Data Watchpoint and Trace (DWT) 0xE000.2000 0xE000.2FFF Flash Patch and Breakpoint (FPB) 0xE000.3000 0xE000.DFFF Reserved 0xE000.E000 0xE000.EFFF Nested Vectored Interrupt Controller (NVIC) 0xE000.F000 0xE003.FFFF Reserved 0xE004.0000 0xE004.0FFF Trace Port Interface Unit (TPIU) 0xE004.1000 0xFFFF.FFFF Reserved - a. All reserved space returns a bus fault when read or written. b. The unavailable flash will bus fault throughout this range. c. The unavailable SRAM will bus fault throughout this range. 42 March 17, 2008 Preliminary Memory Map 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 on page 43 lists all exception types. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 32 interrupts (listed in Table 4-2 on page 44). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You also can group priorities by splitting priority levels into pre-emption priorities and subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts. Note: In Table 4-2 on page 44 interrupts not listed are reserved. Table 4-1. Exception Types Exception Type Position Prioritya Description - 0 - Stack top is loaded from first entry of vector table on reset. Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. Reset 1 -3 (highest) Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Non-Maskable 2 -2 Interrupt (NMI) All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. Hard Fault 3 -1 MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. Memory Management 4 settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Bus Fault 5 settable Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Usage Fault 6 settable - 7-10 - Reserved. SVCall 11 settable System service call with SVC instruction. This is synchronous. March 17, 2008 43 Preliminary LM3S8933 Microcontroller Exception Type Position Prioritya Description Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Debug Monitor 12 settable - 13 - Reserved. Pendable request for system service. This is asynchronous and only pended by software. PendSV 14 settable SysTick 15 settable System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 on page 44 lists the interrupts on the LM3S8933 controller. 16 and settable above Interrupts a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Interrupt (Bit in Interrupt Registers) Description 0 GPIO Port A 1 GPIO Port B 2 GPIO Port C 3 GPIO Port D 4 GPIO Port E 5 UART0 6 UART1 7 SSI0 8 I2C0 14 ADC Sequence 0 15 ADC Sequence 1 16 ADC Sequence 2 17 ADC Sequence 3 18 Watchdog timer 19 Timer0 A 20 Timer0 B 21 Timer1 A 22 Timer1 B 23 Timer2 A 24 Timer2 B 25 Analog Comparator 0 26 Analog Comparator 1 27 Analog Comparator 2 28 System Control 29 Flash Control 30 GPIO Port F 31 GPIO Port G 35 Timer3 A 36 Timer3 B 39 CAN0 44 March 17, 2008 Preliminary Interrupts Interrupt (Bit in Interrupt Registers) Description 42 Ethernet Controller 43 Hibernation Module March 17, 2008 45 Preliminary LM3S8933 Microcontroller 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. The JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: – BYPASS instruction – IDCODE instruction – SAMPLE/PRELOAD instruction – EXTEST instruction – INTEST instruction ■ ARM additional instructions: – APACC instruction – DPACC instruction – ABORT instruction ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. 46 March 17, 2008 Preliminary JTAG Interface 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram Instruction Register (IR) TAP Controller BYPASS Data Register Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TCK TMS TDI TDO Cortex-M3 Debug Port TRST 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 47. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 53 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 546 for JTAG timing diagrams. March 17, 2008 47 Preliminary LM3S8933 Microcontroller 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST,TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1 on page 48. Detailed information on each pin follows. Table 5-1. JTAG Port Pins Reset State Pin Name Data Direction Internal Pull-Up Internal Pull-Down Drive Strength Drive Value TRST Input Enabled Disabled N/A N/A TCK Input Enabled Disabled N/A N/A TMS Input Enabled Disabled N/A N/A TDI Input Enabled Disabled N/A N/A TDO Output Enabled Disabled 2-mA driver High-Z 5.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 50. 48 March 17, 2008 Preliminary JTAG Interface By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 50. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. March 17, 2008 49 Preliminary LM3S8933 Microcontroller Figure 5-2. Test Access Port State Machine Test Logic Reset Run Test Idle Select DR Scan Select IR Scan Capture DR Capture IR Shift DR Shift IR Exit 1 DR Exit 1 IR Exit 2 DR Exit 2 IR Pause DR Pause IR Update DR Update IR 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 53. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 50 March 17, 2008 Preliminary JTAG Interface 5.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. Recovering a "Locked" Device If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 11. Perform the SWD-to-JTAG switch sequence. March 17, 2008 51 Preliminary LM3S8933 Microcontroller 12. Release the RST signal. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 52. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 52 March 17, 2008 Preliminary JTAG Interface 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 5.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 5.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 53. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. JTAG Instruction Register Commands IR[3:0] Instruction Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. 0001 INTEST Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. 0010 SAMPLE / PRELOAD 1000 ABORT Shifts data into the ARM Debug Port Abort Register. 1010 DPACC Shifts data into and out of the ARM DP Access Register. 1011 APACC Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. 1110 IDCODE 1111 BYPASS Connects TDI to TDO through a single Shift Register chain. All Others Reserved Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. 5.4.1.1 EXTEST Instruction The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows March 17, 2008 53 Preliminary LM3S8933 Microcontroller tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.4.1.2 INTEST Instruction The INTEST instruction does not have an associated Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 56 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 56 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 56 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 56 for more information. 54 March 17, 2008 Preliminary JTAG Interface 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 55 for more information. 5.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 55 for more information. 5.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 5.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3 on page 55. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. IDCODE Register Format Version Part Number Manufacturer ID 1 31 28 27 12 11 1 0 TDI TDO 5.4.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4 on page 56. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. March 17, 2008 55 Preliminary LM3S8933 Microcontroller Figure 5-4. BYPASS Register Format TDI 0 TDO 0 5.4.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 56. Each GPIO pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the Data Register chain. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. Boundary Scan Register Format O TDO TDI O IN E UT O O IN U E T O O IN E UT O O IN U E T I N ... ... GPIO PB6 GPIO m RST GPIO m+1 GPIO n For detailed information on the order of the input, output, and output enable bits for each of the GPIO ports, please refer to the Stellaris® Family Boundary Scan Description Language (BSDL) files, downloadable from www.luminarymicro.com. 5.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 56 March 17, 2008 Preliminary JTAG Interface 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 57 ■ Local control, such as reset (see “Reset Control” on page 57), power (see “Power Control” on page 60) and clock control (see “Clock Control” on page 60) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 62 6.1.1 Device Identification Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 6.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 57. 2. Power-on reset (POR), see “Power-On Reset (POR)” on page 58. 3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 58. 4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 59. 5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 59. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 6.1.2.3 RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see “JTAG Interface” on page 46). The external reset sequence is as follows: March 17, 2008 57 Preliminary LM3S8933 Microcontroller 1. The external reset pin (RST) is asserted and then de-asserted. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for synchronization. The external reset timing is shown in Figure 22-11 on page 548. 6.1.2.4 Power-On Reset (POR) The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit generates a reset signal to the internal logic when the power supply ramp reaches a threshold value (VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power supply (VDD) through a pull-up resistor (1K to 10K Ω). The device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within 10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset to hold the device in reset longer than the internal POR, the RST input may be used with the circuit as shown in Figure 6-1 on page 58. Figure 6-1. External Circuitry to Extend Reset R1 C1 R2 RST Stellaris D1 The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 22-12 on page 549. Note: The power-on reset also resets the JTAG controller. An external reset does not. 6.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. 58 March 17, 2008 Preliminary System Control Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivelent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 22-13 on page 549. 6.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 62). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 22-14 on page 549. 6.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. March 17, 2008 59 Preliminary LM3S8933 Microcontroller The watchdog reset timing is shown in Figure 22-15 on page 549. 6.1.3 Power Control The Stellaris® microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. The LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25 pins on the printed circuit board. The LDO requires decoupling capacitors on the printed circuit board. If an external regulator is used, it is strongly recommended that the external regulator supply the controller only and not be shared with other devices on the printed circuit board. 6.1.4 Clock Control System control determines the control of clocks in this part. 6.1.4.1 Fundamental Clock Sources There are four clock sources for use in the device: ■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator (MOSC): The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed depends on whether the main oscillator is used as the clock reference source to the PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit field in the RCC register (see page 74). ■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. ■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency, accurate clock reference. It is intended to provide the system with a real-time clock source. The real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 119) and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (SysClk), is derived from any of the four sources plus two others: the output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). 60 March 17, 2008 Preliminary System Control The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. Figure 6-2 on page 61 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be programmatically enabled/disabled. The ADC clock signal is automatically divided down to 16 MHz for proper ADC operation. Figure 6-2. Main Clock Tree PLL (240 MHz) ÷ 4 PLL Main OSC (400 MHz) Internal OSC (12 MHz) Internal OSC (30 kHz) ÷ 4 Hibernation Module (32.768 kHz) ÷ 25 PWRDN ADC Clock System Clock USB Clock XTALa USBPWRDNc XTALa PWRDN b MOSCDIS a IOSCDISa OSCSRCb,d BYPASS b,d SYSDIVb,d USESYSDIV a,d PWMDW a USEPWMDIVa PWM Clock a. Control provided by RCC register bit/field. b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2. c. Control provided by RCC2 register bit/field. d. Also may be controlled by DSLPCLKCFG when in deep sleep mode. 6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 74) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. March 17, 2008 61 Preliminary LM3S8933 Microcontroller 6.1.4.3 Main PLL Frequency Configuration The main PLL is disabled by default during power-on reset and is enabled later by software if required. Software configures the main PLL input reference clock source, specifies the output divisor to set the system clock frequency, and enables the main PLL to drive the output. If the main oscillator provides the clock reference to the main PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 78). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. The Crystal Value field (XTAL) on page 74 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 6.1.4.4 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 74 and page 79). 6.1.4.5 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 22-6 on page 538). During the relock time, the affected PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system control hardware continues to clock the controller from the source to the PLL until the main PLL is stable (TREADY time met), after which it changes to the PLL. Software can use many methods to ensure that the system is clocked from the main PLL, including periodically polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock interrupt. 6.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. 62 March 17, 2008 Preliminary System Control In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor is not clocked and therefore no longer executes code. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Each mode is described in more detail below. There are four levels of operation for the device defined as: ■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. ■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside of the Hibernation module see a normal "power on" sequence and the processor starts running code. It can determine that it has been restarted from Hibernate mode by inspecting the Hibernation module registers. 6.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: March 17, 2008 63 Preliminary LM3S8933 Microcontroller 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source (using the main oscillator or internal oscillator) and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 6.3 Register Map Table 6-1 on page 64 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register’s address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use by Luminary Micro, Inc. Software should not modify any reserved memory address. Table 6-1. System Control Register Map See Offset Name Type Reset Description page 0x000 DID0 RO - Device Identification 0 66 0x004 DID1 RO - Device Identification 1 82 0x008 DC0 RO 0x00FF.007F Device Capabilities 0 84 0x010 DC1 RO 0x0101.33FF Device Capabilities 1 85 0x014 DC2 RO 0x070F.1013 Device Capabilities 2 87 0x018 DC3 RO 0x0F0F.3FC0 Device Capabilities 3 89 0x01C DC4 RO 0x5100.007F Device Capabilities 4 91 0x030 PBORCTL R/W 0x0000.7FFD Brown-Out Reset Control 68 0x034 LDOPCTL R/W 0x0000.0000 LDO Power Control 69 0x040 SRCR0 R/W 0x00000000 Software Reset Control 0 114 0x044 SRCR1 R/W 0x00000000 Software Reset Control 1 115 0x048 SRCR2 R/W 0x00000000 Software Reset Control 2 117 0x050 RIS RO 0x0000.0000 Raw Interrupt Status 70 0x054 IMC R/W 0x0000.0000 Interrupt Mask Control 71 0x058 MISC R/W1C 0x0000.0000 Masked Interrupt Status and Clear 72 0x05C RESC R/W - Reset Cause 73 64 March 17, 2008 Preliminary System Control See Offset Name Type Reset Description page 0x060 RCC R/W 0x0780.3AD1 Run-Mode Clock Configuration 74 0x064 PLLCFG RO - XTAL to PLL Translation 78 0x070 RCC2 R/W 0x0780.2800 Run-Mode Clock Configuration 2 79 0x100 RCGC0 R/W 0x00000040 Run Mode Clock Gating Control Register 0 93 0x104 RCGC1 R/W 0x00000000 Run Mode Clock Gating Control Register 1 99 0x108 RCGC2 R/W 0x00000000 Run Mode Clock Gating Control Register 2 108 0x110 SCGC0 R/W 0x00000040 Sleep Mode Clock Gating Control Register 0 95 0x114 SCGC1 R/W 0x00000000 Sleep Mode Clock Gating Control Register 1 102 0x118 SCGC2 R/W 0x00000000 Sleep Mode Clock Gating Control Register 2 110 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 97 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 105 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 112 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 81 6.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. March 17, 2008 65 Preliminary LM3S8933 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved VER reserved CLASS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJOR MINOR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 Second version of the DID0 register format. 30:28 VER RO 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:24 reserved RO 0x0 Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x1 Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 66 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 Revision A (initial device) 0x1 Revision B (first base layer revision) 0x2 Revision C (second base layer revision) and so on. 15:8 MAJOR RO - Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 Initial device, or a major revision update. 0x1 First metal layer change. 0x2 Second metal layer change. and so on. 7:0 MINOR RO - March 17, 2008 67 Preliminary LM3S8933 Microcontroller Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved BORIOR reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 1 BORIOR R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 68 March 17, 2008 Preliminary System Control Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VADJ Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value VOUT (V) 0x00 2.50 0x01 2.45 0x02 2.40 0x03 2.35 0x04 2.30 0x05 2.25 0x06-0x3F Reserved 0x1B 2.75 0x1C 2.70 0x1D 2.65 0x1E 2.60 0x1F 2.55 5:0 VADJ R/W 0x0 March 17, 2008 69 Preliminary LM3S8933 Microcontroller Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLRIS reserved BORRIS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 6 PLLLRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 1 BORRIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 70 March 17, 2008 Preliminary System Control Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLIM reserved BORIM reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO RO RO R/W RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 1 BORIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 March 17, 2008 71 Preliminary LM3S8933 Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 70). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PLLLMIS reserved BORMIS reserved Type RO RO RO RO RO RO RO RO RO R/W1C RO RO RO RO R/W1C RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:7 reserved RO 0 PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:2 reserved RO 0 BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 1 BORMIS R/W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 reserved RO 0 72 March 17, 2008 Preliminary System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LDO SW WDT BOR POR EXT Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0 LDO Reset When set, indicates the LDO circuit has lost regulation and has generated a reset event. 5 LDO R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 4 SW R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 3 WDT R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 2 BOR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 1 POR R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. 0 EXT R/W - March 17, 2008 73 Preliminary LM3S8933 Microcontroller Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x0780.3AD1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ACG SYSDIV USESYSDIV reserved Type RO RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN reserved BYPASS reserved XTAL OSCSRC reserved IOSCDIS MOSCDIS Type RO RO R/W RO R/W RO R/W R/W R/W R/W R/W R/W RO RO R/W R/W Reset 0 0 1 1 1 0 1 0 1 1 0 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0x0 Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 27 ACG R/W 0 74 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. Value Divisor (BYPASS=1) Frequency (BYPASS=0) 0x0 reserved reserved 0x1 /2 reserved 0x2 /3 reserved 0x3 /4 50 MHz 0x4 /5 40 MHz 0x5 /6 33.33 MHz 0x6 /7 28.57 MHz 0x7 /8 25 MHz 0x8 /9 22.22 MHz 0x9 /10 20 MHz 0xA /11 18.18 MHz 0xB /12 16.67 MHz 0xC /13 15.38 MHz 0xD /14 14.29 MHz 0xE /15 13.33 MHz 0xF /16 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 74), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 26:23 SYSDIV R/W 0xF Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. 22 USESYSDIV R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 21:14 reserved RO 0 PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 13 PWRDN R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 1 March 17, 2008 75 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. Note: The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. While the ADC works in a 14-18 MHz range, to maintain a 1 M sample/second rate, the ADC must be provided a 16-MHz clock source. 11 BYPASS R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10 reserved RO 0 Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Crystal Frequency (MHz) Using the PLL Crystal Frequency (MHz) Not Using the PLL Value 0x0 1.000 reserved 0x1 1.8432 reserved 0x2 2.000 reserved 0x3 2.4576 reserved 0x4 3.579545 MHz 0x5 3.6864 MHz 0x6 4 MHz 0x7 4.096 MHz 0x8 4.9152 MHz 0x9 5 MHz 0xA 5.12 MHz 0xB 6 MHz (reset value) 0xC 6.144 MHz 0xD 7.3728 MHz 0xE 8 MHz 0xF 8.192 MHz 9:6 XTAL R/W 0xB Oscillator Source Picks among the four input sources for the OSC. The values are: Value Input Source 0x0 Main oscillator 0x1 Internal oscillator (default) 0x2 Internal oscillator / 4 (this is necessary if used as input to PLL) 0x3 reserved 5:4 OSCSRC R/W 0x1 76 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default). 0 MOSCDIS R/W 1 March 17, 2008 77 Preliminary LM3S8933 Microcontroller Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 74). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved F R Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x0 PLL F Value This field specifies the value supplied to the PLL’s F input. 13:5 F RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 4:0 R RO - 78 March 17, 2008 Preliminary System Control Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified. The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system clock frequency for improved Deep Sleep power consumption. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 USERCC2 reserved SYSDIV2 reserved Type R/W RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PWRDN2 reserved BYPASS2 reserved OSCSRC2 reserved Type RO RO R/W RO R/W RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Use RCC2 When set, overrides the RCC register fields. 31 USERCC2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 30:29 reserved RO 0x0 System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. This field is wider than the RCC register SYSDIV field in order to provide additional divisor values. This permits the system clock to be run at much lower frequencies during Deep Sleep mode. For example, where the RCC register SYSDIV encoding of 1111 provides /16, the RCC2 register SYSDIV2 encoding of 111111 provides /64. 28:23 SYSDIV2 R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:14 reserved RO 0x0 Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 Bypass PLL When set, bypasses the PLL for the clock source. 11 BYPASS2 R/W 1 March 17, 2008 79 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 10:7 reserved RO 0x0 System Clock Source Value Description 0x0 Main oscillator (MOSC) 0x1 Internal oscillator (IOSC) 0x2 Internal oscillator / 4 0x3 30 kHz internal oscillator 0x7 32 kHz external oscillator 6:4 OSCSRC2 R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0 80 March 17, 2008 Preliminary System Control Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved DSDIVORIDE reserved Type RO RO RO R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DSOSCSRC reserved Type RO RO RO RO RO RO RO RO RO R/W R/W R/W RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:29 reserved RO 0x0 Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 28:23 DSDIVORIDE R/W 0x0F Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 22:7 reserved RO 0x0 Clock Source When set, forces IOSC to be clock source during Deep Sleep mode. Value Name Description 0x0 NOORIDE No override to the oscillator clock source is done 0x1 IOSC Use internal 12 MHz oscillator as source 0x3 30kHz Use 30 kHz internal oscillator 0x7 32kHz Use 32 kHz external oscillator 6:4 DSOSCSRC R/W 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:0 reserved RO 0x0 March 17, 2008 81 Preliminary LM3S8933 Microcontroller Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VER FAM PARTNO Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PINCOUNT reserved TEMP PKG ROHS QUAL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 0 0 0 0 0 - - - - - 1 - - Bit/Field Name Type Reset Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 Second version of the DID1 register format. 31:28 VER RO 0x1 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 0x0 27:24 FAM RO 0x0 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x8C LM3S8933 23:16 PARTNO RO 0x8C Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin or 108-ball package 15:13 PINCOUNT RO 0x2 82 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12:8 reserved RO 0 Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Commercial temperature range (0°C to 70°C) 0x1 Industrial temperature range (-40°C to 85°C) 0x2 Extended temperature range (-40°C to 105°C) 7:5 TEMP RO - Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 SOIC package 0x1 LQFP package 0x2 BGA package 4:3 PKG RO - RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 2 ROHS RO 1 Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Engineering Sample (unqualified) 0x1 Pilot Production (unqualified) 0x2 Fully Qualified 1:0 QUAL RO - March 17, 2008 83 Preliminary LM3S8933 Microcontroller Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLASHSZ Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 31:16 SRAMSZ RO 0x00FF Flash Size Indicates the size of the on-chip flash memory. Value Description 0x007F 256 KB of Flash 15:0 FLASHSZ RO 0x007F 84 March 17, 2008 Preliminary System Control Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0101.33FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN0 reserved ADC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MINSYSDIV MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD JTAG Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:25 reserved RO 0 CAN Module 0 Present When set, indicates that CAN unit 0 is present. 24 CAN0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:17 reserved RO 0 ADC Module Present When set, indicates that the ADC module is present. 16 ADC RO 1 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 15:12 MINSYSDIV RO 0x3 Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x3 1M samples/second 11:8 MAXADCSPD RO 0x3 March 17, 2008 85 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 7 MPU RO 1 Hibernation Module Present When set, indicates that the Hibernation module is present. 6 HIB RO 1 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 5 TEMPSNS RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 4 PLL RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 3 WDT RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 2 SWO RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 1 SWD RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 0 JTAG RO 1 86 March 17, 2008 Preliminary System Control Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x070F.1013 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved SSI0 reserved UART1 UART0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Present When set, indicates that analog comparator 2 is present. 26 COMP2 RO 1 Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 25 COMP1 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 24 COMP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 Timer 3 Present When set, indicates that General-Purpose Timer module 3 is present. 19 TIMER3 RO 1 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 18 TIMER2 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 17 TIMER1 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 16 TIMER0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 March 17, 2008 87 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description I2C Module 0 Present When set, indicates that I2C module 0 is present. 12 I2C0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:5 reserved RO 0 SSI0 Present When set, indicates that SSI module 0 is present. 4 SSI0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 UART1 Present When set, indicates that UART module 1 is present. 1 UART1 RO 1 UART0 Present When set, indicates that UART module 0 is present. 0 UART0 RO 1 88 March 17, 2008 Preliminary System Control Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x0F0F.3FC0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CCP3 CCP2 CCP1 CCP0 reserved ADC3 ADC2 ADC1 ADC0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved C2PLUS C2MINUS C1O C1PLUS C1MINUS C0O C0PLUS C0MINUS reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:28 reserved RO 0 CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 27 CCP3 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 26 CCP2 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 25 CCP1 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 24 CCP0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 ADC3 Pin Present When set, indicates that ADC pin 3 is present. 19 ADC3 RO 1 ADC2 Pin Present When set, indicates that ADC pin 2 is present. 18 ADC2 RO 1 ADC1 Pin Present When set, indicates that ADC pin 1 is present. 17 ADC1 RO 1 ADC0 Pin Present When set, indicates that ADC pin 0 is present. 16 ADC0 RO 1 March 17, 2008 89 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:14 reserved RO 0 C2+ Pin Present When set, indicates that the analog comparator 2 (+) input pin is present. 13 C2PLUS RO 1 C2- Pin Present When set, indicates that the analog comparator 2 (-) input pin is present. 12 C2MINUS RO 1 C1o Pin Present When set, indicates that the analog comparator 1 output pin is present. 11 C1O RO 1 C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 10 C1PLUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 9 C1MINUS RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 8 C0O RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 7 C0PLUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 6 C0MINUS RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:0 reserved RO 0 90 March 17, 2008 Preliminary System Control Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5100.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved E1588 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 Ethernet PHY0 Present When set, indicates that Ethernet PHY module 0 is present. 30 EPHY0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 Ethernet MAC0 Present When set, indicates that Ethernet MAC module 0 is present. 28 EMAC0 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:25 reserved RO 0 1588 Capable When set, indicates that that EMAC0 is 1588-capable. 24 E1588 RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:7 reserved RO 0 GPIO Port G Present When set, indicates that GPIO Port G is present. 6 GPIOG RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 5 GPIOF RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 4 GPIOE RO 1 March 17, 2008 91 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description GPIO Port D Present When set, indicates that GPIO Port D is present. 3 GPIOD RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 2 GPIOC RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 1 GPIOB RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. 0 GPIOA RO 1 92 March 17, 2008 Preliminary System Control Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN0 reserved ADC Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:25 reserved RO 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:17 reserved RO 0 ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 reserved RO 0 March 17, 2008 93 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 11:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 94 March 17, 2008 Preliminary System Control Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN0 reserved ADC Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:25 reserved RO 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:17 reserved RO 0 ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 reserved RO 0 March 17, 2008 95 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 11:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 96 March 17, 2008 Preliminary System Control Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN0 reserved ADC Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MAXADCSPD reserved HIB reserved WDT reserved Type RO RO RO RO R/W R/W R/W R/W RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:25 reserved RO 0 CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:17 reserved RO 0 ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:12 reserved RO 0 March 17, 2008 97 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 1M samples/second 0x2 500K samples/second 0x1 250K samples/second 0x0 125K samples/second 11:8 MAXADCSPD R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 98 March 17, 2008 Preliminary System Control Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved SSI0 reserved UART1 UART0 Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 March 17, 2008 99 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 100 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 March 17, 2008 101 Preliminary LM3S8933 Microcontroller Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved SSI0 reserved UART1 UART0 Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 102 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 March 17, 2008 103 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 104 March 17, 2008 Preliminary System Control Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved SSI0 reserved UART1 UART0 Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comparator 2 Clock Gating This bit controls the clock gating for analog comparator 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 26 COMP2 R/W 0 Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 March 17, 2008 105 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 18 TIMER2 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:5 reserved RO 0 SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 106 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 March 17, 2008 107 Preliminary LM3S8933 Microcontroller Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 108 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 March 17, 2008 109 Preliminary LM3S8933 Microcontroller Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 110 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 March 17, 2008 111 Preliminary LM3S8933 Microcontroller Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 112 March 17, 2008 Preliminary System Control Bit/Field Name Type Reset Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 March 17, 2008 113 Preliminary LM3S8933 Microcontroller Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved CAN0 reserved ADC Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved HIB reserved WDT reserved Type RO RO RO RO RO RO RO RO RO R/W RO RO R/W RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:25 reserved RO 0 CAN0 Reset Control Reset control for CAN unit 0. 24 CAN0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:17 reserved RO 0 ADC0 Reset Control Reset control for SAR ADC module 0. 16 ADC R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:7 reserved RO 0 HIB Reset Control Reset control for the Hibernation module. 6 HIB R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5:4 reserved RO 0 WDT Reset Control Reset control for Watchdog unit. 3 WDT R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 114 March 17, 2008 Preliminary System Control Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved COMP2 COMP1 COMP0 reserved TIMER3 TIMER2 TIMER1 TIMER0 Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved I2C0 reserved SSI0 reserved UART1 UART0 Type RO RO RO R/W RO RO RO RO RO RO RO R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:27 reserved RO 0 Analog Comp 2 Reset Control Reset control for analog comparator 2. 26 COMP2 R/W 0 Analog Comp 1 Reset Control Reset control for analog comparator 1. 25 COMP1 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 24 COMP0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:20 reserved RO 0 Timer 3 Reset Control Reset control for General-Purpose Timer module 3. 19 TIMER3 R/W 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 18 TIMER2 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 17 TIMER1 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 16 TIMER0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:13 reserved RO 0 I2C0 Reset Control Reset control for I2C unit 0. 12 I2C0 R/W 0 March 17, 2008 115 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:5 reserved RO 0 SSI0 Reset Control Reset control for SSI unit 0. 4 SSI0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 UART1 Reset Control Reset control for UART unit 1. 1 UART1 R/W 0 UART0 Reset Control Reset control for UART unit 0. 0 UART0 R/W 0 116 March 17, 2008 Preliminary System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved EPHY0 reserved EMAC0 reserved Type RO R/W RO R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Type RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31 reserved RO 0 PHY0 Reset Control Reset control for Ethernet PHY unit 0. 30 EPHY0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 29 reserved RO 0 MAC0 Reset Control Reset control for Ethernet MAC unit 0. 28 EMAC0 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:7 reserved RO 0 Port G Reset Control Reset control for GPIO Port G. 6 GPIOG R/W 0 Port F Reset Control Reset control for GPIO Port F. 5 GPIOF R/W 0 Port E Reset Control Reset control for GPIO Port E. 4 GPIOE R/W 0 Port D Reset Control Reset control for GPIO Port D. 3 GPIOD R/W 0 Port C Reset Control Reset control for GPIO Port C. 2 GPIOC R/W 0 Port B Reset Control Reset control for GPIO Port B. 1 GPIOB R/W 0 March 17, 2008 117 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Port A Reset Control Reset control for GPIO Port A. 0 GPIOA R/W 0 118 March 17, 2008 Preliminary System Control 7 Hibernation Module The Hibernation Module manages removal and restoration of power to the rest of the microcontroller to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation Module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in real-time clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: ■ Power-switching logic to discrete external regulator ■ Dedicated pin for waking from an external signal ■ Low-battery detection, signaling, and interrupt generation ■ 32-bit real-time counter (RTC) ■ Two 32-bit RTC match registers for timed wake-up and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal ■ RTC predivider trim for making fine adjustments to the clock rate ■ 64 32-bit words of non-volatile memory ■ Programmable interrupts for RTC match, external wake, and low battery events March 17, 2008 119 Preliminary LM3S8933 Microcontroller 7.1 Block Diagram Figure 7-1. Hibernation Module Block Diagram HIBIM HIBRIS HIBMIS HIBIC HIBRTCT Pre-Divider /128 XOSC0 XOSC1 HIBCTL.CLK32EN HIBCTL.CLKSEL HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 RTC Interrupts Power Sequence Logic MATCH0/1 WAKE Interrupts to CPU Low Battery Detect LOWBAT VDD VBAT HIB HIBCTL.LOWBATEN HIBCTL.PWRCUT HIBCTL.EXTWEN HIBCTL.RTCWEN HIBCTL.VABORT Non-Volatile Memory HIBDATA 7.2 Functional Description The Hibernation module controls the power to the processor with an enable signal (HIB) that signals an external voltage regulator to turn off. The Hibernation module power is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. The Hibernation module also has a separate clock source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low, and optionally prevent hibernation when this occurs. Power-up from a power cut to code execution is defined as the regulator turn-on time (specified at tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 544). 7.2.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain 120 March 17, 2008 Preliminary Hibernation Module Hibernation registers, or between a write followed by a read to those same registers. There is no restriction on timing for back-to-back reads from the Hibernation module. 7.2.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature will not be used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator can be connected to the XOSC0 pin. The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a 32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. 7.2.3 Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage drops below 2.35 V. When this happens, an interrupt can be generated. The module also can be configured so that it will not go into Hibernate mode if the battery voltage drops below this threshold. Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 122). 7.2.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see “Clock Source” on page 121). The 32.768-kHz clock signal is fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate, and down from 0x7FFF in order to speed up the RTC rate. The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust March 17, 2008 121 Preliminary LM3S8933 Microcontroller the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see “Interrupts and Status” on page 122). 7.2.5 Non-Volatile Memory The Hibernation module contains 64 32-bit words of memory which are retained during hibernation. This memory is powered from the battery or auxiliary power supply during hibernation. The processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. The non-volatile memory can be accessed through the HIBDATA registers. 7.2.6 Power Control The Hibernation module controls power to the processor through the use of the HIB pin, which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the microcontroller. The Hibernation module remains powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power supply as the logic 1 reference. When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 122) and by looking for state data in the non-volatile memory (see “Non-Volatile Memory” on page 122). When the HIB signal deasserts, enabling the external regulator, the external regulator must reach the operating voltage within tHIB_TO_VDD. 7.2.7 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register. 122 March 17, 2008 Preliminary Hibernation Module 7.3 Initialization and Configuration The Hibernation module can be set in several different configurations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access Timing” on page 120). The registers that require a delay are listed in a note in “Register Map” on page 124 as well as in each register description. 7.3.1 Initialization The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal is used, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any other operations with the Hibernation module. If a 32.678-kHz oscillator is used, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input. 2. No delay is necessary. The above is only necessary when the entire system is initialized for the first time. If the processor is powered due to a wake from hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. 7.3.2 RTC Match Functionality (No Hibernation) Use the following steps to implement the RTC match functionality of the Hibernation module: 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 7.3.3 RTC Match/Wake-Up from Hibernation Use the following steps to implement the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. March 17, 2008 123 Preliminary LM3S8933 Microcontroller 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 7.3.4 External Wake-Up from Hibernation Use the following steps to implement the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 7.3.5 RTC/External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 7.4 Register Map Table 7-1 on page 124 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Table 7-1. Hibernation Module Register Map See Offset Name Type Reset Description page 0x000 HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 126 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 127 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 128 0x00C HIBRTCLD R/W 0xFFFF.FFFF Hibernation RTC Load 129 0x010 HIBCTL R/W 0x0000.0000 Hibernation Control 130 0x014 HIBIM R/W 0x0000.0000 Hibernation Interrupt Mask 132 0x018 HIBRIS RO 0x0000.0000 Hibernation Raw Interrupt Status 133 0x01C HIBMIS RO 0x0000.0000 Hibernation Masked Interrupt Status 134 0x020 HIBIC R/W1C 0x0000.0000 Hibernation Interrupt Clear 135 0x024 HIBRTCT R/W 0x0000.7FFF Hibernation RTC Trim 136 0x030- HIBDATA R/W 0x0000.0000 Hibernation Data 137 0x12C 124 March 17, 2008 Preliminary Hibernation Module 7.5 Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. March 17, 2008 125 Preliminary LM3S8933 Microcontroller Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description RTC Counter A read returns the 32-bit counter value. This register is read-only. To change the value, use the HIBRTCLD register. 31:0 RTCC RO 0x0000.0000 126 March 17, 2008 Preliminary Hibernation Module Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 31:0 RTCM0 R/W 0xFFFF.FFFF March 17, 2008 127 Preliminary LM3S8933 Microcontroller Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCM1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCM1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. 31:0 RTCM1 R/W 0xFFFF.FFFF 128 March 17, 2008 Preliminary Hibernation Module Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTCLD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCLD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 31:0 RTCLD R/W 0xFFFF.FFFF March 17, 2008 129 Preliminary LM3S8933 Microcontroller Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved VABORT CLK32EN LOWBATEN PINWEN RTCWEN CLKSEL HIBREQ RTCEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Power Cut Abort Enable Value Description 0 Power cut occurs during a low-battery alert. 1 Power cut is aborted. 7 VABORT R/W 0 32-kHz Oscillator Enable Value Description 0 Disabled 1 Enabled This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 6 CLK32EN R/W 0 Low Battery Monitoring Enable Value Description 0 Disabled 1 Enabled When set, low battery voltage detection is enabled (VBAT < 2.35 V). 5 LOWBATEN R/W 0 External WAKE Pin Enable Value Description 0 Disabled 1 Enabled When set, an external event on the WAKE pin will re-power the device. 4 PINWEN R/W 0 130 March 17, 2008 Preliminary Hibernation Module Bit/Field Name Type Reset Description RTC Wake-up Enable Value Description 0 Disabled 1 Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. 3 RTCWEN R/W 0 Hibernation Module Clock Select Value Description 0 Use Divide by 128 output. Use this value for a 4-MHz crystal. 1 Use raw output. Use this value for a 32-kHz oscillator. 2 CLKSEL R/W 0 Hibernation Request Value Description 0 Disabled 1 Hibernation initiated After a wake-up event, this bit is cleared by hardware. 1 HIBREQ R/W 0 RTC Timer Enable Value Description 0 Disabled 1 Enabled 0 RTCEN R/W 0 March 17, 2008 131 Preliminary LM3S8933 Microcontroller Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 External Wake-Up Interrupt Mask Value Description 0 Masked 1 Unmasked 3 EXTW R/W 0 Low Battery Voltage Interrupt Mask Value Description 0 Masked 1 Unmasked 2 LOWBAT R/W 0 RTC Alert1 Interrupt Mask Value Description 0 Masked 1 Unmasked 1 RTCALT1 R/W 0 RTC Alert0 Interrupt Mask Value Description 0 Masked 1 Unmasked 0 RTCALT0 R/W 0 132 March 17, 2008 Preliminary Hibernation Module Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Raw Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Raw Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Raw Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Raw Interrupt Status March 17, 2008 133 Preliminary LM3S8933 Microcontroller Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 3 EXTW RO 0 External Wake-Up Masked Interrupt Status 2 LOWBAT RO 0 Low Battery Voltage Masked Interrupt Status 1 RTCALT1 RO 0 RTC Alert1 Masked Interrupt Status 0 RTCALT0 RO 0 RTC Alert0 Masked Interrupt Status 134 March 17, 2008 Preliminary Hibernation Module Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved EXTW LOWBAT RTCALT1 RTCALT0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x000.0000 External Wake-Up Masked Interrupt Clear Reads return an indeterminate value. 3 EXTW R/W1C 0 Low Battery Voltage Masked Interrupt Clear Reads return an indeterminate value. 2 LOWBAT R/W1C 0 RTC Alert1 Masked Interrupt Clear Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert0 Masked Interrupt Clear Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 March 17, 2008 135 Preliminary LM3S8933 Microcontroller Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TRIM Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. The compensation is made by software by adjusting the default value of 0x7FFF up or down. 15:0 TRIM R/W 0x7FFF 136 March 17, 2008 Preliminary Hibernation Module Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store any non-volatile state data and will not lose power during a power cut operation. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 120. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RTD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTD Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description 31:0 RTD R/W 0x0000.0000 Hibernation Module NV Registers[63:0] March 17, 2008 137 Preliminary LM3S8933 Microcontroller 8 Internal Memory The LM3S8933 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 8.1 Block Diagram Figure 8-1. Flash Block Diagram Flash Control FMA FCMISC FCIM FCRIS FMC FMD Flash Timing USECRL Flash Protection FMPREn FMPPEn Flash Array SRAM Array Bridge Cortex-M3 ICode DCode System Bus APB User Registers USER_REG0 USER_REG1 USER_DBG 8.2 Functional Description This section describes the functionality of both the flash and SRAM memories. 8.2.1 SRAM Memory The internal SRAM of the Stellaris® devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: 138 March 17, 2008 Preliminary Internal Memory bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. 8.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 554 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 8.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 8.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed and contents of the memory block are prohibited from being accessed as data. The policies may be combined as shown in Table 8-1 on page 140. March 17, 2008 139 Preliminary LM3S8933 Microcontroller Table 8-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. 0 0 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 0 1 1 1 No protection. The block may be written, erased, executed or read. An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 141. 8.3 Flash Memory Initialization and Configuration 8.3.1 Flash Programming The Stellaris® devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. 8.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 8.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 8.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. 140 March 17, 2008 Preliminary Internal Memory 8.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the flash memory itself. These registers exist in a separate space from the main flash array and are not affected by an ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit in the FMC register to activate a write operation. For the USER_DBG register, the data to be written must be loaded into the FMD register before it is "committed". All other registers are R/W and can have their operation tried before committing them to nonvolatile memory. Important: These registers can only have bits changed from 1 to 0 by the user and there is no mechanism for the user to erase them back to a 1 value. In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective registers to indicate that they are available for user write. These three registers can only be written once whereas the flash protection registers may be written multiple times. Table 8-2 on page 141 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 8-2. Flash Resident Registersa Register to be Committed FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0008 FMPRE3 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.0001 USER_REG1 USER_DBG 0x7510.0000 FMD a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris® device. 8.4 Register Map Table 8-3 on page 141 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System Control base address of 0x400F.E000. Table 8-3. Flash Register Map See Offset Name Type Reset Description page Flash Control Offset 0x000 FMA R/W 0x0000.0000 Flash Memory Address 143 March 17, 2008 141 Preliminary LM3S8933 Microcontroller See Offset Name Type Reset Description page 0x004 FMD R/W 0x0000.0000 Flash Memory Data 144 0x008 FMC R/W 0x0000.0000 Flash Memory Control 145 0x00C FCRIS RO 0x0000.0000 Flash Controller Raw Interrupt Status 147 0x010 FCIM R/W 0x0000.0000 Flash Controller Interrupt Mask 148 0x014 FCMISC R/W1C 0x0000.0000 Flash Controller Masked Interrupt Status and Clear 149 System Control Offset 0x130 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 151 0x200 FMPRE0 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 0 151 0x134 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 152 0x400 FMPPE0 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 0 152 0x140 USECRL R/W 0x31 USec Reload 150 0x1D0 USER_DBG R/W 0xFFFF.FFFE User Debug 153 0x1E0 USER_REG0 R/W 0xFFFF.FFFF User Register 0 154 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 155 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 156 0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 157 0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 158 0x404 FMPPE1 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 1 159 0x408 FMPPE2 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 2 160 0x40C FMPPE3 R/W 0xFFFF.FFFF Flash Memory Protection Program Enable 3 161 8.5 Flash Register Descriptions (Flash Control Offset) This section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. 142 March 17, 2008 Preliminary Internal Memory Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved OFFSET Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:18 reserved RO 0x0 Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 141 for details on values for this field). 17:0 OFFSET R/W 0x0 March 17, 2008 143 Preliminary LM3S8933 Microcontroller Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Data Value Data value for write operation. 31:0 DATA R/W 0x0 144 March 17, 2008 Preliminary Internal Memory Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 143). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 144) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved COMT MERASE ERASE WRITE Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 31:16 WRKEY WO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:4 reserved RO 0x0 Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 3 COMT R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 2 MERASE R/W 0 March 17, 2008 145 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 1 ERASE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 μs. 0 WRITE R/W 0 146 March 17, 2008 Preliminary Internal Memory Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PRIS ARIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 145). 1 PRIS RO 0 Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPREn) and Flash Memory Protection Program Enable (FMPPEn) registers. Otherwise, no access has tried to improperly access the flash. 0 ARIS RO 0 March 17, 2008 147 Preliminary LM3S8933 Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMASK AMASK Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programming-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 1 PMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 0 AMASK R/W 0 148 March 17, 2008 Preliminary Internal Memory Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PMISC AMISC Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x0 Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 147) is also cleared when the PMISC bit is cleared. 1 PMISC R/W1C 0 Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. 0 AMISC R/W1C 0 8.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. March 17, 2008 149 Preliminary LM3S8933 Microcontroller Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved USEC Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x0 Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 7:0 USEC R/W 0x31 150 March 17, 2008 Preliminary Internal Memory Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.D000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF March 17, 2008 151 Preliminary LM3S8933 Microcontroller Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.D000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF 152 March 17, 2008 Preliminary Internal Memory Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA DBG1 DBG0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 Bit/Field Name Type Reset Description User Debug Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:2 DATA R/W 0x1FFFFFFF Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 1 DBG1 R/W 1 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 March 17, 2008 153 Preliminary LM3S8933 Microcontroller Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:0 DATA R/W 0x7FFFFFFF 154 March 17, 2008 Preliminary Internal Memory Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NW DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Not Written Specifies that this 32-bit dword has not been written. 31 NW R/W 1 User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 30:0 DATA R/W 0x7FFFFFFF March 17, 2008 155 Preliminary LM3S8933 Microcontroller Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF 156 March 17, 2008 Preliminary Internal Memory Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF March 17, 2008 157 Preliminary LM3S8933 Microcontroller Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 READ_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 READ_ENABLE R/W 0xFFFFFFFF 158 March 17, 2008 Preliminary Internal Memory Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF March 17, 2008 159 Preliminary LM3S8933 Microcontroller Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF 160 March 17, 2008 Preliminary Internal Memory Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROG_ENABLE Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 31:0 PROG_ENABLE R/W 0xFFFFFFFF March 17, 2008 161 Preliminary LM3S8933 Microcontroller 9 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module supports 6-36 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ 5-V-tolerant input/outputs ■ 4 high-drive GPIO capacity per device: 18mA maximum at Vol = 1.2V (a maximum of two high-drive pins per device side or BGA pin group). ■ Bit masking in both read and write operations through address lines ■ Programmable control for GPIO pad configuration: – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive for digital communication; 18mA pad drive for high current applications – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 9.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 9-1 on page 163). The LM3S8933 microcontroller contains seven ports and thus seven of these physical GPIO blocks. 162 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Figure 9-1. GPIO Port Block Diagram Alternate Input Alternate Output Alternate Output Enable Interrupt GPIO Input GPIO Output GPIO Output Enable Pad Output Pad Output Enable Package I/O Pin GPIODATA GPIODIR Data Control GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Interrupt Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN Pad Control GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Identification Registers GPIOAFSEL Mode Control DEMUX MUX MUX Digital I/O Pad Pad Input GPIOLOCK Commit Control GPIOCR 9.1.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 9.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 171) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 9.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 170) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. March 17, 2008 163 Preliminary LM3S8933 Microcontroller For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 9-2 on page 164, where u is data unchanged by the write. Figure 9-2. GPIODATA Write Example 0 0 1 0 0 1 1 0 1 0 u u 1 u u 0 1 u 9 8 7 6 5 4 3 2 1 0 1 1 1 0 1 0 1 1 7 6 5 4 3 2 1 0 GPIODATA 0xEB 0x098 ADDR[9:2] During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 164. Figure 9-3. GPIODATA Read Example 0 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 0 7 6 5 4 3 2 1 0 Returned Value GPIODATA 0x0C4 ADDR[9:2] 9.1.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 172) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 173) ■ GPIO Interrupt Event (GPIOIEV) register (see page 174) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 175). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 176 and page 177). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. 164 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR) register (see page 178). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 9.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 9.1.4 Commit Control The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. 9.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 9.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 166 shows all possible configurations of the GPIO pads and the control register settings required to March 17, 2008 165 Preliminary LM3S8933 Microcontroller achieve them. Table 9-2 on page 166 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. Table 9-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Valuea AFSEL DIR ODR DEN PUR PDR DR2R DR4R DR8R SLR Digital Input (GPIO) 0 0 0 1 ? ? X X X X Digital Output (GPIO) 0 1 0 1 ? ? ? ? ? ? Open Drain Input 0 0 1 1 X X X X X X (GPIO) Open Drain Output 0 1 1 1 X X ? ? ? ? (GPIO) Open Drain 1 X 1 1 X X ? ? ? ? Input/Output (I2C) Digital Input (Timer 1 X 0 1 ? ? X X X X CCP) Digital Output (Timer 1 X 0 1 ? ? ? ? ? ? PWM) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (SSI) Digital Input/Output 1 X 0 1 ? ? ? ? ? ? (UART) Analog Input 0 0 0 0 0 0 X X X X (Comparator) Digital Output 1 X 0 1 ? ? ? ? ? ? (Comparator) a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 9-2. GPIO Interrupt Configuration Example Desired Pin 2 Bit Valuea Interrupt Event Trigger Register 7 6 5 4 3 2 1 0 0=edge X X X X X 0 X X 1=level GPIOIS 0=single X X X X X 0 X X edge 1=both edges GPIOIBE 0=Low level, X X X X X 1 X X or negative edge 1=High level, or positive edge GPIOIEV 166 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Desired Pin 2 Bit Valuea Interrupt Event Trigger Register 7 6 5 4 3 2 1 0 0=masked 0 0 0 0 0 1 0 0 1=not masked GPIOIM a. X=Ignored (don’t care bit) 9.3 Register Map Table 9-3 on page 168 lists the GPIO registers. The offset listed is a hexadecimal increment to the register’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 ■ GPIO Port B: 0x4000.5000 ■ GPIO Port C: 0x4000.6000 ■ GPIO Port D: 0x4000.7000 ■ GPIO Port E: 0x4002.4000 ■ GPIO Port F: 0x4002.5000 ■ GPIO Port G: 0x4002.6000 Important: The GPIO registers in this chapter are duplicated in each GPIO block, however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. March 17, 2008 167 Preliminary LM3S8933 Microcontroller Table 9-3. GPIO Register Map See Offset Name Type Reset Description page 0x000 GPIODATA R/W 0x0000.0000 GPIO Data 170 0x400 GPIODIR R/W 0x0000.0000 GPIO Direction 171 0x404 GPIOIS R/W 0x0000.0000 GPIO Interrupt Sense 172 0x408 GPIOIBE R/W 0x0000.0000 GPIO Interrupt Both Edges 173 0x40C GPIOIEV R/W 0x0000.0000 GPIO Interrupt Event 174 0x410 GPIOIM R/W 0x0000.0000 GPIO Interrupt Mask 175 0x414 GPIORIS RO 0x0000.0000 GPIO Raw Interrupt Status 176 0x418 GPIOMIS RO 0x0000.0000 GPIO Masked Interrupt Status 177 0x41C GPIOICR W1C 0x0000.0000 GPIO Interrupt Clear 178 0x420 GPIOAFSEL R/W - GPIO Alternate Function Select 179 0x500 GPIODR2R R/W 0x0000.00FF GPIO 2-mA Drive Select 181 0x504 GPIODR4R R/W 0x0000.0000 GPIO 4-mA Drive Select 182 0x508 GPIODR8R R/W 0x0000.0000 GPIO 8-mA Drive Select 183 0x50C GPIOODR R/W 0x0000.0000 GPIO Open Drain Select 184 0x510 GPIOPUR R/W - GPIO Pull-Up Select 185 0x514 GPIOPDR R/W 0x0000.0000 GPIO Pull-Down Select 186 0x518 GPIOSLR R/W 0x0000.0000 GPIO Slew Rate Control Select 187 0x51C GPIODEN R/W - GPIO Digital Enable 188 0x520 GPIOLOCK R/W 0x0000.0001 GPIO Lock 189 0x524 GPIOCR - - GPIO Commit 190 0xFD0 GPIOPeriphID4 RO 0x0000.0000 GPIO Peripheral Identification 4 192 0xFD4 GPIOPeriphID5 RO 0x0000.0000 GPIO Peripheral Identification 5 193 0xFD8 GPIOPeriphID6 RO 0x0000.0000 GPIO Peripheral Identification 6 194 0xFDC GPIOPeriphID7 RO 0x0000.0000 GPIO Peripheral Identification 7 195 0xFE0 GPIOPeriphID0 RO 0x0000.0061 GPIO Peripheral Identification 0 196 0xFE4 GPIOPeriphID1 RO 0x0000.0000 GPIO Peripheral Identification 1 197 0xFE8 GPIOPeriphID2 RO 0x0000.0018 GPIO Peripheral Identification 2 198 0xFEC GPIOPeriphID3 RO 0x0000.0001 GPIO Peripheral Identification 3 199 0xFF0 GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 200 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 201 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 202 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 203 168 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) 9.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. March 17, 2008 169 Preliminary LM3S8933 Microcontroller Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 171). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 163 for examples of reads and writes. 7:0 DATA R/W 0x00 170 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Data Direction The DIR values are defined as follows: Value Description 0 Pins are inputs. 1 Pins are outputs. 7:0 DIR R/W 0x00 March 17, 2008 171 Preliminary LM3S8933 Microcontroller Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IS Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 Edge on corresponding pin is detected (edge-sensitive). 1 Level on corresponding pin is detected (level-sensitive). 7:0 IS R/W 0x00 172 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 172) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 174). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IBE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 174). 0 1 Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 7:0 IBE R/W 0x00 March 17, 2008 173 Preliminary LM3S8933 Microcontroller Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 172). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IEV Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Event The IEV values are defined as follows: Value Description Falling edge or Low levels on corresponding pins trigger interrupts. 0 Rising edge or High levels on corresponding pins trigger interrupts. 1 7:0 IEV R/W 0x00 174 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IME Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 Corresponding pin interrupt is masked. 1 Corresponding pin interrupt is not masked. 7:0 IME R/W 0x00 March 17, 2008 175 Preliminary LM3S8933 Microcontroller Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 175). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 Corresponding pin interrupt requirements not met. 1 Corresponding pin interrupt has met requirements. 7:0 RIS RO 0x00 176 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (the appropriate bit of GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 Corresponding GPIO line interrupt not active. 1 Corresponding GPIO line asserting interrupt. 7:0 MIS RO 0x00 March 17, 2008 177 Preliminary LM3S8933 Microcontroller Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IC Type RO RO RO RO RO RO RO RO W1C W1C W1C W1C W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 Corresponding interrupt is unaffected. 1 Corresponding interrupt is cleared. 7:0 IC W1C 0x00 178 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x420 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AFSEL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 March 17, 2008 179 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). Hardware control of corresponding GPIO line (alternate hardware function). 1 Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 AFSEL R/W - 180 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV2 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV2 R/W 0xFF March 17, 2008 181 Preliminary LM3S8933 Microcontroller Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV4 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV4 R/W 0x00 182 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DRV8 Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV8 R/W 0x00 March 17, 2008 183 Preliminary LM3S8933 Microcontroller Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 188). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ODE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 Open drain configuration is disabled. 1 Open drain configuration is enabled. 7:0 ODE R/W 0x00 184 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 186). The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x510 Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PUE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 PUE R/W - March 17, 2008 185 Preliminary LM3S8933 Microcontroller Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 185). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PDE Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 7:0 PDE R/W 0x00 186 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 183). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SRL Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 Slew rate control disabled. 1 Slew rate control enabled. 7:0 SRL R/W 0x00 March 17, 2008 187 Preliminary LM3S8933 Microcontroller Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x51C Type R/W, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DEN Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 Digital Enable The DEN values are defined as follows: Value Description 0 Digital functions disabled. 1 Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 DEN R/W - 188 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 190). Writing 0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCK Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description GPIO Lock A write of the value 0x1ACC.E551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked 31:0 LOCK R/W 0x0000.0001 March 17, 2008 189 Preliminary LM3S8933 Microcontroller Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and the corresponding registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x524 Type -, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CR Type RO RO RO RO RO RO RO RO - - - - - - - - Reset 0 0 0 0 0 0 0 0 - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 190 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. 7:0 CR - - March 17, 2008 191 Preliminary LM3S8933 Microcontroller Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 GPIO Peripheral ID Register[7:0] 192 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 GPIO Peripheral ID Register[15:8] March 17, 2008 193 Preliminary LM3S8933 Microcontroller Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 GPIO Peripheral ID Register[23:16] 194 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 GPIO Peripheral ID Register[31:24] March 17, 2008 195 Preliminary LM3S8933 Microcontroller Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x61 196 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 March 17, 2008 197 Preliminary LM3S8933 Microcontroller Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 198 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 March 17, 2008 199 Preliminary LM3S8933 Microcontroller Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 200 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 March 17, 2008 201 Preliminary LM3S8933 Microcontroller Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 202 March 17, 2008 Preliminary General-Purpose Input/Outputs (GPIOs) Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 March 17, 2008 203 Preliminary LM3S8933 Microcontroller 10 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris® General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1, Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The General-Purpose Timer Module is one timing resource available on the Stellaris® microcontrollers. Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 38). The following modes are supported: ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock using 32.768-KHz input clock – Software-controlled event stalling (excluding RTC mode) ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – Software-controlled event stalling ■ 16-bit Input Capture modes – Input edge count capture – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 10.1 Block Diagram Note: In Figure 10-1 on page 205, the specific CCP pins available depend on the Stellaris® device. See Table 10-1 on page 205 for the available CCPs. 204 March 17, 2008 Preliminary General-Purpose Timers Figure 10-1. GPTM Module Block Diagram TA Comparator TB Comparator GPTMTBR GPTMAR Clock / Edge Detect RTC Divider Clock / Edge Detect TimerA Interrupt TimerB Interrupt System Clock 0x0000 (Down Counter Modes) 0x0000 (Down Counter Modes) 32 KHz or Even CCP Pin Odd CCP Pin En En TimerA Control GPTMTAPMR GPTMTAILR GPTMTAMATCHR GPTMTAPR GPTMTAMR TimerB Control GPTMTBPMR GPTMTBILR GPTMTBMATCHR GPTMTBPR GPTMTBMR Interrupt / Config GPTMCFG GPTMRIS GPTMICR GPTMMIS GPTMIMR GPTMCTL Table 10-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin Timer 0 TimerA CCP0 - TimerB - CCP1 Timer 1 TimerA CCP2 - TimerB - CCP3 Timer 2 TimerA - - TimerB - - Timer 3 TimerA - - TimerB - - 10.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 216), the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and the GPTM TimerB Mode (GPTMTBMR) register (see page 219). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. March 17, 2008 205 Preliminary LM3S8933 Microcontroller 10.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 230) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 231). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 234) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 235). 10.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 230 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 231 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 238 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 239 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 10.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 221), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 226), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 228). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 224), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 227). The trigger is enabled by setting the TAOTE bit in GPTMCTL, and can trigger SoC-level events such as ADC conversions. 206 March 17, 2008 Preliminary General-Purpose Timers If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 10.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 232) by the controller. The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 10.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 216). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 10.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The trigger is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. March 17, 2008 207 Preliminary LM3S8933 Microcontroller If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 10-2. 16-Bit Timer With Prescaler Configurations Prescale #Clock (T c)a Max Time Units 00000000 1 1.3107 mS 00000001 2 2.6214 mS 00000010 3 3.9321 mS ------------ -- -- -- 11111100 254 332.9229 mS 11111110 255 334.2336 mS 11111111 256 335.5443 mS a. Tc is the clock period. 10.2.3.2 16-Bit Input Edge Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Count mode. In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 10-2 on page 209 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. 208 March 17, 2008 Preliminary General-Purpose Timers Figure 10-2. 16-Bit Input Edge Count Mode Example 0x000A 0x0006 0x0007 0x0008 0x0009 Input Signal Timer stops, flags asserted Timer reload Count on next cycle Ignored Ignored 10.2.3.3 16-Bit Input Edge Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be Low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency. Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of either rising or falling edges, but not both. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 10-3 on page 210 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). March 17, 2008 209 Preliminary LM3S8933 Microcontroller Figure 10-3. 16-Bit Input Edge Time Mode Example GPTMTnR=Y Input Signal Time Count GPTMTnR=X GPTMTnR=Z Z X Y 0xFFFF 10.2.3.4 16-Bit PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 10-4 on page 211 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. 210 March 17, 2008 Preliminary General-Purpose Timers Figure 10-4. 16-Bit PWM Mode Example Output Signal Time Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A TnPWML = 0 TnPWML = 1 TnEN set 10.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 10.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. March 17, 2008 211 Preliminary LM3S8933 Microcontroller 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 212. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4 pins. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 10.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 212 March 17, 2008 Preliminary General-Purpose Timers In One-Shot mode, the timer stops counting after step 8 on page 212. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 213 through step 9 on page 213. 10.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM March 17, 2008 213 Preliminary LM3S8933 Microcontroller Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 10.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 10.4 Register Map Table 10-3 on page 214 lists the GPTM registers. The offset listed is a hexadecimal increment to the register’s address, relative to that timer’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 ■ Timer3: 0x4003.3000 Table 10-3. Timers Register Map See Offset Name Type Reset Description page 0x000 GPTMCFG R/W 0x0000.0000 GPTM Configuration 216 0x004 GPTMTAMR R/W 0x0000.0000 GPTM TimerA Mode 217 0x008 GPTMTBMR R/W 0x0000.0000 GPTM TimerB Mode 219 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 221 214 March 17, 2008 Preliminary General-Purpose Timers See Offset Name Type Reset Description page 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 224 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 226 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 227 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 228 GPTM TimerA Interval Load 230 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x028 GPTMTAILR R/W 0x02C GPTMTBILR R/W 0x0000.FFFF GPTM TimerB Interval Load 231 GPTM TimerA Match 232 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x030 GPTMTAMATCHR R/W 0x034 GPTMTBMATCHR R/W 0x0000.FFFF GPTM TimerB Match 233 0x038 GPTMTAPR R/W 0x0000.0000 GPTM TimerA Prescale 234 0x03C GPTMTBPR R/W 0x0000.0000 GPTM TimerB Prescale 235 0x040 GPTMTAPMR R/W 0x0000.0000 GPTM TimerA Prescale Match 236 0x044 GPTMTBPMR R/W 0x0000.0000 GPTM TimerB Prescale Match 237 GPTM TimerA 238 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x048 GPTMTAR RO 0x04C GPTMTBR RO 0x0000.FFFF GPTM TimerB 239 10.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. March 17, 2008 215 Preliminary LM3S8933 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved GPTMCFG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 GPTM Configuration The GPTMCFG values are defined as follows: Value Description 0x0 32-bit timer configuration. 0x1 32-bit real-time clock (RTC) counter configuration. 0x2 Reserved 0x3 Reserved 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 0x4-0x7 2:0 GPTMCFG R/W 0x0 216 March 17, 2008 Preliminary General-Purpose Timers Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAAMS TACMR TAMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. 3 TAAMS R/W 0 GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode 2 TACMR R/W 0 March 17, 2008 217 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 1:0 TAMR R/W 0x0 218 March 17, 2008 Preliminary General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBAMS TBCMR TBMR Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 Capture mode is enabled. 1 PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. 3 TBAMS R/W 0 GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 Edge-Count mode 1 Edge-Time mode 2 TBCMR R/W 0 March 17, 2008 219 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register’s contents are ignored and GPTMTAMR is used. 1:0 TBMR R/W 0x0 220 March 17, 2008 Preliminary General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPWML TBOTE reserved TBEVENT TBSTALL TBEN reserved TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN Type RO R/W R/W RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:15 reserved RO 0x00 GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 14 TBPWML R/W 0 GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 The output TimerB trigger is disabled. 1 The output TimerB trigger is enabled. 13 TBOTE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 12 reserved RO 0 March 17, 2008 221 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 11:10 TBEVENT R/W 0x0 GPTM TimerB Stall Enable The TBSTALL values are defined as follows: Value Description 0 TimerB stalling is disabled. 1 TimerB stalling is enabled. 9 TBSTALL R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 TimerB is disabled. TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 8 TBEN R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7 reserved RO 0 GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 Output is unaffected. 1 Output is inverted. 6 TAPWML R/W 0 GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 The output TimerA trigger is disabled. 1 The output TimerA trigger is enabled. 5 TAOTE R/W 0 222 March 17, 2008 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 0 RTC counting is disabled. 1 RTC counting is enabled. 4 RTCEN R/W 0 GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 3:2 TAEVENT R/W 0x0 GPTM TimerA Stall Enable The TASTALL values are defined as follows: Value Description 0 TimerA stalling is disabled. 1 TimerA stalling is enabled. 1 TASTALL R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 TimerA is disabled. TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 1 0 TAEN R/W 0 March 17, 2008 223 Preliminary LM3S8933 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEIM CBMIM TBTOIM reserved RTCIM CAEIM CAMIM TATOIM Type RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 10 CBEIM R/W 0 GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 9 CBMIM R/W 0 GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 8 TBTOIM R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0 224 March 17, 2008 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 3 RTCIM R/W 0 GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 2 CAEIM R/W 0 GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 1 CAMIM R/W 0 GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 Interrupt is disabled. 1 Interrupt is enabled. 0 TATOIM R/W 0 March 17, 2008 225 Preliminary LM3S8933 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBERIS CBMRIS TBTORIS reserved RTCRIS CAERIS CAMRIS TATORIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 10 CBERIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 9 CBMRIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 8 TBTORIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 3 RTCRIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 2 CAERIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 1 CAMRIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 0 TATORIS RO 0 226 March 17, 2008 Preliminary General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBEMIS CBMMIS TBTOMIS reserved RTCMIS CAEMIS CAMMIS TATOMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 10 CBEMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 9 CBMMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 8 TBTOMIS RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 3 RTCMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 2 CAEMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 1 CAMMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. 0 TATOMIS RO 0 March 17, 2008 227 Preliminary LM3S8933 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CBECINT CBMCINT TBTOCINT reserved RTCCINT CAECINT CAMCINT TATOCINT Type RO RO RO RO RO W1C W1C W1C RO RO RO RO W1C W1C W1C W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:11 reserved RO 0x00 GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 10 CBECINT W1C 0 GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 9 CBMCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 8 TBTOCINT W1C 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:4 reserved RO 0x0 228 March 17, 2008 Preliminary General-Purpose Timers Bit/Field Name Type Reset Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 3 RTCCINT W1C 0 GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 2 CAECINT W1C 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 1 CAMCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt The TATOCINT values are defined as follows: Value Description 0 The interrupt is unaffected. 1 The interrupt is cleared. 0 TATOCINT W1C 0 March 17, 2008 229 Preliminary LM3S8933 Microcontroller Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAILRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Interval Load Register High When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TAILRH R/W GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 15:0 TAILRL R/W 0xFFFF 230 March 17, 2008 Preliminary General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBILRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 15:0 TBILRL R/W 0xFFFF March 17, 2008 231 Preliminary LM3S8933 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TAMRH Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Match Register High When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TAMRH R/W GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 15:0 TAMRL R/W 0xFFFF 232 March 17, 2008 Preliminary General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBMRL Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 15:0 TBMRL R/W 0xFFFF March 17, 2008 233 Preliminary LM3S8933 Microcontroller Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 10-2 on page 208 for more details and an example. 7:0 TAPSR R/W 0x00 234 March 17, 2008 Preliminary General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 10-2 on page 208 for more details and an example. 7:0 TBPSR R/W 0x00 March 17, 2008 235 Preliminary LM3S8933 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TAPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 7:0 TAPSMR R/W 0x00 236 March 17, 2008 Preliminary General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TBPSMR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 7:0 TBPSMR R/W 0x00 March 17, 2008 237 Preliminary LM3S8933 Microcontroller Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TARH Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TARL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description GPTM TimerA Register High If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. 0xFFFF (32-bit mode) 0x0000 (16-bit mode) 31:16 TARH RO GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TARL RO 0xFFFF 238 March 17, 2008 Preliminary General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBRL Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x0000 GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TBRL RO 0xFFFF March 17, 2008 239 Preliminary LM3S8933 Microcontroller 11 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris® Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a locking register, and user-enabled stalling. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 11.1 Block Diagram Figure 11-1. WDT Module Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR WDTRIS WDTMIS WDTLOCK WDTTEST WDTLOAD WDTVALUE Comparator 32-Bit Down Counter 0x00000000 Interrupt System Clock Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 11.2 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the 240 March 17, 2008 Preliminary Watchdog Timer Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 11.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 11.4 Register Map Table 11-1 on page 241 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 11-1. Watchdog Timer Register Map See Offset Name Type Reset Description page 0x000 WDTLOAD R/W 0xFFFF.FFFF Watchdog Load 243 0x004 WDTVALUE RO 0xFFFF.FFFF Watchdog Value 244 0x008 WDTCTL R/W 0x0000.0000 Watchdog Control 245 0x00C WDTICR WO - Watchdog Interrupt Clear 246 0x010 WDTRIS RO 0x0000.0000 Watchdog Raw Interrupt Status 247 0x014 WDTMIS RO 0x0000.0000 Watchdog Masked Interrupt Status 248 0x418 WDTTEST R/W 0x0000.0000 Watchdog Test 249 0xC00 WDTLOCK R/W 0x0000.0000 Watchdog Lock 250 March 17, 2008 241 Preliminary LM3S8933 Microcontroller See Offset Name Type Reset Description page 0xFD0 WDTPeriphID4 RO 0x0000.0000 Watchdog Peripheral Identification 4 251 0xFD4 WDTPeriphID5 RO 0x0000.0000 Watchdog Peripheral Identification 5 252 0xFD8 WDTPeriphID6 RO 0x0000.0000 Watchdog Peripheral Identification 6 253 0xFDC WDTPeriphID7 RO 0x0000.0000 Watchdog Peripheral Identification 7 254 0xFE0 WDTPeriphID0 RO 0x0000.0005 Watchdog Peripheral Identification 0 255 0xFE4 WDTPeriphID1 RO 0x0000.0018 Watchdog Peripheral Identification 1 256 0xFE8 WDTPeriphID2 RO 0x0000.0018 Watchdog Peripheral Identification 2 257 0xFEC WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 258 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 259 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 260 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 261 0xFFC WDTPCellID3 RO 0x0000.00B1 Watchdog PrimeCell Identification 3 262 11.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 242 March 17, 2008 Preliminary Watchdog Timer Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLoad Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description 31:0 WDTLoad R/W 0xFFFF.FFFF Watchdog Load Value March 17, 2008 243 Preliminary LM3S8933 Microcontroller Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTValue Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit/Field Name Type Reset Description Watchdog Value Current value of the 32-bit down counter. 31:0 WDTValue RO 0xFFFF.FFFF 244 March 17, 2008 Preliminary Watchdog Timer Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RESEN INTEN Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 Disabled. 1 Enable the Watchdog module reset output. 1 RESEN R/W 0 Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 1 Interrupt event enabled. Once enabled, all writes are ignored. 0 INTEN R/W 0 March 17, 2008 245 Preliminary LM3S8933 Microcontroller Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTIntClr Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description 31:0 WDTIntClr WO - Watchdog Interrupt Clear 246 March 17, 2008 Preliminary Watchdog Timer Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTRIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 0 WDTRIS RO 0 March 17, 2008 247 Preliminary LM3S8933 Microcontroller Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved WDTMIS Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 0 WDTMIS RO 0 248 March 17, 2008 Preliminary Watchdog Timer Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved STALL reserved Type RO RO RO RO RO RO RO R/W RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:9 reserved RO 0x00 Watchdog Stall Enable When set to 1, if the Stellaris® microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. 8 STALL R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:0 reserved RO 0x00 March 17, 2008 249 Preliminary LM3S8933 Microcontroller Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDTLock Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 31:0 WDTLock R/W 0x0000 250 March 17, 2008 Preliminary Watchdog Timer Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID4 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID4 RO 0x00 WDT Peripheral ID Register[7:0] March 17, 2008 251 Preliminary LM3S8933 Microcontroller Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID5 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID5 RO 0x00 WDT Peripheral ID Register[15:8] 252 March 17, 2008 Preliminary Watchdog Timer Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID6 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID6 RO 0x00 WDT Peripheral ID Register[23:16] March 17, 2008 253 Preliminary LM3S8933 Microcontroller Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID7 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID7 RO 0x00 WDT Peripheral ID Register[31:24] 254 March 17, 2008 Preliminary Watchdog Timer Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID0 RO 0x05 Watchdog Peripheral ID Register[7:0] March 17, 2008 255 Preliminary LM3S8933 Microcontroller Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID1 RO 0x18 Watchdog Peripheral ID Register[15:8] 256 March 17, 2008 Preliminary Watchdog Timer Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID2 RO 0x18 Watchdog Peripheral ID Register[23:16] March 17, 2008 257 Preliminary LM3S8933 Microcontroller Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 PID3 RO 0x01 Watchdog Peripheral ID Register[31:24] 258 March 17, 2008 Preliminary Watchdog Timer Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID0 RO 0x0D Watchdog PrimeCell ID Register[7:0] March 17, 2008 259 Preliminary LM3S8933 Microcontroller Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID1 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID1 RO 0xF0 Watchdog PrimeCell ID Register[15:8] 260 March 17, 2008 Preliminary Watchdog Timer Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID2 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID2 RO 0x05 Watchdog PrimeCell ID Register[23:16] March 17, 2008 261 Preliminary LM3S8933 Microcontroller Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved CID3 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0x00 7:0 CID3 RO 0xB1 Watchdog PrimeCell ID Register[31:24] 262 March 17, 2008 Preliminary Watchdog Timer 12 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris® ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor. The ADC module contains a programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. The Stellaris® ADC provides the following features: ■ Four analog input channels ■ Single-ended and differential-input configurations ■ Internal temperature sensor ■ Sample rate of one million samples/second ■ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy March 17, 2008 263 Preliminary LM3S8933 Microcontroller 12.1 Block Diagram Figure 12-1. ADC Module Block Diagram Analog-to-Digital Converter ADCSSFSTAT0 ADCSSCTL0 ADCSSMUX0 Sample Sequencer 0 ADCSSFSTAT1 ADCSSCTL1 ADCSSMUX1 Sample Sequencer 1 ADCSSFSTAT2 ADCSSCTL2 ADCSSMUX2 Sample Sequencer 2 ADCSSFSTAT3 ADCSSCTL3 ADCSSMUX3 Sample Sequencer 3 ADCUSTAT ADCOSTAT ADCACTSS Control/Status ADCSSPRI ADCISC ADCRIS ADCIM Interrupt Control Analog Inputs SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt ADCEMUX ADCPSSI Trigger Events SS0 SS1 SS2 SS3 Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM ADCSSFIFO0 ADCSSFIFO1 ADCSSFIFO2 ADCSSFIFO3 FIFO Block Hardware Averager ADCSAC 12.2 Functional Description The Stellaris® ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approach found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the controller. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. 12.2.1 Sample Sequencers The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 12-1 on page 264 shows the maximum number of samples that each Sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 12-1. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 1 1 SS2 4 4 SS1 4 4 SS0 8 8 264 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample Sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured before being enabled. When configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 12.2.2 Module Control Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such as interrupt generation, sequence prioritization, and trigger configuration. Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock divider configuration targets 16.667 MHz operation for all Stellaris® devices. 12.2.2.1 Interrupts The Sample Sequencers dictate the events that cause interrupts, but they don't have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and Clear (ADCISC) register, which shows the logical AND of the ADCRIS register’s INR bit and the ADCIM register’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. 12.2.2.2 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample Sequencer units with the same priority do not provide consistent results, so software must ensure that all active Sample Sequencer units have a unique priority value. 12.2.2.3 Sampling Events Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select (ADCEMUX) register. The external peripheral triggering sources vary by Stellaris® family member, March 17, 2008 265 Preliminary LM3S8933 Microcontroller but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible to starve other lower priority sequences. 12.2.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 282). There is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or differential. 12.2.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. An internal 3 V reference is used by the converter resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended input mode. 12.2.5 Differential Sampling In addition to traditional single-ended sampling, the ADC module supports differential sampling of two analog input channels. To enable differential sampling, software must set the D bit in a step's configuration nibble. When a sequence step is configured for differential sampling, its corresponding value in the ADCSSMUX register must be set to one of the four differential pairs, numbered 0-3. Differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see Table 12-2 on page 266). The ADC does not support other differential pairings such as analog input 0 with analog input 3. The number of differential pairs supported is dependent on the number of analog inputs (see Table 12-2 on page 266). Table 12-2. Differential Sampling Pairs Differential Pair Analog Inputs 0 0 and 1 1 2 and 3 The voltage sampled in differential mode is the difference between the odd and even channels: ΔV (differential voltage) = V0 (even channels) – V1 (odd channels), therefore: ■ If ΔV = 0, then the conversion result = 0x1FF ■ If ΔV > 0, then the conversion result > 0x1FF (range is 0x1FF–0x3FF) ■ If ΔV < 0, then the conversion result < 0x1FF (range is 0–0x1FF) The differential pairs assign polarities to the analog inputs: the even-numbered input is always positive, and the odd-numbered input is always negative. In order for a valid conversion result to 266 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) appear, the negative input must be in the range of ± 1.5 V of the positive input. If an analog input is greater than 3 V or less than 0 V (the valid range for analog inputs), the input voltage is clipped, meaning it appears as either 3 V or 0 V, respectively, to the ADC. Figure 12-2 on page 267 shows an example of the negative input centered at 1.5 V. In this configuration, the differential range spans from -1.5 V to 1.5 V. Figure 12-3 on page 267 shows an example where the negative input is centered at -0.75 V, meaning inputs on the positive input saturate past a differential voltage of -0.75 V since the input voltage is less than 0 V. Figure 12-4 on page 268 shows an example of the negative input centered at 2.25 V, where inputs on the positive channel saturate past a differential voltage of 0.75 V since the input voltage would be greater than 3 V. Figure 12-2. Differential Sampling Range, Vin(-) = 1.5 V ADC Conversion Result Differential Voltage, Vin (+) = 1.5V -1.5V +1.5V 0x1FF 0x3FF - Input Saturation Figure 12-3. Differential Sampling Range, Vin(-) = 0.75 V ADC Conversion Result -1.5V +1.5V 0x1FF 0x3FF Differential Voltage, Vin (+) = 0.75V 0x0FF -0.75V - Input Saturation March 17, 2008 267 Preliminary LM3S8933 Microcontroller Figure 12-4. Differential Sampling Range, Vin(-) = 2.25 V ADC Conversion Result -1.5V +1.5V 0x1FF 0x3FF Differential Voltage, Vin (+) = 2.25V 0x2FF +0.75V - Input Saturation 12.2.6 Test Modes There is a user-available test mode that allows for loopback operation within the digital portion of the ADC module. This can be useful for debugging software without having to provide actual analog stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see page 295). 12.2.7 Internal Temperature Sensor The internal temperature sensor provides an analog temperature reading as well as a reference voltage. The voltage at the output terminal SENSO is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 12-5 on page 268. Figure 12-5. Internal Temperature Sensor Characteristic 268 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) 12.3 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 12.3.1 Module Initialization Initialization of the ADC module is a simple process with very few steps. The main steps include enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 99). 2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority. 12.3.2 Sample Sequencer Configuration Configuration of the Sample Sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. The configuration for each Sample Sequencer should be as follows: 1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in the ADCACTSS register. Programming of the Sample Sequencers is allowed without having them enabled. Disabling the Sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the ADCACTSS register. 12.4 Register Map Table 12-3 on page 269 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s address, relative to the ADC base address of 0x4003.8000. Table 12-3. ADC Register Map See Offset Name Type Reset Description page 0x000 ADCACTSS R/W 0x0000.0000 ADC Active Sample Sequencer 271 March 17, 2008 269 Preliminary LM3S8933 Microcontroller See Offset Name Type Reset Description page 0x004 ADCRIS RO 0x0000.0000 ADC Raw Interrupt Status 272 0x008 ADCIM R/W 0x0000.0000 ADC Interrupt Mask 273 0x00C ADCISC R/W1C 0x0000.0000 ADC Interrupt Status and Clear 274 0x010 ADCOSTAT R/W1C 0x0000.0000 ADC Overflow Status 275 0x014 ADCEMUX R/W 0x0000.0000 ADC Event Multiplexer Select 276 0x018 ADCUSTAT R/W1C 0x0000.0000 ADC Underflow Status 279 0x020 ADCSSPRI R/W 0x0000.3210 ADC Sample Sequencer Priority 280 0x028 ADCPSSI WO - ADC Processor Sample Sequence Initiate 281 0x030 ADCSAC R/W 0x0000.0000 ADC Sample Averaging Control 282 0x040 ADCSSMUX0 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 0 283 0x044 ADCSSCTL0 R/W 0x0000.0000 ADC Sample Sequence Control 0 285 0x048 ADCSSFIFO0 RO 0x0000.0000 ADC Sample Sequence Result FIFO 0 288 0x04C ADCSSFSTAT0 RO 0x0000.0100 ADC Sample Sequence FIFO 0 Status 289 0x060 ADCSSMUX1 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 1 290 0x064 ADCSSCTL1 R/W 0x0000.0000 ADC Sample Sequence Control 1 291 0x068 ADCSSFIFO1 RO 0x0000.0000 ADC Sample Sequence Result FIFO 1 288 0x06C ADCSSFSTAT1 RO 0x0000.0100 ADC Sample Sequence FIFO 1 Status 289 0x080 ADCSSMUX2 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 2 290 0x084 ADCSSCTL2 R/W 0x0000.0000 ADC Sample Sequence Control 2 291 0x088 ADCSSFIFO2 RO 0x0000.0000 ADC Sample Sequence Result FIFO 2 288 0x08C ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 289 0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 293 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 294 0x0A8 ADCSSFIFO3 RO 0x0000.0000 ADC Sample Sequence Result FIFO 3 288 0x0AC ADCSSFSTAT3 RO 0x0000.0100 ADC Sample Sequence FIFO 3 Status 289 0x100 ADCTMLB R/W 0x0000.0000 ADC Test Mode Loopback 295 12.5 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. 270 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be enabled/disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ASEN3 ASEN2 ASEN1 ASEN0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 ADC SS3 Enable Specifies whether Sample Sequencer 3 is enabled. If set, the sample sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is inactive. 3 ASEN3 R/W 0 ADC SS2 Enable Specifies whether Sample Sequencer 2 is enabled. If set, the sample sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is inactive. 2 ASEN2 R/W 0 ADC SS1 Enable Specifies whether Sample Sequencer 1 is enabled. If set, the sample sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is inactive. 1 ASEN1 R/W 0 ADC SS0 Enable Specifies whether Sample Sequencer 0 is enabled. If set, the sample sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is inactive. 0 ASEN0 R/W 0 March 17, 2008 271 Preliminary LM3S8933 Microcontroller Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved INR3 INR2 INR1 INR0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL3 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN3 bit. 3 INR3 RO 0 SS2 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL2 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN2 bit. 2 INR2 RO 0 SS1 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL1 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN1 bit. 1 INR1 RO 0 SS0 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL0 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN0 bit. 0 INR0 RO 0 272 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MASK3 MASK2 MASK1 MASK0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 3 MASK3 R/W 0 SS2 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 2 MASK2 R/W 0 SS1 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 1 MASK1 R/W 0 SS0 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 0 MASK0 R/W 0 March 17, 2008 273 Preliminary LM3S8933 Microcontroller Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing interrupt conditions, and shows the status of controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still cleared via the ADCISC register, even if the IN bit is not set. ADC Interrupt Status and Clear (ADCISC) Base 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IN3 IN2 IN1 IN0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 Interrupt Status and Clear This bit is set by hardware when the MASK3 and INR3 bits are both 1, providing a level-based interrupt to the controller. It is cleared by writing a 1, and also clears the INR3 bit. 3 IN3 R/W1C 0 SS2 Interrupt Status and Clear This bit is set by hardware when the MASK2 and INR2 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR2 bit. 2 IN2 R/W1C 0 SS1 Interrupt Status and Clear This bit is set by hardware when the MASK1 and INR1 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR1 bit. 1 IN1 R/W1C 0 SS0 Interrupt Status and Clear This bit is set by hardware when the MASK0 and INR0 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR0 bit. 0 IN0 R/W1C 0 274 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OV3 OV2 OV1 OV0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 3 OV3 R/W1C 0 SS2 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 2 OV2 R/W1C 0 SS1 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS0 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 0 OV0 R/W1C 0 March 17, 2008 275 Preliminary LM3S8933 Microcontroller Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each Sample Sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM3 EM2 EM1 EM0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 Reserved 0x7 Reserved 0x8 Reserved 0x9-0xE reserved 0xF Always (continuously sample) 15:12 EM3 R/W 0x00 276 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 Reserved 0x7 Reserved 0x8 Reserved 0x9-0xE reserved 0xF Always (continuously sample) 11:8 EM2 R/W 0x00 SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 Reserved 0x7 Reserved 0x8 Reserved 0x9-0xE reserved 0xF Always (continuously sample) 7:4 EM1 R/W 0x00 March 17, 2008 277 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Analog Comparator 1 0x3 Analog Comparator 2 0x4 External (GPIO PB4) 0x5 Timer 0x6 Reserved 0x7 Reserved 0x8 Reserved 0x9-0xE reserved 0xF Always (continuously sample) 3:0 EM0 R/W 0x00 278 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding underflow condition can be cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved UV3 UV2 UV1 UV0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W1C R/W1C R/W1C R/W1C Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 SS3 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 3 UV3 R/W1C 0 SS2 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 2 UV2 R/W1C 0 SS1 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS0 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 March 17, 2008 279 Preliminary LM3S8933 Microcontroller Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority or the ADC behavior is inconsistent. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS3 reserved SS2 reserved SS1 reserved SS0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x00 SS3 Priority The SS3 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the Sequencers must be uniquely mapped. ADC behavior is not consistent if two or more fields are equal. 13:12 SS3 R/W 0x3 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0x0 SS2 Priority The SS2 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. 9:8 SS2 R/W 0x2 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0x0 SS1 Priority The SS1 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. 5:4 SS1 R/W 0x1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0x0 SS0 Priority The SS0 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. 1:0 SS0 R/W 0x0 280 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the Sample Sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.8000 Offset 0x028 Type WO, reset - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SS3 SS2 SS1 SS0 Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset - - - - - - - - - - - - - - - - Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved WO - SS3 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS register. 3 SS3 WO - SS2 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS register. 2 SS2 WO - SS1 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS register. 1 SS1 WO - SS0 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS register. 0 SS0 WO - March 17, 2008 281 Preliminary LM3S8933 Microcontroller Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG = 7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) Base 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved AVG Type RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:3 reserved RO 0x00 Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 No hardware oversampling 0x1 2x hardware oversampling 0x2 4x hardware oversampling 0x3 8x hardware oversampling 0x4 16x hardware oversampling 0x5 32x hardware oversampling 0x6 64x hardware oversampling 0x7 Reserved 2:0 AVG R/W 0x0 282 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved MUX7 reserved MUX6 reserved MUX5 reserved MUX4 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:30 reserved RO 0 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the Sample Sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 1 indicates the input is ADC1. 29:28 MUX7 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 27:26 reserved RO 0 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 25:24 MUX6 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 23:22 reserved RO 0 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 21:20 MUX5 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 19:18 reserved RO 0 March 17, 2008 283 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 17:16 MUX4 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 15:14 reserved RO 0 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 13:12 MUX3 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 9:8 MUX2 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 5:4 MUX1 R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 1:0 MUX0 R/W 0 284 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) Base 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TS7 IE7 END7 D7 TS6 IE6 END6 D6 TS5 IE5 END5 D5 TS4 IE4 END4 D4 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description 8th Sample Temp Sensor Select The TS7 bit is used during the eighth sample of the sample sequence and specifies the input source of the sample. If set, the temperature sensor is read. Otherwise, the input pin specified by the ADCSSMUX register is read. 31 TS7 R/W 0 8th Sample Interrupt Enable The IE7 bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal (INR0 bit) is asserted at the end of the sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to a controller-level interrupt. When this bit is set, the raw interrupt is asserted, otherwise it is not. It is legal to have multiple samples within a sequence generate interrupts. 30 IE7 R/W 0 8th Sample is End of Sequence The END7 bit indicates that this is the last sample of the sequence. It is possible to end the sequence on any sample position. Samples defined after the sample containing a set END are not requested for conversion even though the fields may be non-zero. It is required that software write the END bit somewhere within the sequence. (Sample Sequencer 3, which only has a single sample in the sequence, is hardwired to have the END0 bit set.) Setting this bit indicates that this sample is the last in the sequence. 29 END7 R/W 0 8th Sample Diff Input Select The D7 bit indicates that the analog input is to be differentially sampled. The corresponding ADCSSMUXx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". The temperature sensor does not have a differential option. When set, the analog inputs are differentially sampled. 28 D7 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 27 TS6 R/W 0 March 17, 2008 285 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 26 IE6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 25 END6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 24 D6 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 23 TS5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 21 END5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 20 D5 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 19 TS4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 17 END4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 16 D4 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 13 END3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 12 D3 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 11 TS2 R/W 0 286 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 9 END2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 8 D2 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 7 TS1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 5 END1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 4 D1 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 March 17, 2008 287 Preliminary LM3S8933 Microcontroller Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 This register contains the conversion results for samples collected with the Sample Sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0) Base 0x4003.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0x00 9:0 DATA RO 0x00 Conversion Result Data 288 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the Sample Sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1, ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) Base 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved FULL reserved EMPTY HPTR TPTR Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:13 reserved RO 0x00 FIFO Full When set, indicates that the FIFO is currently full. 12 FULL RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:9 reserved RO 0x00 FIFO Empty When set, indicates that the FIFO is currently empty. 8 EMPTY RO 1 FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. 7:4 HPTR RO 0x00 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. 3:0 TPTR RO 0x00 March 17, 2008 289 Preliminary LM3S8933 Microcontroller Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 283 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) Base 0x4003.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX3 reserved MUX2 reserved MUX1 reserved MUX0 Type RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:14 reserved RO 0x00 13:12 MUX3 R/W 0 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 11:10 reserved RO 0 9:8 MUX2 R/W 0 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:6 reserved RO 0 5:4 MUX1 R/W 0 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3:2 reserved RO 0 1:0 MUX0 R/W 0 1st Sample Input Select 290 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on page 285 for detailed bit descriptions. ADC Sample Sequence Control 1 (ADCSSCTL1) Base 0x4003.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0x00 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 13 END3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 12 D3 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 11 TS2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 9 END2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 8 D2 R/W 0 March 17, 2008 291 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 7 TS1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 5 END1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 4 D1 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 292 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 283 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved MUX0 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:2 reserved RO 0x00 1:0 MUX0 R/W 0 1st Sample Input Select March 17, 2008 293 Preliminary LM3S8933 Microcontroller Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 285 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) Base 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TS0 IE0 END0 D0 Type RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0x00 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 1 END0 R/W 1 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 0 D0 R/W 0 294 March 17, 2008 Preliminary Analog-to-Digital Converter (ADC) Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned. ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved LB Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:1 reserved RO 0x00 Loopback Mode Enable When set, forces a loopback within the digital block to provide information on input and unique numbering. The ADCSSFIFOn registers do not provide sample data, but instead provide the 10-bit loopback data as shown below. Bit/Field Name Description Continuous Sample Counter Continuous sample counter that is initialized to 0 and counts each sample as it processed. This helps provide a unique value for the data received. 9:6 CNT Continuation Sample Indicator When set, indicates that this is a continuation sample. For example, if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 5 CONT Differential Sample Indicator When set, indicates that this is a differential sample. 4 DIFF Temp Sensor Sample Indicator When set, indicates that this is a temperature sensor sample. 3 TS Analog Input Indicator Indicates which analog input is to be sampled. 2:0 MUX 0 LB R/W 0 March 17, 2008 295 Preliminary LM3S8933 Microcontroller 13 Universal Asynchronous Receivers/Transmitters (UARTs) The Stellaris® Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S8933 controller is equipped with two UART modules. Each UART has the following features: ■ Separate transmit and receive FIFOs ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Programmable baud-rate generator allowing rates up to 3.125 Mbps ■ Standard asynchronous communication bits for start, stop, and parity ■ False start bit detection ■ Line-break generation and detection ■ Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing: – Programmable use of IrDA Serial Infrared (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration 296 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) 13.1 Block Diagram Figure 13-1. UART Module Block Diagram Receiver Transmitter System Clock Control / Status UARTRSR/ECR UARTFR UARTLCRH UARTCTL UARTILPR Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Baud Rate Generator UARTIBRD UARTFBRD Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTDR TXFIFO 16x8 ... RXFIFO 16x8 ... Interrupt UnTx UnRx 13.2 Functional Description Each Stellaris® UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 315). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. 13.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data March 17, 2008 297 Preliminary LM3S8933 Microcontroller bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 13-2 on page 298 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 13-2. UART Character Frame 1 0 5-8 data bits LSB MSB Parity bit if enabled 1-2 stop bits UnTX n Start 13.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 311) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 312). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.) BRD = BRDI + BRDF = UARTSysClk / (16 * Baud Rate) where UARTSysClk is the system clock connected to the UART. The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 313), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 298 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) 13.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 308) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 297). The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 306). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 13.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output, and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 μs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. See page 310 for more information on IrDA low-power pulse-duration configuration. Figure 13-3 on page 300 shows the UART transmit and receive signals, with and without IrDA modulation. March 17, 2008 299 Preliminary LM3S8933 Microcontroller Figure 13-3. IrDA Data Modulation 0 1 0 1 0 0 1 1 0 1 Data bits 0 1 0 1 0 0 1 1 0 1 Start Data bits bit Start Stop Bit period Bit period 3 16 UnTx UnTx with IrDA UnRx with IrDA UnRx Stop bit In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. 13.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 304). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 313). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 308) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 317). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 13.2.6 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error 300 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 322). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 319) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 321). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 323). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 13.2.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 315). In loopback mode, data transmitted on UnTx is received on the UnRx input. 13.2.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 13.3 Initialization and Configuration To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the RCGC1 register. This section discusses the steps that are required to use a UART module. For this example, the UART clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit March 17, 2008 301 Preliminary LM3S8933 Microcontroller ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 298, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 311) should be set to 10. The value to be loaded into the UARTFBRD register (see page 312) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. 13.4 Register Map Table 13-1 on page 302 lists the UART registers. The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 315) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 13-1. UART Register Map See Offset Name Type Reset Description page 0x000 UARTDR R/W 0x0000.0000 UART Data 304 0x004 UARTRSR/UARTECR R/W 0x0000.0000 UART Receive Status/Error Clear 306 0x018 UARTFR RO 0x0000.0090 UART Flag 308 0x020 UARTILPR R/W 0x0000.0000 UART IrDA Low-Power Register 310 0x024 UARTIBRD R/W 0x0000.0000 UART Integer Baud-Rate Divisor 311 302 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) See Offset Name Type Reset Description page 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 312 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 313 0x030 UARTCTL R/W 0x0000.0300 UART Control 315 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 317 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 319 0x03C UARTRIS RO 0x0000.000F UART Raw Interrupt Status 321 0x040 UARTMIS RO 0x0000.0000 UART Masked Interrupt Status 322 0x044 UARTICR W1C 0x0000.0000 UART Interrupt Clear 323 0xFD0 UARTPeriphID4 RO 0x0000.0000 UART Peripheral Identification 4 325 0xFD4 UARTPeriphID5 RO 0x0000.0000 UART Peripheral Identification 5 326 0xFD8 UARTPeriphID6 RO 0x0000.0000 UART Peripheral Identification 6 327 0xFDC UARTPeriphID7 RO 0x0000.0000 UART Peripheral Identification 7 328 0xFE0 UARTPeriphID0 RO 0x0000.0011 UART Peripheral Identification 0 329 0xFE4 UARTPeriphID1 RO 0x0000.0000 UART Peripheral Identification 1 330 0xFE8 UARTPeriphID2 RO 0x0000.0018 UART Peripheral Identification 2 331 0xFEC UARTPeriphID3 RO 0x0000.0001 UART Peripheral Identification 3 332 0xFF0 UARTPCellID0 RO 0x0000.000D UART PrimeCell Identification 0 333 0xFF4 UARTPCellID1 RO 0x0000.00F0 UART PrimeCell Identification 1 334 0xFF8 UARTPCellID2 RO 0x0000.0005 UART PrimeCell Identification 2 335 0xFFC UARTPCellID3 RO 0x0000.00B1 UART PrimeCell Identification 3 336 13.5 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. March 17, 2008 303 Preliminary LM3S8933 Microcontroller Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OE BE PE FE DATA Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:12 reserved RO 0 UART Overrun Error The OE values are defined as follows: Value Description 0 There has been no data loss due to a FIFO overrun. New data was received when the FIFO was full, resulting in data loss. 1 11 OE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 10 BE RO 0 304 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 9 PE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 8 FE RO 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. 7:0 DATA R/W 0 March 17, 2008 305 Preliminary LM3S8933 Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Read-Only Receive Status (UARTRSR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved OE BE PE FE Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:4 reserved RO 0 UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 3 OE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 2 BE RO 0 306 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 1 PE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. 0 FE RO 0 Write-Only Error Clear (UARTECR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DATA Type WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved WO 0 Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. 7:0 DATA WO 0 March 17, 2008 307 Preliminary LM3S8933 Microcontroller Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved TXFE RXFF TXFF RXFE BUSY reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 7 TXFE RO 1 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 6 RXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 5 TXFF RO 0 308 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 4 RXFE RO 1 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 3 BUSY RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2:0 reserved RO 0 March 17, 2008 309 Preliminary LM3S8933 Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR. The duration of SIR pulses generated when low-power mode is enabled is three times the period of the IrLPBaud16 clock. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ILPDVSR Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 7:0 ILPDVSR R/W 0x00 310 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIVINT Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:16 reserved RO 0 15:0 DIVINT R/W 0x0000 Integer Baud-Rate Divisor March 17, 2008 311 Preliminary LM3S8933 Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DIVFRAC Type RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:6 reserved RO 0x00 5:0 DIVFRAC R/W 0x000 Fractional Baud-Rate Divisor 312 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved SPS WLEN FEN STP2 EPS PEN BRK Type RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:8 reserved RO 0 UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 7 SPS R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 6:5 WLEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 4 FEN R/W 0 March 17, 2008 313 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. 3 STP2 R/W 0 UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 2 EPS R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 1 PEN R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 0 BRK R/W 0 314 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. Note: The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register. 1. Disable the UART. 2. Wait for the end of transmission or reception of the current character. 3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register (UARTLCRH). 4. Reprogram the control register. 5. Enable the UART. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved RXE TXE LBE reserved SIRLP SIREN UARTEN Type RO RO RO RO RO RO R/W R/W R/W RO RO RO RO R/W R/W R/W Reset 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Bit/Field Name Type Reset Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 31:10 reserved RO 0 UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. 9 RXE R/W 1 UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. 8 TXE R/W 1 March 17, 2008 315 Preliminary LM3S8933 Microcontroller Bit/Field Name Type Reset Description UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 7 LBE R/W 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6:3 reserved RO 0 UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 310 for more information. 2 SIRLP R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 1 SIREN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 UARTEN R/W 0 316 March 17, 2008 Preliminary Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (U